commit 37055c30a3c8def47535744031ddf6ffea709ece Author: yxming66 <2389287465@qq.com> Date: Fri Dec 26 15:15:18 2025 +0800 fdcan diff --git a/.clangd b/.clangd new file mode 100644 index 0000000..50c62c4 --- /dev/null +++ b/.clangd @@ -0,0 +1,11 @@ +CompileFlags: + Add: + - '-ferror-limit=0' + - '-Wno-implicit-int' + CompilationDatabase: build/Debug +Diagnostics: + Suppress: + - unused-includes + - unknown_typename + - unknown_typename_suggest + - typename_requires_specqual diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..185b49a --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +build +mx.scratch +!.settings \ No newline at end of file diff --git a/.mxproject b/.mxproject new file mode 100644 index 0000000..c1b0dce --- /dev/null +++ b/.mxproject @@ -0,0 +1,37 @@ +[PreviousLibFiles] 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H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h723xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[PreviousUsedKeilFiles] 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+HeaderPath=..\Drivers\STM32H7xx_HAL_Driver\Inc;..\Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;..\Middlewares\Third_Party\FreeRTOS\Source\include;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2;..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F;..\Drivers\CMSIS\Device\ST\STM32H7xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc; +CDefines=USE_PWR_LDO_SUPPLY;USE_PWR_LDO_SUPPLY;USE_HAL_DRIVER;STM32H723xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousUsedCMakes] +SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\freertos.c;Core\Src\fdcan.c;Core\Src\stm32h7xx_it.c;Core\Src\stm32h7xx_hal_msp.c;Core\Src\stm32h7xx_hal_timebase_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;Core\Src\system_stm32h7xx.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;Core\Src\system_stm32h7xx.c;;;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c; +HeaderPath=Drivers\STM32H7xx_HAL_Driver\Inc;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;Middlewares\Third_Party\FreeRTOS\Source\include;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F;Drivers\CMSIS\Device\ST\STM32H7xx\Include;Drivers\CMSIS\Include;Core\Inc; +CDefines=USE_PWR_LDO_SUPPLY;USE_PWR_LDO_SUPPLY;USE_HAL_DRIVER;STM32H723xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=6 +HeaderFiles#0=..\Core\Inc\gpio.h +HeaderFiles#1=..\Core\Inc\FreeRTOSConfig.h +HeaderFiles#2=..\Core\Inc\fdcan.h +HeaderFiles#3=..\Core\Inc\stm32h7xx_it.h +HeaderFiles#4=..\Core\Inc\stm32h7xx_hal_conf.h +HeaderFiles#5=..\Core\Inc\main.h +HeaderFolderListSize=1 +HeaderPath#0=..\Core\Inc +HeaderFiles=; +SourceFileListSize=7 +SourceFiles#0=..\Core\Src\gpio.c +SourceFiles#1=..\Core\Src\freertos.c +SourceFiles#2=..\Core\Src\fdcan.c +SourceFiles#3=..\Core\Src\stm32h7xx_it.c +SourceFiles#4=..\Core\Src\stm32h7xx_hal_msp.c +SourceFiles#5=..\Core\Src\stm32h7xx_hal_timebase_tim.c +SourceFiles#6=..\Core\Src\main.c +SourceFolderListSize=1 +SourcePath#0=..\Core\Src +SourceFiles=; + diff --git a/.settings/bundles-lock.store.json b/.settings/bundles-lock.store.json new file mode 100644 index 0000000..b8edaa2 --- /dev/null +++ b/.settings/bundles-lock.store.json @@ -0,0 +1,147 @@ +{ + "resolved": [ + { + "name": "cmake", + "version": "4.0.1+st.3", + "platform": "darwin", + "selected_by": [ + { + "name": "cmake", + "version": "4.0.1+st.3" + } + ] + }, + { + "name": "cmake", + "version": "4.0.1+st.3", + "platform": "x86_64-linux", + "selected_by": [ + { + "name": "cmake", + "version": "4.0.1+st.3" + } + ] + }, + { + "name": "cmake", + "version": "4.0.1+st.3", + "platform": "x86_64-windows", + "selected_by": [ + { + "name": "cmake", + "version": "4.0.1+st.3" + } + ] + }, + { + "name": "gnu-tools-for-stm32", + "version": "13.3.1+st.9", + "platform": "darwin", + "selected_by": [ + { + "name": "gnu-tools-for-stm32", + "version": "13.3.1+st.9" + } + ] + }, + { + "name": "gnu-tools-for-stm32", + "version": "13.3.1+st.9", + "platform": "x86_64-linux", + "selected_by": [ + { + "name": "gnu-tools-for-stm32", + "version": "13.3.1+st.9" + } + ] + }, + { + "name": "gnu-tools-for-stm32", + "version": "13.3.1+st.9", + "platform": "x86_64-windows", + "selected_by": [ + { + "name": "gnu-tools-for-stm32", + "version": "13.3.1+st.9" + } + ] + }, + { + "name": "gnu-tools-for-stm32-13_3_1-description", + "version": "1.0.1+st.1", + "platform": "all", + "selected_by": [ + { + "name": "gnu-tools-for-stm32-13_3_1-description", + "version": ">=0.0.1" + } + ] + }, + { + "name": "ninja", + "version": "1.13.1+st.1", + "platform": "darwin", + "selected_by": [ + { + "name": "ninja", + "version": "1.13.1+st.1" + } + ] + }, + { + "name": "ninja", + "version": "1.13.1+st.1", + "platform": "x86_64-linux", + "selected_by": [ + { + "name": "ninja", + "version": "1.13.1+st.1" + } + ] + }, + { + "name": "ninja", + "version": "1.13.1+st.1", + "platform": "x86_64-windows", + "selected_by": [ + { + "name": "ninja", + "version": "1.13.1+st.1" + } + ] + }, + { + "name": "st-arm-clangd", + "version": "19.1.2+st.3", + "platform": "darwin", + "selected_by": [ + { + "name": "st-arm-clangd", + "version": "^19.1.2+st.3" + } + ] + }, + { + "name": "st-arm-clangd", + "version": "19.1.2+st.3", + "platform": "x86_64-linux", + "selected_by": [ + { + "name": "st-arm-clangd", + "version": "^19.1.2+st.3" + } + ] + }, + { + "name": "st-arm-clangd", + "version": "19.1.2+st.3", + "platform": "x86_64-windows", + "selected_by": [ + { + "name": "st-arm-clangd", + "version": "^19.1.2+st.3" + } + ] + } + ] +} diff --git a/.settings/bundles.store.json b/.settings/bundles.store.json new file mode 100644 index 0000000..357e80c --- /dev/null +++ b/.settings/bundles.store.json @@ -0,0 +1,20 @@ +{ + "bundles": [ + { + "name": "cmake", + "version": "4.0.1+st.3" + }, + { + "name": "ninja", + "version": "1.13.1+st.1" + }, + { + "name": "gnu-tools-for-stm32", + "version": "13.3.1+st.9" + }, + { + "name": "st-arm-clangd", + "version": "^19.1.2+st.3" + } + ] +} diff --git a/.settings/ide.store.json b/.settings/ide.store.json new file mode 100644 index 0000000..5edba2c --- /dev/null +++ b/.settings/ide.store.json @@ -0,0 +1,6 @@ +{ + "device": "STM32H723VGT6", + "core": "Cortex-M7", + "order": 0, + "toolchain": "GCC" +} \ No newline at end of file diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..233ee1f --- /dev/null +++ b/.vscode/c_cpp_properties.json @@ -0,0 +1,8 @@ +{ + "configurations": [ + { + "name": "STM32", + "compileCommands": "${workspaceFolder}/build/Debug/compile_commands.json" + } + ] +} \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..77d682d --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,15 @@ +{ + "cmake.cmakePath": "cube-cmake", + "cmake.configureArgs": [ + "-DCMAKE_COMMAND=cube-cmake" + ], + "cmake.preferredGenerators": [ + "Ninja" + ], + "stm32cube-ide-clangd.path": "cube", + "stm32cube-ide-clangd.arguments": [ + "starm-clangd", + "--query-driver=${env:CUBE_BUNDLE_PATH}/gnu-tools-for-stm32/13.3.1+st.9/bin/arm-none-eabi-gcc.exe", + "--query-driver=${env:CUBE_BUNDLE_PATH}/gnu-tools-for-stm32/13.3.1+st.9/bin/arm-none-eabi-g++.exe" + ] +} \ No newline at end of file diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..2a1566b --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,86 @@ +cmake_minimum_required(VERSION 3.22) + +# +# This file is generated only once, +# and is not re-generated if converter is called multiple times. +# +# User is free to modify the file as much as necessary +# + +# Setup compiler settings +set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS ON) + + +# Define the build type +if(NOT CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE "Debug") +endif() + +# Set the project name +set(CMAKE_PROJECT_NAME hero) + +# Enable compile command to ease indexing with e.g. clangd +set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE) + +# Core project settings +project(${CMAKE_PROJECT_NAME}) +message("Build type: " ${CMAKE_BUILD_TYPE}) + +# Enable CMake support for ASM and C languages +enable_language(C ASM) + +# Create an executable object type +add_executable(${CMAKE_PROJECT_NAME}) + +# Add STM32CubeMX generated sources +add_subdirectory(cmake/stm32cubemx) + +# Link directories setup +target_link_directories(${CMAKE_PROJECT_NAME} PRIVATE + # Add user defined library search paths +) + +# Add sources to executable +target_sources(${CMAKE_PROJECT_NAME} PRIVATE + # Add user sources here + # User/bsp sources + User/bsp/fdcan.c + User/bsp/mm.c + User/bsp/time.c + + # User/component sources + User/component/filter.c + User/component/pid.c + User/component/user_math.c + User/component/crc16.c + # User/device sources + # User/module sources + ${SINGLE_CHAR_FILES} + # User/task sources + User/task/blink.c + User/task/init.c + User/task/user_task.c +) + +# Add include paths +target_include_directories(${CMAKE_PROJECT_NAME} PRIVATE + # Add user defined include paths + User +) + +# Add project symbols (macros) +target_compile_definitions(${CMAKE_PROJECT_NAME} PRIVATE + # Add user defined symbols +) + +# Remove wrong libob.a library dependency when using cpp files +list(REMOVE_ITEM CMAKE_C_IMPLICIT_LINK_LIBRARIES ob) + +# Add linked libraries +target_link_libraries(${CMAKE_PROJECT_NAME} + stm32cubemx + + # Add user defined libraries +) diff --git a/CMakePresets.json b/CMakePresets.json new file mode 100644 index 0000000..9a0c120 --- /dev/null +++ b/CMakePresets.json @@ -0,0 +1,38 @@ +{ + "version": 3, + "configurePresets": [ + { + "name": "default", + "hidden": true, + "generator": "Ninja", + "binaryDir": "${sourceDir}/build/${presetName}", + "toolchainFile": "${sourceDir}/cmake/gcc-arm-none-eabi.cmake", + "cacheVariables": { + } + }, + { + "name": "Debug", + "inherits": "default", + "cacheVariables": { + "CMAKE_BUILD_TYPE": "Debug" + } + }, + { + "name": "Release", + "inherits": "default", + "cacheVariables": { + "CMAKE_BUILD_TYPE": "Release" + } + } + ], + "buildPresets": [ + { + "name": "Debug", + "configurePreset": "Debug" + }, + { + "name": "Release", + "configurePreset": "Release" + } + ] +} \ No newline at end of file diff --git a/Core/Inc/FreeRTOSConfig.h b/Core/Inc/FreeRTOSConfig.h new file mode 100644 index 0000000..612fe10 --- /dev/null +++ b/Core/Inc/FreeRTOSConfig.h @@ -0,0 +1,170 @@ +/* USER CODE BEGIN Header */ +/* + * FreeRTOS Kernel V10.3.1 + * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ +/* USER CODE END Header */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * These parameters and more are described within the 'configuration' section of the + * FreeRTOS API documentation available on the FreeRTOS.org web site. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ +/* Section where include file can be added */ +/* USER CODE END Includes */ + +/* Ensure definitions are only used by the compiler, and not by the assembler. */ +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) + #include + extern uint32_t SystemCoreClock; +#endif +#ifndef CMSIS_device_header +#define CMSIS_device_header "stm32h7xx.h" +#endif /* CMSIS_device_header */ + +#define configENABLE_FPU 0 +#define configENABLE_MPU 0 + +#define configUSE_PREEMPTION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES ( 56 ) +#define configMINIMAL_STACK_SIZE ((uint16_t)128) +#define configTOTAL_HEAP_SIZE ((size_t)15360) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */ +/* Defaults to size_t for backward compatibility, but can be changed + if lengths will always be less than the number of bytes in a size_t. */ +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH 256 + +/* CMSIS-RTOS V2 flags */ +#define configUSE_OS2_THREAD_SUSPEND_RESUME 1 +#define configUSE_OS2_THREAD_ENUMERATE 1 +#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1 +#define configUSE_OS2_THREAD_FLAGS 1 +#define configUSE_OS2_TIMER 1 +#define configUSE_OS2_MUTEX 1 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_eTaskGetState 1 + +/* + * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used + * by the application thus the correct define need to be enabled below + */ +#define USE_FreeRTOS_HEAP_4 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 4 +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +/* USER CODE BEGIN 1 */ +#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} +/* USER CODE END 1 */ + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler + +/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */ + +#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0 + +/* USER CODE BEGIN Defines */ +/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ +/* USER CODE END Defines */ + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Core/Inc/fdcan.h b/Core/Inc/fdcan.h new file mode 100644 index 0000000..86218a5 --- /dev/null +++ b/Core/Inc/fdcan.h @@ -0,0 +1,58 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file fdcan.h + * @brief This file contains all the function prototypes for + * the fdcan.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FDCAN_H__ +#define __FDCAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern FDCAN_HandleTypeDef hfdcan1; + +extern FDCAN_HandleTypeDef hfdcan2; + +extern FDCAN_HandleTypeDef hfdcan3; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_FDCAN1_Init(void); +void MX_FDCAN2_Init(void); +void MX_FDCAN3_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FDCAN_H__ */ + diff --git a/Core/Inc/gpio.h b/Core/Inc/gpio.h new file mode 100644 index 0000000..9ac4857 --- /dev/null +++ b/Core/Inc/gpio.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + diff --git a/Core/Inc/main.h b/Core/Inc/main.h new file mode 100644 index 0000000..55da3a1 --- /dev/null +++ b/Core/Inc/main.h @@ -0,0 +1,75 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define Power_OUT2_EN_Pin GPIO_PIN_13 +#define Power_OUT2_EN_GPIO_Port GPIOC +#define Power_OUT1_EN_Pin GPIO_PIN_14 +#define Power_OUT1_EN_GPIO_Port GPIOC +#define Power_5V_EN_Pin GPIO_PIN_15 +#define Power_5V_EN_GPIO_Port GPIOC + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Core/Inc/stm32h7xx_hal_conf.h b/Core/Inc/stm32h7xx_hal_conf.h new file mode 100644 index 0000000..bb843e3 --- /dev/null +++ b/Core/Inc/stm32h7xx_hal_conf.h @@ -0,0 +1,514 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_CONF_H +#define STM32H7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_ADC_MODULE_ENABLED */ +#define HAL_FDCAN_MODULE_ENABLED +/* #define HAL_FMAC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_OTFDEC_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HRTIM_MODULE_ENABLED */ +/* #define HAL_HSEM_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_RAMECC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SWPMI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (24000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal oscillator (CSI) default value. + * This value is the default CSI value after Reset. + */ +#if !defined (CSI_VALUE) + #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ +#define USE_SPI_CRC 0U /*!< use CRC in SPI */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################### Ethernet Configuration ######################### */ +#define ETH_TX_DESC_CNT 4U /* number of Ethernet Tx DMA descriptors */ +#define ETH_RX_DESC_CNT 4U /* number of Ethernet Rx DMA descriptors */ + +#define ETH_MAC_ADDR0 (0x02UL) +#define ETH_MAC_ADDR1 (0x00UL) +#define ETH_MAC_ADDR2 (0x00UL) +#define ETH_MAC_ADDR3 (0x00UL) +#define ETH_MAC_ADDR4 (0x00UL) +#define ETH_MAC_ADDR5 (0x00UL) + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_MDMA_MODULE_ENABLED + #include "stm32h7xx_hal_mdma.h" +#endif /* HAL_MDMA_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32h7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32h7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32h7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32h7xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32h7xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32h7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED + #include "stm32h7xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED + #include "stm32h7xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED + #include "stm32h7xx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32h7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32h7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32h7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32h7xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32h7xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED +#include "stm32h7xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32h7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7xx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32h7xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_CONF_H */ diff --git a/Core/Inc/stm32h7xx_it.h b/Core/Inc/stm32h7xx_it.h new file mode 100644 index 0000000..024f655 --- /dev/null +++ b/Core/Inc/stm32h7xx_it.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_IT_H +#define __STM32H7xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +void FDCAN1_IT0_IRQHandler(void); +void FDCAN2_IT1_IRQHandler(void); +void TIM2_IRQHandler(void); +void FDCAN3_IT1_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_IT_H */ diff --git a/Core/Src/fdcan.c b/Core/Src/fdcan.c new file mode 100644 index 0000000..6e7f0b6 --- /dev/null +++ b/Core/Src/fdcan.c @@ -0,0 +1,350 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file fdcan.c + * @brief This file provides code for the configuration + * of the FDCAN instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "fdcan.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +FDCAN_HandleTypeDef hfdcan1; +FDCAN_HandleTypeDef hfdcan2; +FDCAN_HandleTypeDef hfdcan3; + +/* FDCAN1 init function */ +void MX_FDCAN1_Init(void) +{ + + /* USER CODE BEGIN FDCAN1_Init 0 */ + + /* USER CODE END FDCAN1_Init 0 */ + + /* USER CODE BEGIN FDCAN1_Init 1 */ + + /* USER CODE END FDCAN1_Init 1 */ + hfdcan1.Instance = FDCAN1; + hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan1.Init.Mode = FDCAN_MODE_NORMAL; + hfdcan1.Init.AutoRetransmission = ENABLE; + hfdcan1.Init.TransmitPause = DISABLE; + hfdcan1.Init.ProtocolException = ENABLE; + hfdcan1.Init.NominalPrescaler = 5; + hfdcan1.Init.NominalSyncJumpWidth = 5; + hfdcan1.Init.NominalTimeSeg1 = 14; + hfdcan1.Init.NominalTimeSeg2 = 5; + hfdcan1.Init.DataPrescaler = 5; + hfdcan1.Init.DataSyncJumpWidth = 5; + hfdcan1.Init.DataTimeSeg1 = 14; + hfdcan1.Init.DataTimeSeg2 = 5; + hfdcan1.Init.MessageRAMOffset = 0; + hfdcan1.Init.StdFiltersNbr = 1; + hfdcan1.Init.ExtFiltersNbr = 1; + hfdcan1.Init.RxFifo0ElmtsNbr = 8; + hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64; + hfdcan1.Init.RxFifo1ElmtsNbr = 0; + hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8; + hfdcan1.Init.RxBuffersNbr = 0; + hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8; + hfdcan1.Init.TxEventsNbr = 0; + hfdcan1.Init.TxBuffersNbr = 0; + hfdcan1.Init.TxFifoQueueElmtsNbr = 8; + hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_64; + if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN1_Init 2 */ + + /* USER CODE END FDCAN1_Init 2 */ + +} +/* FDCAN2 init function */ +void MX_FDCAN2_Init(void) +{ + + /* USER CODE BEGIN FDCAN2_Init 0 */ + + /* USER CODE END FDCAN2_Init 0 */ + + /* USER CODE BEGIN FDCAN2_Init 1 */ + + /* USER CODE END FDCAN2_Init 1 */ + hfdcan2.Instance = FDCAN2; + hfdcan2.Init.FrameFormat = FDCAN_FRAME_FD_BRS; + hfdcan2.Init.Mode = FDCAN_MODE_NORMAL; + hfdcan2.Init.AutoRetransmission = ENABLE; + hfdcan2.Init.TransmitPause = DISABLE; + hfdcan2.Init.ProtocolException = ENABLE; + hfdcan2.Init.NominalPrescaler = 5; + hfdcan2.Init.NominalSyncJumpWidth = 5; + hfdcan2.Init.NominalTimeSeg1 = 14; + hfdcan2.Init.NominalTimeSeg2 = 5; + hfdcan2.Init.DataPrescaler = 1; + hfdcan2.Init.DataSyncJumpWidth = 5; + hfdcan2.Init.DataTimeSeg1 = 14; + hfdcan2.Init.DataTimeSeg2 = 5; + hfdcan2.Init.MessageRAMOffset = 831; + hfdcan2.Init.StdFiltersNbr = 1; + hfdcan2.Init.ExtFiltersNbr = 1; + hfdcan2.Init.RxFifo0ElmtsNbr = 0; + hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; + hfdcan2.Init.RxFifo1ElmtsNbr = 8; + hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64; + hfdcan2.Init.RxBuffersNbr = 0; + hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8; + hfdcan2.Init.TxEventsNbr = 0; + hfdcan2.Init.TxBuffersNbr = 0; + hfdcan2.Init.TxFifoQueueElmtsNbr = 8; + hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8; + if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN2_Init 2 */ + + /* USER CODE END FDCAN2_Init 2 */ + +} +/* FDCAN3 init function */ +void MX_FDCAN3_Init(void) +{ + + /* USER CODE BEGIN FDCAN3_Init 0 */ + + /* USER CODE END FDCAN3_Init 0 */ + + /* USER CODE BEGIN FDCAN3_Init 1 */ + + /* USER CODE END FDCAN3_Init 1 */ + hfdcan3.Instance = FDCAN3; + hfdcan3.Init.FrameFormat = FDCAN_FRAME_FD_NO_BRS; + hfdcan3.Init.Mode = FDCAN_MODE_NORMAL; + hfdcan3.Init.AutoRetransmission = ENABLE; + hfdcan3.Init.TransmitPause = DISABLE; + hfdcan3.Init.ProtocolException = ENABLE; + hfdcan3.Init.NominalPrescaler = 5; + hfdcan3.Init.NominalSyncJumpWidth = 5; + hfdcan3.Init.NominalTimeSeg1 = 14; + hfdcan3.Init.NominalTimeSeg2 = 5; + hfdcan3.Init.DataPrescaler = 5; + hfdcan3.Init.DataSyncJumpWidth = 5; + hfdcan3.Init.DataTimeSeg1 = 14; + hfdcan3.Init.DataTimeSeg2 = 5; + hfdcan3.Init.MessageRAMOffset = 1662; + hfdcan3.Init.StdFiltersNbr = 1; + hfdcan3.Init.ExtFiltersNbr = 0; + hfdcan3.Init.RxFifo0ElmtsNbr = 0; + hfdcan3.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; + hfdcan3.Init.RxFifo1ElmtsNbr = 8; + hfdcan3.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64; + hfdcan3.Init.RxBuffersNbr = 0; + hfdcan3.Init.RxBufferSize = FDCAN_DATA_BYTES_8; + hfdcan3.Init.TxEventsNbr = 0; + hfdcan3.Init.TxBuffersNbr = 0; + hfdcan3.Init.TxFifoQueueElmtsNbr = 8; + hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + hfdcan3.Init.TxElmtSize = FDCAN_DATA_BYTES_8; + if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN3_Init 2 */ + + /* USER CODE END FDCAN3_Init 2 */ + +} + +static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0; + +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(fdcanHandle->Instance==FDCAN1) + { + /* USER CODE BEGIN FDCAN1_MspInit 0 */ + + /* USER CODE END FDCAN1_MspInit 0 */ + /* FDCAN1 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if(HAL_RCC_FDCAN_CLK_ENABLED==1){ + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**FDCAN1 GPIO Configuration + PD0 ------> FDCAN1_RX + PD1 ------> FDCAN1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* FDCAN1 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); + /* USER CODE BEGIN FDCAN1_MspInit 1 */ + + /* USER CODE END FDCAN1_MspInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN2) + { + /* USER CODE BEGIN FDCAN2_MspInit 0 */ + + /* USER CODE END FDCAN2_MspInit 0 */ + /* FDCAN2 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if(HAL_RCC_FDCAN_CLK_ENABLED==1){ + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**FDCAN2 GPIO Configuration + PB5 ------> FDCAN2_RX + PB6 ------> FDCAN2_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* FDCAN2 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn); + /* USER CODE BEGIN FDCAN2_MspInit 1 */ + + /* USER CODE END FDCAN2_MspInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN3) + { + /* USER CODE BEGIN FDCAN3_MspInit 0 */ + + /* USER CODE END FDCAN3_MspInit 0 */ + /* FDCAN3 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if(HAL_RCC_FDCAN_CLK_ENABLED==1){ + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**FDCAN3 GPIO Configuration + PD12 ------> FDCAN3_RX + PD13 ------> FDCAN3_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_FDCAN3; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* FDCAN3 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN3_IT1_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(FDCAN3_IT1_IRQn); + /* USER CODE BEGIN FDCAN3_MspInit 1 */ + + /* USER CODE END FDCAN3_MspInit 1 */ + } +} + +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* fdcanHandle) +{ + + if(fdcanHandle->Instance==FDCAN1) + { + /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ + + /* USER CODE END FDCAN1_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if(HAL_RCC_FDCAN_CLK_ENABLED==0){ + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN1 GPIO Configuration + PD0 ------> FDCAN1_RX + PD1 ------> FDCAN1_TX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1); + + /* FDCAN1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn); + /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ + + /* USER CODE END FDCAN1_MspDeInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN2) + { + /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ + + /* USER CODE END FDCAN2_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if(HAL_RCC_FDCAN_CLK_ENABLED==0){ + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN2 GPIO Configuration + PB5 ------> FDCAN2_RX + PB6 ------> FDCAN2_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5|GPIO_PIN_6); + + /* FDCAN2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN2_IT1_IRQn); + /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ + + /* USER CODE END FDCAN2_MspDeInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN3) + { + /* USER CODE BEGIN FDCAN3_MspDeInit 0 */ + + /* USER CODE END FDCAN3_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if(HAL_RCC_FDCAN_CLK_ENABLED==0){ + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN3 GPIO Configuration + PD12 ------> FDCAN3_RX + PD13 ------> FDCAN3_TX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_12|GPIO_PIN_13); + + /* FDCAN3 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN3_IT1_IRQn); + /* USER CODE BEGIN FDCAN3_MspDeInit 1 */ + + /* USER CODE END FDCAN3_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/freertos.c b/Core/Src/freertos.c new file mode 100644 index 0000000..8a81b40 --- /dev/null +++ b/Core/Src/freertos.c @@ -0,0 +1,129 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : freertos.c + * Description : Code for freertos applications + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "FreeRTOS.h" +#include "task.h" +#include "main.h" +#include "cmsis_os.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN Variables */ + +/* USER CODE END Variables */ +/* Definitions for defaultTask */ +osThreadId_t defaultTaskHandle; +const osThreadAttr_t defaultTask_attributes = { + .name = "defaultTask", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityNormal, +}; + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN FunctionPrototypes */ + +/* USER CODE END FunctionPrototypes */ + +void StartDefaultTask(void *argument); + +void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ + +/** + * @brief FreeRTOS initialization + * @param None + * @retval None + */ +void MX_FREERTOS_Init(void) { + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* USER CODE BEGIN RTOS_MUTEX */ + /* add mutexes, ... */ + /* USER CODE END RTOS_MUTEX */ + + /* USER CODE BEGIN RTOS_SEMAPHORES */ + /* add semaphores, ... */ + /* USER CODE END RTOS_SEMAPHORES */ + + /* USER CODE BEGIN RTOS_TIMERS */ + /* start timers, add new ones, ... */ + /* USER CODE END RTOS_TIMERS */ + + /* USER CODE BEGIN RTOS_QUEUES */ + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ + + /* Create the thread(s) */ + /* creation of defaultTask */ + defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); + + /* USER CODE BEGIN RTOS_THREADS */ + /* add threads, ... */ + /* USER CODE END RTOS_THREADS */ + + /* USER CODE BEGIN RTOS_EVENTS */ + /* add events, ... */ + /* USER CODE END RTOS_EVENTS */ + +} + +/* USER CODE BEGIN Header_StartDefaultTask */ +/** + * @brief Function implementing the defaultTask thread. + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartDefaultTask */ +void StartDefaultTask(void *argument) +{ + /* USER CODE BEGIN StartDefaultTask */ + /* Infinite loop */ + for(;;) + { + osDelay(1); + } + /* USER CODE END StartDefaultTask */ +} + +/* Private application code --------------------------------------------------*/ +/* USER CODE BEGIN Application */ + +/* USER CODE END Application */ + diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c new file mode 100644 index 0000000..e55444f --- /dev/null +++ b/Core/Src/gpio.c @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, Power_OUT2_EN_Pin|Power_OUT1_EN_Pin|Power_5V_EN_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : Power_OUT2_EN_Pin Power_OUT1_EN_Pin Power_5V_EN_Pin */ + GPIO_InitStruct.Pin = Power_OUT2_EN_Pin|Power_OUT1_EN_Pin|Power_5V_EN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/Core/Src/main.c b/Core/Src/main.c new file mode 100644 index 0000000..ec2a480 --- /dev/null +++ b/Core/Src/main.c @@ -0,0 +1,295 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "cmsis_os.h" +#include "fdcan.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +void PeriphCommonClock_Config(void); +static void MPU_Config(void); +void MX_FREERTOS_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MPU Configuration--------------------------------------------------------*/ + MPU_Config(); + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* Configure the peripherals common clocks */ + PeriphCommonClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_FDCAN1_Init(); + MX_FDCAN2_Init(); + MX_FDCAN3_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Init scheduler */ + osKernelInitialize(); /* Call init function for freertos objects (in cmsis_os2.c) */ + MX_FREERTOS_Init(); + + /* Start scheduler */ + osKernelStart(); + + /* We should never get here as control is now taken by the scheduler */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 40; + RCC_OscInitStruct.PLL.PLLP = 1; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief Peripherals Common Clock Configuration + * @retval None + */ +void PeriphCommonClock_Config(void) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; + PeriphClkInitStruct.PLL2.PLL2M = 24; + PeriphClkInitStruct.PLL2.PLL2N = 200; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 2; + PeriphClkInitStruct.PLL2.PLL2R = 2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_0; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + + /* MPU Configuration */ + +void MPU_Config(void) +{ + MPU_Region_InitTypeDef MPU_InitStruct = {0}; + + /* Disables the MPU */ + HAL_MPU_Disable(); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER0; + MPU_InitStruct.BaseAddress = 0x0; + MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; + MPU_InitStruct.SubRegionDisable = 0x87; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + /* Enables the MPU */ + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + +} + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM2 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM2) + { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/Core/Src/stm32h7xx_hal_msp.c b/Core/Src/stm32h7xx_hal_msp.c new file mode 100644 index 0000000..68add39 --- /dev/null +++ b/Core/Src/stm32h7xx_hal_msp.c @@ -0,0 +1,83 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/stm32h7xx_hal_timebase_tim.c b/Core/Src/stm32h7xx_hal_timebase_tim.c new file mode 100644 index 0000000..4c75d4b --- /dev/null +++ b/Core/Src/stm32h7xx_hal_timebase_tim.c @@ -0,0 +1,130 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_hal_timebase_tim.c + * @brief HAL time base based on the hardware TIM. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" +#include "stm32h7xx_hal_tim.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_HandleTypeDef htim2; +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM2 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock, uwAPB1Prescaler; + uint32_t uwPrescalerValue; + uint32_t pFLatency; + + /*Configure the TIM2 IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0); + + /* Enable the TIM2 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM2_IRQn); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Enable TIM2 clock */ + __HAL_RCC_TIM2_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Get APB1 prescaler */ + uwAPB1Prescaler = clkconfig.APB1CLKDivider; + /* Compute TIM2 clock */ + if (uwAPB1Prescaler == RCC_HCLK_DIV1) + { + uwTimclock = HAL_RCC_GetPCLK1Freq(); + } + else + { + uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); + } + + /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + + /* Initialize TIM2 */ + htim2.Instance = TIM2; + + /* Initialize TIMx peripheral as follow: + * Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base. + * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + * ClockDivision = 0 + * Counter direction = Up + */ + htim2.Init.Period = (1000000U / 1000U) - 1U; + htim2.Init.Prescaler = uwPrescalerValue; + htim2.Init.ClockDivision = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + + if(HAL_TIM_Base_Init(&htim2) == HAL_OK) + { + /* Start the TIM time Base generation in interrupt mode */ + return HAL_TIM_Base_Start_IT(&htim2); + } + + /* Return function status */ + return HAL_ERROR; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM2 update interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM2 update Interrupt */ + __HAL_TIM_DISABLE_IT(&htim2, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling TIM2 update interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM2 Update interrupt */ + __HAL_TIM_ENABLE_IT(&htim2, TIM_IT_UPDATE); +} + diff --git a/Core/Src/stm32h7xx_it.c b/Core/Src/stm32h7xx_it.c new file mode 100644 index 0000000..89fd0d2 --- /dev/null +++ b/Core/Src/stm32h7xx_it.c @@ -0,0 +1,223 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern FDCAN_HandleTypeDef hfdcan1; +extern FDCAN_HandleTypeDef hfdcan2; +extern FDCAN_HandleTypeDef hfdcan3; +extern TIM_HandleTypeDef htim2; + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32H7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32h7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles FDCAN1 interrupt 0. + */ +void FDCAN1_IT0_IRQHandler(void) +{ + /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ + + /* USER CODE END FDCAN1_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan1); + /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */ + + /* USER CODE END FDCAN1_IT0_IRQn 1 */ +} + +/** + * @brief This function handles FDCAN2 interrupt 1. + */ +void FDCAN2_IT1_IRQHandler(void) +{ + /* USER CODE BEGIN FDCAN2_IT1_IRQn 0 */ + + /* USER CODE END FDCAN2_IT1_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan2); + /* USER CODE BEGIN FDCAN2_IT1_IRQn 1 */ + + /* USER CODE END FDCAN2_IT1_IRQn 1 */ +} + +/** + * @brief This function handles TIM2 global interrupt. + */ +void TIM2_IRQHandler(void) +{ + /* USER CODE BEGIN TIM2_IRQn 0 */ + + /* USER CODE END TIM2_IRQn 0 */ + HAL_TIM_IRQHandler(&htim2); + /* USER CODE BEGIN TIM2_IRQn 1 */ + + /* USER CODE END TIM2_IRQn 1 */ +} + +/** + * @brief This function handles FDCAN3 interrupt 1. + */ +void FDCAN3_IT1_IRQHandler(void) +{ + /* USER CODE BEGIN FDCAN3_IT1_IRQn 0 */ + + /* USER CODE END FDCAN3_IT1_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan3); + /* USER CODE BEGIN FDCAN3_IT1_IRQn 1 */ + + /* USER CODE END FDCAN3_IT1_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/syscalls.c b/Core/Src/syscalls.c new file mode 100644 index 0000000..e10d76f --- /dev/null +++ b/Core/Src/syscalls.c @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeMX + * @brief Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +clock_t _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(const char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} + +// --- Picolibc Specific Section --- +#if defined(__PICOLIBC__) + +/** + * @brief Picolibc helper function to output a character to a FILE stream. + * This redirects the output to the low-level __io_putchar function. + * @param c Character to write. + * @param file FILE stream pointer (ignored). + * @retval int The character written. + */ +static int starm_putc(char c, FILE *file) +{ + (void) file; + __io_putchar(c); + return c; +} + +/** + * @brief Picolibc helper function to input a character from a FILE stream. + * This redirects the input from the low-level __io_getchar function. + * @param file FILE stream pointer (ignored). + * @retval int The character read, cast to an unsigned char then int. + */ +static int starm_getc(FILE *file) +{ + unsigned char c; + (void) file; + c = __io_getchar(); + return c; +} + +// Define and initialize the standard I/O streams for Picolibc. +// FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure. +// _FDEV_SETUP_RW indicates the stream is for reading and writing. +static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, + starm_getc, + NULL, + _FDEV_SETUP_RW); + +// Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream. +// Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.). +FILE *const stdin = &__stdio; +__strong_reference(stdin, stdout); +__strong_reference(stdin, stderr); + +// Create strong aliases mapping standard C library function names (without underscore) +// to the implemented system call stubs (with underscore). Picolibc uses these +// standard names internally, so this linking is required. +__strong_reference(_read, read); +__strong_reference(_write, write); +__strong_reference(_times, times); +__strong_reference(_execve, execve); +__strong_reference(_fork, fork); +__strong_reference(_link, link); +__strong_reference(_unlink, unlink); +__strong_reference(_stat, stat); +__strong_reference(_wait, wait); +__strong_reference(_open, open); +__strong_reference(_close, close); +__strong_reference(_lseek, lseek); +__strong_reference(_isatty, isatty); +__strong_reference(_fstat, fstat); +__strong_reference(_exit, exit); +__strong_reference(_kill, kill); +__strong_reference(_getpid, getpid); + +#endif //__PICOLIBC__ diff --git a/Core/Src/sysmem.c b/Core/Src/sysmem.c new file mode 100644 index 0000000..a875d42 --- /dev/null +++ b/Core/Src/sysmem.c @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeMX + * @brief System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} + +#if defined(__PICOLIBC__) + // Picolibc expects syscalls without the leading underscore. + // This creates a strong alias so that + // calls to `sbrk()` are resolved to our `_sbrk()` implementation. + __strong_reference(_sbrk, sbrk); +#endif diff --git a/Core/Src/system_stm32h7xx.c b/Core/Src/system_stm32h7xx.c new file mode 100644 index 0000000..197d15c --- /dev/null +++ b/Core/Src/system_stm32h7xx.c @@ -0,0 +1,556 @@ +/** + ****************************************************************************** + * @file system_stm32h7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock, it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + +#include "stm32h7xx.h" +#include + +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */ +/* #define DATA_IN_D2_SRAM */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +#if defined(DUAL_CORE) && defined(CORE_CM4) +/*!< Uncomment the following line if you need to relocate your vector Table + in D2 AXI SRAM else user remap will be done in FLASH BANK2. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif /* VECT_TAB_SRAM */ +#else +/*!< Uncomment the following line if you need to relocate your vector Table + in D1 AXI SRAM else user remap will be done in FLASH BANK1. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif /* VECT_TAB_SRAM */ +#endif /* DUAL_CORE && CORE_CM4 */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000; + uint32_t SystemD2Clock = 64000000; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting and vector table location + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ +#if defined (DATA_IN_D2_SRAM) + __IO uint32_t tmpreg; +#endif /* DATA_IN_D2_SRAM */ + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + + /* Increasing the CPU frequency */ + if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + +#if defined(D3_SRAM_BASE) + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; +#else + /* Reset CDCFGR1 register */ + RCC->CDCFGR1 = 0x00000000; + + /* Reset CDCFGR2 register */ + RCC->CDCFGR2 = 0x00000000; + + /* Reset SRDCFGR register */ + RCC->SRDCFGR = 0x00000000; +#endif + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x02020200; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x01FF0000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + +#if (STM32H7_DEV_ID == 0x450UL) + /* dual core CM7 or single core line */ + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x000000001U; + } +#endif /* STM32H7_DEV_ID */ + +#if defined(DATA_IN_D2_SRAM) + /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); +#elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); +#else + RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); +#endif /* RCC_AHB2ENR_D2SRAM3EN */ + + tmpreg = RCC->AHB2ENR; + (void) tmpreg; +#endif /* DATA_IN_D2_SRAM */ + +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#else + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#endif /*DUAL_CORE && CORE_CM4*/ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; + float_t fracn1, pllvco; + + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + common_system_clock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + common_system_clock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + common_system_clock = 0U; + } + break; + + default: + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + } + + /* Compute SystemClock frequency --------------------------------------------------*/ +#if defined (RCC_D1CFGR_D1CPRE) + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +#else + tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ +} + +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_armcc.h b/Drivers/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000..59f173a --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_armclang.h b/Drivers/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000..e917f35 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h b/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..feec324 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_compiler.h b/Drivers/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Core/Include/cmsis_gcc.h b/Drivers/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000..3ddcc58 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_iccarm.h b/Drivers/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000..12d68fd --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_version.h b/Drivers/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000..f2e2746 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Core/Include/core_armv81mml.h b/Drivers/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 0000000..8441e57 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_armv8mbl.h b/Drivers/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000..344dca5 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_armv8mml.h b/Drivers/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000..5ddb8ae --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm0.h b/Drivers/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 0000000..cafae5a --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm0plus.h b/Drivers/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 0000000..d104965 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm1.h b/Drivers/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm23.h b/Drivers/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 0000000..b79c6af --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm3.h b/Drivers/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 0000000..8157ca7 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm33.h b/Drivers/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000..7fed59a --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm35p.h b/Drivers/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 0000000..5579c82 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm4.h b/Drivers/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000..12c023b --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm7.h b/Drivers/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 0000000..c4515d8 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_sc000.h b/Drivers/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000..cf92577 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_sc300.h b/Drivers/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000..40f3af8 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/mpu_armv7.h b/Drivers/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000..66ef59b --- /dev/null +++ b/Drivers/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Core/Include/mpu_armv8.h b/Drivers/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000..0041d4d --- /dev/null +++ b/Drivers/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Core/Include/tz_context.h b/Drivers/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c b/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c new file mode 100644 index 0000000..273607b --- /dev/null +++ b/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c @@ -0,0 +1,58 @@ +/****************************************************************************** + * @file main_s.c + * @brief Code template for secure main function + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Use CMSE intrinsics */ +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c b/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c new file mode 100644 index 0000000..e2e8294 --- /dev/null +++ b/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h b/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h new file mode 100644 index 0000000..ec17393 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h @@ -0,0 +1,547 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.3 + * @date 15. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1)) + #define __ARM_ARCH_7A__ 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __forceinline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __wfi + +/** + \brief Wait For Event + */ +#define __WFE __wfe + +/** + \brief Send Event + */ +#define __SEV __sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + +/** + \brief Rotate Right in unsigned value (32 bit) + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + +/* ########################### Core Function Access ########################### */ + +/** + \brief Get FPSCR (Floating Point Status/Control) + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + +/** + \brief Set FPSCR (Floating Point Status/Control) + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +/** \brief Get CPSR (Current Program Status Register) + \return CPSR Register value + */ +__STATIC_INLINE uint32_t __get_CPSR(void) +{ + register uint32_t __regCPSR __ASM("cpsr"); + return(__regCPSR); +} + + +/** \brief Set CPSR (Current Program Status Register) + \param [in] cpsr CPSR value to set + */ +__STATIC_INLINE void __set_CPSR(uint32_t cpsr) +{ + register uint32_t __regCPSR __ASM("cpsr"); + __regCPSR = cpsr; +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_INLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_INLINE __ASM void __set_mode(uint32_t mode) +{ + MOV r1, lr + MSR CPSR_C, r0 + BX r1 +} + +/** \brief Get Stack Pointer + \return Stack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP(void) +{ + MOV r0, sp + BX lr +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP(uint32_t stack) +{ + MOV sp, r0 + BX lr +} + + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYSStack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP_usr(void) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV R0, SP + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV SP, R0 + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Get FPEXC (Floating Point Exception Control Register) + \return Floating Point Exception Control Register value + */ +__STATIC_INLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + return(__regfpexc); +#else + return(0); +#endif +} + +/** \brief Set FPEXC (Floating Point Exception Control Register) + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + __regfpexc = (fpexc); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) +#define __get_CP64(cp, op1, Rt, CRm) \ + do { \ + uint32_t ltmp, htmp; \ + __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \ + } while(0) + +#define __set_CP64(cp, op1, Rt, CRm) \ + do { \ + const uint64_t tmp = (Rt); \ + const uint32_t ltmp = (uint32_t)(tmp); \ + const uint32_t htmp = (uint32_t)(tmp >> 32U); \ + __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + } while(0) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE __ASM void __FPU_Enable(void) +{ + ARM + + //Permit access to VFP/NEON, registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + ISB + + //Enable VFP/NEON + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP/NEON registers to 0 + MOV R2,#0 + + //Initialise D16 registers to 0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + //Initialise D32 registers to 0 + VMOV D16,R2,R2 + VMOV D17,R2,R2 + VMOV D18,R2,R2 + VMOV D19,R2,R2 + VMOV D20,R2,R2 + VMOV D21,R2,R2 + VMOV D22,R2,R2 + VMOV D23,R2,R2 + VMOV D24,R2,R2 + VMOV D25,R2,R2 + VMOV D26,R2,R2 + VMOV D27,R2,R2 + VMOV D28,R2,R2 + VMOV D29,R2,R2 + VMOV D30,R2,R2 + VMOV D31,R2,R2 + ENDIF + + //Initialise FPSCR to a known state + VMRS R1,FPSCR + LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R1,R1,R2 + VMSR FPSCR,R1 + + BX LR +} + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h b/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h new file mode 100644 index 0000000..0a53c4e --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h @@ -0,0 +1,585 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.1.1 + * @date 15. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __builtin_arm_wfi + +/** + \brief Wait For Event + */ +#define __WFE __builtin_arm_wfe + +/** + \brief Send Event + */ +#define __SEV __builtin_arm_sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() do {\ + __schedule_barrier();\ + __builtin_arm_isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() do {\ + __schedule_barrier();\ + __builtin_arm_dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + */ +#define __DMB() do {\ + __schedule_barrier();\ + __builtin_arm_dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __QADD8 __builtin_arm_qadd8 +#define __QSUB8 __builtin_arm_qsub8 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __SXTB16 __builtin_arm_sxtb16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSDX __builtin_arm_smlsdx + + + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ + +/* ########################### Core Function Access ########################### */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP() +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr() +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if __ARM_NEON == 1 + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h b/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h new file mode 100644 index 0000000..dfd07a2 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h @@ -0,0 +1,213 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef CMSIS_DEPRECATED + #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. + #define CMSIS_DEPRECATED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h b/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h new file mode 100644 index 0000000..891bec2 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h @@ -0,0 +1,514 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set ACTRL + \param [in] actrl Auxiliary Control Register value to set + */ +__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) +{ + __set_CP(15, 0, actrl, 1, 0, 1); +} + +/** \brief Get ACTRL + \return Auxiliary Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTRL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); +} + +#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ + defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ +// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CCSIDR + \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. + */ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +{ + __set_CSSELR(value); +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 14, 2); +} + +#endif diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h b/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h new file mode 100644 index 0000000..0c407c2 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h @@ -0,0 +1,814 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.2.0 + * @date 17. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ + +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + + + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + */ +#define __WFI() __ASM volatile ("wfi") + +/** + \brief Wait For Event + */ +#define __WFE() __ASM volatile ("wfe") + +/** + \brief Send Event + */ +#define __SEV() __ASM volatile ("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value)); + return result; +} +#endif + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value +*/ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_get_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); + #else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); + #endif + #else + return(0U); + #endif +} + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set +*/ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_set_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); + #else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + #endif + #else + (void)fpscr; + #endif +} + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h b/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h new file mode 100644 index 0000000..7d44107 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h @@ -0,0 +1,571 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 15. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// Copyright (c) 2018-2019 Arm Limited +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#pragma language=extended + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_7A__ +/* Macro already defined */ +#else + #if defined(__ARM7A__) + #define __ARM_ARCH_7A__ 1 + #endif +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif + +#ifndef __UNALIGNED_UINT16_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) + { + return *(__packed uint16_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) + { + *(__packed uint16_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) + { + return *(__packed uint32_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) + { + *(__packed uint32_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#if 0 +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma language=save + #pragma language=extended + __packed struct __iar_u32 { uint32_t v; }; + #pragma language=restore + #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __enable_irq __iar_builtin_enable_interrupt + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + #if __FPU_PRESENT + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #else + #define __get_FPSCR() ( 0 ) + #endif + + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE)) + + #define __get_CPSR() (__arm_rsr("CPSR")) + #define __get_mode() (__get_CPSR() & 0x1FU) + + #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) + #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) + + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) + + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #define __SSAT __iar_builtin_SSAT + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #define __USAT __iar_builtin_USAT + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if !__FPU_PRESENT + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if !__FPU_PRESENT + #define __get_FPSCR() (0) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + __IAR_FT void __set_mode(uint32_t mode) + { + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); + } + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + __IAR_FT uint32_t __get_FPEXC(void) + { + #if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); + #else + return(0); + #endif + } + + __IAR_FT void __set_FPEXC(uint32_t fpexc) + { + #if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); + #endif + } + + + #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) + #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + + +__IAR_FT uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +#define __get_mode() (__get_CPSR() & 0x1FU) + +__STATIC_INLINE +void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#ifdef __ARM_ADVANCED_SIMD__ + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 \n" + : : : "cc", "r1", "r2" + ); +} + + + +#undef __IAR_FT +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Core_A/Include/core_ca.h b/Drivers/CMSIS/Core_A/Include/core_ca.h new file mode 100644 index 0000000..0bef549 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/core_ca.h @@ -0,0 +1,2613 @@ +/**************************************************************************//** + * @file core_ca.h + * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA_H_GENERIC +#define __CORE_CA_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +/* CMSIS CA definitions */ +#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA_H_DEPENDANT +#define __CORE_CA_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA_REV + #define __CA_REV 0x0000U + #warning "__CA_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< \brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< \brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< \brief Defines 'write only' permissions */ +#define __IO volatile /*!< \brief Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ +#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ +#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + RESERVED(1:1, uint32_t) + uint32_t B:1; /*!< \brief bit: 7 Endianness model */ + RESERVED(2:2, uint32_t) + uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ + RESERVED(3:2, uint32_t) + uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ + RESERVED(4:1, uint32_t) + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< \brief bit: 22 Alignment model */ + RESERVED(5:1, uint32_t) + uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(6:1, uint32_t) + uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(7:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) + uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ + +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + +#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ + +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + RESERVED(1:1, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ + +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + +#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ + +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + +/* CP15 Register ISR */ +typedef union +{ + struct + { + RESERVED(0:6, uint32_t) + uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ + RESERVED(1:23, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ + +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + + +/** + \brief Union type to access the L2C_310 Cache Controller. +*/ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +typedef struct +{ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ +} L2C_310_TypeDef; + +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ +#endif + +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ +#endif + +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Structure type to access the Private Timer +*/ +typedef struct +{ + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register +} Timer_Type; +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ +#endif +#endif + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { + __set_DCCMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { + __set_DCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { + __set_DCCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + uint32_t Dummy; + uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + int32_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CSSELR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if ((log2_num_ways < 0) || (log2_num_ways > 32)) { + return; // FATAL ERROR + } + shift_way = 32U - (uint32_t)log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +* \deprecated Use generic L1C_CleanInvalidateCache instead. +*/ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { + L1C_CleanInvalidateCache(op); +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(0); +} + +/** \brief Clean the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { + L1C_CleanInvalidateCache(1); +} + +/** \brief Clean and invalidate the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(2); +} + +/* ########################## L2 Cache functions ################################# */ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ +__STATIC_INLINE void L2C_Sync(void) +{ + L2C_310->CACHE_SYNC = 0x0; +} + +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ +__STATIC_INLINE int L2C_GetID (void) +{ + return L2C_310->CACHE_ID; +} + +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ +__STATIC_INLINE int L2C_GetType (void) +{ + return L2C_310->CACHE_TYPE; +} + +/** \brief Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_InvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Clean and Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + L2C_310->CONTROL = 0; + L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; + L2C_310->DEBUG_CONTROL = 0; + L2C_310->DATA_LOCK_0_WAY = 0; + L2C_310->CACHE_SYNC = 0; + L2C_310->CONTROL = 0x01; + L2C_Sync(); +} + +/** \brief Disable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Disable(void) +{ + L2C_310->CONTROL = 0x00; + L2C_Sync(); +} + +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_InvPa (void *pa) +{ + L2C_310->INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanPa (void *pa) +{ + L2C_310->CLEAN_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanInvPa (void *pa) +{ + L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} +#endif + +/* ########################## GIC functions ###################################### */ +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_EnableDistributor(void) +{ + GICDistributor->CTLR |= 1U; +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ +__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + for (i = 32U; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + //Set target list to CPU0 + GIC_SetTarget((IRQn_Type)i, 1U); + } + //Enable distributor + GIC_EnableDistributor(); +} + +/** \brief Initialize the CPU's interrupt interface +*/ +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if(i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) + +/* PL1 Physical Timer */ +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ + __set_CNTP_TVAL(value); + __ISB(); +} + +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) +{ + return(__get_CNTP_TVAL()); +} + +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ + __set_CNTP_CTL(value); + __ISB(); +} + +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl(void) +{ + return(__get_CNTP_CTL()); +} +#endif + +/* Private Timer */ +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ + PTIM->LOAD = value; +} + +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ + return(PTIM->LOAD); +} + +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ + return(PTIM->COUNTER); +} + +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ + PTIM->CONTROL = value; +} + +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ + return(PTIM->CONTROL); +} + +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ + PTIM->ISR = 1; +} +#endif +#endif + +/* ########################## MMU functions ###################################### */ + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +//Following macros define the descriptors and attributes +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +/** \brief Set section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 +*/ +__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 +*/ +__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + +/** \brief Set Section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 +*/ +__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] page Page size + + \return 0 +*/ +__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + MMU_MemorySection(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + \param [out] descriptor L1 descriptor + \param [in] reg Section attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + MMU_XNSection(descriptor,reg.xn_t); + MMU_DomainSection(descriptor, reg.domain); + MMU_PSection(descriptor, reg.e_t); + MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1); + MMU_SharedSection(descriptor,reg.sh_t); + MMU_GlobalSection(descriptor,reg.g_t); + MMU_SecureSection(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + } + + return 0; +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + { + //4 bytes aligned + *ttb_l2++ = entry2; + } + entry2 += OFFSET_64K; + } +} + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + __set_TLBIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core_A/Include/irq_ctrl.h b/Drivers/CMSIS/Core_A/Include/irq_ctrl.h new file mode 100644 index 0000000..b171ef0 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/irq_ctrl.h @@ -0,0 +1,186 @@ +/**************************************************************************//** + * @file irq_ctrl.h + * @brief Interrupt Controller API header file + * @version V1.0.0 + * @date 23. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef IRQ_CTRL_H_ +#define IRQ_CTRL_H_ + +#include + +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +/// Interrupt handler data type +typedef void (*IRQHandler_t) (void); +#endif + +#ifndef IRQN_ID_T +#define IRQN_ID_T +/// Interrupt ID number data type +typedef int32_t IRQn_ID_t; +#endif + +/* Interrupt mode bit-masks */ +#define IRQ_MODE_TRIG_Pos (0U) +#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) +#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt +#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt + +#define IRQ_MODE_TYPE_Pos (3U) +#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) +#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line +#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line + +#define IRQ_MODE_DOMAIN_Pos (4U) +#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) +#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain +#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain + +#define IRQ_MODE_CPU_Pos (5U) +#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) +#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs +#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 +#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 +#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 +#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 +#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 +#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 +#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 +#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 + +#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error + +/* Interrupt priority bit-masks */ +#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask +#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error + +/// Initialize interrupt controller. +/// \return 0 on success, -1 on error. +int32_t IRQ_Initialize (void); + +/// Register interrupt handler. +/// \param[in] irqn interrupt ID number +/// \param[in] handler interrupt handler function address +/// \return 0 on success, -1 on error. +int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); + +/// Get the registered interrupt handler. +/// \param[in] irqn interrupt ID number +/// \return registered interrupt handler function address. +IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); + +/// Enable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Enable (IRQn_ID_t irqn); + +/// Disable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Disable (IRQn_ID_t irqn); + +/// Get interrupt enable state. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. +uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); + +/// Configure interrupt request mode. +/// \param[in] irqn interrupt ID number +/// \param[in] mode mode configuration +/// \return 0 on success, -1 on error. +int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); + +/// Get interrupt mode configuration. +/// \param[in] irqn interrupt ID number +/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. +uint32_t IRQ_GetMode (IRQn_ID_t irqn); + +/// Get ID number of current interrupt request (IRQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveIRQ (void); + +/// Get ID number of current fast interrupt request (FIQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveFIQ (void); + +/// Signal end of interrupt processing. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); + +/// Set interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPending (IRQn_ID_t irqn); + +/// Get interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is not pending, 1 - interrupt is pending. +uint32_t IRQ_GetPending (IRQn_ID_t irqn); + +/// Clear interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_ClearPending (IRQn_ID_t irqn); + +/// Set interrupt priority value. +/// \param[in] irqn interrupt ID number +/// \param[in] priority interrupt priority value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); + +/// Get interrupt priority. +/// \param[in] irqn interrupt ID number +/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriority (IRQn_ID_t irqn); + +/// Set priority masking threshold. +/// \param[in] priority priority masking threshold value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityMask (uint32_t priority); + +/// Get priority masking threshold +/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityMask (void); + +/// Set priority grouping field split point +/// \param[in] bits number of MSB bits included in the group priority field comparison +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityGroupBits (uint32_t bits); + +/// Get priority grouping field split point +/// \return current number of MSB bits included in the group priority field comparison with +/// optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityGroupBits (void); + +#endif // IRQ_CTRL_H_ diff --git a/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c b/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c new file mode 100644 index 0000000..25d1359 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c @@ -0,0 +1,410 @@ +/**************************************************************************//** + * @file irq_ctrl_gic.c + * @brief Interrupt controller handling implementation for GIC + * @version V1.0.1 + * @date 9. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "irq_ctrl.h" + +#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U) + +/// Number of implemented interrupt lines +#ifndef IRQ_GIC_LINE_COUNT +#define IRQ_GIC_LINE_COUNT (1020U) +#endif + +static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U }; +static uint32_t IRQ_ID0; + +/// Initialize interrupt controller. +__WEAK int32_t IRQ_Initialize (void) { + uint32_t i; + + for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) { + IRQTable[i] = (IRQHandler_t)NULL; + } + GIC_Enable(); + return (0); +} + + +/// Register interrupt handler. +__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + IRQTable[irqn] = handler; + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get the registered interrupt handler. +__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) { + IRQHandler_t h; + + // Ignore CPUID field (software generated interrupts) + irqn &= 0x3FFU; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + h = IRQTable[irqn]; + } else { + h = (IRQHandler_t)0; + } + + return (h); +} + + +/// Enable interrupt. +__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EnableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Disable interrupt. +__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_DisableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt enable state. +__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) { + uint32_t enable; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + enable = GIC_GetEnableIRQ((IRQn_Type)irqn); + } else { + enable = 0U; + } + + return (enable); +} + + +/// Configure interrupt request mode. +__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) { + uint32_t val; + uint8_t cfg; + uint8_t secure; + uint8_t cpu; + int32_t status = 0; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + // Check triggering mode + val = (mode & IRQ_MODE_TRIG_Msk); + + if (val == IRQ_MODE_TRIG_LEVEL) { + cfg = 0x00U; + } else if (val == IRQ_MODE_TRIG_EDGE) { + cfg = 0x02U; + } else { + cfg = 0x00U; + status = -1; + } + + // Check interrupt type + val = mode & IRQ_MODE_TYPE_Msk; + + if (val != IRQ_MODE_TYPE_IRQ) { + status = -1; + } + + // Check interrupt domain + val = mode & IRQ_MODE_DOMAIN_Msk; + + if (val == IRQ_MODE_DOMAIN_NONSECURE) { + secure = 0U; + } else { + // Check security extensions support + val = GIC_DistributorInfo() & (1UL << 10U); + + if (val != 0U) { + // Security extensions are supported + secure = 1U; + } else { + secure = 0U; + status = -1; + } + } + + // Check interrupt CPU targets + val = mode & IRQ_MODE_CPU_Msk; + + if (val == IRQ_MODE_CPU_ALL) { + cpu = 0xFFU; + } else { + cpu = val >> IRQ_MODE_CPU_Pos; + } + + // Apply configuration if no mode error + if (status == 0) { + GIC_SetConfiguration((IRQn_Type)irqn, cfg); + GIC_SetTarget ((IRQn_Type)irqn, cpu); + + if (secure != 0U) { + GIC_SetGroup ((IRQn_Type)irqn, secure); + } + } + } + + return (status); +} + + +/// Get interrupt mode configuration. +__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) { + uint32_t mode; + uint32_t val; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + mode = IRQ_MODE_TYPE_IRQ; + + // Get trigger mode + val = GIC_GetConfiguration((IRQn_Type)irqn); + + if ((val & 2U) != 0U) { + // Corresponding interrupt is edge triggered + mode |= IRQ_MODE_TRIG_EDGE; + } else { + // Corresponding interrupt is level triggered + mode |= IRQ_MODE_TRIG_LEVEL; + } + + // Get interrupt CPU targets + mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos; + + } else { + mode = IRQ_MODE_ERROR; + } + + return (mode); +} + + +/// Get ID number of current interrupt request (IRQ). +__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) { + IRQn_ID_t irqn; + uint32_t prio; + + /* Dummy read to avoid GIC 390 errata 801120 */ + GIC_GetHighPendingIRQ(); + + irqn = GIC_AcknowledgePending(); + + __DSB(); + + /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */ + /* The following workaround code is for a single-core system. It would be */ + /* different in a multi-core system. */ + /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */ + /* so unlock it, otherwise service the interrupt as normal. */ + /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */ + /* so will not occur here. */ + + if ((irqn == 0) || (irqn >= 0x3FE)) { + /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */ + prio = GIC_GetPriority((IRQn_Type)0); + GIC_SetPriority ((IRQn_Type)0, prio); + + __DSB(); + + if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) { + /* If the ID is 0, is active and has not been seen before */ + IRQ_ID0 = 1U; + } + /* End of Workaround GIC 390 errata 733075 */ + } + + return (irqn); +} + + +/// Get ID number of current fast interrupt request (FIQ). +__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) { + return ((IRQn_ID_t)-1); +} + + +/// Signal end of interrupt processing. +__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) { + int32_t status; + IRQn_Type irq = (IRQn_Type)irqn; + + irqn &= 0x3FFU; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EndInterrupt (irq); + + if (irqn == 0) { + IRQ_ID0 = 0U; + } + + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt pending flag. +__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + +/// Get interrupt pending flag. +__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) { + uint32_t pending; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + pending = GIC_GetPendingIRQ ((IRQn_Type)irqn); + } else { + pending = 0U; + } + + return (pending & 1U); +} + + +/// Clear interrupt pending flag. +__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_ClearPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt priority value. +__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPriority ((IRQn_Type)irqn, priority); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt priority. +__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) { + uint32_t priority; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + priority = GIC_GetPriority ((IRQn_Type)irqn); + } else { + priority = IRQ_PRIORITY_ERROR; + } + + return (priority); +} + + +/// Set priority masking threshold. +__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) { + GIC_SetInterfacePriorityMask (priority); + return (0); +} + + +/// Get priority masking threshold +__WEAK uint32_t IRQ_GetPriorityMask (void) { + return GIC_GetInterfacePriorityMask(); +} + + +/// Set priority grouping field split point +__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) { + int32_t status; + + if (bits == IRQ_PRIORITY_Msk) { + bits = 7U; + } + + if (bits < 8U) { + GIC_SetBinaryPoint (7U - bits); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get priority grouping field split point +__WEAK uint32_t IRQ_GetPriorityGroupBits (void) { + uint32_t bp; + + bp = GIC_GetBinaryPoint() & 0x07U; + + return (7U - bp); +} + +#endif diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/CMakeLists.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/CMakeLists.txt new file mode 100644 index 0000000..3d8e4e9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/CMakeLists.txt @@ -0,0 +1,136 @@ +cmake_minimum_required (VERSION 3.6) +cmake_policy(SET CMP0077 NEW) +# The tests are assuming that MATRIX_CHECK is enabled when building +# CMSIS-DSP. +set(MATRIXCHECK ON) +set(FASTMATHCOMPUTATIONS OFF) +option(DUMPPATTERN "Dump test patterns when test is failing" ON) + +option(CUSTOMIZE_TESTS "Enable customizations of tests" ON) +option(BASICMATH_TESTS "Enable Basic Math testing" ON) +option(COMPLEXMATH_TESTS "Enable Complex Math testing" ON) +option(CONTROLLER_TESTS "Enable Controller testing" ON) +option(FASTMATH_TESTS "Enable Fast Math testing" ON) +option(INTRINSICS_TESTS "Enable Intrinsics testing" ON) +option(FILTERING_TESTS "Enable Filtering testing" ON) +option(MATRIX_TESTS "Enable Matrix testing" ON) +option(STATISTICS_TESTS "Enable Statistics testing" ON) +option(SUPPORT_TESTS "Enable Support testing" ON) +option(TRANSFORM_TESTS "Enable Transform testing" ON) + + +project(DSP_Lib_TestSuite) + +# Needed to find the config modules +list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/..) + + +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../..) + + +file(GLOB MAIN "Common/src/*.c") +file(GLOB BASICMATH_TESTS_SRC "Common/src/basic_math_tests/*.c") +file(GLOB COMPLEXMATH_TESTS_SRC "Common/src/complex_math_tests/*.c") +file(GLOB CONTROLLER_TESTS_SRC "Common/src/controller_tests/*.c") +file(GLOB FASTMATH_TESTS_SRC "Common/src/fast_math_tests/*.c") +file(GLOB FILTERING_TESTS_SRC "Common/src/filtering_tests/*.c") +file(GLOB INTRINSINCS_TESTS_SRC "Common/src/intrinsics_tests/*.c") +file(GLOB MATRIX_TESTS_SRC "Common/src/matrix_tests/*.c") +file(GLOB STATISTICS_TESTS_SRC "Common/src/statistics_tests/*.c") +file(GLOB SUPPORT_TESTS_SRC "Common/src/support_tests/*.c") +file(GLOB TRANSFORM_TESTS_SRC "Common/src/transform_tests/*.c") +file(GLOB JTEST_MAIN "Common/JTest/src/*.c") + +set(TESTSRC ${MAIN} + ${BASICMATH_TESTS_SRC} + ${COMPLEXMATH_TESTS_SRC} + ${CONTROLLER_TESTS_SRC} + ${FASTMATH_TESTS_SRC} + ${FILTERING_TESTS_SRC} + ${INTRINSINCS_TESTS_SRC} + ${MATRIX_TESTS_SRC} + ${STATISTICS_TESTS_SRC} + ${SUPPORT_TESTS_SRC} + ${TRANSFORM_TESTS_SRC} + ${JTEST_MAIN} + ) + +set(JINCS + Common/JTest/inc + Common/JTest/inc/arr_desc + Common/inc/basic_math_tests + Common/inc/complex_math_tests + Common/inc/controller_tests + Common/inc/fast_math_tests + Common/inc/filtering_tests + Common/inc/intrinsics_tests + Common/inc/matrix_tests + Common/inc/statistics_tests + Common/inc/support_tests + Common/inc/transform_tests + ) + +add_subdirectory(../Source bin_dsp) +add_subdirectory(RefLibs bin_ref) + + +add_executable(DSP_Lib_TestSuite) + +if (CUSTOMIZE_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE CUSTOMIZE_TESTS) +endif() + +if (BASICMATH_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_BASICMATH_TESTS) +endif() +if (COMPLEXMATH_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_COMPLEXMATH_TESTS) +endif() +if (CONTROLLER_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_CONTROLLER_TESTS) +endif() +if (FASTMATH_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_FASTMATH_TESTS) +endif() +if (FILTERING_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_FILTERING_TESTS) +endif() +if (INTRINSICS_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_INTRINSICS_TESTS) +endif() +if (MATRIX_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_MATRIX_TESTS) +endif() +if (STATISTICS_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_STATISTICS_TESTS) +endif() +if (SUPPORT_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_SUPPORT_TESTS) +endif() +if (TRANSFORM_TESTS) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_TRANSFORM_TESTS) +endif() + + +if (DUMPPATTERN) + target_compile_definitions(DSP_Lib_TestSuite PRIVATE DUMPPATTERN) +endif() + +# Change behavior of configBoot for scatter file +set(TESTFRAMEWORK ON) + +include(configBoot) + +file(COPY ${ROOT}/CMSIS/DSP/Examples/ARM/boot/RTE_Components.h DESTINATION tempLink) + +target_link_libraries(DSP_Lib_TestSuite PRIVATE CMSISDSP) +target_link_libraries(DSP_Lib_TestSuite PRIVATE DspRefLibs) + +target_sources(DSP_Lib_TestSuite PRIVATE ${TESTSRC}) + +### Includes +target_include_directories(DSP_Lib_TestSuite PRIVATE "Common/inc") +target_include_directories(DSP_Lib_TestSuite PRIVATE "Common/inc/templates") +target_include_directories(DSP_Lib_TestSuite PRIVATE ${JINCS}) + + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h new file mode 100644 index 0000000..7995489 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h @@ -0,0 +1,220 @@ +#ifndef _ARR_DESC_H_ +#define _ARR_DESC_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ +#include +#include /* memset() */ +#include "../util/util.h" /* CONCAT() */ + +/*--------------------------------------------------------------------------------*/ +/* Type Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * Array-descriptor struct. + */ +typedef struct ARR_DESC_struct +{ + void * data_ptr; /* Pointer to the array contents. */ + int32_t element_count; /* Number of current elements. */ + int32_t element_size; /* Size of current elements in bytes. */ + int32_t underlying_size; /* Size of underlying array in bytes. */ +} ARR_DESC_t; + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Prefix of the array variable's name when creating an array and an array + * descriptor at the same time. + */ +#define ARR_DESC_ARR_PREFIX ARR_DESC_ARR_ + +/** + * Evaluate to the array variable's name when creating an array and an array + * descriptor at the same time. + */ +#define ARR_DESC_ARR_NAME(name) \ + CONCAT(ARR_DESC_ARR_PREFIX, name) + +/** + * Define an #ARR_DESC_t by itself. + * + * @note The user must supply an array to store the data used by the + * #ARR_DESC_t. + */ +#define ARR_DESC_INTERNAL_DEFINE(name, data_ptr, \ + element_count, element_size) \ + ARR_DESC_t name = { \ + data_ptr, \ + element_count, \ + element_size, \ + element_count * element_size \ + } \ + +/** + * Define both an array and an #ARR_DESC_t that describes it. + * + * @note Use the #CURLY() macro for the content field; it provides the curly + * braces necessary for an array initialization. + */ +#define ARR_DESC_DEFINE(type, name, element_count, content) \ + type ARR_DESC_ARR_NAME(name)[element_count] = content; \ + ARR_DESC_INTERNAL_DEFINE(name, \ + &ARR_DESC_ARR_NAME(name), \ + element_count, \ + sizeof(type)) /* Note the lacking semicolon */ + +/** + * Create a #ARR_DESC_t which refers to a subset of the data in another. + * + * The new #ARR_DESC_t shares the same underlying array as the aliased + * #ARR_DESC_t, but only describes a subset of the originals values. + */ +#define ARR_DESC_DEFINE_SUBSET(name, original, element_cnt) \ + ARR_DESC_INTERNAL_DEFINE(name, \ + &ARR_DESC_ARR_NAME(original), \ + element_cnt, \ + sizeof(ARR_DESC_ARR_NAME(original)[0]) \ + ) /* Note the lacking semicolon */ + +/** + * Creat an #ARR_DESC_t which points to the data in an existing array. + * + * @param start_idx Offset in array_ptr of first element. + * @param element_cnt Number of elements to include in the #ARR_DESC_t. + * + * @example + * + * float my_floats[4] = {0.0f, 1.0f, 2.0f, 3.0f}; + * + * ARR_DESC_DEFINE_USING_ARR(my_arr_desc, my_floats, 1, 3); + * + * printf("Element 0: %f\n", ARR_DESC_ELT(float, 0, &my_arr_desc)); + * printf("Element 1: %f\n", ARR_DESC_ELT(float, 1, &my_arr_desc)); + * + * Outputs: + * + * Element 0: 1.000000 + * Element 1: 2.000000 + * + * @warning There are no checks in place to catch invalid start indices; This + * is left to the user. + */ +#define ARR_DESC_DEFINE_USING_ARR(type, name, array_ptr, start_idx, element_cnt) \ + ARR_DESC_INTERNAL_DEFINE( \ + name, \ + (type *) (array_ptr + start_idx), \ + element_cnt, \ + sizeof(type) \ + ) /* Note the lacking semicolon*/ + +/** + * Declare an #ARR_DESC_t object. + */ +#define ARR_DESC_DECLARE(name) \ + extern ARR_DESC_t name /* Note the lacking semicolon */ + +/** + * Evaluate to the number of bytes stored in the #ARR_DESC_t. + */ +#define ARR_DESC_BYTES(arr_desc_ptr) \ + ((arr_desc_ptr)->element_count * (arr_desc_ptr)->element_size) + +/** + * Set the contents of #ARR_DESC_t to value. + */ +#define ARR_DESC_MEMSET(arr_desc_ptr, value, bytes) \ + do \ + { \ + memset((arr_desc_ptr)->data_ptr, \ + value, \ + BOUND(0, \ + (arr_desc_ptr)->underlying_size, \ + bytes) \ + ); \ + } while (0) + +/** + * Perform a memcpy of 'bytes' bytes from the source #ARR_DESC_t to the + * destination #ARR_DESC_t. + */ +#define ARR_DESC_MEMCPY(arr_desc_dest_ptr, arr_desc_src_ptr, bytes) \ + do \ + { \ + memcpy((arr_desc_dest_ptr)->data_ptr, \ + (arr_desc_src_ptr)->data_ptr, \ + BOUND(0, \ + (arr_desc_dest_ptr)->underlying_size, \ + bytes)); \ + } while (0) + +/** + * Evaluate to true if the source #ARR_DESC_t contents will fit into the + * destination #ARR_DESC_t and false otherwise. + */ +#define ARR_DESC_COPYABLE(arr_desc_dest_ptr, arr_desc_src_ptr) \ + (ARR_DESC_BYTES(arr_desc_src_ptr) <= \ + (arr_desc_dest_ptr)->underlying_size) + +/** + * Copy all the data from the source #ARR_DESC_t to the destination + * #ARR_DESC_t. + * + * @note If the destination #ARR_DESC_t is too small to fit the source data the + * copy is aborted and nothing happens. + */ +#define ARR_DESC_COPY(arr_desc_dest_ptr, arr_desc_src_ptr) \ + do \ + { \ + if (ARR_DESC_COPYABLE(arr_desc_dest_ptr, \ + arr_desc_src_ptr)) \ + { \ + ARR_DESC_MEMCPY(arr_desc_dest_ptr, \ + arr_desc_src_ptr, \ + ARR_DESC_BYTES(arr_desc_src_ptr)); \ + /* Update the properties*/ \ + (arr_desc_dest_ptr)->element_count = \ + (arr_desc_src_ptr)->element_count; \ + (arr_desc_dest_ptr)->element_size = \ + (arr_desc_src_ptr)->element_size; \ + } \ + } while (0) + +/** + * Compare the data in two #ARR_DESC_t structs for the specified number of + * bytes. + */ +#define ARR_DESC_MEMCMP(arr_desc_ptr_a, arr_desc_ptr_b, bytes) \ + memcmp((arr_desc_ptr_a)->data_ptr, \ + (arr_desc_ptr_b)->data_ptr, \ + bytes) /* Note the lacking semicolon */ \ + +/** + * Zero out the contents of the #ARR_DESC_t. + */ +#define ARR_DESC_ZERO(arr_desc_ptr) \ + ARR_DESC_MEMSET(arr_desc_ptr, \ + 0, \ + (arr_desc_ptr)->underlying_size) + +/** + * Evaluate to the data address in #ARR_DESC_t at offset. + */ +#define ARR_DESC_DATA_ADDR(type, arr_desc_ptr, offset) \ + ((void*)(((type *) \ + ((arr_desc_ptr)->data_ptr)) \ + + offset)) + +/** + * Evaluate to the element in #ARR_DESC_t with type at idx. + */ +#define ARR_DESC_ELT(type, idx, arr_desc_ptr) \ + (*((type *) ARR_DESC_DATA_ADDR(type, \ + arr_desc_ptr, \ + idx))) + +#endif /* _ARR_DESC_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h new file mode 100644 index 0000000..ad48adc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h @@ -0,0 +1,17 @@ +#ifndef _JTEST_H_ +#define _JTEST_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_fw.h" +#include "jtest_test.h" +#include "jtest_test_define.h" +#include "jtest_test_call.h" +#include "jtest_group.h" +#include "jtest_group_define.h" +#include "jtest_group_call.h" +#include "jtest_cycle.h" + +#endif /* _JTEST_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h new file mode 100644 index 0000000..ed09f95 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h @@ -0,0 +1,79 @@ +#ifndef _JTEST_CYCLE_H_ +#define _JTEST_CYCLE_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_fw.h" /* JTEST_DUMP_STRF() */ +#include "jtest_systick.h" +#include "jtest_util.h" /* STR() */ + +/*--------------------------------------------------------------------------------*/ +/* Declare Module Variables */ +/*--------------------------------------------------------------------------------*/ +extern const char * JTEST_CYCLE_STRF; + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Wrap the function call, fn_call, to count execution cycles and display the + * results. + */ +/* skipp function name + param +#define JTEST_COUNT_CYCLES(fn_call) \ + do \ + { \ + uint32_t __jtest_cycle_end_count; \ + \ + JTEST_SYSTICK_RESET(SysTick); \ + JTEST_SYSTICK_START(SysTick); \ + \ + fn_call; \ + \ + __jtest_cycle_end_count = \ + JTEST_SYSTICK_VALUE(SysTick); \ + \ + JTEST_SYSTICK_RESET(SysTick); \ + JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \ + STR(fn_call), \ + (JTEST_SYSTICK_INITIAL_VALUE - \ + __jtest_cycle_end_count)); \ + } while (0) +*/ +#ifndef ARMv7A + +#define JTEST_COUNT_CYCLES(fn_call) \ + do \ + { \ + uint32_t __jtest_cycle_end_count; \ + \ + JTEST_SYSTICK_RESET(SysTick); \ + JTEST_SYSTICK_START(SysTick); \ + \ + fn_call; \ + \ + __jtest_cycle_end_count = \ + JTEST_SYSTICK_VALUE(SysTick); \ + \ + JTEST_SYSTICK_RESET(SysTick); \ + JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \ + (JTEST_SYSTICK_INITIAL_VALUE - \ + __jtest_cycle_end_count)); \ + } while (0) + +#else +/* TODO */ +#define JTEST_COUNT_CYCLES(fn_call) \ + do \ + { \ + fn_call; \ + } while (0) + +#endif + +#endif /* _JTEST_CYCLE_H_ */ + + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h new file mode 100644 index 0000000..13ad0fb --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h @@ -0,0 +1,37 @@ +#ifndef _JTEST_DEFINE_H_ +#define _JTEST_DEFINE_H_ + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Makes a symbol for use as a struct name. Names made this way have two parts; + * the first parts is a prefix common to all structs of that class. The second + * is a specifier which differs for each instance of that struct type. + */ +#define JTEST_STRUCT_NAME(prefix, specifier) \ + CONCAT(prefix, specifier) + +/** + * Define a struct with type with a name generated by #JTEST_STRUCT_NAME(). + */ +#define JTEST_DEFINE_STRUCT(type, struct_name) \ + type struct_name + +/** + * Declare a struct with type with a name generated by #JTEST_STRUCT_NAME(). + */ +#define JTEST_DECLARE_STRUCT(struct_definition) \ + extern struct_definition + +/** + * Define and initialize a struct (created with JTEST_DEFINE_STRUCT()) and + * initialize it with init_values. + */ +#define JTEST_INIT_STRUCT(struct_definition, init_values) \ + struct_definition = { \ + init_values \ + } + +#endif /* _JTEST_DEFINE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h new file mode 100644 index 0000000..e48c0c5 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h @@ -0,0 +1,282 @@ +#ifndef _JTEST_FW_H_ +#define _JTEST_FW_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include /* int32_t */ +#include /* strcpy() */ +#include /* sprintf() */ +#include "jtest_pf.h" /* Extend JTEST_FW_t with Pass/Fail data */ +#include "jtest_group.h" + +/*--------------------------------------------------------------------------------*/ +/* Type Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * A struct used to interface with the Keil Debugger. + */ +typedef struct JTEST_FW_struct +{ + /* Action Triggers: The Keil debugger monitors these values for changes. In + * response to a change, the debugger executes code on the host. */ + volatile int32_t test_start; + volatile int32_t test_end; + volatile int32_t group_start; + volatile int32_t group_end; + volatile int32_t dump_str; + volatile int32_t dump_data; + volatile int32_t exit_fw; + + JTEST_GROUP_t * current_group_ptr; + + /* Buffers: The C-code cannot send strings and data directly to the + * debugging framework. Instead, the debugger can be told to read 128 byte + * (by default) chunks of memory. Data received in this manner requires + * post-processing to be legible.*/ + char * str_buffer; + char * data_buffer; + + /* Pass/Fail Data */ + JTEST_PF_MEMBERS; + +} JTEST_FW_t; + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Default name for the JTEST_FW struct. + * + * Define your own if you want the variable containing the #JTEST_FW_t to have + * a different name. + */ +#ifndef JTEST_FW +#define JTEST_FW JTEST_FW +#endif + +/** + * Default name for the JTEST_FW_STR_BUFFER. + * + * Define your own if you want the variable containing the char buffer to have + * a different name. + */ +#ifndef JTEST_FW_STR_BUFFER +#define JTEST_FW_STR_BUFFER JTEST_FW_STR_BUFFER +#endif + +/** + * Size of the #JTEST_FW_t, output string-buffer. + * + * If you change this value, make sure the "dump_str_fn" and "dump_data_fn" + * functions in jtest_fns.ini uses the same size. If you aren't sure, read the + * documentation Keil Debugger Command 'DISPLAY'. + */ +#define JTEST_BUF_SIZE 256 + + +/** + * The maximum number of bytes output at once using #JTEST_DUMP_STRF(). + */ +#define JTEST_STR_MAX_OUTPUT_SIZE 128 + +/** + * The maximum number of block transimissions needed to send a string from a + * buffer with JTEST_BUF_SIZE. + */ +#define JTEST_STR_MAX_OUTPUT_SEGMENTS \ + (JTEST_BUF_SIZE / JTEST_STR_MAX_OUTPUT_SIZE) + +/** + * Initialize the JTEST framework. + */ +#define JTEST_INIT() \ + do \ + { \ + JTEST_FW.str_buffer = JTEST_FW_STR_BUFFER; \ + } while (0) + +/* Debugger Action-triggering Macros */ +/*--------------------------------------------------------------------------------*/ + +/** + * Dispatch macro to trigger various actions in the Keil Debugger. + */ +#define JTEST_TRIGGER_ACTION(action_name) \ + do \ + { \ + action_name(); \ + } while (0) + +/** + * Trigger the "Test Start" action in the Keil Debugger. + */ +#define JTEST_ACT_TEST_START() \ + JTEST_TRIGGER_ACTION(test_start) + +/** + * Trigger the "Test End" action in the Keil Debugger. + */ +#define JTEST_ACT_TEST_END() \ + JTEST_TRIGGER_ACTION(test_end) + + +/** + * Trigger the "Group Start" action in the Keil Debugger. + */ +#define JTEST_ACT_GROUP_START() \ + JTEST_TRIGGER_ACTION(group_start) + +/** + * Trigger the "Group End" action in the Keil Debugger. + */ +#define JTEST_ACT_GROUP_END() \ + JTEST_TRIGGER_ACTION(group_end) + + +/** + * Fill the buffer named buf_name with value and dump it to the Keil debugger + * using action. + */ +#if defined(ARMv7A) || defined(FILEIO) + +#define JTEST_ACT_DUMP(action, buf_name, value) \ + do \ + { \ + JTEST_CLEAR_BUFFER(buf_name); \ + printf("%s",value); \ + strcpy(JTEST_FW.buf_name, (value)); \ + JTEST_TRIGGER_ACTION(action); \ + } while (0) + +#else + +#define JTEST_ACT_DUMP(action, buf_name, value) \ + do \ + { \ + JTEST_CLEAR_BUFFER(buf_name); \ + strcpy(JTEST_FW.buf_name, (value)); \ + JTEST_TRIGGER_ACTION(action); \ + } while (0) + +#endif +/** + * Trigger the "Exit Framework" action in the Keil Debugger. + */ +#define JTEST_ACT_EXIT_FW() \ + do \ + { \ + JTEST_TRIGGER_ACTION(exit_fw); \ + } while (0) + + +/* Buffer Manipulation Macros */ +/*--------------------------------------------------------------------------------*/ + +/** + * Clear the JTEST_FW buffer with name buf_name. + */ +#define JTEST_CLEAR_BUFFER(buf_name) \ + do \ + { \ + memset(JTEST_FW.buf_name, 0, JTEST_BUF_SIZE); \ + } while (0) + +/** + * Clear the memory needed for the JTEST_FW's string buffer. + */ +#define JTEST_CLEAR_STR_BUFFER() \ + JTEST_CLEAR_BUFFER(str_buffer) + +/** + * Clear the memory needed for the JTEST_FW's data buffer. + */ +#define JTEST_CLEAR_DATA_BUFFER() \ + JTEST_CLEAR_BUFFER(data_buffer) + +/** + * Dump the given string to the Keil Debugger. + */ +#define JTEST_DUMP_STR(string) \ + JTEST_ACT_DUMP(dump_str, str_buffer, string) + +/** + * Dump a formatted string to the Keil Debugger. + */ +#if defined(ARMv7A) || defined(FILEIO) + +#define JTEST_DUMP_STRF(format_str, ... ) \ + do \ + { \ + JTEST_CLEAR_STR_BUFFER(); \ + sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__); \ + printf("%s",JTEST_FW.str_buffer); \ + jtest_dump_str_segments(); \ + } while (0) + +#else + +#define JTEST_DUMP_STRF(format_str, ... ) \ + do \ + { \ + JTEST_CLEAR_STR_BUFFER(); \ + sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__); \ + jtest_dump_str_segments(); \ + } while (0) + +#endif + +/* Pass/Fail Macros */ +/*--------------------------------------------------------------------------------*/ + +/** + * Increment the number of passed tests in #JTEST_FW. + */ +#define JTEST_FW_INC_PASSED(amount) \ + JTEST_PF_INC_PASSED(&JTEST_FW, amount) + +/** + * Increment the number of passed tests in #JTEST_FW. + */ +#define JTEST_FW_INC_FAILED(amount) \ + JTEST_PF_INC_FAILED(&JTEST_FW, amount) + +/* Manipulating the Current Group */ +/*--------------------------------------------------------------------------------*/ + +/** + * Evaluate to the current_group_ptr in #JTEST_FW. + */ +#define JTEST_CURRENT_GROUP_PTR() \ + (JTEST_FW.current_group_ptr) + +#define JTEST_SET_CURRENT_GROUP(group_ptr) \ + do \ + { \ + JTEST_CURRENT_GROUP_PTR() = group_ptr; \ + } while (0) + +/*--------------------------------------------------------------------------------*/ +/* Declare Global Variables */ +/*--------------------------------------------------------------------------------*/ +extern char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE]; +extern volatile JTEST_FW_t JTEST_FW; + +/*--------------------------------------------------------------------------------*/ +/* Function Prototypes */ +/*--------------------------------------------------------------------------------*/ +void jtest_dump_str_segments(void); + +void test_start (void); +void test_end (void); +void group_start (void); +void group_end (void); +void dump_str (void); +void dump_data (void); +void exit_fw (void); + + +#endif /* _JTEST_FW_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h new file mode 100644 index 0000000..de47920 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h @@ -0,0 +1,66 @@ +#ifndef _JTEST_GROUP_H_ +#define _JTEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_pf.h" +#include "jtest_util.h" + +/*--------------------------------------------------------------------------------*/ +/* Type Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * A struct which represents a group of #JTEST_TEST_t structs. This struct is + * used to run the group of tests, and report on their outcomes. + */ +typedef struct JTEST_GROUP_struct +{ + void (* group_fn_ptr) (void); /**< Pointer to the test group */ + char * name_str; /**< Name of the group */ + + /* Extend the #JTEST_GROUP_t with Pass/Fail information.*/ + JTEST_PF_MEMBERS; +} JTEST_GROUP_t; + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Set the name of JTEST_GROUP_t. + */ +#define JTEST_GROUP_SET_NAME(group_ptr, name) \ + JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, name_str, name) + +#define JTEST_GROUP_SET_FN(group_ptr, fn_ptr) \ + JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, group_fn_ptr, fn_ptr) + +/** + * Increment the number of tests passed in the JTEST_GROUP_t pointed to by + * group_ptr. + */ +#define JTEST_GROUP_INC_PASSED(group_ptr, amount) \ + JTEST_PF_INC_PASSED(group_ptr, amount) + +/** + * Increment the number of tests failed in the JTEST_GROUP_t pointed to by + * group_ptr. + */ +#define JTEST_GROUP_INC_FAILED(group_ptr, amount) \ + JTEST_PF_INC_FAILED(group_ptr, amount) + +/** + * Reset the pass/fail information of the #JTEST_GROUP_t pointed to by + * group_ptr. + */ +#define JTEST_GROUP_RESET_PF(group_ptr) \ + do \ + { \ + JTEST_PF_RESET_PASSED(group_ptr); \ + JTEST_PF_RESET_FAILED(group_ptr); \ + } while (0) + +#endif /* _JTEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h new file mode 100644 index 0000000..6b60958 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h @@ -0,0 +1,126 @@ +#ifndef _JTEST_GROUP_CALL_H_ +#define _JTEST_GROUP_CALL_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_fw.h" +#include + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Execute the test in the #JTEST_GROUP_t struct associated witht he identifier + * group_fn. + */ +#define JTEST_GROUP_RUN(group_fn) \ + do \ + { \ + JTEST_DUMP_STR("Group Name:\n"); \ + JTEST_DUMP_STR(JTEST_GROUP_STRUCT_NAME(group_fn).name_str); \ + JTEST_GROUP_STRUCT_NAME(group_fn).group_fn_ptr(); \ + } while (0) + + +/** + * Update the enclosing #JTEST_GROUP_t's pass/fail information using the + * current #JTEST_GROUP_t's. + * + * @param group_ptr Pointer to the current #JTEST_GROUP_t. + * @param parent_ptr Pointer to the enclosing #JTEST_GROUP_t. + * + * @warning Only run this if the current #JTEST_GROUP_t is being called within + * the context of another #JTEST_GROUP_t. + */ +#define JTEST_GROUP_UPDATE_PARENT_GROUP_PF(group_ptr, parent_group_ptr) \ + do \ + { \ + JTEST_GROUP_INC_PASSED(parent_group_ptr, \ + (group_ptr)->passed); \ + JTEST_GROUP_INC_FAILED(parent_group_ptr, \ + (group_ptr)->failed); \ + } while (0) + +/** + * Update the #JTEST_FW's pass/fail information using the current + * #JTEST_GROUP_t's. + */ +#define JTEST_GROUP_UPDATE_FW_PF(group_ptr) \ + do \ + { \ + JTEST_FW_INC_PASSED((group_ptr)->passed); \ + JTEST_FW_INC_FAILED((group_ptr)->failed); \ + } while (0) + +/** + * Update the enclosing context with the current #JTEST_GROUP_t's pass/fail + * information. If this group isn't in an enclosing group, it updates the + * #JTEST_FW's pass/fail info by default. + */ +#define JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(group_ptr, \ + parent_group_ptr) \ + do \ + { \ + /* Update the pass fail counts in the parent group */ \ + if (parent_group_ptr /* Null implies Top*/) \ + { \ + JTEST_GROUP_UPDATE_PARENT_GROUP_PF( \ + group_ptr, \ + parent_group_ptr); \ + } else { \ + JTEST_GROUP_UPDATE_FW_PF( \ + group_ptr); \ + } \ + } while (0) + +/** + * Dump the results of running the #JTEST_GROUP_t to the Keil Debugger. + */ +#define JTEST_GROUP_DUMP_RESULTS(group_ptr) \ + do \ + { \ + JTEST_DUMP_STRF( \ + "Tests Run: %" PRIu32 "\n" \ + "----------\n" \ + " Passed: %" PRIu32 "\n" \ + " Failed: %" PRIu32 "\n", \ + (group_ptr)->passed + (group_ptr)->failed, \ + (group_ptr)->passed, \ + (group_ptr)->failed); \ + } while (0) + +/** + * Call the #JTEST_GROUP_t associated with the identifier group_fn. + */ +#define JTEST_GROUP_CALL(group_fn) \ + do \ + { /* Save the current group from JTEST_FW_t before swapping */ \ + /* it to this group (in order to restore it later )*/ \ + JTEST_GROUP_t * __jtest_temp_group_ptr = \ + JTEST_CURRENT_GROUP_PTR(); \ + JTEST_SET_CURRENT_GROUP(&JTEST_GROUP_STRUCT_NAME(group_fn)); \ + \ + /* Reset this group's pass/fail count. Each group */ \ + /* should only remember counts for its last execution. */ \ + JTEST_GROUP_RESET_PF(JTEST_CURRENT_GROUP_PTR()); \ + \ + /* Run the current group */ \ + JTEST_ACT_GROUP_START(); \ + JTEST_GROUP_RUN(group_fn); \ + JTEST_ACT_GROUP_END(); \ + \ + /* Update the pass fail counts in the parent group (or FW) */ \ + JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF( \ + JTEST_CURRENT_GROUP_PTR(), \ + __jtest_temp_group_ptr); \ + \ + JTEST_GROUP_DUMP_RESULTS(JTEST_CURRENT_GROUP_PTR()); \ + \ + /* Restore the previously current group */ \ + JTEST_SET_CURRENT_GROUP(__jtest_temp_group_ptr); \ + } while (0) + +#endif /* _JTEST_GROUP_CALL_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h new file mode 100644 index 0000000..673a287 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h @@ -0,0 +1,87 @@ +#ifndef _JTEST_GROUP_DEFINE_H_ +#define _JTEST_GROUP_DEFINE_H_ + + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_util.h" +#include "jtest_define.h" +#include "jtest_group.h" + +/* For defining macros with optional arguments */ +#include "opt_arg/opt_arg.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Prefix for all #JTEST_GROUP_t structs. + */ +#define JTEST_GROUP_STRUCT_NAME_PREFIX G_JTEST_GROUP_STRUCT_ + +/** + * Define test template used by #JTEST_GROUP_t tests. + */ +#define JTEST_GROUP_FN_TEMPLATE(group_fn) \ + void group_fn(void) + +#define JTEST_GROUP_FN_PROTOTYPE JTEST_GROUP_FN_TEMPLATE /**< Alias for + #JTEST_GROUP_FN_TEMPLATE. */ + +/** + * Evaluate to the name of the #JTEST_GROUP_t struct associated with group_fn. + */ +#define JTEST_GROUP_STRUCT_NAME(group_fn) \ + JTEST_STRUCT_NAME(JTEST_GROUP_STRUCT_NAME_PREFIX, group_fn) + +/** + * Define a #JTEST_GROUP_t struct based on the given group_fn. + */ +#define JTEST_GROUP_DEFINE_STRUCT(group_fn) \ + JTEST_DEFINE_STRUCT(JTEST_GROUP_t, \ + JTEST_GROUP_STRUCT_NAME(group_fn)) + +/** + * Declare a #JTEST_GROUP_t struct based on the given group_fn. + */ +#define JTEST_GROUP_DECLARE_STRUCT(group_fn) \ + JTEST_DECLARE_STRUCT(JTEST_GROUP_DEFINE_STRUCT(group_fn)) + +/** + * Contents needed to initialize a JTEST_GROUP_t struct. + */ +#define JTEST_GROUP_STRUCT_INIT(group_fn) \ + group_fn, \ + STR_NL(group_fn), \ + JTEST_PF_MEMBER_INIT + +/** + * Initialize the contents of a #JTEST_GROUP_t struct. + */ +#define JTEST_GROUP_INIT(group_fn) \ + JTEST_GROUP_DEFINE_STRUCT(group_fn) = { \ + JTEST_GROUP_STRUCT_INIT(group_fn) \ + } + +/* Test Definition Macro */ +/*--------------------------------------------------------------------------------*/ + +/** + * Define a #JTEST_GROUP_t object and a test function. + */ +#define JTEST_DEFINE_GROUP(group_fn) \ + JTEST_GROUP_FN_PROTOTYPE(group_fn); \ + JTEST_GROUP_INIT(group_fn); \ + JTEST_GROUP_FN_PROTOTYPE(group_fn) /* Notice the lacking semicolon */ + +/** + * Declare a #JTEST_GROUP_t object and a test function prototype. + */ +#define JTEST_DECLARE_GROUP(group_fn) \ + JTEST_GROUP_FN_PROTOTYPE(group_fn); \ + JTEST_GROUP_DECLARE_STRUCT(group_fn) /* Note the lacking semicolon */ + +#endif /* _JTEST_GROUP_DEFINE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h new file mode 100644 index 0000000..6e55d40 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h @@ -0,0 +1,85 @@ +#ifndef _JTEST_PF_H_ +#define _JTEST_PF_H_ + +/*--------------------------------------------------------------------------------*/ +/* Purpose */ +/*--------------------------------------------------------------------------------*/ +/* jtest_pf.h Contains macros useful for capturing pass/fail data. */ + + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Members that can be added to other structs to extend them pass/fail data and + * corresponding functionality. + */ +#define JTEST_PF_MEMBERS \ + uint32_t passed; \ + uint32_t failed /* Note the lacking semicolon*/ \ + +/** + * Used for initializing JTEST_PF_MEMBERS in a struct declaration. + */ +#define JTEST_PF_MEMBER_INIT \ + 0, \ + 0 + +/* Member-Incrementing Macros */ +/*--------------------------------------------------------------------------------*/ + +/** + * Dispatch macro for incrementing #JTEST_PF_MEMBERS. + * + * @param xxx Values: 'passed', 'failed' + */ +#define JTEST_PF_INC_XXX(xxx, struct_pf_ptr, amount) \ + do \ + { \ + ((struct_pf_ptr)->xxx) += (amount); \ + } while (0) + +/** + * Specialization of the #JTEST_PF_INC_XXX macro to increment the passed + * member. + */ +#define JTEST_PF_INC_PASSED(struct_pf_ptr, amount) \ + JTEST_PF_INC_XXX(passed, struct_pf_ptr, amount) + + +/** + * Specialization of the #JTEST_PF_INC_XXX macro to increment the failed + * member. + */ +#define JTEST_PF_INC_FAILED(struct_pf_ptr, amount) \ + JTEST_PF_INC_XXX(failed, struct_pf_ptr, amount) + + +/* Member-Resetting Macros */ +/*--------------------------------------------------------------------------------*/ + +/** + * Dispatch macro for setting #JTEST_PF_MEMBERS to zero. + * + * @param xxx Values: 'passed', 'failed' + */ +#define JTEST_PF_RESET_XXX(xxx, struct_pf_ptr) \ + do \ + { \ + ((struct_pf_ptr)->xxx) = UINT32_C(0); \ + } while (0) + +/** + * Specialization of #JTEST_PF_RESET_XXX for the 'passed' member. + */ +#define JTEST_PF_RESET_PASSED(struct_pf_ptr) \ + JTEST_PF_RESET_XXX(passed, struct_pf_ptr) + +/** + * Specialization of #JTEST_PF_RESET_XXX for the 'failed' member. + */ +#define JTEST_PF_RESET_FAILED(struct_pf_ptr) \ + JTEST_PF_RESET_XXX(failed, struct_pf_ptr) + +#endif /* _JTEST_PF_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h new file mode 100644 index 0000000..afb6e05 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h @@ -0,0 +1,94 @@ +#ifndef _JTEST_SYSTICK_H_ +#define _JTEST_SYSTICK_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +/* Get access to the SysTick structure. */ +#if defined ARMCM0 + #include "ARMCM0.h" +#elif defined ARMCM0P + #include "ARMCM0plus.h" +#elif defined ARMCM0P_MPU + #include "ARMCM0plus_MPU.h" +#elif defined ARMCM3 + #include "ARMCM3.h" +#elif defined ARMCM4 + #include "ARMCM4.h" +#elif defined ARMCM4_FP + #include "ARMCM4_FP.h" +#elif defined ARMCM7 + #include "ARMCM7.h" +#elif defined ARMCM7_SP + #include "ARMCM7_SP.h" +#elif defined ARMCM7_DP + #include "ARMCM7_DP.h" +#elif defined ARMSC000 + #include "ARMSC000.h" +#elif defined ARMSC300 + #include "ARMSC300.h" +#elif defined ARMv8MBL + #include "ARMv8MBL.h" +#elif defined ARMv8MML + #include "ARMv8MML.h" +#elif defined ARMv8MML_DSP + #include "ARMv8MML_DSP.h" +#elif defined ARMv8MML_SP + #include "ARMv8MML_SP.h" +#elif defined ARMv8MML_DSP_SP + #include "ARMv8MML_DSP_SP.h" +#elif defined ARMv8MML_DP + #include "ARMv8MML_DP.h" +#elif defined ARMv8MML_DSP_DP + #include "ARMv8MML_DSP_DP.h" +#elif defined ARMv7A + /* TODO */ +#else + #warning "no appropriate header file found!" +#endif + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Initial value for the SysTick module. + * + * This is also the maximum value, important as SysTick is a decrementing counter. + */ +#define JTEST_SYSTICK_INITIAL_VALUE 0xFFFFFF + +/** + * Reset the SysTick, decrementing timer to it's maximum value and disable it. + * + * This macro should leave the SysTick timer in a state that's ready for cycle + * counting. + */ +#define JTEST_SYSTICK_RESET(systick_ptr) \ + do \ + { \ + (systick_ptr)->CTRL = SysTick_CTRL_CLKSOURCE_Msk; \ + \ + (systick_ptr)->LOAD = JTEST_SYSTICK_INITIAL_VALUE; \ + (systick_ptr)->VAL = JTEST_SYSTICK_INITIAL_VALUE; \ + } while (0) + +/** + * Start the SysTick timer, sourced by the processor clock. + */ +#define JTEST_SYSTICK_START(systick_ptr) \ + do \ + { \ + (systick_ptr)->CTRL = \ + SysTick_CTRL_ENABLE_Msk | \ + SysTick_CTRL_CLKSOURCE_Msk; \ + } while (0) + +/** + * Evaluate to the current value of the SysTick timer. + */ +#define JTEST_SYSTICK_VALUE(systick_ptr) \ + ((systick_ptr)->VAL) + +#endif /* _JTEST_SYSTICK_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h new file mode 100644 index 0000000..397c562 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h @@ -0,0 +1,100 @@ +#ifndef _JTEST_TEST_H_ +#define _JTEST_TEST_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include +#include "jtest_util.h" +#include "jtest_test_ret.h" + +/*--------------------------------------------------------------------------------*/ +/* Type Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * A struct which represents a Test in the JTEST framework. This struct is + * used to enable, run, and describe the test it represents. + */ +typedef struct JTEST_TEST_struct +{ + JTEST_TEST_RET_t ( * test_fn_ptr)(void); /**< Pointer to the test function. */ + char * test_fn_str; /**< Name of the test function */ + char * fut_str; /**< Name of the function under test. */ + + /** + * Flags that govern how the #JTEST_TEST_t behaves. + */ + union { + struct { + unsigned enabled : 1; + unsigned unused : 7; + } bits; + uint8_t byte; /* Access all flags at once. */ + } flags; + +} JTEST_TEST_t; + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Assign a test function to the #JTEST_TEST_t struct. + */ +#define JTEST_TEST_SET_FN(jtest_test_ptr, fn_ptr) \ + JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, test_fn_ptr, fn_ptr) + +/** + * Specify a function under test (FUT) for the #JTEST_TEST_t struct. + */ +#define JTEST_TEST_SET_FUT(jtest_test_ptr, str) \ + JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, fut_str, str) + +/* Macros concerning JTEST_TEST_t flags */ +/*--------------------------------------------------------------------------------*/ + +#define JTEST_TEST_FLAG_SET 1 /**< Value of a set #JTEST_TEST_t flag. */ +#define JTEST_TEST_FLAG_CLR 0 /**< Value of a cleared #JTEST_TEST_t flag. */ + +/** + * Evaluate to the flag in #JTEST_TEST_t having flag_name. + */ +#define JTEST_TEST_FLAG(jtest_test_ptr, flag_name) \ + ((jtest_test_ptr)->flags.bits.flag_name) + +/** + * Dispatch macro for setting and clearing #JTEST_TEST_t flags. + * + * @param jtest_test_ptr Pointer to a #JTEST_TEST_t struct. + * @param flag_name Name of the flag to set in #JTEST_TEST_t.flags.bits + * @param xxx Vaid values: "SET" or "CLR" + * + * @note This function depends on JTEST_TEST_FLAG_SET and JTEST_TEST_FLAG_CLR. + */ +#define JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, xxx) \ + do \ + { \ + JTEST_TEST_FLAG(jtest_test_ptr, flag_name) = JTEST_TEST_FLAG_##xxx ; \ + } while (0) + +/** + * Specification of #JTEST_TEST_XXX_FLAG to set #JTEST_TEST_t flags. + */ +#define JTEST_TEST_SET_FLAG(jtest_test_ptr, flag_name) \ + JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, SET) + +/** + * Specification of #JTEST_TEST_XXX_FLAG to clear #JTEST_TEST_t flags. + */ +#define JTEST_TEST_CLR_FLAG(jtest_test_ptr, flag_name) \ + JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, CLR) + +/** + * Evaluate to true if the #JTEST_TEST_t is enabled. + */ +#define JTEST_TEST_IS_ENABLED(jtest_test_ptr) \ + (JTEST_TEST_FLAG(jtest_test_ptr, enabled) == JTEST_TEST_FLAG_SET) + +#endif /* _JTEST_TEST_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h new file mode 100644 index 0000000..2040370 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h @@ -0,0 +1,121 @@ +#ifndef _JTEST_TEST_CALL_H_ +#define _JTEST_TEST_CALL_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ +#include "jtest_test.h" +#include "jtest_test_define.h" +#include "jtest_fw.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Exectute the test in the #JTEST_TEST_t struct associated with the identifier + * test_fn and store the result in retval. + */ +#define JTEST_TEST_RUN(retval, test_fn) \ + do \ + { \ + JTEST_DUMP_STR("Test Name:\n"); \ + JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).test_fn_str); \ + JTEST_DUMP_STR("Function Under Test:\n"); \ + JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).fut_str); \ + retval = JTEST_TEST_STRUCT_NAME(test_fn).test_fn_ptr(); \ + } while (0) + +/** + * Update the enclosing #JTEST_GROUP_t's pass/fail information based on + * test_retval. + * + * @param test_retval A #JTEST_TEST_RET_enum for the current test. + * + * @warning Only use if #JTEST_TEST_t is called in the context of a + * #JTEST_GROUP_t. + */ +#define JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval) \ + do \ + { \ + /* Update enclosing JTEST_GROUP_t with pass/fail info */ \ + if (test_retval == JTEST_TEST_PASSED) \ + { \ + JTEST_GROUP_INC_PASSED(JTEST_CURRENT_GROUP_PTR(), 1); \ + } else { \ + JTEST_GROUP_INC_FAILED(JTEST_CURRENT_GROUP_PTR(), 1); \ + } \ + } while (0) + +/** + * Update the #JTEST_FW with pass/fail information based on test_retval. + * + * @param test_retval A #JTEST_TEST_RET_enum for the current test. + */ +#define JTEST_TEST_UPDATE_FW_PF(test_retval) \ + do \ + { \ + /* Update the JTEST_FW with pass/fail info */ \ + if (test_retval == JTEST_TEST_PASSED) \ + { \ + JTEST_FW_INC_PASSED( 1); \ + } else { \ + JTEST_FW_INC_FAILED(1); \ + } \ + } while (0) + +/** + * Update the enclosing JTEST_GROUP_t's pass/fail information, or the + * #JTEST_FW's if this test has no enclosing #JTEST_GROUP_t. + * + * @param test_retval A #JTEST_TEST_RET_enum for the current test. + */ +#define JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(test_retval) \ + do \ + { \ + /* Update pass-fail information */ \ + if (JTEST_CURRENT_GROUP_PTR() /* Non-null */) \ + { \ + JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval); \ + } else { \ + JTEST_TEST_UPDATE_FW_PF(test_retval); \ + } \ + } while (0) + +/** + * Dump the results of the test to the Keil Debugger. + */ +#define JTEST_TEST_DUMP_RESULTS(test_retval) \ + do \ + { \ + if (test_retval == JTEST_TEST_PASSED) \ + { \ + JTEST_DUMP_STR("Test Passed\n"); \ + } else { \ + JTEST_DUMP_STR("Test Failed\n"); \ + } \ + } while (0) + +/** + * Call the #JTEST_TEST_t assocaited with the identifier test_fn. + */ +#define JTEST_TEST_CALL(test_fn) \ + do \ + { \ + if (JTEST_TEST_IS_ENABLED(&JTEST_TEST_STRUCT_NAME(test_fn))) \ + { \ + /* Default to failure */ \ + JTEST_TEST_RET_t __jtest_test_ret = JTEST_TEST_FAILED; \ + \ + JTEST_ACT_TEST_START(); \ + JTEST_TEST_RUN(__jtest_test_ret, test_fn); \ + \ + /* Update pass-fail information */ \ + JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(__jtest_test_ret); \ + \ + JTEST_TEST_DUMP_RESULTS(__jtest_test_ret); \ + JTEST_ACT_TEST_END(); \ + } \ + } while (0) + +#endif /* _JTEST_TEST_CALL_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h new file mode 100644 index 0000000..de30251 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h @@ -0,0 +1,133 @@ +#ifndef _JTEST_TEST_DEFINE_H_ +#define _JTEST_TEST_DEFINE_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_util.h" +#include "jtest_define.h" +#include "jtest_test.h" + +/* For defining macros with optional arguments */ +#include "opt_arg/opt_arg.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Prefix for all #JTEST_TEST_t structs. + */ +#define JTEST_TEST_STRUCT_NAME_PREFIX G_JTEST_TEST_STRUCT_ + +/** + * Define test template used by #JTEST_TEST_t tests. + */ +#define JTEST_TEST_FN_TEMPLATE(test_fn) \ + JTEST_TEST_RET_t test_fn(void) + +#define JTEST_TEST_FN_PROTOTYPE JTEST_TEST_FN_TEMPLATE /**< Alias for + * #JTEST_TEST_FN_TEMPLATE. */ + +/** + * Evaluate to the name of the #JTEST_TEST_t struct associated with test_fn. + */ +#define JTEST_TEST_STRUCT_NAME(test_fn) \ + JTEST_STRUCT_NAME(JTEST_TEST_STRUCT_NAME_PREFIX, test_fn) + +/** + * Define a #JTEST_TEST_t struct based on the given test_fn. + */ +#define JTEST_TEST_DEFINE_STRUCT(test_fn) \ + JTEST_DEFINE_STRUCT(JTEST_TEST_t, \ + JTEST_TEST_STRUCT_NAME(test_fn)) + +/** + * Declare a #JTEST_TEST_t struct based on the given test_fn. + */ +#define JTEST_TEST_DECLARE_STRUCT(test_fn) \ + JTEST_DECLARE_STRUCT(JTEST_TEST_DEFINE_STRUCT(test_fn)) + +/** + * Contents needed to initialize a JTEST_TEST_t struct. + */ +#define JTEST_TEST_STRUCT_INIT(test_fn, fut, enable) \ + test_fn, \ + STR_NL(test_fn), \ + STR_NL(fut), \ + { \ + { \ + enable, \ + 0 \ + } \ + } \ + + +/** + * Initialize the contents of a #JTEST_TEST_t struct. + */ +#define JTEST_TEST_INIT(test_fn, fut, enable) \ + JTEST_TEST_DEFINE_STRUCT(test_fn) = { \ + JTEST_TEST_STRUCT_INIT(test_fn, fut, enable) \ + } + +/* Test Definition Macro */ +/*--------------------------------------------------------------------------------*/ + +/** + * Define a #JTEST_TEST_t object and a test function. + */ +#define _JTEST_DEFINE_TEST(test_fn, fut, enable) \ + JTEST_TEST_FN_PROTOTYPE(test_fn); \ + JTEST_TEST_INIT(test_fn, fut, enable); \ + JTEST_TEST_FN_PROTOTYPE(test_fn) /* Notice the lacking semicolon */ + +/** + * Declare a #JTEST_TEST_t object and a test function prototype. + */ +#define JTEST_DECLARE_TEST(test_fn) \ + JTEST_TEST_FN_PROTOTYPE(test_fn); \ + JTEST_TEST_DECLARE_STRUCT(test_fn) /* Note the lacking semicolon */ + +/*--------------------------------------------------------------------------------*/ +/* Macros with optional arguments */ +/*--------------------------------------------------------------------------------*/ + +/* Top-level Interface */ +#define JTEST_DEFINE_TEST(...) \ + JTEST_DEFINE_TEST_(PP_NARG(__VA_ARGS__), ##__VA_ARGS__) + +/* Dispatch Macro*/ +#define JTEST_DEFINE_TEST_(N, ...) \ + SPLICE(JTEST_DEFINE_TEST_, N)(__VA_ARGS__) + +/* Default Arguments */ +#define JTEST_DEFINE_TEST_DEFAULT_FUT /* Blank */ +#define JTEST_DEFINE_TEST_DEFAULT_ENABLE \ + JTEST_TRUE /* Tests enabled by + * default. */ + +/* Dispatch Cases*/ +#define JTEST_DEFINE_TEST_1(_1) \ + _JTEST_DEFINE_TEST( \ + _1, \ + JTEST_DEFINE_TEST_DEFAULT_FUT, \ + JTEST_DEFINE_TEST_DEFAULT_ENABLE \ + ) + +#define JTEST_DEFINE_TEST_2(_1, _2) \ + _JTEST_DEFINE_TEST( \ + _1, \ + _2, \ + JTEST_DEFINE_TEST_DEFAULT_ENABLE \ + ) + +#define JTEST_DEFINE_TEST_3(_1, _2, _3) \ + _JTEST_DEFINE_TEST( \ + _1, \ + _2, \ + _3 \ + ) + +#endif /* _JTEST_TEST_DEFINE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h new file mode 100644 index 0000000..e8d80f3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h @@ -0,0 +1,17 @@ +#ifndef _JTEST_TEST_RET_H_ +#define _JTEST_TEST_RET_H_ + +/*--------------------------------------------------------------------------------*/ +/* Type Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * Values a #JTEST_TEST_t can return. + */ +typedef enum JTEST_TEST_RET_enum +{ + JTEST_TEST_PASSED, + JTEST_TEST_FAILED +} JTEST_TEST_RET_t; + +#endif /* _JTEST_TEST_RET_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h new file mode 100644 index 0000000..3dec6ea --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h @@ -0,0 +1,27 @@ +#ifndef _JTEST_UTIL_H_ +#define _JTEST_UTIL_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "util/util.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/* Define boolean values for the framework. */ +#define JTEST_TRUE 1 /**< Value used for TRUE in JTEST. */ +#define JTEST_FALSE 0 /**< Value used for FALSE in JTEST. */ + +/** + * Set the value of the attribute in the struct to by struct_ptr to value. + */ +#define JTEST_SET_STRUCT_ATTRIBUTE(struct_ptr, attribute, value) \ + do \ + { \ + (struct_ptr)->attribute = (value); \ + } while (0) + +#endif /* _JTEST_UTIL_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h new file mode 100644 index 0000000..94bf0e0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h @@ -0,0 +1,15 @@ +#ifndef _OPT_ARG_H_ +#define _OPT_ARG_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "pp_narg.h" +#include "splice.h" + +/* If you are Joseph Jaoudi, you have a snippet which expands into an + example. If you are not Joseph, but possess his code, study the examples. If + you have no examples, turn back contact Joseph. */ + +#endif /* _OPT_ARG_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h new file mode 100644 index 0000000..48103c4 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h @@ -0,0 +1,25 @@ +#ifndef _PP_NARG_H_ +#define _PP_NARG_H_ + +#define PP_NARG(...) \ + PP_NARG_(__VA_ARGS__,PP_RSEQ_N()) +#define PP_NARG_(...) \ + PP_ARG_N(__VA_ARGS__) +#define PP_ARG_N( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \ + _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ + _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ + _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \ + _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ + _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ + _61,_62,_63,N,...) N +#define PP_RSEQ_N() \ + 63,62,61,60, \ + 59,58,57,56,55,54,53,52,51,50, \ + 49,48,47,46,45,44,43,42,41,40, \ + 39,38,37,36,35,34,33,32,31,30, \ + 29,28,27,26,25,24,23,22,21,20, \ + 19,18,17,16,15,14,13,12,11,10, \ + 9,8,7,6,5,4,3,2,1,0 + +#endif /* _PP_NARG_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h new file mode 100644 index 0000000..e312420 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h @@ -0,0 +1,8 @@ +#ifndef _SPLICE_H_ +#define _SPLICE_H_ + +#define SPLICE(a,b) SPLICE_1(a,b) +#define SPLICE_1(a,b) SPLICE_2(a,b) +#define SPLICE_2(a,b) a##b + +#endif /* _SPLICE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h new file mode 100644 index 0000000..4a7ca9c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h @@ -0,0 +1,52 @@ +#ifndef _UTIL_H_ +#define _UTIL_H_ + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Convert a symbol to a string and add a 'NewLine'. + */ +#define STR_NL(x) STR1_NL(x) +#define STR1_NL(x) (STR2_NL(x)"\n") +#define STR2_NL(x) #x + +/** + * Convert a symbol to a string. + */ +#define STR(x) STR1(x) +#define STR1(x) STR2(x) +#define STR2(x) #x + +/** + * Concatenate two symbols. + */ +#define CONCAT(a, b) CONCAT1(a, b) +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a##b + + +/** + * Place curly braces around a varaible number of macro arguments. + */ +#define CURLY(...) {__VA_ARGS__} + +/** + * Place parenthesis around a variable number of macro arguments. + */ +#define PAREN(...) (__VA_ARGS__) + +/* Standard min/max macros. */ +#define MIN(x,y) (((x) < (y)) ? (x) : (y) ) +#define MAX(x,y) (((x) > (y)) ? (x) : (y) ) + +/** + * Bound value using low and high limits. + * + * Evaluate to a number in the range, endpoint inclusive. + */ +#define BOUND(low, high, value) \ + MAX(MIN(high, value), low) + +#endif /* _UTIL_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c new file mode 100644 index 0000000..d58518b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c @@ -0,0 +1,9 @@ +#include "../inc/jtest_cycle.h" +#include + +/*--------------------------------------------------------------------------------*/ +/* Define Module Variables */ +/*--------------------------------------------------------------------------------*/ + +/* const char * JTEST_CYCLE_STRF = "Running: %s\nCycles: %" PRIu32 "\n"; */ +const char * JTEST_CYCLE_STRF = "Cycles: %" PRIu32 "\n"; /* function name + parameter string skipped */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c new file mode 100644 index 0000000..b546746 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c @@ -0,0 +1,36 @@ +#include "jtest_fw.h" + +/** + * Dump the JTEST_FW.str_buffer the Keil framework in pieces. + * + * The JTEST_FW.str_buffer contains more characters than the Keil framework can + * dump at once. This function dumps them in blocks. + */ +void jtest_dump_str_segments(void) +{ + uint32_t seg_idx = 0; + uint32_t memmove_idx = 0; + uint32_t seg_cnt = + (strlen(JTEST_FW.str_buffer) / JTEST_STR_MAX_OUTPUT_SIZE) + 1; + + for( seg_idx = 0; seg_idx < seg_cnt; ++seg_idx) + { + JTEST_TRIGGER_ACTION(dump_str); + + if (seg_idx < JTEST_STR_MAX_OUTPUT_SEGMENTS) + { + memmove_idx = 0; + while (memmove_idx < (seg_cnt - seg_idx -1) ) + { + memmove( + JTEST_FW.str_buffer+ + (memmove_idx* JTEST_STR_MAX_OUTPUT_SIZE), + JTEST_FW.str_buffer+ + ((memmove_idx+1)*JTEST_STR_MAX_OUTPUT_SIZE), + JTEST_BUF_SIZE); + ++memmove_idx; + } + } + } + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c new file mode 100644 index 0000000..9d4a583 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c @@ -0,0 +1,9 @@ +#include "../inc/jtest.h" + +/*--------------------------------------------------------------------------------*/ +/* Define Global Variables */ +/*--------------------------------------------------------------------------------*/ + +char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE] = {0}; + +volatile JTEST_FW_t JTEST_FW = {0}; diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c new file mode 100644 index 0000000..ca9e43c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c @@ -0,0 +1,37 @@ + +#include "jtest_fw.h" + +void test_start (void) { +// ; + JTEST_FW.test_start++; +} + +void test_end (void) { +// ; + JTEST_FW.test_end++; +} + +void group_start (void) { +// ; + JTEST_FW.group_start++; +} + +void group_end (void) { +// ; + JTEST_FW.group_end++; +} + +void dump_str (void) { +// ; + JTEST_FW.dump_str++; +} + +void dump_data (void) { +// ; + JTEST_FW.dump_data++; +} + +void exit_fw (void) { +// ; + JTEST_FW.exit_fw++; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h new file mode 100644 index 0000000..4b2b935 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h @@ -0,0 +1,9 @@ +#ifndef _ALL_TESTS_H_ +#define _ALL_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(all_tests); + +#endif /* _ALL_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h new file mode 100644 index 0000000..5b6b294 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h @@ -0,0 +1,267 @@ +#ifndef _BASIC_MATH_TEMPLATES_H_ +#define _BASIC_MATH_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ +#include "test_templates.h" + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Compare the outputs used by basic math tests for the function under test and + * the reference function. + */ +#define BASIC_MATH_COMPARE_INTERFACE(block_size, output_type) \ + TEST_ASSERT_BUFFERS_EQUAL( \ + basic_math_output_ref.data_ptr, \ + basic_math_output_fut.data_ptr, \ + block_size * sizeof(output_type)) + +/* + * Comparison SNR thresholds for the data types used in basic_math_tests. + */ +#define BASIC_MATH_SNR_THRESHOLD_float32_t 120 +#define BASIC_MATH_SNR_THRESHOLD_q31_t 100 +#define BASIC_MATH_SNR_THRESHOLD_q15_t 75 +#define BASIC_MATH_SNR_THRESHOLD_q7_t 25 + +/** + * Compare reference and fut outputs using SNR. + * + * @note The outputs are converted to float32_t before comparison. + */ +#define BASIC_MATH_SNR_COMPARE_INTERFACE(block_size, output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + basic_math_output_f32_ref, \ + basic_math_output_ref.data_ptr, \ + basic_math_output_f32_fut, \ + basic_math_output_fut.data_ptr, \ + block_size, \ + output_type, \ + BASIC_MATH_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + + +/** + * Compare reference and fut outputs using SNR. + * + * @note The outputs are converted to float32_t before comparison. + */ +#define BASIC_MATH_SNR_ELT1_COMPARE_INTERFACE(block_size, output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + basic_math_output_f32_ref, \ + basic_math_output_ref.data_ptr, \ + basic_math_output_f32_fut, \ + basic_math_output_fut.data_ptr, \ + 1, \ + output_type, \ + BASIC_MATH_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + + + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define ARM_abs_INPUT_INTERFACE(input, block_size) \ + PAREN(input, basic_math_output_fut.data_ptr, block_size) + +#define REF_abs_INPUT_INTERFACE(input, block_size) \ + PAREN(input, basic_math_output_ref.data_ptr, block_size) + +#define ARM_add_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_add_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \ + +#define ARM_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, block_size, basic_math_output_fut.data_ptr) \ + +#define REF_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, block_size, basic_math_output_ref.data_ptr) \ + +#define ARM_mult_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_mult_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \ + +#define ARM_negate_INPUT_INTERFACE(input, block_size) \ + PAREN(input, basic_math_output_fut.data_ptr, block_size) + +#define REF_negate_INPUT_INTERFACE(input, block_size) \ + PAREN(input, basic_math_output_ref.data_ptr, block_size) + +#define ARM_offset_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_offset_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \ + +#define ARM_shift_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_shift_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \ + +#define ARM_scale_float_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_scale_float_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \ + +/* These two are for the fixed point functions */ +#define ARM_scale_INPUT_INTERFACE(input, elt1, elt2, block_size) \ + PAREN(input, elt1, elt2, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_scale_INPUT_INTERFACE(input, elt1, elt2, block_size) \ + PAREN(input, elt1, elt2, basic_math_output_ref.data_ptr, block_size) \ + +#define ARM_sub_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_sub_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \ + + +/*--------------------------------------------------------------------------------*/ +/* Test Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Specialization of #TEST_TEMPLATE_BUF1_BLK() for basic math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_BLK( \ + basic_math_f_all, \ + basic_math_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + BASIC_MATH_COMPARE_INTERFACE); \ + } + +/** + * Specialization of #TEST_TEMPLATE_BUF2_BLK() for basic math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF2_BLK( \ + basic_math_f_all, \ + basic_math_f_all, \ + basic_math_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + +/** + * Specialization of #TEST_TEMPLATE_BUF1_ELT1_BLK() for basic math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK(fn_name, \ + suffix, \ + input_type, \ + elt_type, \ + output_type) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_ELT1_BLK( \ + basic_math_f_all, \ + basic_math_elts, \ + basic_math_block_sizes, \ + input_type, \ + elt_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + BASIC_MATH_COMPARE_INTERFACE); \ + } + +/** + * Specialization of #TEST_TEMPLATE_BUF1_ELT2_BLK() for basic math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT2_BLK(fn_name, \ + suffix, \ + input_type, \ + elt1_type, \ + elt2_type, \ + output_type) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_ELT2_BLK( \ + basic_math_f_all, \ + basic_math_elts, \ + basic_math_elts2, \ + basic_math_block_sizes, \ + input_type, \ + elt1_type, \ + elt2_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + BASIC_MATH_COMPARE_INTERFACE); \ + } + +#endif /* _BASIC_MATH_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h new file mode 100644 index 0000000..b387e0f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h @@ -0,0 +1,46 @@ +#ifndef ARM_BASIC_MATH_TEST_DATA_H +#define ARM_BASIC_MATH_TEST_DATA_H + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" +#include "arm_math.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ +#define BASIC_MATH_MAX_INPUT_ELEMENTS 32 +#define BASIC_MATH_BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Declare Variables */ +/*--------------------------------------------------------------------------------*/ + +/* Input/Output Buffers */ +ARR_DESC_DECLARE(basic_math_output_fut); +ARR_DESC_DECLARE(basic_math_output_ref); + +extern BASIC_MATH_BIGGEST_INPUT_TYPE +basic_math_output_f32_ref[BASIC_MATH_MAX_INPUT_ELEMENTS]; + +extern BASIC_MATH_BIGGEST_INPUT_TYPE +basic_math_output_f32_fut[BASIC_MATH_MAX_INPUT_ELEMENTS]; + +/* Block Sizes*/ +ARR_DESC_DECLARE(basic_math_block_sizes); + +/* Numbers */ +ARR_DESC_DECLARE(basic_math_elts); +ARR_DESC_DECLARE(basic_math_elts2); +ARR_DESC_DECLARE(basic_math_eltsf); + +/* Float Inputs */ +ARR_DESC_DECLARE(basic_math_zeros); +ARR_DESC_DECLARE(basic_math_f_2); +ARR_DESC_DECLARE(basic_math_f_15); +ARR_DESC_DECLARE(basic_math_f_32); +ARR_DESC_DECLARE(basic_math_f_all); + +#endif diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h new file mode 100644 index 0000000..98b7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h @@ -0,0 +1,9 @@ +#ifndef _BASIC_MATH_TEST_GROUP_H_ +#define _BASIC_MATH_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(basic_math_tests); + +#endif /* _BASIC_MATH_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h new file mode 100644 index 0000000..1b52999 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h @@ -0,0 +1,17 @@ +#ifndef _BASIC_MATH_TESTS_H_ +#define _BASIC_MATH_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(abs_tests); +JTEST_DECLARE_GROUP(add_tests); +JTEST_DECLARE_GROUP(dot_prod_tests); +JTEST_DECLARE_GROUP(mult_tests); +JTEST_DECLARE_GROUP(negate_tests); +JTEST_DECLARE_GROUP(offset_tests); +JTEST_DECLARE_GROUP(scale_tests); +JTEST_DECLARE_GROUP(shift_tests); +JTEST_DECLARE_GROUP(sub_tests); + +#endif /* _BASIC_MATH_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h new file mode 100644 index 0000000..a9c550b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h @@ -0,0 +1,222 @@ +#ifndef _COMPLEX_MATH_TEMPLATES_H_ +#define _COMPLEX_MATH_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ +#include "test_templates.h" + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Compare the real outputs from the function under test and the reference + * function. + */ +#define COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size, output_type) \ + TEST_ASSERT_BUFFERS_EQUAL( \ + complex_math_output_ref_a.data_ptr, \ + complex_math_output_fut_a.data_ptr, \ + block_size * sizeof(output_type)) + +/** + * Compare the real and imaginary outputs from the function under test and the + * reference function. + */ +#define COMPLEX_MATH_COMPARE_CMPLX_INTERFACE(block_size, output_type) \ + do \ + { \ + COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size * 2, output_type); \ + } while (0) + + +/* + * Comparison SNR thresholds for the data types used in complex_math_tests. + */ +#define COMPLEX_MATH_SNR_THRESHOLD_float32_t 120 +#define COMPLEX_MATH_SNR_THRESHOLD_q31_t 100 +#define COMPLEX_MATH_SNR_THRESHOLD_q15_t 75 + +/** + * Compare reference and fut outputs using SNR. + * + * The output_suffix specifies which output buffers to use for the + * comparison. An output_suffix of 'a' expands to the following buffers: + * + * - complex_math_output_f32_ref_a + * - complex_math_output_f32_fut_a + * - complex_math_output_ref_a + * - complex_math_output_fut_a + * + * @note The outputs are converted to float32_t before comparison. + */ +#define COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \ + output_type, \ + output_suffix) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + complex_math_output_f32_ref_##output_suffix, \ + complex_math_output_ref_##output_suffix.data_ptr, \ + complex_math_output_f32_fut_##output_suffix, \ + complex_math_output_fut_##output_suffix.data_ptr, \ + block_size, \ + output_type, \ + COMPLEX_MATH_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + +/** + * Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for real outputs. + */ +#define COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE(block_size, \ + output_type) \ + COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \ + output_type, \ + a) + +/** + * Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for complex outputs. + */ +#define COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE(block_size, \ + output_type) \ + COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size * 2, \ + output_type, \ + a) + +/** + * Compare reference and fut split outputs using SNR. + * + * 'Split' refers to two separate output buffers; one for real and one for + * complex. + */ +#define COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \ + output_type, \ + a); \ + COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \ + output_type, \ + b); \ + } while (0) + + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define ARM_cmplx_conj_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_fut_a.data_ptr, block_size) + +#define REF_cmplx_conj_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_ref_a.data_ptr, block_size) + +#define ARM_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, block_size, \ + complex_math_output_fut_a.data_ptr, \ + complex_math_output_fut_b.data_ptr) + +#define REF_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, block_size, \ + complex_math_output_ref_a.data_ptr, \ + complex_math_output_ref_b.data_ptr) + +#define ARM_cmplx_mag_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_fut_a.data_ptr, block_size) + +#define REF_cmplx_mag_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_ref_a.data_ptr, block_size) + +#define ARM_cmplx_mag_squared_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_fut_a.data_ptr, block_size) + +#define REF_cmplx_mag_squared_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_ref_a.data_ptr, block_size) + +#define ARM_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size) + +#define REF_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size) + +#define ARM_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size) + +#define REF_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size) + +/*--------------------------------------------------------------------------------*/ +/* Test Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Specialization of #TEST_TEMPLATE_BUF1_BLK() for complex math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_BLK( \ + complex_math_f_all, \ + complex_math_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + +/** + * Specialization of #TEST_TEMPLATE_BUF2_BLK1() for complex math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF2_BLK( \ + complex_math_f_all, \ + complex_math_f_all, \ + complex_math_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + +#endif /* _COMPLEX_MATH_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h new file mode 100644 index 0000000..e6438ec --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h @@ -0,0 +1,50 @@ +#ifndef _COMPLEX_MATH_TEST_DATA_H_ +#define _COMPLEX_MATH_TEST_DATA_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" +#include "arm_math.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ +#define COMPLEX_MATH_MAX_INPUT_ELEMENTS 32 +#define COMPLEX_MATH_BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Decalare Variables */ +/*--------------------------------------------------------------------------------*/ + +/* Input/Output Buffers */ +ARR_DESC_DECLARE(complex_math_output_fut_a); +ARR_DESC_DECLARE(complex_math_output_fut_b); +ARR_DESC_DECLARE(complex_math_output_ref_a); +ARR_DESC_DECLARE(complex_math_output_ref_b); + +extern COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_ref_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +extern COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_ref_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +extern COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_fut_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +extern COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_fut_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +/* Block Sizes*/ +ARR_DESC_DECLARE(complex_math_block_sizes); + +/* Float Inputs */ +ARR_DESC_DECLARE(complex_math_zeros); +ARR_DESC_DECLARE(complex_math_f_2); +ARR_DESC_DECLARE(complex_math_f_15); +ARR_DESC_DECLARE(complex_math_f_32); +ARR_DESC_DECLARE(complex_math_f_all); + + +#endif /* _COMPLEX_MATH_TEST_DATA_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h new file mode 100644 index 0000000..6665c92 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h @@ -0,0 +1,9 @@ +#ifndef _COMPLEX_MATH_TEST_GROUP_H_ +#define _COMPLEX_MATH_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(complex_math_tests); + +#endif /* _COMPLEX_MATH_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h new file mode 100644 index 0000000..e6709f3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h @@ -0,0 +1,14 @@ +#ifndef _COMPLEX_MATH_TESTS_H_ +#define _COMPLEX_MATH_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(cmplx_conj_tests); +JTEST_DECLARE_GROUP(cmplx_dot_prod_tests); +JTEST_DECLARE_GROUP(cmplx_mag_tests); +JTEST_DECLARE_GROUP(cmplx_mag_squared_tests); +JTEST_DECLARE_GROUP(cmplx_mult_cmplx_tests); +JTEST_DECLARE_GROUP(cmplx_mult_real_tests); + +#endif /* _COMPLEX_MATH_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h new file mode 100644 index 0000000..6e4d08e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h @@ -0,0 +1,46 @@ +#ifndef _CONTROLLER_TEMPLATES_H_ +#define _CONTROLLER_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "test_templates.h" +#include /* memcpy() */ + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Comparison SNR thresholds for the data types used in transform_tests. + */ +#define CONTROLLER_SNR_THRESHOLD_float32_t 110 +#define CONTROLLER_SNR_THRESHOLD_q31_t 100 +#define CONTROLLER_SNR_THRESHOLD_q15_t 45 + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. + */ +#define CONTROLLER_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + controller_output_f32_ref, \ + (output_type *) controller_output_ref, \ + controller_output_f32_fut, \ + (output_type *) controller_output_fut, \ + block_size, \ + output_type, \ + CONTROLLER_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + + +/*--------------------------------------------------------------------------------*/ +/* TEST Templates */ +/*--------------------------------------------------------------------------------*/ + +#endif /* _CONTROLLER_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h new file mode 100644 index 0000000..e194e90 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h @@ -0,0 +1,33 @@ +#ifndef _CONTROLLER_TEST_DATA_H_ +#define _CONTROLLER_TEST_DATA_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arm_math.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +#define CONTROLLER_MAX_LEN 1024 +#define CONTROLLER_MAX_COEFFS_LEN (12 * 3) +#define TRANFORM_BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Variable Declarations */ +/*--------------------------------------------------------------------------------*/ + +extern float32_t controller_output_fut[CONTROLLER_MAX_LEN]; +extern float32_t controller_output_ref[CONTROLLER_MAX_LEN]; +extern float32_t controller_output_f32_fut[CONTROLLER_MAX_LEN]; +extern float32_t controller_output_f32_ref[CONTROLLER_MAX_LEN]; +extern const float32_t controller_f32_inputs[CONTROLLER_MAX_LEN]; +extern const q31_t controller_q31_inputs[CONTROLLER_MAX_LEN]; +extern const q15_t * controller_q15_inputs; +extern const float32_t controller_f32_coeffs[CONTROLLER_MAX_COEFFS_LEN]; +extern const q31_t controller_q31_coeffs[CONTROLLER_MAX_COEFFS_LEN]; +extern const q15_t controller_q15_coeffs[CONTROLLER_MAX_COEFFS_LEN]; + +#endif /* _CONTROLLER_TEST_DATA_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h new file mode 100644 index 0000000..88d8e47 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h @@ -0,0 +1,9 @@ +#ifndef _CONTROLLER_TEST_GROUP_H_ +#define _CONTROLLER_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Group */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(controller_tests); + +#endif /* _CONTROLLER_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h new file mode 100644 index 0000000..389ffe5 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h @@ -0,0 +1,11 @@ +#ifndef _CONTROLLER_TESTS_H_ +#define _CONTROLLER_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(pid_reset_tests); +JTEST_DECLARE_GROUP(sin_cos_tests); +JTEST_DECLARE_GROUP(pid_tests); + +#endif /* _CONTROLLER_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h new file mode 100644 index 0000000..2ceb450 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h @@ -0,0 +1,102 @@ +#ifndef _FAST_MATH_TEMPLATES_H_ +#define _FAST_MATH_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "test_templates.h" +#include /* memcpy() */ + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Comparison SNR thresholds for the data types used in transform_tests. + */ +#define FAST_MATH_SNR_THRESHOLD_float32_t 95 +#define FAST_MATH_SNR_THRESHOLD_q31_t 95 +#define FAST_MATH_SNR_THRESHOLD_q15_t 45 + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. + */ +#define FAST_MATH_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + fast_math_output_f32_ref, \ + (output_type *) fast_math_output_ref, \ + fast_math_output_f32_fut, \ + (output_type *) fast_math_output_fut, \ + block_size, \ + output_type, \ + FAST_MATH_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + + +/*--------------------------------------------------------------------------------*/ +/* TEST Templates */ +/*--------------------------------------------------------------------------------*/ + +#define SQRT_TEST_TEMPLATE_ELT1(suffix) \ + \ + JTEST_DEFINE_TEST(arm_sqrt_##suffix##_test, arm_sqrt_##suffix) \ + { \ + uint32_t i; \ + \ + JTEST_COUNT_CYCLES( \ + for(i=0;i /* memcpy() */ + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** +* Comparison SNR thresholds for the data types used in transform_tests. +*/ +#define INTRINSICS_SNR_THRESHOLD_q63_t 120 +#define INTRINSICS_SNR_THRESHOLD_q31_t 95 + +/** +* Compare the outputs from the function under test and the reference +* function using SNR. +*/ +#define INTRINSICS_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + intrinsics_output_f32_ref, \ + (output_type##_t *) intrinsics_output_ref, \ + intrinsics_output_f32_fut, \ + (output_type##_t *) intrinsics_output_fut, \ + block_size, \ + output_type, \ + INTRINSICS_SNR_THRESHOLD_##output_type##_t \ + ); \ + } while (0) + + +/*--------------------------------------------------------------------------------*/ +/* TEST Templates */ +/*--------------------------------------------------------------------------------*/ + +#define INTRINSICS_TEST_TEMPLATE_ELT1(functionName, dataType) \ + \ + JTEST_DEFINE_TEST(functionName##_test, functionName) \ + { \ + uint32_t i; \ + \ + JTEST_COUNT_CYCLES( \ + for(i=0;ipData, \ + ((output_type *) &matrix_output_fut)->pData, \ + ((output_type *) &matrix_output_fut)->numRows * \ + ((output_type *) &matrix_output_ref)->numCols * \ + sizeof(output_content_type)) + +/** + * Comparison SNR thresholds for the data types used in matrix_tests. + */ +#define MATRIX_SNR_THRESHOLD 120 + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. + */ +#define MATRIX_SNR_COMPARE_INTERFACE(output_type, output_content_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + (float32_t *)matrix_output_f32_ref, \ + ((output_type *) &matrix_output_ref)->pData, \ + (float32_t *)matrix_output_f32_fut, \ + ((output_type *) &matrix_output_ref)->pData, \ + ((output_type *) &matrix_output_fut)->numRows * \ + ((output_type *) &matrix_output_ref)->numCols, \ + output_content_type, \ + MATRIX_SNR_THRESHOLD \ + ); \ + } while (0) + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. This is special for float64_t + */ +#define MATRIX_DBL_SNR_COMPARE_INTERFACE(output_type) \ + do \ + { \ + TEST_ASSERT_DBL_SNR( \ + (float64_t *)matrix_output_f32_ref, \ + (float64_t *)matrix_output_f32_fut, \ + ((output_type *) &matrix_output_fut)->numRows * \ + ((output_type *) &matrix_output_ref)->numCols, \ + MATRIX_SNR_THRESHOLD \ + ); \ + } while (0) + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define ARM_mat_add_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut) + +#define REF_mat_add_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_cmplx_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut) + +#define REF_mat_cmplx_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_inverse_INPUT_INTERFACE(input_ptr) \ + PAREN(input_ptr, (void *) &matrix_output_fut) + +#define REF_mat_inverse_INPUT_INTERFACE(input_ptr) \ + PAREN(input_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut) + +#define REF_mat_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_mult_fast_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut) + +#define REF_mat_mult_fast_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_sub_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut) + +#define REF_mat_sub_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_trans_INPUT_INTERFACE(input_ptr) \ + PAREN(input_ptr, (void *) &matrix_output_fut) + +#define REF_mat_trans_INPUT_INTERFACE(input_ptr) \ + PAREN(input_ptr, (void *) &matrix_output_ref) + +/*--------------------------------------------------------------------------------*/ +/* Dimension Validation Interfaces */ +/*--------------------------------------------------------------------------------*/ + +#define MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS(input_type, \ + matrix_a_ptr, \ + matrix_b_ptr) \ + ((((input_type) (matrix_a_ptr))->numRows == \ + ((input_type) (matrix_b_ptr))->numRows) && \ + (((input_type) (matrix_a_ptr))->numCols == \ + ((input_type) (matrix_b_ptr))->numCols)) + +#define MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS(input_type, \ + matrix_a_ptr, \ + matrix_b_ptr) \ + (((input_type) (matrix_a_ptr))->numCols == \ + ((input_type) (matrix_b_ptr))->numRows) + +#define MATRIX_TEST_VALID_SQUARE_DIMENSIONS(input_type, \ + matrix_ptr) \ + (((input_type)(matrix_ptr))->numRows == \ + ((input_type)(matrix_ptr))->numCols) + +#define MATRIX_TEST_VALID_DIMENSIONS_ALWAYS(input_type, \ + matrix_ptr) \ + (1 == 1) \ + +/*--------------------------------------------------------------------------------*/ +/* Output Configuration Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* The matrix tests assume the output matrix is always the correct size. These + * interfaces size the properly size the output matrices according to the input + * matrices and the operation at hand.*/ + +#define MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT(input_type, \ + matrix_a_ptr, \ + matrix_b_ptr) \ + do \ + { \ + ((input_type) &matrix_output_fut)->numRows = \ + ((input_type)(matrix_a_ptr))->numRows; \ + ((input_type) &matrix_output_fut)->numCols = \ + ((input_type)(matrix_a_ptr))->numCols; \ + ((input_type) &matrix_output_ref)->numRows = \ + ((input_type)(matrix_a_ptr))->numRows; \ + ((input_type) &matrix_output_ref)->numCols = \ + ((input_type)(matrix_a_ptr))->numCols; \ + } while (0) + +#define MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT(input_type, \ + matrix_a_ptr, \ + matrix_b_ptr) \ + do \ + { \ + ((input_type) &matrix_output_fut)->numRows = \ + ((input_type)(matrix_a_ptr))->numRows; \ + ((input_type) &matrix_output_fut)->numCols = \ + ((input_type)(matrix_b_ptr))->numCols; \ + ((input_type) &matrix_output_ref)->numRows = \ + ((input_type)(matrix_a_ptr))->numRows; \ + ((input_type) &matrix_output_ref)->numCols = \ + ((input_type)(matrix_b_ptr))->numCols; \ + } while (0) + +#define MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(input_type, \ + matrix_ptr) \ + do \ + { \ + ((input_type) &matrix_output_fut)->numRows = \ + ((input_type)(matrix_ptr))->numRows; \ + ((input_type) &matrix_output_fut)->numCols = \ + ((input_type)(matrix_ptr))->numCols; \ + ((input_type) &matrix_output_ref)->numRows = \ + ((input_type)(matrix_ptr))->numRows; \ + ((input_type) &matrix_output_ref)->numCols = \ + ((input_type)(matrix_ptr))->numCols; \ + } while (0) + +#define MATRIX_TEST_CONFIG_TRANSPOSE_OUTPUT(input_type, \ + matrix_ptr) \ + do \ + { \ + ((input_type) &matrix_output_fut)->numRows = \ + ((input_type)(matrix_ptr))->numCols; \ + ((input_type) &matrix_output_fut)->numCols = \ + ((input_type)(matrix_ptr))->numRows; \ + ((input_type) &matrix_output_ref)->numRows = \ + ((input_type)(matrix_ptr))->numCols; \ + ((input_type) &matrix_output_ref)->numCols = \ + ((input_type)(matrix_ptr))->numRows; \ + } while (0) + +/*--------------------------------------------------------------------------------*/ +/* TEST Templates */ +/*--------------------------------------------------------------------------------*/ + +#define MATRIX_TEST_TEMPLATE_ELT1(arr_desc_inputs, \ + input_type, \ + output_type, output_content_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + output_config_interface, \ + dim_validation_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, input_type, input, arr_desc_inputs \ + , \ + JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", \ + (int)input->numRows, \ + (int)input->numCols); \ + \ + if (dim_validation_interface(input_type, \ + input)) { \ + output_config_interface(input_type, \ + input); \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface(input), \ + ref, ref_arg_interface(input)); \ + compare_interface(output_type, \ + output_content_type); \ + } else { \ + arm_status matrix_test_retval; \ + TEST_CALL_FUT( \ + matrix_test_retval = fut, \ + fut_arg_interface(input)); \ + \ + /* If dimensions are known bad, the fut should */ \ + /* detect it. */ \ + if ( matrix_test_retval != ARM_MATH_SIZE_MISMATCH) { \ + return JTEST_TEST_FAILED; \ + } \ + }); \ + return JTEST_TEST_PASSED; \ + } while (0) + + +#define MATRIX_TEST_TEMPLATE_ELT2(arr_desc_inputs_a, \ + arr_desc_inputs_b, \ + input_type, \ + output_type, output_content_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + output_config_interface, \ + dim_validation_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_a_idx, input_type, input_a, arr_desc_inputs_a \ + , \ + input_type input_b = ARR_DESC_ELT( \ + input_type, input_a_idx, \ + &(arr_desc_inputs_b)); \ + \ + JTEST_DUMP_STRF("Matrix Dimensions: A %dx%d B %dx%d\n", \ + (int)input_a->numRows, \ + (int)input_a->numCols, \ + (int)input_b->numRows, \ + (int)input_b->numCols); \ + \ + if (dim_validation_interface(input_type, \ + input_a, \ + input_b)) { \ + \ + output_config_interface(input_type, \ + input_a, \ + input_b); \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface(input_a, input_b), \ + ref, ref_arg_interface(input_a, input_b)); \ + \ + compare_interface(output_type, output_content_type); \ + \ + } else { \ + arm_status matrix_test_retval; \ + TEST_CALL_FUT( \ + matrix_test_retval = fut, fut_arg_interface(input_a, input_b)); \ + \ + /* If dimensions are known bad, the fut should */ \ + /* detect it. */ \ + if ( matrix_test_retval != ARM_MATH_SIZE_MISMATCH) { \ + return JTEST_TEST_FAILED; \ + } \ + }); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Specialization of #MATRIX_TEST_TEMPLATE_ELT2() for matrix tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define MATRIX_DEFINE_TEST_TEMPLATE_ELT2(fn_name, suffix, \ + output_config_interface, \ + dim_validation_interface, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + MATRIX_TEST_TEMPLATE_ELT2( \ + matrix_##suffix##_a_inputs, \ + matrix_##suffix##_b_inputs, \ + arm_matrix_instance_##suffix * , \ + arm_matrix_instance_##suffix, \ + TYPE_FROM_ABBREV(suffix), \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + output_config_interface, \ + dim_validation_interface, \ + comparison_interface); \ + } \ + +/** + * Specialization of #MATRIX_TEST_TEMPLATE_ELT1() for matrix tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define MATRIX_DEFINE_TEST_TEMPLATE_ELT1(fn_name, suffix, \ + output_config_interface, \ + dim_validation_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + MATRIX_TEST_TEMPLATE_ELT1( \ + matrix_##suffix##_a_inputs, \ + arm_matrix_instance_##suffix * , \ + arm_matrix_instance_##suffix, \ + TYPE_FROM_ABBREV(suffix), \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + output_config_interface, \ + dim_validation_interface, \ + MATRIX_COMPARE_INTERFACE); \ + } \ + + +#endif /* _MATRIX_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h new file mode 100644 index 0000000..f96cc15 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h @@ -0,0 +1,54 @@ +#ifndef _MATRIX_TEST_DATA_H_ +#define _MATRIX_TEST_DATA_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" +#include "arm_math.h" /* float32_t */ + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ +#define MATRIX_TEST_MAX_ROWS 4 +#define MATRIX_TEST_MAX_COLS 4 +#define MATRIX_TEST_BIGGEST_INPUT_TYPE float64_t +#define MATRIX_TEST_MAX_ELTS (MATRIX_TEST_MAX_ROWS * MATRIX_TEST_MAX_COLS) +#define MATRIX_MAX_COEFFS_LEN 16 +#define MATRIX_MAX_SHIFTS_LEN 5 + +/** + * Declare the matrix inputs defined by MATRIX_DEFINE_INPUTS. + */ +#define MATRIX_DECLARE_INPUTS(suffix) \ + ARR_DESC_DECLARE(matrix_##suffix##_a_inputs); \ + ARR_DESC_DECLARE(matrix_##suffix##_b_inputs); \ + ARR_DESC_DECLARE(matrix_##suffix##_invertible_inputs) + + +/*--------------------------------------------------------------------------------*/ +/* Declare Variables */ +/*--------------------------------------------------------------------------------*/ + +/* Input/Output Buffers */ +extern arm_matrix_instance_f32 matrix_output_fut; +extern arm_matrix_instance_f32 matrix_output_ref; +extern arm_matrix_instance_f64 matrix_output_fut64; +extern arm_matrix_instance_f64 matrix_output_ref64; +extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_fut[MATRIX_TEST_MAX_ELTS]; +extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_ref[MATRIX_TEST_MAX_ELTS]; +extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_scratch[MATRIX_TEST_MAX_ELTS]; + +/* Matrix Inputs */ +MATRIX_DECLARE_INPUTS(f64); +MATRIX_DECLARE_INPUTS(f32); +MATRIX_DECLARE_INPUTS(q31); +MATRIX_DECLARE_INPUTS(q15); + +extern const float32_t matrix_f32_scale_values[MATRIX_MAX_COEFFS_LEN]; +extern const q31_t matrix_q31_scale_values[MATRIX_MAX_COEFFS_LEN]; +extern const q15_t matrix_q15_scale_values[MATRIX_MAX_COEFFS_LEN]; +extern const int32_t matrix_shift_values[MATRIX_MAX_SHIFTS_LEN]; + +#endif /* _MATRIX_TEST_DATA_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h new file mode 100644 index 0000000..3c92eb1 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h @@ -0,0 +1,9 @@ +#ifndef _MATRIX_TEST_GROUP_H_ +#define _MATRIX_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(matrix_tests); + +#endif /* _MATRIX_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h new file mode 100644 index 0000000..3d0ed9c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h @@ -0,0 +1,17 @@ +#ifndef _MATRIX_TESTS_H_ +#define _MATRIX_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(mat_add_tests); +JTEST_DECLARE_GROUP(mat_cmplx_mult_tests); +JTEST_DECLARE_GROUP(mat_init_tests); +JTEST_DECLARE_GROUP(mat_inverse_tests); +JTEST_DECLARE_GROUP(mat_mult_tests); +JTEST_DECLARE_GROUP(mat_mult_fast_tests); +JTEST_DECLARE_GROUP(mat_sub_tests); +JTEST_DECLARE_GROUP(mat_trans_tests); +JTEST_DECLARE_GROUP(mat_scale_tests); + +#endif /* _MATRIX_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h new file mode 100644 index 0000000..de96f88 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h @@ -0,0 +1,157 @@ +#ifndef _STATISTICS_TEMPLATES_H_ +#define _STATISTICS_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "test_templates.h" + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Compare the outputs from the function under test and the reference function. + */ +#define STATISTICS_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_ASSERT_BUFFERS_EQUAL( \ + statistics_output_ref.data_ptr, \ + statistics_output_fut.data_ptr, \ + 1 * sizeof(output_type) /* All fns return one value*/ \ + ); \ + TEST_ASSERT_EQUAL( \ + statistics_idx_fut, \ + statistics_idx_ref); \ + } while (0) \ + +/* + * Comparison SNR thresholds for the data types used in statistics_tests. + */ +#define STATISTICS_SNR_THRESHOLD_float32_t 120 +#define STATISTICS_SNR_THRESHOLD_q31_t 100 +#define STATISTICS_SNR_THRESHOLD_q15_t 60 +#define STATISTICS_SNR_THRESHOLD_q7_t 30 + +/** + * Compare reference and fut outputs using SNR. + * + * @note The outputs are converted to float32_t before comparison. + */ +#define STATISTICS_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + statistics_output_f32_ref, \ + statistics_output_ref.data_ptr, \ + statistics_output_f32_fut, \ + statistics_output_fut.data_ptr, \ + 1, /* All fns return one element*/ \ + output_type, \ + STATISTICS_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + + + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define ARM_max_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, \ + statistics_output_fut.data_ptr, &statistics_idx_fut) + +#define REF_max_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, \ + statistics_output_ref.data_ptr, &statistics_idx_ref) + +#define ARM_mean_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_fut.data_ptr) + +#define REF_mean_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_ref.data_ptr) + +#define ARM_min_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, \ + statistics_output_fut.data_ptr, &statistics_idx_fut) + +#define REF_min_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, \ + statistics_output_ref.data_ptr, &statistics_idx_ref) + +#define ARM_power_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_fut.data_ptr) + +#define REF_power_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_ref.data_ptr) + +#define ARM_rms_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_fut.data_ptr) + +#define REF_rms_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_ref.data_ptr) + +#define ARM_std_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_fut.data_ptr) + +#define REF_std_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_ref.data_ptr) + +#define ARM_var_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_fut.data_ptr) + +#define REF_var_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_ref.data_ptr) + + +/*--------------------------------------------------------------------------------*/ +/* Test Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Specialization of #TEST_TEMPLATE_BUF1_BLK() for statistics tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_BLK( \ + statistics_f_all, \ + statistics_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + + +#endif /* _STATISTICS_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h new file mode 100644 index 0000000..2dfcc97 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h @@ -0,0 +1,44 @@ +#ifndef _STATISTICS_TEST_DATA_H_ +#define _STATISTICS_TEST_DATA_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" +#include "arm_math.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ +#define STATISTICS_MAX_INPUT_ELEMENTS 32 +#define STATISTICS_BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Declare Variables */ +/*--------------------------------------------------------------------------------*/ + +/* Input/Output Buffers */ +ARR_DESC_DECLARE(statistics_output_fut); +ARR_DESC_DECLARE(statistics_output_ref); +extern uint32_t statistics_idx_fut; +extern uint32_t statistics_idx_ref; + +extern STATISTICS_BIGGEST_INPUT_TYPE +statistics_output_f32_ref[STATISTICS_MAX_INPUT_ELEMENTS]; + +extern STATISTICS_BIGGEST_INPUT_TYPE +statistics_output_f32_fut[STATISTICS_MAX_INPUT_ELEMENTS]; + + +/* Block Sizes */ +ARR_DESC_DECLARE(statistics_block_sizes); + +/* Float Inputs */ +ARR_DESC_DECLARE(statistics_zeros); +ARR_DESC_DECLARE(statistics_f_2); +ARR_DESC_DECLARE(statistics_f_15); +ARR_DESC_DECLARE(statistics_f_32); +ARR_DESC_DECLARE(statistics_f_all); + +#endif /* _STATISTICS_TEST_DATA_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h new file mode 100644 index 0000000..133cfea --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h @@ -0,0 +1,9 @@ +#ifndef _STATISTICS_TEST_GROUP_H_ +#define _STATISTICS_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(statistics_tests); + +#endif /* _STATISTICS_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_tests.h new file mode 100644 index 0000000..489d2a7 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_tests.h @@ -0,0 +1,15 @@ +#ifndef _STATISTICS_TESTS_H_ +#define _STATISTICS_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(max_tests); +JTEST_DECLARE_GROUP(mean_tests); +JTEST_DECLARE_GROUP(min_tests); +JTEST_DECLARE_GROUP(power_tests); +JTEST_DECLARE_GROUP(rms_tests); +JTEST_DECLARE_GROUP(std_tests); +JTEST_DECLARE_GROUP(var_tests); + +#endif /* _STATISTICS_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_templates.h new file mode 100644 index 0000000..9ca4874 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_templates.h @@ -0,0 +1,120 @@ +#ifndef _SUPPORT_TEMPLATES_H_ +#define _SUPPORT_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "test_templates.h" + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Compare the outputs from the function under test and the reference function. + */ +#define SUPPORT_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_ASSERT_BUFFERS_EQUAL( \ + support_output_ref.data_ptr, \ + support_output_fut.data_ptr, \ + block_size * sizeof(output_type)); \ + } while (0) \ + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define ARM_copy_INPUT_INTERFACE(input, block_size) \ + PAREN(input, support_output_fut.data_ptr, block_size) + +#define REF_copy_INPUT_INTERFACE(input, block_size) \ + PAREN(input, support_output_ref.data_ptr, block_size) + +#define ARM_fill_INPUT_INTERFACE(elt, block_size) \ + PAREN(elt, support_output_fut.data_ptr, block_size) + +#define REF_fill_INPUT_INTERFACE(elt, block_size) \ + PAREN(elt, support_output_ref.data_ptr, block_size) + +#define ARM_x_to_y_INPUT_INTERFACE(input, block_size) \ + PAREN(input, support_output_fut.data_ptr, block_size) + +#define REF_x_to_y_INPUT_INTERFACE(input, block_size) \ + PAREN(input, support_output_ref.data_ptr, block_size) + +/*--------------------------------------------------------------------------------*/ +/* Test Templates */ +/*--------------------------------------------------------------------------------*/ + + +/** + * Specialization of #TEST_TEMPLATE_BUF1_BLK() for support tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define SUPPORT_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_BLK( \ + support_f_all, \ + support_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + +/** + * Specialization of #TEST_TEMPLATE_ELT1_BLK() for support tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define SUPPORT_DEFINE_TEST_TEMPLATE_ELT1_BLK(fn_name, \ + suffix, \ + elt_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_ELT1_BLK( \ + support_elts, \ + support_block_sizes, \ + elt_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + +#endif /* _SUPPORT_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_data.h new file mode 100644 index 0000000..52b6d77 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_data.h @@ -0,0 +1,31 @@ +#ifndef ARM_SUPPORT_TEST_DATA_H +#define ARM_SUPPORT_TEST_DATA_H + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" + +/*--------------------------------------------------------------------------------*/ +/* Declare Variables */ +/*--------------------------------------------------------------------------------*/ + +/* Input/Output Buffers */ +ARR_DESC_DECLARE(support_output_fut); +ARR_DESC_DECLARE(support_output_ref); + +/* Block Sizes*/ +ARR_DESC_DECLARE(support_block_sizes); + +/* Numbers */ +ARR_DESC_DECLARE(support_elts); + +/* Float Inputs */ +ARR_DESC_DECLARE(support_zeros); +ARR_DESC_DECLARE(support_f_2); +ARR_DESC_DECLARE(support_f_15); +ARR_DESC_DECLARE(support_f_32); +ARR_DESC_DECLARE(support_f_all); + +#endif diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h new file mode 100644 index 0000000..5a50ae1 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h @@ -0,0 +1,9 @@ +#ifndef _SUPPORT_TEST_GROUP_H_ +#define _SUPPORT_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(support_tests); + +#endif /* _SUPPORT_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h new file mode 100644 index 0000000..66cc538 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h @@ -0,0 +1,11 @@ +#ifndef _SUPPORT_TESTS_H_ +#define _SUPPORT_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(copy_tests); +JTEST_DECLARE_GROUP(fill_tests); +JTEST_DECLARE_GROUP(x_to_y_tests); + +#endif /* _SUPPORT_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h new file mode 100644 index 0000000..15d0b79 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h @@ -0,0 +1,88 @@ +#ifndef _TEMPLATE_H_ +#define _TEMPLATE_H_ + +/*--------------------------------------------------------------------------------*/ +/* Looping and Iteration */ +/*--------------------------------------------------------------------------------*/ + +/** + * Template for the general structure of a loop. + */ +#define TEMPLATE_LOOP(setup, loop_def, body) \ + do \ + { \ + setup; \ + loop_def { \ + body; \ + } \ + } while (0) + +/** + * Template for looping over an array-like sequence. + */ +#define TEMPLATE_DO_ARR_LIKE(iter_idx, type, \ + arr, arr_length, \ + iter_elem_setup, \ + body) \ + do \ + { \ + TEMPLATE_LOOP( \ + int iter_idx, \ + for(iter_idx = 0; iter_idx < (arr_length); ++iter_idx), \ + iter_elem_setup; \ + body); \ + } while (0) + +/** + * Template for looping over the contents of an array. + */ +#define TEMPLATE_DO_ARR(iter_idx, type, iter_elem, arr, arr_length, body) \ + do \ + { \ + TEMPLATE_DO_ARR_LIKE( \ + iter_idx, type, arr, arr_length, \ + type iter_elem = (arr)[iter_idx], \ + body); \ + } while (0) + +/** + * Template for looping over the contents of an #ARR_DESC. + */ +#define TEMPLATE_DO_ARR_DESC(iter_idx, type, iter_elem, arr_desc, body) \ + do \ + { \ + TEMPLATE_DO_ARR_LIKE( \ + iter_idx, type, arr_desc, (arr_desc).element_count, \ + type iter_elem = ARR_DESC_ELT(type, iter_idx, &(arr_desc)), \ + body); \ + } while (0) + +/*--------------------------------------------------------------------------------*/ +/* Test Definition */ +/*--------------------------------------------------------------------------------*/ + +/** + * Template for the general structure of a test. + */ +#define TEMPLATE_TEST(setup, body, teardown) \ + do \ + { \ + setup; \ + body; \ + teardown; \ + } while (0) + +/** + * Template for calling a function. + * + * @note Surround function arguments with the #PAREN() macro. + * + * @example + * void my_func(int arg1, int arg2); + * + * TEMPLATE_CALL_FN(my_func, PAREN(3, 7)); + */ +#define TEMPLATE_CALL_FN(fn, fn_args) \ + fn fn_args + +#endif /* _TEMPLATE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h new file mode 100644 index 0000000..3badc80 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h @@ -0,0 +1,466 @@ +#ifndef _TEST_TEMPLATES_H_ +#define _TEST_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ +#include "template.h" +#include /* memcmp() */ +#include /* PRIu32 */ +#include "math_helper.h" /* arm_snr_f32() */ + +/*--------------------------------------------------------------------------------*/ +/* Function Aliases for use in Templates. */ +/*--------------------------------------------------------------------------------*/ +#define ref_q31_t_to_float ref_q31_to_float +#define ref_q15_t_to_float ref_q15_to_float +#define ref_q7_t_to_float ref_q7_to_float +#define ref_float_to_q31_t ref_float_to_q31 +#define ref_float_to_q15_t ref_float_to_q15 +#define ref_float_to_q7_t ref_float_to_q7 +#define ref_float32_t_to_float ref_copy_f32 +#define ref_float_to_float32_t ref_copy_f32 + + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Call the function-under-test. + */ +#define TEST_CALL_FUT(fut, fut_args) \ + JTEST_COUNT_CYCLES(TEMPLATE_CALL_FN(fut, fut_args)) + +/** + * Call the reference-function. + */ +#define TEST_CALL_REF(ref, ref_args) \ + TEMPLATE_CALL_FN(ref, ref_args) + +/** + * Call the function-under-test and the reference-function. + */ +#define TEST_CALL_FUT_AND_REF(fut, fut_args, ref, ref_args) \ + do { \ + TEST_CALL_FUT(fut, fut_args); \ + TEST_CALL_REF(ref, ref_args); \ + } while (0) + +/** + * This macro eats a variable number of arguments and evaluates to a null + * statement. + */ +#define TEST_NULL_STATEMENT(...) (void) "TEST_NULL_STATEMENT" + +/** + * A function name, Usable in any template where a fut or ref name is accepted, + * that evaluates to a #TEST_NULL_STATEMENT(). + */ +#define TEST_NULL_FN TEST_NULL_STATEMENT + +/** + * Assert that buffers A and B are byte-equivalent for a number of bytes. + */ + +#define TEST_ASSERT_BUFFERS_EQUAL(buf_a, buf_b, bytes)\ + do \ + { \ + if (memcmp(buf_a, buf_b, bytes) != 0) \ + { \ + return JTEST_TEST_FAILED; \ + } \ + } while (0) + + + + +/** + * Assert that the two entities are equal. + */ +#define TEST_ASSERT_EQUAL(a, b) \ + do \ + { \ + if ((a) != (b)) \ + { \ + return JTEST_TEST_FAILED;\ + } \ + } while (0) + +/** + * Convert elements to from src_type to float. + */ +#define TEST_CONVERT_TO_FLOAT(src_ptr, dst_ptr, block_size, src_type) \ + do \ + { \ + ref_##src_type##_to_float( \ + src_ptr, \ + dst_ptr, \ + block_size); \ + } while (0) \ + +/** + * Convert elements to from float to dst_type . + */ +#define TEST_CONVERT_FLOAT_TO(src_ptr, dst_ptr, block_size, dst_type) \ + do \ + { \ + ref_float_to_##dst_type( \ + src_ptr, \ + dst_ptr, \ + block_size); \ + } while (0) \ + +/** + * Assert that the SNR between a reference and test sample is above a given + * threshold. + */ + +#define TEST_ASSERT_SNR(ref_ptr, tst_ptr, block_size, threshold) \ + do \ + { \ + float32_t snr = arm_snr_f32(ref_ptr, tst_ptr, block_size);\ + if ( snr <= threshold) \ + { \ + JTEST_DUMP_STRF("SNR: %f\n", snr); \ + return JTEST_TEST_FAILED; \ + } \ + } while (0) + + +/** + * Assert that the SNR between a reference and test sample is above a given + * threshold. Special case for float64_t + */ + +#define TEST_ASSERT_DBL_SNR(ref_ptr, tst_ptr, block_size, threshold)\ + do \ + { \ + float64_t snr = arm_snr_f64(ref_ptr, tst_ptr, block_size); \ + if ( snr <= threshold) \ + { \ + JTEST_DUMP_STRF("SNR: %f\n", snr); \ + return JTEST_TEST_FAILED; \ + } \ + } while (0) + + +/** + * Compare test and reference elements by converting to float and + * calculating an SNR. + * + * This macro is a merger of the #TEST_CONVERT_TO_FLOAT() and + * #TEST_ASSERT_SNR() macros. + */ +#define TEST_CONVERT_AND_ASSERT_SNR(ref_dst_ptr, ref_src_ptr, \ + tst_dst_ptr, tst_src_ptr, \ + block_size, \ + tst_src_type, \ + threshold) \ + do \ + { \ + TEST_CONVERT_TO_FLOAT(ref_src_ptr, \ + ref_dst_ptr, \ + block_size, \ + tst_src_type); \ + TEST_CONVERT_TO_FLOAT(tst_src_ptr, \ + tst_dst_ptr, \ + block_size, \ + tst_src_type); \ + TEST_ASSERT_SNR(ref_dst_ptr, \ + tst_dst_ptr, \ + block_size, \ + threshold); \ + } while (0) + +/** + * Execute statements only if the combination of block size, function type + * specifier, and input ARR_DESC_t are valid. + * + * @example An ARR_DESC_t that contains 64 bytes cant service a 32 element + * block size if they are extracted in float32_t increments. + * + * 8 * 32 = 256 > 64. + */ +#define TEST_DO_VALID_BLOCKSIZE(block_size, fn_type_spec, \ + input_arr_desc, body) \ + do \ + { \ + if (block_size * sizeof(fn_type_spec) <= \ + ARR_DESC_BYTES(input_arr_desc)) \ + { \ + JTEST_DUMP_STRF("Block Size: %"PRIu32"\n", block_size); \ + body; \ + } \ + } while (0) \ + +/** + * Template for tests that rely on one input buffer and a blocksize parameter. + * + * The buffer is an #ARR_DESC_t. It is iterated over and it's values are + * passed to the function under test and reference functions through their + * appropriate argument interfaces. The argument interfaces this template to + * execute structurally similar functions. + * + */ +#define TEST_TEMPLATE_BUF1_BLK(arr_desc_inputs, \ + arr_desc_block_sizes, \ + input_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \ + , \ + TEMPLATE_DO_ARR_DESC( \ + block_size_idx, uint32_t, block_size, arr_desc_block_sizes \ + , \ + void * input_data_ptr = input_ptr->data_ptr; \ + \ + TEST_DO_VALID_BLOCKSIZE( \ + block_size, input_type, input_ptr \ + , \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_data_ptr, block_size), \ + ref, ref_arg_interface( \ + input_data_ptr, block_size)); \ + \ + compare_interface(block_size, output_type)))); \ + \ + return JTEST_TEST_PASSED; \ + \ + } while (0) + +/** + * Template for tests that rely on an input buffer and an element. + * + * An element can is any thing which doesn't walk and talk like a + * sequence. Examples include numbers, and structures. + */ +#define TEST_TEMPLATE_BUF1_ELT1(arr_desc_inputs, \ + arr_desc_elts, \ + input_type, elt_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \ + , \ + TEMPLATE_DO_ARR_DESC( \ + elt_idx, elt_type, elt, arr_desc_elts \ + , \ + void * input_data_ptr = input_ptr->data_ptr; \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface(input_data_ptr, elt), \ + ref, ref_arg_interface(input_data_ptr, elt)); \ + \ + compare_interface(output_type))); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Template for tests that rely on an input buffer, an element, and a blocksize + * parameter. + */ +#define TEST_TEMPLATE_BUF1_ELT1_BLK(arr_desc_inputs, \ + arr_desc_elts, \ + arr_desc_block_sizes, \ + input_type, elt_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface); \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + inut_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \ + , \ + TEMPLATE_DO_ARR_DESC( \ + block_size_idx, uint32_t, block_size, \ + arr_desc_block_sizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + elt_idx, elt_type, elt, arr_desc_elts \ + , \ + void * input_data_ptr = input_ptr->data_ptr; \ + TEST_DO_VALID_BLOCKSIZE( \ + block_size, input_type, input_ptr, \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_data_ptr, elt, block_size), \ + ref, ref_arg_interface( \ + input_data_ptr, elt, block_size)); \ + compare_interface(block_size, output_type))))); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Template for tests that rely on an input buffer, two elements, and a blocksize + * parameter. + */ +#define TEST_TEMPLATE_BUF1_ELT2_BLK(arr_desc_inputs, \ + arr_desc_elt1s, \ + arr_desc_elt2s, \ + arr_desc_block_sizes, \ + input_type, elt1_type, \ + elt2_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + inut_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \ + , \ + TEMPLATE_DO_ARR_DESC( \ + block_size_idx, uint32_t, block_size, \ + arr_desc_block_sizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + elt1_idx, elt1_type, elt1, arr_desc_elt1s \ + , \ + TEMPLATE_DO_ARR_DESC( \ + elt2_idx, elt2_type, elt2, arr_desc_elt2s \ + , \ + void * input_data_ptr = input_ptr->data_ptr; \ + TEST_DO_VALID_BLOCKSIZE( \ + block_size, input_type, input_ptr, \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_data_ptr, elt1, elt2, block_size), \ + ref, ref_arg_interface( \ + input_data_ptr, elt1, elt2, block_size)); \ + compare_interface(block_size, output_type)))))); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Template for tests that rely on two input buffers and a blocksize parameter. + * + * The two #ARR_DESC_t, input buffers are iterated through in parallel. The + * length of the first #ARR_DESC_t determines the length of the iteration. + */ +#define TEST_TEMPLATE_BUF2_BLK(arr_desc_inputs_a, \ + arr_desc_inputs_b, \ + arr_desc_block_sizes, \ + input_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + /* Iterate over two input arrays in parallel.*/ \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs_a \ + , \ + TEMPLATE_DO_ARR_DESC( \ + block_size_idx, uint32_t, block_size, arr_desc_block_sizes, \ + void * input_a_ptr = input_ptr->data_ptr; \ + void * input_b_ptr = ARR_DESC_ELT( \ + ARR_DESC_t *, input_idx, \ + &(arr_desc_inputs_b))->data_ptr; \ + \ + TEST_DO_VALID_BLOCKSIZE( \ + block_size, input_type, input_ptr \ + , \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_a_ptr, input_b_ptr, block_size), \ + ref, ref_arg_interface( \ + input_a_ptr, input_b_ptr, block_size)); \ + \ + compare_interface(block_size, output_type)))); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Test template that uses a single element. + */ +#define TEST_TEMPLATE_ELT1(arr_desc_elts, \ + elt_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + elt_idx, elt_type, elt, arr_desc_elts \ + , \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + elt), \ + ref, ref_arg_interface( \ + elt)); \ + /* Comparison interfaces typically accept */ \ + /* a block_size. Pass a dummy value 1.*/ \ + compare_interface(1, output_type)); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Test template that iterates over two sets of elements in parallel. + * + * The length of the first set determines the number of iteratsions. + */ +#define TEST_TEMPLATE_ELT2(arr_desc_elts_a, \ + arr_desc_elts_b, \ + elt_a_type, elt_b_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + elt_a_idx, elt_a_type, elt_a, arr_desc_elts_a \ + , \ + elt_b_type * elt_b = ARR_DESC_ELT( \ + elt_b_type, \ + elt_a_idx, \ + arr_desc_elts_b); \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + elt_a, elt_b), \ + ref, ref_arg_interface( \ + elt_a, elt_b)); \ + /* Comparison interfaces typically accept */ \ + /* a block_size. Pass a dummy value 1.*/ \ + compare_interface(1, output_type)); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Test template that uses an element and a block size. + */ +#define TEST_TEMPLATE_ELT1_BLK(arr_desc_elts, \ + arr_desc_block_sizes, \ + elt_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + block_size_idx, uint32_t, block_size, \ + arr_desc_block_sizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + elt_idx, elt_type, elt, arr_desc_elts \ + , \ + JTEST_DUMP_STRF("Block Size: %d\n", \ + (int)block_size); \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + elt, block_size), \ + ref, ref_arg_interface( \ + elt, block_size)); \ + compare_interface(block_size, output_type))); \ + return JTEST_TEST_PASSED; \ + } while (0) + +#endif /* _TEST_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h new file mode 100644 index 0000000..abe75f9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h @@ -0,0 +1,181 @@ +#ifndef _TRANSFORM_TEMPLATES_H_ +#define _TRANSFORM_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "test_templates.h" +#include /* memcpy() */ + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Comparison SNR thresholds for the data types used in transform_tests. + */ +#define TRANSFORM_SNR_THRESHOLD_float32_t 90 +#define TRANSFORM_SNR_THRESHOLD_q31_t 90 +#define TRANSFORM_SNR_THRESHOLD_q15_t 30 + +#define DCT4_TRANSFORM_SNR_THRESHOLD_float32_t 80 +#define DCT4_TRANSFORM_SNR_THRESHOLD_q31_t 75 +#define DCT4_TRANSFORM_SNR_THRESHOLD_q15_t 11 + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. + */ +#define TRANSFORM_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + transform_fft_output_f32_ref, \ + (output_type *) transform_fft_output_ref, \ + transform_fft_output_f32_fut, \ + (output_type *) transform_fft_output_fut, \ + block_size, \ + output_type, \ + TRANSFORM_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. + */ +#define DCT_TRANSFORM_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + transform_fft_output_f32_ref, \ + (output_type *) transform_fft_output_ref, \ + transform_fft_output_f32_fut, \ + (output_type *) transform_fft_output_fut, \ + block_size, \ + output_type, \ + DCT4_TRANSFORM_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) \ + +/** + * Specialization on #TRANSFORM_SNR_COMPARE_INTERFACE() to fix the block_size + * for complex datasets. + */ +#define TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE(block_size, output_type) \ + /* Complex numbers have two components*/ \ + TRANSFORM_SNR_COMPARE_INTERFACE(block_size * 2, output_type ) + +/** + * This macro copys data from the input_ptr into input arrays. + * + * Some functions modify their input data; in order to provide the same data to + * multiple tests, copies must be made so the changes from one function don't + * impact the others. + */ +#define TRANSFORM_COPY_INPUTS(input_ptr, \ + bytes) \ + do \ + { \ + memcpy( \ + transform_fft_input_fut, \ + input_ptr, \ + bytes); \ + memcpy( \ + transform_fft_input_ref, \ + input_ptr, \ + bytes); \ + } while (0) + +/** + * This macro copys data from the input_ptr into input arrays. It also creates + * symmetric input data for rfft inverse. + * + * The 4.534234f just makes the middle entry of the array semi random. It's + * actual value doesn't seem to matter much. + * + * Some functions modify their input data; in order to provide the same data to + * multiple tests, copies must be made so the changes from one function don't + * impact the others. + */ +#define TRANSFORM_PREPARE_INVERSE_INPUTS(input_ptr, \ + fftlen, input_type, bytes) \ + do \ + { \ + uint32_t i; \ + \ + memcpy( \ + transform_fft_input_fut, \ + input_ptr, \ + bytes); \ + \ + ((input_type*)transform_fft_input_fut)[1] = 0; \ + ((input_type*)transform_fft_input_fut)[fftlen + 0] = 0; \ + ((input_type*)transform_fft_input_fut)[fftlen + 1] = 0; \ + for(i=1;i>= 1; \ + *((type*)transform_fft_inplace_input_ref + i) >>= 1;} \ + } while (0) + +/** + * This macro copys data from the input_ptr into the in-place input arrays. + * + * Some functions modify their input data; in order to provide the same data to + * multiple tests, copies must be made so the changes from one function don't + * impact the others. + */ +#define TRANSFORM_PREPARE_INPLACE_INPUTS(input_ptr, \ + bytes) \ + do \ + { \ + memcpy( \ + transform_fft_inplace_input_fut, \ + input_ptr, \ + bytes); \ + memcpy( \ + transform_fft_inplace_input_ref, \ + input_ptr, \ + bytes); \ + } while (0) + + +#endif /* _TRANSFORM_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h new file mode 100644 index 0000000..d80c8a2 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h @@ -0,0 +1,48 @@ +#ifndef _TRANSFORM_TEST_DATA_H_ +#define _TRANSFORM_TEST_DATA_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" +#include "arm_math.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +#define TRANSFORM_MAX_FFT_LEN 4096 +#define TRANFORM_BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Variable Declarations */ +/*--------------------------------------------------------------------------------*/ + +/* Lengths are multiplied by 2 to accomodate complex numbers*/ +extern float32_t transform_fft_output_fut[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t transform_fft_output_ref[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t transform_fft_input_fut[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t transform_fft_input_ref[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t transform_fft_output_f32_fut[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t transform_fft_output_f32_ref[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t * transform_fft_inplace_input_fut; +extern float32_t * transform_fft_inplace_input_ref; +extern float32_t transform_fft_f32_inputs[TRANSFORM_MAX_FFT_LEN * 2]; +extern q31_t transform_fft_q31_inputs[TRANSFORM_MAX_FFT_LEN * 2]; +extern q15_t * transform_fft_q15_inputs; +extern q15_t dct4_transform_fft_q15_inputs[TRANSFORM_MAX_FFT_LEN * 2]; + +/* FFT Lengths */ +ARR_DESC_DECLARE(transform_radix2_fftlens); +ARR_DESC_DECLARE(transform_radix4_fftlens); +ARR_DESC_DECLARE(transform_rfft_fftlens); +ARR_DESC_DECLARE(transform_rfft_fast_fftlens); +ARR_DESC_DECLARE(transform_dct_fftlens); + +/* CFFT Structs */ +ARR_DESC_DECLARE(transform_cfft_f32_structs); +ARR_DESC_DECLARE(transform_cfft_q31_structs); +ARR_DESC_DECLARE(transform_cfft_q15_structs); + +#endif /* _TRANSFORM_TEST_DATA_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h new file mode 100644 index 0000000..4720efc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h @@ -0,0 +1,9 @@ +#ifndef _TRANSFORM_TEST_GROUP_H_ +#define _TRANSFORM_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(transform_tests); + +#endif /* _TRANSFORM_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h new file mode 100644 index 0000000..773b6f2 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h @@ -0,0 +1,13 @@ +#ifndef _TRANSFORM_TESTS_H_ +#define _TRANSFORM_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(cfft_tests); +JTEST_DECLARE_GROUP(cfft_family_tests); +JTEST_DECLARE_GROUP(dct4_tests); +JTEST_DECLARE_GROUP(rfft_tests); +JTEST_DECLARE_GROUP(rfft_fast_tests); + +#endif /* _TRANSFORM_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h new file mode 100644 index 0000000..f59f921 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h @@ -0,0 +1,37 @@ +#ifndef _TYPE_ABBREV_H_ +#define _TYPE_ABBREV_H_ + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Expand the abbreviation for a type into the type itself. + */ +#define TYPE_FROM_ABBREV(abbrev) \ + TYPE_ABBREV_##abbrev \ + +/** + * Expand the type to an abbreviation for that type. + * + * Inverse of #TYPE_FROM_ABBREV(). + * + * @note Should be able to get a type back by writing. + * TYPE_FROM_ABBREV(ABBREV_FROM_TYPE(type)) + */ +#define ABBREV_FROM_TYPE(type) \ + TYPE_SUFFIX_##type + +#define TYPE_ABBREV_f64 float64_t +#define TYPE_ABBREV_f32 float32_t +#define TYPE_ABBREV_q31 q31_t +#define TYPE_ABBREV_q15 q15_t +#define TYPE_ABBREV_q7 q7_t + +#define TYPE_SUFFIX_float64_t f64 +#define TYPE_SUFFIX_float32_t f32 +#define TYPE_SUFFIX_q31_t q31 +#define TYPE_SUFFIX_q15_t q15 +#define TYPE_SUFFIX_q7_t q7 + +#endif /* _TYPE_ABBREV_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c new file mode 100644 index 0000000..1557e71 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c @@ -0,0 +1,52 @@ +/*---------------------------------------------------------------------------- + * Name: Retarget.c + * Purpose: 'Retarget' layer for target-dependent low level functions + * Note(s): + *---------------------------------------------------------------------------- + * This file is part of the uVision/ARM development tools. + * This software may only be used under the terms of a valid, current, + * end user licence from KEIL for a compatible version of KEIL software + * development tools. Nothing else gives you the right to use this software. + * + * This software is supplied "AS IS" without warranties of any kind. + * + * Copyright (c) 2011 Keil - An ARM Company. All rights reserved. + *----------------------------------------------------------------------------*/ + +#include +#include +#include "Serial.h" + +#pragma import(__use_no_semihosting_swi) + + + +struct __FILE { int handle; /* Add whatever you need here */ }; +FILE __stdout; +FILE __stdin; + + +int fputc(int c, FILE *f) { + return (SER_PutChar(c)); +} + + +int fgetc(FILE *f) { + return (SER_GetChar()); +} + + +int ferror(FILE *f) { + /* Your implementation of ferror */ + return EOF; +} + + +void _ttywrch(int c) { + SER_PutChar(c); +} + + +void _sys_exit(int return_code) { +label: goto label; /* endless loop */ +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s new file mode 100644 index 0000000..056174c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s @@ -0,0 +1,111 @@ +;/* File: startup_armv6-m.s +; * Purpose: startup file for armv7-m architecture devices. +; * Should be used with ARMCC +; * Version: V2.00 +; * Date: 16 November 2015 +; * +; */ +;/* Copyright (c) 2011 - 2014 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + BKPT #0 + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + BKPT #0 + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + + ALIGN + + END diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s new file mode 100644 index 0000000..b40c565 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s @@ -0,0 +1,134 @@ +;/* File: startup_armv7-m.s +; * Purpose: startup file for armv7-m architecture devices. +; * Should be used with ARMCC +; * Version: V2.00 +; * Date: 16 November 2015 +; * +; */ +;/* Copyright (c) 2011 - 2014 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + BKPT #0 + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + BKPT #0 + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + BKPT #0 + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + BKPT #0 + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + BKPT #0 + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + + ALIGN + + END diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S new file mode 100644 index 0000000..d3499af --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S @@ -0,0 +1,127 @@ +/* File: startup_armv6-m.S + * Purpose: startup file for armv6-m architecture devices. + * Should be used with ARMCLANG + * Version: V2.00 + * Date: 16 November 2015 + * + */ +/* Copyright (c) 2011 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ +/* + ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + .syntax unified + .arch armv6-m + +/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */ +.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */ + + .global Image$$ARM_LIB_STACK$$ZI$$Limit + + + .section RESET, "x" + .align 2 + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ +__Vectors_End: + + .equ __Vectors_Size, __Vectors_End - __Vectors + + + .text + .thumb + .align 2 + + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + .thumb_func +Reset_Handler: + bl SystemInit + bl __main + + .globl NMI_Handler + .weak NMI_Handler + .type NMI_Handler, %function + .thumb_func +NMI_Handler: + bkpt #0 + b . + + .globl HardFault_Handler + .weak HardFault_Handler + .type HardFault_Handler, %function + .thumb_func +HardFault_Handler: + bkpt #0 + b . + + .globl SVC_Handler + .weak SVC_Handler + .type SVC_Handler, %function + .thumb_func +SVC_Handler: + bkpt #0 + b . + + .globl PendSV_Handler + .weak PendSV_Handler + .type PendSV_Handler, %function + .thumb_func +PendSV_Handler: + bkpt #0 + b . + + .globl SysTick_Handler + .weak SysTick_Handler + .type SysTick_Handler, %function + .thumb_func +SysTick_Handler: + bkpt #0 + b . + + .end diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S new file mode 100644 index 0000000..53a307e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S @@ -0,0 +1,159 @@ +/* File: startup_armv7-m.S + * Purpose: startup file for armv7-m architecture devices. + * Should be used with ARMCLANG + * Version: V2.00 + * Date: 16 November 2015 + * + */ +/* Copyright (c) 2011 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ +/* + ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + .syntax unified + .arch armv7-m + +/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */ +.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */ + + .global Image$$ARM_LIB_STACK$$ZI$$Limit + + + .section RESET, "x" + .align 2 + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ +__Vectors_End: + + .equ __Vectors_Size, __Vectors_End - __Vectors + + + .text + .thumb + .align 2 + + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + .thumb_func +Reset_Handler: + bl SystemInit + bl __main + + .globl NMI_Handler + .weak NMI_Handler + .type NMI_Handler, %function + .thumb_func +NMI_Handler: + bkpt #0 + b . + + .globl HardFault_Handler + .weak HardFault_Handler + .type HardFault_Handler, %function + .thumb_func +HardFault_Handler: + bkpt #0 + b . + + .globl MemManage_Handler + .weak MemManage_Handler + .type MemManage_Handler, %function + .thumb_func +MemManage_Handler: + bkpt #0 + b . + + .globl BusFault_Handler + .weak BusFault_Handler + .type BusFault_Handler, %function + .thumb_func +BusFault_Handler: + bkpt #0 + b . + + .globl UsageFault_Handler + .weak UsageFault_Handler + .type UsageFault_Handler, %function + .thumb_func +UsageFault_Handler: + bkpt #0 + b . + + .globl SVC_Handler + .weak SVC_Handler + .type SVC_Handler, %function + .thumb_func +SVC_Handler: + bkpt #0 + b . + + .globl DebugMon_Handler + .weak DebugMon_Handler + .type DebugMon_Handler, %function + .thumb_func +DebugMon_Handler: + bkpt #0 + b . + + .globl PendSV_Handler + .weak PendSV_Handler + .type PendSV_Handler, %function + .thumb_func +PendSV_Handler: + bkpt #0 + b . + + .globl SysTick_Handler + .weak SysTick_Handler + .type SysTick_Handler, %function + .thumb_func +SysTick_Handler: + bkpt #0 + b . + + .end diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c new file mode 100644 index 0000000..876ce8c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c @@ -0,0 +1,106 @@ +/*---------------------------------------------------------------------------- + * Name: Retarget.c + * Purpose: 'Retarget' layer for target-dependent low level functions + * Note(s): + *---------------------------------------------------------------------------- + * This file is part of the uVision/ARM development tools. + * This software may only be used under the terms of a valid, current, + * end user licence from KEIL for a compatible version of KEIL software + * development tools. Nothing else gives you the right to use this software. + * + * This software is supplied "AS IS" without warranties of any kind. + * + * Copyright (c) 2012 Keil - An ARM Company. All rights reserved. + *----------------------------------------------------------------------------*/ + +#include +#include +#include + +int SER_PutChar (int c) { + + return (c); +} + +int SER_GetChar (void) { + + return (-1); +} + +/*-- GCC - Newlib runtime support --------------------------------------------*/ + +extern int __HeapBase; +extern int __HeapLimit; + +int _open (const char * path, int flags, ...) +{ + return (-1); +} + +int _close (int fd) +{ + return (-1); +} + +int _lseek (int fd, int ptr, int dir) +{ + return (0); +} + +int __attribute__((weak)) _fstat (int fd, struct stat * st) +{ + memset (st, 0, sizeof (* st)); + st->st_mode = S_IFCHR; + return (0); +} + +int _isatty (int fd) +{ + return (1); +} + +int _read (int fd, char * ptr, int len) +{ + char c; + int i; + + for (i = 0; i < len; i++) + { + c = SER_GetChar(); + if (c == 0x0D) break; + *ptr++ = c; + SER_PutChar(c); + } + return (len - i); +} + +int _write (int fd, char * ptr, int len) +{ + int i; + + for (i = 0; i < len; i++) SER_PutChar (*ptr++); + return (i); +} + +caddr_t _sbrk (int incr) +{ + static char * heap; + char * prev_heap; + + if (heap == NULL) + { + heap = (char *)&__HeapBase; + } + + prev_heap = heap; + + if ((heap + incr) > (char *)&__HeapLimit) + { + errno = ENOMEM; + return (caddr_t) -1; + } + + heap += incr; + + return (caddr_t) prev_heap; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S new file mode 100644 index 0000000..a5e14f1 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S @@ -0,0 +1,263 @@ +/* File: startup_armv6-m.S + * Purpose: startup file for armv6-m architecture devices. + * Should be used with GCC for ARM Embedded Processors + * Version: V2.00 + * Date: 16 November 2015 + * + */ +/* Copyright (c) 2011 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00000400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000C00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + bkpt #0 + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + .end diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S new file mode 100644 index 0000000..35b388c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S @@ -0,0 +1,257 @@ +/* File: startup_armv7-m.S + * Purpose: startup file for armv7-m architecture devices. + * Should be used with GCC for ARM Embedded Processors + * Version: V2.00 + * Date: 16 November 2015 + * + */ +/* Copyright (c) 2011 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00000400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000C00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + bkpt #0 + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + .end diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S new file mode 100644 index 0000000..91a9ea3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S @@ -0,0 +1,68 @@ + +#if defined (__CC_ARM) + #if (defined (ARMCM0)) + #include "ARMCC\startup_armv6-m.s" + #elif (defined (ARMCM0P) || defined (ARMCM0P_MPU)) + #include "ARMCC\startup_armv6-m.s" + #elif (defined (ARMCM3)) + #include "ARMCC\startup_armv7-m.s" + #elif (defined (ARMCM4) || defined (ARMCM4_FP)) + #include "ARMCC\startup_armv7-m.s" + #elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP)) + #include "ARMCC\startup_armv7-m.s" + #elif (defined (ARMv8MBL)) + #include "ARMCC\startup_armv6-m.s" + #elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \ + defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \ + defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) ) + #include "ARMCC\startup_armv7-m.s" + #else + #error "No appropriate startup file found!" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if (defined (ARMCM0)) + #include "ARMCLANG\startup_armv6-m.S" + #elif (defined (ARMCM0P) || defined (ARMCM0P_MPU)) + #include "ARMCLANG\startup_armv6-m.S" + #elif (defined (ARMCM3)) + #include "ARMCLANG\startup_armv7-m.S" + #elif (defined (ARMCM4) || defined (ARMCM4_FP)) + #include "ARMCLANG\startup_armv7-m.S" + #elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP)) + #include "ARMCLANG\startup_armv7-m.S" + #elif (defined (ARMv8MBL)) + #include "ARMCLANG\startup_armv6-m.S" + #elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \ + defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \ + defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) ) + #include "ARMCLANG\startup_armv7-m.S" + #else + #error "No appropriate startup file found!" + #endif + +#elif defined (__GNUC__) + #if (defined (ARMCM0)) + #include "GCC\startup_armv6-m.S" + #elif (defined (ARMCM0P) || defined (ARMCM0P_MPU)) + #include "GCC\startup_armv6-m.S" + #elif (defined (ARMCM3)) + #include "GCC\startup_armv7-m.S" + #elif (defined (ARMCM4) || defined (ARMCM4_FP)) + #include "GCC\startup_armv7-m.S" + #elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP)) + #include "GCC\startup_armv7-m.S" + #elif (defined (ARMv8MBL)) + #include "GCC\startup_armv6-m.S" + #elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \ + defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \ + defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) ) + #include "GCC\startup_armv7-m.S" + #else + #error "No appropriate startup file found!" + #endif + +#else + #error "Compiler not supported!" +#endif + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c new file mode 100644 index 0000000..177fc83 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c new file mode 100644 index 0000000..1807ce7 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c @@ -0,0 +1,82 @@ +/**************************************************************************//** + * @file system_ARMCM23.c + * @brief CMSIS Device System Source File for + * ARMCM23 Device Series + * @version V5.00 + * @date 21. October 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM23.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c new file mode 100644 index 0000000..b072192 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c new file mode 100644 index 0000000..d232877 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c @@ -0,0 +1,99 @@ +/**************************************************************************//** + * @file system_ARMCM33.c + * @brief CMSIS Device System Source File for + * ARMCM33 Device Series + * @version V5.00 + * @date 02. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#elif defined (ARMCM33_TZ) + #include "ARMCM33_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#elif defined (ARMCM33_DSP_FP) + #include "ARMCM33_DSP_FP.h" +#elif defined (ARMCM33_DSP_FP_TZ) + #include "ARMCM33_DSP_FP_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */ + (3U << 11U*2U) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c new file mode 100644 index 0000000..9ba60fa --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */ + (3U << 11U*2U) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c new file mode 100644 index 0000000..b5045f0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */ + (3U << 11U*2U) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c new file mode 100644 index 0000000..74bf4e6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMSC000.c + * @brief CMSIS Device System Source File for + * for ARMSC000 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMSC000.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c new file mode 100644 index 0000000..5aafb1c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file system_ARMSC300.c + * @brief CMSIS Device System Source File for + * ARMSC300 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMSC300.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c new file mode 100644 index 0000000..7e652c6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMv8MBL.c + * @brief CMSIS Device System Source File for + * ARMv8MBL Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMv8MBL.h" + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMv8MBL.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c new file mode 100644 index 0000000..451a533 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c @@ -0,0 +1,99 @@ +/**************************************************************************//** + * @file system_ARMv8MML.c + * @brief CMSIS Device System Source File for + * ARMv8MML Device Series + * @version V5.00 + * @date 02. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMv8MML) + #include "ARMv8MML.h" +#elif defined (ARMv8MML_DSP) + #include "ARMv8MML_DSP.h" +#elif defined (ARMv8MML_SP) + #include "ARMv8MML_SP.h" +#elif defined (ARMv8MML_DSP_SP) + #include "ARMv8MML_DSP_SP.h" +#elif defined (ARMv8MML_DP) + #include "ARMv8MML_DP.h" +#elif defined (ARMv8MML_DSP_DP) + #include "ARMv8MML_DSP_DP.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMv8MML.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */ + (3U << 11U*2U) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c new file mode 100644 index 0000000..4db5f76 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c @@ -0,0 +1,27 @@ + +#if (defined (ARMCM0)) + #include "system_ARMCM0.c" + +#elif (defined (ARMCM0P)) + #include "system_ARMCM0plus.c" + +#elif (defined (ARMCM3)) + #include "system_ARMCM3.c" + +#elif (defined (ARMCM4) || defined (ARMCM4_FP)) + #include "system_ARMCM4.c" + +#elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP)) + #include "system_ARMCM7.c" + +#elif defined (ARMv8MBL) + #include "system_ARMv8MBL.c" + +#elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \ + defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \ + defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) ) + #include "system_ARMv8MML.c" + +#else + #error "No appropriate system file found!" +#endif diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c new file mode 100644 index 0000000..2926273 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c @@ -0,0 +1,62 @@ +#include "jtest.h" +#include "basic_math_test_group.h" +#include "complex_math_test_group.h" +#include "controller_test_group.h" +#include "fast_math_test_group.h" +#include "filtering_test_group.h" +#include "matrix_test_group.h" +#include "statistics_test_group.h" +#include "support_test_group.h" +#include "transform_test_group.h" +#include "intrinsics_test_group.h" + +JTEST_DEFINE_GROUP(all_tests) +{ + /* + To skip a test, comment it out + */ +#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_BASICMATH_TESTS) + JTEST_GROUP_CALL(basic_math_tests); +#endif + +#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_COMPLEXMATH_TESTS) + JTEST_GROUP_CALL(complex_math_tests); +#endif + +#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_CONTROLLER_TESTS) + JTEST_GROUP_CALL(controller_tests); +#endif + +#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_FASTMATH_TESTS) + JTEST_GROUP_CALL(fast_math_tests); +#endif + +#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_FILTERING_TESTS) + /* Biquad df2T_f32 will fail with Neon. The test must be updated. + Neon implementation is requiring a different initialization. + */ + JTEST_GROUP_CALL(filtering_tests); +#endif + +#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_MATRIX_TESTS) + JTEST_GROUP_CALL(matrix_tests); +#endif + +#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_STATISTICS_TESTS) + JTEST_GROUP_CALL(statistics_tests); +#endif() + +#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_SUPPORT_TESTS) + JTEST_GROUP_CALL(support_tests); +#endif + +#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_TRANSFORM_TESTS) + JTEST_GROUP_CALL(transform_tests); +#endif + +#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_INTRINSICS_TESTS) + JTEST_GROUP_CALL(intrinsics_tests); +#endif + + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c new file mode 100644 index 0000000..a2dda4d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c @@ -0,0 +1,32 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_ABS_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + abs, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix)) + +JTEST_ARM_ABS_TEST(f32); +JTEST_ARM_ABS_TEST(q31); +JTEST_ARM_ABS_TEST(q15); +JTEST_ARM_ABS_TEST(q7 ); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(abs_tests) +{ + JTEST_TEST_CALL(arm_abs_f32_test); + JTEST_TEST_CALL(arm_abs_q31_test); + JTEST_TEST_CALL(arm_abs_q15_test); + JTEST_TEST_CALL(arm_abs_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c new file mode 100644 index 0000000..85a018d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_ADD_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + add, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + BASIC_MATH_COMPARE_INTERFACE) + +JTEST_ARM_ADD_TEST(f32); +JTEST_ARM_ADD_TEST(q31); +JTEST_ARM_ADD_TEST(q15); +JTEST_ARM_ADD_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(add_tests) +{ + JTEST_TEST_CALL(arm_add_f32_test); + JTEST_TEST_CALL(arm_add_q31_test); + JTEST_TEST_CALL(arm_add_q15_test); + JTEST_TEST_CALL(arm_add_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c new file mode 100644 index 0000000..45c2167 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c @@ -0,0 +1,101 @@ +#include "basic_math_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(BASIC_MATH_BIGGEST_INPUT_TYPE, + basic_math_output_fut, + BASIC_MATH_MAX_INPUT_ELEMENTS, + CURLY(0)); + +ARR_DESC_DEFINE(BASIC_MATH_BIGGEST_INPUT_TYPE, + basic_math_output_ref, + BASIC_MATH_MAX_INPUT_ELEMENTS, + CURLY(0)); + +BASIC_MATH_BIGGEST_INPUT_TYPE +basic_math_output_f32_ref[BASIC_MATH_MAX_INPUT_ELEMENTS]; + +BASIC_MATH_BIGGEST_INPUT_TYPE +basic_math_output_f32_fut[BASIC_MATH_MAX_INPUT_ELEMENTS]; + +/*--------------------------------------------------------------------------------*/ +/* Block Sizes */ +/*--------------------------------------------------------------------------------*/ + +/* + To change test parameter values add/remove values inside CURLY and update + the preceeding parameter to reflect the number of values inside CURLY. +*/ + +ARR_DESC_DEFINE(uint32_t, + basic_math_block_sizes, + 4, + CURLY( 2, 7, 15, 32)); + +/*--------------------------------------------------------------------------------*/ +/* Numbers */ +/*--------------------------------------------------------------------------------*/ + +/* + To change test parameter values add/remove values inside CURLY and update + the preceeding parameter to reflect the number of values inside CURLY. +*/ + +ARR_DESC_DEFINE(uint32_t, + basic_math_elts, + 4, + CURLY( 0, 1, 0x80000000, 0x7fffffff)); + +ARR_DESC_DEFINE(int8_t, + basic_math_elts2, + 5, + CURLY( 0, 3, -3, -7, 7)); + +ARR_DESC_DEFINE(float32_t, + basic_math_eltsf, + 6, + CURLY( 0.0f, 1.0f, 1.254001, -1.665584, -127.435646, 245.34634267)); + +/*--------------------------------------------------------------------------------*/ +/* Test Data */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(float32_t, + basic_math_f_32, + 32, + CURLY( + -0.432565, -1.665584, 0.125332, 0.287676, -1.146471, + 1.190915, 1.189164, -0.037633, 0.327292, 0.174639, + -0.186709, 0.725791, -0.588317, 2.183186, -0.136396, + 0.113931, 1.066768, 0.059281, -0.095648, -0.832349, + 0.294411, -1.336182, 0.714325, 1.623562, -0.691776, + 0.857997, 1.254001, -1.593730, -1.440964, 0.571148, + -0.399886, 0.689997 + )); + +/* Alias the 32 element array with wrappers that end sooner. */ +ARR_DESC_DEFINE_SUBSET(basic_math_f_15, + basic_math_f_32, + 15); + +ARR_DESC_DEFINE_SUBSET(basic_math_f_2, + basic_math_f_32, + 2); + +ARR_DESC_DEFINE(float32_t, + basic_math_zeros, + 32, + CURLY(0)); + +/* Aggregate all float datasets. */ +ARR_DESC_DEFINE(ARR_DESC_t *, + basic_math_f_all, + 4, + CURLY( + &basic_math_zeros, + &basic_math_f_2, + &basic_math_f_15, + &basic_math_f_32 + )); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c new file mode 100644 index 0000000..c1ea8ba --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c @@ -0,0 +1,17 @@ +#include "jtest.h" +#include "basic_math_tests.h" + +JTEST_DEFINE_GROUP(basic_math_tests) +{ + JTEST_GROUP_CALL(abs_tests); + JTEST_GROUP_CALL(add_tests); + JTEST_GROUP_CALL(dot_prod_tests); + JTEST_GROUP_CALL(mult_tests); + JTEST_GROUP_CALL(negate_tests); + JTEST_GROUP_CALL(offset_tests); + JTEST_GROUP_CALL(scale_tests); + JTEST_GROUP_CALL(shift_tests); + JTEST_GROUP_CALL(sub_tests); + + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c new file mode 100644 index 0000000..e92d6e7 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_DOT_PROD_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + dot_prod, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + BASIC_MATH_SNR_ELT1_COMPARE_INTERFACE) + +JTEST_ARM_DOT_PROD_TEST(f32); +JTEST_ARM_DOT_PROD_TEST(q31); +JTEST_ARM_DOT_PROD_TEST(q15); +JTEST_ARM_DOT_PROD_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(dot_prod_tests) +{ + JTEST_TEST_CALL(arm_dot_prod_f32_test); + JTEST_TEST_CALL(arm_dot_prod_q31_test); + JTEST_TEST_CALL(arm_dot_prod_q15_test); + JTEST_TEST_CALL(arm_dot_prod_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c new file mode 100644 index 0000000..d735ade --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MULT_TEST(suffix, compare_interface) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + mult, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + compare_interface) + +JTEST_ARM_MULT_TEST(f32, BASIC_MATH_COMPARE_INTERFACE); +JTEST_ARM_MULT_TEST(q31, BASIC_MATH_SNR_COMPARE_INTERFACE); +JTEST_ARM_MULT_TEST(q15, BASIC_MATH_COMPARE_INTERFACE); +JTEST_ARM_MULT_TEST(q7 , BASIC_MATH_COMPARE_INTERFACE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mult_tests) +{ + JTEST_TEST_CALL(arm_mult_f32_test); + JTEST_TEST_CALL(arm_mult_q31_test); + JTEST_TEST_CALL(arm_mult_q15_test); + JTEST_TEST_CALL(arm_mult_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c new file mode 100644 index 0000000..4b96dc2 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c @@ -0,0 +1,32 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_NEGATE_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + negate, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix)) + +JTEST_ARM_NEGATE_TEST(f32); +JTEST_ARM_NEGATE_TEST(q31); +JTEST_ARM_NEGATE_TEST(q15); +JTEST_ARM_NEGATE_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(negate_tests) +{ + JTEST_TEST_CALL(arm_negate_f32_test); + JTEST_TEST_CALL(arm_negate_q31_test); + JTEST_TEST_CALL(arm_negate_q15_test); + JTEST_TEST_CALL(arm_negate_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c new file mode 100644 index 0000000..f95e523 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_OFFSET_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK( \ + offset, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix)) + +JTEST_ARM_OFFSET_TEST(f32); +JTEST_ARM_OFFSET_TEST(q31); +JTEST_ARM_OFFSET_TEST(q15); +JTEST_ARM_OFFSET_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(offset_tests) +{ + JTEST_TEST_CALL(arm_offset_f32_test); + JTEST_TEST_CALL(arm_offset_q31_test); + JTEST_TEST_CALL(arm_offset_q15_test); + JTEST_TEST_CALL(arm_offset_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c new file mode 100644 index 0000000..09fda86 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c @@ -0,0 +1,52 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + + +#define JTEST_ARM_SCALE_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT2_BLK( \ + scale, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), /*elt1_type*/ \ + int8_t, /*elt2_type*/ \ + TYPE_FROM_ABBREV(suffix)) + +/* float32_t defined separately because it has less arguments */ +JTEST_DEFINE_TEST(arm_scale_f32_test, + arm_scale_f32) +{ + TEST_TEMPLATE_BUF1_ELT1_BLK( + basic_math_f_all, + basic_math_eltsf, + basic_math_block_sizes, + float32_t, + float32_t, + float32_t, + arm_scale_f32, + ARM_scale_float_INPUT_INTERFACE, + ref_scale_f32, + REF_scale_float_INPUT_INTERFACE, + BASIC_MATH_COMPARE_INTERFACE); +} + +JTEST_ARM_SCALE_TEST(q31); +JTEST_ARM_SCALE_TEST(q15); +JTEST_ARM_SCALE_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(scale_tests) +{ + JTEST_TEST_CALL(arm_scale_f32_test); + JTEST_TEST_CALL(arm_scale_q31_test); + JTEST_TEST_CALL(arm_scale_q15_test); + JTEST_TEST_CALL(arm_scale_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c new file mode 100644 index 0000000..c3cd547 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_SHIFT_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK( \ + shift, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + int8_t, /*elt_type*/ \ + TYPE_FROM_ABBREV(suffix)) + +JTEST_ARM_SHIFT_TEST(q31); +JTEST_ARM_SHIFT_TEST(q15); +JTEST_ARM_SHIFT_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(shift_tests) +{ + JTEST_TEST_CALL(arm_shift_q31_test); + JTEST_TEST_CALL(arm_shift_q15_test); + JTEST_TEST_CALL(arm_shift_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c new file mode 100644 index 0000000..e52e73b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_SUB_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + sub, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + BASIC_MATH_COMPARE_INTERFACE) + +JTEST_ARM_SUB_TEST(f32); +JTEST_ARM_SUB_TEST(q31); +JTEST_ARM_SUB_TEST(q15); +JTEST_ARM_SUB_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(sub_tests) +{ + JTEST_TEST_CALL(arm_sub_f32_test); + JTEST_TEST_CALL(arm_sub_q31_test); + JTEST_TEST_CALL(arm_sub_q15_test); + JTEST_TEST_CALL(arm_sub_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c new file mode 100644 index 0000000..24b5cf9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_CONJ_TEST(suffix) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + cmplx_conj, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE) + +JTEST_ARM_CMPLX_CONJ_TEST(f32); +JTEST_ARM_CMPLX_CONJ_TEST(q31); +JTEST_ARM_CMPLX_CONJ_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_conj_tests) +{ + JTEST_TEST_CALL(arm_cmplx_conj_f32_test); + JTEST_TEST_CALL(arm_cmplx_conj_q31_test); + JTEST_TEST_CALL(arm_cmplx_conj_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c new file mode 100644 index 0000000..d9b5bfa --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_DOT_PROD_TEST(suffix, comparison_interface) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + cmplx_dot_prod, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + comparison_interface) + +JTEST_ARM_CMPLX_DOT_PROD_TEST(f32, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE); +JTEST_ARM_CMPLX_DOT_PROD_TEST(q31, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE); +JTEST_ARM_CMPLX_DOT_PROD_TEST(q15, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_dot_prod_tests) +{ + JTEST_TEST_CALL(arm_cmplx_dot_prod_f32_test); + JTEST_TEST_CALL(arm_cmplx_dot_prod_q31_test); + JTEST_TEST_CALL(arm_cmplx_dot_prod_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c new file mode 100644 index 0000000..55e9541 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_MAG_SQUARED_TEST(suffix) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + cmplx_mag_squared, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + COMPLEX_MATH_COMPARE_RE_INTERFACE) + +JTEST_ARM_CMPLX_MAG_SQUARED_TEST(f32); +JTEST_ARM_CMPLX_MAG_SQUARED_TEST(q31); +JTEST_ARM_CMPLX_MAG_SQUARED_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_mag_squared_tests) +{ + JTEST_TEST_CALL(arm_cmplx_mag_squared_f32_test); + JTEST_TEST_CALL(arm_cmplx_mag_squared_q31_test); + JTEST_TEST_CALL(arm_cmplx_mag_squared_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c new file mode 100644 index 0000000..b06e359 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_MAG_TEST(suffix, comparison_interface) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + cmplx_mag, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + comparison_interface) + +JTEST_ARM_CMPLX_MAG_TEST(f32, COMPLEX_MATH_COMPARE_RE_INTERFACE); +JTEST_ARM_CMPLX_MAG_TEST(q31, COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE); +JTEST_ARM_CMPLX_MAG_TEST(q15, COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_mag_tests) +{ + JTEST_TEST_CALL(arm_cmplx_mag_f32_test); + JTEST_TEST_CALL(arm_cmplx_mag_q31_test); + JTEST_TEST_CALL(arm_cmplx_mag_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c new file mode 100644 index 0000000..d2cabd9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_MULT_CMPLX_TEST(suffix) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + cmplx_mult_cmplx, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + COMPLEX_MATH_COMPARE_CMPLX_INTERFACE) + +JTEST_ARM_CMPLX_MULT_CMPLX_TEST(f32); +JTEST_ARM_CMPLX_MULT_CMPLX_TEST(q31); +JTEST_ARM_CMPLX_MULT_CMPLX_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_mult_cmplx_tests) +{ + JTEST_TEST_CALL(arm_cmplx_mult_cmplx_f32_test); + JTEST_TEST_CALL(arm_cmplx_mult_cmplx_q31_test); + JTEST_TEST_CALL(arm_cmplx_mult_cmplx_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c new file mode 100644 index 0000000..a06f165 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_MULT_REAL_TEST(suffix, comparison_interface) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + cmplx_mult_real, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + comparison_interface) + +JTEST_ARM_CMPLX_MULT_REAL_TEST(f32, COMPLEX_MATH_COMPARE_CMPLX_INTERFACE); +JTEST_ARM_CMPLX_MULT_REAL_TEST(q31, COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE); +JTEST_ARM_CMPLX_MULT_REAL_TEST(q15, COMPLEX_MATH_COMPARE_CMPLX_INTERFACE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_mult_real_tests) +{ + JTEST_TEST_CALL(arm_cmplx_mult_real_f32_test); + JTEST_TEST_CALL(arm_cmplx_mult_real_q31_test); + JTEST_TEST_CALL(arm_cmplx_mult_real_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c new file mode 100644 index 0000000..d158bbf --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c @@ -0,0 +1,114 @@ +#include "complex_math_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE, + complex_math_output_fut_a, + COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/, + CURLY(0)); + +ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE, + complex_math_output_fut_b, + COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/, + CURLY(0)); + +ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE, + complex_math_output_ref_a, + COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/, + CURLY(0)); + + +ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE, + complex_math_output_ref_b, + COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/, + CURLY(0)); + + +COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_ref_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_ref_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_fut_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_fut_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +/*--------------------------------------------------------------------------------*/ +/* Block Sizes */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(uint32_t, + complex_math_block_sizes, + 4, + CURLY(1, 2, 15, 32)); + +/*--------------------------------------------------------------------------------*/ +/* Test Data */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(float32_t, + complex_math_f_32, + 32 * 2 /*Complex data has two parts*/, + CURLY( + -0.432564811528220680 , 0.815622288876143300, + -1.665584378238097000 , 0.711908323500893280, + 0.125332306474830680 , 1.290249754932477000, + 0.287676420358548850 , 0.668600505682040320, + -1.146471350681463700 , 1.190838074243369100, + 1.190915465642998800 , -1.202457114773944000, + 1.189164201652103100 , -0.019789557768770449, + -0.037633276593317645 , -0.156717298831980680, + 0.327292361408654140 , -1.604085562001158500, + 0.174639142820924520 , 0.257304234677489860, + -0.186708577681439360 , -1.056472928081482400, + 0.725790548293302700 , 1.415141485872338600, + -0.588316543014188680 , -0.805090404196879830, + 2.183185818197101100 , 0.528743010962224870, + -0.136395883086595700 , 0.219320672667622370, + 0.113931313520809620 , -0.921901624355539130, + 1.066768211359188800 , -2.170674494305262500, + 0.059281460523605348 , -0.059187824521191180, + -0.095648405483669041 , -1.010633706474247400, + -0.832349463650022490 , 0.614463048895480980, + 0.294410816392640380 , 0.507740785341985520, + -1.336181857937804000 , 1.692429870190521400, + 0.714324551818952160 , 0.591282586924175900, + 1.623562064446270700 , -0.643595202682526120, + -0.691775701702286750 , 0.380337251713910140, + 0.857996672828262640 , -1.009115524340785000, + 1.254001421602532400 , -0.019510669530289293, + -1.593729576447476800 , -0.048220789145312269, + -1.440964431901020000 , 0.000043191841625545, + 0.571147623658177950 , -0.317859451247687890, + -0.399885577715363150 , 1.095003738787492500, + 0.689997375464345140 , -1.873990257640960800 + )); + +ARR_DESC_DEFINE_SUBSET(complex_math_f_15, + complex_math_f_32, + 15 * 2 /*Complex data has two parts*/); + +ARR_DESC_DEFINE_SUBSET(complex_math_f_2, + complex_math_f_32, + 2 * 2 /*Complex data has two parts*/); + +ARR_DESC_DEFINE(float32_t, + complex_math_zeros, + 32 * 2 /*Complex data has two parts*/, + CURLY(0)); + +/* Aggregate all float datasets */ +ARR_DESC_DEFINE(ARR_DESC_t *, + complex_math_f_all, + 4, + CURLY( + &complex_math_zeros, + &complex_math_f_2, + &complex_math_f_15, + &complex_math_f_32 + )); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c new file mode 100644 index 0000000..1be8a83 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c @@ -0,0 +1,14 @@ +#include "jtest.h" +#include "complex_math_tests.h" + +JTEST_DEFINE_GROUP(complex_math_tests) +{ + JTEST_GROUP_CALL(cmplx_conj_tests); + JTEST_GROUP_CALL(cmplx_dot_prod_tests); + JTEST_GROUP_CALL(cmplx_mag_tests); + JTEST_GROUP_CALL(cmplx_mag_squared_tests); + JTEST_GROUP_CALL(cmplx_mult_cmplx_tests); + JTEST_GROUP_CALL(cmplx_mult_real_tests); + + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c new file mode 100644 index 0000000..e591293 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c @@ -0,0 +1,499 @@ +#include "controller_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +float32_t controller_output_fut[CONTROLLER_MAX_LEN] = {0}; +float32_t controller_output_ref[CONTROLLER_MAX_LEN] = {0}; +float32_t controller_output_f32_fut[CONTROLLER_MAX_LEN] = {0}; +float32_t controller_output_f32_ref[CONTROLLER_MAX_LEN] = {0}; + +const q31_t controller_q31_inputs[CONTROLLER_MAX_LEN] = +{ + 0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB, 0x41F6F6A, + 0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8, 0x3D060524, 0x93D5E570, + 0x97D7791D, 0xFFE0C38C, 0x26749841, 0xC0A6EE54, 0x218EC386, 0x39FF3726, + 0x8DC1F7CA, 0x702F2CF5, 0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49, + 0x3805DE7E, 0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF, + 0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24, 0x6CE00F5C, + 0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530, 0x73394127, 0x773FA6F4, + 0x9805A980, 0x838DE587, 0x9CF597F4, 0xA2AD1691, 0xFA81A473, 0x7CDC7D7F, + 0x4A5190D0, 0xED895BB9, 0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516, + 0x2501A3E1, 0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E, + 0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4, 0x24DB166C, + 0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6, 0x419E0C75, 0x46BE9F38, + 0x2432B9B2, 0x758D83E0, 0xDCE12926, 0x3F57CB74, 0x1F4458E2, 0xF1DD639, + 0x83A1FB49, 0x173AFC76, 0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549, + 0x5C314C9, 0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715, + 0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F, 0x20BFDEB4, + 0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE, 0x9858E3E1, 0xA36A9C4E, + 0x88BD21F9, 0xAACF7A68, 0x773665E5, 0xCEDFDF66, 0x617A9610, 0x524FC968, + 0xC2D086CD, 0x5F008079, 0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608, + 0xA33A2EE5, 0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5, + 0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4, 0xB358C0D8, + 0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF, 0x33035831, 0x13D93987, + 0xFC542094, 0x845F317E, 0xDDC4BF8B, 0x1379E50C, 0x5C20193F, 0xFDD58298, + 0x9D482B82, 0x4A6BE062, 0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882, + 0xE6F8EA35, 0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD, + 0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677, 0xFB2E04F2, + 0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8, 0x1A8C7F28, 0x861E452E, + 0x932D3F78, 0x7652D852, 0x73357BBA, 0xEBBB0A58, 0x62536AFA, 0x3F6B65EF, + 0x6DC57B58, 0x9EB798CE, 0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302, + 0xA9FD3E40, 0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3, + 0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896, 0x6443A0FE, + 0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820, 0xF18F0810, 0xE1548689, + 0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B, 0xEA0C1BE0, 0xA1B785DB, 0x7086465D, + 0x1CC10929, 0x1E1D716E, 0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4, + 0x441F1E8B, 0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137, + 0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615, 0x92593380, + 0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7, 0x10E916B6, 0xE3BCFA68, + 0x2ACB80BB, 0xE51C5590, 0x994714B5, 0xF30984EE, 0x59BBE1B4, 0xB4867DBC, + 0xB91C706C, 0xBC16C218, 0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, + 0x4B167FD4, 0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55, + 0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A, 0x9D2C662A, + 0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C, 0x20306EDB, 0xE381AAE7, + 0xA55DA748, 0x9B8B617B, 0x3E036FAD, 0x84E4C4A7, 0xD5A3F517, 0x669BA988, + 0x98FDDE8C, 0x67BD85CE, 0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF, + 0x205DB5C, 0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC, + 0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693, 0xC42D12C0, + 0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC, 0x8D874532, 0x5F5C9DD0, + 0x5D167858, 0x8559FEA2, 0x9D821476, 0xD9654ED2, 0x594C0DC7, 0x1A87B506, + 0x3F693200, 0x7A651AB5, 0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0, + 0xB088C72F, 0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB, + 0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D, 0x32581A06, + 0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15, 0xBC79A9BC, 0xB7175917, + 0x354E381C, 0x762AADD7, 0xF643DAC1, 0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4, + 0xD7694875, 0x92D30822, 0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7, + 0x58CE268, 0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1, + 0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB, 0x8FF5534, + 0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7, 0x419545EB, 0x993F7880, + 0xAB246B20, 0x408AABC4, 0xCBF6EA49, 0xC0894C55, 0x4CAA6398, 0xA47856E9, + 0xAF2AE47D, 0x22F55D33, 0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8, + 0x9A77D48, 0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A, + 0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071, 0x7F9930D4, + 0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A, 0x144B2C12, 0x98E425C7, + 0xBAA4B373, 0x18F0D03C, 0x99462AC0, 0xD8B4D2EF, 0x72473895, 0xA6BF5435, + 0xEDAD53B, 0xE0912FA6, 0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929, + 0xB89962F9, 0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0, + 0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841, 0x73A60174, + 0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095, 0x2B370837, 0x83DF6CE3, + 0xDD08EEFA, 0x3F52A7C2, 0x191B4785, 0x60843D82, 0xB0DE11F1, 0x105EA26C, + 0x6E1C7AA2, 0x47AADD14, 0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC, + 0x744206A, 0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9, + 0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F, 0x2E53E6C1, + 0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5, 0x119725CC, 0x5406D347, + 0x1B6FFAF1, 0xECCF71F1, 0x981117F2, 0x7167CA76, 0x74F4B880, 0x77A55F47, + 0x59EADB62, 0x4A331D95, 0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1, + 0x60D47AD5, 0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3, + 0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E, 0x31109C58, + 0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF, 0xBAF8D31E, 0xA4B31611, + 0xED37F331, 0x7A832A22, 0xA22591C7, 0x722D1F89, 0x3B19CF18, 0x261B8A4D, + 0xC3F6F6DB, 0xCF8CED61, 0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4, + 0x3674E663, 0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD, + 0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91, 0x4BF0C248, + 0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26, 0x6C3B7B71, 0xD744B3ED, + 0xFA25D2F6, 0x4CDE642D, 0xD65B8142, 0xA6F9207F, 0xE7A207BE, 0xDB506684, + 0x44DA4780, 0x9175EA0C, 0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2, + 0x5423D9C8, 0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1, + 0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5, 0x1672BA91, + 0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4, 0x32AFD40C, 0x99A5FB3B, + 0xDD1D73A3, 0xA342CB3E, 0xA78445F5, 0x53979C3B, 0x427D7943, 0x5221B58C, + 0xA6CE9A5E, 0xFB50ECA4, 0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04, + 0xFBB65E0C, 0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920, + 0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641, 0x4D6B1760, + 0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF, 0x4E5F9493, 0x4C215DA5, + 0x33A052B, 0x1A4D80C2, 0x40AEEBCA, 0x390D106B, 0xE9E8E018, 0x5AF3D6CF, + 0xE35E1D4, 0xC4FB1C6, 0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6, + 0x2227567D, 0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6, + 0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1, 0xC9D06CBC, + 0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47, 0x9D4804EA, 0x57DD9E67, + 0xF89C7895, 0xF5336111, 0x25C122C8, 0x62742114, 0xCFBF6D26, 0xBF9F6482, + 0xE6F02CD9, 0x11083202, 0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1, + 0x3BF4DC25, 0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129, + 0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA, 0x31C5A0AF, + 0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98, 0x82C34882, 0x5D041F11, + 0x8C613C57, 0xD398CFD1, 0x426F38AD, 0x5599AB1D, 0xFAFA078D, 0xAB25B413, + 0xD94B32CF, 0xB288FE38, 0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D, + 0x2174EBBE, 0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6, + 0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02, 0xC20D47A4, + 0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4, 0xC58612F4, 0xA2827F6F, + 0xC49DCDBA, 0x679B7362, 0x4E495845, 0xCFD2F0D1, 0x395E76A0, 0x375A655E, + 0x92E2058F, 0x73F9F0CA, 0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B, + 0xA219E2E8, 0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF, + 0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40, 0x157F6DDF, + 0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58, 0xB2945F75, 0x4FA23A0E, + 0x836EB8C0, 0xB3B18FD, 0x86114337, 0x24668ACB, 0x99BB82F0, 0x924C8A47, + 0xBA959701, 0x81155ABF, 0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7, + 0x7FC2802D, 0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719, + 0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD, 0xEBA775AE, + 0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D, 0xBBD34AB7, 0x2F85B12A, + 0x16C5C2AD, 0x3990985D, 0x88DF3351, 0x82811AA5, 0x6D351F41, 0x4066A69D, + 0x86B660BF, 0x6EDB4768, 0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687, + 0x947CC9C9, 0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB, + 0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B, 0xB7629C93, + 0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66, 0xEC71B78C, 0xEAF4BB3A, + 0x7C16225E, 0x668F337, 0xCBEE1608, 0x6D5B5552, 0x345DC590, 0x681209CC, + 0x7B24A819, 0xD08A1416, 0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678, + 0x20EECA0, 0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D, + 0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960, 0x7CDF59F3, + 0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110, 0xB8FCF3E3, 0xDEA059B2, + 0x8229B6EA, 0x316486F6, 0x43919185, 0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9, + 0x5CD41244, 0x2C9F0A7B, 0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0, + 0xF105C20D, 0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763, + 0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53, 0x2D2A85F6, + 0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B, 0x9FC5AC5F, 0x11AE5DD7, + 0xA0B9A5A9, 0xFC648AF4, 0x740009AC, 0xED0E0321, 0xB8E6A61, 0x8910C544, + 0xC74F26C8, 0x9525CCF3, 0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D, + 0xE1976DD4, 0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1, + 0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB, 0xF5288568, + 0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A, 0x1BC03B9, 0xB6BC3061, + 0xBF30596E, 0xBE2AD27B, 0x8AC04220, 0x641979A3, 0x9ECCBB89, 0xA144FBC1, + 0x4E8FAE26, 0x8C5A9D90, 0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D, + 0xCEE81CDF, 0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA, + 0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38, 0x2E77F2D, + 0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017, 0x2D6B69A7, 0xFEDB63F9, + 0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8, 0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6, + 0xED193443, 0x7615EF1B, 0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022, + 0x556E825C, 0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF, + 0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC, 0x1E6A1101, + 0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599, 0x54EB4809, 0x7839BE6D, + 0xD50017DD, 0x39B1A0E1, 0x288D52D3, 0x2D52668C, 0x20D22A68, 0x4E1207D1, + 0x3FCC0EFE, 0x47F3FE64, 0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8, + 0x6BEAA655, 0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9, + 0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B, 0x4DCD4EDB, + 0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6, 0x502F41B0, 0x3616D3F1, + 0x2E5B8E31, 0x2026EB19, 0x57E783D7, 0x467BBE00, 0x4703ABA3, 0x1F776B9C, + 0xE2570A84, 0xFEC7DB48, 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, + 0x99D5D8ED, 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F, + 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB, 0x56186AA1, + 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94, 0xAC18B207, 0x5FC78B3, + 0x7F10621E, 0xA769E6B2, 0xEC9F4A11, 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, + 0x73D63FED, 0xE36E9F5E, 0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1, + 0xCD476E86, 0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7, + 0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78, 0xCC4BE4F6, + 0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2, 0x55A8F5EC, 0xE81A9A75, + 0x30A67E1B, 0x4A4A7D0C, 0x20F7F993, 0x1891805, 0x738976AD, 0xD426E7D6, + 0x3C5CEEBF, 0x4499187F, 0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, + 0x421BCF29, 0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE, + 0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46, 0x5D146234, + 0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA, 0xB65530CC, 0x2DFAC48C, + 0x1663D16F, 0x59B80AA, 0x950274EA, 0x92532D4A, 0x3CEF802D, 0x492FBDA5, + 0xA63A2574, 0xEF8005C2, 0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646, + 0xD2598516, 0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75, + 0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F +}; + +/* The source data is random across the q31_t range. Accessing it by word should + remain random. */ +const q15_t * controller_q15_inputs = (q15_t *) controller_q31_inputs; + +const float32_t controller_f32_inputs[CONTROLLER_MAX_LEN] = +{ + 43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580 , + 7.2830326091 , 66.8368719314 , 33.9778190671 , 117.8652289772 , + -129.6077797465, -14.6420815368 , 18.0239223278 , 20.6760530292 , + 55.0375037651 , 1.8674609862 , -85.6534302408 , -33.5750364909 , + 29.2110949614 , 110.4727049460 , -94.1914619387 , -1.4084169343 , + 83.5181653041 , 47.3073514127 , -13.3420621181 , 30.3389699104 , + 12.1188124277 , 100.9730921941 , -114.0146362390, -77.5823200409 , + 37.2019034618 , 40.0026301128 , -58.3387276630 , -34.9472398600 , + -5.1169678311 , -87.7660091118 , -150.5888601131, 56.0349370503 , + 50.2168884079 , -74.2313236767 , 22.3648603560 , -6.8676387051 , + 74.8957303680 , -90.1292012823 , -55.1436241586 , -66.6732976100 , + -6.7918147615 , 7.7612697081 , 35.7892605979 , -20.0470508830 , + 41.8369017546 , -143.7378056984, -41.9127158600 , -108.3531841158, + -57.1917422289 , -124.2808828105, 38.9316388820 , -77.9212517405 , + 37.1990818377 , -28.9545952748 , -155.6371057564, 45.8088886393 , + 36.2537018275 , -6.5727656016 , -104.2070491921, 45.5583813729 , + -19.7674717059 , -80.4802190947 , -1.4444563441 , -42.2142256438 , + 36.6546339194 , -57.0866498590 , 44.4677067511 , 65.7285753407 , + -103.8158864647, 25.4348723711 , -153.5419639389, 39.3608409474 , + 49.1658103436 , 79.5570602275 , 75.2944095996 , 58.9394700746 , + -53.1018534392 , 33.4172444014 , 35.6224682287 , -64.4353396418 , + -125.8464291251, -47.6072111617 , -26.2177687594 , -12.0061322096 , + -17.7887967585 , -28.2926175090 , -62.0691715749 , 40.5098573604 , + -191.1123732593, 119.6750713043 , 19.6182375803 , -26.7615252921 , + 2.2957847015 , -108.3436451287, -50.5906164995 , -5.6360985100 , + -11.6772204201 , -84.2765293757 , -60.9317810068 , 82.0446350218 , + -70.2048296348 , 72.8738253222 , 60.2450218115 , 114.2741231228 , + 46.8180775285 , 6.9915412654 , -8.9909197429 , -78.9165936808 , + 66.4731535459 , -68.4235455651 , -79.8254597080 , -10.6308477115 , + -62.6161569330 , -55.7744410292 , -11.8408366528 , 98.1034940997 , + 35.8213741877 , -54.4694482732 , 86.9631830044 , -53.0343838122 , + -47.4898642865 , -47.2010929590 , -31.3312639685 , -23.0908245172 , + 12.0258009869 , -5.1098204703 , -9.8420230737 , -107.3328761158, + 44.6810431959 , -17.9083820345 , -60.9753512872 , -7.5915088994 , + 17.2250813329 , 57.9176125648 , 124.3004161362 , -63.1950908493 , + 120.5788885640 , -44.1734238117 , -91.7408095116 , -43.5696066595 , + -49.9560710099 , -167.8513443296, -70.9437505499 , -46.4109705355 , + -64.2264526456 , -13.9995803916 , -100.9548186356, 9.9101010575 , + -50.0615130815 , -55.7590145012 , -60.3195153388 , 61.7913378549 , + -102.0850899209, 53.2360193126 , -25.8997883369 , 75.1445512333 , + -113.8148602310, 17.8027281119 , -19.5006822722 , -44.2169628471 , + 107.5017084384 , -113.7909124666, -43.9735396033 , 7.6880981388 , + 46.7384653508 , 9.9047443751 , 81.8646964362 , 132.3812863877 , + -95.6959050236 , -68.5015813484 , 65.8586404494 , 18.5039353889 , + -30.1786166621 , -90.3098515667 , -22.9356228552 , -20.5778272423 , + -2.2127786675 , -35.4418447703 , -51.8722915974 , -107.9024439078, + -51.5940748232 , -51.7463262677 , 74.2795485984 , 94.2205022462 , + 9.7016384049 , -47.3556083155 , -36.7822314478 , -151.6455525363, + -15.7183814485 , 78.2063383182 , 0.1516414969 , 37.9304181609 , + 20.6185902740 , -22.2164106778 , 6.1160554677 , 2.4061326953 , + -111.6681824598, -60.0858917090 , 75.1698614693 , -76.5787410444 , + 28.3391655715 , -2.4946186443 , -68.0378899682 , 104.0893199171 , + -51.8319647254 , 38.8521710524 , 75.9114239564 , 73.9206172905 , + -103.2533029987, 6.9002718274 , -36.6346436319 , -25.1990926265 , + 1.5852145953 , -50.6438436795 , 21.5018844428 , -151.9305562846, + -51.7326681814 , 21.4475994143 , 42.2564011921 , -74.0520586926 , + 49.7370635809 , -13.2957534126 , 36.6746826778 , -31.7005492589 , + 148.4894964268 , 79.7890632353 , 16.8856024809 , 16.1690460177 , + 39.2665169484 , 117.2461167794 , -37.4827984831 , -47.8387803604 , + -95.7025286193 , 34.3058214285 , -124.9536456028, 56.1640195764 , + 94.3636873606 , 35.3992852810 , -38.3920852159 , -100.5738062016, + -29.7837022314 , 42.9133913996 , -34.2715618187 , -14.3589115627 , + -16.5935468750 , 20.4574192236 , -88.7897972666 , -38.6285080386 , + 53.3203422726 , 98.5991486746 , 122.7305462474 , 67.7902817187 , + 5.1764117389 , 5.0632821624 , 21.9288789574 , -78.3140512638 , + -21.2069682335 , 23.6342010925 , 34.4445769455 , 59.1346766615 , + 28.9978778000 , 39.8121180845 , -17.1650033520 , -56.9174900874 , + 17.8157086148 , -112.8801457350, -122.4019040408, 140.8669393157 , + -65.4664329639 , 40.6952775518 , 32.7260891658 , -43.2565155866 , + 19.3945751928 , -20.1815002000 , -67.6601711640 , -18.1921178207 , + -35.6802153684 , 49.9550290306 , 131.4925251016 , -31.2940938167 , + -5.2848453344 , -109.5580577933, 20.2437599390 , -8.8782958734 , + 54.1836717264 , 7.2555852190 , -3.5698316137 , -51.9236786262 , + 6.7861547980 , -104.4814551670, 45.8458629668 , 70.0890876844 , + 38.3572837740 , 61.8024165129 , 68.0176962024 , -12.8193934080 , + -21.4661610917 , -0.9377108815 , -74.2100679061 , 71.0490808147 , + 91.9813889497 , -14.5797640164 , 3.5036749129 , -138.3605478356, + -48.1501349794 , -16.0636922482 , -12.1334197606 , 15.0562207637 , + -34.0878176054 , 55.1075126157 , 97.3829871877 , 0.2053358099 , + -94.8713267382 , 51.5460954054 , 21.2966946363 , 58.1331025047 , + -23.4599044132 , -19.3315856528 , -8.4497193577 , -1.9594679356 , + -33.1906549336 , -144.6825417978, -57.1218958072 , 35.7353406097 , + 61.4666549819 , 14.6536253128 , 82.1632196866 , -44.6230161723 , + -91.1022589278 , -18.5737673927 , -136.8975612334, 56.9606788003 , + 70.7059960183 , -68.2829345081 , -10.2629800455 , -53.6385325047 , + -68.7928766204 , 88.2444688302 , 83.1412324801 , -102.9206928160, + -68.2329763159 , -69.7552955469 , 108.2132269009 , -28.2582329307 , + 5.6685898328 , -36.0392956840 , 43.3269513128 , -8.6436416796 , + -16.5054886972 , 11.5008791788 , 39.6923606683 , -28.9039554061 , + 13.5938214364 , -23.6296332202 , 49.1171161163 , 53.1636857935 , + -62.9672053166 , -54.2594757384 , 48.3838956696 , 8.0469071555 , + -33.6472086213 , -120.5381752144, 55.0880453111 , 17.8990740563 , + 144.9402232336 , 101.7886229203 , -73.3666393712 , -16.4721379138 , + -12.7447935685 , 101.8245160983 , -49.7026860415 , -15.1227790364 , + 65.7430288442 , -131.8695390036, 10.2750933946 , 90.9752774838 , + -26.5859990591 , -95.6962772568 , 76.2174589344 , 24.8796848060 , + -38.8938223046 , 54.1687774852 , -37.3585968996 , -34.6848570502 , + 33.0151011570 , -55.8345877671 , -3.9009101671 , -31.5024971691 , + -9.6863895491 , 91.8719195957 , -58.9993249744 , -25.6887030614 , + -8.0829472205 , 4.6386491741 , -71.4019697167 , -21.3734669095 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81.8152755619 , -13.4979932982 , -21.4680758393 , -85.1088235539 , + -65.3610798409 , -35.0444139470 , -48.0220794487 , -41.6210317362 , + 33.1212995259 , -82.1480936443 , -10.5479715135 , 76.4601917004 , + 42.1983651157 , 92.6104239912 , -42.3536237955 , -24.5644182272 , + 30.4446637772 , -90.2899420489 , 63.6723540422 , 103.0895811428 , + 64.1706769263 , -10.7069812309 , 21.8927240409 , 6.3571071738 , + 57.1457649358 , -52.9866276448 , 66.0981829072 , -29.5372056881 , + -79.2252039810 , -136.2440652798, -57.0106422562 , 86.8203548141 , + 66.4244149837 , 53.3230426111 , -66.1283059222 , -131.0402660353, + 8.0548411081 , 122.9088988100 , 1.2626894208 , -60.5059112373 , + -68.8707203082 , -6.4747987200 , 85.8411327244 , 99.9624156733 , + 90.4197864338 , -35.9630441182 , -22.9158275507 , -17.3660128776 , + 16.7845345761 , 34.7219749782 , -39.3513765878 , 1.0460702756 , + -60.9494500182 , 20.0900333387 , -85.9636743832 , 88.4400782168 , + 15.0729628728 , 61.5499846243 , 11.8579871757 , 107.8617581581 , + -42.9393027864 , -62.8422307621 , -19.0589600542 , 4.0750325807 , + -36.0651825425 , 55.7638724501 , -10.4691736080 , -55.5672537178 , + -61.2061519915 , -21.1885348576 , -131.2535612498, 24.7463552676 , + 22.9426321237 , 14.3038202264 , -138.0926317438, -59.0892900856 , + -162.5416439986, 7.1307658250 , -141.1236672256, -4.7173618068 , + -16.7741532807 , -68.2615451173 , -2.6608701102 , 84.1978109826 , + -11.3446202072 , 59.9630033088 , -1.8994925010 , -37.9301641959 , + -119.4435600954, -11.4587491646 , 12.2423215240 , -7.3169898616 , + -67.0373621128 , 36.0198843055 , 53.9791315249 , -134.5885680695, + -83.8330811965 , -16.6714816463 , -8.8498552035 , -24.0513088196 , + -22.9444328877 , -37.7961441531 , 25.1975736186 , -136.1611637464, + -5.0843464033 , -10.3939554694 , 20.7422826935 , 75.6854136623 , + 46.4179626736 , -57.0052830175 , 7.3457235521 , -51.5504447254 , + -158.4375751701, -200.2426967181, -48.1234996261 , 1.6623945527 , + 21.1746524375 , 99.4092980367 , -2.3206772903 , 45.7989166757 , + 2.0181548348 , -88.0556010969 , -59.1527212096 , 47.3607925077 , + -10.4181140309 , 56.3558125650 , -8.9799125560 , -30.0376711812 , + -36.7132904688 , 35.7785050392 , -13.0763909369 , -2.1855594714 , + 18.1550954005 , -28.6711803575 , -55.4495172398 , -2.8812973198 , + -59.9575059158 , 40.0588875786 , 57.4713686602 , -3.2835144853 , + -36.7193552111 , -64.9415131516 , -166.9555466445, -23.5556853844 , + -54.9408569587 , -35.2310451959 , 21.3345143458 , 65.7590671151 , + 51.2214538168 , 46.1271939944 , -42.2235267919 , 127.2329928299 , + 105.2391778600 , 17.6726845966 , -129.9021148044, 8.7065613044 , + -94.0987112511 , -3.5375742950 , -23.1385452379 , 60.6219530633 , + 92.5445564235 , 48.5111974469 , -52.5699309159 , -60.0634811685 , + 25.9034368684 , 140.0249495491 , 1.5918852392 , 38.0266038291 , + 17.5588710703 , 3.4294066089 , -27.6748782173 , 59.6182974489 , + -35.2924781853 , -38.6198576115 , -13.6119803198 , 7.8375587489 , + 22.7250686519 , -28.3524510951 , -34.4269062817 , 22.6464817325 , + -61.6528147860 , -5.9782002429 , 61.4730771294 , 43.5582379527 , + 55.6862408270 , 87.8745651631 , 46.3401042715 , -19.8780979663 , + 74.1272633369 , 29.8590452377 , -12.8665765140 , 34.2931401219 , + 53.9279617551 , -16.9017895140 , -70.1527553166 , -79.6367897992 , + 109.3728271017 , -129.2214826835, -53.4644539730 , -51.5654458993 , + 17.6062148433 , 3.5090251835 , 74.2615941204 , -109.3431097845, + 40.1403465151 , 28.8714561280 , 94.0868659302 , -19.0047033845 , + -60.0967410050 , -19.0998457619 , -67.2027075128 , 72.0711434846 , + -17.8737851232 , 123.7050551274 , 132.6331504104 , 25.5018761009 , + -36.7817189239 , -29.1580893235 , -6.5848563828 , 90.2868948516 , + -35.7017258498 , -68.5675432955 , -52.4888589786 , 47.1377730021 , + -7.4546621940 , -52.0657517138 , -49.0404829633 , -114.6910280126, + -117.6819819437, -32.7856729408 , 31.8232065591 , 12.1192973039 , + 35.2678513420 , -1.0336778293 , 30.7021249679 , 127.0442906046 , + -84.8457819393 , 28.9862843096 , -47.3524701726 , -126.1094998460, + -2.9700276582 , -2.4956545870 , -53.8624121141 , -85.2114117637 , + 76.9057985618 , 137.1205201755 , -19.0830817212 , 14.3407526579 , + -56.5921994449 , -25.6084873186 , -44.9470801106 , -133.3139496090, + 0.3487447576 , 33.4499716730 , 34.7126257844 , -9.3307383323 , + 27.2996276947 , 10.8765676134 , -91.1032360444 , -90.9584216222 , + 1.6981490570 , 96.8557438791 , 56.7726390913 , -44.3246449237 , + 52.3260643361 , 21.5551140465 , 27.4535327381 , 2.0072717479 , + 7.4823125629 , 77.1185863870 , 16.1372262663 , -10.7206012957 +}; + +const float32_t controller_f32_coeffs[CONTROLLER_MAX_COEFFS_LEN] = +{ + /* S->Kp, S->Ki, S->Kd; */ + 0.0000000000 , -1.0336778293 , 56.7726390913 , + 0.3487447576 , 0.0000000000 , 27.4535327381 , + -29.1580893235, 1.6981490570 , 0.0000000000 , + 0.0000000000 , 0.0000000000 , -2.4956545870 , + 0.0000000000 , 8.7065613044 , 0.0000000000 , + 0.0000000000 , 0.0000000000 , 0.0000000000 , + 18.1550954005 , -5.9782002429 , 2.0072717479 , + 33.1212995259 , -82.1480936443, -10.5479715135, + -23.6296332202, 49.1171161163 , 53.1636857935 , + 7.2830326091 , 66.8368719314 , 33.9778190671 , + 9.4452708243 , 5.3300080251 , 39.0483916714 , + 6.9915412654 , -8.9909197429 , -78.9165936808 +}; + +const q31_t controller_q31_coeffs[CONTROLLER_MAX_COEFFS_LEN] = +{ + 0x00000000, 0xFEF760E4, 0x38C5CBAD, + 0x00594756, 0x00000000, 0x1B741AB9, + 0xE2D78775, 0x01B2B9E6, 0x00000000, + 0x00000000, 0x00000000, 0xFD811CC8, + 0x00000000, 0x08B4E134, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, + 0x1227B455, 0xFA0594AB, 0x0201DC90, + 0x211F0D7C, 0xADDA1689, 0xF573B824, + 0xE85ED05B, 0x311DFB52, 0x3529E750, + 0x074874D3, 0x42D63D3D, 0x21FA525A, + 0x0971FD45, 0x05547B68, 0x270C6366, + 0x06FDD5A6, 0xF7025315, 0xB1155A1E +}; + + +const q15_t controller_q15_coeffs[CONTROLLER_MAX_COEFFS_LEN] = +{ + 0x0000, 0xFEF7, 0x38C6, + 0x0059, 0x0000, 0x1B74, + 0xE2D8, 0x01B3, 0x0000, + 0x0000, 0x0000, 0xFD81, + 0x0000, 0x08B5, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x1228, 0xFA06, 0x0202, + 0x211F, 0xADDA, 0xF574, + 0xE85F, 0x311E, 0x352A, + 0x0748, 0x42D6, 0x21FA, + 0x0972, 0x0554, 0x270C, + 0x06FE, 0xF702, 0xB115 +}; diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c new file mode 100644 index 0000000..994dd0f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c @@ -0,0 +1,13 @@ +#include "jtest.h" +#include "controller_tests.h" + +JTEST_DEFINE_GROUP(controller_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_GROUP_CALL(pid_reset_tests); + JTEST_GROUP_CALL(pid_tests); + JTEST_GROUP_CALL(sin_cos_tests); + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c new file mode 100644 index 0000000..af534c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c @@ -0,0 +1,52 @@ +#include "jtest.h" +#include "arr_desc.h" +#include "arm_math.h" +#include "type_abbrev.h" +#include "test_templates.h" + +/* Bucket of zeros. For comparison with the output of arm_pid_reset_xxx. */ +ARR_DESC_DEFINE(float32_t, zeroes, 3, CURLY(0)); + +/** + * Define a JTEST_TEST_t for the function arm_pid_reset_xxx function having + * suffix. + */ +#define ARM_PID_RESET_TEST(suffix) \ + JTEST_DEFINE_TEST(arm_pid_reset_##suffix##_test, \ + arm_pid_reset_##suffix) \ + { \ + /* Initialise the pid_instance */ \ + arm_pid_instance_##suffix pid_inst = { 0 }; \ + pid_inst.state[0] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff; \ + pid_inst.state[1] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff; \ + pid_inst.state[2] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff; \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES(arm_pid_reset_##suffix(&pid_inst)); \ + \ + /* Test correctness */ \ + TEST_ASSERT_BUFFERS_EQUAL( \ + pid_inst.state, \ + zeroes.data_ptr, \ + 3 * sizeof(TYPE_FROM_ABBREV(suffix))); \ + \ + return JTEST_TEST_PASSED; \ + } + +ARM_PID_RESET_TEST(f32); +ARM_PID_RESET_TEST(q31); +ARM_PID_RESET_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(pid_reset_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_pid_reset_f32_test); + JTEST_TEST_CALL(arm_pid_reset_q31_test); + JTEST_TEST_CALL(arm_pid_reset_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c new file mode 100644 index 0000000..09fab0a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c @@ -0,0 +1,79 @@ +#include "jtest.h" +#include "arr_desc.h" +#include "arm_math.h" +#include "ref.h" +#include "type_abbrev.h" +#include "test_templates.h" +#include "controller_test_data.h" +#include "controller_templates.h" + +/** + * Define a JTEST_TEST_t for the function arm_pid_xxx function having + * suffix. + */ +#define ARM_PID_TEST(suffix,type) \ + JTEST_DEFINE_TEST(arm_pid_##suffix##_test, arm_pid_##suffix) \ + { \ + uint32_t i,j; \ + \ + arm_pid_instance_##suffix fut_pid_inst = { 0 }; \ + arm_pid_instance_##suffix ref_pid_inst = { 0 }; \ + \ + for(i=0;i 0 ? (x) : -(x)) + +/* + Function to test correctness of sin_cos output by comparing it with reference library +*/ +#define COMPARISON_INTERFACE(type, threshold) \ + if ( (ABS((type) sin_val_ref - (type) sin_val_fut) > \ + (type) threshold ) || \ + (ABS((type) cos_val_ref - (type) cos_val_fut) > \ + (type) threshold)) \ + { \ + JTEST_DUMP_STRF("Error: %f %f\n", \ + ABS((type) sin_val_ref - (type) sin_val_fut), \ + ABS((type) cos_val_ref - (type) cos_val_fut)); \ + return JTEST_TEST_FAILED; \ + } + +/* + Sine and cosine test function for float32_t input +*/ +JTEST_DEFINE_TEST(arm_sin_cos_f32_test, arm_sin_cos_f32) +{ + /* Test function for all input degree values */ + TEMPLATE_DO_ARR_DESC( + degree_idx, TYPE_FROM_ABBREV(f32), + degree, arm_sin_cos_degrees_f32 + , + /* Display cycle count and run test */ + JTEST_COUNT_CYCLES( + arm_sin_cos_f32( + degree, + (TYPE_FROM_ABBREV(f32) *) &sin_val_fut, + (TYPE_FROM_ABBREV(f32) *) &cos_val_fut) + ); + ref_sin_cos_f32( + degree, + (TYPE_FROM_ABBREV(f32) *) &sin_val_ref, + (TYPE_FROM_ABBREV(f32) *) &cos_val_ref); + + /* Test correctness */ + COMPARISON_INTERFACE( + TYPE_FROM_ABBREV(f32), + MAX_DELTA_f32)); + + return JTEST_TEST_PASSED; +} + + +/* + Sine and cosine test function for q31_t input +*/ +JTEST_DEFINE_TEST(arm_sin_cos_q31_test, + arm_sin_cos_q31) +{ + /* Test function for all input degree values */ + TEMPLATE_DO_ARR_DESC( + degree_idx, TYPE_FROM_ABBREV(q31), + degree, arm_sin_cos_degrees_q31 + , + /* Display cycle count and run test */ + JTEST_COUNT_CYCLES( + arm_sin_cos_q31( + degree, + (TYPE_FROM_ABBREV(q31) *) &sin_val_fut, + (TYPE_FROM_ABBREV(q31) *) &cos_val_fut) + ); + ref_sin_cos_q31( + degree, + (TYPE_FROM_ABBREV(q31) *) &sin_val_ref, + (TYPE_FROM_ABBREV(q31) *) &cos_val_ref); + + /* Convert q31 numbers to float for comparison purposes. */ + ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &sin_val_fut, &sin_val_fut, 1); + ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &cos_val_fut, &cos_val_fut, 1); + ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &sin_val_ref, &sin_val_ref, 1); + ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &cos_val_ref, &cos_val_ref, 1); + + /* Test correctness */ + COMPARISON_INTERFACE( + TYPE_FROM_ABBREV(f32), + MAX_DELTA_f32)); + + return JTEST_TEST_PASSED; +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(sin_cos_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_sin_cos_f32_test); + JTEST_TEST_CALL(arm_sin_cos_q31_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c new file mode 100644 index 0000000..7b259c9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c @@ -0,0 +1,38 @@ +#include "jtest.h" +#include "ref.h" +#include "arr_desc.h" +#include "fast_math_templates.h" +#include "fast_math_test_data.h" +#include "type_abbrev.h" + +SQRT_TEST_TEMPLATE_ELT1(q31); +SQRT_TEST_TEMPLATE_ELT1(q15); + +SIN_COS_TEST_TEMPLATE_ELT1(f32, float32_t, sin); +SIN_COS_TEST_TEMPLATE_ELT1(q31, q31_t, sin); +SIN_COS_TEST_TEMPLATE_ELT1(q15, q15_t, sin); + +SIN_COS_TEST_TEMPLATE_ELT1(f32, float32_t, cos); +SIN_COS_TEST_TEMPLATE_ELT1(q31, q31_t, cos); +SIN_COS_TEST_TEMPLATE_ELT1(q15, q15_t, cos); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(fast_math_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_sqrt_q31_test); + JTEST_TEST_CALL(arm_sqrt_q15_test); + + JTEST_TEST_CALL(arm_sin_f32_test); + JTEST_TEST_CALL(arm_sin_q31_test); + JTEST_TEST_CALL(arm_sin_q15_test); + + JTEST_TEST_CALL(arm_cos_f32_test); + JTEST_TEST_CALL(arm_cos_q31_test); + JTEST_TEST_CALL(arm_cos_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c new file mode 100644 index 0000000..db74d35 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c @@ -0,0 +1,370 @@ +#include "fast_math_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +float32_t fast_math_output_fut[FAST_MATH_MAX_LEN] = {0}; +float32_t fast_math_output_ref[FAST_MATH_MAX_LEN] = {0}; +float32_t fast_math_output_f32_fut[FAST_MATH_MAX_LEN] = {0}; +float32_t fast_math_output_f32_ref[FAST_MATH_MAX_LEN] = {0}; + +const q31_t fast_math_q31_inputs[FAST_MATH_MAX_LEN] = +{ + 0x414A5524, 0x4CAB5A17, 0x2D6F5B56, 0x7DAF4E3B, 0x29B226EB, 0x41F6F6A , + 0x25CE38BF, 0x3A970AFA, 0x3A44382A, 0x05540F8 , 0x3D060524, 0x13D56570, + 0x17D7791D, 0x7FE0438C, 0x26741841, 0x40A66E54, 0x218E4386, 0x39FF3726, + 0x0DC177CA, 0x702F2CF5, 0x41142FF1, 0x6C1476AB, 0x15F640DD, 0x662C4E49, + 0x38055E7E, 0x770871FE, 0x4F8B5360, 0x0D1928A0, 0x57647821, 0x258558CF, + 0x0C0C604D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0x36462E24, 0x6CE00F5C, + 0x66D40948, 0x355B5831, 0x3B72150A, 0x1EB61530, 0x73394127, 0x773F26F4, + 0x18052980, 0x038D6587, 0x1CF517F4, 0x22AD1691, 0x7A812473, 0x7CDC7D7F, + 0x4A5110D0, 0x6D895BB9, 0x0FD60F35, 0x1A215530, 0x20EB6DDA, 0x3DE62516, + 0x250123E1, 0x5ED813C8, 0x61E175B1, 0x2CBB32F3, 0x6D350907, 0x5B140D7E, + 0x6EAE272D, 0x3E221841, 0x418B7B88, 0x26BB1B80, 0x3CF010E4, 0x24DB166C, + 0x79AB7E42, 0x62DF28D1, 0x47004665, 0x63F56FC6, 0x419E0C75, 0x46BE1F38, + 0x243239B2, 0x758D03E0, 0x5CE12926, 0x3F574B74, 0x1F4458E2, 0x71D5639 , + 0x03A17B49, 0x173A7C76, 0x06EF7531, 0x48D32F34, 0x7D3E3063, 0x0F2F3549, + 0x5C314C9 , 0x18CB6B6D, 0x26F83697, 0x447B1E9C, 0x2E323A33, 0x50745715, + 0x01AC5746, 0x655A4E04, 0x4891060F, 0x1DA36B4F, 0x60E6227F, 0x20BF5EB4, + 0x50B3225B, 0x40C10544, 0x415656C , 0x15405EAE, 0x185863E1, 0x236A1C4E, + 0x08BD21F9, 0x2ACF7A68, 0x773665E5, 0x4EDF5F66, 0x617A1610, 0x524F4968, + 0x42D006CD, 0x5F000079, 0x24DC2447, 0x6A4F5599, 0x37064D4A, 0x1DE70608, + 0x233A2EE5, 0x137E488E, 0x18061B7B, 0x4079569D, 0x24A817D5, 0x44CE48F5, + 0x575F7883, 0x22406802, 0x71AD70BB, 0x1D4A5D79, 0x3CBC7CE4, 0x335840D8, + 0x05792E47, 0x27AD2C05, 0x3D196EAB, 0x331A40AF, 0x33035831, 0x13D93987, + 0x7C542094, 0x045F317E, 0x5DC43F8B, 0x1379650C, 0x5C20193F, 0x7DD50298, + 0x1D482B82, 0x4A6B6062, 0x5C8A757B, 0x272917C1, 0x10E16FBC, 0x355A5882, + 0x66F86A35, 0x604555A1, 0x7DF7FBB , 0x758A6216, 0x1A113463, 0x53541BAD, + 0x21576756, 0x483B6D8D, 0x1F052FCC, 0x4EA63DFB, 0x55B84677, 0x7B2E04F2, + 0x787A796C, 0x04A12CD3, 0x46029BD , 0x1DB22DD8, 0x1A8C7F28, 0x061E452E, + 0x132D3F78, 0x76525852, 0x73357BBA, 0x6BBB0A58, 0x62536AFA, 0x3F6B65EF, + 0x6DC57B58, 0x1EB718CE, 0x66B02740, 0x5FF60B47, 0x32477B8F, 0x7FF35302, + 0x29FD3E40, 0x475A43D1, 0x6FF9528A, 0x2018209D, 0x47E079C9, 0x4CF576D3, + 0x28074E34, 0x5D6F58ED, 0x234045D1, 0x51CE35F9, 0x25297896, 0x644320FE, + 0x0F4449A9, 0x54C361C6, 0x701D52F1, 0x4E094820, 0x718F0810, 0x61540689, + 0x79DE5A1F, 0x52865C23, 0x48AC3A4B, 0x6A0C1BE0, 0x21B705DB, 0x7086465D, + 0x1CC10929, 0x1E1D716E, 0x6D231D4C, 0x20495108, 0x38FF1971, 0x149C78D4, + 0x441F1E8B, 0x43D95372, 0x69C324B4, 0x210B7DC9, 0x47815E78, 0x02476137, + 0x6163DDF , 0x390D6EC2, 0x2F684E5B, 0x0E680ABD, 0x02232615, 0x12593380, + 0x7B1465FE, 0x065A6957, 0x130F53EB, 0x6D772EF7, 0x10E916B6, 0x63BC7A68, + 0x2ACB00BB, 0x651C5590, 0x194714B5, 0x730904EE, 0x59BB61B4, 0x34867DBC, + 0x391C706C, 0x3C164218, 0x28931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, + 0x4B167FD4, 0x66902F4C, 0x7A794932, 0x54B152C , 0x30856EA9, 0x39466D55, + 0x36696451, 0x0F5B1E8C, 0x077A3C6A, 0x51B956B4, 0x367E2D2A, 0x1D2C662A, + 0x78FB6880, 0x4E6D40B6, 0x40706FDC, 0x4DF9679C, 0x20306EDB, 0x63812AE7, + 0x255D2748, 0x1B8B617B, 0x3E036FAD, 0x04E444A7, 0x55A37517, 0x669B2988, + 0x18FD5E8C, 0x67BD05CE, 0x34BB346C, 0x76994800, 0x05B958B6, 0x6DFA2FEF, + 0x2055B5C , 0x1F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB90B61, 0x43235DAC, + 0x31D424B4, 0x768C0D7E, 0x162F2F9D, 0x7B2A7A99, 0x79392693, 0x442D12C0, + 0x0692273E, 0x59A16E80, 0x5D956856, 0x44E73DAC, 0x0D874532, 0x5F5C1DD0, + 0x5D167858, 0x05597EA2, 0x1D821476, 0x59654ED2, 0x594C0DC7, 0x1A873506, + 0x3F693200, 0x7A651AB5, 0x20CC3C8A, 0x1F9E662C, 0x78E7631 , 0x2A01DA0 , + 0x3088472F, 0x12EE0D42, 0x360D4D5F, 0x73337E48, 0x0D634C06, 0x233A0ACB, + 0x706651ED, 0x7AA54079, 0x262239D1, 0x3EBB6BB6, 0x225A4F3D, 0x32581A06, + 0x6E6F5780, 0x577377C7, 0x75ED1DDC, 0x10DF2D15, 0x3C7929BC, 0x37175917, + 0x354E381C, 0x762A2DD7, 0x76435AC1, 0x73BB749E, 0x52FE4E7E, 0x6C8140F4, + 0x57694875, 0x12D30822, 0x474227CF, 0x37926D98, 0x121C7E24, 0x204E1EE7, + 0x58C6268 , 0x2152080 , 0x316C3323, 0x7AB14A31, 0x61C13C03, 0x7D8E74F1, + 0x73F446D0, 0x6C6C6A0A, 0x3BFD79FB, 0x67242969, 0x3E5524EB, 0x0FF5534 , + 0x52F05F1C, 0x17102DE3, 0x540F4A21, 0x798468E7, 0x419545EB, 0x193F7880, + 0x2B246B20, 0x408A2BC4, 0x4BF66A49, 0x40894C55, 0x4CAA6398, 0x247856E9, + 0x2F2A647D, 0x22F55D33, 0x70D37915, 0x50634C72, 0x5983671 , 0x2BCC5AF8, + 0x1A77D48 , 0x411B5CFA, 0x71074D7E, 0x3A6B3593, 0x61425F05, 0x6271012A, + 0x5B830310, 0x3D8418CA, 0x10A50792, 0x239F7137, 0x213D5071, 0x7F9930D4, + 0x2462664F, 0x54180F8E, 0x291505BA, 0x6586387A, 0x144B2C12, 0x18E425C7, + 0x3AA43373, 0x18F0503C, 0x19462AC0, 0x58B452EF, 0x72473895, 0x26BF5435, + 0x6DA553B , 0x60912FA6, 0x5C337331, 0x3D93CD7 , 0x4D035752, 0x20691929, + 0x389962F9, 0x36E701E9, 0x758B642C, 0x5FCA69E3, 0x596027F4, 0x2D5A2FD0, + 0x5F18324A, 0x3DB165AA, 0x76BA3876, 0x1BC21AF6, 0x3CC10841, 0x73A60174, + 0x625B7F58, 0x67C57724, 0x4458653C, 0x61573095, 0x2B370837, 0x03DF6CE3, + 0x5D086EFA, 0x3F5227C2, 0x191B4785, 0x60843D82, 0x30DE11F1, 0x105E226C, + 0x6E1C7AA2, 0x47AA5D14, 0x36676D03, 0x3B8D4DF6, 0x7372694 , 0x409521DC, + 0x744206A , 0x4722023F, 0x2BE46AD5, 0x63E11D76, 0x4A4A09AB, 0x5CF252B9, + 0x31586916, 0x4DFD7D84, 0x32037634, 0x2D7329D4, 0x4524582F, 0x2E5366C1, + 0x3B0E019B, 0x38530C6A, 0x6A2542D , 0x0A6A00E5, 0x119725CC, 0x54065347, + 0x1B6F7AF1, 0x6CCF71F1, 0x181117F2, 0x71674A76, 0x74F43880, 0x77A55F47, + 0x59EA5B62, 0x4A331D95, 0x3CBB276F, 0x245C4D50, 0x4718D5 , 0x07CE05D1, + 0x60D47AD5, 0x25CA1C40, 0x30061766, 0x669B39DF, 0x3D5F1320, 0x19306AD3, + 0x28B30325, 0x0DD090F , 0x6A6E6F37, 0x2DF16F66, 0x2B514C7E, 0x31101C58, + 0x7D4847FC, 0x515341CA, 0x77AB0EA6, 0x41320DAF, 0x3AF8531E, 0x24B31611, + 0x6D377331, 0x7A832A22, 0x222511C7, 0x722D1F89, 0x3B194F18, 0x261B0A4D, + 0x43F676DB, 0x4F8C6D61, 0x190F2250, 0x202E72A9, 0x560D4EA2, 0x308E67B4, + 0x36746663, 0x17CC3852, 0x27EB2EAC, 0x7FDE0AA8, 0x264719A , 0x23261EDD, + 0x3C0B339E, 0x06284D40, 0x48D82ECB, 0x24D44CF8, 0x43631B91, 0x4BF04248, + 0x36497B9B, 0x68273C58, 0x630B7AF9, 0x20CC3F26, 0x6C3B7B71, 0x574433ED, + 0x7A2552F6, 0x4CDE642D, 0x565B0142, 0x26F9207F, 0x67A207BE, 0x5B506684, + 0x44DA4780, 0x11756A0C, 0x156104AF, 0x415561B0, 0x6E3A6886, 0x1DBA1EA2, + 0x542359C8, 0x4C024E22, 0x758F052A, 0x1DD6395 , 0x2D194BAD, 0x616475A1, + 0x42084602, 0x09C274AD, 0x13CB5562, 0x57FE2D5B, 0x607A4EE5, 0x16723A91, + 0x4F624CCF, 0x2E5E24A3, 0x28FE6FAF, 0x3DDA6EF4, 0x32AF540C, 0x19A57B3B, + 0x5D1D73A3, 0x23424B3E, 0x278445F5, 0x53971C3B, 0x427D7943, 0x5221358C, + 0x26CE1A5E, 0x7B506CA4, 0x3B86636E, 0x60831F6D, 0x45E142F3, 0x21B77B04, + 0x7BB65E0C, 0x78B80F5E, 0x7D8D172B, 0x3BF33A90, 0x2D572D9 , 0x2B5B4920, + 0x36A05E01, 0x52745306, 0x47C64855, 0x1CAA669B, 0x304A2641, 0x4D6B1760, + 0x3E176D79, 0x523241B0, 0x24A67957, 0x4BDE76AF, 0x4E5F1493, 0x4C215DA5, + 0x33A052B , 0x1A4D00C2, 0x40AE6BCA, 0x390D106B, 0x69E86018, 0x5AF356CF, + 0x63561D4 , 0x44F31C6 , 0x14B6299B, 0x0D2E25F0, 0x4CBF132A, 0x45AC18B6, + 0x2227567D, 0x06B54E2F, 0x26344534, 0x22C515EC, 0x2442370D, 0x6C3721C6, + 0x34EF687D, 0x1C06323A, 0x6AF36A60, 0x60396F52, 0x6AE70AA1, 0x49D06CBC, + 0x6F9576C8, 0x584C4258, 0x3A9A27BB, 0x66DF0D47, 0x1D4804EA, 0x57DD1E67, + 0x789C7895, 0x75336111, 0x25C122C8, 0x62742114, 0x4FBF6D26, 0x3F9F6482, + 0x66F02CD9, 0x11083202, 0x499E2618, 0x7EBC1351, 0x440112F1, 0x49DF7BC1, + 0x3BF45C25, 0x31BA7FA0, 0x61AF1AED, 0x6B1F7D29, 0x2D865294, 0x63E01129, + 0x7E9E77A5, 0x100435D7, 0x1FE3A71 , 0x08597C81, 0x722849FA, 0x31C520AF, + 0x7BA178DC, 0x7F102D31, 0x5CA07864, 0x150E6F98, 0x02C34882, 0x5D041F11, + 0x0C613C57, 0x53984FD1, 0x426F38AD, 0x55992B1D, 0x7AFA078D, 0x2B253413, + 0x594B32CF, 0x32887E38, 0x28933B46, 0x1A0B4168, 0x291B4A94, 0x653A5E8D, + 0x21746BBE, 0x5EFE6415, 0x30DA429C, 0x50C5640C, 0x34711AA4, 0x529C67A6, + 0x105957CD, 0x4D287499, 0x03CA0AA7, 0x28385832, 0x25A04A02, 0x420D47A4, + 0x35627556, 0x4BC11E4C, 0x59E215C7, 0x27E838B4, 0x458612F4, 0x22827F6F, + 0x449D4DBA, 0x679B7362, 0x4E495845, 0x4FD270D1, 0x395E76A0, 0x375A655E, + 0x12E2058F, 0x73F970CA, 0x61EF73B3, 0x51FF5362, 0x67410345, 0x7FDA0B3B, + 0x221962E8, 0x17AB6543, 0x26557412, 0x4B30084D, 0x268E191D, 0x7E0D13DF, + 0x73EF127D, 0x4DEC5DB1, 0x77FA745F, 0x56002898, 0x12DD0A40, 0x157F6DDF, + 0x42A55F8E, 0x43597924, 0x7B630C3F, 0x338B6B58, 0x32945F75, 0x4FA23A0E, + 0x036E38C0, 0x33B18FD , 0x06114337, 0x24660ACB, 0x19BB02F0, 0x124C0A47, + 0x3A951701, 0x01155ABF, 0x0C612D71, 0x36074CA7, 0x51660C41, 0x635F58C7, + 0x7FC2002D, 0x0E6A7CF3, 0x65B07D07, 0x015F6A6B, 0x791B70DD, 0x6E475719, + 0x424314C7, 0x68426EB , 0x71942FEE, 0x464A2F52, 0x677579FD, 0x6BA775AE, + 0x1F66EFF , 0x1A795237, 0x78D9545F, 0x1D0B344D, 0x3BD34AB7, 0x2F85312A, + 0x16C542AD, 0x3990185D, 0x08DF3351, 0x02811AA5, 0x6D351F41, 0x4066269D, + 0x06B660BF, 0x6EDB4768, 0x5DD70CF0, 0x35D74F6E, 0x689E220C, 0x11431687, + 0x147C49C9, 0x385762BD, 0x302F0AE4, 0x1DAB67F8, 0x483256C9, 0x37D50FCB, + 0x4EA82711, 0x4D7B2C98, 0x19DB78BC, 0x58DE0DC2, 0x6AFF7E7B, 0x37621C93, + 0x792C6E19, 0x77001192, 0x7F88439D, 0x2E196A66, 0x6C71378C, 0x6AF43B3A, + 0x7C16225E, 0x6687337 , 0x4BEE1608, 0x6D5B5552, 0x345D4590, 0x681209CC, + 0x7B242819, 0x508A1416, 0x19880FE3, 0x1FC7288A, 0x24BD0502, 0x6A1D1678, + 0x20E6CA0 , 0x59BE2057, 0x5ADE11EB, 0x5EA8649D, 0x7A200E6F, 0x1149481D, + 0x72281E93, 0x0A5B0451, 0x67312D58, 0x63B849F1, 0x52217960, 0x7CDF59F3, + 0x33C775C0, 0x1EBA0799, 0x7DF1506 , 0x34E96110, 0x38FC73E3, 0x5EA059B2, + 0x022936EA, 0x316406F6, 0x43911185, 0x6C0D10F3, 0x1C6F3DF8, 0x38DB12A9, + 0x5CD41244, 0x2C9F0A7B, 0x5F4A315F, 0x77CE1C66, 0x4C800860, 0x318D53E0, + 0x7105420D, 0x575361F2, 0x750810BA, 0x217E4CA5, 0x2010140 , 0x4D884763, + 0x42BB0DA7, 0x32D53A74, 0x141C6CD4, 0x087F5FC3, 0x464B53 , 0x2D2A05F6, + 0x15532B45, 0x5D5C3CE1, 0x3EB9216A, 0x2214611B, 0x1FC52C5F, 0x11AE5DD7, + 0x20B925A9, 0x7C640AF4, 0x740009AC, 0x6D0E0321, 0x38E6A61 , 0x09104544, + 0x474F26C8, 0x15254CF3, 0x341A6B59, 0x661904CE, 0x598B2197, 0x2412659D, + 0x61976DD4, 0x329B3E16, 0x08FD1FB0, 0x304006F3, 0x3456309 , 0x55CC15F1, + 0x59DA7630, 0x5C801335, 0x0036D52 , 0x353775A5, 0x299476EB, 0x75280568, + 0x766F5264, 0x2EA233A6, 0x647619F3, 0x7FB30C7A, 0x1BC03B9 , 0x36BC3061, + 0x3F30596E, 0x3E2A527B, 0x0AC04220, 0x641979A3, 0x1ECC3B89, 0x21447BC1, + 0x4E8F2E26, 0x0C5A1D90, 0x299E5467, 0x57C947E3, 0x1D4865ED, 0x76F31C3D, + 0x4EE81CDF, 0x3479195E, 0x6FFB3AE1, 0x5C82398 , 0x300F7364, 0x47940AFA, + 0x3B853E3E, 0x598C440D, 0x224A3D89, 0x3A674204, 0x22880A38, 0x2E77F2D , + 0x22841C9C, 0x4F0609C3, 0x1FE90922, 0x09335017, 0x2D6B69A7, 0x7EDB63F9, + 0x099A74EF, 0x1F9F1B40, 0x24BE17E8, 0x251D2F7A, 0x16AC50D3, 0x28D7ED6 , + 0x6D193443, 0x76156F1B, 0x30DF6A4E, 0x64FF6794, 0x63DB2C9A, 0x74353022, + 0x556E025C, 0x23802AF9, 0x425018A4, 0x675A18BB, 0x70B227B9, 0x7FB01BF , + 0x63E7910 , 0x6C661591, 0x65745D2B, 0x4F6E379D, 0x52B32FAC, 0x1E6A1101, + 0x1DE22385, 0x2338191F, 0x469704B6, 0x4BAB4599, 0x54EB4809, 0x78393E6D, + 0x550017DD, 0x39B120E1, 0x288D52D3, 0x2D52668C, 0x20D22A68, 0x4E1207D1, + 0x3FCC0EFE, 0x47F37E64, 0x25177A90, 0x34BF5D4D, 0x5A8D3DCE, 0x6F7275A8, + 0x6BEA2655, 0x2A1810FC, 0x64DB593A, 0x0A4D4BC0, 0x2C402E93, 0x71C077F9, + 0x6F0C4577, 0x70412414, 0x752F1DC1, 0x582E38EA, 0x2C455F7B, 0x4DCD4EDB, + 0x12BC2696, 0x7B037135, 0x4FCA1F8C, 0x3D5E75F6, 0x502F41B0, 0x361653F1, + 0x2E5B0E31, 0x20266B19, 0x57E703D7, 0x467B3E00, 0x47032BA3, 0x1F776B9C, + 0x62570A84, 0x7EC75B48, 0x1BD5012 , 0x7D0A2D5D, 0x7FCC29F2, 0x291304B6, + 0x19D558ED, 0x47551C8 , 0x7D12738F, 0x3ADE0892, 0x5F741997, 0x25D2E2F , + 0x2B9F2269, 0x5C134FED, 0x15E92399, 0x54437F4E, 0x272D32AB, 0x56186AA1, + 0x7E4D355C, 0x234D7836, 0x2A871760, 0x4637A94 , 0x2C183207, 0x5FC78B3 , + 0x7F10621E, 0x276966B2, 0x6C9F4A11, 0x4E3F182C, 0x62BA2EF5, 0x25F239CD, + 0x73D63FED, 0x636E1F5E, 0x0AC15A0E, 0x3F3D33EB, 0x738326EA, 0x35C366B1, + 0x4D476E86, 0x02F63208, 0x711A1FC1, 0x426A4396, 0x7E4D1B93, 0x75E46DB7, + 0x2F3C44A7, 0x51A56F5C, 0x7AD2463D, 0x0A5639CA, 0x49952C78, 0x4C4B64F6, + 0x3AFE7F8D, 0x66993D04, 0x43867F37, 0x4BC146C2, 0x55A875EC, 0x681A1A75, + 0x30A67E1B, 0x4A4A7D0C, 0x20F77993, 0x1891805 , 0x738976AD, 0x542667D6, + 0x3C5C6EBF, 0x4499187F, 0x2BF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, + 0x421B4F29, 0x76740F9C, 0x09163B8D, 0x3D72AAB , 0x1AD54DD7, 0x754946EE, + 0x7317342B, 0x218546D4, 0x10563DA7, 0x54BB4CCE, 0x0CE63E46, 0x5D146234, + 0x33BE6C63, 0x325044E5, 0x09D72335, 0x07C36BA , 0x365530CC, 0x2DFA448C, + 0x1663516F, 0x59B00AA , 0x150274EA, 0x12532D4A, 0x3CEF002D, 0x492F3DA5, + 0x263A2574, 0x6F8005C2, 0x14A10651, 0x2F627ABA, 0x68293238, 0x26987646, + 0x52590516, 0x10144D36, 0x59B151B9, 0x2B2A4F05, 0x53953699, 0x27851C75, + 0x180646F3, 0x2E970306, 0x32843145, 0x18F4FE8F +}; + +/* The source data is random across the q31_t range. Accessing it by word should + remain random. */ +const q15_t * fast_math_q15_inputs = (q15_t *) fast_math_q31_inputs; + +const float32_t fast_math_f32_inputs[FAST_MATH_MAX_LEN] = +{ + /* Special values close to increments of pi/2 */ + -0.0, 0.0, -1.5E-07, 1.5E-07, 1.5707964, 1.5707965, + -1.5707964, -1.5707965, 3.1415925, 3.1415927, -3.1415925, -3.1415927, + 6.2831855, 6.283186, -6.2831855, -6.283186, + + /* Test some slightly larger values too */ + 10.1, -13.2, + + /* Random values (0, 2pi) */ + -1.3684878, 1.1444261, 0.2627620, 0.6719343, 3.8732286, 5.9040643, + -2.2271110, 2.5800587, 6.1848498, 5.9412493, 4.2514839, 6.2096863, + -4.8181437, 2.1155439, 4.1618680, 1.5341357, 1.8567268, 4.2736867, + -3.3165594, 2.5861183, 3.7864876, 4.7156566, 3.6664471, 3.4670146, + -3.6666823, 3.2158594, 0.5189454, 4.5211925, 6.2590334, 2.2276047, + -6.1025991, 2.1768018, 5.5703194, 2.8569321, 2.5976403, 1.3680509, + -0.7895111, 1.9409676, 4.5622487, 4.9189303, 4.3591961, 0.0615894, + -5.2980657, 5.7951829, 4.8440482, 0.2680398, 2.3762136, 4.4254964, + -4.5836656, 1.4091744, 1.6905207, 4.2287795, 3.0001720, 3.9189258, + -1.4856273, 1.1129014, 5.2128031, 4.8187110, 5.8715002, 0.6778860, + -1.1449692, 0.6226340, 3.0772767, 1.2141962, 5.6290528, 0.6225986, + -0.2775005, 3.5015887, 4.8537297, 1.9599772, 1.1245801, 2.1297213, + -1.3203840, 3.2053828, 5.6948550, 3.9516457, 0.6379562, 2.4558128, + -0.3431663, 3.1496534, 2.7125841, 6.2678565, 5.0994494, 3.0514394, + -5.6199810, 0.8642307, 2.4504731, 5.8267510, 5.7647838, 4.4835177, + 3.8851284, 2.1569414, 5.8812331, 0.7839784, 4.5904032, 4.0619375, + 5.2348483, 2.5024810, 4.7112719, 5.2478452, 2.0260784, 3.4699621, + 6.1520498, 3.4514073, 2.0761128, 3.8922546, 2.2659464, 4.7532896, + 2.6006151, 3.0934955, 4.3652005, 6.1118673, 2.0593452, 5.2640727, + 4.6437278, 5.9952549, 0.2005758, 2.2422740, 4.1635768, 1.7687265, + 1.4475395, 4.4681525, 3.9243074, 3.7109036, 4.1496541, 0.2987948, + 2.1914796, 2.8358565, 1.5136507, 4.4927603, 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a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c new file mode 100644 index 0000000..a6837f7 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c @@ -0,0 +1,244 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +#define BIQUAD_DEFINE_TEST(suffix, instance_name, config_suffix, output_type) \ + JTEST_DEFINE_TEST(arm_biquad_cascade_##config_suffix##_##suffix##_test, \ + arm_biquad_cascade_##config_suffix##_##suffix) \ + { \ + instance_name biquad_inst_fut = { 0 }; \ + instance_name biquad_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numstages_idx, uint16_t, numStages, filtering_numstages \ + , \ + /* Initialize the BIQUAD Instances */ \ + arm_biquad_cascade_##config_suffix##_init_##suffix( \ + &biquad_inst_fut, numStages, \ + (output_type*)filtering_coeffs_b_##suffix, \ + (void *) filtering_pState); \ + \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Stages: %d\n", \ + (int)blockSize, \ + (int)numStages); \ + \ + JTEST_COUNT_CYCLES( \ + arm_biquad_cascade_##config_suffix##_##suffix( \ + &biquad_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_biquad_cascade_##config_suffix##_init_##suffix( \ + &biquad_inst_ref, numStages, \ + (output_type*)filtering_coeffs_b_##suffix, \ + (void *) filtering_pState); \ + \ + ref_biquad_cascade_##config_suffix##_##suffix( \ + &biquad_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(suffix, config_suffix, speed, output_type) \ + JTEST_DEFINE_TEST(arm_biquad_cascade_##config_suffix##speed##_##suffix##_test, \ + arm_biquad_cascade_##config_suffix##speed##_##suffix) \ + { \ + arm_biquad_casd_##config_suffix##_inst_##suffix biquad_inst_fut = { 0 }; \ + arm_biquad_casd_##config_suffix##_inst_##suffix biquad_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numstages_idx, uint16_t, numStages, filtering_numstages \ + , \ + TEMPLATE_DO_ARR_DESC( \ + postshifts_idx, uint8_t, postShift, filtering_postshifts \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Stages: %d\n" \ + "Post Shift: %d\n", \ + (int)blockSize, \ + (int)numStages, \ + (int)postShift); \ + \ + /* Initialize the BIQUAD Instances */ \ + arm_biquad_cascade_##config_suffix##_init_##suffix( \ + &biquad_inst_fut, numStages, \ + (output_type*)filtering_coeffs_b_##suffix, \ + (void *) filtering_pState, postShift); \ + \ + JTEST_COUNT_CYCLES( \ + arm_biquad_cascade_##config_suffix##speed##_##suffix( \ + &biquad_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_biquad_cascade_##config_suffix##_init_##suffix( \ + &biquad_inst_ref, numStages, \ + (output_type*)filtering_coeffs_b_##suffix, \ + (void *) filtering_pState, postShift); \ + \ + ref_biquad_cascade_##config_suffix##speed##_##suffix( \ + &biquad_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type)))); \ + \ + return JTEST_TEST_PASSED; \ + } + + +JTEST_DEFINE_TEST(arm_biquad_cas_df1_32x64_q31_test, + arm_biquad_cas_df1_32x64_q31) +{ + arm_biquad_cas_df1_32x64_ins_q31 biquad_inst_fut = { 0 }; + arm_biquad_cas_df1_32x64_ins_q31 biquad_inst_ref = { 0 }; + + TEMPLATE_DO_ARR_DESC( + blocksize_idx, uint32_t, blockSize, filtering_blocksizes + , + TEMPLATE_DO_ARR_DESC( + numstages_idx, uint16_t, numStages, filtering_numstages + , + TEMPLATE_DO_ARR_DESC( + postshifts_idx, uint8_t, postShift, filtering_postshifts + , + /* Initialize the BIQUAD Instances */ + arm_biquad_cas_df1_32x64_init_q31( + &biquad_inst_fut, numStages, + (q31_t*)filtering_coeffs_b_q31, + (void *) filtering_pState, postShift); + + /* Display test parameter values */ + JTEST_DUMP_STRF("Block Size: %d\n" + "Number of Stages: %d\n", + (int)blockSize, + (int)numStages); + + JTEST_COUNT_CYCLES( + arm_biquad_cas_df1_32x64_q31( + &biquad_inst_fut, + (void *) filtering_q31_inputs, + (void *) filtering_output_fut, + blockSize)); + + arm_biquad_cas_df1_32x64_init_q31( + &biquad_inst_ref, numStages, + (q31_t*)filtering_coeffs_b_q31, + (void *) filtering_pState, postShift); + + ref_biquad_cas_df1_32x64_q31( + &biquad_inst_ref, + (void *) filtering_q31_inputs, + (void *) filtering_output_ref, + blockSize); + + FILTERING_SNR_COMPARE_INTERFACE( + blockSize, + q31_t)))); + + return JTEST_TEST_PASSED; +} + +JTEST_DEFINE_TEST(arm_biquad_cascade_df2T_f64_test, + arm_biquad_cascade_df2T_f64) +{ + arm_biquad_cascade_df2T_instance_f64 biquad_inst_fut = { 0 }; + arm_biquad_cascade_df2T_instance_f64 biquad_inst_ref = { 0 }; + + TEMPLATE_DO_ARR_DESC( + blocksize_idx, uint32_t, blockSize, filtering_blocksizes + , + TEMPLATE_DO_ARR_DESC( + numstages_idx, uint16_t, numStages, filtering_numstages + , + /* Display test parameter values */ + JTEST_DUMP_STRF("Block Size: %d\n" + "Number of Stages: %d\n", + (int)blockSize, + (int)numStages); + + /* Initialize the BIQUAD Instances */ + arm_biquad_cascade_df2T_init_f64( + &biquad_inst_fut, numStages, + (float64_t*)filtering_coeffs_b_f64, + (void *) filtering_pState); + + JTEST_COUNT_CYCLES( + arm_biquad_cascade_df2T_f64( + &biquad_inst_fut, + (void *) filtering_f64_inputs, + (void *) filtering_output_fut, + blockSize)); + + arm_biquad_cascade_df2T_init_f64( + &biquad_inst_ref, numStages, + (float64_t*)filtering_coeffs_b_f64, + (void *) filtering_pState); + + ref_biquad_cascade_df2T_f64( + &biquad_inst_ref, + (void *) filtering_f64_inputs, + (void *) filtering_output_ref, + blockSize); + + FILTERING_DBL_SNR_COMPARE_INTERFACE( + blockSize, + float64_t))); + + return JTEST_TEST_PASSED; +} + + +BIQUAD_DEFINE_TEST(f32,arm_biquad_casd_df1_inst_f32, df1,float32_t); +BIQUAD_DEFINE_TEST(f32,arm_biquad_cascade_df2T_instance_f32,df2T,float32_t); +BIQUAD_DEFINE_TEST(f32,arm_biquad_cascade_stereo_df2T_instance_f32,stereo_df2T,float32_t); +BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q31,df1,,q31_t); +BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q15,df1,,q15_t); +BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q31,df1,_fast,q31_t); +BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q15,df1,_fast,q15_t); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(biquad_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_biquad_cascade_df1_f32_test); + JTEST_TEST_CALL(arm_biquad_cascade_df2T_f32_test); + JTEST_TEST_CALL(arm_biquad_cascade_stereo_df2T_f32_test); + JTEST_TEST_CALL(arm_biquad_cascade_df2T_f64_test); + JTEST_TEST_CALL(arm_biquad_cascade_df1_q31_test); + JTEST_TEST_CALL(arm_biquad_cascade_df1_q15_test); + JTEST_TEST_CALL(arm_biquad_cascade_df1_fast_q31_test); + JTEST_TEST_CALL(arm_biquad_cascade_df1_fast_q15_test); + JTEST_TEST_CALL(arm_biquad_cas_df1_32x64_q31_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c new file mode 100644 index 0000000..981004b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c @@ -0,0 +1,473 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +/*--------------------------------------------------------------------------------*/ +/* Header Stuff */ +/*--------------------------------------------------------------------------------*/ + +#define CONV_MAX_INPUT_ELTS 32 +#define CONV_MAX_OUTPUT_ELTS (CONV_MAX_INPUT_ELTS * 2) + +#define CONV_TEST_VALID_PARTIAL_PARAMS(input_a_len, input_b_len, \ + first_index, num_points) \ + (((((input_a_len) + (input_b_len) - 1)) >= num_points + first_index ) \ + && (num_points > 0)) + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define CONV_arm_conv_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut) + +#define CONV_ref_conv_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref) + +#define CONV_arm_conv_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_fut, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_ref_conv_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_ref, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_arm_conv_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut) + +#define CONV_ref_conv_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref) + +#define CONV_arm_conv_fast_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_fut, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_ref_conv_fast_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_ref, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_arm_conv_partial_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_fut, first_index, num_points) + +#define CONV_ref_conv_partial_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_ref, first_index, num_points) + +#define CONV_arm_conv_partial_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_fut, first_index, num_points) + +#define CONV_ref_conv_partial_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_ref, first_index, num_points) + +#define CONV_arm_conv_partial_opt_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_fut, first_index, num_points, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_ref_conv_partial_opt_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_ref, first_index, num_points, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_arm_conv_partial_fast_opt_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_fut, first_index, num_points, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_ref_conv_partial_fast_opt_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_ref, first_index, num_points, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +/*--------------------------------------------------------------------------------*/ +/* Convolution Inputs */ +/*--------------------------------------------------------------------------------*/ + +/* The following symbols alias the filtering_q31_inputs array: + * + * - filtering_q15_inputs + * - filtering_q7_inputs + * + * The aliasing conflicts with the instantiation of #ARR_DESC_t structs. + * + * These macro-level aliases allow the #CONV_DEFINE_RAND_INPUT_ARR_DESCS() macro + * to correctly select the filtering_q31_input or filtering_f32_input array, + * within a template, by type_suffix. + * + */ +#define CONV_f32_INPUTS filtering_f32_inputs +#define CONV_q31_INPUTS filtering_q31_inputs +#define CONV_q15_INPUTS filtering_q31_inputs +#define CONV_q7_INPUTS filtering_q31_inputs + +/** + * Defines #ARR_DESC_t objects that wrap existing, type-specific, common + * inputs. + */ +#define CONV_DEFINE_RAND_INPUT_ARR_DESCS(type_suffix) \ + ARR_DESC_DEFINE_USING_ARR( \ + TYPE_FROM_ABBREV(type_suffix), \ + conv_input_rand1_##type_suffix, \ + CONV_##type_suffix##_INPUTS, \ + 0, \ + CONV_MAX_INPUT_ELTS); \ + \ + ARR_DESC_DEFINE_USING_ARR( \ + TYPE_FROM_ABBREV(type_suffix), \ + conv_input_rand2_##type_suffix, \ + CONV_##type_suffix##_INPUTS, \ + 1, \ + CONV_MAX_INPUT_ELTS) /* Note the lacking semicolon */ + +CONV_DEFINE_RAND_INPUT_ARR_DESCS(f32); +CONV_DEFINE_RAND_INPUT_ARR_DESCS(q31); +CONV_DEFINE_RAND_INPUT_ARR_DESCS(q15); +CONV_DEFINE_RAND_INPUT_ARR_DESCS(q7); +ARR_DESC_DEFINE(float32_t, conv_input_zeros, CONV_MAX_INPUT_ELTS, CURLY(0)); + +/** + * Define Input #ARR_DESC_t arrays by type suffix. + * + * Taking inputs in parallel from the 'a' and 'b' arrays yields the following + * test cases (star is convolution): + * + * - zero_array * zero_array + * - zero_array * random_array + * - random_array * zero_array + * - random_array * different_random_arary + */ +#define CONV_DEFINE_ALL_INPUTS(type_suffix) \ + ARR_DESC_DEFINE(ARR_DESC_t *, \ + conv_##type_suffix##_a_inputs, \ + 4, \ + CURLY( \ + &conv_input_zeros, \ + &conv_input_zeros, \ + &conv_input_rand1_##type_suffix, \ + &conv_input_rand1_##type_suffix \ + )); \ + ARR_DESC_DEFINE(ARR_DESC_t *, \ + conv_##type_suffix##_b_inputs, \ + 4, \ + CURLY( \ + &conv_input_zeros, \ + &conv_input_rand1_##type_suffix, \ + &conv_input_zeros, \ + &conv_input_rand2_##type_suffix \ + )) /* Note the lacking semicolon */ + +CONV_DEFINE_ALL_INPUTS(f32); +CONV_DEFINE_ALL_INPUTS(q31); +CONV_DEFINE_ALL_INPUTS(q15); +CONV_DEFINE_ALL_INPUTS(q7); + +/*--------------------------------------------------------------------------------*/ +/* Convolution Lengths */ +/*--------------------------------------------------------------------------------*/ + +/* + * The conv_lens_a and conv_lens_b #ARR_DESC_t objects are accessed in parallel + * to provide convolution-length pairs. Taken in parallel they provide the + * following cases: + * + * - 1 * 1 : Shortest convolution possible. + * - 1 * 2 : Short convolution , one side is degenerate . + * - 17 * 1 : Medium convolution , one side is degenerate . + * - 15 * MAX : Longest convolution , one side is degenerate . + * MAX * MAX : Longest convolution. + */ +ARR_DESC_DEFINE(uint32_t, + conv_lens_a, + 5, + CURLY( + 1, + 1, + 17, + 15, + CONV_MAX_INPUT_ELTS + )); + +ARR_DESC_DEFINE(uint32_t, + conv_lens_b, + 5, + CURLY( + 1, + 2, + 1, + CONV_MAX_INPUT_ELTS, + CONV_MAX_INPUT_ELTS + )); + +/*--------------------------------------------------------------------------------*/ +/* Partial Indexing */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(uint32_t, + first_index_arr_desc, + 4, + CURLY( + 0, + 1, + CONV_MAX_INPUT_ELTS / 2, + CONV_MAX_INPUT_ELTS + )); + +ARR_DESC_DEFINE(uint32_t, + num_points_arr_desc, + 3, + CURLY( + 1, + CONV_MAX_OUTPUT_ELTS / 2, + CONV_MAX_OUTPUT_ELTS + )); + +/*--------------------------------------------------------------------------------*/ +/* Convolution Tests */ +/*--------------------------------------------------------------------------------*/ + +#define CONV_TEST_TEMPLATE(fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + suffix, output_type) \ + JTEST_DEFINE_TEST(fut##_tests, fut) \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, conv_##suffix##_a_inputs \ + , \ + void * input_a_ptr = input_ptr->data_ptr; \ + void * input_b_ptr = ARR_DESC_ELT( \ + ARR_DESC_t *, input_idx, \ + &(conv_##suffix##_b_inputs))->data_ptr; \ + \ + TEMPLATE_DO_ARR_DESC( \ + conv_len_idx, uint32_t, conv_len_a, conv_lens_a \ + , \ + uint32_t conv_len_b = ARR_DESC_ELT( \ + uint32_t, conv_len_idx, &(conv_lens_b)); \ + \ + JTEST_DUMP_STRF("Input A Length: %d\n" \ + "Input B Length: %d\n", \ + (int)conv_len_a, \ + (int)conv_len_b); \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_a_ptr, conv_len_a, input_b_ptr, conv_len_b), \ + ref, ref_arg_interface( \ + input_a_ptr, conv_len_a, input_b_ptr, conv_len_b)); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + conv_len_a + conv_len_b - 1, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } \ + \ + +#define CONV_PARTIAL_TEST_TEMPLATE(fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + suffix, output_type) \ + JTEST_DEFINE_TEST(fut##_tests, fut) \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, conv_##suffix##_a_inputs \ + , \ + void * input_a_ptr = input_ptr->data_ptr; \ + void * input_b_ptr = ARR_DESC_ELT( \ + ARR_DESC_t *, input_idx, \ + &(conv_##suffix##_b_inputs))->data_ptr; \ + TEMPLATE_DO_ARR_DESC( \ + conv_len_idx, uint32_t, conv_len_a, conv_lens_a \ + , \ + uint32_t conv_len_b = ARR_DESC_ELT( \ + uint32_t, conv_len_idx, &(conv_lens_b)); \ + \ + TEMPLATE_DO_ARR_DESC( \ + first_index_idx, uint32_t, first_index, \ + first_index_arr_desc \ + , \ + TEMPLATE_DO_ARR_DESC( \ + num_points_idx, uint32_t, num_points, \ + num_points_arr_desc \ + , \ + if (CONV_TEST_VALID_PARTIAL_PARAMS( \ + conv_len_a, conv_len_b, \ + first_index, num_points)) \ + { \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Input A Length: %d\n" \ + "Input B Length: %d\n" \ + "First Sample Index: %d\n" \ + "Number of Output Points: %d\n", \ + (int)conv_len_a, \ + (int)conv_len_b, \ + (int)first_index, \ + (int)num_points); \ + \ + memset(filtering_output_ref,0, \ + (2*CONV_MAX_INPUT_ELTS)*sizeof(output_type)); \ + memset(filtering_output_fut,0, \ + (2*CONV_MAX_INPUT_ELTS)*sizeof(output_type)); \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_a_ptr, conv_len_a, \ + input_b_ptr, conv_len_b, \ + first_index, num_points), \ + ref, ref_arg_interface( \ + input_a_ptr, conv_len_a, \ + input_b_ptr, conv_len_b, \ + first_index, num_points)); \ + \ + FILTERING_SNR_COMPARE_INTERFACE_OFFSET( \ + first_index, \ + num_points, \ + output_type); \ + } else { \ + /* FUT should return ARM_MATH_ARGUMENT_ERROR*/ \ + /* if first_index and num_points don't make */ \ + /* sense*/ \ + \ + arm_status conv_test_retval; \ + TEST_CALL_FUT( \ + conv_test_retval = fut, \ + fut_arg_interface( \ + input_a_ptr, conv_len_a, \ + input_b_ptr, conv_len_b, \ + first_index, num_points)); \ + \ + if (conv_test_retval != ARM_MATH_ARGUMENT_ERROR) { \ + JTEST_DUMP_STR("FUT failed to raise error."); \ + /* return JTEST_TEST_FAILED; */ \ + } \ + })))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define CONV_DEFINE_TEST(fn_name, suffix, output_type, test_template) \ + test_template( \ + arm_##fn_name##_##suffix, \ + CONV_arm_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + CONV_ref_##fn_name##_INPUT_INTERFACE, \ + suffix, \ + output_type \ + ) /* Note the lacking semicolon*/ + +/* Tests on functions without partial outputs */ +CONV_DEFINE_TEST(conv , f32, float32_t, CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv , q31, q31_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv , q15, q15_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv , q7 , q7_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_opt , q15, q15_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_opt , q7 , q7_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_fast , q31, q31_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_fast , q15, q15_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_fast_opt , q15, q15_t , CONV_TEST_TEMPLATE); + +/* Tests on functions with partial outputs */ +CONV_DEFINE_TEST(conv_partial , f32, float32_t, CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial , q31, q31_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial , q7 , q7_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial_fast , q31, q31_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial_fast , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial_fast_opt , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial_opt , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial_opt , q7 , q7_t , CONV_PARTIAL_TEST_TEMPLATE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(conv_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_conv_f32_tests); + JTEST_TEST_CALL(arm_conv_q31_tests); + JTEST_TEST_CALL(arm_conv_q15_tests); + JTEST_TEST_CALL(arm_conv_q7_tests); + + JTEST_TEST_CALL(arm_conv_opt_q15_tests); + JTEST_TEST_CALL(arm_conv_opt_q7_tests); + + JTEST_TEST_CALL(arm_conv_fast_q31_tests); + JTEST_TEST_CALL(arm_conv_fast_q15_tests); + + JTEST_TEST_CALL(arm_conv_fast_opt_q15_tests); + + JTEST_TEST_CALL(arm_conv_partial_f32_tests); + JTEST_TEST_CALL(arm_conv_partial_q31_tests); + JTEST_TEST_CALL(arm_conv_partial_q15_tests); + JTEST_TEST_CALL(arm_conv_partial_q7_tests); + + JTEST_TEST_CALL(arm_conv_partial_fast_q31_tests); + JTEST_TEST_CALL(arm_conv_partial_fast_q15_tests); + + JTEST_TEST_CALL(arm_conv_partial_fast_opt_q15_tests); + + JTEST_TEST_CALL(arm_conv_partial_opt_q15_tests); + JTEST_TEST_CALL(arm_conv_partial_opt_q7_tests); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c new file mode 100644 index 0000000..b00c7cc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c @@ -0,0 +1,310 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +/*--------------------------------------------------------------------------------*/ +/* Header Stuff */ +/*--------------------------------------------------------------------------------*/ + +#define CORRELATE_MAX_INPUT_ELTS 32 +#define CORRELATE_MAX_OUTPUT_ELTS (CORRELATE_MAX_INPUT_ELTS * 2) + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define CORRELATE_arm_correlate_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut) + +#define CORRELATE_ref_correlate_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref) + +#define CORRELATE_arm_correlate_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_fut, \ + (void*) filtering_scratch) + +#define CORRELATE_arm_correlate_opt_q7_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_fut, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CORRELATE_ref_correlate_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_ref, \ + (void*) filtering_scratch) + +#define CORRELATE_ref_correlate_opt_q7_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_ref, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CORRELATE_arm_correlate_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut) + +#define CORRELATE_ref_correlate_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref) + +#define CORRELATE_arm_correlate_fast_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_fut, \ + (void*) filtering_scratch) + +#define CORRELATE_ref_correlate_fast_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_ref, \ + (void*) filtering_scratch) + +/*--------------------------------------------------------------------------------*/ +/* Convolution Inputs */ +/*--------------------------------------------------------------------------------*/ + +/* The following symbols alias the filtering_q31_inputs array: + * + * - filtering_q15_inputs + * - filtering_q7_inputs + * + * The aliasing conflicts with the instantiation of #ARR_DESC_t structs. + * + * These macro-level aliases allow the #CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS() macro + * to correctly select the filtering_q31_input or filtering_f32_input array, + * within a template, by type_suffix. + * + */ +#define CORRELATE_f32_INPUTS filtering_f32_inputs +#define CORRELATE_q31_INPUTS filtering_q31_inputs +#define CORRELATE_q15_INPUTS filtering_q31_inputs +#define CORRELATE_q7_INPUTS filtering_q31_inputs + +/** + * Defines #ARR_DESC_t objects that wrap existing, type-specific, common + * inputs. + */ +#define CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(type_suffix) \ + ARR_DESC_DEFINE_USING_ARR( \ + TYPE_FROM_ABBREV(type_suffix), \ + correlate_input_rand1_##type_suffix, \ + CORRELATE_##type_suffix##_INPUTS, \ + 0, \ + CORRELATE_MAX_INPUT_ELTS); \ + \ + ARR_DESC_DEFINE_USING_ARR( \ + TYPE_FROM_ABBREV(type_suffix), \ + correlate_input_rand2_##type_suffix, \ + CORRELATE_##type_suffix##_INPUTS, \ + 1, \ + CORRELATE_MAX_INPUT_ELTS) /* Note the lacking semicolon */ + +CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(f32); +CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q31); +CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q15); +CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q7); +ARR_DESC_DEFINE(float32_t, correlate_input_zeros, CORRELATE_MAX_INPUT_ELTS, CURLY(0)); + +/** + * Define Input #ARR_DESC_t arrays by type suffix. + * + * Taking inputs in parallel from the 'a' and 'b' arrays yields the following + * test cases (star is correlate): + * + * - zero_array * zero_array + * - zero_array * random_array + * - random_array * zero_array + * - random_array * different_random_arary + */ +#define CORRELATE_DEFINE_ALL_INPUTS(type_suffix) \ + ARR_DESC_DEFINE(ARR_DESC_t *, \ + correlate_##type_suffix##_a_inputs, \ + 4, \ + CURLY( \ + &correlate_input_zeros, \ + &correlate_input_zeros, \ + &correlate_input_rand1_##type_suffix, \ + &correlate_input_rand1_##type_suffix \ + )); \ + ARR_DESC_DEFINE(ARR_DESC_t *, \ + correlate_##type_suffix##_b_inputs, \ + 4, \ + CURLY( \ + &correlate_input_zeros, \ + &correlate_input_rand1_##type_suffix, \ + &correlate_input_zeros, \ + &correlate_input_rand2_##type_suffix \ + )) /* Note the lacking semicolon */ + +CORRELATE_DEFINE_ALL_INPUTS(f32); +CORRELATE_DEFINE_ALL_INPUTS(q31); +CORRELATE_DEFINE_ALL_INPUTS(q15); +CORRELATE_DEFINE_ALL_INPUTS(q7); + +/*--------------------------------------------------------------------------------*/ +/* Convolution Lengths */ +/*--------------------------------------------------------------------------------*/ + +/* + * The correlate_lens_a and correlate_lens_b #ARR_DESC_t objects are accessed in parallel + * to provide correlate-length pairs. Taken in parallel they provide the + * following cases: + * + * - 1 * 1 : Shortest correlate possible. + * - 1 * 2 : Short correlate , one side is degenerate. + * - 17 * 1 : Medium correlate, one side is degenerate. + * - 15 * MAX : Longest correlate. + * MAX * MAX : Longest correlate. + */ +ARR_DESC_DEFINE(uint32_t, + correlate_lens_a, + 5, + CURLY( + 1, + 1, + 17, + 15, + CORRELATE_MAX_INPUT_ELTS + )); + +ARR_DESC_DEFINE(uint32_t, + correlate_lens_b, + 5, + CURLY( + 1, + 2, + 1, + CORRELATE_MAX_INPUT_ELTS, + CORRELATE_MAX_INPUT_ELTS + )); + +/*--------------------------------------------------------------------------------*/ +/* Convolution Tests */ +/*--------------------------------------------------------------------------------*/ + +#define CORRELATE_TEST_TEMPLATE(fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + suffix, output_type) \ + JTEST_DEFINE_TEST(fut##_tests, fut) \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, correlate_##suffix##_a_inputs \ + , \ + void * input_a_ptr = input_ptr->data_ptr; \ + void * input_b_ptr = ARR_DESC_ELT( \ + ARR_DESC_t *, input_idx, \ + &(correlate_##suffix##_b_inputs))->data_ptr; \ + \ + TEMPLATE_DO_ARR_DESC( \ + correlate_len_idx, uint32_t, correlate_len_a, correlate_lens_a \ + , \ + uint32_t correlate_len_b = ARR_DESC_ELT( \ + uint32_t, correlate_len_idx, &(correlate_lens_b)); \ + \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Input A Length: %d\n" \ + "Input B Length: %d\n", \ + (int)correlate_len_a, \ + (int)correlate_len_b); \ + \ + memset(filtering_output_ref,0, \ + (2*CORRELATE_MAX_INPUT_ELTS)*sizeof(output_type)); \ + memset(filtering_output_fut,0, \ + (2*CORRELATE_MAX_INPUT_ELTS)*sizeof(output_type)); \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_a_ptr, correlate_len_a, input_b_ptr, correlate_len_b), \ + ref, ref_arg_interface( \ + input_a_ptr, correlate_len_a, input_b_ptr, correlate_len_b)); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + correlate_len_a + correlate_len_b - 2, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define CORRELATE_DEFINE_TEST(fn_name, suffix, output_type, test_template) \ + test_template( \ + arm_##fn_name##_##suffix, \ + CORRELATE_arm_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + CORRELATE_ref_##fn_name##_INPUT_INTERFACE, \ + suffix, \ + output_type \ + ) /* Note the lacking semicolon*/ + +/* Tests on functions without partial outputs */ +CORRELATE_DEFINE_TEST(correlate , f32, float32_t, CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate , q31, q31_t , CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate , q15, q15_t , CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate , q7 , q7_t , CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate_opt , q15, q15_t , CORRELATE_TEST_TEMPLATE); + +CORRELATE_TEST_TEMPLATE( + arm_correlate_opt_q7, + CORRELATE_arm_correlate_opt_q7_INPUT_INTERFACE, + ref_correlate_opt_q7, + CORRELATE_ref_correlate_opt_q7_INPUT_INTERFACE, + q7, + q7_t + ); + +CORRELATE_DEFINE_TEST(correlate_fast , q31, q31_t , CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate_fast , q15, q15_t , CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate_fast_opt , q15, q15_t , CORRELATE_TEST_TEMPLATE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(correlate_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_correlate_f32_tests); + JTEST_TEST_CALL(arm_correlate_q31_tests); + JTEST_TEST_CALL(arm_correlate_q15_tests); + JTEST_TEST_CALL(arm_correlate_q7_tests); + + JTEST_TEST_CALL(arm_correlate_opt_q15_tests); + JTEST_TEST_CALL(arm_correlate_opt_q7_tests); + + JTEST_TEST_CALL(arm_correlate_fast_q31_tests); + JTEST_TEST_CALL(arm_correlate_fast_q15_tests); + + JTEST_TEST_CALL(arm_correlate_fast_opt_q15_tests); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c new file mode 100644 index 0000000..0fc4178 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c @@ -0,0 +1,757 @@ +#include "filtering_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +//must be max(LMS_MAX_BLOCKSIZE*2, FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_L) +float32_t filtering_output_fut[LMS_MAX_BLOCKSIZE*2] = {0}; +float32_t filtering_output_ref[LMS_MAX_BLOCKSIZE*2] = {0}; +float32_t filtering_output_f32_fut[LMS_MAX_BLOCKSIZE*2] = {0}; +float32_t filtering_output_f32_ref[LMS_MAX_BLOCKSIZE*2] = {0}; +float32_t filtering_input_lms[LMS_MAX_BLOCKSIZE*2] = {0}; +__ALIGNED(8) float32_t filtering_pState[LMS_MAX_BLOCKSIZE + FILTERING_MAX_NUMTAPS] = {0}; +float32_t filtering_scratch[FILTERING_MAX_BLOCKSIZE * 3] = {0}; +float32_t filtering_scratch2[FILTERING_MAX_BLOCKSIZE * 3] = {0}; +float32_t filtering_coeffs_lms[FILTERING_MAX_NUMTAPS]; + +const q31_t filtering_q31_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS] = +{ + 0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB, + 0x41F6F6A, 0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8, + 0x3D060524, 0x93D5E570, 0x97D7791D, 0xFFE0C38C, 0x26749841, + 0xC0A6EE54, 0x218EC386, 0x39FF3726, 0x8DC1F7CA, 0x702F2CF5, + 0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49, 0x3805DE7E, + 0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF, + 0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24, + 0x6CE00F5C, 0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530, + 0x73394127, 0x773FA6F4, 0x9805A980, 0x838DE587, 0x9CF597F4, + 0xA2AD1691, 0xFA81A473, 0x7CDC7D7F, 0x4A5190D0, 0xED895BB9, + 0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516, 0x2501A3E1, + 0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E, + 0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4, + 0x24DB166C, 0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6, + 0x419E0C75, 0x46BE9F38, 0x2432B9B2, 0x758D83E0, 0xDCE12926, + 0x3F57CB74, 0x1F4458E2, 0xF1DD639, 0x83A1FB49, 0x173AFC76, + 0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549, 0x5C314C9, + 0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715, + 0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F, + 0x20BFDEB4, 0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE, + 0x9858E3E1, 0xA36A9C4E, 0x88BD21F9, 0xAACF7A68, 0x773665E5, + 0xCEDFDF66, 0x617A9610, 0x524FC968, 0xC2D086CD, 0x5F008079, + 0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608, 0xA33A2EE5, + 0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5, + 0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4, + 0xB358C0D8, 0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF, + 0x33035831, 0x13D93987, 0xFC542094, 0x845F317E, 0xDDC4BF8B, + 0x1379E50C, 0x5C20193F, 0xFDD58298, 0x9D482B82, 0x4A6BE062, + 0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882, 0xE6F8EA35, + 0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD, + 0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677, + 0xFB2E04F2, 0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8, + 0x1A8C7F28, 0x861E452E, 0x932D3F78, 0x7652D852, 0x73357BBA, + 0xEBBB0A58, 0x62536AFA, 0x3F6B65EF, 0x6DC57B58, 0x9EB798CE, + 0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302, 0xA9FD3E40, + 0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3, + 0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896, + 0x6443A0FE, 0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820, + 0xF18F0810, 0xE1548689, 0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B, + 0xEA0C1BE0, 0xA1B785DB, 0x7086465D, 0x1CC10929, 0x1E1D716E, + 0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4, 0x441F1E8B, + 0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137, + 0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615, + 0x92593380, 0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7, + 0x10E916B6, 0xE3BCFA68, 0x2ACB80BB, 0xE51C5590, 0x994714B5, + 0xF30984EE, 0x59BBE1B4, 0xB4867DBC, 0xB91C706C, 0xBC16C218, + 0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, 0x4B167FD4, + 0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55, + 0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A, + 0x9D2C662A, 0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C, + 0x20306EDB, 0xE381AAE7, 0xA55DA748, 0x9B8B617B, 0x3E036FAD, + 0x84E4C4A7, 0xD5A3F517, 0x669BA988, 0x98FDDE8C, 0x67BD85CE, + 0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF, 0x205DB5C, + 0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC, + 0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693, + 0xC42D12C0, 0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC, + 0x8D874532, 0x5F5C9DD0, 0x5D167858, 0x8559FEA2, 0x9D821476, + 0xD9654ED2, 0x594C0DC7, 0x1A87B506, 0x3F693200, 0x7A651AB5, + 0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0, 0xB088C72F, + 0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB, + 0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D, + 0x32581A06, 0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15, + 0xBC79A9BC, 0xB7175917, 0x354E381C, 0x762AADD7, 0xF643DAC1, + 0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4, 0xD7694875, 0x92D30822, + 0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7, 0x58CE268, + 0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1, + 0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB, + 0x8FF5534, 0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7, + 0x419545EB, 0x993F7880, 0xAB246B20, 0x408AABC4, 0xCBF6EA49, + 0xC0894C55, 0x4CAA6398, 0xA47856E9, 0xAF2AE47D, 0x22F55D33, + 0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8, 0x9A77D48, + 0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A, + 0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071, + 0x7F9930D4, 0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A, + 0x144B2C12, 0x98E425C7, 0xBAA4B373, 0x18F0D03C, 0x99462AC0, + 0xD8B4D2EF, 0x72473895, 0xA6BF5435, 0xEDAD53B, 0xE0912FA6, + 0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929, 0xB89962F9, + 0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0, + 0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841, + 0x73A60174, 0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095, + 0x2B370837, 0x83DF6CE3, 0xDD08EEFA, 0x3F52A7C2, 0x191B4785, + 0x60843D82, 0xB0DE11F1, 0x105EA26C, 0x6E1C7AA2, 0x47AADD14, + 0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC, 0x744206A, + 0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9, + 0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F, + 0x2E53E6C1, 0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5, + 0x119725CC, 0x5406D347, 0x1B6FFAF1, 0xECCF71F1, 0x981117F2, + 0x7167CA76, 0x74F4B880, 0x77A55F47, 0x59EADB62, 0x4A331D95, + 0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1, 0x60D47AD5, + 0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3, + 0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E, + 0x31109C58, 0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF, + 0xBAF8D31E, 0xA4B31611, 0xED37F331, 0x7A832A22, 0xA22591C7, + 0x722D1F89, 0x3B19CF18, 0x261B8A4D, 0xC3F6F6DB, 0xCF8CED61, + 0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4, 0x3674E663, + 0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD, + 0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91, + 0x4BF0C248, 0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26, + 0x6C3B7B71, 0xD744B3ED, 0xFA25D2F6, 0x4CDE642D, 0xD65B8142, + 0xA6F9207F, 0xE7A207BE, 0xDB506684, 0x44DA4780, 0x9175EA0C, + 0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2, 0x5423D9C8, + 0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1, + 0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5, + 0x1672BA91, 0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4, + 0x32AFD40C, 0x99A5FB3B, 0xDD1D73A3, 0xA342CB3E, 0xA78445F5, + 0x53979C3B, 0x427D7943, 0x5221B58C, 0xA6CE9A5E, 0xFB50ECA4, + 0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04, 0xFBB65E0C, + 0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920, + 0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641, + 0x4D6B1760, 0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF, + 0x4E5F9493, 0x4C215DA5, 0x33A052B, 0x1A4D80C2, 0x40AEEBCA, + 0x390D106B, 0xE9E8E018, 0x5AF3D6CF, 0xE35E1D4, 0xC4FB1C6, + 0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6, 0x2227567D, + 0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6, + 0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1, + 0xC9D06CBC, 0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47, + 0x9D4804EA, 0x57DD9E67, 0xF89C7895, 0xF5336111, 0x25C122C8, + 0x62742114, 0xCFBF6D26, 0xBF9F6482, 0xE6F02CD9, 0x11083202, + 0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1, 0x3BF4DC25, + 0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129, + 0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA, + 0x31C5A0AF, 0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98, + 0x82C34882, 0x5D041F11, 0x8C613C57, 0xD398CFD1, 0x426F38AD, + 0x5599AB1D, 0xFAFA078D, 0xAB25B413, 0xD94B32CF, 0xB288FE38, + 0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D, 0x2174EBBE, + 0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6, + 0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02, + 0xC20D47A4, 0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4, + 0xC58612F4, 0xA2827F6F, 0xC49DCDBA, 0x679B7362, 0x4E495845, + 0xCFD2F0D1, 0x395E76A0, 0x375A655E, 0x92E2058F, 0x73F9F0CA, + 0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B, 0xA219E2E8, + 0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF, + 0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40, + 0x157F6DDF, 0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58, + 0xB2945F75, 0x4FA23A0E, 0x836EB8C0, 0xB3B18FD, 0x86114337, + 0x24668ACB, 0x99BB82F0, 0x924C8A47, 0xBA959701, 0x81155ABF, + 0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7, 0x7FC2802D, + 0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719, + 0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD, + 0xEBA775AE, 0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D, + 0xBBD34AB7, 0x2F85B12A, 0x16C5C2AD, 0x3990985D, 0x88DF3351, + 0x82811AA5, 0x6D351F41, 0x4066A69D, 0x86B660BF, 0x6EDB4768, + 0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687, 0x947CC9C9, + 0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB, + 0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B, + 0xB7629C93, 0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66, + 0xEC71B78C, 0xEAF4BB3A, 0x7C16225E, 0x668F337, 0xCBEE1608, + 0x6D5B5552, 0x345DC590, 0x681209CC, 0x7B24A819, 0xD08A1416, + 0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678, 0x20EECA0, + 0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D, + 0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960, + 0x7CDF59F3, 0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110, + 0xB8FCF3E3, 0xDEA059B2, 0x8229B6EA, 0x316486F6, 0x43919185, + 0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9, 0x5CD41244, 0x2C9F0A7B, + 0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0, 0xF105C20D, + 0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763, + 0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53, + 0x2D2A85F6, 0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B, + 0x9FC5AC5F, 0x11AE5DD7, 0xA0B9A5A9, 0xFC648AF4, 0x740009AC, + 0xED0E0321, 0xB8E6A61, 0x8910C544, 0xC74F26C8, 0x9525CCF3, + 0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D, 0xE1976DD4, + 0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1, + 0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB, + 0xF5288568, 0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A, + 0x1BC03B9, 0xB6BC3061, 0xBF30596E, 0xBE2AD27B, 0x8AC04220, + 0x641979A3, 0x9ECCBB89, 0xA144FBC1, 0x4E8FAE26, 0x8C5A9D90, + 0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D, 0xCEE81CDF, + 0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA, + 0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38, + 0x2E77F2D, 0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017, + 0x2D6B69A7, 0xFEDB63F9, 0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8, + 0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6, 0xED193443, 0x7615EF1B, + 0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022, 0x556E825C, + 0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF, + 0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC, + 0x1E6A1101, 0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599, + 0x54EB4809, 0x7839BE6D, 0xD50017DD, 0x39B1A0E1, 0x288D52D3, + 0x2D52668C, 0x20D22A68, 0x4E1207D1, 0x3FCC0EFE, 0x47F3FE64, + 0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8, 0x6BEAA655, + 0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9, + 0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B, + 0x4DCD4EDB, 0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6, + 0x502F41B0, 0x3616D3F1, 0x2E5B8E31, 0x2026EB19, 0x57E783D7, + 0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48, + 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED, + 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F, + 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB, + 0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94, + 0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11, + 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x73D63FED, 0xE36E9F5E, + 0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1, 0xCD476E86, + 0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7, + 0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78, + 0xCC4BE4F6, 0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2, + 0x55A8F5EC, 0xE81A9A75, 0x30A67E1B, 0x4A4A7D0C, 0x20F7F993, + 0x1891805, 0x738976AD, 0xD426E7D6, 0x3C5CEEBF, 0x4499187F, + 0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, 0x421BCF29, + 0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE, + 0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46, + 0x5D146234, 0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA, + 0xB65530CC, 0x2DFAC48C, 0x1663D16F, 0x59B80AA, 0x950274EA, + 0x92532D4A, 0x3CEF802D, 0x492FBDA5, 0xA63A2574, 0xEF8005C2, + 0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646, 0xD2598516, + 0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75, + 0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F, 0xECDD35CC, + 0xDDC1EE0E, 0xC4848865, 0x925826BD, 0x4078BE39, 0x68A8561A, + 0x323045DC, 0xA933B37F, 0xBA2AEE2E, 0x4F24F65D, 0x349EE246, + 0xF97B9D0E, 0x46DC5759, 0x4529F425, 0x80D17B42, 0x8E16F709, + 0x1B42206A, 0x4934A526, 0x391BB6DE, 0xB52EF45C, 0x26C30290, + 0xCBA23CAA, 0xA501A8C3, 0xD922C4F8, 0xE8824E53, 0x6F4255DC, + 0x5960B544, 0x58BC69D6, 0xCA936323, 0xFDDF053C, 0xC2E002D6, + 0x7D750755, 0x8A3F9CD1, 0x35F8F6F8, 0xFB7BD154, 0x65CFF94F, + 0x390A58DD, 0xD97C4093, 0x501CA2A3, 0x8EA5DEBC, 0xCA93461F, + 0xE02D984C, 0x126F8517, 0x39FDD887, 0x46241AE9, 0x777E854D, + 0xE2B36349, 0x58E3FA9F, 0x971DEF1E, 0x8E156228, 0xC0E14E9, + 0xA9A01BE6, 0xB318C990, 0x971680D6, 0xA1F359CE, 0x487E23F4, + 0x7DE465B0, 0x4E4C905E, 0x2A652959, 0x116FF167, 0x5C74AAB9, + 0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48, + 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED, + 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F, + 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB, + 0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94, + 0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11, + 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x4FEFC920, 0x28DF4EB8, + 0x29EBF45A, 0x1E350CF6 + }; + +/* The source data is random across the q31_t range. Accessing it by word should + remain random. */ +const q15_t * filtering_q15_inputs = (q15_t *) filtering_q31_inputs; +const q7_t * filtering_q7_inputs = (q7_t *) filtering_q31_inputs; + +const float32_t filtering_f32_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS] = +{ + 43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580 , 7.2830326091 , 66.8368719314 , 33.9778190671 , 117.8652289772 , + -129.6077797465, -14.6420815368 , 18.0239223278 , 20.6760530292 , 55.0375037651 , 1.8674609862 , -85.6534302408 , -33.5750364909 , + 29.2110949614 , 110.4727049460 , -94.1914619387 , -1.4084169343 , 83.5181653041 , 47.3073514127 , -13.3420621181 , 30.3389699104 , + 12.1188124277 , 100.9730921941 , -114.0146362390, -77.5823200409 , 37.2019034618 , 40.0026301128 , -58.3387276630 , -34.9472398600 , + -5.1169678311 , -87.7660091118 , -150.5888601131, 56.0349370503 , 50.2168884079 , -74.2313236767 , 22.3648603560 , -6.8676387051 , + 74.8957303680 , -90.1292012823 , -55.1436241586 , -66.6732976100 , -6.7918147615 , 7.7612697081 , 35.7892605979 , -20.0470508830 , + 41.8369017546 , -143.7378056984, -41.9127158600 , -108.3531841158, -57.1917422289 , -124.2808828105, 38.9316388820 , -77.9212517405 , + 37.1990818377 , -28.9545952748 , -155.6371057564, 45.8088886393 , 36.2537018275 , -6.5727656016 , -104.2070491921, 45.5583813729 , + -19.7674717059 , -80.4802190947 , -1.4444563441 , -42.2142256438 , 36.6546339194 , -57.0866498590 , 44.4677067511 , 65.7285753407 , + -103.8158864647, 25.4348723711 , -153.5419639389, 39.3608409474 , 49.1658103436 , 79.5570602275 , 75.2944095996 , 58.9394700746 , + -53.1018534392 , 33.4172444014 , 35.6224682287 , -64.4353396418 , -125.8464291251, -47.6072111617 , -26.2177687594 , -12.0061322096 , + -17.7887967585 , -28.2926175090 , -62.0691715749 , 40.5098573604 , -191.1123732593, 119.6750713043 , 19.6182375803 , -26.7615252921 , + 2.2957847015 , -108.3436451287, -50.5906164995 , -5.6360985100 , -11.6772204201 , -84.2765293757 , -60.9317810068 , 82.0446350218 , + -70.2048296348 , 72.8738253222 , 60.2450218115 , 114.2741231228 , 46.8180775285 , 6.9915412654 , -8.9909197429 , -78.9165936808 , + 66.4731535459 , -68.4235455651 , -79.8254597080 , -10.6308477115 , -62.6161569330 , -55.7744410292 , -11.8408366528 , 98.1034940997 , + 35.8213741877 , -54.4694482732 , 86.9631830044 , -53.0343838122 , -47.4898642865 , -47.2010929590 , -31.3312639685 , -23.0908245172 , + 12.0258009869 , -5.1098204703 , -9.8420230737 , -107.3328761158, 44.6810431959 , -17.9083820345 , -60.9753512872 , -7.5915088994 , + 17.2250813329 , 57.9176125648 , 124.3004161362 , -63.1950908493 , 120.5788885640 , -44.1734238117 , -91.7408095116 , -43.5696066595 , + -49.9560710099 , -167.8513443296, -70.9437505499 , -46.4109705355 , -64.2264526456 , -13.9995803916 , -100.9548186356, 9.9101010575 , + -50.0615130815 , -55.7590145012 , -60.3195153388 , 61.7913378549 , -102.0850899209, 53.2360193126 , -25.8997883369 , 75.1445512333 , + -113.8148602310, 17.8027281119 , -19.5006822722 , -44.2169628471 , 107.5017084384 , -113.7909124666, -43.9735396033 , 7.6880981388 , + 46.7384653508 , 9.9047443751 , 81.8646964362 , 132.3812863877 , -95.6959050236 , -68.5015813484 , 65.8586404494 , 18.5039353889 , + -30.1786166621 , -90.3098515667 , -22.9356228552 , -20.5778272423 , -2.2127786675 , -35.4418447703 , -51.8722915974 , -107.9024439078, + -51.5940748232 , -51.7463262677 , 74.2795485984 , 94.2205022462 , 9.7016384049 , -47.3556083155 , -36.7822314478 , -151.6455525363, + -15.7183814485 , 78.2063383182 , 0.1516414969 , 37.9304181609 , 20.6185902740 , -22.2164106778 , 6.1160554677 , 2.4061326953 , + -111.6681824598, -60.0858917090 , 75.1698614693 , -76.5787410444 , 28.3391655715 , -2.4946186443 , -68.0378899682 , 104.0893199171 , + -51.8319647254 , 38.8521710524 , 75.9114239564 , 73.9206172905 , -103.2533029987, 6.9002718274 , -36.6346436319 , -25.1990926265 , + 1.5852145953 , -50.6438436795 , 21.5018844428 , -151.9305562846, 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-22.5356086770 , -97.1978653617 , 86.5565049535 , 70.6118545777 , -30.6978082909 , 118.7238621666 , 14.5922386932 , 11.3449652072 , + 65.6007783405 , 82.6369678204 , -52.0390492248 , -47.0160551227 , -95.5142448634 , 99.7162626888 , -36.5523815090 , -42.8042935534 , + 68.3566199798 , -13.8451547552 , -71.1629911780 , 36.2989433752 , -32.4867163365 , 112.4079947071 , -75.6295117422 , 47.5276421639 , + 51.8078250755 , -26.8715188457 , -9.6291144797 , 40.1999849640 , -38.4634033246 , 40.9764960915 , -26.1715730268 , 36.5996396515 , + -26.9924731886 , 53.7879986570 , -83.1658398348 , 23.6381378489 , 43.8794937753 , -55.4133836419 , 90.0266130838 , 14.1036181982 , + -18.1225736715 , 85.1363181151 , -62.5970846379 , -18.5291947838 , -25.7341986703 , -49.7061342931 , -59.0442763971 , 50.8960636803 , + -87.6471123430 , -36.7217762531 , 22.5952364054 , 11.1107885650 , -0.5377327229 , 160.8145792630 , 73.3103441505 , 10.1656872354 , + -50.4554350397 , -57.3478171016 , -15.4201715357 , -26.9135446491 , -4.9891264771 , -37.0226770057 , -80.9919535641 , 50.4418660876 , + -25.8517575250 , -69.9538258421 , -17.5730160671 , 15.9405836751 , 113.9545230349 , -46.1040379057 , -94.2458635014 , -69.0338522452 , + 43.5813790265 , 107.1836101171 , -55.1012654323 , -77.1529555887 , -33.1530320656 , -94.5582659641 , -53.6837586872 , 27.0680381378 , + 93.9385415207 , -61.0955216188 , 18.0530957225 , 7.9150142320 , -12.1218191587 , 34.0173961457 , 40.0084937565 , 9.8119275580 , + 44.2065861274 , -1.8718514394 , 67.4740024215 , 46.7391150131 , 207.2404815875 , 45.1635364462 , 43.3580102761 , -44.0244218674 , + 83.2387206007 , -8.6441851856 , 12.3993902588 , -22.5091685270 , -19.8332981376 , 97.9196509289 , -76.6720306234 , 28.9740705859 , + 121.9415248016 , 9.6656982611 , -51.0996453694 , 37.3704374740 , 74.7589840907 , -113.4066752631, 120.0029566342 , -105.3786221360, + 81.8152755619 , -13.4979932982 , -21.4680758393 , -85.1088235539 , -65.3610798409 , -35.0444139470 , -48.0220794487 , -41.6210317362 , + 33.1212995259 , -82.1480936443 , -10.5479715135 , 76.4601917004 , 42.1983651157 , 92.6104239912 , -42.3536237955 , -24.5644182272 , + 30.4446637772 , -90.2899420489 , 63.6723540422 , 103.0895811428 , 64.1706769263 , -10.7069812309 , 21.8927240409 , 6.3571071738 , + 57.1457649358 , -52.9866276448 , 66.0981829072 , -29.5372056881 , -79.2252039810 , -136.2440652798, -57.0106422562 , 86.8203548141 , + 66.4244149837 , 53.3230426111 , -66.1283059222 , -131.0402660353, 8.0548411081 , 122.9088988100 , 1.2626894208 , -60.5059112373 , + -68.8707203082 , -6.4747987200 , 85.8411327244 , 99.9624156733 , 90.4197864338 , -35.9630441182 , -22.9158275507 , -17.3660128776 , + 16.7845345761 , 34.7219749782 , -39.3513765878 , 1.0460702756 , -60.9494500182 , 20.0900333387 , -85.9636743832 , 88.4400782168 , + 15.0729628728 , 61.5499846243 , 11.8579871757 , 107.8617581581 , -42.9393027864 , -62.8422307621 , -19.0589600542 , 4.0750325807 , + -36.0651825425 , 55.7638724501 , -10.4691736080 , -55.5672537178 , -61.2061519915 , -21.1885348576 , -131.2535612498, 24.7463552676 , + 22.9426321237 , 14.3038202264 , -138.0926317438, -59.0892900856 , -162.5416439986, 7.1307658250 , -141.1236672256, -4.7173618068 , + -16.7741532807 , -68.2615451173 , -2.6608701102 , 84.1978109826 , -11.3446202072 , 59.9630033088 , -1.8994925010 , -37.9301641959 , + -119.4435600954, -11.4587491646 , 12.2423215240 , -7.3169898616 , -67.0373621128 , 36.0198843055 , 53.9791315249 , -134.5885680695, + -83.8330811965 , -16.6714816463 , -8.8498552035 , -24.0513088196 , -22.9444328877 , -37.7961441531 , 25.1975736186 , -136.1611637464, + -5.0843464033 , -10.3939554694 , 20.7422826935 , 75.6854136623 , 46.4179626736 , -57.0052830175 , 7.3457235521 , -51.5504447254 , + -158.4375751701, -200.2426967181, -48.1234996261 , 1.6623945527 , 21.1746524375 , 99.4092980367 , -2.3206772903 , 45.7989166757 , + 2.0181548348 , -88.0556010969 , -59.1527212096 , 47.3607925077 , -10.4181140309 , 56.3558125650 , -8.9799125560 , -30.0376711812 , + -36.7132904688 , 35.7785050392 , -13.0763909369 , -2.1855594714 , 18.1550954005 , -28.6711803575 , -55.4495172398 , -2.8812973198 , + -59.9575059158 , 40.0588875786 , 57.4713686602 , -3.2835144853 , -36.7193552111 , -64.9415131516 , -166.9555466445, -23.5556853844 , + -54.9408569587 , -35.2310451959 , 21.3345143458 , 65.7590671151 , 51.2214538168 , 46.1271939944 , -42.2235267919 , 127.2329928299 , + 105.2391778600 , 17.6726845966 , -129.9021148044, 8.7065613044 , -94.0987112511 , -3.5375742950 , -23.1385452379 , 60.6219530633 , + 92.5445564235 , 48.5111974469 , -52.5699309159 , -60.0634811685 , 25.9034368684 , 140.0249495491 , 1.5918852392 , 38.0266038291 , + 17.5588710703 , 3.4294066089 , -27.6748782173 , 59.6182974489 , -35.2924781853 , -38.6198576115 , -13.6119803198 , 7.8375587489 , + 22.7250686519 , -28.3524510951 , -34.4269062817 , 22.6464817325 , -61.6528147860 , -5.9782002429 , 61.4730771294 , 43.5582379527 , + 55.6862408270 , 87.8745651631 , 46.3401042715 , -19.8780979663 , 74.1272633369 , 29.8590452377 , -12.8665765140 , 34.2931401219 , + 53.9279617551 , -16.9017895140 , -70.1527553166 , -79.6367897992 , 109.3728271017 , -129.2214826835, -53.4644539730 , -51.5654458993 , + 17.6062148433 , 3.5090251835 , 74.2615941204 , -109.3431097845, 40.1403465151 , 28.8714561280 , 94.0868659302 , -19.0047033845 , + -60.0967410050 , -19.0998457619 , -67.2027075128 , 72.0711434846 , -17.8737851232 , 123.7050551274 , 132.6331504104 , 25.5018761009 , + -36.7817189239 , -29.1580893235 , -6.5848563828 , 90.2868948516 , -35.7017258498 , -68.5675432955 , -52.4888589786 , 47.1377730021 , + -7.4546621940 , -52.0657517138 , -49.0404829633 , -114.6910280126, -117.6819819437, -32.7856729408 , 31.8232065591 , 12.1192973039 , + 35.2678513420 , -1.0336778293 , 30.7021249679 , 127.0442906046 , -84.8457819393 , 28.9862843096 , -47.3524701726 , -126.1094998460, + -2.9700276582 , -2.4956545870 , -53.8624121141 , -85.2114117637 , 76.9057985618 , 137.1205201755 , -19.0830817212 , 14.3407526579 , + -56.5921994449 , -25.6084873186 , -44.9470801106 , -133.3139496090, 0.3487447576 , 33.4499716730 , 34.7126257844 , -9.3307383323 , + 27.2996276947 , 10.8765676134 , -91.1032360444 , -90.9584216222 , 1.6981490570 , 96.8557438791 , 56.7726390913 , -44.3246449237 , + 52.3260643361 , 21.5551140465 , 27.4535327381 , 2.0072717479 , 7.4823125629 , 77.1185863870 , 16.1372262663 , -10.7206012957 , + 66.8830091413 , 49.3523828287 , 54.0855375598 , 30.8570349345 , -10.9255375390 , 62.3910624674 , 30.9238561381 , 0.3352881853 , + 72.1022806197 , -28.8319885008 , 23.3335288806 , 46.8999035980 , -67.0984424822 , -164.7917209112, 42.5767681360 , -92.4668227688 , + 43.8491734282 , -17.1126540408 , 37.4819594334 , 69.0774409673 , -39.3530526854 , -14.0693747124 , -60.2520781215 , -80.3860105519 , + 32.6689956840 , 15.3393042576 , -18.5529761307 , 97.3942151573 , -4.4462855745 , 13.7614349817 , 158.3358780719 , -44.7258299667 , + -17.7741912819 , 116.5136962268 , -33.6261057820 , 22.8344441288 , -155.1423976144, 5.7070117893 , -22.7906543902 , -45.0633909283 , + -13.9329987929 , -66.0848932507 , 1.1383038109 , 123.8386958483 , 67.6662401589 , 45.9152963554 , -27.4397697462 , 97.9596747354 , + -6.3544655181 , 29.0832146722 , 96.3468162499 , 32.4535976137 , -91.0650399301 , 2.7293262791 , 70.7853483111 , -92.3655274571 , + 69.0359217256 , 83.1530567979 , 35.8375091111 , 7.3393552348 , -95.1770165365 , 76.4905790891 , 55.6253140577 , -29.5315327050 , + -16.5935468750 , 20.4574192236 , -88.7897972666 , -38.6285080386 , 53.3203422726 , 98.5991486746 , 122.7305462474 , 67.7902817187 , + 5.1764117389 , 5.0632821624 , 21.9288789574 , -78.3140512638 , -21.2069682335 , 23.6342010925 , 34.4445769455 , 59.1346766615 , + 28.9978778000 , 39.8121180845 , -17.1650033520 , -56.9174900874 , 17.8157086148 , -112.8801457350, -122.4019040408, 140.8669393157 , + -65.4664329639 , 40.6952775518 , 32.7260891658 , -43.2565155866 , 19.3945751928 , -20.1815002000 , -67.6601711640 , -18.1921178207 , + -35.6802153684 , -19.6571455162 +}; + +/*--------------------------------------------------------------------------------*/ +/* Blocksizes */ +/*--------------------------------------------------------------------------------*/ +ARR_DESC_DEFINE(uint32_t, + filtering_blocksizes, + 5, + CURLY( + 1, 7, 14, 32, FILTERING_MAX_BLOCKSIZE)); + +ARR_DESC_DEFINE(uint32_t, + lms_blocksizes, + 3, + CURLY( + 128, 256, LMS_MAX_BLOCKSIZE)); + +ARR_DESC_DEFINE(uint16_t, + filtering_numtaps, + 5, + CURLY( + 4, 6, 14, 32, FILTERING_MAX_NUMTAPS)); + +ARR_DESC_DEFINE(uint16_t, + filtering_numtaps2, + 5, + CURLY( + 6, 12, 18, 24, 30)); + +ARR_DESC_DEFINE(uint16_t, + filtering_numstages, + 3, + CURLY( + 1, 7, FILTERING_MAX_NUMSTAGES)); + +ARR_DESC_DEFINE(uint8_t, + filtering_postshifts, + 3, + CURLY( + 0, 1, FILTERING_MAX_POSTSHIFT)); + +ARR_DESC_DEFINE(uint8_t, + filtering_Ls, + 3, + CURLY( + 1, 2, FILTERING_MAX_L)); + +ARR_DESC_DEFINE(uint8_t, + filtering_Ms, + 6, + CURLY( + 1, 2, 4, 7, 11, FILTERING_MAX_M)); + + +/*--------------------------------------------------------------------------------*/ +/* Coefficient Lists */ +/*--------------------------------------------------------------------------------*/ + +// There must be at least max( FILTERING_MAX_NUMTAPS + 2 , FILTERING_MAX_NUMSTAGES * 6 + 2) coefficients +const float32_t filtering_coeffs_f32[FILTERING_MAX_NUMSTAGES * 6 + 2] = +{ + -13.0572f, 0.0f , -97.4724f, 8.4111f , -7.2193f , -53.7577f, 22.2630f , + -1.0509f , -25.9198f, 26.5207f , -12.6697f, -78.7453f, -0.6540f , 0.3119f , + 13.4595f , -6.7225f , -4.1313f , -38.5974f, 3.2700f , -51.6191f, -22.4314f, + 0.2481f , 32.9779f , -37.6421f, 5.4469f , -7.0023f , 24.3657f , 9.9140f , + 0.2870f , -13.0499f, 29.3333f , -53.1396f, -2.7555f , 0.5377f , 35.3491f , + -3.7134f , 0.8548f , 4.7469f , -10.5865f, -2.7285f , -1.5912f , -13.3502f, + 6.8532f , -8.2304f , -8.1193f , 3.8257f , -2.1703f , 13.5727f , 14.2736f , + -0.9855f , -8.9334f , -13.8883f, 11.8430f , -2.2024f , 0.9795f , 15.6191f , + 5.2121f , 10.8102f , -9.4171f , 6.0411f , -0.9131f , 10.6992f , -3.2634f , + 7.5849f , -4.9305f , -6.0549f , -7.9409f , 1.5827f , 13.3177f , 8.6727f , + -13.2268f , 11.1239f , 0.2481f , 32.9779f , -37.6421f, 5.4469f , -13.8883f, + 11.8430f , -2.2024f , 0.9795f , 15.6191f , 0.2481f , 32.9779f , -37.6421f, + 3.2700f , -51.6191f +}; +const float64_t filtering_coeffs_f64[FILTERING_MAX_NUMSTAGES * 6 + 2] = +{ + -13.0572f, 0.0f , -97.4724f, 8.4111f , -7.2193f , -53.7577f, 22.2630f , + -1.0509f , -25.9198f, 26.5207f , -12.6697f, -78.7453f, -0.6540f , 0.3119f , + 13.4595f , -6.7225f , -4.1313f , -38.5974f, 3.2700f , -51.6191f, -22.4314f, + 0.2481f , 32.9779f , -37.6421f, 5.4469f , -7.0023f , 24.3657f , 9.9140f , + 0.2870f , -13.0499f, 29.3333f , -53.1396f, -2.7555f , 0.5377f , 35.3491f , + -3.7134f , 0.8548f , 4.7469f , -10.5865f, -2.7285f , -1.5912f , -13.3502f, + 6.8532f , -8.2304f , -8.1193f , 3.8257f , -2.1703f , 13.5727f , 14.2736f , + -0.9855f , -8.9334f , -13.8883f, 11.8430f , -2.2024f , 0.9795f , 15.6191f , + 5.2121f , 10.8102f , -9.4171f , 6.0411f , -0.9131f , 10.6992f , -3.2634f , + 7.5849f , -4.9305f , -6.0549f , -7.9409f , 1.5827f , 13.3177f , 8.6727f , + -13.2268f , 11.1239f , 0.2481f , 32.9779f , -37.6421f, 5.4469f , -13.8883f, + 11.8430f , -2.2024f , 0.9795f , 15.6191f , 0.2481f , 32.9779f , -37.6421f, + 3.2700f , -51.6191f +}; + +const float32_t filtering_coeffs_b_f32[FILTERING_MAX_NUMSTAGES * 6 + 2] = +{ + -0.0572f, 0.0f , -0.4724f, 0.4111f , -0.9999f, -0.7577f, 0.2630f , + -0.0509f, -1.0000f, 0.5207f , -0.6697f, -0.7453f, -0.6540f, 0.3119f , + 0.4595f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, -0.4314f, + 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f , + 0.2870f , -0.0499f, 0.3333f , -0.1396f, -0.7555f, 0.5377f , 0.3491f , + 0.2369f , -0.5310f, -0.5904f, 0.6263f , 0.0205f , 0.1088f , -0.2926f, + -0.4187f, -0.5094f, 0.4479f , -0.3594f, -0.3102f, 0.6748f , 0.7620f , + 0.0033f , -0.9195f, 0.3192f , -0.1705f, 0.5524f , -0.5025f, 0.4898f , + -0.0119f, -0.3982f, -0.7818f, -0.9186f, -0.0944f, 0.7228f , 0.7014f , + 0.4850f , -0.6814f, 0.4914f , -0.6286f, 0.5130f , -0.8585f, 0.3000f , + 0.6068f , 0.4978f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, + 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f , + 0.2369f , -0.5310f +}; + +const float64_t filtering_coeffs_b_f64[FILTERING_MAX_NUMSTAGES * 6 + 2] = +{ + -0.0572f, 0.0f , -0.4724f, 0.4111f , -0.9999f, -0.7577f, 0.2630f , + -0.0509f, -1.0000f, 0.5207f , -0.6697f, -0.7453f, -0.6540f, 0.3119f , + 0.4595f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, -0.4314f, + 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f , + 0.2870f , -0.0499f, 0.3333f , -0.1396f, -0.7555f, 0.5377f , 0.3491f , + 0.2369f , -0.5310f, -0.5904f, 0.6263f , 0.0205f , 0.1088f , -0.2926f, + -0.4187f, -0.5094f, 0.4479f , -0.3594f, -0.3102f, 0.6748f , 0.7620f , + 0.0033f , -0.9195f, 0.3192f , -0.1705f, 0.5524f , -0.5025f, 0.4898f , + -0.0119f, -0.3982f, -0.7818f, -0.9186f, -0.0944f, 0.7228f , 0.7014f , + 0.4850f , -0.6814f, 0.4914f , -0.6286f, 0.5130f , -0.8585f, 0.3000f , + 0.6068f , 0.4978f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, + 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f , + 0.2369f , -0.5310f +}; + +const float32_t *filtering_coeffs_c_f32 = filtering_coeffs_b_f32 + 1; + +const q31_t filtering_coeffs_q31[FILTERING_MAX_NUMSTAGES * 6 + 2] = +{ + 0xEEDA759C, 0x00000000, 0x80000000, 0x0B0BA027, 0xF6850544, 0xB967E3EC, + 0x1D3C4F64, 0xFFFFFFFF, 0xDDF65B14, 0x22D3A62D, 0xEF5CBB89, 0x98979EE0, + 0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5, + 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690, + 0x0727234D, 0xF6CDFB14, 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A, + 0x268530EF, 0xBA37B050, 0x7FFFFFFF, 0xEF5CBB89, 0x00000000, 0x2B4E6639, + 0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5, + 0x1D3C4F64, 0xFFFFFFFF, 0xDDF65B14, 0x22D3A62D, 0xEF5CBB89, 0x98979EE0, + 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690, + 0x0727234D, 0xF6CDFB14, 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A, + 0xE28B1589, 0x0053690B, 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0xB967E3EC, + 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690, + 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A, 0xFFFFFFFF, 0xDDF65B14, + 0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5, + 0x2B4E6639, 0xCE919690 +}; + +const q31_t *filtering_coeffs_b_q31 = filtering_coeffs_q31 + 1; +const q31_t *filtering_coeffs_c_q31 = filtering_coeffs_q31 + 2; + +//fourth coefficient MUST be zero for arm_biquad_cascade_df1_fast_q15 to work +//every 6th coefficient after that must also be zero +const q15_t filtering_coeffs_q15[FILTERING_MAX_NUMSTAGES * 6 + 4] = +{ + 0xBA37, 0xEEDA, 0x8000, 0x0000, 0x0B0B, 0xF685, 0xB967, + 0x1D3C, 0xFFFF, 0x0000, 0x22D3, 0xEF5C, 0x9897, + 0xFF24, 0x0068, 0x0000, 0xF72C, 0xFA93, 0xCD50, + 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91, + 0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC, + 0x2685, 0xBA37, 0x0000, 0xDDF6, 0x0000, 0x2B4E, + 0xFF24, 0x0068, 0x0000, 0xF72C, 0xFA93, 0xCD50, + 0x1D3C, 0xFFFF, 0x0000, 0x22D3, 0xEF5C, 0x9897, + 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91, + 0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC, + 0xE28B, 0x0053, 0x0000, 0xBC36, 0xE28B, 0xB967, + 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91, + 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91, + 0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC, + 0xE28B, 0x11AC, 0x0000, +}; + +const q15_t *filtering_coeffs_b_q15 = filtering_coeffs_q15 + 2; +const q15_t *filtering_coeffs_c_q15 = filtering_coeffs_q15 + 4; + +const q7_t filtering_coeffs_q7[FILTERING_MAX_NUMSTAGES * 6 + 8] = +{ + 0xEE, 0x00, 0x80, 0x0B, 0xF6, 0xB9, + 0x1D, 0xFF, 0xDD, 0x22, 0xEF, 0x98, + 0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xCD, + 0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE, + 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE, + 0x26, 0xBA, 0x7F, 0x00, 0x80, 0x2B, + 0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xCD, + 0x1D, 0xFF, 0xDD, 0x22, 0xEF, 0x98, + 0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE, + 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE, + 0xE2, 0x00, 0x04, 0xBC, 0xE2, 0xB9, + 0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE, + 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE, + 0x26, 0xBA, 0x7F, 0x00, 0x80, 0x2B, + 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE, + 0xFA, 0xCD +}; + +const q7_t *filtering_coeffs_b_q7 = filtering_coeffs_q7 + 4; +const q7_t *filtering_coeffs_c_q7 = filtering_coeffs_q7 + 8; + +/*--------------------------------------------------------------------------------*/ +/* Tap Delay Lists */ +/*--------------------------------------------------------------------------------*/ +//const int32_t filtering_tap_delay[FILTERING_MAX_NUMTAPS] = { +// 0xEE, 0x00, 0x10, 0x0B, 0xF6, 0xD9, +// 0x1D, 0xFF, 0xDD, 0x1A, 0xEF, 0xE8, +// 0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xDD, +// 0x04, 0xEC, 0xE2, 0x00, 0x2B, 0xFE, +// 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE, +// 0x20, 0xDF, 0x21 +//}; + +const int32_t filtering_tap_delay[FILTERING_MAX_NUMTAPS] = { + 0x00, 0x01, 0x10, 0x0B, 0x03, 0x05, + 0x1D, 0x21, 0x11, 0x1A, 0x1F, 0x07, + 0x20, 0x01, 0x10, 0x0B, 0x03, 0x05, + 0x1D, 0x21, 0x11, 0x1A, 0x1F, 0x07, + 0x00, 0x01, 0x10, 0x0B, 0x03, 0x05, + 0x1D, 0x21, 0x11 +}; + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c new file mode 100644 index 0000000..453bad6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c @@ -0,0 +1,17 @@ +#include "jtest.h" +#include "filtering_tests.h" + +JTEST_DEFINE_GROUP(filtering_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_GROUP_CALL(biquad_tests); + JTEST_GROUP_CALL(conv_tests); + JTEST_GROUP_CALL(correlate_tests); + JTEST_GROUP_CALL(fir_tests); + JTEST_GROUP_CALL(iir_tests); + JTEST_GROUP_CALL(lms_tests); + + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c new file mode 100644 index 0000000..14925d7 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c @@ -0,0 +1,402 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +#define FIR_DEFINE_TEST(suffix, config_suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir##config_suffix##_##suffix##_test, \ + arm_fir##config_suffix##_##suffix) \ + { \ + arm_fir_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps \ + , \ + /* Initialize the FIR Instances */ \ + arm_fir_init_##suffix( \ + &fir_inst_fut, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n", \ + (int)blockSize, \ + (int)numTaps); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir##config_suffix##_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_fir_init_##suffix( \ + &fir_inst_ref, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + ref_fir##config_suffix##_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define FIR_INTERPOLATE_DEFINE_TEST(suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir_interpolate_##suffix##_test, \ + arm_fir_interpolate_##suffix) \ + { \ + arm_fir_interpolate_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_interpolate_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps2 \ + , \ + TEMPLATE_DO_ARR_DESC( \ + L_idx, uint8_t, L, filtering_Ls \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n" \ + "Upsample factor: %d\n", \ + (int)blockSize, \ + (int)numTaps, \ + (int)L); \ + \ + /* Initialize the FIR Instances */ \ + arm_fir_interpolate_init_##suffix( \ + &fir_inst_fut, L, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir_interpolate_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_fir_interpolate_init_##suffix( \ + &fir_inst_ref, L, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + ref_fir_interpolate_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize * (uint32_t)L, \ + output_type)))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define FIR_DECIMATE_DEFINE_TEST(suffix, config_suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir_decimate##config_suffix##_##suffix##_test, \ + arm_fir_decimate##config_suffix##_##suffix) \ + { \ + arm_fir_decimate_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_decimate_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps \ + , \ + TEMPLATE_DO_ARR_DESC( \ + M_idx, uint8_t, M, filtering_Ms \ + , \ + if (blockSize % M == 0) \ + { \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n" \ + "Decimation Factor: %d\n", \ + (int)blockSize, \ + (int)numTaps, \ + (int)M); \ + \ + /* Initialize the FIR Instances */ \ + arm_fir_decimate_init_##suffix( \ + &fir_inst_fut, numTaps, M, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir_decimate##config_suffix##_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_fir_decimate_init_##suffix( \ + &fir_inst_ref, numTaps, M, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + ref_fir_decimate##config_suffix##_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize / M, \ + output_type); \ + }))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define FIR_LATTICE_DEFINE_TEST(suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir_lattice_##suffix##_test, \ + arm_fir_lattice_##suffix) \ + { \ + arm_fir_lattice_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_lattice_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numstages_idx, uint16_t, numStages, filtering_numstages \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Stages: %d\n", \ + (int)blockSize, \ + (int)numStages); \ + \ + /* Initialize the FIR Instances */ \ + arm_fir_lattice_init_##suffix( \ + &fir_inst_fut, numStages, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir_lattice_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_fir_lattice_init_##suffix( \ + &fir_inst_ref, numStages, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState); \ + \ + ref_fir_lattice_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + + +#define FIR_SPARSE_DEFINE_TEST(suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir_sparse_##suffix##_test, \ + arm_fir_sparse_##suffix) \ + { \ + arm_fir_sparse_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_sparse_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n" \ + "Tap Delay: %d\n", \ + (int)blockSize, \ + (int)numTaps, \ + (int)FILTERING_MAX_TAP_DELAY); \ + \ + /* Initialize the FIR Instances */ \ + arm_fir_sparse_init_##suffix( \ + &fir_inst_fut, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, \ + (int32_t*)filtering_tap_delay, \ + FILTERING_MAX_TAP_DELAY, blockSize); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir_sparse_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + (void *) filtering_scratch, \ + blockSize)); \ + \ + arm_fir_sparse_init_##suffix( \ + &fir_inst_ref, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, \ + (int32_t*)filtering_tap_delay, \ + FILTERING_MAX_TAP_DELAY, blockSize); \ + \ + ref_fir_sparse_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + (void *) filtering_scratch, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define FIR_SPARSE2_DEFINE_TEST(suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir_sparse_##suffix##_test, \ + arm_fir_sparse_##suffix) \ + { \ + arm_fir_sparse_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_sparse_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n" \ + "Tap Delay: %d\n", \ + (int)blockSize, \ + (int)numTaps, \ + (int)FILTERING_MAX_TAP_DELAY); \ + \ + /* Initialize the FIR Instances */ \ + arm_fir_sparse_init_##suffix( \ + &fir_inst_fut, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, \ + (int32_t*)filtering_tap_delay, \ + FILTERING_MAX_TAP_DELAY, blockSize); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir_sparse_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + (void *) filtering_scratch, \ + (void *) filtering_scratch2, \ + blockSize)); \ + \ + arm_fir_sparse_init_##suffix( \ + &fir_inst_ref, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, \ + (int32_t*)filtering_tap_delay, \ + FILTERING_MAX_TAP_DELAY, blockSize); \ + \ + ref_fir_sparse_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + (void *) filtering_scratch, \ + (void *) filtering_scratch2, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +FIR_DEFINE_TEST(f32,,float32_t); +FIR_DEFINE_TEST(q31,,q31_t); +FIR_DEFINE_TEST(q15,,q15_t); +FIR_DEFINE_TEST(q31,_fast,q31_t); +FIR_DEFINE_TEST(q15,_fast,q15_t); +FIR_DEFINE_TEST(q7,,q7_t); + +FIR_LATTICE_DEFINE_TEST(f32,float32_t); +FIR_LATTICE_DEFINE_TEST(q31,q31_t); +FIR_LATTICE_DEFINE_TEST(q15,q15_t); + +FIR_INTERPOLATE_DEFINE_TEST(f32,float32_t); +FIR_INTERPOLATE_DEFINE_TEST(q31,q31_t); +FIR_INTERPOLATE_DEFINE_TEST(q15,q15_t); + +FIR_DECIMATE_DEFINE_TEST(f32,,float32_t); +FIR_DECIMATE_DEFINE_TEST(q31,,q31_t); +FIR_DECIMATE_DEFINE_TEST(q15,,q15_t); +FIR_DECIMATE_DEFINE_TEST(q31,_fast,q31_t); +FIR_DECIMATE_DEFINE_TEST(q15,_fast,q15_t); + +FIR_SPARSE_DEFINE_TEST(f32,float32_t); +FIR_SPARSE_DEFINE_TEST(q31,q31_t); +FIR_SPARSE2_DEFINE_TEST(q15,q15_t); +FIR_SPARSE2_DEFINE_TEST(q7,q7_t); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(fir_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_fir_f32_test); + JTEST_TEST_CALL(arm_fir_q31_test); + JTEST_TEST_CALL(arm_fir_q15_test); + JTEST_TEST_CALL(arm_fir_q7_test); + JTEST_TEST_CALL(arm_fir_fast_q31_test); + JTEST_TEST_CALL(arm_fir_fast_q15_test); + + JTEST_TEST_CALL(arm_fir_lattice_f32_test); + JTEST_TEST_CALL(arm_fir_lattice_q31_test); + JTEST_TEST_CALL(arm_fir_lattice_q15_test); + + JTEST_TEST_CALL(arm_fir_interpolate_f32_test); + JTEST_TEST_CALL(arm_fir_interpolate_q31_test); + JTEST_TEST_CALL(arm_fir_interpolate_q15_test); + + JTEST_TEST_CALL(arm_fir_decimate_f32_test); + JTEST_TEST_CALL(arm_fir_decimate_q31_test); + JTEST_TEST_CALL(arm_fir_decimate_q15_test); + JTEST_TEST_CALL(arm_fir_decimate_fast_q31_test); + JTEST_TEST_CALL(arm_fir_decimate_fast_q15_test); + + JTEST_TEST_CALL(arm_fir_sparse_f32_test); + JTEST_TEST_CALL(arm_fir_sparse_q31_test); + JTEST_TEST_CALL(arm_fir_sparse_q15_test); + JTEST_TEST_CALL(arm_fir_sparse_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c new file mode 100644 index 0000000..1d4a0ac --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c @@ -0,0 +1,76 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +#define IIR_DEFINE_TEST(suffix, output_type) \ + JTEST_DEFINE_TEST(arm_iir_lattice_##suffix##_test, \ + arm_iir_lattice_##suffix) \ + { \ + arm_iir_lattice_instance_##suffix iir_inst_fut = { 0 }; \ + arm_iir_lattice_instance_##suffix iir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numstages_idx, uint16_t, numStages, filtering_numstages \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Stages: %d\n", \ + (int)blockSize, \ + (int)numStages); \ + \ + /* Initialize the IIR Instances */ \ + arm_iir_lattice_init_##suffix( \ + &iir_inst_fut, numStages, (output_type*)filtering_coeffs_b_##suffix, \ + (output_type*)filtering_coeffs_c_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + JTEST_COUNT_CYCLES( \ + arm_iir_lattice_##suffix( \ + &iir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_iir_lattice_init_##suffix( \ + &iir_inst_ref, numStages, (output_type*)filtering_coeffs_b_##suffix, \ + (output_type*)filtering_coeffs_c_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + ref_iir_lattice_##suffix( \ + &iir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +IIR_DEFINE_TEST(f32, float32_t); +IIR_DEFINE_TEST(q31, q31_t); +IIR_DEFINE_TEST(q15, q15_t); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(iir_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_iir_lattice_f32_test); + JTEST_TEST_CALL(arm_iir_lattice_q31_test); + JTEST_TEST_CALL(arm_iir_lattice_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c new file mode 100644 index 0000000..deadd7c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c @@ -0,0 +1,219 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +static const float32_t mu_f32 = 0.00854f;//1.0f; +static const float32_t mu2_f32 = 1.0f; +static const q31_t mu_q31 = 0x7fffffff; +static const q15_t mu_q15 = 0x7fff; + +#define LMS_DEFINE_TEST(suffix, config_suffix, output_type, mu) \ + JTEST_DEFINE_TEST(arm_lms##config_suffix##_##suffix##_test, \ + arm_lms##config_suffix##_##suffix) \ + { \ + arm_lms##config_suffix##_instance_##suffix lms_inst_fut = { 0 }; \ + arm_lms##config_suffix##_instance_##suffix lms_inst_ref = { 0 }; \ + arm_fir_instance_##suffix fir_inst = { 0 }; \ + uint32_t i; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, lms_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps \ + , \ + /* Initialize the FIR Instances */ \ + arm_fir_init_##suffix( \ + &fir_inst, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + ref_fir_##suffix( \ + &fir_inst, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_input_lms, \ + blockSize); \ + \ + for(i=0;i> 6; \ + } \ + \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n" \ + "Post Shift: %d\n", \ + (int)blockSize, \ + (int)numTaps, \ + (int)postShift); \ + \ + /* Initialize the LMS Instances */ \ + arm_lms##config_suffix##_init_##suffix( \ + &lms_inst_fut, numTaps, \ + (output_type*)filtering_coeffs_lms, \ + (void *) filtering_pState, mu_##suffix, blockSize, postShift); \ + \ + JTEST_COUNT_CYCLES( \ + arm_lms##config_suffix##_##suffix( \ + &lms_inst_fut, \ + (void *) filtering_output_f32_fut, \ + (void *) filtering_input_lms, \ + (void *) filtering_output_fut, \ + (void *) ((output_type*)filtering_output_fut+blockSize), \ + blockSize)); \ + \ + for(i=0;i= 6010050) && !defined (__MICROLIB) +__asm(" .global __ARM_use_no_argv\n"); +#endif + + +void debug_init(void) +{ + uint32_t * SHCSR_ptr = (uint32_t *) 0xE000ED24; /* System Handler Control and State Register */ + *SHCSR_ptr |= 0x70000; /* Enable UsageFault, BusFault, and MemManage fault*/ +} + +int main(void) +{ +#if !defined(FILEIO) + debug_init(); +#endif + + JTEST_INIT(); /* Initialize test framework. */ + + JTEST_GROUP_CALL(all_tests); /* Run all tests. */ + + JTEST_ACT_EXIT_FW(); /* Exit test framework. */ +#if !defined(FILEIO) + while (1); /* Never return. */ +#endif +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c new file mode 100644 index 0000000..2b1d30d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c @@ -0,0 +1,509 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param float* Pointer to the reference buffer + * @param float* Pointer to the test buffer + * @param uint32_t total number of samples + * @return float SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(100000.0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(100000.0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(100000.0); + } + + + SNR = 10 * log10f (EnergySignal / EnergyError); + + /* Checking for a NAN value in SNR */ + test = (int *)(&SNR); + temp = *test; + + if (temp == 0x7FC00000) + { + return(100000.0); + } + + return (SNR); + +} + + + +double arm_snr_f64(double *pRef, double *pTest, uint32_t buffSize) +{ + double EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + double SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(100000.0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(100000.0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(100000.0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + /* Checking for a NAN value in SNR */ + test = (int *)(&SNR); + temp = *test; + + if (temp == 0x7FC00000) + { + return(10000.0); + } + + return (SNR); + +} + +/** + * @brief Provide guard bits for Input buffer + * @param q15_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param q15_t* Pointer to Ref buffer + * @param q15_t* Pointer to Test buffer + * @param uint32_t number of samples in the buffer + * @return none + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param q31_t* Pointer to Ref buffer + * @param q31_t* Pointer to Test buffer + * @param uint32_t number of samples in the buffer + * @return none + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param q31_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param q31_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param uint32_t number of additions + * @return none + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Converts Q15 to floating-point + * @param uint32_t number of samples in the buffer + * @return none + */ + +void arm_apply_guard_bits (float32_t * pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param uint32_t number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param pIn input buffer + * @param numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c new file mode 100644 index 0000000..e9d1dcf --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_ADD_TEST(suffix) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \ + mat_add, \ + suffix, \ + MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT, \ + MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS, \ + MATRIX_COMPARE_INTERFACE) + +JTEST_ARM_MAT_ADD_TEST(f32); +JTEST_ARM_MAT_ADD_TEST(q31); +JTEST_ARM_MAT_ADD_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_add_tests) +{ + JTEST_TEST_CALL(arm_mat_add_f32_test); + JTEST_TEST_CALL(arm_mat_add_q31_test); + JTEST_TEST_CALL(arm_mat_add_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c new file mode 100644 index 0000000..43bc3c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c @@ -0,0 +1,59 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_CMPLX_MULT_TEST(suffix, comparison_interface) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \ + mat_cmplx_mult, \ + suffix, \ + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, \ + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, \ + comparison_interface) + +JTEST_ARM_MAT_CMPLX_MULT_TEST(f32, MATRIX_SNR_COMPARE_INTERFACE); +JTEST_ARM_MAT_CMPLX_MULT_TEST(q31, MATRIX_COMPARE_INTERFACE); + +/*--------------------------------------------------------------------------------*/ +/* Q15 Uses a Different interface than the others. */ +/*--------------------------------------------------------------------------------*/ + +#define ARM_mat_cmplx_mult_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, \ + (void *) &matrix_output_fut, \ + (q15_t *) matrix_output_scratch) + +JTEST_DEFINE_TEST(arm_mat_cmplx_mult_q15_test, arm_mat_cmplx_mult_q15) +{ + MATRIX_TEST_TEMPLATE_ELT2( + matrix_q15_a_inputs, + matrix_q15_b_inputs, + arm_matrix_instance_q15 * , + arm_matrix_instance_q15, + TYPE_FROM_ABBREV(q15), + arm_mat_cmplx_mult_q15, + ARM_mat_cmplx_mult_q15_INPUT_INTERFACE, + ref_mat_cmplx_mult_q15, + REF_mat_cmplx_mult_INPUT_INTERFACE, + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, + MATRIX_COMPARE_INTERFACE); +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_cmplx_mult_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_cmplx_mult_f32_test); + JTEST_TEST_CALL(arm_mat_cmplx_mult_q31_test); + JTEST_TEST_CALL(arm_mat_cmplx_mult_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c new file mode 100644 index 0000000..67d0190 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c @@ -0,0 +1,58 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_INIT_TEST(suffix) \ + JTEST_DEFINE_TEST(arm_mat_init_##suffix##_test, \ + arm_mat_init_##suffix) \ + { \ + const uint16_t rows = 4; \ + const uint16_t cols = 2; \ + arm_matrix_instance_##suffix matrix = {0}; \ + /* TYPE_FROM_ABBREV(suffix) data[rows*cols] = {0}; */ \ + TYPE_FROM_ABBREV(suffix) data[4*2] = {0}; \ + \ + arm_mat_init_##suffix(&matrix, \ + rows, \ + cols, \ + data); \ + \ + JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", \ + (int)matrix.numRows, \ + (int)matrix.numCols); \ + \ + if ((matrix.numRows == rows) && \ + (matrix.numCols == cols) && \ + (matrix.pData == data)) \ + { \ + return JTEST_TEST_PASSED; \ + } \ + else \ + { \ + return JTEST_TEST_FAILED; \ + } \ + \ + } + +JTEST_ARM_MAT_INIT_TEST(f32); +JTEST_ARM_MAT_INIT_TEST(q31); +JTEST_ARM_MAT_INIT_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_init_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_init_f32_test); + JTEST_TEST_CALL(arm_mat_init_q31_test); + JTEST_TEST_CALL(arm_mat_init_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c new file mode 100644 index 0000000..4ad4cef --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c @@ -0,0 +1,92 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +JTEST_DEFINE_TEST(arm_mat_inverse_f32_test, arm_mat_inverse_f32) +{ + TEMPLATE_DO_ARR_DESC( + mat_idx, arm_matrix_instance_f32 *, mat_ptr, matrix_f32_invertible_inputs + , + JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", + (int)mat_ptr->numRows, + (int)mat_ptr->numCols); + + if (MATRIX_TEST_VALID_SQUARE_DIMENSIONS(arm_matrix_instance_f32 *, mat_ptr)) + { + MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f32 *, mat_ptr); + + /* arm_mat_inverse_f32() modifies its source input. Use the scratch + * buffer to store a copy of the intended input. */ + { + float32_t * original_pdata_ptr = mat_ptr->pData; + + memcpy(matrix_output_scratch, + mat_ptr->pData, + mat_ptr->numRows * mat_ptr->numCols * sizeof(float32_t)); + mat_ptr->pData = (void*) &matrix_output_scratch; + + JTEST_COUNT_CYCLES(arm_mat_inverse_f32(mat_ptr, &matrix_output_fut)); + mat_ptr->pData = original_pdata_ptr; + } + + ref_mat_inverse_f32(mat_ptr, &matrix_output_ref); + + MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_f32, + float32_t); + }); + + return JTEST_TEST_PASSED; +} + +JTEST_DEFINE_TEST(arm_mat_inverse_f64_test, arm_mat_inverse_f64) +{ + TEMPLATE_DO_ARR_DESC( + mat_idx, arm_matrix_instance_f64 *, mat_ptr, matrix_f64_invertible_inputs + , + JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", + (int)mat_ptr->numRows, + (int)mat_ptr->numCols); + + if (MATRIX_TEST_VALID_SQUARE_DIMENSIONS(arm_matrix_instance_f64 *, mat_ptr)) + { + MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f64 *, mat_ptr); + + /* arm_mat_inverse_f64() modifies its source input. Use the scratch + * buffer to store a copy of the intended input. */ + { + float64_t * original_pdata_ptr = mat_ptr->pData; + + memcpy(matrix_output_scratch, + mat_ptr->pData, + mat_ptr->numRows * mat_ptr->numCols * sizeof(float64_t)); + mat_ptr->pData = (void*) &matrix_output_scratch; + + JTEST_COUNT_CYCLES(arm_mat_inverse_f64(mat_ptr, &matrix_output_fut64)); + mat_ptr->pData = original_pdata_ptr; + } + + ref_mat_inverse_f64(mat_ptr, &matrix_output_ref64); + + MATRIX_DBL_SNR_COMPARE_INTERFACE(arm_matrix_instance_f64); + }); + + return JTEST_TEST_PASSED; +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_inverse_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_inverse_f32_test); + JTEST_TEST_CALL(arm_mat_inverse_f64_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c new file mode 100644 index 0000000..7cdf71b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c @@ -0,0 +1,57 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_MULT_FAST_TEST(suffix) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \ + mat_mult_fast, \ + suffix, \ + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, \ + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, \ + MATRIX_SNR_COMPARE_INTERFACE) + +JTEST_ARM_MAT_MULT_FAST_TEST(q31); + +/*--------------------------------------------------------------------------------*/ +/* Q15 Uses a Different interface than the others. */ +/*--------------------------------------------------------------------------------*/ + +#define ARM_mat_mult_fast_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, \ + (void *) &matrix_output_fut, \ + (q15_t *) matrix_output_scratch) + +JTEST_DEFINE_TEST(arm_mat_mult_fast_q15_test, arm_mat_mult_fast_q15) +{ + MATRIX_TEST_TEMPLATE_ELT2( + matrix_q15_a_inputs, + matrix_q15_b_inputs, + arm_matrix_instance_q15 * , + arm_matrix_instance_q15, + TYPE_FROM_ABBREV(q15), + arm_mat_mult_fast_q15, + ARM_mat_mult_fast_q15_INPUT_INTERFACE, + ref_mat_mult_fast_q15, + REF_mat_mult_fast_INPUT_INTERFACE, + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, + MATRIX_SNR_COMPARE_INTERFACE); +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_mult_fast_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_mult_fast_q31_test); + JTEST_TEST_CALL(arm_mat_mult_fast_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c new file mode 100644 index 0000000..f3230e0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c @@ -0,0 +1,59 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_MULT_TEST(suffix) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \ + mat_mult, \ + suffix, \ + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, \ + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, \ + MATRIX_COMPARE_INTERFACE) + +JTEST_ARM_MAT_MULT_TEST(f32); +JTEST_ARM_MAT_MULT_TEST(q31); + +/*--------------------------------------------------------------------------------*/ +/* Q15 Uses a Different interface than the others. */ +/*--------------------------------------------------------------------------------*/ + +#define ARM_mat_mult_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, \ + (void *) &matrix_output_fut, \ + (q15_t *) matrix_output_scratch) + +JTEST_DEFINE_TEST(arm_mat_mult_q15_test, arm_mat_mult_q15) +{ + MATRIX_TEST_TEMPLATE_ELT2( + matrix_q15_a_inputs, + matrix_q15_b_inputs, + arm_matrix_instance_q15 * , + arm_matrix_instance_q15, + TYPE_FROM_ABBREV(q15), + arm_mat_mult_q15, + ARM_mat_mult_q15_INPUT_INTERFACE, + ref_mat_mult_q15, + REF_mat_mult_INPUT_INTERFACE, + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, + MATRIX_COMPARE_INTERFACE); +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_mult_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_mult_f32_test); + JTEST_TEST_CALL(arm_mat_mult_q31_test); + JTEST_TEST_CALL(arm_mat_mult_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c new file mode 100644 index 0000000..cf0a1dd --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c @@ -0,0 +1,90 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +/* This is for the two fixed point cases */ +#define JTEST_ARM_MAT_SCALE_TEST(suffix,type) \ + JTEST_DEFINE_TEST(arm_mat_scale_##suffix##_test, arm_mat_scale_##suffix) \ + { \ + uint32_t i,j; \ + \ + TEMPLATE_DO_ARR_DESC( \ + mat_idx, arm_matrix_instance_##suffix *, \ + mat_ptr, matrix_##suffix##_b_inputs \ + , \ + MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT( \ + arm_matrix_instance_##suffix *, mat_ptr); \ + \ + for(i=0;inumRows, \ + (int)mat_ptr->numCols); \ + \ + JTEST_COUNT_CYCLES( \ + arm_mat_scale_##suffix(mat_ptr, \ + matrix_##suffix##_scale_values[i], \ + matrix_shift_values[j], \ + (arm_matrix_instance_##suffix*) &matrix_output_fut)); \ + \ + ref_mat_scale_##suffix(mat_ptr, \ + matrix_##suffix##_scale_values[i], \ + matrix_shift_values[j], \ + (arm_matrix_instance_##suffix*) &matrix_output_ref); \ + \ + MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_##suffix, \ + type); \ + } \ + }); \ + \ + return JTEST_TEST_PASSED; \ + } + +JTEST_DEFINE_TEST(arm_mat_scale_f32_test, arm_mat_scale_f32) +{ + uint32_t i; + + TEMPLATE_DO_ARR_DESC( + mat_idx, arm_matrix_instance_f32 *, mat_ptr, matrix_f32_b_inputs + , + MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f32 *, mat_ptr); + + for(i=0;inumRows, + (int)mat_ptr->numCols); + JTEST_COUNT_CYCLES(arm_mat_scale_f32(mat_ptr, matrix_f32_scale_values[i], &matrix_output_fut)); + + ref_mat_scale_f32(mat_ptr, matrix_f32_scale_values[i], &matrix_output_ref); + + MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_f32, + float32_t); + }); + + return JTEST_TEST_PASSED; +} + +JTEST_ARM_MAT_SCALE_TEST(q31,q31_t); +JTEST_ARM_MAT_SCALE_TEST(q15,q15_t); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_scale_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_scale_f32_test); + JTEST_TEST_CALL(arm_mat_scale_q31_test); + JTEST_TEST_CALL(arm_mat_scale_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c new file mode 100644 index 0000000..137e9cd --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c @@ -0,0 +1,34 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_SUB_TEST(suffix) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \ + mat_sub, \ + suffix, \ + MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT, \ + MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS, \ + MATRIX_COMPARE_INTERFACE) + +JTEST_ARM_MAT_SUB_TEST(f32); +JTEST_ARM_MAT_SUB_TEST(q31); +JTEST_ARM_MAT_SUB_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_sub_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_sub_f32_test); + JTEST_TEST_CALL(arm_mat_sub_q31_test); + JTEST_TEST_CALL(arm_mat_sub_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c new file mode 100644 index 0000000..8f238f8 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_TRANS_TEST(suffix) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT1( \ + mat_trans, \ + suffix, \ + MATRIX_TEST_CONFIG_TRANSPOSE_OUTPUT, \ + MATRIX_TEST_VALID_DIMENSIONS_ALWAYS) + +JTEST_ARM_MAT_TRANS_TEST(f32); +JTEST_ARM_MAT_TRANS_TEST(q31); +JTEST_ARM_MAT_TRANS_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_trans_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_trans_f32_test); + JTEST_TEST_CALL(arm_mat_trans_q31_test); + JTEST_TEST_CALL(arm_mat_trans_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c new file mode 100644 index 0000000..9043a23 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c @@ -0,0 +1,259 @@ +#include "arm_math.h" +#include "matrix_test_data.h" +#include "type_abbrev.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_fut_data[2*MATRIX_TEST_MAX_ELTS] = {0}; +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_ref_data[2*MATRIX_TEST_MAX_ELTS] = {0}; +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_scratch[MATRIX_TEST_MAX_ELTS] = {0}; + +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_fut[MATRIX_TEST_MAX_ELTS]; +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_ref[MATRIX_TEST_MAX_ELTS]; + +arm_matrix_instance_f32 matrix_output_fut = { + 0, + 0, + (float32_t *) &matrix_output_fut_data +}; + +arm_matrix_instance_f32 matrix_output_ref = { + 0, + 0, + (float32_t *) &matrix_output_ref_data +}; + +arm_matrix_instance_f64 matrix_output_fut64 = { + 0, + 0, + (float64_t *) &matrix_output_fut_data +}; + +arm_matrix_instance_f64 matrix_output_ref64 = { + 0, + 0, + (float64_t *) &matrix_output_ref_data +}; + +/*--------------------------------------------------------------------------------*/ +/* Data Buckets */ +/*--------------------------------------------------------------------------------*/ + +/** + * Pool of random data to base matrix inputs from. + */ +float32_t matrix_f32_100_rand[100] = { +/* -45.0345569674258, first number negativ causes fault in 1x1 multiplay with 0. + AC6 DSP_Lib calculatas a -0.0 which is not a 0.0 in memcmp! + */ + 45.0345569674258, -11.0261163038747, -14.6841428777929, + 0.0345569674258, -11.0261163038747, -14.6841428777929, + -20.3679194392227, 27.5712678608402, -12.1390617339732, + -19.8753669720509, 42.3379642103244, -23.7788252219155, + -23.7517765301667, 40.2716109915281, -25.8308714086167, + 32.1194040197959, 24.4692807074156, -1.32083675968276, + 31.1580458282477, -2.90766514824093, -6.97926086704160, + 10.2843089382083, 30.1014622769739, 44.4787189721646, + -9.60878544118853, -48.4596562348445, -31.1044984967456, + -6.41414114190809, 3.28255887994549, -26.9511839788442, + -31.5183679875864, 21.1215780433683, -47.0779722437854, + -0.913590753192006, -40.3545474831611, -45.6976198342192, + 18.6775433365315, -5.32162505701938, -14.9272896423117, + 34.4308792695389, 40.4880968679893, -27.8253265982760, + 42.8854139478045, -1.07473615999811, -36.8026707393665, + -33.1009970537296, -31.6488844262730, -19.3650527983443, + 43.9001561999887, -30.5235710432951, 47.9748378356085, + -38.2582349144194, 23.0330862855453, -16.2280590178623, + 44.2050590775485, 14.9115474956452, -13.1515403509664, + 0.850865538112700, 37.5942811492984, -27.4078219027601, + -6.11300268738968, -20.3324126781673, -1.13910261964209, + 40.0053846417662, 45.6134540229802, 23.1722385658670, + 12.5618560729690, 1.07715641721097, 5.01563428984222, + -32.9291952852141, -38.8880776559401, -18.1221698074118, + 7.85250610234389, -13.0753218879785, 7.52085950784656, + 14.7745963136307, 28.0227435151377, 31.7627708322262, + 12.2475086001227, -27.2335702183447, -24.1935304087933, + -7.58332402861928, -26.2716420228479, -38.8797244706213, + -44.0220457052844, -4.90762935690551, -41.8874231134215, + 29.4831416883453, 8.70447045314168, -6.43013158961009, + -9.12801538874479, 0.785828466111815, -4.11511718200689, + 28.0252068321138, -26.5220086627594, 4.70088922863450, + 42.9385970968730, 14.4318130193692, -29.2257707266972, + 46.3088539286913 +}; + +float64_t matrix_f64_100_rand[100] = { +// -45.0345569674258, -11.0261163038747, -14.6841428777929, + 45.0345569674258, -11.0261163038747, -14.6841428777929, + 0.0345569674258, -11.0261163038747, -14.6841428777929, + -20.3679194392227, 27.5712678608402, -12.1390617339732, + -19.8753669720509, 42.3379642103244, -23.7788252219155, + -23.7517765301667, 40.2716109915281, -25.8308714086167, + 32.1194040197959, 24.4692807074156, -1.32083675968276, + 31.1580458282477, -2.90766514824093, -6.97926086704160, + 10.2843089382083, 30.1014622769739, 44.4787189721646, + -9.60878544118853, -48.4596562348445, -31.1044984967456, + -6.41414114190809, 3.28255887994549, -26.9511839788442, + -31.5183679875864, 21.1215780433683, -47.0779722437854, + -0.913590753192006, -40.3545474831611, -45.6976198342192, + 18.6775433365315, -5.32162505701938, -14.9272896423117, + 34.4308792695389, 40.4880968679893, -27.8253265982760, + 42.8854139478045, -1.07473615999811, -36.8026707393665, + -33.1009970537296, -31.6488844262730, -19.3650527983443, + 43.9001561999887, -30.5235710432951, 47.9748378356085, + -38.2582349144194, 23.0330862855453, -16.2280590178623, + 44.2050590775485, 14.9115474956452, -13.1515403509664, + 0.850865538112700, 37.5942811492984, -27.4078219027601, + -6.11300268738968, -20.3324126781673, -1.13910261964209, + 40.0053846417662, 45.6134540229802, 23.1722385658670, + 12.5618560729690, 1.07715641721097, 5.01563428984222, + -32.9291952852141, -38.8880776559401, -18.1221698074118, + 7.85250610234389, -13.0753218879785, 7.52085950784656, + 14.7745963136307, 28.0227435151377, 31.7627708322262, + 12.2475086001227, -27.2335702183447, -24.1935304087933, + -7.58332402861928, -26.2716420228479, -38.8797244706213, + -44.0220457052844, -4.90762935690551, -41.8874231134215, + 29.4831416883453, 8.70447045314168, -6.43013158961009, + -9.12801538874479, 0.785828466111815, -4.11511718200689, + 28.0252068321138, -26.5220086627594, 4.70088922863450, + 42.9385970968730, 14.4318130193692, -29.2257707266972, + 46.3088539286913 +}; + +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_zeros[MATRIX_TEST_MAX_ELTS] = {0}; + +const float32_t matrix_f32_scale_values[MATRIX_MAX_COEFFS_LEN] = +{ + 43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580 , + 7.2830326091 , 66.8368719314 , 33.9778190671 , 117.8652289772 , + -129.6077797465, -14.6420815368 , 18.0239223278 , 1.0000000000 , + 55.0375037651 , 1.8674609862 , 0.00000000000 , -33.5750364909 +}; + +const q31_t matrix_q31_scale_values[MATRIX_MAX_COEFFS_LEN] = +{ + 0x0201DC90, 0x211F0D7C, 0x80000000, 0xF573B824, + 0xE85ED05B, 0x311DFB52, 0x3529E750, 0x00000000, + 0x7FFFFFFF, 0x21FA525A, 0x0971FD45, 0x05547B68, + 0x270C6366, 0x06FDD5A6, 0xF7025315, 0xB1155A1E +}; + +const q15_t matrix_q15_scale_values[MATRIX_MAX_COEFFS_LEN] = +{ + 0x0201, 0x211F, 0x8000, 0xF573, + 0xE85E, 0x311D, 0x3529, 0x0000, + 0x7FFF, 0x21FA, 0x0971, 0x0554, + 0x270C, 0x06FD, 0xF702, 0xB115 +}; + +const int32_t matrix_shift_values[MATRIX_MAX_SHIFTS_LEN] = +{ + -16, -7, 0, 7, 16 +}; + +/*--------------------------------------------------------------------------------*/ +/* Matrix Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * Define matrices by suffix (f32, q31, q15) for use in test cases. + * + * The rand1 and rand2 suffixes get their data from the same pool of random + * data, but their starting points differ by 1 element. + * + * Makes available: + * - matrix_`suffix`_1x1_rand1/2 + * - matrix_`suffix`_1x4_rand1/2 + * - matrix_`suffix`_2x4_rand1/2 + * - matrix_`suffix`_4x4_rand1/2 + */ +#define MATRIX_DEFINE_MATRICES(suffix) \ + arm_matrix_instance_##suffix matrix_##suffix##_1x1_rand1 = \ + {1, 1, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \ + arm_matrix_instance_##suffix matrix_##suffix##_1x1_rand2 = \ + {1, 1, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \ + arm_matrix_instance_##suffix matrix_##suffix##_1x1_zeros = \ + {1, 1, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}; \ + \ + arm_matrix_instance_##suffix matrix_##suffix##_1x4_rand1 = \ + {1, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \ + arm_matrix_instance_##suffix matrix_##suffix##_1x4_rand2 = \ + {1, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \ + arm_matrix_instance_##suffix matrix_##suffix##_1x4_zeros = \ + {1, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}; \ + \ + arm_matrix_instance_##suffix matrix_##suffix##_2x4_rand1 = \ + {2, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \ + arm_matrix_instance_##suffix matrix_##suffix##_2x4_rand2 = \ + {2, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \ + arm_matrix_instance_##suffix matrix_##suffix##_2x4_zeros = \ + {2, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}; \ + \ + arm_matrix_instance_##suffix matrix_##suffix##_4x4_rand1 = \ + {4, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \ + arm_matrix_instance_##suffix matrix_##suffix##_4x4_rand2 = \ + {4, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \ + arm_matrix_instance_##suffix matrix_##suffix##_4x4_zeros = \ + {4, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros} + +MATRIX_DEFINE_MATRICES(f64); +MATRIX_DEFINE_MATRICES(f32); +MATRIX_DEFINE_MATRICES(q31); +MATRIX_DEFINE_MATRICES(q15); + +/*--------------------------------------------------------------------------------*/ +/* Matrix-Input Arrays */ +/*--------------------------------------------------------------------------------*/ + +/* Define Input #ARR_DESC_t by suffix. + * + * Taking inputs in parallel from the 'a' and 'b' arrays yields the following + * test cases: + * - 1x1 multiplication by zero + * - 1x1 multiplication between random numbers + * - 1x1 * 1x4 valid dimension interaction + * - 1x1 * 2x4 invalid dimension interaction + * - 2x4 * 4x4 larger valid dimension interaction + * - 4x4 * 4x4 larger valid dimension interaction + */ +#define MATRIX_DEFINE_INPUTS(suffix) \ + ARR_DESC_DEFINE(arm_matrix_instance_##suffix *, \ + matrix_##suffix##_a_inputs, \ + 6, \ + CURLY( \ + &matrix_##suffix##_1x1_rand1, \ + &matrix_##suffix##_1x1_rand1, \ + &matrix_##suffix##_1x1_rand1, \ + &matrix_##suffix##_1x1_rand1, \ + &matrix_##suffix##_2x4_rand1, \ + &matrix_##suffix##_4x4_rand1 \ + )); \ + \ + ARR_DESC_DEFINE(arm_matrix_instance_##suffix *, \ + matrix_##suffix##_b_inputs, \ + 6, \ + CURLY( \ + &matrix_##suffix##_1x1_zeros, \ + &matrix_##suffix##_1x1_rand2, \ + &matrix_##suffix##_1x4_rand2, \ + &matrix_##suffix##_2x4_rand2, \ + &matrix_##suffix##_4x4_rand2, \ + &matrix_##suffix##_4x4_rand2 \ + )); \ + \ + ARR_DESC_DEFINE(arm_matrix_instance_##suffix *, \ + matrix_##suffix##_invertible_inputs, \ + 4, \ + CURLY( \ + &matrix_##suffix##_1x1_rand1, \ + &matrix_##suffix##_1x1_rand2, \ + &matrix_##suffix##_4x4_rand1, \ + &matrix_##suffix##_4x4_rand2 \ + )) \ + +MATRIX_DEFINE_INPUTS(f64); +MATRIX_DEFINE_INPUTS(f32); +MATRIX_DEFINE_INPUTS(q31); +MATRIX_DEFINE_INPUTS(q15); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c new file mode 100644 index 0000000..d36d820 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c @@ -0,0 +1,19 @@ +#include "jtest.h" +#include "matrix_tests.h" + +JTEST_DEFINE_GROUP(matrix_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_GROUP_CALL(mat_add_tests); + JTEST_GROUP_CALL(mat_cmplx_mult_tests); + JTEST_GROUP_CALL(mat_init_tests); + JTEST_GROUP_CALL(mat_inverse_tests); + JTEST_GROUP_CALL(mat_mult_tests); + JTEST_GROUP_CALL(mat_mult_fast_tests); + JTEST_GROUP_CALL(mat_sub_tests); + JTEST_GROUP_CALL(mat_trans_tests); + JTEST_GROUP_CALL(mat_scale_tests); + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c new file mode 100644 index 0000000..7e4f6f3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c @@ -0,0 +1,36 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAX_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + max, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_COMPARE_INTERFACE) + +JTEST_ARM_MAX_TEST(f32); +JTEST_ARM_MAX_TEST(q31); +JTEST_ARM_MAX_TEST(q15); +JTEST_ARM_MAX_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(max_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_max_f32_test); + JTEST_TEST_CALL(arm_max_q31_test); + JTEST_TEST_CALL(arm_max_q15_test); + JTEST_TEST_CALL(arm_max_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c new file mode 100644 index 0000000..ded6d28 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c @@ -0,0 +1,36 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MEAN_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + mean, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_COMPARE_INTERFACE) + +JTEST_ARM_MEAN_TEST(f32); +JTEST_ARM_MEAN_TEST(q31); +JTEST_ARM_MEAN_TEST(q15); +JTEST_ARM_MEAN_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mean_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mean_f32_test); + JTEST_TEST_CALL(arm_mean_q31_test); + JTEST_TEST_CALL(arm_mean_q15_test); + JTEST_TEST_CALL(arm_mean_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c new file mode 100644 index 0000000..2eed629 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c @@ -0,0 +1,36 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MIN_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + min, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_COMPARE_INTERFACE) + +JTEST_ARM_MIN_TEST(f32); +JTEST_ARM_MIN_TEST(q31); +JTEST_ARM_MIN_TEST(q15); +JTEST_ARM_MIN_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(min_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_min_f32_test); + JTEST_TEST_CALL(arm_min_q31_test); + JTEST_TEST_CALL(arm_min_q15_test); + JTEST_TEST_CALL(arm_min_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c new file mode 100644 index 0000000..fae2351 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c @@ -0,0 +1,36 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_POWER_TEST(suffix, output_type) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + power, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_SNR_COMPARE_INTERFACE) + +JTEST_ARM_POWER_TEST(f32, float32_t); +JTEST_ARM_POWER_TEST(q31, q63_t); +JTEST_ARM_POWER_TEST(q15, q63_t); +JTEST_ARM_POWER_TEST(q7, q31_t); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(power_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_power_f32_test); + JTEST_TEST_CALL(arm_power_q31_test); + JTEST_TEST_CALL(arm_power_q15_test); + JTEST_TEST_CALL(arm_power_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c new file mode 100644 index 0000000..46d8e52 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c @@ -0,0 +1,34 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_RMS_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + rms, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_SNR_COMPARE_INTERFACE) + +JTEST_ARM_RMS_TEST(f32); +JTEST_ARM_RMS_TEST(q31); +JTEST_ARM_RMS_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(rms_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_rms_f32_test); + JTEST_TEST_CALL(arm_rms_q31_test); + JTEST_TEST_CALL(arm_rms_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c new file mode 100644 index 0000000..18eac07 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c @@ -0,0 +1,94 @@ +#include "statistics_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + + +ARR_DESC_DEFINE(STATISTICS_BIGGEST_INPUT_TYPE, + statistics_output_fut, + STATISTICS_MAX_INPUT_ELEMENTS, + CURLY(0)); + +ARR_DESC_DEFINE(STATISTICS_BIGGEST_INPUT_TYPE, + statistics_output_ref, + STATISTICS_MAX_INPUT_ELEMENTS, + CURLY(0)); + +uint32_t statistics_idx_fut = 0; +uint32_t statistics_idx_ref = 0; + +STATISTICS_BIGGEST_INPUT_TYPE +statistics_output_f32_ref[STATISTICS_MAX_INPUT_ELEMENTS]; + +STATISTICS_BIGGEST_INPUT_TYPE +statistics_output_f32_fut[STATISTICS_MAX_INPUT_ELEMENTS]; + +/*--------------------------------------------------------------------------------*/ +/* Block Sizes */ +/*--------------------------------------------------------------------------------*/ + +/* + To change test parameter values add/remove values inside CURLY and update + the preceeding parameter to reflect the number of values inside CURLY. +*/ + +ARR_DESC_DEFINE(uint32_t, + statistics_block_sizes, + 4, + CURLY(1, 2, 15, 32)); + +/*--------------------------------------------------------------------------------*/ +/* Test Data */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(float32_t, + statistics_f_32, + 32, + CURLY( + -0.0865129623056441 , -0.3331168756476194, + 0.0250664612949661 , 0.0575352840717098, + -0.2292942701362928 , 0.2381830931285998, + 0.2378328403304206 , -0.0075266553186635, + 0.0654584722817308 , 0.0349278285641849, + -0.0373417155362879 , 0.1451581096586606, + -0.1176633086028378 , 0.4366371636394202, + -0.0272791766173191 , 0.0227862627041619, + 0.2133536422718378 , 0.0118562921047211, + -0.0191296810967338 , -0.1664698927300045, + 0.0588821632785281 , -0.2672363715875608, + 0.1428649103637904 , 0.3247124128892542, + -0.1383551403404573 , 0.1715993345656525, + 0.2508002843205065 , -0.3187459152894954, + -0.2881928863802040 , 0.1142295247316356, + -0.0799771155430726 , 0.1379994750928690 + )); + + +ARR_DESC_DEFINE_SUBSET(statistics_f_31, + statistics_f_32, + 31); + +ARR_DESC_DEFINE_SUBSET(statistics_f_15, + statistics_f_32, + 15); + +ARR_DESC_DEFINE_SUBSET(statistics_f_2, + statistics_f_32, + 2); + +ARR_DESC_DEFINE(float32_t, + statistics_zeros, + 32, + CURLY(0)); + +/* Aggregate all float datasets */ +ARR_DESC_DEFINE(ARR_DESC_t *, + statistics_f_all, + 4, + CURLY( + &statistics_zeros, + &statistics_f_2, + &statistics_f_15, + &statistics_f_32 + )); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c new file mode 100644 index 0000000..41dcf9a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c @@ -0,0 +1,14 @@ +#include "jtest.h" +#include "statistics_tests.h" + +JTEST_DEFINE_GROUP(statistics_tests) +{ + JTEST_GROUP_CALL(max_tests); + JTEST_GROUP_CALL(mean_tests); + JTEST_GROUP_CALL(min_tests); + JTEST_GROUP_CALL(power_tests); + JTEST_GROUP_CALL(rms_tests); + JTEST_GROUP_CALL(std_tests); + JTEST_GROUP_CALL(var_tests); + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c new file mode 100644 index 0000000..2d30a34 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c @@ -0,0 +1,34 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_STD_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + std, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_SNR_COMPARE_INTERFACE) + +JTEST_ARM_STD_TEST(f32); +JTEST_ARM_STD_TEST(q31); +JTEST_ARM_STD_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(std_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_std_f32_test); + JTEST_TEST_CALL(arm_std_q31_test); + JTEST_TEST_CALL(arm_std_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c new file mode 100644 index 0000000..41f8cd2 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c @@ -0,0 +1,34 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_VAR_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + var, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_SNR_COMPARE_INTERFACE) + +JTEST_ARM_VAR_TEST(f32); +JTEST_ARM_VAR_TEST(q31); +JTEST_ARM_VAR_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(var_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_var_f32_test); + JTEST_TEST_CALL(arm_var_q31_test); + JTEST_TEST_CALL(arm_var_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c new file mode 100644 index 0000000..63d58ff --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "support_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "support_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_COPY_TEST(suffix) \ + SUPPORT_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + copy, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + SUPPORT_COMPARE_INTERFACE) + +JTEST_ARM_COPY_TEST(f32); +JTEST_ARM_COPY_TEST(q31); +JTEST_ARM_COPY_TEST(q15); +JTEST_ARM_COPY_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(copy_tests) +{ + JTEST_TEST_CALL(arm_copy_f32_test); + JTEST_TEST_CALL(arm_copy_q31_test); + JTEST_TEST_CALL(arm_copy_q15_test); + JTEST_TEST_CALL(arm_copy_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c new file mode 100644 index 0000000..0831b75 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c @@ -0,0 +1,36 @@ +#include "jtest.h" +#include "support_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "support_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_FILL_TEST(suffix) \ + SUPPORT_DEFINE_TEST_TEMPLATE_ELT1_BLK( \ + fill, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + SUPPORT_COMPARE_INTERFACE) + +JTEST_ARM_FILL_TEST(f32); +JTEST_ARM_FILL_TEST(q31); +JTEST_ARM_FILL_TEST(q15); +JTEST_ARM_FILL_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(fill_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_fill_f32_test); + JTEST_TEST_CALL(arm_fill_q31_test); + JTEST_TEST_CALL(arm_fill_q15_test); + JTEST_TEST_CALL(arm_fill_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c new file mode 100644 index 0000000..da21ba9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c @@ -0,0 +1,85 @@ +#include "arm_math.h" +#include "support_test_data.h" + +#define MAX_INPUT_ELEMENTS 32 +#define BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(BIGGEST_INPUT_TYPE, + support_output_fut, + MAX_INPUT_ELEMENTS, + CURLY(0)); + +ARR_DESC_DEFINE(BIGGEST_INPUT_TYPE, + support_output_ref, + MAX_INPUT_ELEMENTS, + CURLY(0)); + +/*--------------------------------------------------------------------------------*/ +/* Block Sizes */ +/*--------------------------------------------------------------------------------*/ + +/* + To change test parameter values add/remove values inside CURLY and update + the preceeding parameter to reflect the number of values inside CURLY. +*/ + +ARR_DESC_DEFINE(uint32_t, + support_block_sizes, + 4, + CURLY( 2, 7, 15, 32)); + +/*--------------------------------------------------------------------------------*/ +/* Numbers */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(uint32_t, + support_elts, + 4, + CURLY( 0, 1, 0x80000000, 0x7fffffff)); + +/*--------------------------------------------------------------------------------*/ +/* Test Data */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(float32_t, + support_f_32, + 32, + CURLY( + 0.24865986 , -0.13364227, -0.27233250 , -7.33488200, + 0.42190653 , 1.17435880 , -0.49824914 , 0.87883663, + 0.63066370 , 1.80275680 , -84.83916000, -2.06773800, + 7.63452500 , 1.01487610 , -0.65785825 , 1.78019030, + -0.34160388, 0.68546050 , -1.81721590 , -0.10340453, + -4.48600340, -1.69763480, -1.26022340 , -1.58457480, + 0.51993870 , 2.83526470 , -0.21502694 , -0.57690346, + -0.22945681, 0.79509383 , 0.07275216 , -2.16279080 + )); + +/* Alias the 32 element array with wrappers that end sooner. */ +ARR_DESC_DEFINE_SUBSET(support_f_15, + support_f_32, + 15); + +ARR_DESC_DEFINE_SUBSET(support_f_2, + support_f_32, + 2); + +ARR_DESC_DEFINE(float32_t, + support_zeros, + 32, + CURLY(0)); + +/* Aggregate all float datasets. */ +ARR_DESC_DEFINE(ARR_DESC_t *, + support_f_all, + 4, + CURLY( + &support_zeros, + &support_f_2, + &support_f_15, + &support_f_32 + )); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c new file mode 100644 index 0000000..714f75c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c @@ -0,0 +1,10 @@ +#include "jtest.h" +#include "support_tests.h" + +JTEST_DEFINE_GROUP(support_tests) +{ + JTEST_GROUP_CALL(copy_tests); + JTEST_GROUP_CALL(fill_tests); + JTEST_GROUP_CALL(x_to_y_tests); + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c new file mode 100644 index 0000000..1d4107b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c @@ -0,0 +1,80 @@ +#include "jtest.h" +#include "support_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "support_templates.h" +#include "type_abbrev.h" + +/* Aliases to play nicely with templates. */ +#define arm_f32_to_q31 arm_float_to_q31 +#define arm_f32_to_q15 arm_float_to_q15 +#define arm_f32_to_q7 arm_float_to_q7 +#define arm_q31_to_f32 arm_q31_to_float +#define arm_q15_to_f32 arm_q15_to_float +#define arm_q7_to_f32 arm_q7_to_float +#define ref_f32_to_q31 ref_float_to_q31 +#define ref_f32_to_q15 ref_float_to_q15 +#define ref_f32_to_q7 ref_float_to_q7 +#define ref_q31_to_f32 ref_q31_to_float +#define ref_q15_to_f32 ref_q15_to_float +#define ref_q7_to_f32 ref_q7_to_float + +#define JTEST_ARM_X_TO_Y_TEST(prefix, suffix) \ + JTEST_DEFINE_TEST(arm_##prefix##_to_##suffix##_test, \ + arm_##prefix##_to_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_BLK( \ + support_f_all, \ + support_block_sizes, \ + TYPE_FROM_ABBREV(prefix), \ + TYPE_FROM_ABBREV(suffix), \ + arm_##prefix##_to_##suffix, \ + ARM_x_to_y_INPUT_INTERFACE, \ + ref_##prefix##_to_##suffix, \ + REF_x_to_y_INPUT_INTERFACE, \ + SUPPORT_COMPARE_INTERFACE); \ + } + +JTEST_ARM_X_TO_Y_TEST(f32, q31); +JTEST_ARM_X_TO_Y_TEST(f32, q15); +JTEST_ARM_X_TO_Y_TEST(f32, q7); + +JTEST_ARM_X_TO_Y_TEST(q31, f32); +JTEST_ARM_X_TO_Y_TEST(q31, q15); +JTEST_ARM_X_TO_Y_TEST(q31, q7); + +JTEST_ARM_X_TO_Y_TEST(q15, f32); +JTEST_ARM_X_TO_Y_TEST(q15, q31); +JTEST_ARM_X_TO_Y_TEST(q15, q7); + +JTEST_ARM_X_TO_Y_TEST(q7, f32); +JTEST_ARM_X_TO_Y_TEST(q7, q31); +JTEST_ARM_X_TO_Y_TEST(q7, q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(x_to_y_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_f32_to_q31_test); + JTEST_TEST_CALL(arm_f32_to_q15_test); + JTEST_TEST_CALL(arm_f32_to_q7_test); + + JTEST_TEST_CALL(arm_q31_to_f32_test); + JTEST_TEST_CALL(arm_q31_to_q15_test); + JTEST_TEST_CALL(arm_q31_to_q7_test); + + JTEST_TEST_CALL(arm_q15_to_f32_test); + JTEST_TEST_CALL(arm_q15_to_q31_test); + JTEST_TEST_CALL(arm_q15_to_q7_test); + + JTEST_TEST_CALL(arm_q7_to_f32_test); + JTEST_TEST_CALL(arm_q7_to_q31_test); + JTEST_TEST_CALL(arm_q7_to_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c new file mode 100644 index 0000000..9fb8834 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c @@ -0,0 +1,183 @@ +#include "jtest.h" +#include "ref.h" +#include "arr_desc.h" +#include "transform_templates.h" +#include "transform_test_data.h" +#include "type_abbrev.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +#define CFFT_FN_NAME(fn_specifier, type_suffix) \ + arm_cfft_##fn_specifier##_##type_suffix \ + +#define CFFT_TEST_NAME(fn_specifier, type_suffix, config_suffix) \ + arm_cfft_##fn_specifier##_##type_suffix##_##config_suffix##_test \ + +/*--------------------------------------------------------------------------------*/ +/* Function Aliases */ +/*--------------------------------------------------------------------------------*/ + +/* These aliases allow expansions in the CFFT_FAMILY_DEFINE_TEST() template to + make sense */ +#define arm_cfft_mag_init_f32 arm_cfft_radix4_init_f32 +#define arm_cfft_mag_init_q31 arm_cfft_radix4_init_q31 +#define arm_cfft_mag_init_q15 arm_cfft_radix4_init_q15 +#define arm_cfft_mag_instance_f32 arm_cfft_radix4_instance_f32 +#define arm_cfft_mag_instance_q31 arm_cfft_radix4_instance_q31 +#define arm_cfft_mag_instance_q15 arm_cfft_radix4_instance_q15 +#define transform_mag_fftlens transform_radix4_fftlens + +/*--------------------------------------------------------------------------------*/ +/* Test Definition */ +/*--------------------------------------------------------------------------------*/ + +/** + * Defines a test for the family of CFFT transforms. + * + * The family of CFFT transforms includes: + * + * - arm_cfft_radix4_xxx + * - arm_cfft_radix2_xxx + * - arm_cfft_mag_xxx + * + * Where xxx can be f32, q31, or q15. + * + * @param fn_specifier Allowed values: radix4, radix2, mag. + * @param type_suffix Allowed values: f32, q31, q15. + * + * @param config_suffix Used to differentiate test names based configuration + * (in this case whether the ifft_flag is set or not.) + + * @param comparison_interface Macro name used to compare reference and fut + * outputs. + * + * @param output_tpe The type of variable contained in the output + * (e.g. float32_t, uint32_t, etc). + * + * @param ifft_flag Determines whether the arm_cfft_instance_xxx is configured + * for an inverse FFT. + */ +#define CFFT_FAMILY_DEFINE_TEST(fn_specifier, \ + type_suffix, \ + config_suffix, /* Delineate between test configs*/ \ + comparison_interface, \ + output_type, \ + ifft_flag) \ + JTEST_DEFINE_TEST(CFFT_TEST_NAME(fn_specifier, type_suffix, \ + config_suffix), \ + CFFT_FN_NAME(fn_specifier, type_suffix)) \ + { \ + arm_cfft_##fn_specifier##_instance_##type_suffix cfft_inst_fut; \ + arm_cfft_##fn_specifier##_instance_##type_suffix cfft_inst_ref; \ + \ + TEMPLATE_DO_ARR_DESC( \ + fftlen_idx, uint16_t, fftlen, transform_##fn_specifier##_fftlens \ + , \ + \ + /* Initialize the cfft instance */ \ + arm_cfft_##fn_specifier##_init_##type_suffix( \ + &cfft_inst_fut, fftlen, ifft_flag, (uint8_t)1); \ + arm_cfft_##fn_specifier##_init_##type_suffix( \ + &cfft_inst_ref, fftlen, ifft_flag, (uint8_t)1); \ + \ + TRANSFORM_PREPARE_INPLACE_INPUTS( \ + transform_fft_##type_suffix##_inputs, \ + fftlen * \ + sizeof(TYPE_FROM_ABBREV(type_suffix)) * \ + 2 /*complex_inputs*/); \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Inverse-transform flag: %d\n", \ + (int)fftlen, \ + (int)ifft_flag); \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES( \ + arm_cfft_##fn_specifier##_##type_suffix( \ + &cfft_inst_fut, \ + (void*) transform_fft_inplace_input_fut)); \ + \ + ref_cfft_##fn_specifier##_##type_suffix( \ + &cfft_inst_ref, \ + (void *) transform_fft_inplace_input_ref); \ + \ + /* Test correctness */ \ + comparison_interface( \ + fftlen, \ + output_type)); \ + \ + return JTEST_TEST_PASSED; \ + } + +/** + * Bulk wrapper for all tests instantiated using #CFFT_FAMILY_DEFINE_TEST(). + * + * This macro allows several test definitions to share the same config_suffix + * and ifft_flag settings. + */ +#define CFFT_FAMILY_DEFINE_ALL_TESTS(config_suffix, ifft_flag) \ + /* Radix2 tests*/ \ + CFFT_FAMILY_DEFINE_TEST(radix2, q31, config_suffix, \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \ + TYPE_FROM_ABBREV(q31), \ + ifft_flag); \ + CFFT_FAMILY_DEFINE_TEST(radix2, q15, config_suffix, \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \ + TYPE_FROM_ABBREV(q15), \ + ifft_flag); \ + /* Radix4 tests*/ \ + CFFT_FAMILY_DEFINE_TEST(radix4, q31, config_suffix, \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \ + TYPE_FROM_ABBREV(q31), \ + ifft_flag); \ + CFFT_FAMILY_DEFINE_TEST(radix4, q15, config_suffix, \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \ + TYPE_FROM_ABBREV(q15), \ + ifft_flag) + /* /\* Mag tests*\/ \ */ + /* CFFT_FAMILY_DEFINE_TEST(mag, f32, config_suffix, \ */ + /* TRANSFORM_SNR_COMPARE_INTERFACE, \ */ + /* TYPE_FROM_ABBREV(f32), \ */ + /* ifft_flag); \ */ + /* CFFT_FAMILY_DEFINE_TEST(mag, q31, config_suffix, \ */ + /* TRANSFORM_SNR_COMPARE_INTERFACE, \ */ + /* TYPE_FROM_ABBREV(q31), \ */ + /* ifft_flag); \ */ + /* CFFT_FAMILY_DEFINE_TEST(mag, q15, config_suffix, \ */ + /* TRANSFORM_SNR_COMPARE_INTERFACE, \ */ + /* TYPE_FROM_ABBREV(q15), \ */ + /* ifft_flag) */ + +CFFT_FAMILY_DEFINE_ALL_TESTS(forward, 0U); +CFFT_FAMILY_DEFINE_ALL_TESTS(inverse, 1U); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cfft_family_tests) +{ + /* Forward FFT tests */ + JTEST_TEST_CALL(arm_cfft_radix2_q31_forward_test); + JTEST_TEST_CALL(arm_cfft_radix2_q15_forward_test); + JTEST_TEST_CALL(arm_cfft_radix4_q31_forward_test); + JTEST_TEST_CALL(arm_cfft_radix4_q15_forward_test); + + /* Inverse FFT Tests */ + JTEST_TEST_CALL(arm_cfft_radix2_q31_inverse_test); + JTEST_TEST_CALL(arm_cfft_radix2_q15_inverse_test); + JTEST_TEST_CALL(arm_cfft_radix4_q31_inverse_test); + JTEST_TEST_CALL(arm_cfft_radix4_q15_inverse_test); + + /* Magnitude tests removed from the DSP Library. Keeping them here in case + minds are changed. */ + /* JTEST_TEST_CALL(arm_cfft_mag_f32_forward_test); */ + /* JTEST_TEST_CALL(arm_cfft_mag_q31_forward_test); */ + /* JTEST_TEST_CALL(arm_cfft_mag_q15_forward_test); */ + /* JTEST_TEST_CALL(arm_cfft_mag_f32_inverse_test); */ + /* JTEST_TEST_CALL(arm_cfft_mag_q31_inverse_test); */ + /* JTEST_TEST_CALL(arm_cfft_mag_q15_inverse_test); */ +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c new file mode 100644 index 0000000..2a4a98d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c @@ -0,0 +1,144 @@ +#include "jtest.h" +#include "ref.h" +#include "arr_desc.h" +#include "transform_templates.h" +#include "transform_test_data.h" + +#define CFFT_SNR_THRESHOLD 120 + +/* + CFFT function test template. Arguments are: inverse-transform flag, function + suffix (q7/q15/q31/f32) and the output type (q7_t, q15_t, q31_t, float32_t) +*/ +#define CFFT_TEST_BODY(ifft_flag, suffix, output_type) \ + do \ + { \ + /* Go through all arm_cfft_instances */ \ + TEMPLATE_DO_ARR_DESC( \ + cfft_inst_idx, const arm_cfft_instance_##suffix *, cfft_inst_ptr, \ + transform_cfft_##suffix##_structs \ + , \ + \ + TRANSFORM_PREPARE_INPLACE_INPUTS( \ + transform_fft_##suffix##_inputs, \ + cfft_inst_ptr->fftLen * \ + sizeof(output_type) * \ + 2 /*complex_inputs*/); \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Inverse-transform flag: %d\n", \ + (int)cfft_inst_ptr->fftLen, \ + (int)ifft_flag); \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES( \ + arm_cfft_##suffix(cfft_inst_ptr, \ + (void *) transform_fft_inplace_input_fut, \ + ifft_flag, /* IFFT Flag */ \ + 1)); /* Bitreverse flag */ \ + ref_cfft_##suffix(cfft_inst_ptr, \ + (void *) transform_fft_inplace_input_ref, \ + ifft_flag, /* IFFT Flag */ \ + 1); /* Bitreverse flag */ \ + \ + /* Test correctness */ \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE( \ + cfft_inst_ptr->fftLen, \ + output_type)); \ + \ + return JTEST_TEST_PASSED; \ + } while (0) + + +/* + CFFT function with downshift test template. Arguments are: inverse-transform flag, + function suffix (q7/q15/q31/f32) and the output type (q7_t, q15_t, q31_t, float32_t) +*/ +#define CFFT_DOWNSHIFT_INPUT_TEST_BODY(ifft_flag, suffix, output_type) \ + do \ + { \ + /* Go through all arm_cfft_instances */ \ + TEMPLATE_DO_ARR_DESC( \ + cfft_inst_idx, const arm_cfft_instance_##suffix *, cfft_inst_ptr, \ + transform_cfft_##suffix##_structs \ + , \ + \ + TRANSFORM_PREPARE_INPLACE_INPUTS_DOWNSHIFT( \ + transform_fft_##suffix##_inputs, \ + cfft_inst_ptr->fftLen * \ + sizeof(output_type) * \ + 2 /*complex_inputs*/, output_type); \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Inverse-transform flag: %d\n", \ + (int)cfft_inst_ptr->fftLen, \ + (int)ifft_flag); \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES( \ + arm_cfft_##suffix(cfft_inst_ptr, \ + (void *) transform_fft_inplace_input_fut, \ + ifft_flag, /* IFFT Flag */ \ + 1)); /* Bitreverse flag */ \ + ref_cfft_##suffix(cfft_inst_ptr, \ + (void *) transform_fft_inplace_input_ref, \ + ifft_flag, /* IFFT Flag */ \ + 1); /* Bitreverse flag */ \ + \ + /* Test correctness */ \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE( \ + cfft_inst_ptr->fftLen, \ + output_type)); \ + \ + return JTEST_TEST_PASSED; \ + } while (0) + + +/* Test declarations */ +JTEST_DEFINE_TEST(cfft_f32_test, cfft_f32) +{ + CFFT_TEST_BODY((uint8_t) 0, f32, float32_t); +} + +JTEST_DEFINE_TEST(cfft_f32_ifft_test, cfft_f32) +{ + CFFT_TEST_BODY((uint8_t) 1, f32, float32_t); +} + +JTEST_DEFINE_TEST(cfft_q31_test, cfft_q31) +{ + CFFT_TEST_BODY((uint8_t) 0, q31, q31_t); +} + +JTEST_DEFINE_TEST(cfft_q31_ifft_test, cfft_q31) +{ + CFFT_TEST_BODY((uint8_t) 1, q31, q31_t); +} + +JTEST_DEFINE_TEST(cfft_q15_test, cfft_q15) +{ + CFFT_TEST_BODY((uint8_t) 0, q15, q15_t); +} + +JTEST_DEFINE_TEST(cfft_q15_ifft_test, cfft_q15) +{ + CFFT_TEST_BODY((uint8_t) 1, q15, q15_t); +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cfft_tests) +{ + JTEST_TEST_CALL(cfft_f32_test); + JTEST_TEST_CALL(cfft_f32_ifft_test); + + JTEST_TEST_CALL(cfft_q31_test); + JTEST_TEST_CALL(cfft_q31_ifft_test); + + JTEST_TEST_CALL(cfft_q15_test); + JTEST_TEST_CALL(cfft_q15_ifft_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c new file mode 100644 index 0000000..f55e7b3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c @@ -0,0 +1,197 @@ +#include "jtest.h" +#include "ref.h" +#include "arm_math.h" +#include "arr_desc.h" +#include "transform_templates.h" +#include "transform_test_data.h" +#include "type_abbrev.h" +#include /* sqrtf() */ + +/*--------------------------------------------------------------------------------*/ +/* Aliases to aid macro expansion */ +/*--------------------------------------------------------------------------------*/ +#define ref_sqrt_f32(x) sqrtf(x) + +/*--------------------------------------------------------------------------------*/ +/* Test Definitions */ +/*--------------------------------------------------------------------------------*/ + +/* +DCT function test template. Arguments are: function configuration suffix +(q7/q15/q31/f32) and input type (q7_t/q15_t/q31_t/float32_t) +*/ +#define DCT4_DEFINE_TEST(suffix, input_type) \ + JTEST_DEFINE_TEST(arm_dct4_##suffix##_test, arm_dct4_##suffix) \ + { \ + CONCAT(arm_dct4_instance_,suffix) dct4_inst_fut = {0}; \ + CONCAT(arm_rfft_instance_,suffix) rfft_inst_fut = {0}; \ + CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_fut = {0}; \ + \ + CONCAT(arm_dct4_instance_,suffix) dct4_inst_ref = {0}; \ + CONCAT(arm_rfft_instance_,suffix) rfft_inst_ref = {0}; \ + CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_ref = {0}; \ + \ + /* Go through all dct lengths */ \ + TEMPLATE_DO_ARR_DESC( \ + fftlen_idx, uint16_t, fftlen, transform_dct_fftlens \ + , \ + \ + float32_t normalize_f32 = \ + ref_sqrt_f32((2.0f/(float32_t)fftlen)); \ + input_type normalize; \ + \ + /* Calculate normalized DCT4 value for input_type. */ \ + TEST_CONVERT_FLOAT_TO(&normalize_f32, &normalize, \ + 1, input_type); \ + \ + /* Initialize the DCT4, RFFT, and CFFT instances */ \ + arm_dct4_init_##suffix( \ + &dct4_inst_fut, &rfft_inst_fut, &cfft_inst_fut, \ + fftlen, \ + fftlen/2, \ + normalize); \ + \ + arm_dct4_init_##suffix( \ + &dct4_inst_ref, &rfft_inst_ref, &cfft_inst_ref, \ + fftlen, \ + fftlen/2, \ + normalize); \ + \ + memset( transform_fft_input_fut,0, \ + fftlen*sizeof(input_type)); \ + \ + TRANSFORM_PREPARE_INPLACE_INPUTS( \ + transform_fft_##suffix##_inputs, \ + fftlen * sizeof(input_type)); \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n", \ + (int)fftlen); \ + \ + /* Input provided as a scratch buffer. Inplace input is \ + * actual input. Display cycle count and run test*/ \ + JTEST_COUNT_CYCLES( \ + arm_dct4_##suffix( \ + &dct4_inst_fut, \ + (void *) transform_fft_input_fut, \ + (void *) transform_fft_inplace_input_fut)); \ + \ + memset( transform_fft_input_ref,0, \ + fftlen*sizeof(input_type)); \ + \ + /* Input provided as a scratch buffer. Inplace input is */ \ + /* actual input. */ \ + ref_dct4_##suffix( \ + &dct4_inst_ref, \ + (void *) transform_fft_input_ref, \ + (void *) transform_fft_inplace_input_ref); \ + \ + /* Test correctness */ \ + DCT_TRANSFORM_SNR_COMPARE_INTERFACE( \ + fftlen, \ + input_type)); \ + \ + return JTEST_TEST_PASSED; \ + } + +/* + DCT function test template for fixed point data. Arguments are: function + suffix (q7/q15/q31/f32), input type (q7_t/q15_t/q31_t/float32_t) and prefix + (dct_4) +*/ +#define DCT4_FIXED_POINT_DEFINE_TEST(suffix, input_type, prefix) \ + JTEST_DEFINE_TEST(arm_dct4_##suffix##_test, arm_dct4_##suffix) \ + { \ + CONCAT(arm_dct4_instance_,suffix) dct4_inst_fut = {0}; \ + CONCAT(arm_rfft_instance_,suffix) rfft_inst_fut = {0}; \ + CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_fut = {0}; \ + \ + CONCAT(arm_dct4_instance_,suffix) dct4_inst_ref = {0}; \ + CONCAT(arm_rfft_instance_,suffix) rfft_inst_ref = {0}; \ + CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_ref = {0}; \ + \ + TEMPLATE_DO_ARR_DESC( \ + fftlen_idx, uint16_t, fftlen, transform_dct_fftlens \ + , \ + uint32_t i; \ + float32_t normalize_f32 = \ + ref_sqrt_f32((2.0f/(float32_t)fftlen)); \ + input_type normalize; \ + \ + /* Calculate normalized DCT4 value for input_type. */ \ + TEST_CONVERT_FLOAT_TO(&normalize_f32, &normalize, \ + 1, input_type); \ + \ + /* Initialize the DCT4, RFFT, and CFFT instances */ \ + arm_dct4_init_##suffix( \ + &dct4_inst_fut, &rfft_inst_fut, &cfft_inst_fut, \ + fftlen, \ + fftlen/2, \ + normalize); \ + \ + arm_dct4_init_##suffix( \ + &dct4_inst_ref, &rfft_inst_ref, &cfft_inst_ref, \ + fftlen, \ + fftlen/2, \ + normalize); \ + \ + /* Input samples need to be downscaled by 1 bit to \ + * avoid saturations in the Q31 DCT process, \ + * as the conversion from DCT2 to DCT4 involves \ + * one subtraction. \ + */ \ + for(i=0; i < fftlen; i++) \ + { \ + ((input_type*)transform_fft_inplace_input_fut)[i] = \ + prefix##transform_fft_##suffix##_inputs[i] >> 1; \ + ((input_type*)transform_fft_inplace_input_ref)[i] = \ + prefix##transform_fft_##suffix##_inputs[i] >> 1; \ + } \ + \ + memset( transform_fft_input_fut,0, \ + fftlen*sizeof(input_type)); \ + \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n", \ + (int)fftlen); \ + \ + /* Input provided as a scratch buffer. Inplace input is \ + * actual input. */ \ + JTEST_COUNT_CYCLES( \ + arm_dct4_##suffix( \ + &dct4_inst_fut, \ + (void *) transform_fft_input_fut, \ + (void *) transform_fft_inplace_input_fut)); \ + \ + memset( transform_fft_input_ref,0, \ + fftlen*sizeof(input_type)); \ + \ + /* Input provided as a scratch buffer. Inplace input is */ \ + /* actual input. */ \ + ref_dct4_##suffix( \ + &dct4_inst_ref, \ + (void *) transform_fft_input_ref, \ + (void *) transform_fft_inplace_input_ref); \ + \ + /* Test correctness */ \ + DCT_TRANSFORM_SNR_COMPARE_INTERFACE( \ + fftlen, \ + input_type)); \ + \ + return JTEST_TEST_PASSED; \ + } + +DCT4_DEFINE_TEST(f32, float32_t); +DCT4_FIXED_POINT_DEFINE_TEST(q31, q31_t,); +DCT4_FIXED_POINT_DEFINE_TEST(q15, q15_t, dct4_); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(dct4_tests) +{ + JTEST_TEST_CALL(arm_dct4_f32_test); + JTEST_TEST_CALL(arm_dct4_q31_test); + JTEST_TEST_CALL(arm_dct4_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c new file mode 100644 index 0000000..1b4ece2 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c @@ -0,0 +1,75 @@ +#include "jtest.h" +#include "ref.h" +#include "arr_desc.h" +#include "transform_templates.h" +#include "transform_test_data.h" +#include "type_abbrev.h" + +/* +FFT fast function test template. Arguments are: function configuration suffix +(q7/q15/q31/f32) and inverse-transform flag +*/ +#define RFFT_FAST_DEFINE_TEST(config_suffix, ifft_flag) \ + JTEST_DEFINE_TEST(arm_rfft_fast_f32_##config_suffix##_test, \ + arm_fft_f32) \ + { \ + arm_rfft_fast_instance_f32 rfft_inst_fut = {{0}, 0, 0}; \ + arm_rfft_fast_instance_f32 rfft_inst_ref = {{0}, 0, 0}; \ + \ + /* Go through all FFT lengths */ \ + TEMPLATE_DO_ARR_DESC( \ + fftlen_idx, uint16_t, fftlen, transform_rfft_fast_fftlens \ + , \ + \ + /* Initialize the RFFT and CFFT Instances */ \ + arm_rfft_fast_init_f32( \ + &rfft_inst_fut, fftlen); \ + \ + arm_rfft_fast_init_f32( \ + &rfft_inst_ref, fftlen); \ + \ + TRANSFORM_COPY_INPUTS( \ + transform_fft_f32_inputs, \ + fftlen * \ + sizeof(float32_t)); \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Inverse-transform flag: %d\n", \ + (int)fftlen, \ + (int)ifft_flag); \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES( \ + arm_rfft_fast_f32( \ + &rfft_inst_fut, \ + (void *) transform_fft_input_fut, \ + (void *) transform_fft_output_fut, \ + ifft_flag)); \ + \ + ref_rfft_fast_f32( \ + &rfft_inst_ref, \ + (void *) transform_fft_input_ref, \ + (void *) transform_fft_output_ref, \ + ifft_flag); \ + \ + /* Test correctness */ \ + TRANSFORM_SNR_COMPARE_INTERFACE( \ + fftlen, \ + float32_t)); \ + \ + return JTEST_TEST_PASSED; \ + } + +RFFT_FAST_DEFINE_TEST(forward, 0U); +RFFT_FAST_DEFINE_TEST(inverse, 1U); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(rfft_fast_tests) +{ + JTEST_TEST_CALL(arm_rfft_fast_f32_forward_test); + JTEST_TEST_CALL(arm_rfft_fast_f32_inverse_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c new file mode 100644 index 0000000..092525c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c @@ -0,0 +1,94 @@ +#include "jtest.h" +#include "ref.h" +#include "arr_desc.h" +#include "transform_templates.h" +#include "transform_test_data.h" +#include "type_abbrev.h" + +/* + FFT function test template. Arguments are: function suffix (q7/q15/q31/f32) + function configuration suffix (same as function suffix), inverse-transform flag, + input and output type (both q7_t/q15_t/q31_t/float32_t) +*/ +#define RFFT_DEFINE_TEST(suffix, config_suffix, \ + ifft_flag, input_type, output_type) \ + JTEST_DEFINE_TEST(arm_rfft_##suffix##_##config_suffix##_test, \ + arm_rfft_##suffix) \ + { \ + CONCAT(arm_rfft_instance_, suffix) rfft_inst_fut = {0}; \ + CONCAT(arm_rfft_instance_, suffix) rfft_inst_ref = {0}; \ + \ + /* Go through all arm_rfft lengths */ \ + TEMPLATE_DO_ARR_DESC( \ + fftlen_idx, uint16_t, fftlen, transform_rfft_fftlens \ + , \ + \ + /* Initialize the RFFT and CFFT Instances */ \ + arm_rfft_init_##suffix( \ + &rfft_inst_fut, \ + (uint32_t) fftlen, ifft_flag, 1U); \ + \ + arm_rfft_init_##suffix( \ + &rfft_inst_ref, \ + (uint32_t) fftlen, ifft_flag, 1U); \ + \ + if (ifft_flag) \ + { \ + TRANSFORM_PREPARE_INVERSE_INPUTS( \ + transform_fft_##suffix##_inputs, \ + fftlen, input_type, \ + fftlen * \ + sizeof(input_type)); \ + } \ + else \ + { \ + TRANSFORM_COPY_INPUTS( \ + transform_fft_##suffix##_inputs, \ + fftlen * \ + sizeof(input_type)); \ + } \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Inverse-transform flag: %d\n", \ + (int)fftlen, \ + (int)ifft_flag); \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES( \ + arm_rfft_##suffix( \ + &rfft_inst_fut, \ + (void *) transform_fft_input_fut, \ + (void *) transform_fft_output_fut)); \ + \ + ref_rfft_##suffix( \ + &rfft_inst_ref, \ + (void *) transform_fft_input_ref, \ + (void *) transform_fft_output_ref); \ + \ + /* Test correctness */ \ + TRANSFORM_SNR_COMPARE_INTERFACE( \ + fftlen, \ + output_type)); \ + \ + return JTEST_TEST_PASSED; \ + } + +RFFT_DEFINE_TEST(q31, forward, 0U, TYPE_FROM_ABBREV(q31), TYPE_FROM_ABBREV(q31)); +RFFT_DEFINE_TEST(q15, forward, 0U, TYPE_FROM_ABBREV(q15), TYPE_FROM_ABBREV(q15)); +//RFFT_DEFINE_TEST(f32, inverse, 1U, TYPE_FROM_ABBREV(f32), TYPE_FROM_ABBREV(f32)); +RFFT_DEFINE_TEST(q31, inverse, 1U, TYPE_FROM_ABBREV(q31), TYPE_FROM_ABBREV(q31)); +RFFT_DEFINE_TEST(q15, inverse, 1U, TYPE_FROM_ABBREV(q15), TYPE_FROM_ABBREV(q15)); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(rfft_tests) +{ + JTEST_TEST_CALL(arm_rfft_q31_forward_test); + JTEST_TEST_CALL(arm_rfft_q15_forward_test); + //JTEST_TEST_CALL(arm_rfft_f32_inverse_test); + JTEST_TEST_CALL(arm_rfft_q31_inverse_test); + JTEST_TEST_CALL(arm_rfft_q15_inverse_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.c new file mode 100644 index 0000000..93e1e62 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.c @@ -0,0 +1,11 @@ +#include "jtest.h" +#include "transform_tests.h" + +JTEST_DEFINE_GROUP(transform_tests) +{ + JTEST_GROUP_CALL(cfft_tests); + JTEST_GROUP_CALL(cfft_family_tests); + JTEST_GROUP_CALL(rfft_tests); + JTEST_GROUP_CALL(rfft_fast_tests); + JTEST_GROUP_CALL(dct4_tests); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.c new file mode 100644 index 0000000..4a04721 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.c @@ -0,0 +1,3311 @@ +#include "transform_test_data.h" +#include "arm_const_structs.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +float32_t transform_fft_output_fut[TRANSFORM_MAX_FFT_LEN * 2] = {0}; +float32_t transform_fft_output_ref[TRANSFORM_MAX_FFT_LEN * 2] = {0}; +float32_t transform_fft_input_fut[TRANSFORM_MAX_FFT_LEN * 2] = {0}; +float32_t transform_fft_input_ref[TRANSFORM_MAX_FFT_LEN * 2] = {0}; +float32_t transform_fft_output_f32_fut[TRANSFORM_MAX_FFT_LEN * 2] = {0}; +float32_t transform_fft_output_f32_ref[TRANSFORM_MAX_FFT_LEN * 2] = {0}; + +/* Some of the transform function modify their inputs in-place, so that they + * become the outputs. */ +float32_t * transform_fft_inplace_input_fut = transform_fft_output_fut; +float32_t * transform_fft_inplace_input_ref = transform_fft_output_ref; + +q31_t transform_fft_q31_inputs[TRANSFORM_MAX_FFT_LEN * 2] = +{ + 0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB, + 0x41F6F6A, 0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8, + 0x3D060524, 0x93D5E570, 0x97D7791D, 0xFFE0C38C, 0x26749841, + 0xC0A6EE54, 0x218EC386, 0x39FF3726, 0x8DC1F7CA, 0x702F2CF5, + 0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49, 0x3805DE7E, + 0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF, + 0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24, + 0x6CE00F5C, 0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530, + 0x73394127, 0x773FA6F4, 0x9805A980, 0x838DE587, 0x9CF597F4, + 0xA2AD1691, 0xFA81A473, 0x7CDC7D7F, 0x4A5190D0, 0xED895BB9, + 0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516, 0x2501A3E1, + 0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E, + 0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4, + 0x24DB166C, 0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6, + 0x419E0C75, 0x46BE9F38, 0x2432B9B2, 0x758D83E0, 0xDCE12926, + 0x3F57CB74, 0x1F4458E2, 0xF1DD639, 0x83A1FB49, 0x173AFC76, + 0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549, 0x5C314C9, + 0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715, + 0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F, + 0x20BFDEB4, 0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE, + 0x9858E3E1, 0xA36A9C4E, 0x88BD21F9, 0xAACF7A68, 0x773665E5, + 0xCEDFDF66, 0x617A9610, 0x524FC968, 0xC2D086CD, 0x5F008079, + 0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608, 0xA33A2EE5, + 0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5, + 0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4, + 0xB358C0D8, 0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF, + 0x33035831, 0x13D93987, 0xFC542094, 0x845F317E, 0xDDC4BF8B, + 0x1379E50C, 0x5C20193F, 0xFDD58298, 0x9D482B82, 0x4A6BE062, + 0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882, 0xE6F8EA35, + 0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD, + 0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677, + 0xFB2E04F2, 0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8, + 0x1A8C7F28, 0x861E452E, 0x932D3F78, 0x7652D852, 0x73357BBA, + 0xEBBB0A58, 0x62536AFA, 0x3F6B65EF, 0x6DC57B58, 0x9EB798CE, + 0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302, 0xA9FD3E40, + 0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3, + 0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896, + 0x6443A0FE, 0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820, + 0xF18F0810, 0xE1548689, 0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B, + 0xEA0C1BE0, 0xA1B785DB, 0x7086465D, 0x1CC10929, 0x1E1D716E, + 0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4, 0x441F1E8B, + 0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137, + 0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615, + 0x92593380, 0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7, + 0x10E916B6, 0xE3BCFA68, 0x2ACB80BB, 0xE51C5590, 0x994714B5, + 0xF30984EE, 0x59BBE1B4, 0xB4867DBC, 0xB91C706C, 0xBC16C218, + 0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, 0x4B167FD4, + 0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55, + 0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A, + 0x9D2C662A, 0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C, + 0x20306EDB, 0xE381AAE7, 0xA55DA748, 0x9B8B617B, 0x3E036FAD, + 0x84E4C4A7, 0xD5A3F517, 0x669BA988, 0x98FDDE8C, 0x67BD85CE, + 0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF, 0x205DB5C, + 0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC, + 0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693, + 0xC42D12C0, 0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC, + 0x8D874532, 0x5F5C9DD0, 0x5D167858, 0x8559FEA2, 0x9D821476, + 0xD9654ED2, 0x594C0DC7, 0x1A87B506, 0x3F693200, 0x7A651AB5, + 0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0, 0xB088C72F, + 0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB, + 0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D, + 0x32581A06, 0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15, + 0xBC79A9BC, 0xB7175917, 0x354E381C, 0x762AADD7, 0xF643DAC1, + 0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4, 0xD7694875, 0x92D30822, + 0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7, 0x58CE268, + 0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1, + 0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB, + 0x8FF5534, 0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7, + 0x419545EB, 0x993F7880, 0xAB246B20, 0x408AABC4, 0xCBF6EA49, + 0xC0894C55, 0x4CAA6398, 0xA47856E9, 0xAF2AE47D, 0x22F55D33, + 0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8, 0x9A77D48, + 0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A, + 0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071, + 0x7F9930D4, 0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A, + 0x144B2C12, 0x98E425C7, 0xBAA4B373, 0x18F0D03C, 0x99462AC0, + 0xD8B4D2EF, 0x72473895, 0xA6BF5435, 0xEDAD53B, 0xE0912FA6, + 0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929, 0xB89962F9, + 0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0, + 0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841, + 0x73A60174, 0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095, + 0x2B370837, 0x83DF6CE3, 0xDD08EEFA, 0x3F52A7C2, 0x191B4785, + 0x60843D82, 0xB0DE11F1, 0x105EA26C, 0x6E1C7AA2, 0x47AADD14, + 0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC, 0x744206A, + 0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9, + 0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F, + 0x2E53E6C1, 0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5, + 0x119725CC, 0x5406D347, 0x1B6FFAF1, 0xECCF71F1, 0x981117F2, + 0x7167CA76, 0x74F4B880, 0x77A55F47, 0x59EADB62, 0x4A331D95, + 0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1, 0x60D47AD5, + 0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3, + 0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E, + 0x31109C58, 0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF, + 0xBAF8D31E, 0xA4B31611, 0xED37F331, 0x7A832A22, 0xA22591C7, + 0x722D1F89, 0x3B19CF18, 0x261B8A4D, 0xC3F6F6DB, 0xCF8CED61, + 0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4, 0x3674E663, + 0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD, + 0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91, + 0x4BF0C248, 0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26, + 0x6C3B7B71, 0xD744B3ED, 0xFA25D2F6, 0x4CDE642D, 0xD65B8142, + 0xA6F9207F, 0xE7A207BE, 0xDB506684, 0x44DA4780, 0x9175EA0C, + 0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2, 0x5423D9C8, + 0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1, + 0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5, + 0x1672BA91, 0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4, + 0x32AFD40C, 0x99A5FB3B, 0xDD1D73A3, 0xA342CB3E, 0xA78445F5, + 0x53979C3B, 0x427D7943, 0x5221B58C, 0xA6CE9A5E, 0xFB50ECA4, + 0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04, 0xFBB65E0C, + 0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920, + 0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641, + 0x4D6B1760, 0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF, + 0x4E5F9493, 0x4C215DA5, 0x33A052B, 0x1A4D80C2, 0x40AEEBCA, + 0x390D106B, 0xE9E8E018, 0x5AF3D6CF, 0xE35E1D4, 0xC4FB1C6, + 0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6, 0x2227567D, + 0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6, + 0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1, + 0xC9D06CBC, 0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47, + 0x9D4804EA, 0x57DD9E67, 0xF89C7895, 0xF5336111, 0x25C122C8, + 0x62742114, 0xCFBF6D26, 0xBF9F6482, 0xE6F02CD9, 0x11083202, + 0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1, 0x3BF4DC25, + 0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129, + 0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA, + 0x31C5A0AF, 0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98, + 0x82C34882, 0x5D041F11, 0x8C613C57, 0xD398CFD1, 0x426F38AD, + 0x5599AB1D, 0xFAFA078D, 0xAB25B413, 0xD94B32CF, 0xB288FE38, + 0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D, 0x2174EBBE, + 0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6, + 0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02, + 0xC20D47A4, 0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4, + 0xC58612F4, 0xA2827F6F, 0xC49DCDBA, 0x679B7362, 0x4E495845, + 0xCFD2F0D1, 0x395E76A0, 0x375A655E, 0x92E2058F, 0x73F9F0CA, + 0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B, 0xA219E2E8, + 0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF, + 0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40, + 0x157F6DDF, 0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58, + 0xB2945F75, 0x4FA23A0E, 0x836EB8C0, 0xB3B18FD, 0x86114337, + 0x24668ACB, 0x99BB82F0, 0x924C8A47, 0xBA959701, 0x81155ABF, + 0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7, 0x7FC2802D, + 0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719, + 0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD, + 0xEBA775AE, 0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D, + 0xBBD34AB7, 0x2F85B12A, 0x16C5C2AD, 0x3990985D, 0x88DF3351, + 0x82811AA5, 0x6D351F41, 0x4066A69D, 0x86B660BF, 0x6EDB4768, + 0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687, 0x947CC9C9, + 0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB, + 0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B, + 0xB7629C93, 0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66, + 0xEC71B78C, 0xEAF4BB3A, 0x7C16225E, 0x668F337, 0xCBEE1608, + 0x6D5B5552, 0x345DC590, 0x681209CC, 0x7B24A819, 0xD08A1416, + 0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678, 0x20EECA0, + 0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D, + 0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960, + 0x7CDF59F3, 0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110, + 0xB8FCF3E3, 0xDEA059B2, 0x8229B6EA, 0x316486F6, 0x43919185, + 0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9, 0x5CD41244, 0x2C9F0A7B, + 0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0, 0xF105C20D, + 0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763, + 0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53, + 0x2D2A85F6, 0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B, + 0x9FC5AC5F, 0x11AE5DD7, 0xA0B9A5A9, 0xFC648AF4, 0x740009AC, + 0xED0E0321, 0xB8E6A61, 0x8910C544, 0xC74F26C8, 0x9525CCF3, + 0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D, 0xE1976DD4, + 0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1, + 0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB, + 0xF5288568, 0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A, + 0x1BC03B9, 0xB6BC3061, 0xBF30596E, 0xBE2AD27B, 0x8AC04220, + 0x641979A3, 0x9ECCBB89, 0xA144FBC1, 0x4E8FAE26, 0x8C5A9D90, + 0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D, 0xCEE81CDF, + 0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA, + 0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38, + 0x2E77F2D, 0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017, + 0x2D6B69A7, 0xFEDB63F9, 0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8, + 0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6, 0xED193443, 0x7615EF1B, + 0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022, 0x556E825C, + 0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF, + 0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC, + 0x1E6A1101, 0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599, + 0x54EB4809, 0x7839BE6D, 0xD50017DD, 0x39B1A0E1, 0x288D52D3, + 0x2D52668C, 0x20D22A68, 0x4E1207D1, 0x3FCC0EFE, 0x47F3FE64, + 0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8, 0x6BEAA655, + 0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9, + 0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B, + 0x4DCD4EDB, 0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6, + 0x502F41B0, 0x3616D3F1, 0x2E5B8E31, 0x2026EB19, 0x57E783D7, + 0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48, + 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED, + 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F, + 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB, + 0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94, + 0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11, + 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x73D63FED, 0xE36E9F5E, + 0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1, 0xCD476E86, + 0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7, + 0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78, + 0xCC4BE4F6, 0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2, + 0x55A8F5EC, 0xE81A9A75, 0x30A67E1B, 0x4A4A7D0C, 0x20F7F993, + 0x1891805, 0x738976AD, 0xD426E7D6, 0x3C5CEEBF, 0x4499187F, + 0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, 0x421BCF29, + 0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE, + 0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46, + 0x5D146234, 0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA, + 0xB65530CC, 0x2DFAC48C, 0x1663D16F, 0x59B80AA, 0x950274EA, + 0x92532D4A, 0x3CEF802D, 0x492FBDA5, 0xA63A2574, 0xEF8005C2, + 0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646, 0xD2598516, + 0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75, + 0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F, 0xECDD35CC, + 0xDDC1EE0E, 0xC4848865, 0x925826BD, 0x4078BE39, 0x68A8561A, + 0x323045DC, 0xA933B37F, 0xBA2AEE2E, 0x4F24F65D, 0x349EE246, + 0xF97B9D0E, 0x46DC5759, 0x4529F425, 0x80D17B42, 0x8E16F709, + 0x1B42206A, 0x4934A526, 0x391BB6DE, 0xB52EF45C, 0x26C30290, + 0xCBA23CAA, 0xA501A8C3, 0xD922C4F8, 0xE8824E53, 0x6F4255DC, + 0x5960B544, 0x58BC69D6, 0xCA936323, 0xFDDF053C, 0xC2E002D6, + 0x7D750755, 0x8A3F9CD1, 0x35F8F6F8, 0xFB7BD154, 0x65CFF94F, + 0x390A58DD, 0xD97C4093, 0x501CA2A3, 0x8EA5DEBC, 0xCA93461F, + 0xE02D984C, 0x126F8517, 0x39FDD887, 0x46241AE9, 0x777E854D, + 0xE2B36349, 0x58E3FA9F, 0x971DEF1E, 0x8E156228, 0xC0E14E9, + 0xA9A01BE6, 0xB318C990, 0x971680D6, 0xA1F359CE, 0x487E23F4, + 0x7DE465B0, 0x4E4C905E, 0x2A652959, 0x116FF167, 0x5C74AAB9, + 0x4FEFC920, 0x28DF4EB8, 0x29EBF45A, 0x1E350CF6, 0x7134F224, + 0x22CCF1B6, 0x3890ACCD, 0x9BC304F0, 0x7A37B14E, 0xF3724F9C, + 0xDAC493BE, 0x504692EB, 0x82A56D75, 0x42BC73F0, 0xADA92177, + 0x2D9D9FD2, 0x41D874F, 0xEFCFD8FE, 0x8E83A5A2, 0xB84AF0DA, + 0x65F9B035, 0x6DF4EEE0, 0x7D403714, 0x1CCB8B3A, 0x25B30F14, + 0x5384B044, 0xD21FB429, 0x2C407A2, 0x88622917, 0x92D49C25, + 0x845AA406, 0x532D7675, 0xC0B7713D, 0x30E6933B, 0xD270DE3B, + 0x78771A87, 0x1949A28, 0xAEC00040, 0x10A092F4, 0xBD9D5066, + 0xDE166CB7, 0xE8ECE4D3, 0x867417C9, 0xCF0657E4, 0xD7D550F7, + 0xCD472B6D, 0x8CD0F002, 0xD7D47B7C, 0xA2E5475F, 0x2B66B40, + 0x397A7C9F, 0x6C4BC024, 0x9FDA402, 0xD981917E, 0xA3A6C8E, + 0xC9A42042, 0xCF0D1D5B, 0x1A96C11B, 0x9271030B, 0x4BD5D13C, + 0xCDA08C03, 0x1E4B3256, 0xDBB263E, 0x94B1E758, 0x5CF0232F, + 0xC76F252E, 0x27FF7F55, 0xA55DC287, 0x72886B75, 0x38AA73C2, + 0xA5759CFB, 0xF0A75C8C, 0x7059CBE3, 0x6519FBE2, 0x8C3B4162, + 0x5A19A4DE, 0x9D93E753, 0xA9EDF8B5, 0xD68126CD, 0xEA6A7399, + 0xA73005B4, 0x45BC5168, 0xABD166BA, 0x4D0CC0DF, 0xE1376FF9, + 0x393FB309, 0xE995744E, 0xD5EF71BE, 0x66C2BF35, 0x88D62A85, + 0x14121E08, 0x7006CE98, 0x7F0A7076, 0x7DB9C751, 0xDC7056CD, + 0xC1517CD, 0x65BCE88, 0x1B0F1E71, 0x54C2DA11, 0x101BFDD8, + 0x28096AAD, 0xC365859F, 0xACE13396, 0x7CB432BC, 0xB19EA011, + 0xAD9BC7D2, 0x3AF387B1, 0xCCE30470, 0x5335FC46, 0x40D13C16, + 0xD548B4CC, 0xC476A7BD, 0x66BC0663, 0xB7C6960F, 0x12D1E821, + 0x9A536C48, 0x42641630, 0x740C9A48, 0xF61664E8, 0x3B11E69A, + 0xBD79E1F1, 0x3F930B7D, 0xD98B085D, 0x2151962F, 0xD4D7F80E, + 0x88975123, 0x5302989, 0x12F5CA2B, 0x37C29573, 0xD1D2A3A6, + 0x46DA55DA, 0x2EC8C098, 0x802A42DF, 0xD07A11E5, 0xD5BF4B16, + 0x171BCB96, 0xB5843001, 0x57BDCAA7, 0xDDD36F33, 0x633D0AA0, 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0xAC18A45C, 0x74DE3ADE, 0xD0E6FAD4, 0xE10C242E, + 0x797DF7BA, 0x812CD7B8, 0xED45B681, 0x8F6CCDE8, 0xC2376DFF, + 0xCABE35D6, 0xD450395B, 0x13493CE3, 0x870E1BF5, 0x7B0BF341, + 0xEBD572F2, 0xAE22B3F1, 0x7ED22DF8, 0xEFE826ED, 0xF147F4BD, + 0xA12DA6F2, 0xF3871967, 0xE4423B70, 0x298472D9, 0x45E03E3D, + 0x2BE705AC, 0x41E3AE6C, 0xA29DF92C, 0x54B33739, 0x8EA8F7A9, + 0xDEFF7BC9, 0x77D06961, 0x71981BA1, 0xBA5A5647, 0x4A8E0E2E, + 0x9F519F5D, 0x31BBA940, 0x3D3A0532, 0x7090F0AD, 0x8B47D658, + 0x8D198BAF, 0x9ED929B6, 0x323BB81, 0x97210404, 0x7B8790DA, + 0xD8438C25, 0xDFBB1C93, 0x2C3F415B, 0x14738C42, 0xB46C2C7A, + 0xA3627CAB, 0xFC540D08, 0xE8227979, 0x672B87FE, 0xB257C949, + 0x9C2B31FF, 0x97AAACA8, 0xC662B448, 0x5BFEFC7C, 0xC2FDEDDE, + 0xAD306CED, 0x639A2576, 0x9ECC1378, 0xA72D71B3, 0x94E11CDB, + 0x8BF14832, 0x945C1728, 0x49AE595B, 0x526DD500, 0x40A7D344, + 0x8EB1DA34, 0x731E17C5, 0xA7CF41A4, 0xCB068104, 0xC842B8E, + 0x7F5733E1, 0xAC9CB3B, 0x2E3F58C0, 0xFD8BC4F, 0xFFBCBBAA, + 0x620248F9, 0x27AC344D, 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0x75F665AD, 0x6ABADB10, + 0xAB43129, 0x26B7A5B8, 0xA321DDBD, 0x467AD732, 0x153A1AE, + 0xAD6B1842, 0xBE19B6BE, 0xC1E22C82, 0x73372EA5, 0xF9EF4AD7, + 0x24C81977, 0xD8451807, 0xCD10ADC8, 0x8FBD95E2, 0xE0789969, + 0xC77A80F2, 0xF1165BCE, 0x3488C653, 0x16F3E378, 0x8D71B29A, + 0x628EC98A, 0x40963234, 0xF918E028, 0x9A584D33, 0xC174E2FE, + 0x417C5145, 0x1C751175, 0xB21E0C12, 0x30218ECC, 0x9D7731BD, + 0xA07DBA0F, 0xE7504D39, 0x3E37F16B, 0xD3BAB050, 0x6F3DE64, + 0x1998A7BA, 0xA61A6D07, 0x424FBED7, 0xCD6B3236, 0x68E71248, + 0x58CC3DFB, 0x584FA4F5, 0xFFE8E2BD, 0x9F0E3D75, 0x788DD779, + 0x978ED891, 0x7E1BFFC8, 0xB812A1C9, 0x5CCC1A32, 0xF1A47219, + 0xD6BA6E71, 0xAFA86EB5, 0x28D128E2, 0x9EDD53B, 0x9AAB7E9C, + 0x493B76F2, 0x31C5C89, 0xCE5FC3B6, 0x974CC3F5, 0xCBBD90FB, + 0x61DE988E, 0x99B927CB, 0x972EFCCD, 0x2719AD6, 0xE06E4B29, + 0x48215B1, 0x37EDE8E4, 0xABF9F87F, 0x8BC1C626, 0x5B19EC05, + 0x212A2AE1, 0x28446975, 0x20D04126, 0xFC453267, 0x967D9524, + 0xDF1CDF8, 0xFB17DCA3, 0x11E68AC6, 0x3AD7D667, 0xD133EF43, + 0x5EC41DA3, 0x587AA639, 0x17ADAE3, 0x816DF77A, 0x37D0726A, + 0x49DC33D9, 0x6C9737E, 0xA6A2F950, 0xEC5F352C, 0x50D1E06D, + 0xC10009A6, 0x2F70F8BE, 0x382269B1, 0x4C29E7CB, 0xBD474FF3, + 0xD19A4F6, 0xC3CCE458, 0xE09B348, 0xD15A0DC5, 0x1C10D20E, + 0x4AFDED15, 0x3C109DC1, 0xD8C117F5, 0xB501DDF5, 0x39C92B5F, + 0xE76FCA13, 0x76DBAA1B, 0xB0730EBF, 0x67DD1FBC, 0xD8B87AB6, + 0xA826225B, 0xAB2F7089, 0x499FA36D, 0xF26455B, 0xDC79F8EF, + 0x987E765E, 0xA13E60C7, 0x500C7803, 0x492C871D, 0x970DE4EE, + 0xD1423DC1, 0xB66048A3, 0x804895AB, 0xC079A15F, 0x5E6FD682, + 0xE936476E, 0x8DECE38F, 0x76A011D, 0x53575B91, 0xB263D36A, + 0x8F2624C1, 0x26B34937, 0x75A7EC2F, 0xE33ED24, 0xBF1BE7C7, + 0x8D6BA785, 0x1D9FE802, 0xB8F4EC20, 0xD5C714B2, 0xC1326D06, + 0xFCA78B3F, 0xC0065015, 0xA4B9F286, 0x53F92A8B, 0xF4B02DBB, + 0xEC47E64C, 0xA29FFB12, 0xBA94FFB2, 0xB6980EB2, 0x7415C83F, + 0x93F91A24, 0x4C6F7615, 0x34431174, 0xC7D63B4, 0xB1599158, + 0xA3A01FCE, 0xBD477764, 0x6B16EC41, 0x772D8BF5, 0x90F0A785, + 0x8F72672C, 0x7AD22CDC, 0x70824998, 0x1BED16D5, 0x596E84FF, + 0x48B5B4F4, 0xB20D0B81, 0xF00F7AFF, 0x80F618DA, 0xD10AFE11, + 0xA8EA3109, 0x91BA5E43, 0x31345A01, 0xEB0EF0F8, 0xCC6E7FB5, + 0x3348AE52, 0xEBB124D9, 0x447E58B1, 0xF2A3D592, 0x7F3EE5D8, + 0xD3D7B836, 0x9C98DCD4, 0x27F0B7A0, 0xA9655FD9, 0xAB48E5F8, + 0x7F996D8E, 0xAC13B08B, 0x2530AC6D, 0xAA542552, 0xD4E6B42A, + 0x6432AA64, 0xEAC84F76, 0x41D5F959, 0xCDE91DDF, 0xA0AA485A, + 0x6453698, 0x277C18A4, 0x161A497, 0x66FECAE2, 0x1B64683, + 0x948DD228, 0x1F3C5950, 0xFFC271FB, 0x15C4DF12, 0x7C78252B, + 0x9D4EBB89, 0xE6FA1D49, 0x6B032100, 0xB65DD3CC, 0x106BC9B5, + 0xE0223D45, 0xF7779B03, 0x4B0EA0C2, 0x3CB5AAF2, 0x9A458E5F, + 0x524090ED, 0x3BB1F18F, 0xB4DD065E, 0xA8F13E4F, 0xC4949ABB, + 0xD8142D31, 0x99069DE6, 0x989D2A16, 0xC72D929, 0xA2AC5754, + 0x7E29B714, 0x6E25C15F, 0xE8777078, 0x467DDCEA, 0xF94B2ACB, + 0xDF429476, 0x69AE316, 0x363C664D, 0x85D6AA1E, 0xD727E39E, + 0x5AF440A3, 0x2F0BB16D, 0x461D52D, 0x610559B6, 0xC28066D9, + 0x3C13AE61, 0xA965B865, 0x2BCE3D4A, 0x361C4848, 0x46B94657, + 0xF2AE634D, 0xD7FD4B8B, 0x70C175D8, 0x33128DF, 0xB9718A3B, + 0x8EF80C0F, 0xAB12E738, 0x124B8055, 0x43448325, 0x9F05E427, + 0xA0A9F843, 0x57A9A3FA, 0x492EEA32, 0xE73D2B18, 0xF3113C2C, + 0x2BA9B42D, 0xFF0B320, 0x3A18CD71, 0x59804367, 0xC37F9B87, + 0xB8A990, 0xAFE9F267, 0x1892892B, 0x25B9C66D, 0x52D4056E, + 0xCC1508CA, 0xAD213DB2, 0x8B43F743, 0xAA9705AD, 0x9BC756A2, + 0x43F42526, 0x596FEE87, 0x2B8AFF32, 0x46DEDB48, 0xBF06317C, + 0x876D4CF2, 0x16951456, 0x2B051AFD, 0xFD093E9D, 0x2F113180, + 0x77BFC4C0, 0x29200C52, 0x182D384E, 0x54AE29E0, 0xF90961E8, + 0x6072B8F8, 0x3D346F4E, 0x9AA5DBA4, 0xE5E22EC6, 0x392170DA, + 0x40939B9B, 0x65B89151, 0xC54AB94, 0xAD7280BC, 0xA3D4395E, + 0x3B5754D2, 0x9E77A6A2, 0x9A737F56, 0x9B2D432D, 0x8FDDA7E7, + 0x5958516E, 0x7F52CD74, 0xC1761A50, 0x2B80C01F, 0x5AA99F54, + 0x36FAA395, 0x5DB4B3AD, 0x82024C73, 0x988CEFE0, 0xB44498C0, + 0xF9561A4, 0x280470E6, 0x6966F3A0, 0x47E374F4, 0xF00F4CFF, + 0xBC5C4DB2, 0xE287924F, 0x1ED57369, 0x484FE06D, 0xE92E6564, + 0x7429DAD2, 0x1473AF49, 0x9619E0CD, 0xE6EC2B63, 0xF7A983B5, + 0xEC43C28F, 0x4C98EBE7, 0xA61FDF89, 0xA867E5ED, 0x1088A7C, + 0xCF1CEAE8, 0x223AA207, 0x686F4F7B, 0xEBB013E1, 0xDDC01886, + 0x77478D4E, 0x2FFCEAEB, 0xFCA58846, 0x1208668E, 0x32F8252, + 0x65C9F3ED, 0xC7584B2F, 0xF3EB26B2, 0x90890270, 0x5D97ED04, + 0xF5B5B18A, 0xCF415DF9, 0x4CF4683F, 0xE2E3F29F, 0x850E4BEF, + 0xDBABF6E2, 0xBD183286, 0x2F36215C, 0xD8CA1DD3, 0x4309CC6F, + 0x9FA52446, 0xBD94348E, 0x8693D9B6, 0x61E880C2, 0xA1851D5E, + 0xAAB94F80, 0xF8919C00, 0x74D82ECA, 0x4466A1B6, 0xA0A98E8C, + 0x95B6D1D, 0xE5393A4C, 0x5A40CFFB, 0x67013370, 0x571B0FDA, + 0x9E7E805C, 0x15E32653, 0x2CFE7902, 0xA02E0906, 0xA8883783, + 0x7A68B719, 0x3402833A, 0x68BFD324, 0xE0B43DA3, 0xF9DB0F, + 0xC9510610, 0x690D30B, 0xE79AB417, 0xC917E4C0, 0x7B05CE55, + 0xE116EFDB, 0x69E3B158, 0xF91ED58D, 0x1832D16A, 0x91F4EA17, + 0x3D24C408, 0x76A2C6D0, 0x99B19825, 0x2BF52475, 0xAD49289D, + 0x66238CD7, 0xAC1571F5, 0xA2EABC02, 0x889337AE, 0x3219AFFB, + 0x104B8779, 0x810488A8, 0xAC35416A, 0x2C6DEF85, 0x2ED109F5, + 0xCC8C6732, 0x97CD8E90, 0x339F3E81, 0x91486206, 0x2708D41D, + 0x1F2B19A7, 0x51A60303, 0x5E90E440, 0xB63092C8, 0xF1031823, + 0x971A06, 0xB624F6A2, 0x58AC0181, 0xA983D599, 0xA776D877, + 0xB727FE1, 0x55AC01B1, 0x4298EA17, 0x4D6BB9AA, 0x31C55C65, + 0x6A266780, 0x4FD92256, 0x817DB37A, 0x46A14DF1, 0xEC7D9F14, + 0x98D1C1B7, 0x911DF80D, 0xBFBF24E1, 0x9B4DBC6A, 0xE1F71BA4, + 0x9EE5E44A, 0xD1868C4C, 0x6FB45D76, 0x11EC8672, 0x1CED7F0C, + 0x1524A040, 0xA49DE9D3, 0x99FF328A, 0xC392F619, 0x52A856CC, + 0xDB0B0AE6, 0x67F0162E, 0x2C20D410, 0x4E23C4D, 0x828032EA, + 0xC2E7DFFA, 0x908CF524, 0x919F61EE, 0xF001C6F, 0xA81DDF65, + 0x5EC56647, 0x28385ACF, 0xBDD764C0, 0x75C853AB, 0xDF0ADD73, + 0xEEA9C63D, 0x804949F5, 0x658ACD0A, 0xD12F3F50, 0x1FD4F7EE, + 0x7F023D80, 0xD2CB08B5, 0x477EA9A1, 0x872DB719, 0x7B8B6AE9, + 0x84F6AC4, 0x81634EB4, 0xD1A89CF, 0xB3F4F3B9, 0x3A6B024B, + 0xAA2CA2C5, 0x9C902C0C, 0xC40E4135, 0x3C6E612F, 0x11219414, + 0x1F184277, 0x11B6B30C, 0xDD8A6A5A, 0xA0D21C9D, 0x55377022, + 0xD0708FBD, 0x8D761020, 0x54FCFCFC, 0x477801BD, 0xD6919EB8, + 0x9AD29078, 0x36F8D9B8, 0xAE525B8C, 0xCA7ED140, 0x2D8F8B97, + 0xD1B79EAA, 0x2E26FB2A, 0xFB396E32, 0x399129A3, 0x28B55FA1, + 0x2ECB2CF0, 0xDF1CBF7C, 0xDE57A70D, 0x33410B33, 0x7C5759BF, + 0xF534264B, 0x16C8C221, 0x874A3A63, 0xD05808ED, 0x679674BC, + 0x24B060C9, 0x4B162B53, 0xC7D01208, 0xE753DE61, 0xFA9840E4, + 0xA4FEC439, 0x4143E13F, 0x327E9EE8, 0x319D901E, 0xC40FC209, + 0xB1E1FFFC, 0xE737D52B, 0xD074E058, 0xAD8892EE, 0x86B93396, + 0x49C13F4B, 0x60A5721C, 0xD4C4F599, 0x14B38EBB, 0x86BA655, + 0x95F4E0C, 0x4217E99A, 0xD0CA3861, 0xBDD3617B, 0xB0BDBF4D, + 0x99E3389A, 0x8200DCFA, 0xEC22C8AC, 0xBA8DDB32, 0x3F7DDFC8, + 0xC7DDC171, 0x211CF31, 0xCC31A0C7, 0x99A84F32, 0xC9FFD317, + 0x2267733A, 0xFBD05569, 0x306BC05F, 0x6E2685D5, 0x43FBF7D1, + 0x5A2DB2D3, 0xE6491D4B, 0xAD078066, 0x7CAF7AAD, 0x2B1FEBA5, + 0x3418A0EC, 0xC359E9B7, 0xB024E024, 0x58F22A6B, 0x18EEE710, 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0x2CA39696, 0xE460F7D1, 0xCA32CCB3, 0xA6D9D934, + 0xAD01079C, 0x9B07D89C, 0x226CE0A5, 0x60D67762, 0xD35A4B7B, + 0xFF0A698F, 0xDB73BF89, 0xF41FBA9A, 0xCACDF26D, 0xBF594213, + 0xCD4D3E90, 0xD12F3EB8, 0xE689D238, 0x8CD4C0CA, 0xEB3E841E, + 0xA513EF0F, 0x2DF4B65D, 0x90161625, 0x9C02AC36, 0x208F328D, + 0x12BF5D93, 0x7C8C355C, 0x3CDFCA22, 0x29381080, 0x3FF6CA14, + 0x9F269C74, 0x8A48070B, 0x3BDF51BD, 0x85932156, 0xA7B6F9FF, + 0x80554507, 0x43820D97, 0x59B7214A, 0xFC3ECC27, 0xED39DB19, + 0x2B9BDB43, 0xABD4E298, 0xC2C5953E, 0xD3DB0C09, 0x66EC81DA, + 0x7F41EDE1, 0x5146E8D7, 0x49171DF2, 0xB334BF9A, 0x3AADC9E6, + 0x56E12468, 0xA2D4B032, 0x662B1F49, 0x9C448B1F, 0xA219526C, + 0x56D66A27, 0x41609345, 0x8E685EFA, 0x392DA3A4, 0xDE58C26B, + 0x9C779FC9, 0xCA834F65, 0xA1E34DC4, 0xEC5BE6EA, 0x3737B7AB, + 0x2E9B7D0A, 0x929E96B9, 0xE38B0019, 0xC1E4115B, 0xD8141740, + 0x66977F67, 0x7D4CE4B3, 0x245AB554, 0x26F98B88, 0xEC78F24D, + 0xE1F34C1A, 0x5737AD34, 0xC1A19AC6, 0x3291E363, 0x4E824FF3, + 0xAC42BDF3, 0x7C2DACE8, 0x8D5C97F6, 0xD120875, 0xC4E5C39D, + 0xE22AE85D, 0x290FF39D, 0xD495E52A, 0x95414374, 0xD65757A6, + 0x1E7657F9, 0xF5073D56, 0xC2AA7589, 0xC166A0B3, 0xA0DF8CDE, + 0x4057EAE5, 0xBAC4DD2F, 0xB51F621F, 0xA96F90E3, 0x392B5D6F, + 0xC31E9CA1, 0xCCC02FD3, 0x5181074, 0x7BC15C18, 0xCA9232A4, + 0xD1D104E9, 0x5F0C5D3, 0x4947F6D2, 0x3C923E97, 0x6B486C35, + 0x9C8ADA96, 0x175C4D87, 0x39A1A0FE, 0x417F201B, 0xD080E114, + 0x4847B147, 0xFD634E49, 0xBC0BF4CA, 0xECABB1DF, 0x869B0263, + 0xCD797C28, 0xD2A4683, 0xD50F6A0B, 0x2CA40138, 0x8DA4EB55, + 0x5D198E5A, 0xA98DB40D, 0x96CA0E68, 0xA8D92294, 0xC4813E60, + 0x81CD6B09, 0xEBBEBF80, 0x6777688, 0xCDAF6EC5, 0xEB85653E, + 0x3BB780DD, 0x73718A21, 0x70E8A324, 0x654DE06A, 0x2CB2494A, + 0xFC1DA829, 0x64059A2F, 0x61CE9D0D, 0x5BC51CAB, 0xDF7DE6AE, + 0x1596B477, 0xB0F9EA86, 0x9D87D85B, 0x877620A7, 0x586F3AD6, + 0x96AE645E, 0x65E9D5D7, 0xDB69CEB, 0x2753EF35, 0xC226F633, + 0xBD373F9D, 0xF2A0E198, 0x4372EEC3, 0xA66F7010, 0xD30E1D18, + 0x152C0DFB, 0xEB86FC75, 0xC208FE7E, 0xB36625A4, 0xBBE2DE8, + 0xEC49F9C9, 0xCE724FFE, 0x2D509471, 0xCA6C24B6, 0x1BA93DDF, + 0xEABE9550, 0xB512D359, 0x83F76766, 0xC8267976, 0x7E50802B, + 0xE3EC2199, 0xD3269B8E, 0xC515B0CE, 0xB5752537, 0x70474BD, + 0x7F50EBE, 0xF9FC0B38, 0xD899D19C, 0x317AA41D, 0x6B706374, + 0x66479538, 0x560455A3, 0xD770DD85, 0x55BB61BD, 0x6DE6723A, + 0x3F89034B, 0x9C9650BC, 0xE569992C, 0x7B8F4D95, 0x3FB7C516, + 0x7C28C04B, 0xA12DE6B9, 0x8CFC5AFE, 0xA734A25A, 0xCF1483E8, + 0x1AB22339, 0xAA94F43F, 0x16319A1E, 0x2C9AA4D0, 0xE9D2618, + 0x790B699B, 0x3AD9C3A1, 0x55A778DA, 0x6517152F, 0x2139AB74, + 0x12F762CC, 0x4BE02E6F, 0xE69400F7, 0xDC48DCD0, 0x563DB028, + 0x32299125, 0x7C9145A9, 0xFB88067B, 0xF070F6FF, 0x3D9A42FF, + 0xC5D20DC, 0xF96F7EE1, 0xA9C209A3, 0x9A192F36, 0x3E158AD, + 0x1265DF79, 0x2E49E297, 0x99D3A002, 0xE6AFDDCB, 0x3B56751D, + 0xB248A31F, 0xE6BE0FFD, 0xBBAB635E, 0xB383C45C, 0xA9DC9F2D, + 0x735CE03F, 0x69992E32, 0xD1E6A77, 0xE38A7F46, 0xC1E59620, + 0xFAE7F99A, 0xBDFB440C, 0x9F53F99C, 0x224EA340, 0xAB5D1AF0, + 0x35F3126D, 0x99430549, 0x83E12C62, 0x6403957B, 0x7B119103, + 0xC8382BAB, 0x99A85991, 0x9BF370AF, 0xDFA83CAF, 0xDBEC2CC3, + 0x416D8EBA, 0x774E58FF, 0x29C222F, 0x3DE60561, 0xDF038931, + 0x8297C377, 0x9867C08, 0x58ADEAED, 0xD88F0856, 0x6E4C2A39, + 0x2599DF28, 0xD7A6D06A, 0x433B35BE, 0xDAD3175B, 0xC358D423, + 0x84BF4580, 0xE7D3BE65, 0x9EC8CDBA, 0xCE901946, 0xC4B4D088, + 0x98B1245D, 0xFBB0CC10, 0xE8CB9C76, 0xDE665AF2, 0x28E46D8B, + 0xF7012A56, 0xE29F8C07, 0x8BF87AFB, 0x2907C051, 0x820923CB, + 0xC3E95542, 0x6AB5559E, 0x314BD068, 0x1CEB5637, 0xD1D830D, + 0xC442D6C2, 0x5F6074F4, 0x37F08A2A, 0x21F782BE, 0xF378B1AE, + 0xB7FC74DA, 0x4ACB450F, 0x365F3092, 0xFB0C842C, 0x5DD80554, + 0x741C4F79, 0x290716E0, 0x76E56BA9, 0x10006310, 0x42A183C7, + 0x5F1FB962, 0x8DE2BA39, 0x6176B6D9, 0xFC059A44, 0x9907DE39, + 0x71A5EA7B, 0x42309616, 0x1DDE34DD, 0xF0DFA4BF, 0xF69B5E2F, + 0xD145268, 0x49A3E7B, 0x90508840, 0x861DE564, 0x904730CB, + 0xC844CD6F, 0xD5A2CEB6, 0xCE895F0D, 0x73EEE4D6, 0xEB4565CF, + 0x533ED4ED, 0xF4AAB655, 0x591BC278, 0xBD1D929D, 0x80AD7DA6, + 0x527B3C51, 0x40F627DD, 0xDA420FFD, 0xB9A6F685, 0x5F6D9BC2, + 0x4F67DE58, 0xFB5F87F0, 0x47540936, 0xB2083BC8, 0xAD48DD69, + 0x63F7CA5A, 0x28D5372D, 0x61DA54B0, 0x7DA88170, 0xA2DA7B83, + 0xE1D70E32, 0xA3ADEA46, 0x97026868, 0x60FA4303, 0xA4104416, + 0x3DB4A8CC, 0x72F0F53B, 0xFF270297, 0xD5600E97, 0xD7D25D62, + 0x46DBCAC5, 0xFD61775D, 0x93E100DB, 0xBFE0E0C0, 0x8CE51426, + 0x8216C272, 0xE7300A56, 0x5A61C30E, 0xA7667C78, 0xBD23D39B, + 0xDC425756, 0x7AE9A42B, 0x249E8C42, 0xABB91D5C, 0xBD1334D5, + 0x8BCE967D, 0x5CF89EEA, 0xDB125339, 0x225E3C4C, 0xC5DDA12, + 0xA92903F8, 0xF2F29634, 0xD2AB3419, 0x396DAE59, 0xA02C965E, + 0x450B8DEF, 0x1E4911B2, 0x4F94BA94, 0x6802E7C0, 0x779671B7, + 0xC0B06A93, 0x65BF0119, 0x3D672B7F, 0xE7E68CA, 0xF173FBF, + 0x503C50F4, 0x3D8CA779, 0xD9BC10B2, 0xE6B89F78, 0xFC04B6F2, + 0x74B0E1B4, 0x3BB8594A, 0x5866C0E6, 0x125FBE40, 0x21239465, + 0xC00E2791, 0xD7957B76, 0x331D18CA, 0x87D0C340, 0x8D7347DF, + 0x296D2AA1, 0x8EAA71DF, 0x1D477388, 0x4F666705, 0x211D2B0D, + 0xA41C0741, 0xD8F7CEEC, 0x4C6EDC5E, 0xFE5DC02A, 0xAA83AED3, + 0x9AE501A6, 0xFF82168C, 0xDC638114, 0x4C345BA0, 0xDD7E0F1D, + 0x4C072ABD, 0xFF606768, 0x3CE74279, 0x93DED13D, 0xAB7A9752, + 0xAF27666, 0x784EDE4F, 0x7F4BE8A7, 0x9A45141D, 0x69E507FF, + 0x78BAC3AC, 0xDB2A62AC, 0x52561515, 0xA9DFA9A8, 0xCC51778C, + 0x886CC6A, 0x5246AD23, 0x68A7480, 0xBC267A85, 0x1FF771F4, + 0x5199BC1E, 0xF8CCD05A, 0x7BD65764, 0xC61A33FA, 0xC9F24B8E, + 0xBC0B1D9F, 0xE43E103, 0xBE3D7AAF, 0x39154AD2, 0x941C2098, + 0x1C26174D, 0xC63D21F1, 0xFBC6D732, 0x8C43AE71, 0x1495C044, + 0x9483EE96, 0x909A94F0, 0xC1B02D9E, 0xDF9A2114, 0x2F4883E9, + 0x4806958A, 0x209A2722, 0xFE514205, 0xEB85D85F, 0xC25BED82, + 0xEB2CEABE, 0x8B2A2EDA, 0x68641725, 0x10570304, 0xE53EE68B, + 0xC43FB1C1, 0x8F763232, 0x41ECC1D0, 0xE3E44CBD, 0xA1A68EC0, + 0xDAFA770A, 0x6996A5A8, 0x38407C06, 0x4FAD77B4, 0xE30E2912, + 0x47EE2FD, 0x2CDA167F, 0x88F915F1, 0xF3DF6195, 0x530FBEDE, + 0x2CFC1C0C, 0x47B21171, 0xDEC1A586, 0x2031A43A, 0xDAAD77AD, + 0x8BE637E6, 0xA6AC1EBB, 0x6AB9F2A3, 0xBFB5ED6C, 0x15792C44, + 0xFD3AB89D, 0x27A7E24E, 0x3E76999F, 0x77EE2E6A, 0xE505F3B7, + 0x429839A6, 0x6BEE7B15, 0xF61F0084, 0xFC20752C, 0x4BF79989, + 0xC8B4F8E8, 0x46B33427, 0x9F4BA3E8, 0x41B9354D, 0xEED27E23, + 0xA7FC575F, 0x279180C5, 0x141C3A06, 0x2C2FCEF9, 0x4403AA1F, + 0xD4496B6C, 0x25C33091, 0x452C754, 0x80534A0, 0x80842F72, + 0x3DB756B1, 0xEFD010BD, 0x1DE7F9EA, 0x5F9B1769, 0x55D9839F, + 0xD5B11F46, 0x941D69AE, 0x8C4F3D35, 0xE710E268, 0x2DFBC983, + 0x5D417C19, 0x7C2561F9, 0x25415FCF, 0xF331B119, 0x235B632F, + 0x9B1463A9, 0x8249E513, 0xB6F14826, 0x1005E62C, 0x2B1B4F3E, + 0xEF793550, 0xA90F6AA2, 0x77BFECE6, 0xA6E1C13E, 0xBCB6E143, + 0x2496D0ED, 0xF4A8D5F0, 0x29C27A0C, 0x7D231D55, 0xB8526623, + 0xDDDCB82C, 0x2A18B465, 0xB5FD564D, 0xA9647CB5, 0x4300919B, + 0x9FB2B27A, 0xDB25B0D9, 0xBB5D5711, 0xAA747FC4, 0xAA831194, + 0x9603ED14, 0xAF921A0E, 0xFA1447D7, 0x8B766768, 0xE8F1C89E, + 0xB7985D4, 0x6C5C1AEE, 0x2EA66EF3, 0xD176E7D9, 0x228CD940, + 0xD90C84B4, 0x36253A66, 0xADD7AE4F, 0xF25D5CA5, 0xD34F702F, + 0xA535AA29, 0xFCF10FB, 0x3D075696, 0x63EF7EF3, 0x81554091, + 0xC7EEFC78, 0xE0DCDB21, 0x62EFF001, 0x9ACFD7CD, 0xAEBA43ED, + 0x371BA99B, 0x508B7A31, 0xFF447B05, 0xA239F5D2, 0xA5620A57, + 0xA16B995A, 0xC334401E, 0x535F51AB, 0xAEA26D82, 0x81D72269, + 0x3C0BA1D2, 0x80590850, 0x818A26AA, 0xC43E6B02, 0xF72DFB63, + 0xE7AE3F6A, 0xD31AB683, 0xB99D787A, 0x691FFB53, 0x37EA1E35, + 0xC2C9FFF8, 0x2A13F6D4, 0x4CC79564, 0x6DD5F2DE, 0xC53560B, + 0x5A562B6F, 0x3F2C49F1, 0x6953F4CC, 0x8BA12AF2, 0x98A08428, + 0xA1EF80B3, 0xA977E388, 0x1A3DD9D1, 0x687A3424, 0x2759B568, + 0xC626A765, 0x7887651E, 0xFC9005E1, 0xE84376A4, 0x387BCF66, + 0xF7AA4980, 0xBAEE372C, 0xE89CF460, 0xA275FC1A, 0xA5EF8668, + 0x899F85CE, 0x9CB086A3, 0xF16158AC, 0x4C49EBC0, 0xDCE10FAA, + 0x4B46ABDA, 0x56947FA1, 0xAD4E7245, 0x54C23373, 0x8B0B6C4D, + 0x82590F05, 0x5E292D4C, 0x277B63C5, 0x9D51D8CF, 0x86D379EF, + 0x52CBEF63, 0x7A62AF4C, 0xAC1FA33E, 0x25D454AE, 0x1CDA792D, + 0x17434813, 0x759F50A7, 0xEEB0D38A, 0xB30964A6, 0x941230A0, + 0xA464FA3C, 0x9F8685AF, 0xB9A018F4, 0x8080362, 0x2D565F63, + 0xAB60790A, 0x67252A3C, 0x1715B01D, 0x5384E7F3, 0x79299519, + 0xA9786ABE, 0x1107A1FC, 0xE0D9B037, 0x4DD34883, 0xA7D476E3, + 0x5B194AE9, 0x89E50FB1, 0xA9676565, 0xC77CF621, 0x93612BF2, + 0xE027B80, 0x359C7FBF, 0x39B166FB, 0x1F3B28DF, 0x2848DE70, + 0xFFE261DD, 0xB78D413C, 0xE011DD7B, 0x286F752B, 0x74A8D775, + 0x5E540B67, 0xFAF973F, 0xC0035501, 0xB0F16059, 0x1C981017, + 0xD4871112, 0x9745C0BC, 0x6D85B805, 0xA40253E8, 0x2B0D55CD, + 0x8FF7EDC4, 0x47EB4ECB, 0xC41A2F17, 0x41C9702F, 0x8549DEE0, + 0x865FD46C, 0x64A1F181, 0x24E64D11, 0x13337A33, 0xE8CB0924, + 0x8A2DC003, 0x113C04C7, 0x1CA62E13, 0xC360E708, 0x57DE03AB, + 0x4D8F2BB5, 0x2CE2E2A1, 0x2580C90D, 0xBF162A7C, 0xEB1490A8, + 0xBCABC2A7, 0xFBC4C25C, 0xBC83AB6A, 0x25C47DCB, 0x8FE447A9, + 0x2C0F77CF, 0x6D896845, 0x63CEF5AE, 0xB2FF0326, 0x14D71520, + 0xA1C15C8E, 0xE53550FB, 0x676B299D, 0xC20A5C14, 0xDB3EC54, + 0x359733CE, 0x8A619B1E, 0xCDB53E, 0xD285EED5, 0xA6E0181E, + 0xB81AA3EF, 0x41F8E1A2, 0xE3DEDC6D, 0x4F7CBE5B, 0x24006857, + 0xACB9B719, 0x4E725B2D, 0x8536AF54, 0x329509E7, 0x72E7C0A7, + 0xBA97CC78, 0xD822798F, 0x9DFC6780, 0x63E263CA, 0x7B2397A5, + 0xA42C0C0B, 0x1D5EC588, 0x292F1E7C, 0x2BF5A75, 0xFCD8786B, + 0x14EB1952, 0x84031982, 0xA0800A40, 0x629C9211, 0x3B17F481, + 0x50861D9D, 0x8371A304, 0xB3D21511, 0x720E2C6C, 0x5A07F87E, + 0x868F95BD, 0x8617E7B, 0xD7762105, 0x90707C5A, 0x777473F4, + 0x67737DC4, 0xC4154562, 0x1840CEB3, 0x373635EE, 0x4E6D4EBA, + 0x1736A5EC, 0x4D3E335B, 0x59FDB9A1, 0x9162B39A, 0x3F9E1502, + 0xF661B3DA, 0x77BE0255, 0x65EC8603, 0x21FCA0B, 0x55291C5C, + 0x69F57B1, 0x5DE1E0D6, 0xA6296E1D, 0x595A45F8, 0x90B166DF, + 0x61ABB34E, 0xC6D48B5B, 0xB05EF88F, 0x368B0C6E, 0x94C36250, + 0xB435D440, 0xEFB62847, 0x1473E647, 0x9A101218, 0xC7AA11BF, + 0x80C241E3, 0xAF648F26, 0xDF48753D, 0x7073509A, 0xAB52665F, + 0xD1ECCFC0, 0x7BE293F1, 0x396CA014, 0x84336AB9, 0xF9B7E448, + 0x9566C90E, 0x239F7C25, 0x91A452B3, 0x1E9A4F1C, 0xCCE286F6, + 0xF46520D6, 0x2943A671, 0xAAA30DCF, 0x28D190CE, 0x88E3D0C9, + 0x423944F0, 0x81E6712, 0x2714B6B2, 0xF927748, 0x59A5430F, + 0xCBA530A9, 0x91E12A0E, 0x92598CBE, 0xE61058F5, 0x2604B4B, + 0x4CB7C3A7, 0x43B5812F, 0xFD90660, 0xD73DF50D, 0xAD3AE409, + 0xF74D721B, 0xCC2A88D1, 0xCED79510, 0xE64714DD, 0x3BDF0A8A, + 0xC2C7B689, 0x25B387D8, 0x968DA1A2, 0x8EA5D185, 0xF05F03E1, + 0xFDDC5B50, 0x78AECEF, 0xE32FBBA2, 0xD512F0AD, 0x5410D1B5, + 0xDBFD9FFF, 0xC0F2DD4E, 0xF66F8DBA, 0xF5EBA3C8, 0x65F96FE3, + 0xF7C8962D, 0x8E48A78, 0x255BEDC7, 0xE8FD3698, 0xFD1C4903, + 0xFDE9830, 0xCDBCF434, 0x16540D39, 0x418EF731, 0xB2F80637, + 0xDFCC0C9D, 0xB53DC5BC, 0x5A68B10C, 0xC4DCB3DD, 0x8B3778F4, + 0x7788B194, 0xECBD4903, 0xFD390223, 0x79598BFB, 0xBDECB9D9, + 0x29576BE3, 0x220F82A5, 0xDBB262F6, 0x1876EF0, 0xE2D9C444, + 0x32D5ADEF, 0x5F8739ED, 0xAF427122, 0x171E7D7D, 0xA5468BB4, + 0x94451936, 0x51565032, 0x3CE3CD5, 0xF231F54, 0x98614C6E, + 0xCE18455D, 0x958D2BD2, 0xA5934FE0, 0x3543931E, 0x77D9C2FB, + 0x3D3ED736, 0x6762E077, 0xF1B052A, 0x88AF353B, 0xB2A38925, + 0x8C919686, 0x715EEAAC, 0x34BA46DD, 0xEB486F1C, 0xDF58D7CA, + 0x90B97BE6, 0x37335293, 0x499414CC, 0x7F725BAF, 0x5ABEBF8, + 0xE9344F69, 0x1C110FD, 0xA937AD4C, 0xA7CDD9C0, 0x750FD5FE, + 0x7A7B6D40, 0x41EA948A, 0xA10EE17C, 0x7689C967, 0x9F411C02, + 0x6C40C3FD, 0xA6FFC648, 0xC6D6F914, 0xA100AF92, 0x4CD97ED5, + 0x17D9CCBF, 0x915833F, 0x788D78C0, 0xC81903A3, 0x6DE5BAF0, + 0x3E4D6DCC, 0x98415810, 0xEC23B7AD, 0x822471B0, 0xD2CF5D5A, + 0xA1BACAD5, 0x40843135, 0x430135A, 0xA7655BAD, 0x7A2472BE, + 0xCC3D44CC, 0xD1BC9E10, 0x7C215C92, 0x717FA7DD, 0x7EF7D128, + 0x1BC85798, 0x7C6E19CA, 0xE3FAB7E4, 0xBC884D38, 0x3E220CA, + 0xE7AE4D8, 0xC8EDD021, 0xF3F05D3E, 0xDE302EB8, 0x40CEFF27, + 0x56C0550A, 0x96162C92, 0xC004EA48, 0xE0C29A65, 0x496AE22B, + 0xC7468E6F, 0x8E31BD1F, 0xA53763CF, 0x166CC258, 0x1A2B9CC4, + 0xDBBADE7B, 0xF8D21AC9, 0xB21CA593, 0xB92F0DEE, 0x9A4391F, + 0xCDB4D373, 0xB687B3F5, 0x877BF0A0, 0xFD7395DD, 0x1C56AA87, + 0xCA146BB9, 0x21A2314B, 0x8207A2AC, 0xAA874DC0, 0x4F404E64, + 0xB69FDE48, 0x324FD456, 0x45F19CF, 0xFC7E6D0E, 0xC8A01C04, + 0x76C63378, 0xC526F7B3, 0xFDCD2EEF, 0xFFB2F9B9, 0x2DDE75AF, + 0x5ADF2F86, 0xC9AC84D3, 0x70FF53A0, 0x3FB077C, 0xC2795B30, + 0xF5438170, 0x557D7080, 0xB784684E, 0xCD089E1D, 0x332B71B0, + 0x493C3C2A, 0x1D1DED89, 0x8240E170, 0xA7D17522, 0x48C542AD, + 0xCB357D8F, 0x21E37C1, 0x3B000B34, 0xAAAE4818, 0xCD1EB4B3, + 0x1736CA0E, 0xDDF8EA2B, 0x76E21C4C, 0x6EE99A3C, 0x27F71B20, + 0xF6AE929C, 0x3C9CAF6C, 0x5CA7DA97, 0x8EF033C5, 0x8C7EC36B, + 0x3CB1CFAD, 0x1C5ABBB7, 0xDEF7A78C, 0x9CBC4A73, 0xB3871393, + 0x8C61DF59, 0x54DF941C, 0xCDD23FE8, 0x758EAD7E, 0x49BE795B, + 0xC960C6B, 0xE9B76479, 0xC88843F7, 0x82DC3137, 0xEDEE1A1E, + 0xC6568A7D, 0x42F7F484, 0xA6115655, 0x494779B5, 0xD95FE16A, + 0xB2AB15F4, 0x64C185B3, 0x9A46066E, 0x8BAE077E, 0xBAAE323F, + 0x79A965C6, 0x764B71F0, 0x3654F6D3, 0x96B4B2AB, 0x15C2B523, + 0x720AF416, 0xE6D0F423, 0xFAE44868, 0x6E776BC2, 0x264D41A8, + 0x3FE4BEE, 0x1598B97B, 0x15A70419, 0xA13CD124, 0x751A09E2, + 0xF7F7C12B, 0x718AC211, 0x11D03CD1, 0x2F9247BE, 0x77C210E1, + 0xA2268AAB, 0x2E99F0DD, 0x949D5CC5, 0xA8A309F2, 0x749EC6BE, + 0x5BD5124A, 0x8BF599E9, 0x3919AD4F, 0xA40901C2, 0xA1D4CC03, + 0x6ADCA36F, 0x9D5CCB0F, 0x870E2A58, 0xCEBC6333, 0xB2FA28A4, + 0x579C76A, 0x444849D0, 0x33887308, 0xB3BE3C75, 0x93745501, + 0xC289F137, 0x89739C7, 0x97C73423, 0xD627FB64, 0x6EE36F05, + 0x1F4B4B98, 0xFBB7A8AC, 0x60941E62, 0xC3A8ABDC, 0x4AC5E7C9, + 0x88ACE940, 0x5AA2AE59, 0x9F10C0B7, 0x8F45920B, 0x5FDE21BE, + 0x1D47779A, 0x3ED27D8B, 0x69FF2BB1, 0xCB1409FB, 0xF27F4FFF, + 0xA19E3DDC, 0x206050FD, 0xAD98C2D5, 0x4DA4BC0C, 0x95D9B019, + 0x556ABBFA, 0xBC78B5A, 0xF0F224F8, 0xA9785F8F, 0xED1CE98C, + 0xD368072E, 0xE212ACE5, 0xBB7F76E0, 0xB02F237F, 0x6D85C5AF, + 0x31539988, 0x4312BA19, 0x1D5023A7, 0x7320504B, 0x70563ABD, + 0x2553791A, 0xE9768150, 0xC1B2AF4B, 0x3AF0FD24, 0x3818D0E8, + 0x7F356F58, 0x98A15B0D, 0xAFA943C4, 0xB2B38831, 0x2E411F37, + 0xE3D5AF87, 0x67BEEC5A, 0x825E60CC, 0x1C44D856, 0x1A59493A, + 0x13BAABCF, 0xAEAA4D44, 0x5CFF2A6E, 0xFB47865B, 0xE778E607, + 0x101500E8, 0x2C17E66A, 0xA0B30350, 0xFC649CDF, 0x8B9802D9, + 0xAB87D61A, 0x21F38439, 0xD3D11051, 0x1FDA9955, 0xCB9313B8, + 0x327D1A94, 0x35293099, 0xB803B298, 0x5B8E6883, 0xFA309C3, + 0xDFDA8B2, 0xDF89211F, 0x9918F18E, 0xF0C05CB1, 0x71D8A4B7, + 0xE681031D, 0x537012F6, 0x4DF822F2, 0x34B75C8C, 0x4429F85E, + 0x5D3C4C4D, 0xFB0FC6C7, 0x25F4ECDD, 0xB19D5EFD, 0xD70FD7CF, + 0xD95C45D5, 0xCDAC06B8, 0x9C3B963B, 0xAB2F2A9C, 0x4D3D4F7D, + 0x12692C03, 0xB1AEF97E, 0xF243EFA7, 0x78C4C8DF, 0x182D9C17, + 0x8D2AF450, 0x7596BD9B, 0xE8E7C9C2, 0x86F617F8, 0x1F37A708, + 0x3F648305, 0x27FF6DF6, 0x4D5FF17D, 0xA9541C2D, 0x9773013, + 0x78B2313C, 0x82C0B20F, 0xD36A4F02, 0x8DB2BC4F, 0x9296D8BF, + 0xA983CC7, 0x31AEE908, 0x48CD7E6F, 0x9CB1DD7F, 0xAB89D57, + 0x5156132E, 0x6345AA59, 0x8D2CB12D, 0x94D3AE56, 0xA4E91B27, + 0xEE58338, 0x8620EA15, 0x5454D04E, 0x1142ACF0, 0xCA059044, + 0x31811D8A, 0xD498290, 0xB65F1B67, 0x462745F3, 0xA899191C, + 0xB9C19F48, 0x824659FE, 0x9A257101, 0xC330F34B, 0x42109127, + 0x9DA8504B, 0x6C3A989F, 0x5F426E6C, 0x2B922D32, 0x373C66FD, + 0xAFE3418B, 0xE3788682, 0x83B46626, 0xD0106A4E, 0xFD10B903, + 0xB0F6531C, 0xC65419E0, 0x3963952B, 0xB8799DF9, 0x3EEB8C1D, + 0x5C4D3C08, 0x6DD028A6, 0xA55678A0, 0xB8247141, 0xC1267586, + 0xF6746B19, 0x46C38465, 0x483D24B, 0x99BF79DC, 0x78F778C3, + 0xAFF40193, 0x58872B07, 0x6DA7F4FA, 0x66B5CEA3, 0xDD2D8C79, + 0x2A8D289B, 0xB5789670, 0x66AEFCE3, 0x56FB52B3, 0x20FE3BE1, + 0xCCDFB492, 0xB0F263E8, 0xD0707433, 0x5E58F5DC, 0x4ABEBE63, + 0x8A45CD95, 0x97037830, 0xBDB1F1B5, 0xA1BE2990, 0x57B718FA, + 0xD50EC023, 0x810DD849, 0xE650D43F, 0x3895C77D, 0xE142C382, + 0x35551E5B, 0x3B94330, 0xE92D8A91, 0x50BC837D, 0x61499A8F, + 0x2639B468, 0xF8FF36E1, 0x74956FC6, 0xFF0F4192, 0x6BBA0C53, + 0x5B44FF85, 0xBBE4A1DF, 0x12D6CB14, 0x6C679A10, 0x3C0F554D, + 0xECBADA32, 0x8A99BA10, 0x738C03C4, 0xB8902AC3, 0x7008D470, + 0x49BC2ED9, 0xFBE19B5A, 0xA1E4879A, 0x36129694, 0x94987C3C, + 0xE54B84D8, 0x9CFAEF1E, 0x527127DC, 0xA8FCAE0, 0x8699252C, + 0xDAAD4629, 0xC41F3866, 0x2559C272, 0xB1C25848, 0x3F9B1702, + 0x7C448BF3, 0x8CCEDF5C, 0x3A37F712, 0xFB9E4F83, 0x5754E801, + 0xB38FD367, 0x780F4825, 0x959330C4, 0xF6276BE5, 0xAE3E2018, + 0x182DC907, 0x88E733F9, 0x6FF870A, 0x79EF2D01, 0x3EAC0D6D, + 0x20D4FF88, 0xAE6EB8C1, 0x80810451, 0xC228E035, 0xBD942803, + 0x3F3733F2, 0x9F8F16F6, 0xAAA65031, 0x55E839BC, 0x7EAD3461, + 0x5F5BEE8A, 0x8668BDBA, 0x399366DB, 0x2A54237E, 0x776789E, + 0x7B171AF5, 0x8C9FCB92, 0xD87465F2, 0xFA3CAAB5, 0xBA5B131E, + 0x1FD2D438, 0xDCAA9DA, 0xE1BF0AAA, 0x1EAEA8AE, 0xEB46A646, + 0x989D1EA2, 0x98E8B45F, 0x12A2415B, 0xD107D293, 0x5F54D087, + 0x95AF5C33, 0x2A12BA88, 0x6381D0FF, 0x688EA1E0, 0xACC60CA2, + 0xF19636C6, 0xD4D465E2, 0x2A50DC57, 0xFB595CCF, 0xF5C63674, + 0xB4965626, 0xB903D3D0, 0xD9581548, 0xBBD9E82E, 0xE22BCEF3, + 0x9FE759D, 0x6E8D8F4E, 0x655325D2, 0xE1986814, 0xEA2B93BF, + 0x88085C18, 0xF82BFCB0, 0x3FCF713F, 0xADE03EDC, 0x2D2DDCBC, + 0xEDE2694E, 0xF6DFB11D, 0x5CF35A5A, 0xD38C82D3, 0x52DE32CF, + 0xB88EA70E, 0xF7FB134F, 0xAEC78D1E, 0x58402C66, 0x54CD1763, + 0x78A7EB4, 0x88F49C30, 0xDC17F8C0, 0x9C49A368, 0x926E18EB, + 0x4DD461E1, 0xA6BD8F3C, 0x6D2E4C31, 0x657506D9, 0x445EF83F, + 0x77E28461, 0xF715400F, 0xBB76D1D, 0x9B670CD2, 0xCEB9EB90, + 0x7F297088, 0xD3929A52, 0x9B62909, 0x46474012, 0x3D74DFDF, + 0x46288EF0, 0xF0C51C07, 0xEC642B66, 0x3C76B83C, 0x1E72D08F, + 0x9F95DC1E, 0x106883C5, 0xB6A867BD, 0xA532C423, 0x95076036, + 0xA9DBEA73, 0xA3F8C65D, 0x799CF6BF, 0xA4508346, 0xB37CACB2, + 0xF6A07B5A, 0xA2C24137, 0x2E1D8DEF, 0xD28C26AD, 0xCE745089, + 0x3B7D9638, 0x7189CE82, 0xBC3F7850, 0x5660A9B8, 0x13895B5C, + 0xFA59A643, 0x9B0FF4AF, 0xFD2B4FD3, 0x4C0C4E52, 0x272631DE, + 0xA52FAE47, 0x65850A25, 0xD51ACF2B, 0xD206E6EB, 0x3CDC96EB, + 0xA6FF9E3A, 0xFC601E27, 0x658EF7F0, 0xB45FF508, 0x36A9A571, + 0xCE75E7E9, 0xC4BF9261, 0x3A261099, 0xF1B1CE3E, 0x3D28A165, + 0x3435D2FF, 0x70830AAE, 0x8DFE14F7, 0x3E27CDC1, 0x97BE4BA1, + 0x33F8D0E2, 0x9B2E7BCD, 0x1923B1C, 0xAA248E78, 0xFDA8AEB9, + 0x7825E511, 0xBF20B777, 0x218E4234, 0x7B5D1181, 0xA08988A0, + 0xD9009231, 0xEB15A567, 0x47E045A0, 0x3C515808, 0x35194ACB, + 0xA476304A, 0xEF738BD6, 0xD035FB8C, 0x3B2013F4, 0x4DE60F26, + 0x361431DC, 0x82ECB228, 0xAB22266, 0x4E056EEE, 0x6642D288, + 0x48D851E3, 0xE05D55D9, 0xDC2D6D4F, 0x158F7F48, 0x5D7F7D5A, + 0xC2835158, 0x793509C5, 0x479DF33C, 0xDEF0696A, 0x9FC2BECD, + 0xF4EFC675, 0xF8D1FF02, 0x493D3BD6, 0x7FA1C10F, 0x641B324D, + 0x996DBDDD, 0x24098529, 0x81CCFC35, 0x47F0BE17, 0x5E241815, + 0xF7F62788, 0x261CDAF5, 0x10CBC4B8, 0x5D6C6A7B, 0xD671AE81, + 0xB2C8DCD9, 0xD215CB7E, 0x3403AB1B, 0xA7C5999, 0x4675A50, + 0x369C560C, 0x32C619D9, 0x4FD2E12E, 0xB4A20359, 0x37E93502, + 0x5EC0CE10, 0xB374340, 0xB0DF0419, 0x5960ED4F, 0xF0A7770E, + 0x7F504F30, 0x54A92972, 0x3E9848B8, 0xCD980ABE, 0xDE69D570, + 0xA9FDFFBD, 0x9812C681, 0xDAFCCF4E, 0x2B636CB5, 0xB2B9FF2D, + 0xB9972800, 0x701231C6, 0x2E1108F8, 0x8C323A3E, 0x20A17A77, + 0xF2C6CC7, 0x44C5FD1C, 0x731622D4, 0x9BF0C91E, 0xB61CD1B1, + 0x61FA9CF2, 0x5E460518, 0xF75A1C06, 0x417CCEE2, 0xB45E0FB5, + 0x53DC30E8, 0x500CBD7F, 0xED61DAE3, 0xEFE91818, 0xB56814BA, + 0xD37D84C8, 0xD5DA9ED7, 0x5F40F92, 0xF1507FAD, 0x2CC74A65, + 0x32AA6279, 0x33731317, 0x30E09F03, 0xE1D9C403, 0xC21E638A, + 0xA7394D05, 0x3879F710, 0xDBB52C37, 0xB7780268, 0xE268E178, + 0x9F8072D3, 0x97CC035A, 0xEE65287D, 0xA197441A, 0x21C8AFA4, + 0xB81B50A9, 0xAF6ACC93, 0x7BB55B77, 0x564A0BD4, 0x17F7A6A9, + 0x36627846, 0xDCE746EA, 0xBB9762DE, 0x47B5B8F0, 0xEF5DA4AD, + 0x1922E420, 0x15F9299D, 0x243DAB0D, 0x953C67A3, 0xF3DA71D8, + 0x57122A3E, 0x423A78B, 0xC4A53000, 0xFBE92583, 0x968F3AE, + 0x61629123, 0x792FA07B, 0xBF45729D, 0x99DDD38E, 0xA14565FC, + 0x268E9E3F, 0x7EC9286, 0xCCA1D92A, 0xF06519DA, 0x22396664, + 0xD5DAC24D, 0x71BB4DD5, 0x7D329BB3, 0x401DAB69, 0x19D3E40A, + 0xB6F40F32, 0xE8D1CAF8, 0x5CD5F35D, 0x6F662316, 0xD38D1A6C, + 0xF86E720F, 0xE165D1B9, 0x1BC14E79, 0xC19FB43D, 0x891C013B, + 0x44AED4DC, 0xA7351AAC, 0x5F707A18, 0x3850148, 0x4A425E1, + 0xF7DD6EBD, 0xE0C3FD0E, 0x8266A425, 0x3BA17650, 0x48753ADB, + 0x679FA015, 0x88771712, 0x2174B185, 0x29F9A85A, 0x1560964A, + 0x198E4FCD, 0xD3410A86, 0x9186793D, 0xDAFC5C35, 0x971F4CC8, + 0x1F8F0E8B, 0x11A884F2, 0x66E6D2AC, 0xE85ECDB0, 0x86C76472, + 0xDF3B3320, 0xEEF446A6, 0x834CF19B, 0xECEA602A, 0x46C680AD, + 0x807BA92F, 0x4B3FC42B, 0xEC229845, 0x3FE389C1, 0x63E042D7, + 0x6C855119, 0x7B1ADF33, 0xE1B9CAE0, 0x62C20BAE, 0xEDF0E919, + 0xA50FC7EB, 0x2399262F, 0xD6F88130, 0xE2ADA5DB, 0x7D07BC3C, + 0x36A922F3, 0x7693B84E, 0x3015CD0C, 0x1D1047A7, 0x5D3A75A5, + 0xEE6F1CA9, 0x734BD19F, 0x3308DD73, 0xCEBBC9FA, 0xF79DD5A6, + 0xA41CF168, 0xED762FD8, 0x6642159, 0xA63C5CD6, 0xCB96A282, + 0xA29D9F5C, 0x45CC6CD4, 0x344611EF, 0xC345FE03, 0xC55ADDE0, + 0xB2B8374C, 0x14F730B1, 0x301D9266, 0xA2D98FD8, 0xBC107DF, + 0x59905EE3, 0xDB3560DF, 0x1D49F4F3, 0x785F8E0B, 0x8B116097, + 0x56154F60, 0xE312D829, 0xE0AFAE9B, 0xEAE3692E, 0x95915B8F, + 0x83BEEE75, 0x48C1C92, 0x8166D95E, 0x697FECA8, 0x135DEBF9, + 0xF83E6507, 0x11570809, 0x4862CBDE, 0x820E288D, 0x6CA59B2B, + 0x49DF6AD5, 0x86F41C43, 0xDD128A28, 0x601198A0, 0x3DDD49CB, + 0x95F3ACCE, 0x500CD9D6, 0xF54A50F2, 0x9936957B, 0x7C881875, + 0x743B055D, 0x44FD7934, 0xAF2253BB, 0xA2F4A27C, 0xBA8E1C2B, + 0xCCFA3259, 0x892FC73F, 0x283E74B4, 0x86119027, 0x87961F02, + 0x1D015187, 0xBA83B762, 0x61948B32, 0xAC741667, 0xFA9E0E39, + 0xD440D9CB, 0xED93F9F, 0x5FA97905, 0x2F5F82D8, 0x92EC7646, + 0xC60B3F9, 0xAA28822A, 0x7BA7CD3D, 0x3E41A20B, 0xDE4441A9, + 0xC75E539B, 0xD9D568C2, 0x2DCAE06, 0x7762550, 0x21C2D5EE, + 0x95CB6C94, 0xE31FC800, 0x3C03C172, 0xE166E564, 0x359C5102, + 0x7F717599, 0xBE301B47, 0xB207FA5C, 0x38B8B24B, 0xE6EFF05D, + 0x9F09D305, 0x31A27808, 0xC56D934F, 0xB440BD60, 0x52B1AAC4, + 0x78654045, 0x106A67B8, 0xF2A861E5, 0xC45D72B0, 0xA8FF8296, + 0x97F475A6, 0xDC222733, 0x7A835D7A, 0x45774E9A, 0x9E558C34, + 0x1124605D, 0x1689FED3, 0x70AB9928, 0xADBF8E55, 0x9C09EE27, + 0xF95A8C49, 0x75CD52D7, 0x4FC7275A, 0xA46C29F6, 0x747D788, + 0xA3347E5, 0x5B08AB02, 0x13CDC08C, 0xEDB65176, 0x6B36600A, + 0x26F5AD2A, 0x39949D1, 0xA1C8F6E5, 0xEBF0CEFF, 0xAB60A06B, + 0x10E522E8, 0x80E056D8, 0x1B301392, 0xDC3E0B07, 0xE10174EE, + 0x25DC4733, 0xB4E5A24A, 0x4B569CFE, 0xCCFE9F0D, 0x19BDC038, + 0xF8A0A718, 0x9944E8E0, 0x9591528, 0xBF27BDF1, 0x2C160255, + 0xF9E2F1B, 0xCE4FD96B, 0x703B2A77, 0xDB6EB2A7, 0xBFC2FA6A, + 0x11D00F81, 0x9540FD8D, 0x75849882, 0x183AC87C, 0x91DD1783, + 0xA3A0CC0D, 0x47F1CED1, 0x4DA4EE62, 0x819BA59E, 0xD5DA1DA5, + 0xDC218BF5, 0x899CC3A1, 0x1DECAD82, 0x77E193A5, 0x9F390C10, + 0xF5FCD674, 0x1E43657A, 0x6B61D25E, 0x99B9140E, 0xFEFB9CF9, + 0x6569445D, 0x14C9A2AF, 0x85A33FB1, 0xE4029ADE, 0x4FABD0FB, + 0xDE02379B, 0x65C8311F, 0x3CF60630, 0xC8B179FF, 0x9D83CE64, + 0xFF683C7E, 0x6D796948, 0x249B0AFA, 0xC5A65FDF, 0x252DA26D, + 0xFE92E52E, 0x90D081E5, 0xC5A8E180, 0xEBDB0943, 0xB0E7C78B, + 0xD5A89E4D, 0x684EE280, 0x8AAB613C, 0x6BD1547, 0xD12F7355, + 0x9C5D1363, 0x91E410A4, 0xDC841FBA, 0x703A9371, 0x79F8663, + 0x553650FC, 0x633CA726, 0x20107BD7, 0x2565F252, 0xCDD93830, + 0x3446CF7, 0x92B6B42A, 0xA070B2D1, 0x5E0384D1, 0x7CC5A19C, + 0x6890558F, 0x10D308AA, 0xDFF3016C, 0x1093AA3B, 0x8927683A, + 0x9259502B, 0x2B544B7C, 0x419B1B1A, 0x22D9E939, 0x568ECCEE, + 0x4F3CE09B, 0x8B990521, 0x8D6906A3, 0xC15DEDC4, 0x98384A4A, + 0x8F2F2652, 0xEDB9D614, 0x1D010AC3, 0xA2CDC134, 0xEEE9A9ED, + 0x241DB9A2, 0xE9DB9AE7, 0x7A788F9E, 0xBD0778B7, 0x27373539, + 0x7C6B4A4B, 0x3C7A6B37, 0xDE1C625, 0xC1256E67, 0xB8E69163, + 0xCC05D09B, 0x728A1427, 0xECAC2530, 0x1DD40BC8, 0xEFE42E56, + 0xB4266BE0, 0x9AD3F869, 0xDDFC2F60, 0xEF29B3F7, 0x7C15F90A, + 0x705C2992, 0x99AC7AEA, 0xCF1F09A0, 0xB41F14D9, 0xBF3C252C, + 0xF3483286, 0xD3AC398E, 0xB84BC93D, 0x6B780D11, 0xF682D379, + 0xB8A062C2, 0x9A003A9E, 0xF18F54FC, 0xDE81BB83, 0xE84C5234, + 0x37CB67FA, 0xDB685C6, 0xBF2BF28D, 0x8CDE583, 0x94CCD0BD, + 0x8BCAF516, 0x31BE93C2, 0x3ED4B623, 0xCD23346E, 0x8254E7A0, + 0x6091EF1F, 0x17A42562, 0xC9821677, 0x447B6623, 0x19D9356C, + 0x4A1C1953, 0xD1F3B7F9, 0x99F8388D, 0x62F22304, 0x5EDF1ECA, + 0xB6C9FC2F, 0x42968E22, 0x531BD76E, 0x25E6A95A, 0xA1669784, + 0x8B915BD2, 0xA5E21483, 0x5ABE3226, 0x605C0E15, 0xFDE713CC, + 0xFAC58D3B, 0x44FAF6E8, 0x41E2D699, 0x8EE11E34, 0xB03BE4F6, + 0x75054C0D, 0x1AF2D37, 0xF38E6829, 0xE7F2A519, 0xC9CF2CFF, + 0x996DDE8, 0x395AC493, 0x42AFF184, 0xB380B71C, 0x11AA0B90, + 0x66DC636, 0x56557CA8, 0xCB8CAA43, 0x9EBF806E, 0x63F66159, + 0xA011191D, 0x17B0AED3, 0xB9621251, 0x2B189E3, 0xD45A5D7, + 0x23009D12, 0x5DEB7918, 0xFDFB1FC8, 0x46808A73, 0x91D29330, + 0xF872C15D, 0x7BE90206, 0x257E9FCB, 0x2E52FF67, 0x1852DDF9, + 0x6A2C5C49, 0x6ACF891B, 0x29FFB0E2, 0x76E32CD2, 0x588799, + 0xD71D970E, 0x9B079EC8, 0xEBD25420, 0xDDB60276, 0x761B106F, + 0x871473C4, 0xBC697CE2, 0x5378E0E9, 0x8DAECE28, 0xE5B275FA, + 0x6E6E332, 0x853884E7, 0xD0FFF1A2, 0x722D372, 0xDD5A754D, + 0x87CDDA3C, 0xA9B629C0, 0xAB2E650D, 0x1709413D, 0xDAE63819, + 0xC60DE8CA, 0x9F344BD6, 0x8E651EF9, 0x3B6A8019, 0x95CC1296, + 0xB12DAEAB, 0x8D550156, 0xF14E85AA, 0xD2547469, 0x6336E320, + 0x223B05B9, 0xB88AD493, 0xEE14916F, 0xC78AF1FE, 0x65FC2787, + 0x778FA85F, 0xBA23A57E, 0x957EA954, 0xAE4F9577, 0x47C38D4F, + 0xDB7BCDC9, 0xBA13E42E, 0x46B01094, 0x1A15F5E4, 0x315AB789, + 0x9E44B54F, 0x8C690B2F, 0xDC4954CD, 0xF176F3FF, 0x9B154C06, + 0x112BD6D0, 0xCB120BBC, 0x11101771, 0x1F29A19D, 0xC3F8193A, + 0x805D6739, 0xE3B00ACB, 0x23DD9494, 0x4F88EBA5, 0xE6F32E0E, + 0x4B76F089, 0x43B66BEB, 0xF2420B12, 0x2CFC5E01, 0x1C68D3DC, + 0x30C1BD38, 0xF3A0FCCA, 0x2AF13CD5, 0x13E38185, 0x2DEE2A21, + 0xFC318E26, 0x1954D4B6, 0x3FB86424, 0x24D698F1, 0x4AB76D48, + 0xA9E87BD9, 0xCE1DD2F2, 0xF5904D9F, 0xF614DB18, 0xF83111D, + 0x1FB56EFD, 0x5CBD08D8, 0x2D8D4884, 0xE388C534, 0x413D5BB8, + 0xEB6D14D6, 0xAE54E361, 0xF73D926B, 0x43F27197, 0x7C50A2E5, + 0x10EDBD6C, 0xD151B569, 0x47C50C06, 0x8FD59E74, 0x551C6841, + 0x2EC2B6DC, 0x5CEAB3A9, 0x1E6A1609, 0x3FB07FED, 0xC0D5849A, + 0x6354A21B, 0xEBF18830, 0x2BB3EBBD, 0x9D4DF510, 0xBBBE1103, + 0x918D6DDF, 0x3FEE7A8B, 0x4FC47254, 0xE0E1EA65, 0xF3DDB31A, + 0xADF8DE67, 0xADA31FAF, 0x2BC0B8A2, 0x184B7432, 0xFDB2E733, + 0x236B014, 0x21062C, 0x8FAAD8D7, 0xA1DA7E44, 0x3EF7F42F, + 0xA67AAB82, 0x9238F0D8, 0x42F93C63, 0xEF0F4BA1, 0xE61DC644, + 0x994EF92C, 0x71A58613, 0x371665E5, 0x82E77BA1, 0x2FFA1DAE, + 0xFE19AAA0, 0x95C72A53, 0x6A21395F, 0xC03F853C, 0xBC7B73BC, + 0xED62A949, 0x4F7D3C52, 0xCACFB353, 0xA1629BE9, 0x16255784, + 0xAE465FC4, 0xE7FC2626, 0x5E9B0FC2, 0xD109084D, 0xE30E7B89, + 0x94CD7424, 0x6127AF6E, 0x7D08ED7, 0xFA0B9293, 0x450A112F, + 0xD0D79344, 0xA204F8B0, 0x5F825780, 0xD681148D, 0x71C6AE83, + 0x1DF62587, 0x99ABC8A6, 0xCFEE8131, 0xFCD11719, 0xD0D48B0E, + 0xCC4A710E, 0x7414791C, 0x22167734, 0xD17FE049, 0x5BF15C46, + 0x30B718E0, 0x6E85104E, 0x52F72575, 0xA17F09E1, 0xCDA7B24E, + 0xDAF7D03B, 0x3632D94B, 0xBAF4E9EE, 0x390CD998, 0x168C055E, + 0xBC2D8D0D, 0x35E9F642, 0x89757E1A, 0x2BB98011, 0xC19BCD15, + 0xEEB73587, 0x6A5194EB, 0xC2C1B4BA, 0x3C8F73FC, 0x8F075D29, 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0xC6D5F72, 0x97C35532, 0x6580493F, 0x9D31E266, 0xEF926A38, + 0xF68CF9C6, 0xF770C570, 0xCA18C06A, 0xFA2BB2, 0xFBA375DC, + 0xC2FE76ED, 0xB91611FA, 0x528A8EA5, 0x360A527, 0xF631D04B, + 0xF0C67ECF, 0x4E490A69, 0x19DB46F0, 0x497DFBF4, 0x58E490FC, + 0x24A51378, 0x186BDC14, 0x90E633A3, 0x6D6F8D95, 0x2FDE02DD, + 0x4B2714A6, 0x6FC87FE0, 0x21569667, 0xDCC31F06, 0xC9D9DFD0, + 0x830AA4A4, 0x78FBFE69, 0xDF17CD55, 0x3952AAA7, 0x9A4B5A7D, + 0xB1EBF3EF, 0x4F3BC1C9, 0xDFEEBF40, 0xAB130CC8, 0x1EB84425, + 0x4625E802, 0x20B990D6, 0x4E36869F, 0x5EEC0472, 0x29194460, + 0xCA425ECA, 0xEB0742C, 0x17D07C02, 0xF38BCA14, 0xBC9D555E, + 0xF15822E7, 0x89CF96E0, 0xAA848F9C, 0x90731AC9, 0x86EECBE3, + 0x308F3257, 0x5FF375DC, 0x1E62C041, 0xFDB6A3E7, 0xDFEBED8E, + 0x8FC77E76, 0x6973E542, 0x2AD1616C, 0x99B549C6, 0xD28CF364, + 0x88C87768, 0xECA2CFB, 0xA0D0B060, 0x42DFFD8, 0xAF80A6DE, + 0xFF323760, 0x1CB2DAAA, 0xD11DE4FC, 0xEEBF565A, 0x9C986CAC, + 0xC1C95B3F, 0x6868BF0, 0xF5604930, 0x316DD9EF, 0x1231D331, + 0x95E38E67, 0x7D30C191, 0x354804BA, 0x265EE5E, 0xC6728C70, + 0xD36F32D0, 0xBBEA0ECA, 0xD055ED76, 0x9135E317, 0x8A7B9770, + 0x4D1344B0, 0xE9F29AE3, 0x7BA303B9, 0x2C38AEC, 0x82ABCBA6, + 0x7729F177, 0x71793932, 0x6FE6E38D, 0x1F8416B, 0x147D8310, + 0x6A962FEC, 0xFE2F100E, 0x4FB1D511, 0x3D38AB33, 0x58ADC416, + 0x64B07504, 0x458CC4B4, 0x584BC93E, 0xDE49B6D1, 0x7347876, + 0x4A2C3EB6, 0xDF5DE09C, 0xBFD376DC, 0xC9F451C5, 0x5F793A0, + 0x892952A2, 0x15060767, 0xE1E3B589, 0x4D513C3F, 0xAF3D2CC7, + 0x289DAA2E, 0x8C711417, 0x62E5E006, 0x3BECED98, 0x99E73ACC, + 0xDE156054, 0x1283655B, 0x5123FC41, 0x3DE21841, 0xC032F050, + 0x94B5151F, 0xA5577757, 0xCC0C8DF, 0xBDB52821, 0xD530FAAD, + 0xD070D8FC, 0x46F5BB68, 0xB02DFF88, 0xD4923EA8, 0xC85A5622, + 0x93E834A3, 0x38E84468, 0x79408C75, 0xCCB635, 0xE76BADA2, + 0xC2296DA1, 0x711543BB, 0xF441F4A2, 0xBD18127C, 0x8385BFB9, + 0xD350D4D, 0x90FAF999, 0xABD1A695, 0xFCEE12C7, 0xF428912A, + 0xC9759F80, 0x6DB6491, 0xD1421D30, 0xBC398DC4, 0xB8E0A889, + 0xC854AA72, 0x82CAAF64, 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0xCBE90203, 0x6979F11D, + 0x251C50A4, 0xDAD9C59F, 0x5E4E5BFD, 0xCCD4DF48, 0x72BD66E, + 0xE7FB1B35, 0x75B4B83B, 0x29E9282A, 0x2590317D, 0x7835F9A1, + 0x25D3602C, 0xCFEC2E4F, 0x9CA2B0E7, 0xA4714302, 0x8F3D53C4, + 0xDE00F109, 0xC26D6273, 0x3E8DC623, 0xE3A972E2, 0xF67DF096, + 0x781682A5, 0x6C16F144, 0x49DC8D17, 0xB2EB82EA, 0x3CB93D91, + 0x44D4D3C4, 0x556040F, 0x1406DD74, 0x55FA83ED, 0x91C35357, + 0xF5A1C63, 0xA64E34D0, 0x7DF58C80, 0x62E97E52, 0xFBA1A2FE, + 0x8CB29D60, 0xDC1AEDE5, 0xB260BBF, 0x1AD9C6A6, 0xC60E9788, + 0xAD9DFA42, 0x2E422C17, 0x51CB5E86, 0xEB840466, 0x2666D5D8, + 0x7A0F7C62, 0xDE052A31, 0x6F0330C4, 0x9142D4AD, 0xDC8578C9, + 0x978F3E76, 0xEE43CB4D, 0x14E7EFC7, 0xB50B064B, 0xD7FB2900, + 0x67C4F4A3, 0x4D1193D7, 0x5091FB73, 0x3EB9C846, 0x960BE069, + 0x88250E7E, 0x94503385, 0x1C1F244A, 0xCFD72CE3, 0x8CD5F105, + 0x2B34131F, 0x60D266E2, 0x16BA806A, 0x25C25A42, 0x5FF6C068, + 0xD23A191F, 0x7AB5C53D, 0x9EA37FBB, 0xD1AD4B07, 0x40BCB39C, + 0xF45C8526, 0x80FEF5BF, 0x197D6D43, 0xD56FD4D0, 0xF39E498B, + 0xFB4F6847, 0x84DF289A, 0x2246F5CF, 0xF979B823, 0x42DCD843, + 0x1AB1BB0C, 0xABEC5FCE, 0x6E7EBC1, 0xE013DB54, 0x73BC8A04, + 0x88D0F71E, 0x4D93B6D8, 0x57B0B7CF, 0x99371728, 0x86B129E9, + 0xF4EB3DD2, 0x6956AA9D, 0x4C84AA0, 0xFD22CA10, 0x36E6915F, + 0xC830D7EA, 0x1EE1666, 0x1036A43F, 0x3FC86E7C, 0xF10F9CD2, + 0xEFF5F21B, 0xBF9082E0, 0xDD0DD00C, 0x80524F27, 0xDD5A3222, + 0xEA53B93F, 0x7FDA09AC, 0x89840C97, 0xC3A9BDCF, 0x1EC26899, + 0xEBCAF99C, 0x2EBB3226, 0x936A3254, 0x2E1E1786, 0x57E4CB9C, + 0xE5CDBE5, 0xFBA2458C, 0x48F3D0EF, 0x74FD06AB, 0x96C30795, + 0x14FEF0E9, 0x2F5FBA0C, 0x3CCEA60E, 0x7BA0354A, 0xCD7329FF, + 0xD4169550, 0x5FAA5E66, 0xF0C25CA2, 0xEBCC8065, 0x3F147D8F, + 0x5ED3293E, 0x6457117D, 0xE4CF4B98, 0x11F1E74E, 0xC13F47EC, + 0xBC7E22DC, 0x22512D19, 0x9140ACBB, 0x490D52F, 0x3E2D54C2, + 0x9FCBBC1B, 0x89646A33, 0x9FE4B65F, 0x92CE9ECC, 0xFBD59FB9, + 0xCE95DAD1, 0xBBCDE794, 0x9C0FA1C6, 0xCFD90F8B, 0x494C1770, + 0x21AD2AAE, 0x58EC00A6, 0xB0848A25, 0xEC4FEB5E, 0xFF1517EC, + 0x52871C07, 0x105E05B0, 0x178B1913, 0x18023805, 0xB16BBC6B, + 0xF8522A7F, 0xB17DEC22, 0x3808ACAC, 0xBC5B9043, 0xBEC01BA4, + 0xBC6CDA0B, 0x17906D50, 0x8422829F, 0x51C9AFB9, 0x54F78CEF, + 0x72CEEA16, 0x76A74B94, 0x7EC063E2, 0x51C65B1D, 0xD97ED9B8, + 0xDE89F034, 0xB5AEEFA0, 0xB88D3E9D, 0x9D4C57AE, 0xC8CEA9C1, + 0x941A74D3, 0x8E2FC33, 0xEDCEB551, 0xB91FA3E4, 0x8BA2261F, + 0xE558E0F2, 0xA4E81979, 0xAAE31455, 0x70B62249, 0xD48D1A67, + 0x11767EB6, 0x823DFECA, 0xC815C538, 0x2AB67EE6, 0x22FA86BA, + 0xD7A1F96C, 0xBA96E382, 0xB75B3FB7, 0xCB705FAF, 0xD1B9D3E2, + 0xD4C8DC2F, 0xF954B0A5, 0xDABE493B, 0xCA3FBB37, 0xBBDC387C, + 0xA30C87D6, 0xB5B493D5, 0x584F5615, 0x90FB6370, 0x5544A92D, + 0x980F7FA2, 0xF1459235, 0x130B11BD, 0xC7A44998, 0xFEBCA776, + 0x7943BE84, 0x72C99B04, 0x353F6042, 0x66F5C2F2, 0x9C5B2CC5, + 0x9FF06E41, 0xAC9E5492, 0xFF9A1CC8, 0x4429DE05, 0x97845307, + 0xDBA36668, 0x40BEBB2F, 0x606DBA6A, 0xDE7A4225, 0x9AF7FB71, + 0xE97A0E6C, 0x99C2AA59, 0xE00C525B, 0x5D4F9521, 0x89C5D7BB, + 0x18481C9F, 0xA27A1F59, 0x2A6267A3, 0xC467981A, 0xE04CE94D, + 0xAAB2AC1D, 0x5FD1AC86, 0x8F33E395, 0xE1FBE285, 0x636C2961, + 0xD838584E, 0x2F845D90, 0xAD52A8ED, 0x8F8C841B, 0x829A3861, + 0xAA0FF413, 0xA079F240, 0xB15D507B, 0x93722B10, 0x833AF929, + 0x4FB5B879, 0xEDD3031D, 0xE22CE740, 0x9ADF835A, 0x13A0C7A3, + 0xD5791B98, 0x99D9409F, 0x9F776A0E, 0x8665EC9F, 0x7301EF7C, + 0x9B341035, 0x59EADE7F, 0x242C1ECA, 0x20FD13FD, 0xE22DAF76, + 0x3859E84D, 0x6ED83DA, 0x54ABF391, 0xC43F4740, 0x4661F86, + 0xC6442213, 0x7FEAF294, 0xC0CAC024, 0x38B9FA9C, 0xFFF33259, + 0x1AD86335, 0xB365445F, 0x54B58378, 0xFD7AE96A, 0xE019B245, + 0xCF51C4EC, 0x604D7EE, 0x7B40C023, 0xA5E168B0, 0xD7B8C643, + 0x91C028D3, 0xCB939A6B, 0x169B0123, 0x96FF8CFA, 0xFCB3E126, + 0xB95C01B1, 0x1758BFB6, 0x50F50968, 0xF774D536, 0xC5A8BFE7, + 0xE2496BE, 0x6FB8D434, 0x3F7FEDB9, 0x9BDEE991, 0x1CBD2009, + 0x2CE74DB4, 0x1CB51025, 0xE965ECE6, 0x89100034, 0xA089E8C0, + 0x5860A65B, 0x9C4D349E, 0x54898852, 0xD07C9738, 0xBC677E89, + 0x75B5D0C1, 0xCFD435AF, 0xED550357, 0xAED9301, 0xDCD1734A, + 0xEDCD21D7, 0x69F6A592, 0xEF8009F7, 0x44374358, 0x9405770D, + 0x668AC4FA, 0x50507E61, 0x2DB19DDC, 0xA9BDD137, 0xFB722699, + 0xBC067E88, 0x88740174, 0x717CCEDC, 0x9F7F1E11, 0x389F4CC, + 0xCF4D0018, 0x24588FF1, 0x25C9F951, 0xDA660468, 0x6C09D91C, + 0xC9F788E, 0xDD4DF43F, 0x8B04484A, 0xC7F67DDB, 0xD2939F8B, + 0x96BCFDE5, 0xF6DD10D8, 0x1124A3BC, 0x7C281FBB, 0x5FAFA71B, + 0x58A9C493, 0x4747793C, 0xD3B79E72, 0x357AA675, 0x8E94A74B, + 0x1994025, 0x95D10FB8, 0x5C64AE63, 0x9E37973F, 0xFCE67009, + 0x8480F94E, 0x34DA26F7, 0x126CFB46, 0x206AAA6B, 0xBA0A6200, + 0x8DF3F67F, 0x4936802F, 0x950F62F8, 0x17E64C44, 0xC70E523E, + 0x2F910727, 0xAF7C5BC, 0x9EA24508, 0x1E945729, 0x55E48FBD, + 0x897CB57, 0x8C134FEB, 0x54E68223, 0x91912044, 0x7A461BDB, + 0xCE91309, 0x72135AF, 0xBF94D484, 0xDD752690, 0x32248D12, + 0xEA092355, 0xC24CA220, 0xE8A95D65, 0xE4E2EAE6, 0x664763E9, + 0x71F1AA47, 0x832550FF, 0xFFA73B6B, 0x96F5DFF6, 0x60CB9B66, + 0x75F29F5C, 0xF863AC8F, 0xF16993FC, 0x3503801C, 0x3D1E8B2, + 0x583CDFF6, 0x62AD49F2, 0x8261843F, 0x826EA9B6, 0x5E2EF3, + 0x8D3848EC, 0x7391A581, 0xDFC466FB, 0xB38DCBD1, 0x4145C3C0, + 0x73F322D7, 0x2B55F284, 0x6B19FBA6, 0xD9446AD1, 0x36C330C5, + 0xB71E4B29, 0xF29F504E, 0xB4FA4CFB, 0x290B6941, 0xA2197E21, + 0xF2AAE27F, 0x1A1728B5, 0xAFF5632, 0x6AEE763B, 0x2962A376, + 0x965D67E7, 0x231A8B76, 0xBD3596FC, 0xD4AE3E8D, 0x58D4D740, + 0x4EA3B6DC, 0x5479A7F5, 0x110A4791, 0x9A772A63, 0x728C4794, + 0x6D6A0801, 0x3F89D9E1, 0x326D1BC4, 0x49B3798, 0x5E2B3CA8, + 0x742C385A, 0x89450FE0, 0x24236A74, 0x81AC9891, 0x7BEF3C66, + 0xACECD674, 0x29009073, 0x94D6BDBF, 0xF2C6CDF4, 0xDBC21EE3, + 0xC65C89A4, 0x35DC5337, 0xBA281430, 0x787521B0, 0xADF8317E, + 0xD5739B77, 0x8567F3A2, 0x374E0CAC, 0x5AFFF50F, 0x9654D41, + 0x4A86EDEF, 0xE16C9A62, 0x59D15E49, 0xA69769C8, 0xA9197100, + 0x1E04CB9F, 0xA926CCB8, 0x5047C429, 0xB7E369C, 0x812F5F0A, + 0xA53EA5BA, 0x9AE5C105, 0xD4C7CC5D, 0xC99E02F9, 0x5BCDFE96, + 0xCDBAA854, 0xCF209B89, 0xBE08E9B, 0x5C73AED2, 0xBD959602, + 0x63C309AB, 0xEE289A4, 0xEDA954C9, 0x5C54F616, 0x3BC34487, + 0x47A3C772, 0xAB0084A4, 0x2CFB8D44, 0xF5F8411D, 0x43F6361D, + 0x12B8467F, 0xCDC437A5, 0xAC96A375, 0x7962CD18, 0x5D728EF4, + 0x66B11DEF, 0x73C87A6, 0xA35AEF9A, 0xC84F12F7, 0xB1EDE9B4, + 0x2F6A1752, 0xCF8DA321, 0x2E37F4E0, 0x4985F516, 0x684E49AF, + 0x56287772, 0xF74F95EF, 0xD994FF05, 0xC1D23E99, 0x81214F78, + 0xA5DF2934, 0xC2B686DB, 0xABC54017, 0x6918D067, 0x737A798C, + 0x3904B21C, 0xD4CB6EFF, 0xC256E4F8, 0x38B0CD4D, 0xE2D27089, + 0x75A00DC2, 0xDC1D5E7B, 0xE2295307, 0x2F0A683C, 0xD00AF450, + 0xE45C3252, 0xD86804C8, 0xF9628DB9, 0xEA011DB9, 0x6A67523A, + 0x488B54B3, 0xA292CDEA, 0xB1D1D89A, 0x17415325, 0x3EAD3D80, + 0x5D092525, 0xB5880E29, 0x1104A8AF, 0xBC177790, 0xEC730159, + 0x11B0A1AD, 0xB809FD7C, 0xB23FE31, 0xCCBED7C8, 0x45B7F7BF, + 0x9491B0EB, 0x1B1A90F9, 0xE34F4317, 0xF060A5B3, 0xF795EF1, + 0x8254A941, 0xC6CC30E4, 0x770FC40C, 0x17EC9C1F, 0x20DA83EF, + 0xF9CCBFC9, 0x9D0675AD, 0xACEA7EB3, 0x56326F5C, 0x74D4DF3A, + 0xA8FF9A9, 0x8F55E3E2, 0x5B0D12F1, 0x12DDB28C, 0x95FADBED, + 0x81F48694, 0xABEE8392, 0x90E96B15, 0x2C44972E, 0x4E2D3A4F, + 0xE8D34D14, 0x83C03E59, 0xDC295E2E, 0xDDEA452F, 0xC2A2A33F, + 0x617210DE, 0x69542DB0, 0x1DD96D24, 0x3E3871D0, 0x9DDDAF6C, + 0xBD326CD5, 0xD87CE143, 0xF3C79B3A, 0x7F811CCD, 0xDE1B1502, + 0x8075EA04, 0x9D09F1DC, 0x8CCBD152, 0x669F35C, 0xC9414276, + 0xA2BFFE0E, 0xF8AAE650, 0x190C1AE7, 0x2DBB4A7D, 0x575B247D, + 0x3A599D3E, 0xB09B4DFC, 0xCE4904A0, 0x63C72670, 0x15A3BD05, + 0x799B50CD, 0x19A2718C, 0x4142750D, 0x9013BE74, 0x21288938, + 0x590BD2BB, 0xE4303149, 0x46B308C0, 0xD2BB7D56, 0x1BFB248, + 0x943B2E72, 0xCAB18644, 0xFCC921C4, 0x5308C4D9, 0x9098CEE2, + 0x435B219F, 0x69F1BBE5, 0x155216D4, 0x83F2A4A5, 0xE177744D, + 0x37DF6FDE, 0x9D9EA50A, 0xDFA8D408, 0x6C72E71E, 0xEA617E3E, + 0xDAD6C13B, 0xB83A850D, 0x45F6BEB5, 0x6AFB346D, 0x400B29FB, + 0xBC8E57DE, 0xC6C1081A, 0x4F6A9545, 0xF878303F, 0xB9E519DC, + 0xCCF25FBA, 0xCAE069A5, 0xB79B082E, 0xF70BB7E7, 0xE6A5535C, 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0x9CA0073, 0x76772A47, 0xFBB63B16, 0x78F3C3B7, + 0xF118B4A6, 0x8E86A34A, 0x56693D7E, 0x381EA186, 0xCB9B430D, + 0xAD11DC36, 0x599B3370, 0x7A6B80C0, 0xF2A282DC, 0xF58F96FF, + 0x97AADB3A, 0x5AA06FD, 0x44A43553, 0xBE8097C6, 0x4CF5002D, + 0xBADE20DD, 0xFEC25B7, 0xC8B50C4E, 0xF0C899D4, 0x815F9958, + 0x77772B46, 0x7413F82A, 0x7203A939, 0xF4623F73, 0x35EE625C, + 0x2723BC68, 0x33790B09, 0xA58391E4, 0xA27C7C25, 0xBC032556, + 0x1D812AD4, 0x301BB65D, 0x22FAF223, 0xDCBB79DE, 0x78CE1CBF, + 0x570C796B, 0x17EF8909, 0x8E2C32E5, 0xB54FF82F, 0x7702F70, + 0x1C0A78C2, 0xCB3078DF, 0x7155531A, 0xEAC77450, 0xB9DC2EDF, + 0xA8B6A1A6, 0x57FC52F0, 0x6B5543E4, 0x40679BEA, 0xE46813E7, + 0x65525695, 0x6C9CD43C, 0x5E5BD786, 0x44212626, 0x847A8357, + 0x7E39813D, 0x9FE22F0E, 0x29EC985A, 0xC91CF47C, 0xB31A26AC, + 0xA4C8B43C, 0x8EAB7865, 0xF6F2F67E, 0x3F73A8DC, 0x4FAF5455, + 0xE1253CAD, 0x3001A083, 0x532DEAE4, 0x6A110DF6, 0x585D0FDE, + 0x19071CC0, 0x1A351A69, 0x2FEAD890, 0x33902499, 0xA218C193, + 0x2294A970, 0xB0544EA1, 0xC54B25F0, 0x6C89048C, 0xC8203390, + 0x237F30DA, 0xE8F10E5F, 0x6B57E331, 0x43744B6E, 0x2EEF4BB4, + 0xEBD13AA, 0xA9024B04, 0x22895C31, 0x321C459A, 0xFCEFD3EE, + 0x94772392, 0xA094B3F3, 0xC070FBB2, 0xF30ADCDF, 0x8D294C6E, + 0x89E4C299, 0x47DE058E, 0x841A807E, 0xDEA7608F, 0x3A45D7AE, + 0xFE08A063, 0xF2C65E08, 0x4C653ADB, 0x8E4BED1C, 0xC85C1323, + 0x63DF1750, 0x4EF4B72F, 0x209903A9, 0x3ECCC1C6, 0x4283795A, + 0x205AC943, 0x38B1ABE3, 0x1241AC5D, 0x7C645871, 0x747695BB, + 0x29206570, 0x31BACE6E, 0xFDEEDAC9, 0x4DEFF536, 0xCD6CFDC0, + 0xEB0FAB42, 0x7DFA5EB6, 0x8363D9BA, 0xCFCD2514, 0x69FEB823, + 0x10BDBDCD, 0xE4C27020, 0x56DCF966, 0x9C97BD95, 0xCDAB9269, + 0x8316F55E, 0xC62F7354, 0x5415281A, 0x31EBDCED, 0xCDF7A05D, + 0x5F674F71, 0xF70EE58B, 0x26037964, 0x584174B4, 0xFEA5520C, + 0xD01A8007, 0x7F2772E8, 0xC2FF1456, 0x7B2CA1FB, 0xE938BBD0, + 0xD96CCCF2, 0x9AE8088B, 0xF3A25E6B, 0x3780417E, 0xB9E2917D, + 0x95872990, 0x12D99C68, 0x2FC5DDB0, 0x55437D2B, 0xDB9C14B7, + 0x6BBE6AF9, 0xFBDC9201, 0xDCB32A70, 0x1CABF45D, 0xD8BCBF4F, + 0x271AE6A5, 0xD34B8953, 0x58BBFB3A, 0x537F049A, 0x55B51226, + 0xCD809DC9, 0x846DB4EB, 0xED476D72, 0xEFC8F8AF, 0x6AA3228D, + 0xA363F656, 0x2207127, 0xA1BBE245, 0x2AB58A00, 0x637810C9, + 0x91F61AD, 0x347D333B, 0x1E9598E3, 0x2E7BD8C6, 0x8DCE469F, + 0x73B82620, 0x9257D4E0, 0xD9580F88, 0xE8EF6D53, 0x2D9FAC45, + 0xB56E2C6, 0x9B369045, 0xB50702C6, 0x955D3700, 0x577CC21E, + 0xED02FCBA, 0x73320B99, 0xB55DE16B, 0x7F578129, 0x3F6FD052, + 0xF211A764, 0x9B7F9204, 0xC61EDC01, 0x1363AA4F, 0xEFAF1CF2, + 0xE5AF97EC, 0xEEAD4FB7, 0xF41B649, 0x373087FB, 0xE81355EB, + 0xE04FF410, 0xFD04F4F7, 0xFA269CEE, 0xBE8D7535, 0x5FC007DE, + 0xCF085F76, 0x94D7201F, 0xAF49F41D, 0x8D6E7F, 0x9D63B6ED, + 0x9A2A0877, 0xF06123D9, 0x6624C891, 0x508266E4, 0x6921EAA4, + 0xD6E69A49, 0xCDA0F920, 0xA5870B5E, 0x1A93A2CF, 0xE3A030C6, + 0x6EC03FE5, 0x37FDBDF6, 0xBEFD0BFF, 0x3D3CBD0E, 0x2DDBFD7D, + 0x8B58AE2B, 0xCAD61AF3, 0x624F4677, 0xC402CF5E, 0x431D2CC1, + 0x5C205AE5, 0xFC3B8ED4, 0x501C36DA, 0xBC9217E5, 0x6752573D, + 0x3BE702E, 0x8E06CF12, 0x81494C86, 0xB2DC2F63, 0x792EC845, + 0xC6BDEDB5, 0xB255BA4B, 0x6C66C28D, 0xD1A16904, 0x93ABFF21, + 0x94827FC4, 0x87825689, 0x314D1F33, 0xC0D8B98A, 0xC84AC57D, + 0xEBDB0F92, 0xBA4F473B, 0x61130498, 0xA534064B, 0x3DC04FBD, + 0xD0A701F2, 0xA671765D, 0x17464B7E, 0x4CCCB84, 0xC297BAED, + 0xAAF8C84A, 0x631313F, 0x8E0FD926, 0x1699F616, 0xD9808C9D, + 0x55BF5BC2, 0x27FD10B0, 0xAE975927, 0x92B3F52F, 0x9025C6B3, + 0x95E5E313, 0x4CB83334, 0xE4A1E7B8, 0x74F7D3D5, 0xDDDC42B9, + 0x5A89BEF1, 0xF66A6AE5, 0x33730C23, 0xEB7F079E, 0x742FEF19, + 0x2C68CAC5, 0x2410679F, 0x9D1632DA, 0x458F4AAD, 0x8889E6AE, + 0xA3B48216, 0xC9AF4AEC, 0xA506C8F6, 0xB6AF9E59, 0xC6340436, + 0xA6B294E, 0xF35CF92B, 0xEB3A4113, 0x98070AD1, 0x9E61E01E, + 0x58C2893A, 0xCC1F8C34, 0xCAD665A0, 0xD0414D39, 0x643BDCD8, + 0x8AF801AD, 0x9ADBB106, 0x2BD02351, 0x8F890436, 0x546747D0, + 0x6DC33C48, 0x95FA7FD6, 0x5F12C5A5, 0x5DF2761D, 0x9A9B2F8A, + 0x8C61276B, 0xACCC7F4, 0x37A5829D, 0xF1A0F1, 0xAAED57E0, + 0x180CD2A3, 0xDC393CA7, 0x504E7405, 0x89DE2F7, 0xA4D8C4EA, + 0xD8BECE01, 0xD664017C, 0xF57FA30, 0x6049928D, 0x9832E166, + 0x176AAC31, 0xA793F88A, 0xCFFA8B54, 0xA30DF1EF, 0x3B6C7611, + 0xDEFC961, 0x9BFB79F1, 0x1483D430, 0xC3A77C0C, 0x42AC1FA0, + 0xFA3605B6, 0x9A2EBDF0, 0x684D414E, 0xD9308E10, 0x64D68C19, + 0xA8A9B67B, 0xF5E7B9D4, 0xC7B70ACE, 0xA6EB6DB8, 0x8A22FBE2, + 0x3AFFDDA1, 0xFB61F7D5, 0xE057717B, 0x846D96CB, 0x20A4B400, + 0x574089BB, 0x9F3D2DBD, 0xEEDDDB4B, 0x5E64EA6B, 0x6781DC90, + 0xCFD86A6, 0xA92441CD, 0xAC5DCCD6, 0xE6BB5582, 0x32FA6B3F, + 0x3ABB8A64, 0xA49D2003, 0xA965E430, 0xEC4053BB, 0x95859D40, + 0x2672832, 0xCAC3E608, 0xF8C13A53, 0xB04EC2A3, 0x87F54941, + 0x62A3A924, 0xE0B48702, 0xE8700446, 0x95BD4B11, 0xCFCFDF9A, + 0x19F67E7D, 0x60853AC6, 0x468F963, 0x298066B9, 0xEE53E89A, + 0xFC63E607, 0x6FA101E5, 0x8B2F1F84, 0x24AE7C1C, 0x385008FF, + 0x96E75EB6, 0xF1175277, 0xE5B4A577, 0xB0C97AC, 0xC21CC45A, + 0x5C680DF8, 0xDEB046DC, 0x1487FC03, 0x1D90CE3C, 0x712563BF, + 0x65A26CD9, 0x4D094F62, 0xB5DFE29C, 0xF58B2A62, 0x9420A9DC, + 0xCEC7537F, 0xC46D1FCA, 0xAD5D7B10, 0x68777A24, 0x6C096D2, + 0xD787D72, 0xC7743F50, 0xB3D05F4D, 0x53E0A7E3, 0x9E627C6D, + 0x1AA0959F, 0xD1E00E47, 0x8874BA26, 0xCEAC0958, 0x10F67BBD, + 0x712C6597, 0x3478BD73, 0x4D6F116, 0xD30BC24B, 0xB98C565A, + 0xD7C5B116, 0xA8CDAC4F, 0x4144673, 0x848F37E3, 0xADD946EE, + 0x6F17EAE3, 0xEA0FA265, 0x41DB99E0, 0x6BCFDA5A, 0xB46ECED5, + 0xAF67610E, 0xC7E9DF2C, 0x5CC6F0C6, 0xAB2C2BA, 0x6BCC3881, + 0xE482C243, 0xD8053417, 0xFFDB6E41, 0xF13EEB84, 0xE8292661, + 0xEB9940A6, 0xF0B45F98, 0x1CA82AF4, 0xCCA7771D, 0xDD5F3CFE, + 0x58BD8E91, 0xDF9E3342, 0xA1003957, 0x4621AF52, 0xF926F465, + 0x209925AD, 0xB1C72F09, 0x3FAB8ED, 0xA15C0A17, 0xDBE73D2C, + 0xF917CE51, 0xED047661, 0x7361B752, 0x1AAA57A8, 0x31445667, + 0xFEC0FD81, 0xE3073574, 0x7D36F720, 0xF418181A, 0x1CB8758E, + 0x8E85AFBA, 0x407E9AD9, 0xF724E308, 0xD030D3ED, 0x4610418E, + 0xE799EA4D, 0xF8B68F92, 0xB84B9ACD, 0x4B8168C0, 0x9888977, + 0x216F3B3E, 0x5C49C1DB, 0x759E718D, 0x7C4309FF, 0xBF6DEE2C, + 0xE566F231, 0x774B0A7A, 0xBE55CCFF, 0x3081B8CD, 0x2284369E, + 0x2FDF7473, 0x3AF68AC7, 0x6047E9B8, 0x3743BA0E, 0x691D261, + 0xADC440E1, 0x24150207, 0xFBFE466C, 0xF767E860, 0x8157332E, + 0xFB54D774, 0x1AF34C22, 0x74E05695, 0x2101FD57, 0x2904274C, + 0xA1294E9A, 0xF43CA18F, 0x4FA79EB5, 0xAFD1C9EE, 0x6EB3953F, + 0xDDFCB3AA, 0xDB48F7BA, 0xE1742183, 0x8A78CEBD, 0x225CD669, + 0xD76B771A, 0x3520113, 0x428B2892, 0x3A5CE8DD, 0xAB4AC42C, + 0x2928BE8D, 0xC34E3031, 0x93F0CB9B, 0xB7A6FDB4, 0xEEB2B85E, + 0xC393597B, 0x9D8457EF, 0x91F0F0FA, 0xC54AEA3C, 0xC639521, + 0xB668AFE4, 0xE4CCE3CD, 0x86223A5D, 0x6A51A2EB, 0x4333C505, + 0x3233B8B7, 0x1D01F51E, 0xF0C691A6, 0x699EBC2C, 0x7FEE8DBC, + 0xCC50E42A, 0x7951DB68, 0x8CF01752, 0x33D33841, 0xB46E353A, + 0x700B65B, 0x59ACA844, 0x38631893, 0xC32D0F92, 0x6897EFDD, + 0x3F93BCDD, 0xD50E33C3, 0xD0075F1D, 0xB3CB6096, 0x875896CB, + 0x5DF6651, 0x8E2D197F, 0xCDF68F10, 0xC74018CE, 0x83E6C42A, + 0x994DEA76, 0xF932D8AF, 0x98775C2D, 0xF79CAAE5, 0xF2BEB839, + 0x7318C6DB, 0x3AFD6D85, 0x37F18BDF, 0x10194867, 0xA73B5205, + 0x3F06A1BD, 0xBC8026DF, 0x531CF753, 0xCAFAED74, 0x817C9E70, + 0x32338A3F, 0xA5177C74, 0x9A3C131F, 0x90F9AF0, 0xE9281B62, + 0xEDD87C1E, 0x16577CB0, 0x5E3F7AC3, 0x4E49E1EA, 0x495C1B67, + 0xC282F5FE, 0xF8993B1, 0x47563C68, 0x49FA0716, 0x26A55B80, + 0xDF870F8D, 0xFBB8DDA5, 0x130EA4E3, 0xB0B66F1A, 0xD7B92F0F, + 0x55FD4759, 0x6D11AC86, 0x8AB0B6F8, 0xD8C8C8B0, 0x758DA8A, + 0x9CD589F, 0xB808C0A0, 0xB2C7A3F3, 0xBA40DA44, 0x937532CF, + 0x279CFDB2, 0x545896EA, 0x387A8F38, 0xB2E5F9D0, 0x7566CA0D, + 0x51B45DC4, 0xA93B6EAE, 0x1C22D8D5, 0xEB96BD1D, 0xB8F40750, + 0xCB7DCF85, 0x188F6018, 0x95BA817E, 0xF7C19E4E, 0xAAF97DDA, + 0xE5BD967B, 0x1604352F, 0x3758C3BB, 0xE2FA13D1, 0xE3666F4E, + 0x218059EA, 0x2F4750EA, 0x2F065B46, 0x8FC4F43F, 0x2F45422F, + 0x45928A5E, 0x77055776, 0xBB8103E1, 0x160EFF29, 0xA704F79B, + 0x6655E735, 0x2C19DC79, 0xE407A7CD, 0x9F4AE1F0, 0xBED7DCE5, + 0xA870A304, 0xDC413709, 0x903181E, 0x7C1F6803, 0x44971A01, + 0xF7A81ED1, 0x5DDFB023, 0x2D90CFBB, 0x7F7A432A, 0x35F3F5B0, + 0x7D935FC5, 0x1D99E7BB, 0x8EFC82B0, 0xAB0DEF56, 0x70702FA1, + 0xCF0064DF, 0xDD9DEAA9, 0xF05F927B, 0xB483A6DD, 0x9B7388B8, + 0x2FD82389, 0xAC982F20, 0xC86AD76F, 0x15C6977C, 0xAB10A137, + 0x1433E4A0, 0x2762D44, 0x1CB5399B, 0x310A54D8, 0xD4B8623A, + 0x40FAB5F3, 0xC2D51618, 0xC1F4AF55, 0x17C18E1C, 0x4F37D33F, + 0x2DC9F168, 0xF5BB9754, 0x716FB1F4, 0x7CFB1CE8, 0x1333224D, + 0x344C13B3, 0x7798CB50, 0xB4278C76, 0xD7CC1B03, 0x168B21E5, + 0xF7D77AAB, 0x3B651846, 0x639EB0CD, 0x68EB3E8B, 0xEC82FE45, + 0x622A71DE, 0xAA05B6CB, 0x878B59B1, 0x3E7FB616, 0x1D650408, + 0xF21F8C64, 0x9BF7BF7A, 0xA0874898, 0xFE4E3C6E, 0xFA36122E, + 0x1BCDF4FB, 0xC371B365, 0x8F791BB3, 0x9833AD98, 0xE84887FC, + 0xF8988AB6, 0x180916E2, 0xB587E39C, 0xD5C884C6, 0x27B6BFEB, + 0xD8868D1E, 0x689DA503, 0x936B4EFC, 0xDE0DB3C, 0x7950FDCB, + 0xA61C81C5, 0x9F1C93B2, 0xC983179A, 0x6F847EB0, 0x6F7F899D, + 0xD270412, 0xCC255717, 0x763112A0, 0x8725C96D, 0x48BC2863, + 0x85F13BF0, 0x6D8E0251, 0xB7E66CC3, 0xA4F5829F, 0x8779F381, + 0x16A5E04F, 0x3DF42C14, 0x367F06A3, 0x3BF8666C, 0xC6649CFB, + 0x4DD9808F, 0xB4F9AFD, 0xC2642410, 0x9740E4F6, 0x8FB667BE, + 0x4D4B0D3E, 0xE9B236F7, 0x6E30550C, 0x79DA7B48, 0xE721889D, + 0x79D9B21A, 0xA06B8C2E, 0x997B1696, 0x4383FC27, 0x8B77D293, + 0x6FAE2A9F, 0xB45ED194, 0xF38E2C59, 0xEAA0D05C, 0xA3BC449A, + 0x6EB0BB4B, 0x6B242CFF, 0x7FCA0B8A, 0x47221D33, 0x4E18FE39, + 0xF4691580, 0x6D03D791, 0x3B937AC5, 0x9CB761C3, 0x42812232, + 0xFB987D6C, 0x86AD164E, 0x5D8CED49, 0x22D6D058, 0x42FADF98, + 0x9363A1B3, 0x83C6DB74, 0x7AF44F4E, 0x20086D60, 0x7A37665E, + 0xC4A29C82, 0x330F278B, 0x8750B539, 0xDD2E83D0, 0xB8E002B1, + 0xF2A9323F, 0x91B60885, 0xDE83F01D, 0xACA126, 0x2F0FADA2, + 0xC0E879A6, 0x7C715655, 0x16642BA2, 0x43B9C083, 0x95F6789D, + 0xE6576886, 0x46BEF133, 0x84199FC3, 0xC45BA082, 0x26489AC1, + 0xA4FE268A, 0x633A25B0, 0x4FCD341D, 0x8E7374B3, 0x7F8A3466, + 0xC82B53F7, 0x2E2114DC, 0x59213BE7, 0xE72A2395, 0xAC5F982B, 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0xE9D2DD1A, 0x78DA23CE, 0xCADBA5C9, 0x77015761, + 0xF5581BDF, 0xDEB4DAA0, 0xAF7E41B0, 0x71347196, 0xF8A29A93, + 0x8DA3BAE6, 0x73396AAD, 0xD4DF7765, 0x326AFF23, 0x27888A0C, + 0xE48AC062, 0xB9F18047, 0xDE9830DA, 0x8EF78C4D, 0xFBC1896E, + 0x9BB566A6, 0xB640ED13, 0x8B0D9D1E, 0xD84B471D, 0x4040EFB4, + 0xF6DF7908, 0xCB8ACF04, 0x253494DD, 0xA85F6D88, 0x1326822, + 0x61EFDFB8, 0x1C78154F, 0xB13866B1, 0x3ABE5DBB, 0xBB5907BF, + 0xA1A57FDF, 0x410549C8, 0xA9A364F4, 0x2A371B73, 0x24AC7296, + 0xA01C035C, 0xE839029C, 0x6E12051E, 0xE6A549FD, 0x345F10FF, + 0x3BB57347, 0xBDBF3A6A, 0x2A41C3C8, 0x6E0232B0, 0xAE66D42E, + 0x3BE90433, 0xE185FBF2, 0x9BCA91FE, 0xF4FFB74E, 0x142B6971, + 0xA75CD7B, 0x9B900DDD, 0xEC56B79, 0x2FE0CD8D, 0x87BE8237, + 0xB38A7226, 0xB5D8B437, 0xAAADC41D, 0x8014E227, 0x38D84DD1, + 0xEDF5294F, 0x862F0F, 0xD69F77F6, 0x409C3B68, 0x2F12B0FC, + 0x32A670B9, 0x5746EE2, 0x96B4901A, 0x57208639, 0xA282A77D, + 0xE9D9F48E, 0x651ADDA6, 0xFF5E974C, 0x37C833C, 0x41F2BD58, + 0xDFE1D009, 0x32222DA6, 0x22201781, 0x64A06BAF, 0x8F188902, + 0xA9C2A07B, 0x617C7DF7, 0x842DA704, 0x40AFDB72, 0x49625110, + 0x72484F13, 0x7340AC89, 0x6C6A2F36, 0x828EF5F9, 0x20344923, + 0x21D3304F, 0xD6EEB7C3, 0x8F99732F, 0xEBA045D5, 0x5C0065D4, + 0xEEB5E899, 0x1B079C47, 0x6198EE3B, 0x946A805F, 0x7C19F966, + 0x75E8F043, 0xFD9880BE, 0x47BF619, 0x9C001ADB, 0x7438184B, + 0xA3787EF2, 0xA461EF4E, 0xEB515D0E, 0x64EFA69D, 0xD41F3145, + 0xD08A900B, 0x495968AC, 0x746639C9, 0x43E85DCB, 0x62E55B3, + 0x6B913D8E, 0x2685D73B, 0xE4F98C19, 0xB404BD4B, 0xFEA327C5, + 0x1E0CC908, 0x71BC53EA, 0x530AAECB, 0xBD2977B, 0xB661A52, + 0x86560EE2, 0x250E2591, 0xDA57D5B3, 0x347D3C22, 0x6CE15221, + 0x6E5288EB, 0xA79875F3, 0xCA89972F, 0x36E93777, 0x257262E1, + 0xD1D4E5A4, 0xF7ED5D52, 0xECE58036, 0x644ACA69, 0xCA36DFB8, + 0x60EAB44D, 0x46FB8AB3, 0x81E6C199, 0xD5AA5C63, 0x4A7CB01D, + 0xFCC109CD, 0xD999C46B, 0x3FA4C688, 0xC95C0FBE, 0xA1E9DD3, + 0xBE9EAEF6, 0x1A3014D7, 0x729A662, 0xDC8178FD, 0x7FCAA1EF, + 0xD4005420, 0x2A904DAD, 0xEE7E52DB, 0x886C0F23, 0x12D49E10, + 0x2B3F3B39, 0x3373A6C6, 0x5D0759F5, 0x8CF5EF25, 0xCE02371C, + 0x2FFEEFDE, 0x5D9CFD69, 0x2B5BB7D0, 0x5A378EA9, 0x5BED8331, + 0x9C1A37CA, 0x702799F, 0x4D37A8EB, 0x370CEDF8, 0x43B95BE0, + 0xA0C1E534, 0x204130B2, 0x8E4995AC, 0xCF1C3C28, 0x3E901F78, + 0xB0F43C57, 0xED4B7492, 0xABD3C5CD, 0xEA95ABC4, 0xE03B739A, + 0x58388E80, 0xFDF22044, 0xF4379C7E, 0x87CFA0C, 0xAE9CA79E, + 0x41DCB004, 0x8F69512D, 0x73ED4756, 0xE215297A, 0xD931A6AD, + 0x59866B3D, 0x61825B1D, 0x4F5099E1, 0x25AE168B, 0x1272D5C6, + 0xBE071035, 0x24314F71, 0x82F4B23F, 0x6C7F3385, 0x36CF0505, + 0xB71C0E3D, 0xE9F881D0, 0x27F0C290, 0xF4BE30D7, 0x88315CE8, + 0x9E04FD20, 0xDE197591, 0xCF0D2FF4, 0x67A4C473, 0x158447BF, + 0xA4B37C88, 0x27918292, 0x5FDE3DF0, 0xE8A93C3D, 0x886287E8, + 0x746E199B, 0x9A894103, 0x7A529374, 0xA195E2AF, 0xAA3EB0C6, + 0xF70788A9, 0xCE2B7F30, 0x9C4724AA, 0x902EB7A8, 0x2CBBB407, + 0x3799651F, 0x9016E9D0, 0xD1C0ABC8, 0xC7684FDD, 0xE4670051, + 0x25B69E83, 0x1CEC9BBF, 0xD066D2B4, 0x2AD4BF14, 0x7AFBD3CF, + 0xCB8E5EFA, 0x63B67572, 0x89F7E3F3, 0x8E8D39E6, 0x60617ECD, + 0x9EECEA31, 0x59E57FAB, 0x807AFCD6, 0xFD0397B8, 0x3C57D963, + 0x9A972CF5, 0xFC47B628, 0x9CCFAA8B, 0x405869C3, 0x3CC128C1, + 0xE154C33E, 0xBE53F87D, 0xD23C7947, 0x4CBEB3BB, 0x1F068FFA, + 0x8A7D350A, 0xB822F33E, 0xFB3BB431, 0x741D2D0F, 0x81FAFE09, + 0x80B8BA3C, 0x30B4BE94, 0x4B2A2909, 0x31740925, 0xE68C0BC9, + 0x8E7F31D4, 0x29DA2599, 0xB9D267C9, 0xEDE811D2, 0x8BC7CBC3, + 0x69DDA8B6, 0x879E1212, 0xF915F0F1, 0xBBCDB1AD, 0x3A01011A, + 0x7CD005C4, 0x475FC718, 0xF03F454B, 0x7457F264, 0xB22D9DFD, + 0x569DE931, 0xB585EFEB, 0x9A183445, 0x9CB353AC, 0xE3AA9817, + 0x32E0722, 0xF0C7595E, 0x316DBD6A, 0x96D0F65C, 0xA6F0ECCE, + 0xCB8A9494, 0x5B077241, 0xD36BBC7, 0x9C4CD0F9, 0x108F5B32, + 0xC43C599A, 0x7B10108A, 0xA4106EE9, 0x3860CF99, 0x87B782C, + 0xF667524C, 0x129929C, 0xEA85C1D5, 0x1A07973E, 0xB9524891, + 0xBC02BD1F, 0xF378D7F, 0xD0BED4D7, 0x5B782DE2, 0x738681A, + 0x4BA1192C, 0x46DF1224, 0x4529AED7, 0x9B1DB01D, 0x810AA334, + 0x661982C8, 0xD3B32F94, 0xF50AC9D6, 0xCE9107C4, 0x203078BF, + 0x6B0F3B2B, 0xCF63520C, 0xACA9E5BF, 0x7FBE448E, 0x51BD1E2F, + 0xDF958295, 0x114A9693, 0x60FCBB39, 0x6669B642, 0xC490D54, + 0xD19C8DBC, 0x14CC7B2A, 0x7106D506, 0xAFDADD98, 0xAF398DF4, + 0x88AC5400, 0x1912BF0A, 0x5389D050, 0x5AF6233, 0xF10842A3, + 0x94DD7008, 0x93812804, 0xD8111DFD, 0xB7C97490, 0x7748A45E, + 0xE70A47A0, 0xC29B718E, 0x55783AEC, 0xA2789E21, 0x97488EBC, + 0xD9222F6A, 0xBF74BDD2, 0x9A983E5C, 0x6CC067D5, 0xBCFDD3B2, + 0xD7A2A5FE, 0x4733F2F5, 0xC7AA3556, 0x1CDB485D, 0x31755CA0, + 0xB9F8E9A7, 0x1346410D, 0x7D885AD7, 0xA30030D8, 0x9813B41C, + 0x8A64EFD4, 0x273F4CED, 0xFEDDC3FD, 0xF34D9687, 0x6B67F2DC, + 0x13F72B5A, 0x96445DDB, 0xAC94658B, 0x8FBF54BC, 0xA7C13389, + 0x95814EA3, 0x7823E5BC, 0x544C27DB, 0xECE6439B, 0xD1141B27, + 0x7A95ACF4, 0x806E58E7, 0xD07B5422, 0xFD0353AE, 0xC1840431, + 0x1DD89E9, 0xA102016D, 0x3730505, 0x1F91E46A, 0x3279C793, + 0xA060010D, 0x9BF86C80, 0xD0C35484, 0x33E81EF7, 0x1C4D3EA7, + 0x6C2A9935, 0xD65E2FB1, 0xBB1CA42E, 0xEA3E3609, 0x7B478C84, + 0x70C1DF93, 0xA872CA92, 0x7C025178, 0xF3B19C7D, 0x6F2BD89B, + 0x1AD7BBDC, 0x39A48FCC, 0xAB5B72E1, 0x821761B9, 0xD2368C1, + 0x20ABB349, 0x29A3F960, 0xFDB18DF1, 0xC4118A52, 0x5E28E88A, + 0x549A3386, 0xD81024CE, 0x82DAD5E0, 0xB20BCD42, 0x9DEA0D36, + 0x49A4992D, 0xAFCB2026, 0xCE7536E8, 0x2C191A65, 0x24FEE0D6, + 0xA769AB6D, 0xF47E292E, 0xCB501191, 0x6DE13907, 0xF1343277, + 0xB32AA746, 0xB055DB9E, 0x87CB8583, 0xA546A4C3, 0xF06F809C, + 0x8FE7A8AA, 0xD0E4037F, 0xD81FCF88, 0xF85830C2, 0x3D6F4840, + 0x5A43700E, 0xCD300C58, 0x3B81C27C, 0x8AF86EA8, 0xF65935FC, + 0x46367D7, 0x7FB75E63, 0xBB28A406, 0x173F982, 0xCB92DD14, + 0xAAA0B1D1, 0x1BCA8892, 0x64D21, 0xFF081A44, 0x8706E93B, + 0xB7DEFAD9, 0x4A6DEF76, 0xDA1670DF, 0x94ABCEBA, 0x465DA4C6, + 0x2484496C, 0x97BB3321, 0xEFB09CB, 0x2988AA2E, 0x2722344E, + 0x5301B744, 0xC5E16C47, 0xF7E05D01, 0xCBE7C20F, 0x4882A6EA, + 0x7168CF40, 0xA98A2747, 0x35F8E15A, 0x5FAF49F9, 0xD2008D24, + 0xCC45A63, 0x858A3255, 0xE4C095B6, 0x7074F7A5, 0x699C98FD, + 0xF0BFE2EA, 0xBDA35C64, 0xE83B891D, 0x7CD09FEA, 0xE8735FDD, + 0xFEA27F06, 0x631D71D3, 0xA08136CD, 0x42395363, 0xDCBA6E41, + 0x1562897, 0x4B1061A9, 0xB4F9640B, 0x38D24E3E, 0x76DF4423, + 0x94B5ED97, 0xFE6AB3B6, 0x6B329B8B, 0x37AFD275, 0xC9ABA12A, + 0xEC9693B, 0xD49B5585, 0xE0C2BEF7, 0x315D40A8, 0x34FBE3A, + 0xEBE81550, 0x569F6FC8, 0x5A9C8404, 0x9DBA0090, 0xFE985DE8, + 0xFF4209AE, 0x89F9E7AF, 0xF841164C, 0x6B4B8F5D, 0x95CB1085, + 0x1990660C, 0x31263B36, 0xCF8F435C, 0xDEBCF88A, 0xD1EE25C2, + 0x53D80B69, 0x9EB8F01C, 0xD682EA3C, 0xEEE79205, 0xA7EFAC65, + 0xE9AA6899, 0x3C1E197E, 0xC8ABE1E9, 0x7BEFE9CA, 0xE792E7D4, + 0xA955D60F, 0x3FE8A02F, 0xC963FDC1, 0xB3D53E43, 0xE28FFC12, + 0x7D5BECCC, 0x18E9F223, 0xBC8B0465, 0x7ED8EEFE, 0xBB90FFEE, + 0x904A9F3A, 0xBC467FF, 0x8AD43A15, 0xF3FC404A, 0x2492D5F4, + 0xBB3F5025, 0xBED0B8BF, 0x467FE6C2, 0x36E55C77, 0x8E2CAC4F, + 0xD12D325F, 0x68A4D268, 0xB1AA0895, 0x755B98FC, 0x2314C4FF, + 0xC3667346, 0x8003B9E8, 0x1185476D, 0x227B69D8, 0x5BADD019, + 0xB06567BF, 0x2B837581, 0x9E11F7, 0x158E67AE, 0x339AA6FC, + 0x8FE50AD9, 0x65902A97, 0x42917220, 0xF9AD39C, 0x2DAAD225, + 0x9673B896, 0xFAE150D6, 0xBEDE3417, 0xD233D722, 0x7E67F33C, + 0x6E150E30, 0xC856792A, 0x28EF69BA, 0xE2AC7866, 0x928D0A4A, + 0x8032C4A9, 0x3D413533, 0xC1BA5CCA, 0xD2BDAC83, 0x94198A14, + 0x3A25972F, 0x253EC030, 0x42D7A1F5, 0x97C28C1C, 0xBE4D0710, + 0x92F31B62, 0x73CA2F55, 0x15FC5417, 0xEF76B1C6, 0x655A963D, + 0xBC17C3FD, 0xD5BED3BC, 0xAB0E4857, 0x38BAD61A, 0x8C17E47F, + 0xE3C27887, 0x45D2A34, 0x6D48333A, 0xF400B767, 0x6ACF41B0, + 0x88DA15A9, 0x3FA0EAB1, 0xAF7B3786, 0x87F182FF, 0x4112A079, + 0x53360864, 0xDB5CE625, 0x630678D7, 0x63E01F17, 0x7BF658F1, + 0xB5E4F1A3, 0xB30E4393, 0x27454C31, 0x8E7E0E2, 0x2151A5F, + 0x2892E2B2, 0x92B53840, 0x1EB3D483, 0xA4273A65, 0xF0CC632, + 0x99AC2694, 0xE0A19111, 0xC7FBA613, 0x46C8F873, 0x88A27741, + 0x7E9A5972, 0xC2E76F79, 0xA5CA8180, 0xA28FF0EE, 0x2A1F7DE1, + 0xCC130B22, 0x50ECFD8A, 0xF5BAA999, 0x5FA2EC9C, 0xC1B5C5C4, + 0x90EC0E5D, 0x9C26620A, 0xA97D2935, 0xE1C08B89, 0xCB574B80, + 0xB3DE8B61, 0x1AF89CA0, 0xFD4A77DC, 0xED9485E1, 0xAF804C92, + 0x6B8EB167, 0xDCC836B6, 0x85A7FFFD, 0xD4E9A94A, 0x77DDCC31, + 0x8897B5F9, 0xA4FA88D3, 0x8ECB3E82, 0xBC175E89, 0x963A073E, + 0x547520C7, 0xEEB81BFB, 0x1D8B1867, 0x78833A4, 0xE40A0CCB, + 0xF8D5452F, 0x954BDCF6, 0xAC228FFA, 0xE6B32DF3, 0x181ED541, + 0xACE26A73, 0xF1C1440D, 0xA1B93EDD, 0xE90FF70A, 0xF6741843, + 0x4DF581AC, 0xBE785B32, 0x751509B5, 0xC30AD864, 0xC18D8A72, + 0x3BF07FD4, 0x827B4CBA, 0x7DD39A4F, 0x2CFEFE25, 0xE071F371, + 0xC0C3F6CB, 0x1FD70F85, 0xFDABDA88, 0x8F308991, 0x4CD794F9, + 0x5D18B022, 0xC13D5FC2, 0xD84337F, 0xED868BB8, 0x9904CD2, + 0x7551499C, 0x124B262, 0x5139C2A5, 0xEF56F59B, 0xE8B87B40, + 0x2F030010, 0x42D2E271, 0x4E344F3F, 0xC87CDFE1, 0x44A615C7, + 0xC32DB543, 0xCFC889E4, 0x60078825, 0x786F5917, 0x2DF9E82, + 0xEE26DA93, 0x48D0C94, 0xE97D5456, 0xF487F2EB, 0x35A47D65, + 0x183DA0CA, 0x1A7E1218, 0x8D2674C5, 0xB38D0910, 0x5D9C871C, + 0x7B463ED1, 0xBBC90FFD, 0x31DED99F, 0x5171DCFA, 0xF9413D0B, + 0x632A00FD, 0x7B6DA34C, 0xA475C597, 0x8E157360, 0x5911736B, + 0xCA19D544, 0xF487D465, 0x6E749BB9, 0x888BFB52, 0x3FDAD497, + 0xDB5D401A, 0x7015A4EC, 0xC1F571, 0xB2D7671A, 0x8203032F, + 0x5A755E9, 0x24F25BF5, 0x4D2AC51B, 0xE5950FA7, 0x20196F5B, + 0x68E90D90, 0x5D24196C, 0x9CFCD1C0, 0x745C0318, 0xEEB977E8, + 0x14AA16D, 0x80662EE1, 0x7BD55DE3, 0x35EE2B08, 0xD3E8051F, + 0x3D0EA4B5, 0xD551399E, 0x8FF94435, 0xDD4E34ED, 0x9139E4A3, + 0xE6AF7E5E, 0xE1ED4EAF, 0x638D2846, 0x7084F7EB, 0xF9705E17, + 0x2E7A89DC, 0x45855252, 0xBA8E51C7, 0x8510425C, 0xA97AF6D, + 0xF0C27DA, 0x9E00CA15, 0x3BCC0651, 0xEEC38CA9, 0x19597B08, + 0x4C68AB5D, 0x16CA41DB, 0x35EFBEF9, 0x1E441529, 0x25131FA1, + 0xC3D8483C, 0xD8650832, 0x60D271E3, 0x47C92A47, 0x9EFBB554, + 0xBF5DBFBF, 0xFF421FA2, 0x3A38F28, 0xAE4EE06B, 0x819945D1, + 0xC43101, 0xA3EE9278, 0x5BAE3EE4, 0x57ACE55E, 0xC3D95551, + 0xC00717B0, 0x38EC1B28, 0x123597, 0x6314F3F7, 0xB3F99DAB, + 0x7226CE1E, 0xE8350DE6, 0xD7C582CA, 0xBB1D38D, 0x54E656FE, + 0x400B60BD, 0x48291A06, 0x97819179, 0x850BF937, 0x93888A87, + 0xF51E684F, 0x4B111E, 0xC6B37E02, 0x6C923547, 0xEF25AF3B, + 0x8C12CE8E, 0x89296F4F, 0x3BE2C3DA, 0x8A29A35B, 0xBBE2E80C, + 0x79D0188D, 0xBD4320BC, 0xAFF4F0A9, 0x7FAE6C37, 0xCCA1777E, + 0xB06D2AE1, 0x26B6398C, 0x5A3E5876, 0xE814DF4E, 0xC43E9677, + 0x4C962CE8, 0x6C274FF8, 0x8B5A1A03, 0x963E1401, 0xD8CE0DF7, + 0x659190E7, 0x3AD63330, 0x894BFEDB, 0xEB4CF73A, 0x3731BC86, + 0x30FE0433, 0x94F5FD2, 0x8417999C, 0x337E86B8, 0xAFE08EF6, + 0x5B5F05DC, 0x8001C95F, 0x8C8092DC, 0x5EBC7995, 0xDCBE88EE, + 0x9C602950, 0xE3376596, 0x5D80E318, 0xAF3AC8C3, 0x8C7EDCC6, + 0x3E795E7, 0xDA8987AB, 0x7B7B4E3C, 0x3239CD40, 0x1B527DED, + 0xC95DEF29, 0xE40D047D, 0xE53C10C5, 0x5BAF528B, 0xA47921F9, + 0x6DCB9B0A, 0x7EA11040, 0xBBEFCCD5, 0x502F33FA, 0xAB5EBE8F, + 0xD59C448, 0x8C34FF3D, 0x4A3255A2, 0x4CFFDCB1, 0x3880A182, + 0x3499DAAF, 0xA1319450, 0xC550CCE5, 0x51026E2C, 0x73C4F05D, + 0x21F5FAAC, 0xE1C31B7D, 0xA390E6E6, 0x7B1582ED, 0xB92B4C3B, + 0x41C1128E, 0xF728F655, 0x3BC8AE16, 0x8A2A4E57, 0x9A8A7DE, + 0x86065598, 0x4328A574, 0xDBDAFC7D, 0x2C5EE98, 0xEAB5CE80, + 0xF7E8F60C, 0x7B4C3C0E, 0xE4A2F720, 0x90330B1D, 0xB6783BF2, + 0x48A8C26B, 0x847F1AAC, 0x351DB247, 0x43E84AC5, 0xAF726AA3, + 0x5CB4C059, 0x2C5784DE, 0xBA1111FB, 0x9F427968, 0xE41D29D1, + 0x2CAA8CA7, 0x764C8B63, 0xBDAA6F10, 0x280277B6, 0xE4A908B6, + 0xA6A9783, 0xD0643B01, 0x44FE52AD, 0x60B04A5, 0x194C190E, + 0xF73DA669, 0x12EE11C8, 0x2C769D96, 0x694787A4, 0x9FB03623, + 0xAC6F837C, 0xFC1E5935, 0x16246787, 0x4F94B817, 0xA3A4281F, + 0x1535252D, 0x13F8F1CB, 0xAAF6A508, 0xB38E10E, 0x7A4B238, + 0xC6A47410, 0xC864256, 0xF3C25E27, 0x94CE51D4, 0xF4ECAEEA, + 0x32684D74, 0x1AC8765, 0xDE6F6313, 0xF8C09409, 0xFB21FD21, + 0x6DB586BA, 0x241894B5, 0x65806E1F, 0x4B9D0DE7, 0x32DDDD16, + 0x3B16F0B0, 0xB56CAAF0, 0xC533ED5C, 0xADE48431, 0xB5893123, + 0xE977699C, 0xB295808B, 0x7A252898, 0xE3748392, 0x687A8ACD, + 0xB792504E, 0xBF4E2D8A, 0xB5EC4376, 0x754D9C34, 0x17BE53CC, + 0xC817A127, 0x732346E2, 0x29593976, 0x41D6AF89, 0x9072FAEC, + 0xC2B22666, 0x16A150DF, 0x4D379A36, 0xE732017F, 0xA6D12516, + 0xEA3DB9B5, 0x6E4C766B, 0xCA0ADEF5, 0x75E98F68, 0xC31687C3, + 0x62F16F66, 0x6486B129, 0xE237231B, 0xC6653007, 0x2BE06DFC, + 0x2BC32DC4, 0x9E3DD054, 0x47AA701E, 0x7741E537, 0xA09F9CD8, + 0x9D40881, 0x4F02F58, 0x6A5F31BB, 0x32BBBD23, 0x4520EB05, + 0x1DBFDD00, 0x6CCEC7D, 0x48CFC70C, 0xB41FBC13, 0x5B377E90, + 0x3B87923D, 0xC09F6D28, 0xC1CF24FB, 0xDD6BE459, 0x8B8BDD37, + 0xF7B103C8, 0xC1611360, 0xA8B8FCC8, 0xC16D4E2, 0x6AD23606, + 0x951A051, 0x6FC3B984, 0x95876867, 0xA0E1A04C, 0x8267F62C, + 0xC4B69588, 0xF53421DF, 0xC348685B, 0x59769E2B, 0x21F0FF90, + 0x2B978BB4, 0x3FDA987B, 0x216F4FFF, 0x95C68589, 0x2286F5D8, + 0x81E2702D, 0x88E2D01F, 0xE6F6B356, 0x2EA0C31, 0xA5E11CAF, + 0xE17DC578, 0x2115A0EA, 0x8DC2B323, 0xEB86957, 0xF3C7BECB, + 0xBCD805EC, 0x1121C3F5, 0xE6DEF224, 0x8EA2EE24, 0x2703D7B7, + 0x24D73574, 0x4068552C, 0xA85F5B6A, 0x65B563E, 0x4050954C, + 0xC7043820, 0x91E4A088, 0x19084C84, 0x7250FB54, 0xC1EC72, + 0x9FDB2412, 0x3B78E4E9, 0x588C2D17, 0x345C3232, 0xBC7CCB29, + 0xCB5F1F0A, 0x24EDD656, 0x7A9F0605, 0xC2EDB0E5, 0x7F01D20D, + 0x8EB211A2, 0x74AC4C1A, 0x37EDEDDB, 0x55B9AFF2, 0x100C4193, + 0x43CDF2C3, 0x9C75E7C1, 0xC43ABEFF, 0xB9704827, 0xDD4E6376, + 0xEA5FA0D3, 0xC6E14A66, 0xCB163673, 0x9515389, 0x5D3D30C5, + 0xD1FF8777, 0xC1347921, 0x21A5BAC, 0xD6CB5F87, 0xC6CE680B, + 0x46D1E5FB, 0x9B98BC15, 0x8D1446D6, 0x184659E7, 0xAAC79D5A, + 0x773E019E, 0xA1B9F814, 0x933D3D0B, 0x11DB7615, 0xC206A22A, + 0xE4EF5BA1, 0xF0EFA194, 0xDE0E6C2B, 0xBE185B42, 0xC28FDE0C, + 0xE416DD8A, 0xC636753F, 0xAFD119E, 0xB0198B17, 0x94C4115C, + 0x76EDF82A, 0x66818700, 0x6F003485, 0x993DFB2B, 0xF5A1F91E, + 0xDAB0080C, 0x7DF290D2, 0x72F65E9B, 0xBC126473, 0xF6050B10, + 0xB7380CA, 0x3352530, 0x9A403054, 0xB12581C1, 0x6F8E0370, + 0xBB5C1ED1, 0xCE738AFF, 0xE9F605DB, 0xA976BFE4, 0x68C9D107, + 0xA2BD1833, 0x545ACCE2, 0x965FBAF, 0x12D998F, 0x2C16B1CD, + 0xB20788BF, 0x96AADE36, 0xDF821415, 0xF1EBD654, 0x33F3C413, + 0xF2F2A6BF, 0x2DFB0ABA, 0x96845EC5, 0xB24622DD, 0xA83EEE5F, + 0x49DF9AF8, 0xB8DCFB8A, 0x16F7643, 0x436EFD30, 0xD90C9F8, + 0x9C10CD4E, 0x600CB15B, 0xE686606A, 0x5EC0502C, 0x23B2DCE5, + 0xDD5DE18D, 0x235A755C, 0xCB58A693, 0xACBEAFDE, 0xCA201FB5, + 0x2AE90380, 0x4F7455EC, 0xCA923312, 0x1BD202DD, 0x2D92B9E3, + 0xA2670F18, 0x831728C, 0x77D33D8C, 0x12400BDA, 0x9508A626, + 0x9253042B, 0x63C70C8C, 0x5496452F, 0x9237D610, 0x10448F3A, + 0x9303C709, 0x660D7EC, 0xDF6750F0, 0xBC4F14F2, 0x8F59720C, + 0xEE5AB051, 0xD5EC1228, 0xCC3E04CE, 0xE9E4D3B9, 0x8676FA58, + 0xF523860E, 0xF87D9BED, 0x4A6D02C9, 0xC5AD6CF0, 0x65F09045, + 0x8C620984, 0xDC40B4CD, 0x4216C291, 0x7A44C04B, 0x1E2B5D31, + 0xA0E77B7D, 0x12076C51, 0x22262FA1, 0x483B54F1, 0x2A7EF465, + 0xD1395E25, 0xB564369F, 0xC94A47A4, 0xFD678BAA, 0xECEE926A, + 0xE41A06AE, 0xE8F293C1, 0x3EB052BE, 0xD0959EF1, 0x93FF1935, + 0x4D65E4F1, 0xE87FC1F9, 0x3BD4BB2B, 0xD5F24F5B, 0x54FF70D4, + 0x968C7B60, 0x44F9BDE4, 0xF4894BDF, 0x3CFDDF7B, 0xD5CC3F10, + 0xD7F952C2, 0xEA3DCB60, 0xEFDAC96A, 0xBBF8F5EB, 0x41526813, + 0x714E3D51, 0x5E15A386, 0x1286AF4F, 0x5E1E5A3E, 0x676C9938, + 0xA716071B, 0x14D79998, 0x5CB794ED, 0xD815EDED, 0xCB1CA55A, + 0x9D6D74FD, 0xBE032C25, 0xF3FE1425, 0xC0CB5217, 0x3931A93F, + 0x82DB8222, 0xD8FF587F, 0x5AD4E8AC, 0xBCF00442, 0x4298A961, + 0x9F8CC3C2, 0x60E2347F, 0x7E090E, 0x691B735, 0x3D4C4D83, + 0x5612B097, 0x7B8DA321, 0x2C28A057, 0xF8FE8901, 0xDA39D0DD, + 0x465CE561, 0xA78756, 0x3B771E01, 0xE638B09, 0x201853B5, + 0xF934D7D2, 0xBD515A83, 0xC1B5C34E, 0x89159FA9, 0x2DDE3EBE, + 0xE27771DB, 0xB5983F05, 0xA3FD869D, 0x8ABA53CB, 0x55C8606C, + 0xDAB769C3, 0x4C4C2EAC, 0x18EE2A56, 0x88452A07, 0x9767C386, + 0x5C0418D6, 0xF79CA785, 0xF291195D, 0x9B0C286F, 0x68460BED, + 0xBF0079E5, 0x9906D932, 0x2F9E5535, 0x2A3C4947, 0xF0E240C3, + 0xE835A264, 0x43F38C0, 0x82DAADD8, 0x313612B1, 0x560D56FB, + 0x61BD734A, 0x58FD6B36, 0x2C45C40B, 0x55F70159, 0xA21A817D, + 0xAAA6FCE, 0x85BFDFB9, 0x1C71DE25, 0x56CB4C2C, 0x50FD91E5, + 0xF2340E88, 0x72BD5702, 0xB4FFBD3A, 0x1B35B171, 0xE94A34BD, + 0xC4C77575, 0x95B10420, 0x2471BC3F, 0xCB429841, 0x6DC5347F, + 0xC93CF782, 0xF1D26B2C, 0xEB2A260F, 0x67C3AE9, 0x34A56A4, + 0xF1F3D01B, 0xD8295F22, 0x7F9E5D4A, 0xE4DB3DEA, 0xE1531DCB, + 0x2C5FF857, 0x73622A7C, 0xC2691F1, 0xBC622B61, 0xE6A08C89, + 0xBA1807D4, 0x43ADBE43, 0xD90D427C, 0xC7A5C24, 0x613ED316, + 0xEC810B10, 0x1049BF74, 0x9A14C123, 0xA7B24E7E, 0x73254165, + 0x2C54081E, 0x14FF25AA, 0x7A12F3B4, 0xB4DF7C56, 0x89BFE8FC, + 0x5D5A04A6, 0xBE007173, 0x829DF863, 0x63E5E57D, 0x58F64C28, + 0x31A38144, 0xE843289B, 0xB48DFAF1, 0x2B335C2A, 0xEC3C96CE, + 0x255543F6, 0x33F17311, 0x3C60C51A, 0xE5D0D660, 0x5E162559, + 0xA2D9416, 0x9DDE4967, 0x28156A65, 0x71650796, 0x74EE54D1, + 0x3E8C19F7, 0x797C1E42, 0x2C536DFD, 0x2F3EED4D, 0x3BFC7C95, + 0x8EAEF87D, 0x18F5B02A, 0xA3532651, 0x24508E13, 0x280B9049, + 0xE4FC61CB, 0x388BA30F, 0xEC180A43, 0xBFDE77A4, 0x98CDB399, + 0xF82B586D, 0x38525AE7, 0x9D857BE8, 0xDD939D18, 0xD5CA6EBA, + 0xB70DDBA, 0xDFF43867, 0xD06AB2D0, 0xD8C78BB, 0x78F6AE4F, + 0x4C9A58CC, 0x9F9AA50E, 0x7D6A3912, 0xD897C7E4, 0x82F5939D, + 0xA4A9FFF5, 0x2CB56FDE, 0x3E082D4B, 0xB829DC58, 0xE4515CEB, + 0xCE585A33, 0x27901244, 0x68860E95, 0xE156A451, 0x9E351FE0, + 0xC69BD757, 0x4B2C4A2B, 0xD5DE5A91, 0x3557B0DE, 0x99E910B0, + 0x975BE470, 0xDB4DE130, 0xE4C6DA1D, 0xC2BC058F, 0x37544906, + 0x12CC200E, 0x54569133, 0x6586FC03, 0xF183C0CF, 0x642583E, + 0xFBE882CD, 0x8A098C35, 0xE8300988, 0xFE835E55, 0xEA74FD24, + 0xF3127AB2, 0xEE8379F2, 0x3F136FD2, 0x472AA942, 0x3BC1A7D7, + 0x5B6A8A98, 0xF039CCF3, 0x5E55425B, 0x3F801B4, 0x44556FB4, + 0xCC966D37, 0x56E32B90, 0x2BCDA2E5, 0xC70F1125, 0x8C2A015C, + 0x3D37FCA7, 0x2118A4EF, 0xCE051A9C, 0xCB84DCB9, 0x8451C9E0, + 0x4BDB1900, 0x8FC71D5D, 0xF61FD749, 0xA696D2E0, 0x6EED502A, + 0xB345CE8B, 0x76FCDA8E, 0xBE4A45F8, 0x8375E9E7, 0x625FF29B, + 0xCEC61240, 0x3876B21D, 0xBA8C8F59, 0x8CD169C6, 0x9F82251F, + 0x2E6EC495, 0x99319E, 0xB0160B46, 0x8B77EDD8, 0x6217902B, + 0x76FA6AD0, 0xB541F2BC, 0x961EA91C, 0x6F554C1F, 0xBD92328D, + 0xA9C077FD, 0x90A5311C, 0xEFE9B1FB, 0x9C84AA8C, 0x812517C3, + 0xFE71D7F4, 0xC4F6A5BF, 0x8B75A262, 0xC726EB36, 0x5F803035, + 0xCECDE2B7, 0xF61152A8, 0x78557ED1, 0x50F3BB55, 0xDD830290, + 0xB125B524, 0xC8683B0D, 0xE5FD573B, 0x48B13066, 0x62AE556E, + 0x5A637C89, 0x498D69F, 0x3F3A5BE5, 0xB98B86D7, 0x20CF4AF4, + 0xA3E55E7D, 0xEE93FC6F, 0xCCA95763, 0x5B3C5706, 0x8342B013, + 0xA0C7BDB9, 0x83D686E4, 0x6934B64, 0x324D75C3, 0x9A100C81, + 0x72E7E9AE, 0xC729A8AC, 0x9E8489E0, 0xFE5BC233, 0x64709AE9, + 0x113437BC, 0x296DEBC0, 0xC4376603, 0x9F0CD7EE, 0x6412AB97, + 0x3EECEFCD, 0x62DCD50, 0x15DFF1, 0xEEFDCF8E, 0x119849C1, + 0xDAAC93FF, 0xD531AF57, 0x82A10F47, 0xD55B7A97, 0x2F3A268B, + 0x4F1CC181, 0xAE01C1AC, 0xF3CF6F61, 0xE8BDAED5, 0x7397FD99, + 0xDD36A03C, 0x9BAED7C3, 0x51404903, 0xB9867B61, 0x3880A4FD, + 0x42B90A49, 0xA94696C1, 0x546DEA1D, 0xEE73A3DE, 0x1A4BAC37, + 0xBC6AF7AE, 0x7DD5B57B, 0xD2F121F, 0xD2BCCA1E, 0xD5DC4753, + 0xA135C08C, 0x78E97831, 0x9B91C00B, 0xFFF2C044, 0x147B797F, + 0x299CFB60, 0x71083BB, 0xB39A6C4F, 0x4814E3E1, 0xBD246AB0, + 0xBCD61250, 0x2D0870, 0xC660435C, 0xCA11681E, 0xADA4C80E, + 0x790C8875, 0x8C4F0D08, 0x48D90C74, 0xE874E9AA, 0xA8013EE8, + 0xB2D23A7A, 0xAF73A16E, 0x2485512C, 0x698E0CB2, 0x2FF566C9, + 0xC1B0C3C6, 0x2BE17C0E, 0xC42C3907, 0xD8A2EA94, 0x8991D24C, + 0x19B939F1, 0xF936F8B3, 0xA72D7EF1, 0x97EED001, 0xBF9C5156, + 0x75F08A67, 0x9AFD5756, 0x5D9D359C, 0xF905B7EC, 0x2B1553E1, + 0x9E0FD4E1, 0x8DC4814C, 0x89F28E6D, 0x14174915, 0x1F3A4217, + 0xA8F367F9, 0x93EE87C5, 0xAD70C6D8, 0xF04D465C, 0xE403D72B, + 0xA686EC0F, 0xCD3A5728, 0xA1BD007, 0x9E21E401, 0xAE8517CF, + 0x6DDB79FC, 0x8CB2C475, 0x6F71544, 0xBEAC91CF, 0x4739DC4E, + 0x6CF4F788, 0x36BAD9AC, 0xF23568D4, 0x250BAB0A, 0x4633384F, + 0x54F6F251, 0x454F9605, 0xCB1A346, 0x632E207F, 0x3017539C, + 0x174A33ED, 0xBDCFD2DE, 0xC17F3D39, 0x17B8A9A2, 0xC267FB51, + 0x9322387D, 0x348760C, 0x3C14D7E0, 0xE4E4254E, 0xCA72AA41, + 0xB6102ED3, 0x6317A3F, 0xD3B6B9F7, 0xA8C71BB7, 0x6E452957, + 0x3F896E32, 0xE38A4A58, 0x9893F432, 0x110A21D4, 0xE835FEBE, + 0x90F51080, 0xD0AC5AF, 0x4FCB9903, 0xFE547785, 0x144B285D, + 0xD0ECC753, 0xAE503BA4, 0x57CEAABC, 0x95713FE6, 0x5B0F4F86, + 0xD94BD751, 0x4017F139, 0xF60F5E1D, 0xB9A63351, 0xF7F94F6A, + 0x7E556ECC, 0xBFDB8642, 0xB70D07D, 0x351BEA77, 0xD1F3CAD, + 0xA3D7EF4D, 0x1EAA28E3, 0x98A2EA79, 0xD8647392, 0x1B896804, + 0x35CA6A08, 0x305258F, 0xE58BD955, 0xABCB6278, 0x87CF1146, + 0x13145966, 0x45BB55CD, 0x818AA368, 0xA027F11F, 0x64C427A3, + 0xEC831B99, 0xF2BD53F9, 0x7FDA7301, 0x35BE80D4, 0x5256E6FB, + 0xC97D33AE, 0x30921709, 0xC2724BEC, 0x78F5436F, 0x4F5749CD, + 0x9007F551, 0x327C31C0, 0x89782D13, 0x119AD125, 0xB1071A01, + 0x63100C70, 0x83120035, 0xA8E2E403, 0x7E213FA3, 0xBF06AAC4, + 0xBA68C4D9, 0x4B568927, 0x1DDD40F, 0x10FC10E8, 0xBBD7230A, + 0x96475640, 0x8C8E6EC1, 0x44A1134A, 0xEF0F40F0, 0x51E2A5E0, + 0x61AE6D65, 0x9DE72FD6, 0xB1711336, 0x90BEB84, 0xD610EFC6, + 0x3D231F91, 0xB5885164, 0x2CB2112C, 0x36F50789, 0x3DEF2AB9, + 0x1D9DC1DA, 0xA37DB070, 0x2AA92EB, 0x2D57ED6E, 0xD6E2C2CD, + 0xB78FC54C, 0x767A565E, 0x1D1F5AAE, 0x89F256DB, 0x716A97D, + 0x1344431D, 0xFAF015FB, 0xFED59649, 0xC479882A, 0xEEFC3D1E, + 0x840AE162, 0xD963A347, 0x75462C25, 0xDA990E07, 0x9A57DE31, + 0x74A35F20, 0x91852CD6, 0x3F16DE14, 0x5FA6A255, 0x47D00F85, + 0x1B4836C9, 0xC73D0290, 0xE301026B, 0x592068D6, 0x7C32A301, + 0x3A3C04C4, 0xB5BD3BAF, 0xB8C3BF60, 0x76723A1B, 0xD05BC35E, + 0x7679021C, 0x6298096, 0x590BA59C, 0xBB30A2F6, 0xE5F6B06C, + 0x21BD2A9E, 0xAC68D7DA, 0xEDA2ED5A, 0xA10E60FA, 0xABDBF569, + 0x17F5868E, 0x82AA8505, 0x384BD8FC, 0x68DC2746, 0x8F029C0D, + 0x3755EB11, 0xAEF4BB79, 0x453B87BA, 0x9926977F, 0x1FA1B806, + 0xC905618, 0x9BFE8E92, 0xF6F68A5A, 0xAA955D92, 0x44F57A4A, + 0x2186E272, 0x62EB01DA, 0x85A2D502, 0xB087955D, 0x26FF2BA0, + 0x8D462C04, 0xE024573B, 0x609CDBD7, 0xA99B9D19, 0xFEEB3F60, + 0x12903A0D, 0x46480C6, 0xDD0BD1B9, 0x6C60C43, 0x5E11A4FE, + 0x935E9E58, 0x8A7F6D33, 0xA505132D, 0xBB2E3E12, 0xF48633F4, + 0xF3BA8CF7, 0xC25D4EDD, 0x788672B8, 0xB2812608, 0xACB3A62, + 0x2EEB679A, 0x443A71B9, 0xC42F4B12, 0xD28B3482, 0x5571FA8A, + 0x5C0B3D55, 0x8B8619C6, 0xF564F10C, 0xD9A7C914, 0xFBD1EF46, + 0xCEABC573, 0xEC609D28, 0x5839413B, 0x5019E901, 0x248FFF30, + 0x7BFFB801, 0x7FD46584, 0x43702812, 0x3A5A0880, 0x7E3E9EDA, + 0xCA4623E3, 0x2FB87A70, 0xFE70D956, 0xCE9EB3E6, 0x9A2CD2F1, + 0x92EFB0C8, 0xC7E23873, 0x53B63A86, 0xB9D93548, 0x3C022B2, + 0xCF4F22A6, 0x981E70BC, 0x4A05F3AB, 0xD763E93B, 0x6EAF767D, + 0x4162629D, 0xD82A25E7, 0x6CDD19A3, 0x13524F68, 0xE5F23FDC, + 0xB37F311F, 0x35FD43B6, 0x36626469, 0x1E409CF6, 0xE4C04F9D, + 0xC1B58001, 0xD131078F, 0x9DE279A, 0x80B62212, 0x526405DD, + 0xC17777C1, 0x7045FCDC, 0x53862AEC, 0x5D583056, 0xEB532222, + 0x5837EA32, 0x719C06A4, 0x43D4F131, 0x577C6DDB, 0x9E5815A7, + 0x8189DDD9, 0x170F154F, 0xEF813B20, 0x4DD83A53, 0xB09A28FD, + 0x8D0DBED5, 0x1836596D, 0xC5BB2696, 0xA69FC859, 0xD6FF5E0D, + 0xCCC65761, 0xC818C6F7, 0x7A25F980, 0xF949133, 0xC515C093, + 0xA8AD04B5, 0x6768AC1C, 0xB5BE2C4A, 0x4F04616F, 0xBD28E4E3, + 0x4CCA6347, 0x5F61C031 +}; + +/* The source data is random across the q31_t range. Accessing it by word should + remain random. */ +q15_t * transform_fft_q15_inputs = (q15_t *) transform_fft_q31_inputs; + +q15_t dct4_transform_fft_q15_inputs[TRANSFORM_MAX_FFT_LEN * 2] = +{ + 0x0000, 0x2d5c, 0x54d5, 0x714b, 0x7f0d, 0x7c51, 0x6972, 0x48e4, + 0x1edf, 0xf0da, 0xc4cb, 0xa06c, 0x8874, 0x8001, 0x882a, 0x9fe2, + 0xc413, 0xf00c, 0x1e16, 0x4839, 0x68fc, 0x7c1f, 0x7f25, 0x71ab, + 0x5570, 0x2e1e, 0x00cf, 0xd367, 0xabc7, 0x8f16, 0x810d, 0x837e, + 0x9619, 0xb672, 0xe057, 0x0e58, 0x3a7c, 0x5f0a, 0x7741, 0x7ffe, + 0x781e, 0x60a7, 0x3ca4, 0x10c2, 0xe2b4, 0xb873, 0x977b, 0x8415, + 0x80c3, 0x8df6, 0xa9f6, 0xd121, 0xfe61, 0x2bd6, 0x539c, 0x7087, + 0x7ed8, 0x7cb1, 0x6a5c, 0x4a38, 0x2072, 0xf277, 0xc63d, 0xa182, + 0x890b, 0x8005, 0x879b, 0x9ed2, 0xc2a6, 0xee70, 0x1c81, 0x46e0, + 0x680c, 0x7bb7, 0x7f53, 0x7268, 0x56a3, 0x2fa0, 0x026f, 0xd4ed, + 0xad02, 0x8fdc, 0x8145, 0x8321, 0x9531, 0xb51f, 0xdec5, 0x0cba, + 0x390a, 0x5df1, 0x76a8, 0x7ff7, 0x78ab, 0x61b5, 0x3e10, 0x125e, + 0xe449, 0xb9cd, 0x986d, 0x847f, 0x8099, 0x8d3c, 0xa8c4, 0xcf9f, + 0xfcc2, 0x2a4f, 0x5260, 0x6fbf, 0x7e9d, 0x7d0c, 0x6b40, 0x4b89, + 0x2203, 0xf414, 0xc7b1, 0xa29c, 0x89a7, 0x800e, 0x8710, 0x9dc5, + 0xc13a, 0xecd5, 0x1aec, 0x4585, 0x6718, 0x7b4a, 0x7f7b, 0x7320, + 0x57d3, 0x3121, 0x040e, 0xd675, 0xae40, 0x90a7, 0x8182, 0x82c8, + 0x944f, 0xb3d0, 0xdd35, 0x0b1d, 0x3795, 0x5cd5, 0x760a, 0x7fec, + 0x7933, 0x62bf, 0x3f7a, 0x13f8, 0xe5df, 0xbb2a, 0x9964, 0x84ef, + 0x8073, 0x8c86, 0xa796, 0xce20, 0xfb23, 0x28c6, 0x5120, 0x6ef2, + 0x7e5e, 0x7d63, 0x6c21, 0x4cd7, 0x2393, 0xf5b2, 0xc927, 0xa3ba, + 0x8a47, 0x801c, 0x868b, 0x9cbd, 0xbfd1, 0xeb3b, 0x1955, 0x4427, + 0x6620, 0x7ad7, 0x7f9d, 0x73d3, 0x5900, 0x329f, 0x05ad, 0xd7ff, + 0xaf81, 0x9176, 0x81c4, 0x8274, 0x9370, 0xb284, 0xdba6, 0x097f, + 0x361d, 0x5bb5, 0x7566, 0x7fda, 0x79b6, 0x63c6, 0x40e2, 0x1592, + 0xe777, 0xbc8a, 0x9a5e, 0x8564, 0x8053, 0x8bd5, 0xa66b, 0xcca2, + 0xf983, 0x273c, 0x4fdd, 0x6e21, 0x7e19, 0x7db3, 0x6cfd, 0x4e21, + 0x2521, 0xf750, 0xca9f, 0xa4dc, 0x8aed, 0x8030, 0x860a, 0x9bb9, + 0xbe6b, 0xe9a1, 0x17bd, 0x42c6, 0x6523, 0x7a60, 0x7fbb, 0x7481, + 0x5a29, 0x341c, 0x074c, 0xd98a, 0xb0c6, 0x924a, 0x820b, 0x8226, + 0x9297, 0xb13b, 0xda18, 0x07e0, 0x34a4, 0x5a92, 0x74bf, 0x7fc4, + 0x7a34, 0x64c8, 0x4247, 0x172b, 0xe90f, 0xbdec, 0x9b5d, 0x85dd, + 0x8038, 0x8b29, 0xa544, 0xcb27, 0xf7e5, 0x25af, 0x4e97, 0x6d4b, + 0x7dcf, 0x7dff, 0x6dd5, 0x4f69, 0x26ae, 0xf8ef, 0xcc1a, 0xa601, + 0x8b97, 0x8049, 0x858f, 0x9ab9, 0xbd08, 0xe809, 0x1625, 0x4162, + 0x6422, 0x79e4, 0x7fd3, 0x752b, 0x5b4e, 0x3596, 0x08eb, 0xdb17, + 0xb20e, 0x9322, 0x8258, 0x81dd, 0x91c1, 0xaff5, 0xd88c, 0x0641, + 0x3328, 0x596a, 0x7412, 0x7fa8, 0x7aad, 0x65c6, 0x43a9, 0x18c3, + 0xeaa8, 0xbf51, 0x9c5f, 0x865c, 0x8023, 0x8a82, 0xa421, 0xc9ad, + 0xf646, 0x2422, 0x4d4d, 0x6c70, 0x7d80, 0x7e46, 0x6ea8, 0x50ad, + 0x2839, 0xfa8e, 0xcd97, 0xa72b, 0x8c46, 0x8067, 0x8518, 0x99bd, + 0xbba7, 0xe671, 0x148b, 0x3ffb, 0x631e, 0x7963, 0x7fe6, 0x75d0, + 0x5c6f, 0x370f, 0x0a89, 0xdca6, 0xb359, 0x93ff, 0x82a9, 0x8199, + 0x90f0, 0xaeb2, 0xd702, 0x04a2, 0x31aa, 0x583f, 0x7360, 0x7f88, + 0x7b21, 0x66c0, 0x4508, 0x1a5a, 0xec42, 0xc0b9, 0x9d66, 0x86e0, + 0x8012, 0x89e0, 0xa302, 0xc836, 0xf4a8, 0x2292, 0x4c01, 0x6b91, + 0x7d2c, 0x7e87, 0x6f76, 0x51ee, 0x29c3, 0xfc2d, 0xcf16, 0xa858, + 0x8cfa, 0x808b, 0x84a7, 0x98c5, 0xba4a, 0xe4da, 0x12f1, 0x3e92, + 0x6215, 0x78dc, 0x7ff4, 0x7670, 0x5d8c, 0x3884, 0x0c27, 0xde36, + 0xb4a7, 0x94e0, 0x8300, 0x815a, 0x9024, 0xad73, 0xd579, 0x0303, + 0x302a, 0x5711, 0x72aa, 0x7f61, 0x7b90, 0x67b5, 0x4664, 0x1bf0, + 0xeddd, 0xc223, 0x9e71, 0x8769, 0x8007, 0x8942, 0xa1e6, 0xc6c2, + 0xf30b, 0x2102, 0x4ab1, 0x6aae, 0x7cd2, 0x7ec3, 0x7040, 0x532b, + 0x2b4b, 0xfdcc, 0xd097, 0xa988, 0x8db3, 0x80b4, 0x843a, 0x97d1, + 0xb8ef, 0xe345, 0x1155, 0x3d27, 0x6108, 0x7851, 0x7ffc, 0x770b, + 0x5ea6, 0x39f8, 0x0dc4, 0xdfc7, 0xb5f8, 0x95c5, 0x835c, 0x8120, + 0x8f5d, 0xac37, 0xd3f2, 0x0164, 0x2ea8, 0x55de, 0x71ef, 0x7f36, + 0x7bfa, 0x68a7, 0x47be, 0x1d85, 0xef79, 0xc390, 0x9f80, 0x87f6, + 0x8001, 0x88a9, 0xa0cf, 0xc54f, 0xf16e, 0x1f70, 0x495e, 0x69c6, + 0x7c74, 0x7efa, 0x7106, 0x5465, 0x2cd1, 0xff6c, 0xd219, 0xaabc, + 0x8e70, 0x80e2, 0x83d3, 0x96e2, 0xb796, 0xe1b1, 0x0fb9, 0x3bb8, + 0x5ff7, 0x77c1, 0x7fff, 0x77a1, 0x5fbc, 0x3b69, 0x0f61, 0xe15a, + 0xb74d, 0x96af, 0x83bd, 0x80ec, 0x8e9a, 0xaaff, 0xd26d, 0xffc5, + 0x2d24, 0x54a8, 0x712f, 0x7f05, 0x7c5f, 0x6994, 0x4914, 0x1f19, + 0xf115, 0xc500, 0xa093, 0x8889, 0x8001, 0x8816, 0x9fbb, 0xc3df, + 0xefd1, 0x1ddc, 0x4808, 0x68da, 0x7c10, 0x7f2c, 0x71c6, 0x559c, + 0x2e55, 0x010a, 0xd39e, 0xabf4, 0x8f32, 0x8115, 0x8371, 0x95f7, + 0xb641, 0xe01e, 0x0e1d, 0x3a48, 0x5ee2, 0x772c, 0x7ffd, 0x7832, + 0x60cd, 0x3cd8, 0x10fd, 0xe2ee, 0xb8a4, 0x979e, 0x8423, 0x80bd, + 0x8ddb, 0xa9ca, 0xd0ea, 0xfe26, 0x2b9f, 0x536f, 0x706b, 0x7ed0, + 0x7cbf, 0x6a7c, 0x4a68, 0x20ab, 0xf2b2, 0xc672, 0xa1aa, 0x8921, + 0x8006, 0x8787, 0x9eab, 0xc272, 0xee36, 0x1c48, 0x46af, 0x67ea, + 0x7ba8, 0x7f59, 0x7282, 0x56cf, 0x2fd7, 0x02aa, 0xd525, 0xad2f, + 0x8ff9, 0x814d, 0x8314, 0x9511, 0xb4ef, 0xde8c, 0x0c80, 0x38d5, + 0x5dc9, 0x7692, 0x7ff6, 0x78bf, 0x61db, 0x3e44, 0x1298, 0xe483, + 0xb9ff, 0x9890, 0x848f, 0x8093, 0x8d22, 0xa899, 0xcf68, 0xfc87, + 0x2a17, 0x5232, 0x6fa2, 0x7e95, 0x7d19, 0x6b61, 0x4bb8, 0x223c, + 0xf44f, 0xc7e6, 0xa2c5, 0x89bd, 0x8010, 0x86fd, 0x9d9f, 0xc107, + 0xec9b, 0x1ab2, 0x4553, 0x66f5, 0x7b3a, 0x7f80, 0x7339, 0x57fe, + 0x3157, 0x0449, 0xd6ad, 0xae6d, 0x90c4, 0x818b, 0x82bc, 0x942f, + 0xb3a0, 0xdcfc, 0x0ae2, 0x375f, 0x5cad, 0x75f3, 0x7fe9, 0x7946, + 0x62e5, 0x3fae, 0x1433, 0xe619, 0xbb5c, 0x9987, 0x84ff, 0x806f, + 0x8c6d, 0xa76b, 0xcde9, 0xfae7, 0x288e, 0x50f2, 0x6ed5, 0x7e54, + 0x7d6e, 0x6c41, 0x4d06, 0x23cc, 0xf5ed, 0xc95c, 0xa3e3, 0x8a5f, + 0x801f, 0x8678, 0x9c98, 0xbf9e, 0xeb00, 0x191b, 0x43f5, 0x65fc, + 0x7ac7, 0x7fa2, 0x73ec, 0x592a, 0x32d6, 0x05e8, 0xd837, 0xafaf, + 0x9194, 0x81ce, 0x8269, 0x9351, 0xb255, 0xdb6d, 0x0944, 0x35e8, + 0x5b8c, 0x754f, 0x7fd8, 0x79c8, 0x63eb, 0x4115, 0x15cc, 0xe7b1, + 0xbcbc, 0x9a82, 0x8575, 0x804f, 0x8bbd, 0xa641, 0xcc6c, 0xf948, + 0x2703, 0x4faf, 0x6e03, 0x7e0f, 0x7dbf, 0x6d1c, 0x4e50, 0x255a, + 0xf78b, 0xcad5, 0xa505, 0x8b05, 0x8033, 0x85f8, 0x9b94, 0xbe39, + 0xe967, 0x1783, 0x4293, 0x64ff, 0x7a4f, 0x7fbf, 0x749a, 0x5a52, + 0x3452, 0x0787, 0xd9c3, 0xb0f4, 0x9268, 0x8216, 0x821b, 0x9278, + 0xb10c, 0xd9e0, 0x07a5, 0x346e, 0x5a68, 0x74a6, 0x7fc0, 0x7a46, + 0x64ec, 0x4279, 0x1765, 0xe949, 0xbe1f, 0x9b81, 0x85ef, 0x8035, + 0x8b11, 0xa51b, 0xcaf1, 0xf7aa, 0x2577, 0x4e68, 0x6d2c, 0x7dc4, + 0x7e0a, 0x6df3, 0x4f97, 0x26e6, 0xf92a, 0xcc50, 0xa62c, 0x8bb0, + 0x804d, 0x857d, 0x9a95, 0xbcd6, 0xe7cf, 0x15ea, 0x412f, 0x63fe, + 0x79d2, 0x7fd6, 0x7543, 0x5b77, 0x35cc, 0x0925, 0xdb50, 0xb23d, + 0x9341, 0x8263, 0x81d3, 0x91a3, 0xafc7, 0xd854, 0x0606, 0x32f2, + 0x5940, 0x73f9, 0x7fa4, 0x7abe, 0x65ea, 0x43db, 0x18fd, 0xeae2, + 0xbf84, 0x9c85, 0x866f, 0x8020, 0x8a6b, 0xa3f8, 0xc978, 0xf60b, + 0x23e9, 0x4d1e, 0x6c51, 0x7d74, 0x7e4f, 0x6ec5, 0x50db, 0x2871, + 0xfac9, 0xcdcd, 0xa755, 0x8c60, 0x806c, 0x8508, 0x9999, 0xbb75, + 0xe637, 0x1451, 0x3fc8, 0x62f8, 0x7950, 0x7fe8, 0x75e7, 0x5c98, + 0x3744, 0x0ac4, 0xdcdf, 0xb388, 0x941e, 0x82b5, 0x8190, 0x90d3, + 0xae85, 0xd6ca, 0x0467, 0x3173, 0x5814, 0x7347, 0x7f82, 0x7b31, + 0x66e3, 0x453a, 0x1a94, 0xec7d, 0xc0ec, 0x9d8c, 0x86f3, 0x8011, + 0x89c9, 0xa2d9, 0xc801, 0xf46d, 0x2259, 0x4bd1, 0x6b71, 0x7d1f, + 0x7e90, 0x6f93, 0x521b, 0x29fb, 0xfc68, 0xcf4c, 0xa883, 0x8d14, + 0x8090, 0x8497, 0x98a2, 0xba18, 0xe4a1, 0x12b6, 0x3e5f, 0x61ef, + 0x78c9, 0x7ff5, 0x7686, 0x5db5, 0x38b9, 0x0c61, 0xde6f, 0xb4d7, + 0x9500, 0x830d, 0x8152, 0x9007, 0xad46, 0xd541, 0x02c8, 0x2ff3, + 0x56e5, 0x7290, 0x7f5c, 0x7ba0, 0x67d8, 0x4696, 0x1c2a, 0xee17, + 0xc257, 0x9e97, 0x877d, 0x8006, 0x892c, 0xa1be, 0xc68d, 0xf2d0, + 0x20c8, 0x4a81, 0x6a8d, 0x7cc5, 0x7ecc, 0x705d, 0x5358, 0x2b82, + 0xfe08, 0xd0ce, 0xa9b4, 0x8dce, 0x80ba, 0x842b, 0x97af, 0xb8bd, + 0xe30b, 0x111b, 0x3cf3, 0x60e1, 0x783d, 0x7ffd, 0x7721, 0x5ece, + 0x3a2d, 0x0dff, 0xe000, 0xb629, 0x95e6, 0x836a, 0x8119, 0x8f41, + 0xac0b, 0xd3bb, 0x0129, 0x2e71, 0x55b2, 0x71d4, 0x7f2f, 0x7c09, + 0x68c9, 0x47ef, 0x1dbf, 0xefb3, 0xc3c4, 0x9fa7, 0x880b, 0x8001, + 0x8894, 0xa0a7, 0xc51b, 0xf133, 0x1f36, 0x492d, 0x69a5, 0x7c66, + 0x7f02, 0x7121, 0x5492, 0x2d08, 0xffa7, 0xd251, 0xaae8, 0x8e8b, + 0x80e9, 0x83c5, 0x96c1, 0xb766, 0xe177, 0x0f7f, 0x3b84, 0x5fd0, + 0x77ac, 0x7fff, 0x77b6, 0x5fe3, 0x3b9d, 0x0f9b, 0xe193, 0xb77d, + 0x96d1, 0x83cc, 0x80e5, 0x8e7e, 0xaad3, 0xd236, 0xff8a, 0x2ced, + 0x547c, 0x7114, 0x7efe, 0x7c6d, 0x69b5, 0x4945, 0x1f52, 0xf150, + 0xc534, 0xa0ba, 0x889e, 0x8001, 0x8801, 0x9f94, 0xc3ab, 0xef97, + 0x1da3, 0x47d7, 0x68b8, 0x7c02, 0x7f33, 0x71e1, 0x55c8, 0x2e8c, + 0x0145, 0xd3d6, 0xac20, 0x8f4e, 0x811c, 0x8363, 0x95d6, 0xb611, + 0xdfe5, 0x0de2, 0x3a13, 0x5eba, 0x7716, 0x7ffd, 0x7847, 0x60f4, + 0x3d0c, 0x1137, 0xe327, 0xb8d5, 0x97c0, 0x8432, 0x80b7, 0x8dc1, + 0xa99f, 0xd0b3, 0xfdeb, 0x2b67, 0x5342, 0x704f, 0x7ec8, 0x7ccc, + 0x6a9d, 0x4a98, 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0x9da0, 0xc108, 0xec9c, 0x1ab4, 0x4555 +}; + +float32_t transform_fft_f32_inputs[TRANSFORM_MAX_FFT_LEN * 2] = +{ + 43.0264275639, -17.0525215570, -94.8488973910, -8.1924989580, 7.2830326091, 66.8368719314, 33.9778190671, 117.8652289772, + -129.6077797465, -14.6420815368, 18.0239223278, 20.6760530292, 55.0375037651, 1.8674609862, -85.6534302408, -33.5750364909, + 29.2110949614, 110.4727049460, -94.1914619387, -1.4084169343, 83.5181653041, 47.3073514127, -13.3420621181, 30.3389699104, + 12.1188124277, 100.9730921941, -114.0146362390, -77.5823200409, 37.2019034618, 40.0026301128, -58.3387276630, -34.9472398600, + -5.1169678311, -87.7660091118, -150.5888601131, 56.0349370503, 50.2168884079, -74.2313236767, 22.3648603560, -6.8676387051, + 74.8957303680, -90.1292012823, -55.1436241586, -66.6732976100, -6.7918147615, 7.7612697081, 35.7892605979, -20.0470508830, + 41.8369017546, -143.7378056984, -41.9127158600, -108.3531841158, -57.1917422289, -124.2808828105, 38.9316388820, -77.9212517405, + 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+/*--------------------------------------------------------------------------------*/ +/* FFT Lengths */ +/*--------------------------------------------------------------------------------*/ + +/* + To change test parameter values add/remove values inside CURLY and update + the preceeding parameter to reflect the number of values inside CURLY. +*/ + +ARR_DESC_DEFINE(uint16_t, + transform_radix2_fftlens, + 7, + CURLY( + 16, 32, 64, 128, 256, + 512, 1024/*, 2048 , 4096 */)); + +ARR_DESC_DEFINE(uint16_t, + transform_radix4_fftlens, + 4, + CURLY( + 16, 64, 256, 1024/* , 4096 */)); + +ARR_DESC_DEFINE(uint16_t, + transform_rfft_fftlens, + 6, + CURLY( + 32, 64, 128, 256, + 512, 1024/*, 2048 , 4096, 8192*/)); + +ARR_DESC_DEFINE(uint16_t, + transform_dct_fftlens, + 3, + CURLY( + 128, 512, 2048/*, 8192*/)); + +ARR_DESC_DEFINE(uint16_t, + transform_rfft_fast_fftlens, + 7, + CURLY( + 32, 64, 128, 256, + 512, 1024, 2048)); + +/*--------------------------------------------------------------------------------*/ +/* CFFT_F32 Structs */ +/*--------------------------------------------------------------------------------*/ + +/* Uses radix2 lengths */ +ARR_DESC_DEFINE(const arm_cfft_instance_f32 *, + transform_cfft_f32_structs, + 5, + CURLY( + &arm_cfft_sR_f32_len16, + &arm_cfft_sR_f32_len32, + &arm_cfft_sR_f32_len64, + &arm_cfft_sR_f32_len128, + &arm_cfft_sR_f32_len256/*, + &arm_cfft_sR_f32_len512, */ + /* &arm_cfft_sR_f32_len1024, */ + /* &arm_cfft_sR_f32_len2048, */ + /* &arm_cfft_sR_f32_len4096 */ + )); + +/*--------------------------------------------------------------------------------*/ +/* CFFT_Q31 Structs */ +/*--------------------------------------------------------------------------------*/ + +/* Uses radix2 lengths */ +ARR_DESC_DEFINE(const arm_cfft_instance_q31 *, + transform_cfft_q31_structs, + 5, + CURLY( + &arm_cfft_sR_q31_len16, + &arm_cfft_sR_q31_len32, + &arm_cfft_sR_q31_len64, + &arm_cfft_sR_q31_len128, + &arm_cfft_sR_q31_len256/*, + &arm_cfft_sR_q31_len512, */ + /* &arm_cfft_sR_q31_len1024, */ + /* &arm_cfft_sR_q31_len2048, */ + /* &arm_cfft_sR_q31_len4096 */ + )); + +/*--------------------------------------------------------------------------------*/ +/* CFFT_q15 Structs */ +/*--------------------------------------------------------------------------------*/ + +/* Uses radix2 lengths */ +ARR_DESC_DEFINE(const arm_cfft_instance_q15 *, + transform_cfft_q15_structs, + 5, + CURLY( + &arm_cfft_sR_q15_len16, + &arm_cfft_sR_q15_len32, + &arm_cfft_sR_q15_len64, + &arm_cfft_sR_q15_len128, + &arm_cfft_sR_q15_len256/*, + &arm_cfft_sR_q15_len512, */ + /* &arm_cfft_sR_q15_len1024, */ + /* &arm_cfft_sR_q15_len2048, */ + /* &arm_cfft_sR_q15_len4096 */ + )); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt new file mode 100644 index 0000000..d9cb90a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt @@ -0,0 +1,11 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt new file mode 100644 index 0000000..9c3cfc2 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt new file mode 100644 index 0000000..011260a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt new file mode 100644 index 0000000..2a0a82a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt new file mode 100644 index 0000000..4140d9b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt new file mode 100644 index 0000000..8e33c76 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm0ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm0ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt new file mode 100644 index 0000000..2caf254 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm3ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm3ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt new file mode 100644 index 0000000..1c9fece --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt new file mode 100644 index 0000000..eb832ed --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt new file mode 100644 index 0000000..4e591c9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt new file mode 100644 index 0000000..1888d60 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt new file mode 100644 index 0000000..1888d60 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..da85ffe --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack underflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + break; + } + for (;;) {} +return 0U; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..f567411 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 512 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x01U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x01U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x05U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x01U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x01U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x01U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x01U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x01U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x01U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x01U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x01U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.c new file mode 100644 index 0000000..6afdccc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Exception handlers (C functions) + * + * ----------------------------------------------------------------------------- + */ +#include "RTE_Components.h" +#include CMSIS_device_header + + +//Fault Status Register (IFSR/DFSR) definitions +#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup +#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external +#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external +#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external +#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external +#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external +#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal +#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal +#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal +#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal +#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal +#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal +#define FSR_PERMISSION_FAULT_FIRST 0x0f //MMU Fault - internal +#define FSR_PERMISSION_FAULT_SECOND 0x0d //MMU Fault - internal +#define FSR_DEBUG_EVENT 0x02 //internal +#define FSR_SYNC_EXT_ABORT 0x08 //sync/external +#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external +#define FSR_LOCKDOWN 0x14 //internal +#define FSR_COPROCESSOR_ABORT 0x1a //internal +#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external +#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external +#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external + +void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { + uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status + + switch(FS) { + //Synchronous parity errors - retry + case FSR_SYNC_PARITY_ERROR: + case FSR_SYNC_PARITY_TTB_WALK_FIRST: + case FSR_SYNC_PARITY_TTB_WALK_SECOND: + return; + + //Your code here. Value in DFAR is invalid for some fault statuses. + case FSR_ALIGNMENT_FAULT: + case FSR_INSTRUCTION_CACHE_MAINTENANCE: + case FSR_SYNC_EXT_TTB_WALK_FIRST: + case FSR_SYNC_EXT_TTB_WALK_SECOND: + case FSR_TRANSLATION_FAULT_FIRST: + case FSR_TRANSLATION_FAULT_SECOND: + case FSR_ACCESS_FLAG_FAULT_FIRST: + case FSR_ACCESS_FLAG_FAULT_SECOND: + case FSR_DOMAIN_FAULT_FIRST: + case FSR_DOMAIN_FAULT_SECOND: + case FSR_PERMISSION_FAULT_FIRST: + case FSR_PERMISSION_FAULT_SECOND: + case FSR_DEBUG_EVENT: + case FSR_SYNC_EXT_ABORT: + case FSR_TLB_CONFLICT_ABORT: + case FSR_LOCKDOWN: + case FSR_COPROCESSOR_ABORT: + case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid + case FSR_ASYNC_PARITY_ERROR: //DFAR invalid + default: + while(1); + } +} + +void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { + uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status + + switch(FS) { + //Synchronous parity errors - retry + case FSR_SYNC_PARITY_ERROR: + case FSR_SYNC_PARITY_TTB_WALK_FIRST: + case FSR_SYNC_PARITY_TTB_WALK_SECOND: + return; + + //Your code here. Value in IFAR is invalid for some fault statuses. + case FSR_SYNC_EXT_TTB_WALK_FIRST: + case FSR_SYNC_EXT_TTB_WALK_SECOND: + case FSR_TRANSLATION_FAULT_FIRST: + case FSR_TRANSLATION_FAULT_SECOND: + case FSR_ACCESS_FLAG_FAULT_FIRST: + case FSR_ACCESS_FLAG_FAULT_SECOND: + case FSR_DOMAIN_FAULT_FIRST: + case FSR_DOMAIN_FAULT_SECOND: + case FSR_PERMISSION_FAULT_FIRST: + case FSR_PERMISSION_FAULT_SECOND: + case FSR_DEBUG_EVENT: //IFAR invalid + case FSR_SYNC_EXT_ABORT: + case FSR_TLB_CONFLICT_ABORT: + case FSR_LOCKDOWN: + case FSR_COPROCESSOR_ABORT: + default: + while(1); + } +} + + +//returns amount to decrement lr by +//this will be 0 when we have emulated the instruction and want to execute the next instruction +//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2) +//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4) +uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { + const int THUMB = 2; + const int ARM = 4; + //Lazy VFP/NEON initialisation and switching + + // (ARM ARM section A7.5) VFP data processing instruction? + // (ARM ARM section A7.6) VFP/NEON register load/store instruction? + // (ARM ARM section A7.8) VFP/NEON register data transfer instruction? + // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction? + if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) || + (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) { + if (((opcode & 0x00000E00) >> 9) == 5) { + __FPU_Enable(); + return state; + } + } + + // (ARM ARM section A7.4) NEON data processing instruction? + if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) || + (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) || + // (ARM ARM section A7.7) NEON load/store instruction? + (state == ARM && ((opcode >> 24) == 0xF4)) || + (state == THUMB && ((opcode >> 24) == 0xF9))) { + __FPU_Enable(); + return state; + } + + //Add code here for other Undef cases + while(1); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mem_ARMCA5.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mem_ARMCA5.h new file mode 100644 index 0000000..04669d0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mem_ARMCA5.h @@ -0,0 +1,94 @@ +/**************************************************************************//** + * @file mem_ARMCA5.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.00 + * @date 10. January 2018 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_ARMCA5_H +#define __MEM_ARMCA5_H + +/*---------------------------------------------------------------------------- + User Stack & Heap size definition + *----------------------------------------------------------------------------*/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- ROM Configuration ------------------------------------ +// +// ROM Configuration +// ROM Base Address <0x0-0xFFFFFFFF:8> +// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x80000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- RAM Configuration ----------------------------------- +// RAM Configuration +// RAM Base Address <0x0-0xFFFFFFFF:8> +// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8> +// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> +// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Exceptional Modes +// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +// +// + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x80200000 +#define __RAM_SIZE 0x00200000 + +#define __RW_DATA_SIZE 0x00100000 +#define __ZI_DATA_SIZE 0x000F0000 + +#define __STACK_SIZE 0x00001000 +#define __HEAP_SIZE 0x00008000 + +#define __UND_STACK_SIZE 0x00000100 +#define __ABT_STACK_SIZE 0x00000100 +#define __SVC_STACK_SIZE 0x00000100 +#define __IRQ_STACK_SIZE 0x00000100 +#define __FIQ_STACK_SIZE 0x00000100 + +/*----------------------------------------------------------------------------*/ + +/*--------------------- TTB Configuration ------------------------------------ +// +// TTB Configuration +// TTB Base Address <0x0-0xFFFFFFFF:8> +// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __TTB_BASE 0x80500000 +#define __TTB_SIZE 0x00004000 + +#endif /* __MEM_ARMCA5_H */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.c new file mode 100644 index 0000000..2aa1a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.c @@ -0,0 +1,235 @@ +/**************************************************************************//** + * @file mmu_ARMCA5.c + * @brief MMU Configuration for ARM Cortex-A5 Device Series + * @version V1.1.0 + * @date 23. November 2018 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map + + Memory Type +0xffffffff |--------------------------| ------------ + | FLAG SYNC | Device Memory +0xfffff000 |--------------------------| ------------ + | Fault | Fault +0xfff00000 |--------------------------| ------------ + | | Normal + | | + | Daughterboard | + | memory | + | | +0x80505000 |--------------------------| ------------ + |TTB (L2 Sync Flags ) 4k | Normal +0x80504C00 |--------------------------| ------------ + |TTB (L2 Peripherals-B) 16k| Normal +0x80504800 |--------------------------| ------------ + |TTB (L2 Peripherals-A) 16k| Normal +0x80504400 |--------------------------| ------------ + |TTB (L2 Priv Periphs) 4k | Normal +0x80504000 |--------------------------| ------------ + | TTB (L1 Descriptors) | Normal +0x80500000 |--------------------------| ------------ + | Heap | Normal + |--------------------------| ------------ + | Stack | Normal +0x80400000 |--------------------------| ------------ + | ZI Data | Normal +0x80300000 |--------------------------| ------------ + | RW Data | Normal +0x80200000 |--------------------------| ------------ + | RO Data | Normal + |--------------------------| ------------ + | RO Code | USH Normal +0x80000000 |--------------------------| ------------ + | Daughterboard | Fault + | HSB AXI buses | +0x40000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x2c002000 |--------------------------| ------------ + | Private Address | Device Memory +0x2c000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x20000000 |--------------------------| ------------ + | Peripherals | Device Memory RW/RO + | | & Fault +0x00000000 |--------------------------| +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 + +#include "ARMCA5.h" + + +// L2 table pointers +//---------------------------------------- +#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space +#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization +#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF +#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF + +//--------------------- PERIPHERALS ------------------- +#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) +#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) + +//--------------------- SYNC FLAGS -------------------- +#define FLAG_SYNC 0xFFFFF000 +#define F_SYNC_BASE 0xFFF00000 //1M aligned + +//Import symbols from linker +extern uint32_t Image$$VECTORS$$Base; +extern uint32_t Image$$RW_DATA$$Base; +extern uint32_t Image$$ZI_DATA$$Base; +extern uint32_t Image$$TTB$$ZI$$Base; + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; + + //Create 4GB of faulting entries + MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); + + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Define Image + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 2, Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW); + + //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal); + + //--------------------- PERIPHERALS ------------------- + MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_SRAM_BASE , 64, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_USB_BASE , 16, Sect_Device_RW); + + // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); + // Define peripheral range 0x1C000000-0x1C00FFFF + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + + // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); + // Define peripheral range 0x1C100000-0x1C10FFFF + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + + // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory + MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); + // Define private address space entry. + MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); + // Define L2CC entry. Uncomment if PL310 is present + // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); + + // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) + MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); + // Define synchronization space entry. + MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x1 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x01 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x0 (Inner WB WA) */ + __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 0x48); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.c new file mode 100644 index 0000000..535a200 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.c @@ -0,0 +1,138 @@ +/****************************************************************************** + * @file startup_ARMCA5.c + * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series + * @version V1.00 + * @date 10. January 2018 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +/*---------------------------------------------------------------------------- + Definitions + *----------------------------------------------------------------------------*/ +#define USR_MODE 0x10 // User mode +#define FIQ_MODE 0x11 // Fast Interrupt Request mode +#define IRQ_MODE 0x12 // Interrupt Request mode +#define SVC_MODE 0x13 // Supervisor mode +#define ABT_MODE 0x17 // Abort mode +#define UND_MODE 0x1B // Undefined Instruction mode +#define SYS_MODE 0x1F // System mode + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Vectors (void) __attribute__ ((naked, section("RESET"))); +void Reset_Handler (void) __attribute__ ((naked)); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector Table + *----------------------------------------------------------------------------*/ +void Vectors(void) { + __ASM volatile( + "LDR PC, =Reset_Handler \n" + "LDR PC, =Undef_Handler \n" + "LDR PC, =SVC_Handler \n" + "LDR PC, =PAbt_Handler \n" + "LDR PC, =DAbt_Handler \n" + "NOP \n" + "LDR PC, =IRQ_Handler \n" + "LDR PC, =FIQ_Handler \n" + ); +} + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) { + __ASM volatile( + + // Mask interrupts + "CPSID if \n" + + // Put any cores other than 0 to sleep + "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR + "ANDS R0, R0, #3 \n" + "goToSleep: \n" + "WFINE \n" + "BNE goToSleep \n" + + // Reset SCTLR Settings + "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register + "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache + "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache + "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU + "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction + "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs + "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register + "ISB \n" + + // Configure ACTLR + "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register + "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) + "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register + + // Set Vector Base Address Register (VBAR) to point to this application's vector table + "LDR R0, =Vectors \n" + "MCR p15, 0, R0, c12, c0, 0 \n" + + // Setup Stack for each exceptional mode + "CPS #0x11 \n" + "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" + "CPS #0x12 \n" + "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" + "CPS #0x13 \n" + "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" + "CPS #0x17 \n" + "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" + "CPS #0x1B \n" + "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" + "CPS #0x1F \n" + "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" + + // Call SystemInit + "BL SystemInit \n" + + // Unmask interrupts + "CPSIE if \n" + + // Call __main + "BL __main \n" + ); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + while(1); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c new file mode 100644 index 0000000..5f599f6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c @@ -0,0 +1,93 @@ +/****************************************************************************** + * @file system_ARMCA5.c + * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series + * @version V1.0.1 + * @date 13. February 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "irq_ctrl.h" + +#define SYSTEM_CLOCK 12000000U + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +/* do not use global variables because this function is called before + reaching pre-main. RW section may be overwritten afterwards. */ + + // Invalidate entire Unified TLB + __set_TLBIALL(0); + + // Invalidate entire branch predictor array + __set_BPIALL(0); + __DSB(); + __ISB(); + + // Invalidate instruction cache and flush branch target cache + __set_ICIALLU(0); + __DSB(); + __ISB(); + + // Invalidate data cache + L1C_InvalidateDCacheAll(); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + // Create Translation Table + MMU_CreateTranslationTable(); + + // Enable MMU + MMU_Enable(); + + // Enable Caches + L1C_EnableCaches(); + L1C_EnableBTAC(); + +#if (__L2C_PRESENT == 1) + // Enable GIC + L2C_Enable(); +#endif + + // IRQ Initialize + IRQ_Initialize(); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.h new file mode 100644 index 0000000..6a2a6da --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * @file system_ARMCA5.h + * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series + * @version V1.00 + * @date 10. January 2018 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_ARMCA5_H +#define __SYSTEM_ARMCA5_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + \brief Create Translation Table. + + Creates Memory Management Unit Translation Table. + */ +extern void MMU_CreateTranslationTable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_ARMCA5_H */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/RTE_Components.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/RTE_Components.h new file mode 100644 index 0000000..e894dc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: DspLibTest_FVP_A5 + * RTE configuration: DspLibTest_FVP_A5.rteconfig +*/ +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +/* + * Define the Device Header File: +*/ +#define CMSIS_device_header "ARMCA5.h" + +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.c new file mode 100644 index 0000000..6ca58ab --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.c @@ -0,0 +1,34 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + *---------------------------------------------------------------------------*/ + +#include + +#include "jtest.h" +#include "all_tests.h" +#include "arm_math.h" + + +int main (void) { + + JTEST_INIT(); /* Initialize test framework. */ + JTEST_GROUP_CALL(all_tests); /* Run all tests. */ + JTEST_ACT_EXIT_FW(); /* Exit test framework. */ + + while(1); /* Never return */ +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/HowTo.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/HowTo.txt new file mode 100644 index 0000000..c466e14 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/HowTo.txt @@ -0,0 +1,29 @@ + +Used board: + MPS2+. + +Used BIOS: + mbb_v121.ebf ; use this for ULINKpro + mbb_v220.ebf ; CMSIS-DAP + +Used Images: + AN382\an382_v3.txt ; Cortex-M0 + AN385\an385_v3.txt ; Cortex-M3 + AN386\an386_v3.txt ; Cortex-M4 + AN500\an500_v1.txt ; Cortex-M7 + AN505\an505_v2.txt ; Cortex-M33 (IoT Kit) + AN519\an519_v1.txt ; Cortex-M23 (IoT Kit) + +Used Debugger: + IoT Kit: + ULINKpro, JTAG, 25MHz, HW Reset + other: + ULINKpro, JTAG, 25MHz, Autodetect + +Memory Settings: + IoT Kit: + ROM: 0x10000000 + RAM: 0x38000000 + other: + ROM: 0x00000000 + RAM: 0x20000000 \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MBLl_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MBLl_config.txt new file mode 100644 index 0000000..d9cb90a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MBLl_config.txt @@ -0,0 +1,11 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLl_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLl_config.txt new file mode 100644 index 0000000..9c3cfc2 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLl_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLld_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLld_config.txt new file mode 100644 index 0000000..011260a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLld_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLldfsp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLldfsp_config.txt new file mode 100644 index 0000000..2a0a82a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLldfsp_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLlfsp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLlfsp_config.txt new file mode 100644 index 0000000..4140d9b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLlfsp_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM0l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM0l_config.txt new file mode 100644 index 0000000..8e33c76 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM0l_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm0ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm0ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM3l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM3l_config.txt new file mode 100644 index 0000000..2caf254 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM3l_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm3ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm3ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM4l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM4l_config.txt new file mode 100644 index 0000000..1c9fece --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM4l_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM4lf_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM4lf_config.txt new file mode 100644 index 0000000..eb832ed --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM4lf_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7l_config.txt new file mode 100644 index 0000000..4e591c9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7l_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7lfdp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7lfdp_config.txt new file mode 100644 index 0000000..1888d60 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7lfdp_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7lfsp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7lfsp_config.txt new file mode 100644 index 0000000..1888d60 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7lfsp_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MBLl_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MBLl_config.txt new file mode 100644 index 0000000..d9cb90a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MBLl_config.txt @@ -0,0 +1,11 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLl_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLl_config.txt new file mode 100644 index 0000000..9c3cfc2 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLl_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLld_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLld_config.txt new file mode 100644 index 0000000..011260a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLld_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLldfsp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLldfsp_config.txt new file mode 100644 index 0000000..2a0a82a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLldfsp_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLlfsp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLlfsp_config.txt new file mode 100644 index 0000000..4140d9b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/ARMv8MMLlfsp_config.txt @@ -0,0 +1,13 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM0l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM0l_config.txt new file mode 100644 index 0000000..8e33c76 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM0l_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm0ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm0ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM3l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM3l_config.txt new file mode 100644 index 0000000..2caf254 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM3l_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm3ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm3ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM4l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM4l_config.txt new file mode 100644 index 0000000..1c9fece --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM4l_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM4lf_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM4lf_config.txt new file mode 100644 index 0000000..eb832ed --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM4lf_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM7l_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM7l_config.txt new file mode 100644 index 0000000..4e591c9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM7l_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM7lfdp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM7lfdp_config.txt new file mode 100644 index 0000000..1888d60 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM7lfdp_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM7lfsp_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM7lfsp_config.txt new file mode 100644 index 0000000..1888d60 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_SV_MPS2/cortexM7lfsp_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3] +armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt new file mode 100644 index 0000000..41ca5a6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt @@ -0,0 +1,137 @@ +HowTo DSP_Lib_TestSuite 18.02.2019 +======================================= + +This file describes the folder structure, content, prerequisites and instructions to validate the +build of the CMSIS-DSP library. This is done by processing input data sets using the DSP Library +functions executing on a target simulator or hardware. The output data sets are then compared +with the reference data set produced by unoptimized DSP functions and a Signal to Noise Ratio (SNR) +is computed. If the SNR is below a defined threshold the test is considered "passed". + + +Folder structure +---------------- + .\DSP_Lib_TestSuite Batch files for building the reference libraries and running the tests. + .\DSP_Lib_TestSuite\Common + .\DSP_Lib_TestSuite\Common\inc DSP_Lib test include files + .\DSP_Lib_TestSuite\Common\JTest JTEST Test Framework + INI files for uVision + .\DSP_Lib_TestSuite\Common\platform ARM/GCC device startup/system files + .\DSP_Lib_TestSuite\Common\src DSP_Lib test source files + .\DSP_Lib_TestSuite\DspLibTest_FVP ARM/GCC DSP_Lib test projects for Fixed Virtual Platforms + .\DSP_Lib_TestSuite\DspLibTest_MPS2 ARM/GCC DSP_Lib test projects for MPS2 + .\DSP_Lib_TestSuite\DspLibTest_Simulator ARM/GCC DSP_Lib test projects for uVision simulator + .\DSP_Lib_TestSuite\RefLibs ARM/GCC DSP_Lib reference libraries (and projects) + + + +Prerequisites +-------------- + - Python (running on Windows). Tested with ActivePython 2.7.8.10. + - Keil MDK-ARM (tested with MDK-ARM 5.22: http://www2.keil.com/mdk5) + - ULINKpro debug adapter (http://www2.keil.com/mdk5/ulink) + - MPS2 (Cortex-M Prototyping System:https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php) + - CMSIS 5.0.0 (https://github.com/ARM-software/CMSIS_5/releases/tag/5.0.0) + + +Setup +------ + - remove 'read-only' tag from folder .\CMSIS\DSP\Lib + (required for rebuild of the DSP_Lib libraries) + + - open a Windows command window in folder .\CMSIS\DSP\DSP_Lib_TestSuite. + + + +How to run the tests +--------------------- + +a) build the DSP_Lib libraries: + - batch file: buildDspLibs.bat + Note: only require if the DSP_Lib source code got updated or the desired configuration is missing + buildDspLibs.bat overwrites the prebuild libraries in .\CMSIS\DSP\Lib. + Log files of the build process are generated in folder .\CMSIS\DSP\DSP_Lib/[ARM|GCC] + - run: buildDspLibs.bat in a Windows command window in folder .\CMSIS\DSP\DSP_Lib_TestSuite + buildDspLibs ARM -> builds the ARMCC libraries + buildDspLibs GCC -> builds the GCC libraries + +b) build the reference libraries: + - batch file: buildRefLibs.bat + + Log files of the build process are generated in folder .\CMSIS\DSP\DSP_Lib_TestSuite\RefLibs/[ARM|GCC] + - run: buildRefLibs.bat in a Windows command window in folder .\CMSIS\DSP\DSP_Lib_TestSuite + buildRefLibs ARM -> builds the ARMCC reference libraries + buildRefLibs GCC -> builds the GCC reference libraries + +c) running an individual test using uVision (MDK-ARM): + - batch file: runTest.bat + - run: runTest.bat in a Windows command window in folder .\CMSIS\DSP\DSP_Lib_TestSuite + runTest -> prints usage information + e.g. runTest ARM cortexM4lf Simulator -> runs the test for toolchain ARM, Cortex-M4 littel endian with FPU, uVision Simulator. + + Tests running on MPS2 requires additional steps to setup. See section 'MPS2'. + +d) parsing the test output log file + - script: parseLog.py + - run: parseLog.py python script in a Windows command window in folder .\CMSIS\DSP\DSP_Lib_TestSuite + command line options should match the invocation of the runTest executed before. + e.g: runTest ARM cortexM4lf Simulator -> python parseLog.py ARM cortexM4lf Simulator + + - check the test log + depending on your test parameters change into the required folder + .\DSP_Lib_TestSuite\DspLibTest_[FVP|MPS2|Simulator]\[ARM|GCC]\Logs + the folder will contain the following files (e.g. for a 'runTest') : + DspLibTest_Simulator.log raw result of the last test run. + DspLibTest_Simulator_cortexM4lf.log raw result of a cortexM4lf test run + DspLibTest_Simulator_cortexM4lf_build.log build result of cortexM4lf test + DspLibTest_Simulator_cortexM4lf_parsed.log parsed log of raw result of a cortexM4lf test run + DspLibTest_Simulator_cortexM4lf_time.log log how long the test took (some tests e.g. M0 take really a long time!). + 'runTest' produces files of the format: DspLibTest__... + + +Differences between the tests for FVP, MPS2, Simulator +------------------------------------------------------ + - all tests are identical except for: + 'Simulator' uses uVision with uVision simulator and generates also code coverage information + can be used for little/big endian tests + ! do not use 'Simulator' for M7 with FPU -> no uVision simulation available. + ! do not use 'Simulator' for ARMv8-M devices -> no uVision simulation available. + 'MPS2' uses uVision with ULINKpro debugger and MPS2. No code coverage information is generated. + can be used for little endian only (because of the lack of MPS2 FPGA images). + 'FVP' uses uVision with Models debugger. No code coverage information is generated. + can be used for little/big endian tests. + ! config files must be prepared. + ! uVision target for big endianess are not yet prepared. + + +Setup 'MPS2' +------------- + - load the appropriate FPGA image to the MPS2 board matching the CPU of the test builds prior to running the test + - check if ULINKpro can connect with the configured debug connection (JTAG or SWD) as this must + match the protocol implemented in the FPGA image. + + +How to select tests for "run all tests" +---------------------------------------- + - edit .\CMSIS\DSP\DSP_Lib_TestSuite\Common\src\all_tests.c + comment out all unwanted test groups. + e.g. // JTEST_GROUP_CALL(complex_math_tests); + + - edit .\CMSIS\DSP\DSP_Lib_TestSuite\Common\src\/_group.c + comment out all unwanted sub test groups. + e.g. file .\DSP_Lib_TestSuite\Common\src\basic_math_tests\basic_math_test_group.c -> // JTEST_GROUP_CALL(abs_tests); + + - edit .\CMSIS\DSP\DSP_Lib_TestSuite\Common\src\/_tests.c + comment out all unwanted tests. + e.g. file .\DSP_Lib_TestSuite\Common\src\basic_math_tests\abs_tests.c -> // JTEST_TEST_CALL(arm_abs_f32_test); + + +Notes +----- + - How to use ARM Clang (ARM Compiler 6): + in uVision 'Options for Target' tab you can select which compiler to use + by default uVision uses ARMCC V5 for Cortex-M devices and ARMCLANG V6 only for ARMv8M. + Only ARMv8M cores have been tested using ARMCLANG + + - test data used for the tests is used as provided by DSP Concepts. + + - some tests run for a very long time before they finish. This is expected + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo_SV.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo_SV.txt new file mode 100644 index 0000000..ccf7531 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo_SV.txt @@ -0,0 +1,117 @@ +HowTo DSP_Lib_TestSuite (Source Variant) 18.02.2019 +====================================================== + +This file describes the folder structure, content, prerequisites and instructions to validate the +build of the CMSIS-DSP library. This is done by processing input data sets using the DSP Library +functions executing on a target simulator or hardware. The output data sets are then compared +with the reference data set produced by unoptimized DSP functions and a Signal to Noise Ratio (SNR) +is computed. If the SNR is below a defined threshold the test is considered "passed". + + +Folder structure +---------------- + .\DSP_Lib_TestSuite Batch files for building the reference libraries and running the tests. + .\DSP_Lib_TestSuite\Common + .\DSP_Lib_TestSuite\Common\inc DSP_Lib test include files + .\DSP_Lib_TestSuite\Common\JTest JTEST Test Framework + INI files for uVision + .\DSP_Lib_TestSuite\Common\platform ARM/GCC device startup/system files + .\DSP_Lib_TestSuite\Common\src DSP_Lib test source files + .\DSP_Lib_TestSuite\DspLibTest_FVP ARM/GCC DSP_Lib test projects for Fixed Virtual Platforms + .\DSP_Lib_TestSuite\DspLibTest_MPS2 ARM/GCC DSP_Lib test projects for MPS2 + .\DSP_Lib_TestSuite\DspLibTest_Simulator ARM/GCC DSP_Lib test projects for uVision simulator + .\DSP_Lib_TestSuite\RefLibs ARM/GCC DSP_Lib reference libraries (and projects) + + + +Prerequisites +-------------- + - Python (running on Windows). Tested with ActivePython 2.7.8.10. + - Keil MDK-ARM (tested with MDK-ARM 5.22: http://www2.keil.com/mdk5) + - ULINKpro debug adapter (http://www2.keil.com/mdk5/ulink) + - MPS2 (Cortex-M Prototyping System:https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php) + - CMSIS 5.0.0 (https://github.com/ARM-software/CMSIS_5/releases/tag/5.0.0) + + +Setup +------ + - open a Windows command window in folder .\CMSIS\DSP\DSP_Lib_TestSuite. + + + +How to run the tests +--------------------- + +a) running an individual test using uVision (MDK-ARM): + - batch file: runTest_SV.bat + - run: runTest_SV.bat in a Windows command window in folder .\CMSIS\DSP\DSP_Lib_TestSuite + runTest_SV -> prints usage information + e.g. runTest_SV ARM cortexM4lf Simulator -> runs the test for toolchain ARM, Cortex-M4 littel endian with FPU, uVision Simulator. + + Tests running on MPS2 requires additional steps to setup. See section 'MPS2'. + +d) parsing the test output log file + - script: parseLog_SV.py + - run: parseLog_SV.py python script in a Windows command window in folder .\CMSIS\DSP\DSP_Lib_TestSuite + command line options should match the invocation of the runTest executed before. + e.g: runTest ARM cortexM4lf Simulator -> python parseLog.py ARM cortexM4lf Simulator + + - check the test log + depending on your test parameters change into the required folder + .\DSP_Lib_TestSuite\DspLibTest_[FVP|MPS2|Simulator]\[ARM|GCC]\Logs + the folder will contain the following files (e.g. for a 'runTest') : + DspLibTest_Simulator.log raw result of the last test run. + DspLibTest_Simulator_cortexM4lf.log raw result of a cortexM4lf test run + DspLibTest_Simulator_cortexM4lf_build.log build result of cortexM4lf test + DspLibTest_Simulator_cortexM4lf_parsed.log parsed log of raw result of a cortexM4lf test run + DspLibTest_Simulator_cortexM4lf_time.log log how long the test took (some tests e.g. M0 take really a long time!). + 'runTest' produces files of the format: DspLibTest__... + + +Differences between the tests for FVP, MPS2, Simulator +------------------------------------------------------ + - all tests are identical except for: + 'Simulator' uses uVision with uVision simulator and generates also code coverage information + can be used for little/big endian tests + ! do not use 'Simulator' for M7 with FPU -> no uVision simulation available. + ! do not use 'Simulator' for ARMv8-M devices -> no uVision simulation available. + 'MPS2' uses uVision with ULINKpro debugger and MPS2. No code coverage information is generated. + can be used for little endian only (because of the lack of MPS2 FPGA images). + 'FVP' uses uVision with Models debugger. No code coverage information is generated. + can be used for little/big endian tests. + ! config files must be prepared. + ! uVision target for big endianess are not yet prepared. + + +Setup 'MPS2' +------------- + - load the appropriate FPGA image to the MPS2 board matching the CPU of the test builds prior to running the test + - check if ULINKpro can connect with the configured debug connection (JTAG or SWD) as this must + match the protocol implemented in the FPGA image. + + +How to select tests for "run all tests" +---------------------------------------- + - edit .\CMSIS\DSP\DSP_Lib_TestSuite\Common\src\all_tests.c + comment out all unwanted test groups. + e.g. // JTEST_GROUP_CALL(complex_math_tests); + + - edit .\CMSIS\DSP\DSP_Lib_TestSuite\Common\src\/_group.c + comment out all unwanted sub test groups. + e.g. file .\DSP_Lib_TestSuite\Common\src\basic_math_tests\basic_math_test_group.c -> // JTEST_GROUP_CALL(abs_tests); + + - edit .\CMSIS\DSP\DSP_Lib_TestSuite\Common\src\/_tests.c + comment out all unwanted tests. + e.g. file .\DSP_Lib_TestSuite\Common\src\basic_math_tests\abs_tests.c -> // JTEST_TEST_CALL(arm_abs_f32_test); + + +Notes +----- + - How to use ARM Clang (ARM Compiler 6): + in uVision 'Options for Target' tab you can select which compiler to use + by default uVision uses ARMCC V5 for Cortex-M devices and ARMCLANG V6 only for ARMv8M. + Only ARMv8M cores have been tested using ARMCLANG + + - test data used for the tests is used as provided by DSP Concepts. + + - some tests run for a very long time before they finish. This is expected + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/CMakeLists.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/CMakeLists.txt new file mode 100644 index 0000000..2fbb191 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/CMakeLists.txt @@ -0,0 +1,78 @@ +cmake_minimum_required (VERSION 3.6) + +project(DspRefLibs) + +# Needed to find the config modules +list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/../..) + + + + +set(REFSRC src/BasicMathFunctions/abs.c + src/BasicMathFunctions/add.c + src/BasicMathFunctions/dot_prod.c + src/BasicMathFunctions/mult.c + src/BasicMathFunctions/negate.c + src/BasicMathFunctions/offset.c + src/BasicMathFunctions/scale.c + src/BasicMathFunctions/shift.c + src/BasicMathFunctions/sub.c + src/ComplexMathFunctions/cmplx_conj.c + src/ComplexMathFunctions/cmplx_dot_prod.c + src/ComplexMathFunctions/cmplx_mag.c + src/ComplexMathFunctions/cmplx_mag_squared.c + src/ComplexMathFunctions/cmplx_mult_cmplx.c + src/ComplexMathFunctions/cmplx_mult_real.c + src/ControllerFunctions/pid.c + src/ControllerFunctions/sin_cos.c + src/FastMathFunctions/cos.c + src/FastMathFunctions/sin.c + src/FastMathFunctions/sqrt.c + src/FilteringFunctions/biquad.c + src/FilteringFunctions/conv.c + src/FilteringFunctions/correlate.c + src/FilteringFunctions/fir.c + src/FilteringFunctions/fir_decimate.c + src/FilteringFunctions/fir_interpolate.c + src/FilteringFunctions/fir_lattice.c + src/FilteringFunctions/fir_sparse.c + src/FilteringFunctions/iir_lattice.c + src/FilteringFunctions/lms.c + src/HelperFunctions/mat_helper.c + src/HelperFunctions/ref_helper.c + src/Intrinsics/intrinsics.c + src/MatrixFunctions/mat_add.c + src/MatrixFunctions/mat_cmplx_mult.c + src/MatrixFunctions/mat_inverse.c + src/MatrixFunctions/mat_mult.c + src/MatrixFunctions/mat_scale.c + src/MatrixFunctions/mat_sub.c + src/MatrixFunctions/mat_trans.c + src/StatisticsFunctions/max.c + src/StatisticsFunctions/mean.c + src/StatisticsFunctions/min.c + src/StatisticsFunctions/power.c + src/StatisticsFunctions/rms.c + src/StatisticsFunctions/std.c + src/StatisticsFunctions/var.c + src/SupportFunctions/copy.c + src/SupportFunctions/fill.c + src/SupportFunctions/fixed_to_fixed.c + src/SupportFunctions/fixed_to_float.c + src/SupportFunctions/float_to_fixed.c + src/TransformFunctions/bitreversal.c + src/TransformFunctions/cfft.c + src/TransformFunctions/dct4.c + src/TransformFunctions/rfft.c + ) + +add_library(DspRefLibs STATIC ${REFSRC}) + +include(config) +configdsp(DspRefLibs ../../Source) + +### Includes +target_include_directories(DspRefLibs PUBLIC "inc") +target_include_directories(DspRefLibs PUBLIC "../../Include") + + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/inc/ref.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/inc/ref.h new file mode 100644 index 0000000..69d83d1 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/inc/ref.h @@ -0,0 +1,1401 @@ + +#ifndef _REF_H +#define _REF_H + +#include +#include +#include "arm_math.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ +// typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ +// typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ +// typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ +// typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ +// typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ +// typedef double float64_t; + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + REF_Q7 = 0, + REF_Q15, + REF_Q31, + REF_F32, + } dataType; + + +#ifndef FLT_MAX +#define FLT_MAX 3.40282347e+38F +#endif + +#define DBL_MAX 1.79769313486231571e+308 + +#ifndef FLT_MIN +#define FLT_MIN 1.175494351e-38F +#endif +#define DBL_MIN 2.22507385850720138e-308 + +#define SCHAR_MIN (-128) + /* mimimum value for an object of type signed char */ +#define SCHAR_MAX 127 + /* maximum value for an object of type signed char */ +#define UCHAR_MAX 255 + /* maximum value for an object of type unsigned char */ +#define SHRT_MIN (-0x8000) + /* minimum value for an object of type short int */ +#define SHRT_MAX 0x7fff + /* maximum value for an object of type short int */ +#define USHRT_MAX 65535 + /* maximum value for an object of type unsigned short int */ +#define INT_MIN (~0x7fffffff) /* -2147483648 and 0x80000000 are unsigned */ + /* minimum value for an object of type int */ +#define INT_MAX 0x7fffffff + /* maximum value for an object of type int */ +#define UINT_MAX 0xffffffffU + /* maximum value for an object of type unsigned int */ +#define LONG_MIN (~0x7fffffffL) + /* minimum value for an object of type long int */ +#define LONG_MAX 0x7fffffffL + /* maximum value for an object of type long int */ +#define ULONG_MAX 0xffffffffUL + /* maximum value for an object of type unsigned long int */ + + /* + * Ref Lib Global Variables + */ +extern float32_t scratchArray[]; +extern arm_cfft_instance_f32 ref_cfft_sR_f32_len8192; + + /* + * Ref Lib Functions + */ + + /* + * Helper Functions + */ +q31_t ref_sat_n(q31_t num, uint32_t bits); + +q31_t ref_sat_q31(q63_t num); + +q15_t ref_sat_q15(q31_t num); + +q7_t ref_sat_q7(q15_t num); + +float32_t ref_pow(float32_t a, uint32_t b); + +extern float32_t tempMatrixArray[]; + +float32_t ref_detrm(float32_t *pSrc, float32_t *temp, uint32_t size); + +void ref_cofact(float32_t *pSrc, float32_t *pDst, float32_t *temp, uint32_t size); + +float64_t ref_detrm64(float64_t *pSrc, float64_t *temp, uint32_t size); + +void ref_cofact64(float64_t *pSrc, float64_t *pDst, float64_t *temp, uint32_t size); + + /* + * Basic Math Functions + */ +void ref_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + +void ref_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + +void ref_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + +void ref_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + +void ref_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + +void ref_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + +void ref_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + +void ref_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + +void ref_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + +void ref_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + +void ref_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + +void ref_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + +void ref_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + +void ref_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + +void ref_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + +void ref_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + +void ref_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + +void ref_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + +void ref_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + +void ref_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + +void ref_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + +void ref_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + +void ref_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + +void ref_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + +void ref_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + +void ref_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + +void ref_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /* + * Complex Math Functions + */ +void ref_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + +void ref_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + +void ref_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + +void ref_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + +void ref_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + +void ref_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + +void ref_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + +void ref_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + +void ref_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /* + * Controller Functions + */ +void ref_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + +void ref_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + +float32_t ref_pid_f32( + arm_pid_instance_f32 * S, + float32_t in); + +q31_t ref_pid_q31( + arm_pid_instance_q31 * S, + q31_t in); + +q15_t ref_pid_q15( + arm_pid_instance_q15 * S, + q15_t in); + + /* + * Fast Math Functions + */ +#define ref_sin_f32(a) sinf(a) + +q31_t ref_sin_q31(q31_t x); + +q15_t ref_sin_q15(q15_t x); + +#define ref_cos_f32(a) cosf(a) + +q31_t ref_cos_q31(q31_t x); + +q15_t ref_cos_q15(q15_t x); + +arm_status ref_sqrt_q31(q31_t in, q31_t * pOut); + +arm_status ref_sqrt_q15(q15_t in, q15_t * pOut); + + /* + * Filtering Functions + */ +void ref_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + +arm_status ref_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +void ref_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + +void ref_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + +arm_status ref_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +arm_status ref_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +void ref_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + +#define ref_conv_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + pScratch1, pScratch2) \ + ref_conv_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +void ref_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + +void ref_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + +arm_status ref_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +#define ref_conv_partial_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + firstIndex, numPoints, \ + pScratch1, pScratch2) \ + ref_conv_partial_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + firstIndex, numPoints) + +arm_status ref_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +arm_status ref_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + +void ref_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + +#define ref_conv_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + pScratch1, pScratch2) \ + ref_conv_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +arm_status ref_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +#define ref_conv_partial_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + firstIndex, numPoints, \ + pScratch1, pScratch2) \ + ref_conv_partial_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + firstIndex, numPoints) + +void ref_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + +void ref_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + +void ref_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + +void ref_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + +#define ref_correlate_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + pScratch1) \ + ref_correlate_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +void ref_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + +void ref_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + +void ref_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + +#define ref_correlate_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + pScratch1, pScratch2) \ + ref_correlate_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +void ref_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + +void ref_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + +void ref_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + +void ref_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t *pSrc, + q7_t *pDst, + q7_t *pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + +void ref_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + +void ref_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + +void ref_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + +void ref_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + +void ref_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + +void ref_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + +void ref_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /* + * Matrix Functions + */ +arm_status ref_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + +arm_status ref_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + +arm_status ref_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_inverse_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst); + +arm_status ref_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + +/* Alias for testing purposes*/ +#define ref_mat_mult_fast_q31 ref_mat_mult_q31 + +arm_status ref_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + +/* Alias for testing purposes*/ +#define ref_mat_mult_fast_q15 ref_mat_mult_q15 + +arm_status ref_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scale, + int32_t shift, + arm_matrix_instance_q31 * pDst); + +arm_status ref_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scale, + int32_t shift, + arm_matrix_instance_q15 * pDst); + +arm_status ref_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + +arm_status ref_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + +arm_status ref_mat_trans_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst); + +arm_status ref_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + +arm_status ref_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + +arm_status ref_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + +arm_status ref_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /* + * Statistics Functions + */ +void ref_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +void ref_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +void ref_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +void ref_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +void ref_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +void ref_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +void ref_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + +void ref_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + +void ref_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +void ref_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +void ref_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +void ref_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +void ref_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +void ref_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + +void ref_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + +void ref_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +void ref_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +void ref_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +void ref_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + +void ref_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +void ref_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +void ref_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + +void ref_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +void ref_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +void ref_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /* + * Support Functions + */ +void ref_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + +void ref_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +void ref_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + +void ref_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + +void ref_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_q63_to_float( + q63_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /* + * Transform Functions + */ +void ref_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void ref_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void ref_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void ref_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + +void ref_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + +void ref_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + +void ref_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + +void ref_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +void ref_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + +void ref_rfft_f32( + arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + +void ref_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + +void ref_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + +void ref_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + +void ref_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + +void ref_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + +void ref_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /* + * Intrinsics + */ +q31_t ref__QADD8(q31_t x, q31_t y); +q31_t ref__QSUB8(q31_t x, q31_t y); +q31_t ref__QADD16(q31_t x, q31_t y); +q31_t ref__SHADD16(q31_t x, q31_t y); +q31_t ref__QSUB16(q31_t x, q31_t y); +q31_t ref__SHSUB16(q31_t x, q31_t y); +q31_t ref__QASX(q31_t x, q31_t y); +q31_t ref__SHASX(q31_t x, q31_t y); +q31_t ref__QSAX(q31_t x, q31_t y); +q31_t ref__SHSAX(q31_t x, q31_t y); +q31_t ref__SMUSDX(q31_t x, q31_t y); +q31_t ref__SMUADX(q31_t x, q31_t y); +q31_t ref__QADD(q31_t x, q31_t y); +q31_t ref__QSUB(q31_t x, q31_t y); +q31_t ref__SMLAD(q31_t x, q31_t y, q31_t sum); +q31_t ref__SMLADX(q31_t x, q31_t y, q31_t sum); +q31_t ref__SMLSDX(q31_t x, q31_t y, q31_t sum); +q63_t ref__SMLALD(q31_t x, q31_t y, q63_t sum); +q63_t ref__SMLALDX(q31_t x, q31_t y, q63_t sum); +q31_t ref__SMUAD(q31_t x, q31_t y); +q31_t ref__SMUSD(q31_t x, q31_t y); +q31_t ref__SXTB16(q31_t x); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/BasicMathFunctions.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/BasicMathFunctions.c new file mode 100644 index 0000000..3f4dfbc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/BasicMathFunctions.c @@ -0,0 +1,11 @@ + +#include "abs.c" +#include "add.c" +#include "dot_prod.c" +#include "mult.c" +#include "negate.c" +#include "offset.c" +#include "scale.c" +#include "shift.c" +#include "sub.c" + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c new file mode 100644 index 0000000..9aba7d1 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c @@ -0,0 +1,53 @@ +#include "ref.h" + +void ref_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 14; //16.48 + } + *result = sum; +} + +void ref_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t i; + q63_t sum = 0.0f; + + for(i=0;i> 32; + temp = temp << 1; + pDst[i] = ref_sat_q31(temp); + } +} + +void ref_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + q31_t temp; + + for(i=0;i> 15; //this comment is for JD, this is specifically 15 and not 16 like the q31 case might imply. This is because CMSIS DSP lib does it this way. No other reason. + pDst[i] = ref_sat_q15(temp); + } +} + +void ref_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + q15_t temp; + + for(i=0;i> 7; + pDst[i] = ref_sat_q7(temp); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c new file mode 100644 index 0000000..7ee1299 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c @@ -0,0 +1,53 @@ +#include "ref.h" + +void ref_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 32; + if (sign) + pDst[i] = temp >> -kShift; + else + pDst[i] = ref_sat_q31( (q63_t)temp << kShift ); + } +} + +void ref_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + int8_t kShift = 15 - shift; /* Shift to apply after scaling */ + + for(i=0;i> kShift); + } +} + +void ref_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + int8_t kShift = 7 - shift; /* Shift to apply after scaling */ + + for(i=0;i> kShift); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c new file mode 100644 index 0000000..7d8a049 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c @@ -0,0 +1,73 @@ +#include "ref.h" + +void ref_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + if (shiftBits < 0) + { + for(i=0;i> -shiftBits; + } + } +} + +void ref_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + if (shiftBits < 0) + { + for(i=0;i> -shiftBits; + } + } +} + +void ref_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + if (shiftBits < 0) + { + for(i=0;i> -shiftBits; + } + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c new file mode 100644 index 0000000..996459b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c @@ -0,0 +1,57 @@ +#include "ref.h" + +void ref_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 14) - (((q63_t)pSrcA[i+1] * pSrcB[i+1]) >> 14); + sumi += (((q63_t)pSrcA[i] * pSrcB[i+1]) >> 14) + (((q63_t)pSrcA[i+1] * pSrcB[i] ) >> 14); + } + + *realResult = sumr; + *imagResult = sumi; +} + +void ref_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult) +{ + q63_t sumr, sumi; + uint32_t i; + + sumr = 0; + sumi = 0; + + for(i=0;i> 6); + *imagResult = (q31_t)(sumi >> 6); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c new file mode 100644 index 0000000..1c2ddc8 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c @@ -0,0 +1,49 @@ +#include "ref.h" + +void ref_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + + for(i=0;i> 33); + acc1 = (q31_t)(((q63_t)pSrc[i+1] * pSrc[i+1]) >> 33); + out = acc0 + acc1; + *pDst++ = (q31_t)(sqrtf((float)out / 2147483648.0f) * 2147483648.0f); + } +} + +void ref_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + q31_t acc0,acc1; + q15_t out; + + for(i=0;i> 17); + *pDst++ = (q15_t)(sqrtf((float)out / 32768.0f) * 32768.0f); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.c new file mode 100644 index 0000000..6dd8681 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.c @@ -0,0 +1,46 @@ +#include "ref.h" + +void ref_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + + for(i=0;i> 33); + acc1 = (q31_t)(((q63_t)pSrc[i+1] * pSrc[i+1]) >> 33); + *pDst++ = acc0 + acc1; + } +} + +void ref_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + q31_t acc0,acc1; + + for(i=0;i> 17); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c new file mode 100644 index 0000000..61ac49c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c @@ -0,0 +1,56 @@ +#include "ref.h" + +void ref_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + + for(i=0;i> 33; + mul2 = ((q63_t)pSrcA[i+1] * pSrcB[i+1]) >> 33; + mul3 = ((q63_t)pSrcA[i] * pSrcB[i+1]) >> 33; + mul4 = ((q63_t)pSrcA[i+1] * pSrcB[i]) >> 33; + pDst[i] = mul1 - mul2; + pDst[i+1] = mul3 + mul4; + } +} + +void ref_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + q31_t mul1, mul2, mul3, mul4; + + for(i=0;i> 17; + mul2 = ((q31_t)pSrcA[i+1] * pSrcB[i+1]) >> 17; + mul3 = ((q31_t)pSrcA[i] * pSrcB[i+1]) >> 17; + mul4 = ((q31_t)pSrcA[i+1] * pSrcB[i]) >> 17; + pDst[i] = mul1 - mul2; + pDst[i+1] = mul3 + mul4; + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.c new file mode 100644 index 0000000..c273fd3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.c @@ -0,0 +1,52 @@ +#include "ref.h" + +void ref_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t i; + + for(i=0;i> 32; + tempI = ((q63_t) pSrcCmplx[2*i+1] * pSrcReal[i]) >> 32; + pCmplxDst[2*i+0] = ref_sat_n(tempR, 31) << 1; + pCmplxDst[2*i+1] = ref_sat_n(tempI, 31) << 1; + } +} + +void ref_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t i; + q31_t tempR, tempI; + + for(i=0;i> 15; + tempI = ((q31_t) pSrcCmplx[2*i+1] * pSrcReal[i]) >> 15; + pCmplxDst[2*i+0] = ref_sat_q15(tempR); + pCmplxDst[2*i+1] = ref_sat_q15(tempI); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/ControllerFunctions.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/ControllerFunctions.c new file mode 100644 index 0000000..0c39953 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/ControllerFunctions.c @@ -0,0 +1,4 @@ + +#include "pid.c" +#include "sin_cos.c" + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c new file mode 100644 index 0000000..652991e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c @@ -0,0 +1,97 @@ +#include "ref.h" + +float32_t ref_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) +{ + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = S->state[2] + S->A0 * in + S->A1 * S->state[0] + S->A2 * S->state[1]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +q31_t ref_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) +{ + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +q15_t ref_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) +{ + q63_t acc; + q15_t out; + q15_t A1, A2; + +#if defined (ARM_MATH_DSP) + +#ifndef ARM_MATH_BIG_ENDIAN + A2 = S->A1 >> 16; + A1 = (q15_t)S->A1; +#else + A1 = S->A1 >> 16; + A2 = (q15_t)S->A1; +#endif + +#else + + A1 = S->A1; + A2 = S->A2; + +#endif + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) A1 * S->state[0]; + acc += (q31_t) A2 * S->state[1]; + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = ref_sat_q15(acc >> 15); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c new file mode 100644 index 0000000..3dd3955 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c @@ -0,0 +1,21 @@ +#include "ref.h" + +void ref_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal) +{ + //theta is given in degrees + *pSinVal = sinf(theta * 6.28318530717959f / 360.0f); + *pCosVal = cosf(theta * 6.28318530717959f / 360.0f); +} + +void ref_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal) +{ + //theta is given in the range [-1,1) to represent [-pi,pi) + *pSinVal = (q31_t)(sinf((float32_t)theta * 3.14159265358979f / 2147483648.0f) * 2147483648.0f); + *pCosVal = (q31_t)(cosf((float32_t)theta * 3.14159265358979f / 2147483648.0f) * 2147483648.0f); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/FastMathFunctions.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/FastMathFunctions.c new file mode 100644 index 0000000..bc59cb4 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/FastMathFunctions.c @@ -0,0 +1,5 @@ + +#include "cos.c" +#include "sin.c" +#include "sqrt.c" + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.c new file mode 100644 index 0000000..245942f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.c @@ -0,0 +1,11 @@ +#include "ref.h" + +q31_t ref_cos_q31(q31_t x) +{ + return (q31_t)(cosf((float32_t)x * 6.28318530717959f / 2147483648.0f) * 2147483648.0f); +} + +q15_t ref_cos_q15(q15_t x) +{ + return (q15_t)(cosf((float32_t)x * 6.28318530717959f / 32768.0f) * 32768.0f); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c new file mode 100644 index 0000000..ecd4aa0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c @@ -0,0 +1,11 @@ +#include "ref.h" + +q31_t ref_sin_q31(q31_t x) +{ + return (q31_t)(sinf((float32_t)x * 6.28318530717959f / 2147483648.0f) * 2147483648.0f); +} + +q15_t ref_sin_q15(q15_t x) +{ + return (q15_t)(sinf((float32_t)x * 6.28318530717959f / 32768.0f) * 32768.0f); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.c new file mode 100644 index 0000000..30b42ee --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.c @@ -0,0 +1,15 @@ +#include "ref.h" + +arm_status ref_sqrt_q31(q31_t in, q31_t * pOut) +{ + *pOut = (q31_t)(sqrtf((float32_t)in / 2147483648.0f) * 2147483648.0f); + + return ARM_MATH_SUCCESS; +} + +arm_status ref_sqrt_q15(q15_t in, q15_t * pOut) +{ + *pOut = (q15_t)(sqrtf((float32_t)in / 32768.0f) * 32768.0f); + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/FilteringFunctions.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/FilteringFunctions.c new file mode 100644 index 0000000..8faec35 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/FilteringFunctions.c @@ -0,0 +1,12 @@ + +#include "biquad.c" +#include "conv.c" +#include "correlate.c" +#include "fir.c" +#include "fir_decimate.c" +#include "fir_interpolate.c" +#include "fir_lattice.c" +#include "fir_sparse.c" +#include "iir_lattice.c" +#include "lms.c" + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c new file mode 100644 index 0000000..1eb7667 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c @@ -0,0 +1,713 @@ +#include "ref.h" + +void ref_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn; /* temporary input */ + float32_t d1, d2; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc = (b0 * Xn) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = (b1 * Xn + a1 * acc) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn) + (a2 * acc); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + + +void ref_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc1a, acc1b; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1a, Xn1b; /* temporary input */ + float32_t d1a, d2a, d1b, d2b; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn1a = *pIn++; //Channel a + Xn1b = *pIn++; //Channel b + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1a; + *pState++ = d2a; + *pState++ = d1b; + *pState++ = d2b; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} + +void ref_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + float64_t *pIn = pSrc; /* source pointer */ + float64_t *pOut = pDst; /* destination pointer */ + float64_t *pState = S->pState; /* State pointer */ + float64_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float64_t acc; /* accumulator */ + float64_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float64_t Xn; /* temporary input */ + float64_t d1, d2; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc = (b0 * Xn) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = (b1 * Xn + a1 * acc) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn) + (a2 * acc); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* Simulates the accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t Xn; /* temporary input */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (q63_t)Xn*b0 + (q63_t)Xn1*b1 + (q63_t)Xn2*b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q63_t acc; /* accumulator */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q31_t *pState = S->pState; /* pState pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q63_t) b0 *Xn; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) b1 *Xn1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t) b2 *Xn2; + /* acc += a1 * y[n-1] */ + acc += (q63_t) a1 *Yn1; + /* acc += a2 * y[n-2] */ + acc += (q63_t) a2 *Yn2; + + /* The result is converted to 1.31 */ + acc = acc >> lShift; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q31_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + + +void ref_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t acc = 0; /* accumulator */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q31_t *pState = S->pState; /* pState pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + mult_32x32_keep32_R(acc, b0, Xn); + multAcc_32x32_keep32_R(acc, b1, Xn1); + multAcc_32x32_keep32_R(acc, b2, Xn2); + multAcc_32x32_keep32_R(acc, a1, Yn1); + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 */ + acc <<= shift; + + /* Every time after the output is computed state should be updated. */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* Store the output in the destination buffer. */ + *pOut++ = acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q31_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (q31_t)b0*Xn + (q31_t)b1*Xn1 + (q31_t)b2*Xn2 + (q31_t)a1*Yn1 + (q31_t)a2*Yn2; + + /* The result is converted to 1.15 */ + acc = ref_sat_q15(acc >> shift); + + /* Every time after the output is computed state should be updated. */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q63_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (q31_t)b0*Xn + (q31_t)b1*Xn1 + (q31_t)b2*Xn2 + (q31_t)a1*Yn1 + (q31_t)a2*Yn2; + + /* The result is converted to 1.15 */ + acc = ref_sat_q15(acc >> shift); + + /* Every time after the output is computed state should be updated. */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c new file mode 100644 index 0000000..b10c874 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c @@ -0,0 +1,350 @@ +#include "ref.h" + +void ref_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += pSrcB[i - j] * pSrcA[j]; + } + } + /* Store the output in the destination buffer */ + pDst[i] = sum; + } +} + +arm_status ref_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_f32(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} + +void ref_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q63_t) pSrcA[j] * (pSrcB[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t)(sum >> 31U); + } +} + +void ref_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum = (q31_t) ((((q63_t)sum << 32) + + ((q63_t)pSrcA[j] * pSrcB[i - j])) >> 32); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t)(sum << 1U); + } +} + +arm_status ref_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_q31(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} + +arm_status ref_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_fast_q31(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} + +void ref_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } +} + +arm_status ref_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } + + return ARM_MATH_SUCCESS; +} + +void ref_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum >> 15U; + } +} + +void ref_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } +} + +arm_status ref_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_q15(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} + +arm_status ref_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_fast_q15(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} + + +void ref_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q15_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t)ref_sat_q7(sum >> 7); + } +} + +arm_status ref_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_q7(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c new file mode 100644 index 0000000..9ce170c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c @@ -0,0 +1,513 @@ +#include "ref.h" + +void ref_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + float32_t *pIn1 = pSrcA; /* inputA pointer */ + float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. + * srcB is always made to slide across srcA. + * So srcBLen is always considered as shorter or equal to srcALen + * But CORR(x, y) is reverse of CORR(y, x) + * So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer + * and a variable, inv is set to 1 + * If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs + * If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer + * If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer + * Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. + */ + + /* Calculate the length of the remaining sequence */ + tot = srcALen + srcBLen - 2U; + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + /* Initialise the pointer after zero padding */ + pDst += srcALen - srcBLen; + } + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + srcALen - 1U; + + /* Initialisation of the pointer after zero padding */ + pDst += tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += pIn1[j] * pIn2[-((int32_t)i - j)]; + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } +} + +void ref_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + q31_t *pIn1 = pSrcA; /* inputA pointer */ + q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate correlation for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to correlation equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q31_t)(sum >> 31U); + else + *pDst++ = (q31_t)(sum >> 31U); + } +} + +void ref_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + q31_t *pIn1 = pSrcA; /* inputA pointer */ + q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate correlation for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to correlation equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)])) >> 32); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q31_t)(sum << 1U); + else + *pDst++ = (q31_t)(sum << 1U); + } +} + +void ref_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + q15_t *pIn1 = pSrcA; /* inputA pointer */ + q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t) ref_sat_q15(sum >> 15U); + else + *pDst++ = (q15_t) ref_sat_q15(sum >> 15U); + } +} + +void ref_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + q15_t *pIn1 = pSrcA; /* inputA pointer */ + q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t)(sum >> 15U); + else + *pDst++ = (q15_t)(sum >> 15U); + } +} + +void ref_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + q15_t *pIn1 = pSrcA; /* inputA pointer */ + q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q31_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t) ref_sat_q15(sum >> 15U); + else + *pDst++ = (q15_t) ref_sat_q15(sum >> 15U); + } +} + +void ref_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + q7_t *pIn1 = pSrcA; /* inputA pointer */ + q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q7_t) __SSAT((sum >> 7U), 8U); + else + *pDst++ = (q7_t) __SSAT((sum >> 7U), 8U); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c new file mode 100644 index 0000000..40ab773 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c @@ -0,0 +1,325 @@ +#include "ref.h" + +void ref_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counters */ + float32_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;ipState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counter */ + q63_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;i> 31); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counter */ + q31_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;i> 32); + } + + /* The result is store in the destination buffer. */ + *pDst++ = (q31_t)(acc << 1); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counter */ + q63_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;i> 15); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counter */ + q31_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;i> 15); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counter */ + q31_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;i> 7); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t sum0; /* Accumulator */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0.0f; + + for(i=0;iM; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement the loop counter */ + blkCnt--; + } + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy numTaps number of values */ + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for(i=0;iM; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for(i=0;i> 32); + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 << 1); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for(i=0;iM; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = ref_sat_q15(sum0 >> 15); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for(i=0;iM; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = ref_sat_q15(sum0 >> 15); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c new file mode 100644 index 0000000..bfc5c09 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c @@ -0,0 +1,291 @@ +#include "ref.h" + +void ref_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum; /* Accumulator */ + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */ + + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + phaseLen - 1; + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + i - 1; + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum += *ptr1++ * *ptr2; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + tapCnt = phaseLen - 1U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} + +void ref_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum; /* Accumulator */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */ + + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + (q31_t)phaseLen - 1; + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + i - 1; + + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Read the coefficient */ + c0 = *(ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the input sample */ + x0 = *ptr1++; + + /* Perform the multiply-accumulate */ + sum += (q63_t) x0 *c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t)(sum >> 31); + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + tapCnt = phaseLen - 1U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} + +void ref_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum; /* Accumulator */ + q15_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + phaseLen - 1; + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + i - 1; + + /* Loop over the polyPhase length */ + tapCnt = (uint32_t)phaseLen; + + while (tapCnt > 0U) + { + /* Read the coefficient */ + c0 = *ptr2; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the input sample */ + x0 = *ptr1++; + + /* Perform the multiply-accumulate */ + sum += (q31_t) x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result after converting to 1.15 format in the destination buffer */ + *pDst++ = ref_sat_q15(sum >> 15); + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = (uint32_t) phaseLen - 1U; + + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } + +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c new file mode 100644 index 0000000..efaa44a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c @@ -0,0 +1,241 @@ +#include "ref.h" + +void ref_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* temporary state pointer */ + const float32_t *pk; /* temporary coefficient pointer */ + float32_t fcurr, fnext, gcurr, gnext; /* temporary variables */ + uint32_t numStages = S->numStages; /* Length of the filter */ + uint32_t blkCnt, stageCnt; /* temporary variables for counts */ + + pState = &S->pState[0]; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Initialize state pointer */ + px = pState; + + /* read g0(n-1) from state buffer */ + gcurr = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext = fcurr + ((*pk) * gcurr); + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext = (fcurr * (*pk++)) + gcurr; + + /* save f0(n) in state buffer */ + *px++ = fcurr; + + /* f1(n) is saved in fcurr + for next stage processing */ + fcurr = fnext; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext = fcurr + ((*pk) * gcurr); + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext = (fcurr * (*pk++)) + gcurr; + + /* f1(n) is saved in fcurr1 + for next stage processing */ + fcurr = fnext; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr; + + blkCnt--; + } +} + +void ref_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* temporary state pointer */ + const q31_t *pk; /* temporary coefficient pointer */ + q31_t fcurr, fnext, gcurr, gnext; /* temporary variables */ + uint32_t numStages = S->numStages; /* Length of the filter */ + uint32_t blkCnt, stageCnt; /* temporary variables for counts */ + + pState = &S->pState[0]; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Initialize state pointer */ + px = pState; + + /* read g0(n-1) from state buffer */ + gcurr = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr; + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr; + /* save g1(n) in state buffer */ + *px++ = fcurr; + + /* f1(n) is saved in fcurr1 + for next stage processing */ + fcurr = fnext; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr; + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr; + + /* f1(n) is saved in fcurr1 + for next stage processing */ + fcurr = fnext; + + stageCnt--; + + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr; + + blkCnt--; + + } +} + +void ref_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* temporary state pointer */ + const q15_t *pk; /* temporary coefficient pointer */ + q31_t fcurnt, fnext, gcurnt, gnext; /* temporary variables */ + uint32_t numStages = S->numStages; /* Length of the filter */ + uint32_t blkCnt, stageCnt; /* temporary variables for counts */ + + pState = &S->pState[0]; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurnt = *pSrc++; + + /* Initialize coeff pointer */ + pk = (pCoeffs); + + /* Initialize state pointer */ + px = pState; + + /* read g0(n-1) from state buffer */ + gcurnt = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext = ((gcurnt * (*pk)) >> 15U) + fcurnt; + fnext = ref_sat_q15(fnext); + + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext = ((fcurnt * (*pk++)) >> 15U) + gcurnt; + gnext = ref_sat_q15(gnext); + + /* save f0(n) in state buffer */ + *px++ = (q15_t) fcurnt; + + /* f1(n) is saved in fcurnt + for next stage processing */ + fcurnt = fnext; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g1(n-1) from state buffer */ + gcurnt = *px; + + /* save g0(n-1) in state buffer */ + *px++ = (q15_t) gnext; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext = ((gcurnt * (*pk)) >> 15U) + fcurnt; + fnext = ref_sat_q15(fnext); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext = ((fcurnt * (*pk++)) >> 15U) + gcurnt; + gnext = ref_sat_q15(gnext); + + + /* f1(n) is saved in fcurnt + for next stage processing */ + fcurnt = fnext; + + stageCnt--; + + } + + /* y(n) = fN(n) */ + *pDst++ = ref_sat_q15(fcurnt); + + + blkCnt--; + + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c new file mode 100644 index 0000000..060128f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c @@ -0,0 +1,485 @@ +#include "ref.h" + +void ref_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Scratch buffer pointer */ + float32_t *py = pState; /* Temporary pointers for state buffer */ + float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + float32_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + float32_t coeff = *pCoeffs++; /* Read the first coefficient value */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, + (int32_t *) pSrc, 1, blockSize); + + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer */ + px = pb; + + /* Working pointer for destination buffer */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = *px++ * coeff; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 1U; + + while (tapCnt > 0U) + { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer */ + px = pb; + + /* Working pointer for destination buffer */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } +} + +void ref_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Scratch buffer pointer */ + q31_t *py = pState; /* Temporary pointers for state buffer */ + q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q31_t *pOut; /* Destination pointer */ + q63_t out; /* Temporary output variable */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Filter order */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t in; + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, + (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in the destination buffer */ + *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 1U; + + while (tapCnt > 0U) + { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } + + /* Working output pointer is updated */ + pOut = pDst; + + /* Output is converted into 1.31 format. */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pIn = pSrc; /* Working pointer for input */ + q15_t *pOut = pDst; /* Working pointer for output */ + q15_t *px; /* Temporary pointers for scratch buffer */ + q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q15_t *py = pState; /* Temporary pointers for state buffer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Filter order */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q15_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t *pScr2 = pScratchOut; /* Working pointer for pScratchOut */ + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, delaySize, &readIndex, 1, + pb, pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) * px++ * coeff); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 1U; + + while (tapCnt > 0U) + { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, delaySize, &readIndex, 1, + pb, pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) * px++ * coeff; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ + /* Loop over the blockSize. */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16); + blkCnt--; + } +} + +void ref_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t *pSrc, + q7_t *pDst, + q7_t *pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *px; /* Scratch buffer pointer */ + q7_t *py = pState; /* Temporary pointers for state buffer */ + q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q7_t *pOut = pDst; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Filter order */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q7_t coeff = *pCoeffs++; /* Read the coefficient value */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q31_t in; + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1, + blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb, + (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + /* Loop over the blockSize */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) * px++ * coeff); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 1U; + + while (tapCnt > 0U) + { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb, + (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + /* Loop over the blockSize */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ + /* Loop over the blockSize. */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c new file mode 100644 index 0000000..7a0c91f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c @@ -0,0 +1,271 @@ +#include "ref.h" + +void ref_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t fcurr, fnext = 0, gcurr, gnext; /* Temporary variables for lattice stages */ + float32_t acc; /* Accumlator */ + uint32_t blkCnt, tapCnt; /* temporary variables for counts */ + float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* number of stages */ + float32_t *pState; /* State pointer */ + float32_t *pStateCurnt; /* State current pointer */ + + blkCnt = blockSize; + pState = &S->pState[0]; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize state read pointer */ + px1 = pState; + /* Initialize state write pointer */ + px2 = pState; + /* Set accumulator to zero */ + acc = 0.0f; + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Process sample for numStages */ + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = fcurr - (*pk) * gcurr; + gnext = fnext * (*pk++) + gcurr; + + /* Output samples for last taps */ + acc += gnext * (*pv++); + *px2++ = gnext; + fcurr = fnext; + + /* Decrementing loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += fnext * (*pv); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = acc; + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCurnt = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy the data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* number of stages */ + q31_t *pState; /* State pointer */ + q31_t *pStateCurnt; /* State current pointer */ + + blkCnt = blockSize; + pState = &S->pState[0]; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize state read pointer */ + px1 = pState; + /* Initialize state write pointer */ + px2 = pState; + /* Set accumulator to zero */ + acc = 0; + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = + ref_sat_q31(((q63_t) fcurr - + ((q31_t) (((q63_t) gcurr * (*pk)) >> 31)))); + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = + ref_sat_q31(((q63_t) gcurr + + ((q31_t) (((q63_t) fnext * (*pk++)) >> 31)))); + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q63_t) fnext *(*pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCurnt = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + uint32_t stgCnt; /* Temporary variables for counts */ + q63_t acc; /* Accumlator */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* number of stages */ + q15_t *pState; /* State pointer */ + q15_t *pStateCurnt; /* State current pointer */ + q15_t out; /* Temporary variable for output */ + + blkCnt = blockSize; + pState = &S->pState[0]; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize state read pointer */ + px1 = pState; + /* Initialize state write pointer */ + px2 = pState; + /* Set accumulator to zero */ + acc = 0; + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - ((gcurr * (*pk)) >> 15); + fnext = ref_sat_q15(fnext); + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = ((fnext * (*pk++)) >> 15) + gcurr; + gnext = ref_sat_q15(gnext); + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) ((fnext * (*pv++))); + + out = ref_sat_q15(acc >> 15); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + /* Points to the start of the state buffer */ + pStateCurnt = &S->pState[0]; + pState = &S->pState[blockSize]; + + stgCnt = numStages; + + /* copy data */ + while (stgCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + stgCnt--; + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.c new file mode 100644 index 0000000..2b7f3de --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.c @@ -0,0 +1,695 @@ +#include "ref.h" + +void ref_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w = 0.0f; /* weight factor */ + + e = 0.0f; + d = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[numTaps - 1U]); + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + sum = 0.0f; + + for(i=0;ipState[i] = pState[i]; + } +} + +void ref_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + d = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[numTaps - 1U]); + + for(blkCnt = blockSize; blkCnt > 0U; blkCnt--) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + sum = 0.0f; + + for(i=0;ienergy = energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + * start of the state buffer. This prepares the state buffer for the + * next function call. */ + for(i=0;ipState[i] = pState[i]; + } +} + +void ref_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t mu = S->mu; /* Adaptive factor */ + q31_t *px; /* Temporary pointer for state */ + q31_t *pb; /* Temporary pointer for coefficient buffer */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t e = 0; /* error of data sample */ + q31_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* temporary input */ + uint32_t uShift = (uint32_t)S->postShift + 1; + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for(blkCnt = blockSize; blkCnt > 0U; blkCnt--) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t)(*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Store the result from accumulator into the destination buffer. */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + *pOut++ = (q31_t)acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t)acc; + + *pErr++ = (q31_t)e; + + /* Weighting factor for the LMS version */ + alpha = (q31_t)(((q63_t)e * mu) >> 31); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t)(((q63_t) alpha * (*px++)) >> 32); + *pb = ref_sat_q31((q63_t)*pb + (coef << 1)); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + } + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Copy (numTaps - 1U) samples */ + tapCnt = numTaps - 1; + + /* Copy the data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t energy; /* Energy of the input */ + q63_t acc; /* Accumulator */ + q31_t e = 0, d = 0; /* error, reference data sample */ + q31_t w = 0, in; /* weight factor and state */ + q31_t x0; /* temporary variable to hold input sample */ + q63_t errorXmu; /* Temporary variables to store error and mu product and reciprocal of energy */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for(blkCnt = blockSize; blkCnt > 0U; blkCnt--) + { + + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy = (q31_t)((((q63_t)energy << 32) - (((q63_t)x0 * x0) << 1)) >> 32) & 0xffffffff; + energy = (q31_t)(((((q63_t)in * in) << 1) + ((q63_t)energy << 32)) >> 32) & 0xffffffff; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t)acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q31_t)acc; + *pErr++ = e; + + /* Calculation of product of (e * mu) */ + errorXmu = (q63_t)e * mu; + + /* Weighting factor for the normalized version */ + w = ref_sat_q31(errorXmu / (energy + DELTA_Q31)); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* coef is in 2.30 format */ + coef = (q31_t)(((q63_t)w * (*px++)) >> 32); + /* get coef in 1.31 format by left shifting */ + *pb = ref_sat_q31((q63_t)*pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState++; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q31_t)energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Loop for (numTaps - 1U) samples copy */ + tapCnt = numTaps - 1; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t mu = S->mu; /* Adaptive factor */ + q15_t *px; /* Temporary pointer for state */ + q15_t *pb; /* Temporary pointer for coefficient buffer */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q15_t e = 0; /* error of data sample */ + q15_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Teporary variable for coefficient */ + q31_t acc_l, acc_h; + int32_t lShift = 15 - (int32_t)S->postShift; /* Post shift */ + int32_t uShift = 32 - lShift; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for(blkCnt = blockSize; blkCnt > 0U; blkCnt--) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t)((q31_t)(*px++) * (*pb++)); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = ref_sat_q15(acc); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t)acc; + + /* Compute and store error */ + e = *pRef++ - (q15_t)acc; + + *pErr++ = (q15_t)e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q15_t)(((q31_t)e * mu) >> 15); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) ref_sat_q15(coef); + + /* Decrement the loop counter */ + tapCnt--; + } + } + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Copy (numTaps - 1U) samples */ + tapCnt = numTaps - 1; + + /* Copy the data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q31_t energy; /* Energy of the input */ + q63_t acc; /* Accumulator */ + q15_t e = 0, d = 0; /* error, reference data sample */ + q15_t w = 0, in; /* weight factor and state */ + q15_t x0; /* temporary variable to hold input sample */ + q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + //q31_t errorXmu; /* Temporary variables to store error and mu product and reciprocal of energy */ + q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Teporary variable for coefficient */ + q31_t acc_l, acc_h; + int32_t lShift = 15 - (int32_t)S->postShift; /* Post shift */ + int32_t uShift = 32 - lShift; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for(blkCnt = blockSize; blkCnt > 0U; blkCnt--) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= (((q31_t)x0 * x0) >> 15) & 0xffff; + energy += (((q31_t)in * in) >> 15) & 0xffff; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q31_t)*px++ * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = ref_sat_q15(acc); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q15_t) acc; + *pErr++ = e; + +#if 0 + /* Calculation of e * mu value */ + errorXmu = (q31_t) e * mu; + + /* Calculation of (e * mu) /energy value */ + acc = errorXmu / (energy + DELTA_Q15); +#endif + + /* Calculation of 1/energy */ + postShift = arm_recip_q15((q15_t) energy + DELTA_Q15, + &oneByEnergy, S->recipTable); + + /* Calculation of e * mu value */ + errorXmu = (q15_t) (((q31_t) e * mu) >> 15); + + /* Calculation of (e * mu) * (1/energy) value */ + acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift)); + + /* Weighting factor for the normalized version */ + w = ref_sat_q15((q31_t)acc); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = *pb + (((q31_t)w * (*px++)) >> 15); + *pb++ = ref_sat_q15(coef); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q15_t)energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy (numTaps - 1U) data */ + tapCnt = numTaps - 1; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/HelperFunctions.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/HelperFunctions.c new file mode 100644 index 0000000..aa5a40f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/HelperFunctions.c @@ -0,0 +1,4 @@ + +#include "mat_helper.c" +#include "ref_helper.c" + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c new file mode 100644 index 0000000..ee2be4e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c @@ -0,0 +1,193 @@ +#include "ref.h" + +float32_t ref_detrm(float32_t *pSrc, float32_t *temp, uint32_t size) +{ + float32_t s = 1, det = 0; + int i, j, m, n, c; + + if ( size == 1 ) + { + return ( pSrc[ 0 ] ); + } + else + { + det = 0; + + for ( c = 0;c < size;c++ ) + { + m = 0; + n = 0; + + for ( i = 0;i < size;i++ ) + { + for ( j = 0;j < size;j++ ) + { + temp[ i*size + j ] = 0; + + if ( i != 0 && j != c ) + { + temp[ m*(size-1) + n ] = pSrc[ i*size + j ]; + + if ( n < ( size - 2 ) ) + { + n++; + } + else + { + n = 0; + m++; + } + } + } + } + + det += s * ( pSrc[ c ] * ref_detrm( temp, temp + size*size, size - 1 ) ); + s = -s; + } + } + + return ( det ); +} + + +void ref_cofact(float32_t *pSrc, float32_t *pDst, float32_t *temp, uint32_t size) +{ + int p, q, m, n, i, j; + + if (size == 1) + { + pDst[0] = 1; + return; + } + + for ( q = 0;q < size;q++ ) + { + for ( p = 0;p < size;p++ ) + { + m = 0; + n = 0; + + for ( i = 0;i < size;i++ ) + { + for ( j = 0;j < size;j++ ) + { + temp[ i*size + j ] = 0; + + if ( i != q && j != p ) + { + temp[ m*(size-1) + n ] = pSrc[ i*size + j ]; + + if ( n < ( size - 2 ) ) + { + n++; + } + else + { + n = 0; + m++; + } + } + } + } + + pDst[ q*size + p ] = ref_pow( -1, q + p ) * ref_detrm( temp, temp + (size-1)*(size-1), size - 1 ); + } + } +} + + + +float64_t ref_detrm64(float64_t *pSrc, float64_t *temp, uint32_t size) +{ + float64_t s = 1, det = 0; + int i, j, m, n, c; + + if ( size == 1 ) + { + return ( pSrc[ 0 ] ); + } + else + { + det = 0; + + for ( c = 0;c < size;c++ ) + { + m = 0; + n = 0; + + for ( i = 0;i < size;i++ ) + { + for ( j = 0;j < size;j++ ) + { + temp[ i*size + j ] = 0; + + if ( i != 0 && j != c ) + { + temp[ m*(size-1) + n ] = pSrc[ i*size + j ]; + + if ( n < ( size - 2 ) ) + { + n++; + } + else + { + n = 0; + m++; + } + } + } + } + + det += s * ( pSrc[ c ] * ref_detrm64( temp, temp + size*size, size - 1 ) ); + s = -s; + } + } + + return ( det ); +} + + +void ref_cofact64(float64_t *pSrc, float64_t *pDst, float64_t *temp, uint32_t size) +{ + int p, q, m, n, i, j; + + if (size == 1) + { + pDst[0] = 1; + return; + } + + for ( q = 0;q < size;q++ ) + { + for ( p = 0;p < size;p++ ) + { + m = 0; + n = 0; + + for ( i = 0;i < size;i++ ) + { + for ( j = 0;j < size;j++ ) + { + temp[ i*size + j ] = 0; + + if ( i != q && j != p ) + { + temp[ m*(size-1) + n ] = pSrc[ i*size + j ]; + + if ( n < ( size - 2 ) ) + { + n++; + } + else + { + n = 0; + m++; + } + } + } + } + + pDst[ q*size + p ] = ref_pow( -1, q + p ) * ref_detrm64( temp, temp + (size-1)*(size-1), size - 1 ); + } + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c new file mode 100644 index 0000000..c749daf --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c @@ -0,0 +1,103 @@ +#include "ref.h" + +float32_t scratchArray[8192*2]; + +arm_cfft_instance_f32 ref_cfft_sR_f32_len8192 = { 8192, 0, 0, 0 }; + +q31_t ref_sat_n(q31_t num, uint32_t bits) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (bits - 1); i++) + { + posMax = posMax * 2; + } + + if (num > 0) + { + posMax = (posMax - 1); + + if (num > posMax) + { + num = posMax; + } + } + else + { + negMin = -posMax; + + if (num < negMin) + { + num = negMin; + } + } + return (num); +} + +q31_t ref_sat_q31(q63_t num) +{ + if (num > (q63_t)INT_MAX) + { + return INT_MAX; + } + else if (num < (q63_t)0xffffffff80000000ll) + { + return INT_MIN; + } + else + { + return (q31_t)num; + } +} + +q15_t ref_sat_q15(q31_t num) +{ + if (num > (q31_t)SHRT_MAX) + { + return SHRT_MAX; + } + else if (num < (q31_t)0xffff8000) + { + return SHRT_MIN; + } + else + { + return (q15_t)num; + } +} + +q7_t ref_sat_q7(q15_t num) +{ + if (num > (q15_t)SCHAR_MAX) + { + return SCHAR_MAX; + } + else if (num < (q15_t)0xff80) + { + return SCHAR_MIN; + } + else + { + return (q7_t)num; + } +} + +float32_t ref_pow(float32_t a, uint32_t b) +{ + uint32_t i; + float32_t r = a; + + for(i=1;i> 24) + ((y << 16) >> 24))), 8); + t = ref_sat_n(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = ref_sat_n(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + +} + +q31_t ref__QSUB8(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = ref_sat_n((r - s), 8); + s = ref_sat_n(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = ref_sat_n(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = ref_sat_n(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); + + return sum; +} + +q31_t ref__QADD16(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ref_sat_q15(r + s); + s = (q31_t)ref_sat_q15(((q31_t) ((x >> 16) + (y >> 16)))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + +} + +q31_t ref__SHADD16(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = (r + s) >> 1; + s = ((q31_t) (((x >> 16) + (y >> 16)) >> 1) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + +} + +q31_t ref__QSUB16(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ref_sat_q15(r - s); + s = (q31_t)ref_sat_q15(((q31_t) ((x >> 16) - (y >> 16)))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +q31_t ref__SHSUB16(q31_t x, q31_t y) +{ + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; +} + +q31_t ref__QASX(q31_t x, q31_t y) +{ + q31_t sum = 0; + q31_t xL, xH, yL, yH; + + // extract bottom halfword and sign extend + xL = (q15_t)(x & 0xffff); + // extract bottom halfword and sign extend + yL = (q15_t)(y & 0xffff); + // extract top halfword and sign extend + xH = (q15_t)(x >> 16); + // extract top halfword and sign extend + yH = (q15_t)(y >> 16); + + sum = (((q31_t)ref_sat_q15(xH + yL )) << 16) | + (((q31_t)ref_sat_q15(xL - yH )) & 0xffff); + + return sum; +} + +q31_t ref__SHASX(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = (r - (y >> 16)) / 2; + s = (((x >> 16) + s) << 15); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +q31_t ref__QSAX(q31_t x, q31_t y) +{ + q31_t sum = 0; + q31_t xL, xH, yL, yH; + + // extract bottom halfword and sign extend + xL = (q15_t)(x & 0xffff); + // extract bottom halfword and sign extend + yL = (q15_t)(y & 0xffff); + // extract top halfword and sign extend + xH = (q15_t)(x >> 16); + // extract top halfword and sign extend + yH = (q15_t)(y >> 16); + + sum = (((q31_t)ref_sat_q15(xH - yL )) << 16) | + (((q31_t)ref_sat_q15(xL + yH )) & 0xffff); + + return sum; +} + +q31_t ref__SHSAX(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = (r + (y >> 16)) / 2; + s = (((x >> 16) - s) << 15); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +q31_t ref__SMUSDX(q31_t x, q31_t y) +{ + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - ((q15_t) (x >> 16) * (q15_t) y))); +} + +q31_t ref__SMUADX(q31_t x, q31_t y) +{ + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + ((q15_t) (x >> 16) * (q15_t) y))); +} + +q31_t ref__QADD(q31_t x, q31_t y) +{ + return ref_sat_q31((q63_t) x + y); +} + +q31_t ref__QSUB(q31_t x, q31_t y) +{ + return ref_sat_q31((q63_t) x - y); +} + +q31_t ref__SMLAD(q31_t x, q31_t y, q31_t sum) +{ + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); +} + +q31_t ref__SMLADX(q31_t x, q31_t y, q31_t sum) +{ + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + ((q15_t) x * (q15_t) (y >> 16))); +} + +q31_t ref__SMLSDX(q31_t x, q31_t y, q31_t sum) +{ + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + ((q15_t) x * (q15_t) (y >> 16))); +} + +q63_t ref__SMLALD(q31_t x, q31_t y, q63_t sum) +{ + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); +} + +q63_t ref__SMLALDX(q31_t x, q31_t y, q63_t sum) +{ + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); +} + +q31_t ref__SMUAD(q31_t x, q31_t y) +{ + return (((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + +q31_t ref__SMUSD(q31_t x, q31_t y) +{ + return (-((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + +q31_t ref__SXTB16(q31_t x) +{ + return ((((x << 24) >> 24) & 0x0000FFFF) | (((x << 8) >> 8) & 0xFFFF0000)); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/MatrixFunctions.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/MatrixFunctions.c new file mode 100644 index 0000000..b611bfd --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/MatrixFunctions.c @@ -0,0 +1,9 @@ + +#include "mat_add.c" +#include "mat_cmplx_mult.c" +#include "mat_inverse.c" +#include "mat_mult.c" +#include "mat_scale.c" +#include "mat_sub.c" +#include "mat_trans.c" + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c new file mode 100644 index 0000000..7275b7a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c @@ -0,0 +1,58 @@ +#include "ref.h" + +arm_status ref_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = pSrcA->pData[i] + pSrcB->pData[i]; + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = ref_sat_q31( (q63_t)pSrcA->pData[i] + pSrcB->pData[i]); + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = ref_sat_q15( (q31_t)pSrcA->pData[i] + pSrcB->pData[i]); + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.c new file mode 100644 index 0000000..c1e3bff --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.c @@ -0,0 +1,118 @@ +#include "ref.h" + +arm_status ref_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + float32_t sumR,sumI; + float32_t a0,b0,c0,d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[2*(r*innerSize + i) + 0]; + b0 = pSrcA->pData[2*(r*innerSize + i) + 1]; + c0 = pSrcB->pData[2*(i*outC + c) + 0]; + d0 = pSrcB->pData[2*(i*outC + c) + 1]; + + sumR += a0 * c0 - b0 * d0; + sumI += b0 * c0 + a0 * d0; + } + + pDst->pData[2*(r*outC + c) + 0] = sumR; + pDst->pData[2*(r*outC + c) + 1] = sumI; + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + q63_t sumR,sumI; + q31_t a0,b0,c0,d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[2*(r*innerSize + i) + 0]; + b0 = pSrcA->pData[2*(r*innerSize + i) + 1]; + c0 = pSrcB->pData[2*(i*outC + c) + 0]; + d0 = pSrcB->pData[2*(i*outC + c) + 1]; + + sumR += (q63_t)a0 * c0 - (q63_t)b0 * d0; + sumI += (q63_t)b0 * c0 + (q63_t)a0 * d0; + } + + pDst->pData[2*(r*outC + c) + 0] = ref_sat_q31(sumR >> 31); + pDst->pData[2*(r*outC + c) + 1] = ref_sat_q31(sumI >> 31); + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + q63_t sumR,sumI; + q15_t a0,b0,c0,d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[2*(r*innerSize + i) + 0]; + b0 = pSrcA->pData[2*(r*innerSize + i) + 1]; + c0 = pSrcB->pData[2*(i*outC + c) + 0]; + d0 = pSrcB->pData[2*(i*outC + c) + 1]; + + sumR += (q31_t)a0 * c0 - (q31_t)b0 * d0; + sumI += (q31_t)b0 * c0 + (q31_t)a0 * d0; + } + + pDst->pData[2*(r*outC + c) + 0] = ref_sat_q15(sumR >> 15); + pDst->pData[2*(r*outC + c) + 1] = ref_sat_q15(sumI >> 15); + } + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.c new file mode 100644 index 0000000..4886bcc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.c @@ -0,0 +1,57 @@ +#include "ref.h" + +arm_status ref_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t det; + uint32_t i, size; + arm_matrix_instance_f32 tmp; + + tmp.numCols = pSrc->numCols; + tmp.numRows = pSrc->numRows; + tmp.pData = scratchArray; + + det = ref_detrm(pSrc->pData,scratchArray,pSrc->numCols); + + size = pSrc->numCols * pSrc->numCols; + + ref_cofact(pSrc->pData,scratchArray,scratchArray + size,pSrc->numCols); + + ref_mat_trans_f32(&tmp,pDst); + + for(i=0;ipData[i] /= det; + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_inverse_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + float64_t det; + uint32_t i, size; + arm_matrix_instance_f64 tmp; + + tmp.numCols = pSrc->numCols; + tmp.numRows = pSrc->numRows; + tmp.pData = (float64_t*)scratchArray; + + det = ref_detrm64(pSrc->pData,(float64_t*)scratchArray,pSrc->numCols); + + size = pSrc->numCols * pSrc->numCols; + + ref_cofact64(pSrc->pData,(float64_t*)scratchArray,(float64_t*)scratchArray + size,pSrc->numCols); + + ref_mat_trans_f64(&tmp,pDst); + + for(i=0;ipData[i] /= det; + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.c new file mode 100644 index 0000000..daffce6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.c @@ -0,0 +1,91 @@ +#include "ref.h" + +arm_status ref_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + float32_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[r*innerSize + i] * pSrcB->pData[i*outC + c]; + } + + pDst->pData[r*outC + c] = sum; + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + q63_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[r*innerSize + i]) * pSrcB->pData[i*outC + c]; + } + + pDst->pData[r*outC + c] = ref_sat_q31(sum >> 31); + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + q63_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[r*innerSize + i]) * pSrcB->pData[i*outC + c]; + } + + pDst->pData[r*outC + c] = ref_sat_q15(sum >> 15); + } + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c new file mode 100644 index 0000000..1b2a370 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c @@ -0,0 +1,64 @@ +#include "ref.h" + +arm_status ref_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + + for(i=0;ipData[i] = pSrc->pData[i] * scale; + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scale, + int32_t shift, + arm_matrix_instance_q31 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + int32_t totShift = shift + 1; + q31_t tmp; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + + for(i=0;ipData[i] * scale) >> 32; + pDst->pData[i] = ref_sat_q31((q63_t)tmp << totShift ); + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scale, + int32_t shift, + arm_matrix_instance_q15 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + int32_t totShift = 15 - shift; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + + for(i=0;ipData[i] = ref_sat_q15( ((q31_t)pSrc->pData[i] * scale) >> totShift); + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c new file mode 100644 index 0000000..048d157 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c @@ -0,0 +1,58 @@ +#include "ref.h" + +arm_status ref_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = pSrcA->pData[i] - pSrcB->pData[i]; + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = ref_sat_q31( (q63_t)pSrcA->pData[i] - pSrcB->pData[i]); + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = ref_sat_q15( (q31_t)pSrcA->pData[i] - pSrcB->pData[i]); + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.c new file mode 100644 index 0000000..b4fed2f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.c @@ -0,0 +1,77 @@ +#include "ref.h" + +arm_status ref_mat_trans_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + uint64_t r,c; + uint64_t numR = pSrc->numRows; + uint64_t numC = pSrc->numCols; + + for(r=0;rpData[c*numR + r] = pSrc->pData[r*numC + c]; + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + uint32_t r,c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for(r=0;rpData[c*numR + r] = pSrc->pData[r*numC + c]; + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + uint32_t r,c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for(r=0;rpData[c*numR + r] = pSrc->pData[r*numC + c]; + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + uint32_t r,c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for(r=0;rpData[c*numR + r] = pSrc->pData[r*numC + c]; + } + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/StatisticsFunctions.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/StatisticsFunctions.c new file mode 100644 index 0000000..426c3f7 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/StatisticsFunctions.c @@ -0,0 +1,8 @@ + +#include "max.c" +#include "mean.c" +#include "min.c" +#include "power.c" +#include "rms.c" +#include "std.c" +#include "var.c" diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c new file mode 100644 index 0000000..a4739d7 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c @@ -0,0 +1,85 @@ +#include "ref.h" + +void ref_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + uint32_t i, ind=0; + float32_t max=-FLT_MAX; + + for(i=0;i pSrc[i]) + { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} + +void ref_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + uint32_t i, ind=0; + q31_t min=INT_MAX; + + for(i=0;i pSrc[i]) + { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} + +void ref_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + uint32_t i, ind=0; + q15_t min=SHRT_MAX; + + for(i=0;i pSrc[i]) + { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} + +void ref_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + uint32_t i, ind=0; + q7_t min=SCHAR_MAX; + + for(i=0;i pSrc[i]) + { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.c new file mode 100644 index 0000000..6160bfe --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.c @@ -0,0 +1,61 @@ +#include "ref.h" + +void ref_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t i; + float32_t sumsq=0; + + for(i=0;i> 14; + } + *pResult = sumsq; +} + +void ref_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t i; + q63_t sumsq=0; + + for(i=0;i> 31; + tmp2 = ref_sat_q31(tmp1); + + /* GCC M0 problem: __aeabi_f2iz(QNAN) returns not 0 */ + help_float = (sqrtf((float)tmp2 / 2147483648.0f) * 2147483648.0f); + /* Checking for a NAN value in help_float */ + if (((*((int *)(&help_float))) & 0x7FC00000) == 0x7FC00000) { + help_float = 0; + } + *pResult = (q31_t)(help_float); + +// *pResult = (q31_t)(sqrtf((float)tmp2 / 2147483648.0f) * 2147483648.0f); +} + +void ref_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t i; + q63_t sumsq=0; + q31_t tmp1; + q15_t tmp2; + + for(i=0;i> 15; + tmp2 = ref_sat_q15(tmp1); + *pResult = (q15_t)(sqrtf((float)tmp2 / 32768.0f) * 32768.0f); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c new file mode 100644 index 0000000..148b5c7 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c @@ -0,0 +1,74 @@ +#include "ref.h" + +void ref_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t i; + float32_t sum=0, sumsq=0; + + if (blockSize == 1) + { + *pResult = 0; + return; + } + + for(i=0;i> 8; + sum += in; + sumsq += (q63_t)in * in; + } + sumsq /= (q63_t)(blockSize - 1); + sum = sum * sum / (q63_t)(blockSize * (blockSize - 1)); + *pResult = (q31_t)(sqrtf((float)( (sumsq - sum) >> 15) / 2147483648.0f ) * 2147483648.0f); +} + +void ref_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t i; + q31_t sum=0; + q63_t sumsq=0; + + if (blockSize == 1) + { + *pResult = 0; + return; + } + + for(i=0;i> 15) / 32768.0f ) * 32768.0f); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c new file mode 100644 index 0000000..0dfb015 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c @@ -0,0 +1,70 @@ +#include "ref.h" + +void ref_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t i; + float32_t sum=0, sumsq=0; + + if (blockSize == 1) + { + *pResult = 0; + return; + } + + for(i=0;i> 8; + sum += in; + sumsq += (q63_t)in * in; + } + *pResult = (sumsq - sum * sum / (q31_t)blockSize) / ((q31_t)blockSize - 1) >> 15; +} + +void ref_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t i; + q31_t sum=0; + q63_t sumsq=0; + + if (blockSize == 1) + { + *pResult = 0; + return; + } + + for(i=0;i> 15; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/SupportFunctions.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/SupportFunctions.c new file mode 100644 index 0000000..647eb46 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/SupportFunctions.c @@ -0,0 +1,6 @@ + +#include "copy.c" +#include "fill.c" +#include "fixed_to_fixed.c" +#include "fixed_to_float.c" +#include "float_to_fixed.c" diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c new file mode 100644 index 0000000..b8ffd28 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c @@ -0,0 +1,53 @@ +#include "ref.h" + +void ref_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 16; + } +} + +void ref_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 24; + } +} + +void ref_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 8; + } +} + +void ref_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i 0.0f ? 0.5f : -0.5f; //round + pDst[i] = ref_sat_q31((q63_t)in); //cast and saturate + } +} + +void ref_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + float32_t in; + + for(i=0;i 0.0f ? 0.5f : -0.5f; + pDst[i] = ref_sat_q15((q31_t)in); + } +} + +void ref_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + float32_t in; + + for(i=0;i 0.0f ? 0.5f : -0.5f; + pDst[i] = ref_sat_q7((q15_t)in); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/TransformFunctions.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/TransformFunctions.c new file mode 100644 index 0000000..d0d10c4 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/TransformFunctions.c @@ -0,0 +1,4 @@ + +#include "cfft.c" +#include "dct4.c" +#include "rfft.c" diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c new file mode 100644 index 0000000..1b564fc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c @@ -0,0 +1,30 @@ +#include "ref.h" + + +;/* +;* @brief In-place bit reversal function. +;* @param[in, out] *pSrc points to the in-place buffer of unknown 32-bit data type. +;* @param[in] bitRevLen bit reversal table length +;* @param[in] *pBitRevTab points to bit reversal table. +;* @return none. +;*/ +void ref_arm_bitreversal_32(uint32_t *pSrc, uint32_t bitRevLen, uint32_t *pBitRevTab) +{ + uint32_t a,b,i,tmp; + + for(i=0; ifftLen; + int32_t dir = (ifftFlag) ? -1 : 1; + + // decrement pointer since the original version used fortran style indexing. + data--; + + n = N << 1; + j = 1; + for (i = 1; i < n; i += 2) { + if (j > i) { + tempr = data[j]; data[j] = data[i]; data[i] = tempr; + tempr = data[j+1]; data[j+1] = data[i+1]; data[i+1] = tempr; + } + m = n >> 1; + while (m >= 2 && j > m) { + j -= m; + m >>= 1; + } + j += m; + } + mmax = 2; + while (n > mmax) { + istep = 2*mmax; + theta = -6.283185307179586f/(dir*mmax); + wtemp = sinf(0.5f*theta); + wpr = -2.0f*wtemp*wtemp; + wpi = sinf(theta); + wr = 1.0f; + wi = 0.0f; + for (m = 1; m < mmax; m += 2) { + for (i = m; i <= n; i += istep) { + j =i + mmax; + tempr = wr*data[j] - wi*data[j+1]; + tempi = wr*data[j+1] + wi*data[j]; + data[j] = data[i] - tempr; + data[j+1] = data[i+1] - tempi; + data[i] += tempr; + data[i+1] += tempi; + } + wr = (wtemp = wr)*wpr - wi*wpi + wr; + wi = wi*wpr + wtemp*wpi + wi; + } + mmax = istep; + } + + // Inverse transform is scaled by 1/N + if (ifftFlag) + { + data++; + for(i = 0; i<2*N; i++) + { + data[i] /= N; + } + } +} + +void ref_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)p1; + + for(i=0;ifftLen*2;i++) + { + //read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)p1[i] / 2147483648.0f; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, ifftFlag, bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, ifftFlag, bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, ifftFlag, bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, ifftFlag, bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, ifftFlag, bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, ifftFlag, bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, ifftFlag, bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, ifftFlag, bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, ifftFlag, bitReverseFlag); + break; + } + + if (ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)( fSrc[i] * 2147483648.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)( fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)pSrc; + + for(i=0;ifftLen*2;i++) + { + //read the q15 data, cast to float, scale down for float, place in temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for(i=0;ifftLen*2;i++) + { + //copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, ifftFlag, bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, ifftFlag, bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, ifftFlag, bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, ifftFlag, bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, ifftFlag, bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, ifftFlag, bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, ifftFlag, bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, ifftFlag, bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, ifftFlag, bitReverseFlag); + break; + } + + if (ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc) +{ + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)pSrc; + + for(i=0;ifftLen*2;i++) + { + //read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + } + + if (S->ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)pSrc; + + for(i=0;ifftLen*2;i++) + { + //read the q15 data, cast to float, scale down for float, place in temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for(i=0;ifftLen*2;i++) + { + //copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + } + + if (S->ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc) +{ + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)pSrc; + + for(i=0;ifftLen*2;i++) + { + //read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + } + + if (S->ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)pSrc; + + for(i=0;ifftLen*2;i++) + { + //read the q15 data, cast to float, scale down for float, place in temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for(i=0;ifftLen*2;i++) + { + //copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + } + + if (S->ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c new file mode 100644 index 0000000..60bbb1a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c @@ -0,0 +1,89 @@ +#include "ref.h" + +void ref_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer) +{ + uint32_t n,k; + float32_t sum; + float32_t pi_by_N = 3.14159265358979f / (float32_t)S->N; + float32_t tmp; + float32_t normalize = sqrtf(2.0f / (float32_t)S->N); + + for(k=0;kN;k++) + { + sum=0.0f; + tmp = ((float32_t)k + 0.5f)*pi_by_N; + for(n=0;nN;n++) + { + sum += pInlineBuffer[n] * cosf(tmp * ((float32_t)n + 0.5f)); + } + scratchArray[k] = normalize * sum; + } + + for(k=0;kN;k++) + { + pInlineBuffer[k] = scratchArray[k]; + } +} + +void ref_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer) +{ + arm_dct4_instance_f32 SS; + float32_t *fSrc = (float32_t*)pInlineBuffer; + uint32_t i; + + SS.N = S->N; + + for(i=0;iN;i++) + { + //read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pInlineBuffer[i] / 2147483648.0f; + } + + ref_dct4_f32(&SS,(float32_t*)0,fSrc); + + for(i=0;iN;i++) + { + fSrc[i] = fSrc[i] * 2147483648.0f / (float32_t)S->N ; + fSrc[i] += (fSrc[i] > 0) ? 0.5f : -0.5f; + pInlineBuffer[i] = (q31_t)fSrc[i]; + } +} + +void ref_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer) +{ + arm_dct4_instance_f32 SS; + float32_t *fSrc = (float32_t*)pInlineBuffer; + uint32_t i; + + SS.N = S->N; + + for(i=0;iN;i++) + { + //read the q15 data, cast to float, scale down for float, place in temporary buffer + scratchArray[i] = (float32_t)pInlineBuffer[i] / 32768.0f; + } + + for(i=0;iN;i++) + { + //copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + ref_dct4_f32(&SS,(float32_t*)0,fSrc); + + for(i=0;iN;i++) + { + fSrc[i] = fSrc[i] * 32768.0f / (float32_t)S->N; + fSrc[i] += (fSrc[i] > 0) ? 0.5f : -0.5f; + pInlineBuffer[i] = (q15_t)fSrc[i]; + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c new file mode 100644 index 0000000..9be22d0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c @@ -0,0 +1,302 @@ +#include "ref.h" +#include "arm_const_structs.h" + +void ref_rfft_f32( + arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst) +{ + uint32_t i; + + if (S->ifftFlagR) + { + for(i=0;ifftLenReal*2;i++) + { + pDst[i] = pSrc[i]; + } + } + else + { + for(i=0;ifftLenReal;i++) + { + pDst[2*i+0] = pSrc[i]; + pDst[2*i+1] = 0.0f; + } + } + + switch(S->fftLenReal) + { + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, pDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, pDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, pDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, pDst, S->ifftFlagR, S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) + { + //throw away the imaginary part which should be all zeros + for(i=0;ifftLenReal;i++) + { + pDst[i] = pDst[2*i]; + } + } +} + +void ref_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag) +{ + uint32_t i,j; + + if (ifftFlag) + { + for(i=0;ifftLenRFFT;i++) + { + pOut[i] = p[i]; + } + //unpack first sample's complex part into middle sample's real part + pOut[S->fftLenRFFT] = pOut[1]; + pOut[S->fftLenRFFT+1] = 0; + pOut[1] = 0; + j=4; + for(i = S->fftLenRFFT / 2 + 1;i < S->fftLenRFFT;i++) + { + pOut[2*i+0] = p[2*i+0 - j]; + pOut[2*i+1] = -p[2*i+1 - j]; + j+=4; + } + } + else + { + for(i=0;ifftLenRFFT;i++) + { + pOut[2*i+0] = p[i]; + pOut[2*i+1] = 0.0f; + } + } + + switch(S->fftLenRFFT) + { + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, pOut, ifftFlag, 1); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, pOut, ifftFlag, 1); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, pOut, ifftFlag, 1); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, pOut, ifftFlag, 1); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, pOut, ifftFlag, 1); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, pOut, ifftFlag, 1); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, pOut, ifftFlag, 1); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, pOut, ifftFlag, 1); + break; + } + + if (ifftFlag) + { + //throw away the imaginary part which should be all zeros + for(i=0;ifftLenRFFT;i++) + { + pOut[i] = pOut[2*i]; + } + } + else + { + //pack last sample's real part into first sample's complex part + pOut[1] = pOut[S->fftLenRFFT]; + } +} + +void ref_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst) +{ + uint32_t i; + float32_t *fDst = (float32_t*)pDst; + + if (S->ifftFlagR) + { + for(i=0;ifftLenReal*2;i++) + { + fDst[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + } + else + { + for(i=0;ifftLenReal;i++) + { + fDst[2*i+0] = (float32_t)pSrc[i] / 2147483648.0f; + fDst[2*i+1] = 0.0f; + } + } + + switch(S->fftLenReal) + { + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) + { + //throw away the imaginary part which should be all zeros + for(i=0;ifftLenReal;i++) + { + //read the float data, scale up for q31, cast to q31 + pDst[i] = (q31_t)( fDst[2*i] * 2147483648.0f); + } + } + else + { + for(i=0;ifftLenReal;i++) + { + //read the float data, scale up for q31, cast to q31 + pDst[i] = (q31_t)( fDst[i] * 2147483648.0f / (float32_t)S->fftLenReal); + } + } +} + +void ref_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst) +{ + uint32_t i; + float32_t *fDst = (float32_t*)pDst; + + + if (S->ifftFlagR) + { + for(i=0;ifftLenReal*2;i++) + { + fDst[i] = (float32_t)pSrc[i] / 32768.0f; + } + } + else + { + for(i=0;ifftLenReal;i++) + { + //read the q15 data, cast to float, scale down for float + fDst[2*i+0] = (float32_t)pSrc[i] / 32768.0f; + fDst[2*i+1] = 0.0f; + } + } + + switch(S->fftLenReal) + { + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) + { + //throw away the imaginary part which should be all zeros + for(i=0;ifftLenReal;i++) + { + pDst[i] = (q15_t)( fDst[2*i] * 32768.0f); + } + } + else + { + for(i=0;ifftLenReal;i++) + { + pDst[i] = (q15_t)( fDst[i] * 32768.0f / (float32_t)S->fftLenReal); + } + } +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt new file mode 100644 index 0000000..46a2ec9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_class_marks_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c new file mode 100644 index 0000000..1d62419 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c @@ -0,0 +1,211 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_class_marks_example_f32.c +* +* Description: Example code to calculate Minimum, Maximum +* Mean, std and variance of marks obtained in a class +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ClassMarks Class Marks Example + * + * \par Description: + * \par + * Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance + * and Matrix functions to calculate statistical values of marks obtained in a class. + * + * \note This example also demonstrates the usage of static initialization. + * + * \par Variables Description: + * \par + * \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects + * \li \c max_marks Maximum of all marks + * \li \c min_marks Minimum of all marks + * \li \c mean Mean of all marks + * \li \c var Variance of the marks + * \li \c std Standard deviation of the marks + * \li \c numStudents Total number of students in the class + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_mult_f32() + * - arm_max_f32() + * - arm_min_f32() + * - arm_mean_f32() + * - arm_std_f32() + * - arm_var_f32() + * + * Refer + * \link arm_class_marks_example_f32.c \endlink + * + */ + + +/** \example arm_class_marks_example_f32.c + */ +#include "arm_math.h" + +#define USE_STATIC_INIT + + /* ---------------------------------------------------------------------- +** Global defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES (20*4) + +/* ---------------------------------------------------------------------- +** List of Marks scored by 20 students for 4 subjects +** ------------------------------------------------------------------- */ +const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] = +{ + 42.000000, 37.000000, 81.000000, 28.000000, + 83.000000, 72.000000, 36.000000, 38.000000, + 32.000000, 51.000000, 63.000000, 64.000000, + 97.000000, 82.000000, 95.000000, 90.000000, + 66.000000, 51.000000, 54.000000, 42.000000, + 67.000000, 56.000000, 45.000000, 57.000000, + 67.000000, 69.000000, 35.000000, 52.000000, + 29.000000, 81.000000, 58.000000, 47.000000, + 38.000000, 76.000000, 100.000000, 29.000000, + 33.000000, 47.000000, 29.000000, 50.000000, + 34.000000, 41.000000, 61.000000, 46.000000, + 52.000000, 50.000000, 48.000000, 36.000000, + 47.000000, 55.000000, 44.000000, 40.000000, + 100.000000, 94.000000, 84.000000, 37.000000, + 32.000000, 71.000000, 47.000000, 77.000000, + 31.000000, 50.000000, 49.000000, 35.000000, + 63.000000, 67.000000, 40.000000, 31.000000, + 29.000000, 68.000000, 61.000000, 38.000000, + 31.000000, 28.000000, 28.000000, 76.000000, + 55.000000, 33.000000, 29.000000, 39.000000 +}; + + +/* ---------------------------------------------------------------------- +* Number of subjects X 1 +* ------------------------------------------------------------------- */ +const float32_t testUnity_f32[4] = +{ + 1.000, 1.000, 1.000, 1.000 +}; + + +/* ---------------------------------------------------------------------- +** f32 Output buffer +** ------------------------------------------------------------------- */ +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + + +/* ------------------------------------------------------------------ +* Global defines +*------------------------------------------------------------------- */ +#define NUMSTUDENTS 20 +#define NUMSUBJECTS 4 + +/* ------------------------------------------------------------------ +* Global variables +*------------------------------------------------------------------- */ + + uint32_t numStudents = 20; + uint32_t numSubjects = 4; +float32_t max_marks, min_marks, mean, std, var; + uint32_t student_num; + +/* ---------------------------------------------------------------------------------- +* Main f32 test function. It returns maximum marks secured and student number +* ------------------------------------------------------------------------------- */ + +int32_t main() +{ + +#ifndef USE_STATIC_INIT + + arm_matrix_instance_f32 srcA; + arm_matrix_instance_f32 srcB; + arm_matrix_instance_f32 dstC; + + /* Input and output matrices initializations */ + arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32); + arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32); + arm_mat_init_f32(&dstC, numStudents, 1, testOutput); + +#else + + /* Static Initializations of Input and output matrix sizes and array */ + arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32}; + arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32}; + arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput}; + +#endif + + + /* ---------------------------------------------------------------------- + *Call the Matrix multiplication process function + * ------------------------------------------------------------------- */ + arm_mat_mult_f32(&srcA, &srcB, &dstC); + + /* ---------------------------------------------------------------------- + ** Call the Max function to calculate max marks among numStudents + ** ------------------------------------------------------------------- */ + arm_max_f32(testOutput, numStudents, &max_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Min function to calculate min marks among numStudents + ** ------------------------------------------------------------------- */ + arm_min_f32(testOutput, numStudents, &min_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Mean function to calculate mean + ** ------------------------------------------------------------------- */ + arm_mean_f32(testOutput, numStudents, &mean); + + /* ---------------------------------------------------------------------- + ** Call the std function to calculate standard deviation + ** ------------------------------------------------------------------- */ + arm_std_f32(testOutput, numStudents, &std); + + /* ---------------------------------------------------------------------- + ** Call the var function to calculate variance + ** ------------------------------------------------------------------- */ + arm_var_f32(testOutput, numStudents, &var); + + while (1); /* main function does not return */ +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt new file mode 100644 index 0000000..2abb089 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_convolution_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c new file mode 100644 index 0000000..8af04b8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c @@ -0,0 +1,247 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_convolution_example_f32.c +* +* Description: Example code demonstrating Convolution of two input signals using fft. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ConvolutionExample Convolution Example + * + * \par Description: + * \par + * Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex + * Multiplication, and Support Functions. + * + * \par Algorithm: + * \par + * The convolution theorem states that convolution in the time domain corresponds to + * multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of + * two signals is equal to the product of their individual Fourier transforms. + * The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). + * \par + * Two input signals, a[n] and b[n], with lengths \c n1 and \c n2 respectively, + * are zero padded so that their lengths become \c N, which is greater than or equal to (n1+n2-1) + * and is a power of 4 as FFT implementation is radix-4. + * The convolution of a[n] and b[n] is obtained by taking the FFT of the input + * signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of + * the multiplied result. + * \par + * This is denoted by the following equations: + * 
 A[k] = FFT(a[n],N)
+ * B[k] = FFT(b[n],N)
+ * conv(a[n], b[n]) = IFFT(A[k] * B[k], N)
+ * where A[k] and B[k] are the N-point FFTs of the signals a[n] + * and b[n] respectively. + * The length of the convolved signal is (n1+n2-1). + * + * \par Block Diagram: + * \par + * \image html Convolution.gif + * + * \par Variables Description: + * \par + * \li \c testInputA_f32 points to the first input sequence + * \li \c srcALen length of the first input sequence + * \li \c testInputB_f32 points to the second input sequence + * \li \c srcBLen length of the second input sequence + * \li \c outLen length of convolution output sequence, (srcALen + srcBLen - 1) + * \li \c AxB points to the output array where the product of individual FFTs of inputs is stored. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fill_f32() + * - arm_copy_f32() + * - arm_cfft_radix4_init_f32() + * - arm_cfft_radix4_f32() + * - arm_cmplx_mult_cmplx_f32() + * + * Refer + * \link arm_convolution_example_f32.c \endlink + * + */ + + +/** \example arm_convolution_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 128 +#define DELTA (0.000001f) +#define SNR_THRESHOLD 90 + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t Ak[MAX_BLOCKSIZE]; /* Input A */ +float32_t Bk[MAX_BLOCKSIZE]; /* Input B */ +float32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */ + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Convolution example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +float32_t testInputA_f32[64] = +{ + -0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285, + 1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579, + -0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377, + -2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827, + -0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938, + -0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619, + 0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222, + -0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249, + -1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355, + -1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090, + -0.161050, -0.940794, 0.367961, 0.291907 + +}; + +float32_t testInputB_f32[64] = +{ + 0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885, + 0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493, + -0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692, + -0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962, + 0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397, + 1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399, + -1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011, + 0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456, + 0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182, + -1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952, + 0.635474, -0.970468, 1.334057, -0.111370 +}; + +const float testRefOutput_f32[127] = +{ + -0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656, + 5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012, + -1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236, + -7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508, + -1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267, + 11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552, + 1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344, + -0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488, + -13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415, + -0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462, + 8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280, + 7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073, + -2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291, + 1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885, + 8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417, + 8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678, + -6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410, + -2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013, + -3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358, + -4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638, + 1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440, 0 +}; + + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t srcALen = 64; /* Length of Input A */ +uint32_t srcBLen = 64; /* Length of Input B */ +uint32_t outLen; /* Length of convolution output */ +float32_t snr; /* output SNR */ + +int32_t main(void) +{ + arm_status status; /* Status of the example */ + arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */ + + /* CFFT Structure instance pointer */ + arm_cfft_radix4_instance_f32 *cfft_instance_ptr = + (arm_cfft_radix4_instance_f32*) &cfft_instance; + + /* output length of convolution */ + outLen = srcALen + srcBLen - 1; + + /* Initialise the fft input buffers with all zeros */ + arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE); + arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE); + + /* Copy the input values to the fft input buffers */ + arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2); + arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2); + + /* Initialize the CFFT function to compute 64 point fft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1); + + /* Transform input a[n] from time domain to frequency domain A[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Ak); + /* Transform input b[n] from time domain to frequency domain B[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Bk); + + /* Complex Multiplication of the two input buffers in frequency domain */ + arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2); + + /* Initialize the CIFFT function to compute 64 point ifft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1); + + /* Transform the multiplication output from frequency domain to time domain, + that gives the convolved output */ + arm_cfft_radix4_f32(cfft_instance_ptr, AxB); + + /* SNR Calculation */ + snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1); + + /* Compare the SNR with threshold to test whether the + computed output is matched with the reference output values. */ + if ( snr > SNR_THRESHOLD) + { + status = ARM_MATH_SUCCESS; + } + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c new file mode 100644 index 0000000..4b0ee1f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h new file mode 100644 index 0000000..46b0af3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt new file mode 100644 index 0000000..c8dbd44 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_dotproduct_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c new file mode 100644 index 0000000..21966a0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_dotproduct_example_f32.c +* +* Description: Example code computing dot product of two vectors. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup DotproductExample Dot Product Example + * + * \par Description: + * \par + * Demonstrates the use of the Multiply and Add functions to perform the dot product. + * The dot product of two vectors is obtained by multiplying corresponding elements + * and summing the products. + + * \par Algorithm: + * \par + * The two input vectors \c A and \c B with length \c n, are multiplied element-by-element + * and then added to obtain dot product. + * \par + * This is denoted by the following equation: + * 
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]
+ * + * \par Block Diagram: + * \par + * \image html dotProduct.gif + * + * \par Variables Description: + * \par + * \li \c srcA_buf_f32 points to first input vector + * \li \c srcB_buf_f32 points to second input vector + * \li \c testOutput stores dot product of the two input vectors. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_dotproduct_example_f32.c \endlink + * + */ + + +/** \example arm_dotproduct_example_f32.c + */ + +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Dot Product example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +/* ---------------------------------------------------------------------- +** Test input data of srcA for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcA_buf_f32[MAX_BLOCKSIZE] = +{ + -0.4325648115282207, -1.6655843782380970, 0.1253323064748307, + 0.2876764203585489, -1.1464713506814637, 1.1909154656429988, + 1.1891642016521031, -0.0376332765933176, 0.3272923614086541, + 0.1746391428209245, -0.1867085776814394, 0.7257905482933027, + -0.5883165430141887, 2.1831858181971011, -0.1363958830865957, + 0.1139313135208096, 1.0667682113591888, 0.0592814605236053, + -0.0956484054836690, -0.8323494636500225, 0.2944108163926404, + -1.3361818579378040, 0.7143245518189522, 1.6235620644462707, + -0.6917757017022868, 0.8579966728282626, 1.2540014216025324, + -1.5937295764474768, -1.4409644319010200, 0.5711476236581780, + -0.3998855777153632, 0.6899973754643451 +}; + +/* ---------------------------------------------------------------------- +** Test input data of srcB for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcB_buf_f32[MAX_BLOCKSIZE] = +{ + 1.7491401329284098, 0.1325982188803279, 0.3252281811989881, + -0.7938091410349637, 0.3149236145048914, -0.5272704888029532, + 0.9322666565031119, 1.1646643544607362, -2.0456694357357357, + -0.6443728590041911, 1.7410657940825480, 0.4867684246821860, + 1.0488288293660140, 1.4885752747099299, 1.2705014969484090, + -1.8561241921210170, 2.1343209047321410, 1.4358467535865909, + -0.9173023332875400, -1.1060770780029008, 0.8105708062681296, + 0.6985430696369063, -0.4015827425012831, 1.2687512030669628, + -0.7836083053674872, 0.2132664971465569, 0.7878984786088954, + 0.8966819356782295, -0.1869172943544062, 1.0131816724341454, + 0.2484350696132857, 0.0596083377937976 +}; + +/* Reference dot product output */ +float32_t refDotProdOut = 5.9273644806352142; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +float32_t multOutput[MAX_BLOCKSIZE]; /* Intermediate output */ +float32_t testOutput; /* Final ouput */ + +arm_status status; /* Status of the example */ + +int32_t main(void) +{ + uint32_t i; /* Loop counter */ + float32_t diff; /* Difference between reference and test outputs */ + + /* Multiplication of two input buffers */ + arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE); + + /* Accumulate the multiplication output values to + get the dot product of the two inputs */ + for(i=0; i< MAX_BLOCKSIZE; i++) + { + arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1); + } + + /* absolute value of difference between ref and test */ + diff = fabsf(refDotProdOut - testOutput); + + /* Comparison of dot product value with reference */ + if (diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if ( status == ARM_MATH_TEST_FAILURE) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt new file mode 100644 index 0000000..8395b53 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_fft_bin_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c new file mode 100644 index 0000000..b5159e5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c @@ -0,0 +1,308 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fft_bin_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +Test Input signal contains 10KHz signal + Uniformly distributed white noise +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_10khz[2048] = +{ +-0.865129623056441, 0.000000000000000, -2.655020678073846, 0.000000000000000, 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2.337405215062395, 0.000000000000000, -3.980689173859100, 0.000000000000000, + + +}; + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c new file mode 100644 index 0000000..9e36b2b --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fft_bin_example_f32.c +* +* Description: Example code demonstrating calculation of Max energy bin of +* frequency domain of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FrequencyBin Frequency Bin Example + * + * \par Description + * \par + * Demonstrates the calculation of the maximum energy bin in the frequency + * domain of the input signal with the use of Complex FFT, Complex + * Magnitude, and Maximum functions. + * + * \par Algorithm: + * \par + * The input test signal contains a 10 kHz signal with uniformly distributed white noise. + * Calculating the FFT of the input signal will give us the maximum energy of the + * bin corresponding to the input frequency of 10 kHz. + * + * \par Block Diagram: + * \image html FFTBin.gif "Block Diagram" + * \par + * The figure below shows the time domain signal of 10 kHz signal with + * uniformly distributed white noise, and the next figure shows the input + * in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. + * \par + * \image html FFTBinInput.gif "Input signal in Time domain" + * \image html FFTBinOutput.gif "Input signal in Frequency domain" + * + * \par Variables Description: + * \par + * \li \c testInput_f32_10khz points to the input data + * \li \c testOutput points to the output data + * \li \c fftSize length of FFT + * \li \c ifftFlag flag for the selection of CFFT/CIFFT + * \li \c doBitReverse Flag for selection of normal order or bit reversed order + * \li \c refIndex reference index value at which maximum energy of bin ocuurs + * \li \c testIndex calculated index value at which maximum energy of bin ocuurs + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cfft_f32() + * - arm_cmplx_mag_f32() + * - arm_max_f32() + * + * Refer + * \link arm_fft_bin_example_f32.c \endlink + * + */ + + +/** \example arm_fft_bin_example_f32.c + */ + + +#include "arm_math.h" +#include "arm_const_structs.h" + +#define TEST_LENGTH_SAMPLES 2048 + +/* ------------------------------------------------------------------- +* External Input and Output buffer Declarations for FFT Bin Example +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; +static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; + +/* ------------------------------------------------------------------ +* Global variables for FFT Bin Example +* ------------------------------------------------------------------- */ +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; + +/* Reference index at which max energy of bin ocuurs */ +uint32_t refIndex = 213, testIndex = 0; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_status status; + float32_t maxValue; + + status = ARM_MATH_SUCCESS; + + /* Process the data through the CFFT/CIFFT module */ + arm_cfft_f32(&arm_cfft_sR_f32_len1024, testInput_f32_10khz, ifftFlag, doBitReverse); + + /* Process the data through the Complex Magnitude Module for + calculating the magnitude at each bin */ + arm_cmplx_mag_f32(testInput_f32_10khz, testOutput, fftSize); + + /* Calculates maxValue and returns corresponding BIN value */ + arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); + + if (testIndex != refIndex) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt new file mode 100644 index 0000000..c06d3f3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_fir_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c new file mode 100644 index 0000000..283a25e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fir_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input signal contains 1000Hz + 15000 Hz +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_1kHz_15kHz[320] = +{ ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +}; + +float32_t refOutput[320] = +{ ++0.0000000000f, -0.0010797829f, -0.0007681386f, -0.0001982932f, +0.0000644313f, +0.0020854271f, +0.0036891871f, +0.0015855941f, +-0.0026280805f, -0.0075907658f, -0.0119390538f, -0.0086665968f, +0.0088981202f, +0.0430539279f, +0.0974468742f, +0.1740405600f, ++0.2681416601f, +0.3747720089f, +0.4893362230f, +0.6024154672f, +0.7058740791f, +0.7968348987f, +0.8715901940f, +0.9277881093f, ++0.9682182661f, +0.9934674267f, +1.0012052245f, +0.9925859371f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, -0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f +}; + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c new file mode 100644 index 0000000..333d230 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library + * Title: arm_fir_example_f32.c + * + * Description: Example code demonstrating how an FIR filter can be used + * as a low pass filter. + * + * Target Processor: Cortex-M4/Cortex-M3 + * +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FIRLPF FIR Lowpass Filter Example + * + * \par Description: + * \par + * Removes high frequency signal components from the input using an FIR lowpass filter. + * The example demonstrates how to configure an FIR filter and then pass data through + * it in a block-by-block fashion. + * \image html FIRLPF_signalflow.gif + * + * \par Algorithm: + * \par + * The input signal is a sum of two sine waves: 1 kHz and 15 kHz. + * This is processed by an FIR lowpass filter with cutoff frequency 6 kHz. + * The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output. + * \par + * The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and + * a length of 29 points. + * The MATLAB code to generate the filter coefficients is shown below: + * 
+ *     h = fir1(28, 6/24);
+ *
+ * The first argument is the "order" of the filter and is always one less than the desired length. + * The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist). + * A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25. + * The CMSIS FIR filter function requires the coefficients to be in time reversed order. + * 
+ *     fliplr(h)
+ *
+ * The resulting filter coefficients and are shown below. + * Note that the filter is symmetric (a property of linear phase FIR filters) + * and the point of symmetry is sample 14. Thus the filter will have a delay of + * 14 samples for all frequencies. + * \par + * \image html FIRLPF_coeffs.gif + * \par + * The frequency response of the filter is shown next. + * The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz. + * \par + * \image html FIRLPF_response.gif + * \par + * The input signal is shown below. + * The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation. + * The two sine wave components can be clearly seen. + * \par + * \image html FIRLPF_input.gif + * \par + * The output of the filter is shown below. The 15 kHz component has been eliminated. + * \par + * \image html FIRLPF_output.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32_1kHz_15kHz points to the input data + * \li \c refOutput points to the reference output data + * \li \c testOutput points to the test output data + * \li \c firStateF32 points to state buffer + * \li \c firCoeffs32 points to coefficient buffer + * \li \c blockSize number of samples processed at a time + * \li \c numBlocks number of frames + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fir_init_f32() + * - arm_fir_f32() + * + * Refer + * \link arm_fir_example_f32.c \endlink + * + */ + + +/** \example arm_fir_example_f32.c + */ + +/* ---------------------------------------------------------------------- +** Include Files +** ------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +** Macro Defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 320 +#define SNR_THRESHOLD_F32 140.0f +#define BLOCK_SIZE 32 +#define NUM_TAPS 29 + +/* ------------------------------------------------------------------- + * The input signal and reference output (computed with MATLAB) + * are defined externally in arm_fir_lpf_data.c. + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]; +extern float32_t refOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare Test output buffer + * ------------------------------------------------------------------- */ + +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare State buffer of size (numTaps + blockSize - 1) + * ------------------------------------------------------------------- */ + +static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1]; + +/* ---------------------------------------------------------------------- +** FIR Coefficients buffer generated using fir1() MATLAB function. +** fir1(28, 6/24) +** ------------------------------------------------------------------- */ + +const float32_t firCoeffs32[NUM_TAPS] = { + -0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, + -0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, + +0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, + +0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f +}; + +/* ------------------------------------------------------------------ + * Global variables for FIR LPF Example + * ------------------------------------------------------------------- */ + +uint32_t blockSize = BLOCK_SIZE; +uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE; + +float32_t snr; + +/* ---------------------------------------------------------------------- + * FIR LPF Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_fir_instance_f32 S; + arm_status status; + float32_t *inputF32, *outputF32; + + /* Initialize input and output buffer pointers */ + inputF32 = &testInput_f32_1kHz_15kHz[0]; + outputF32 = &testOutput[0]; + + /* Call FIR init function to initialize the instance structure. */ + arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize); + + /* ---------------------------------------------------------------------- + ** Call the FIR process function for every blockSize samples + ** ------------------------------------------------------------------- */ + + for(i=0; i < numBlocks; i++) + { + arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize); + } + + /* ---------------------------------------------------------------------- + ** Compare the generated output against the reference output computed + ** in MATLAB. + ** ------------------------------------------------------------------- */ + + snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) + { + status = ARM_MATH_TEST_FAILURE; + } + else + { + status = ARM_MATH_SUCCESS; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signal does not match the reference output. + ** ------------------------------------------------------------------- */ + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + +/** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c new file mode 100644 index 0000000..4b0ee1f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h new file mode 100644 index 0000000..46b0af3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt new file mode 100644 index 0000000..91f8991 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_graphic_equalizer_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c new file mode 100644 index 0000000..ffb0ff3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_graphic_equalizer_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +float32_t testRefOutput_f32[320] = { + +0.000000000000000000, 0.001898396760225296, 0.004215449094772339, 0.007432077080011368, 0.010948467999696732, 0.015026375651359558, 0.019191544502973557, 0.023574527353048325, +0.027919445186853409, 0.032277785241603851, 0.036551639437675476, 0.040732793509960175, 0.044799156486988068, 0.048710610717535019, 0.052476800978183746, 0.056059073656797409, +0.059482168406248093, 0.062726479023694992, 0.065821025520563126, 0.068763464689254761, 0.071577839553356171, 0.074270240962505341, 0.076856281608343124, 0.079344697296619415, +0.081745062023401260, 0.084067162126302719, 0.086318407207727432, 0.088509257882833481, 0.090647127479314804, 0.092742368578910828, 0.094802625477313995, 0.096837285906076431, +0.098853722214698792, 0.100859899073839190, 0.102862443774938580, 0.104867763817310330, 0.106881409883499150, 0.108908228576183320, 0.110952425748109820, 0.113017357885837550, +0.115105822682380680, 0.117219865322113040, 0.119361080229282380, 0.121530555188655850, 0.123729091137647630, 0.125957202166318890, 0.128215309232473370, 0.130503740161657330, +0.132822841405868530, 0.135173004120588300, 0.137554679065942760, 0.139968376606702800, 0.142414685338735580, 0.144894234836101530, 0.147407654672861100, 0.149955596774816510, +0.152538605034351350, 0.155157200992107390, 0.157811731100082400, 0.160502441227436070, 0.163229387253522870, 0.165992442518472670, 0.168791320174932480, 0.171625509858131410, +0.174494370818138120, 0.177397061139345170, 0.180332608520984650, 0.183299910277128220, 0.186297744512557980, 0.189324837177991870, 0.192379791289567950, 0.195461250841617580, +0.198567759245634080, 0.201697919517755510, 0.204850304871797560, 0.208023533225059510, 0.211216274648904800, 0.214427210390567780, 0.217655111104249950, 0.220898788422346120, +0.224157124757766720, 0.227429077029228210, 0.230713658034801480, 0.234009962528944020, 0.237317133694887160, 0.240634419023990630, 0.243961080908775330, 0.247296508401632310, +0.250640105456113820, 0.253991369158029560, 0.257349837571382520, 0.260715119540691380, 0.264086868613958360, 0.267464816570281980, 0.270848698914051060, 0.274238351732492450, +0.277633611112833020, 0.281034380197525020, 0.284440591931343080, 0.287852220237255100, 0.291269283741712570, 0.294691801071166990, 0.298119872808456420, 0.301553562283515930, +0.304993014782667160, 0.308438356965780260, 0.311889752745628360, 0.315347377210855480, 0.318811416625976560, 0.322282072156667710, 0.325759567320346830, 0.329244095832109450, +0.332735907286405560, 0.336235217750072480, 0.339742250740528110, 0.343257248401641850, 0.346780419349670410, 0.350311983376741410, 0.353852160274982450, 0.357401121407747270, +0.360959105193614960, 0.364526227116584780, 0.368102725595235820, 0.371688675135374070, 0.375284302979707720, 0.378889638930559160, 0.382504884153604510, 0.386130042374134060, +0.389765247702598570, 0.393410529941320420, 0.397065933793783190, 0.400731507688760760, 0.404407206922769550, 0.408093083649873730, 0.411789052188396450, 0.415495119988918300, +0.419211201369762420, 0.422937240451574330, 0.426673140376806260, 0.430418811738491060, 0.434174135327339170, 0.437938995659351350, 0.441713258624076840, 0.445496778935194020, +0.449289388954639430, 0.453090950846672060, 0.456901267170906070, 0.460720170289278030, 0.464547459036111830, 0.468382950872182850, 0.472226426005363460, 0.476077698171138760, +0.479936532676219940, 0.483802750706672670, 0.487676106393337250, 0.491556398570537570, 0.495443399995565410, 0.499336875975131990, 0.503236617892980580, 0.507142387330532070, +0.511053957045078280, 0.514971107244491580, 0.518893606960773470, 0.522821225225925450, 0.526753749698400500, 0.530690938234329220, 0.534632585942745210, 0.538578454405069350, +0.542528338730335240, 0.546481993049383160, 0.550439231097698210, 0.554399792104959490, 0.558363504707813260, 0.562330115586519240, 0.566299438476562500, 0.570271246135234830, +0.574245333671569820, 0.578221492469310760, 0.582199502736330030, 0.586179181933403020, 0.590160276740789410, 0.594142623245716090, 0.598125983029603960, 0.602110169827938080, +0.606094967573881150, 0.610080175101757050, 0.614065583795309070, 0.618050977587699890, 0.622036151587963100, 0.626020893454551700, 0.630004994571208950, 0.633988231420516970, +0.637970402836799620, 0.641951277852058410, 0.645930647850036620, 0.649908289313316350, 0.653883971273899080, 0.657857488840818410, 0.661828581243753430, 0.665797054767608640, +0.669762641191482540, 0.673725124448537830, 0.677684243768453600, 0.681639779359102250, 0.685591462999582290, 0.689539063721895220, 0.693482317030429840, 0.697420965880155560, +0.701354760676622390, 0.705283410847187040, 0.709206689149141310, 0.713124278932809830, 0.717035952955484390, 0.720941375941038130, 0.724840316921472550, 0.728732451796531680, +0.732617516070604320, 0.736495196819305420, 0.740365199744701390, 0.744227230548858640, 0.748080968856811520, 0.751926124095916750, 0.755762357264757160, 0.759589381515979770, +0.763406842947006230, 0.767214450985193250, 0.771011855453252790, 0.774798732250928880, 0.778574761003255840, 0.782339565455913540, 0.786092851310968400, 0.789834223687648770, +0.793563373386859890, 0.797279909253120420, 0.800983514636754990, 0.804673787206411360, 0.808350402861833570, 0.812012966722249980, 0.815661124885082240, 0.819294504821300510, +0.822912722826004030, 0.826515413820743560, 0.830102190375328060, 0.833672653883695600, 0.837226435542106630, 0.840763118118047710, 0.844282336533069610, 0.847783654928207400, +0.851266715675592420, 0.854731071740388870, 0.858176350593566890, 0.861602116376161580, 0.865007970482110980, 0.868393491953611370, 0.871758259832859040, 0.875101849436759950, +0.878423850983381270, 0.881723806262016300, 0.885001312941312790, 0.888255912810564040, 0.891487173736095430, 0.894694659858942030, 0.897877920418977740, 0.901036512106657030, +0.904169965535402300, 0.907277844846248630, 0.910359673202037810, 0.913415014743804930, 0.916443370282649990, 0.919444311410188670, 0.922417331486940380, 0.925361987203359600, +0.928277771919965740, 0.931164238601922990, 0.934020876884460450, 0.936847217381000520, 0.939642757177352910, 0.942407000809907910, 0.945139460265636440, 0.947839632630348210, +0.950507018715143200, 0.953141096979379650, 0.955741371959447860, 0.958307322114706040, 0.960838429629802700, 0.963334184139966960, 0.965794049203395840, 0.968217510730028150, +0.970604017376899720, 0.972953058779239650, 0.975264083594083790, 0.977536566555500030, 0.979769956320524220, 0.981963708996772770, 0.984117280691862110, 0.986230112612247470, +0.988301653414964680, 0.990331344306468960, 0.992318630218505860, 0.994262944906950000, 0.996163722127676010, 0.998020399361848830, 0.999832402914762500, 1.001599155366420700, +1.003320086747407900, 1.004994612187147100, 1.006622135639190700, 1.008202098309993700, 1.009733878076076500, 1.011216927319765100, 1.012650609016418500, 1.014034371823072400, +1.015367589890956900, 1.016649682074785200, 1.017880033701658200, 1.019058048725128200, 1.020183108747005500, 1.021254621446132700, 1.022271949797868700, 1.023234523832798000, + +}; +/* ---------------------------------------------------------------------- +** Test input - logarithmic chirp signal +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[320] = + { + 0.000000000000000061, 0.002622410992047861, 0.005253663973466970, 0.007893770384930297, 0.010542741395035495, 0.013200587895525877, 0.015867320496454066, 0.018542949521290073, +0.021227485001971542, 0.023920936673895138, 0.026623313970853074, 0.029334626019908643, 0.032054881636210709, 0.034784089317753723, 0.037522257240071598, 0.040269393250875855, +0.043025504864628375, 0.045790599257054837, 0.048564683259595690, 0.051347763353792118, 0.054139845665610427, 0.056940935959702531, 0.059751039633601337, 0.062570161711849828, +0.065398306840066575, 0.068235479278943648, 0.071081682898178900, 0.073936921170339814, 0.076801197164660218, 0.079674513540768196, 0.082556872542344922, 0.085448275990715375, +0.088348725278367082, 0.091258221362398390, 0.094176764757897533, 0.097104355531246703, 0.100040993293358240, 0.102986677192832010, 0.105941405909045980, 0.108905177645166230, +0.111877990121087980, 0.114859840566297130, 0.117850725712659680, 0.120850641787131110, 0.123859584504392860, 0.126877549059407400, 0.129904530119898690, 0.132940521818751430, +0.135985517746334080, 0.139039510942737950, 0.142102493889940090, 0.145174458503884160, 0.148255396126476810, 0.151345297517508140, 0.154444152846483080, 0.157551951684374300, +0.160668682995289720, 0.163794335128054890, 0.166928895807713030, 0.170072352126936720, 0.173224690537355760, 0.176385896840798810, 0.179555956180445340, 0.182734853031894270, +0.185922571194139130, 0.189119093780459800, 0.192324403209221870, 0.195538481194587030, 0.198761308737133020, 0.201992866114384050, 0.205233132871247170, 0.208482087810360570, +0.211739708982344370, 0.215005973675965020, 0.218280858408200220, 0.221564338914212730, 0.224856390137231970, 0.228156986218334190, 0.231466100486134670, 0.234783705446379690, +0.238109772771442410, 0.241444273289723230, 0.244787176974952890, 0.248138452935395580, 0.251498069402956710, 0.254865993722190930, 0.258242192339209860, 0.261626630790492030, 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All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_graphic_equalizer_example_q31.c +* +* Description: Example showing an audio graphic equalizer constructed +* out of Biquad filters. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GEQ5Band Graphic Audio Equalizer Example + * + * \par Description: + * \par + * This example demonstrates how a 5-band graphic equalizer can be constructed + * using the Biquad cascade functions. + * A graphic equalizer is used in audio applications to vary the tonal quality + * of the audio. + * + * \par Block Diagram: + * \par + * The design is based on a cascade of 5 filter sections. + * \image html GEQ_signalflow.gif + * Each filter section is 4th order and consists of a cascade of two Biquads. + * Each filter has a nominal gain of 0 dB (1.0 in linear units) and + * boosts or cuts signals within a specific frequency range. + * The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz. + * Each band has an adjustable boost or cut in the range of +/- 9 dB. + * For example, the band that extends from 500 to 2000 Hz has the response shown below: + * \par + * \image html GEQ_bandresponse.gif + * \par + * With 1 dB steps, each filter has a total of 19 different settings. + * The filter coefficients for all possible 19 settings were precomputed + * in MATLAB and stored in a table. With 5 different tables, there are + * a total of 5 x 19 = 95 different 4th order filters. + * All 95 responses are shown below: + * \par + * \image html GEQ_allbandresponse.gif + * \par + * Each 4th order filter has 10 coefficents for a grand total of 950 different filter + * coefficients that must be tabulated. The input and output data is in Q31 format. + * For better noise performance, the two low frequency bands are implemented using the high + * precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard + * 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp. + * \par + * \image html GEQ_inputchirp.gif + * \par + * The array bandGains specifies the gain in dB to apply in each band. + * For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be: + * \par + * \image html GEQ_outputchirp.gif + * \par + * \note The output chirp signal follows the gain or boost of each band. + * \par + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c testRefOutput_f32 points to the reference output data + * \li \c testOutput points to the test output data + * \li \c inputQ31 temporary input buffer + * \li \c outputQ31 temporary output buffer + * \li \c biquadStateBand1Q31 points to state buffer for band1 + * \li \c biquadStateBand2Q31 points to state buffer for band2 + * \li \c biquadStateBand3Q31 points to state buffer for band3 + * \li \c biquadStateBand4Q31 points to state buffer for band4 + * \li \c biquadStateBand5Q31 points to state buffer for band5 + * \li \c coeffTable points to coefficient buffer for all bands + * \li \c gainDB gain buffer which has gains applied for all the bands + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_biquad_cas_df1_32x64_init_q31() + * - arm_biquad_cas_df1_32x64_q31() + * - arm_biquad_cascade_df1_init_q31() + * - arm_biquad_cascade_df1_q31() + * - arm_scale_q31() + * - arm_scale_f32() + * - arm_float_to_q31() + * - arm_q31_to_float() + * + * Refer + * \link arm_graphic_equalizer_example_q31.c \endlink + * + */ + + +/** \example arm_graphic_equalizer_example_q31.c + */ + + +#include "arm_math.h" +#include "math_helper.h" + +/* Length of the overall data in the test */ +#define TESTLENGTH 320 + +/* Block size for the underlying processing */ +#define BLOCKSIZE 32 + +/* Total number of blocks to run */ +#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE) + +/* Number of 2nd order Biquad stages per filter */ +#define NUMSTAGES 2 + +#define SNR_THRESHOLD_F32 98 + +/* ------------------------------------------------------------------- + * External Declarations for Input and Output buffers + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32[TESTLENGTH]; +static float32_t testOutput[TESTLENGTH]; + +extern float32_t testRefOutput_f32[TESTLENGTH]; + +/* ---------------------------------------------------------------------- +** Q31 state buffers for Band1, Band2, Band3, Band4, Band5 +** ------------------------------------------------------------------- */ + +static q63_t biquadStateBand1Q31[4 * 2]; +static q63_t biquadStateBand2Q31[4 * 2]; +static q31_t biquadStateBand3Q31[4 * 2]; +static q31_t biquadStateBand4Q31[4 * 2]; +static q31_t biquadStateBand5Q31[4 * 2]; + +/* ---------------------------------------------------------------------- +** Q31 input and output buffers +** ------------------------------------------------------------------- */ + +q31_t inputQ31[BLOCKSIZE]; +q31_t outputQ31[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +** Entire coefficient table. There are 10 coefficients per 4th order Biquad +** cascade filter. The first 10 coefficients correspond to the -9 dB gain +** setting of band 1; the next 10 coefficient correspond to the -8 dB gain +** setting of band 1; and so on. There are 10*19=190 coefficients in total +** for band 1 (gains = -9, -8, -7, ..., 9). After this come the 190 coefficients +** for band 2. +** +** The coefficients are in Q29 format and require a postShift of 2. +** ------------------------------------------------------------------- */ + +const q31_t coeffTable[950] = { + + /* Band 1, -9 dB gain */ + 535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981, + /* Band 1, -8 dB gain */ + 535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778, + 535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686, + 536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972, + 536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897, + 536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716, + 536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676, + 536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017, + 536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975, + 536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777, + 537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648, + 537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803, + 537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454, + 537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806, + 537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059, + 537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409, + 537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045, + 538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151, + 538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907, + + /* Band 2, -9 dB gain */ + 531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367, + /* Band 2, -8 dB gain */ + 532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122, + 532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090, + 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-745714425, -293206383, + 643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077, + 667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004, + 692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294, + 717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515, + 744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673 + +}; + +/* ---------------------------------------------------------------------- +** Desired gains, in dB, per band +** ------------------------------------------------------------------- */ + +int gainDB[5] = {0, -3, 6, 4, -6}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- + * Graphic equalizer Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + float32_t *inputF32, *outputF32; + arm_biquad_cas_df1_32x64_ins_q31 S1; + arm_biquad_cas_df1_32x64_ins_q31 S2; + arm_biquad_casd_df1_inst_q31 S3; + arm_biquad_casd_df1_inst_q31 S4; + arm_biquad_casd_df1_inst_q31 S5; + int i; + int32_t status; + + inputF32 = &testInput_f32[0]; + outputF32 = &testOutput[0]; + + /* Initialize the state and coefficient buffers for all Biquad sections */ + + arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES, + (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)], + &biquadStateBand1Q31[0], 2); + + arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES, + (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)], + &biquadStateBand2Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES, + (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)], + &biquadStateBand3Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES, + (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)], + &biquadStateBand4Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES, + (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)], + &biquadStateBand5Q31[0], 2); + + + /* Call the process functions and needs to change filter coefficients + for varying the gain of each band */ + + for(i=0; i < NUMBLOCKS; i++) + { + + /* ---------------------------------------------------------------------- + ** Convert block of input data from float to Q31 + ** ------------------------------------------------------------------- */ + + arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale down by 1/8. This provides additional headroom so that the + ** graphic EQ can apply gain. + ** ------------------------------------------------------------------- */ + + arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2 + ** ------------------------------------------------------------------- */ + + arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5 + ** ------------------------------------------------------------------- */ + + arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Convert Q31 result back to float + ** ------------------------------------------------------------------- */ + + arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale back up + ** ------------------------------------------------------------------- */ + + arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + }; + + snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH); + + if (snr < SNR_THRESHOLD_F32) + { + status = ARM_MATH_TEST_FAILURE; + } + else + { + status = ARM_MATH_SUCCESS; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signal does not match the reference output. + ** ------------------------------------------------------------------- */ + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + +/** \endlink */ + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c new file mode 100644 index 0000000..4b0ee1f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h new file mode 100644 index 0000000..46b0af3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt new file mode 100644 index 0000000..472fa34 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_linear_interp_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c new file mode 100644 index 0000000..5a53ec6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c @@ -0,0 +1,23616 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_linear_interp_data.c +* +* Description: Data file used for example. Generation method described +* below +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Table generated from following MATLAB Command +* x = -pi: 0.00005 : (2*pi - 0.00005); +* y = sin(x); +* where pi value is 3.141592653589793 +* --------------------------------------------------------------------*/ + +float arm_linear_interep_table[188495] = { + + +-0.000000000000000122, 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@@ -0,0 +1,204 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_linear_interp_example_f32.c +* +* Description: Example code demonstrating usage of sin function +* and uses linear interpolation to get higher precision +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup LinearInterpExample Linear Interpolate Example + * + * CMSIS DSP Software Library -- Linear Interpolate Example + * + * Description + * This example demonstrates usage of linear interpolate modules and fast math modules. + * Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses + * linear interpolation function and results are compared to reference output. + * Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation. + * + * \par Block Diagram: + * \par + * \image html linearInterpExampleMethod1.gif "Method 1: Sine caluclation using fast math" + * \par + * \image html linearInterpExampleMethod2.gif "Method 2: Sine caluclation using interpolation function" + * + * \par Variables Description: + * \par + * \li \c testInputSin_f32 points to the input values for sine calculation + * \li \c testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function + * \li \c testOutput points to output buffer calculation from cubic interpolation + * \li \c testLinIntOutput points to output buffer calculation from linear interpolation + * \li \c snr1 Signal to noise ratio for reference and cubic interpolation output + * \li \c snr2 Signal to noise ratio for reference and linear interpolation output + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_sin_f32() + * - arm_linear_interp_f32() + * + * Refer + * \link arm_linear_interp_example_f32.c \endlink + * + */ + + +/** \example arm_linear_interp_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#define SNR_THRESHOLD 90 +#define TEST_LENGTH_SAMPLES 10 +#define XSPACING (0.00005f) + +/* ---------------------------------------------------------------------- +* Test input data for F32 SIN function +* Generated by the MATLAB rand() function +* randn('state', 0) +* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi)); +* --------------------------------------------------------------------*/ +float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] = +{ + -0.649716504673081170, -2.501723745497831200, + 0.188250329003310100, 0.432092748487532540, + -1.722010988459680800, 1.788766476323060600, + 1.786136060975809500, -0.056525543169408797, + 0.491596272728153760, 0.262309671126153390 +}; + +/*------------------------------------------------------------------------------ +* Reference out of SIN F32 function for Block Size = 10 +* Calculated from sin(testInputSin_f32) +*------------------------------------------------------------------------------*/ +float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] = +{ + -0.604960695383043530, -0.597090287967934840, + 0.187140422442966500, 0.418772124875992690, + -0.988588831792106880, 0.976338412038794010, + 0.976903856413481100, -0.056495446835214236, + 0.472033731854734240, 0.259311907228582830 +}; + +/*------------------------------------------------------------------------------ +* Method 1: Test out Buffer Calculated from Cubic Interpolation +*------------------------------------------------------------------------------*/ +float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* Method 2: Test out buffer Calculated from Linear Interpolation +*------------------------------------------------------------------------------*/ +float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* External table used for linear interpolation +*------------------------------------------------------------------------------*/ +extern float arm_linear_interep_table[188495]; + +/* ---------------------------------------------------------------------- +* Global Variables for caluclating SNR's for Method1 & Method 2 +* ------------------------------------------------------------------- */ +float32_t snr1; +float32_t snr2; + +/* ---------------------------------------------------------------------------- +* Calculation of Sine values from Cubic Interpolation and Linear interpolation +* ---------------------------------------------------------------------------- */ +int32_t main(void) +{ + uint32_t i; + arm_status status; + + arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, &arm_linear_interep_table[0]}; + + /*------------------------------------------------------------------------------ + * Method 1: Test out Calculated from Cubic Interpolation + *------------------------------------------------------------------------------*/ + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testOutput[i] = arm_sin_f32(testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation + *------------------------------------------------------------------------------*/ + + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * SNR calculation for method 1 + *------------------------------------------------------------------------------*/ + snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2); + + /*------------------------------------------------------------------------------ + * SNR calculation for method 2 + *------------------------------------------------------------------------------*/ + snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + if ( snr2 > snr1) + { + status = ARM_MATH_SUCCESS; + } + else + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c new file mode 100644 index 0000000..4b0ee1f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h new file mode 100644 index 0000000..46b0af3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt new file mode 100644 index 0000000..6bc6ae8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_matrix_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c new file mode 100644 index 0000000..078b547 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_matrix_example_f32.c +* +* Description: Example code demonstrating least square fit to data +* using matrix functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup MatrixExample Matrix Example + * + * \par Description: + * \par + * Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse + * functions to apply least squares fitting to input data. Least squares fitting is + * the procedure for finding the best-fitting curve that minimizes the sum of the + * squares of the offsets (least square error) from a given set of data. + * + * \par Algorithm: + * \par + * The linear combination of parameters considered is as follows: + * \par + * A * X = B, where \c X is the unknown value and can be estimated + * from \c A & \c B. + * \par + * The least squares estimate \c X is given by the following equation: + * \par + * X = Inverse(AT * A) * AT * B + * + * \par Block Diagram: + * \par + * \image html matrixExample.gif + * + * \par Variables Description: + * \par + * \li \c A_f32 input matrix in the linear combination equation + * \li \c B_f32 output matrix in the linear combination equation + * \li \c X_f32 unknown matrix estimated using \c A_f32 & \c B_f32 matrices + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_trans_f32() + * - arm_mat_mult_f32() + * - arm_mat_inverse_f32() + * + * Refer + * \link arm_matrix_example_f32.c \endlink + * + */ + + +/** \example arm_matrix_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#define SNR_THRESHOLD 90 + +/* -------------------------------------------------------------------------------- +* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize +* and tapSize +* --------------------------------------------------------------------------------- */ + +const float32_t B_f32[4] = +{ + 782.0, 7577.0, 470.0, 4505.0 +}; + +/* -------------------------------------------------------------------------------- +* Formula to fit is C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize +* -------------------------------------------------------------------------------- */ + +const float32_t A_f32[16] = +{ + /* Const, numTaps, blockSize, numTaps*blockSize */ + 1.0, 32.0, 4.0, 128.0, + 1.0, 32.0, 64.0, 2048.0, + 1.0, 16.0, 4.0, 64.0, + 1.0, 16.0, 64.0, 1024.0, +}; + + +/* ---------------------------------------------------------------------- +* Temporary buffers for storing intermediate values +* ------------------------------------------------------------------- */ +/* Transpose of A Buffer */ +float32_t AT_f32[16]; +/* (Transpose of A * A) Buffer */ +float32_t ATMA_f32[16]; +/* Inverse(Transpose of A * A) Buffer */ +float32_t ATMAI_f32[16]; +/* Test Output Buffer */ +float32_t X_f32[4]; + +/* ---------------------------------------------------------------------- +* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB +* ------------------------------------------------------------------- */ +const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_matrix_instance_f32 A; /* Matrix A Instance */ + arm_matrix_instance_f32 AT; /* Matrix AT(A transpose) instance */ + arm_matrix_instance_f32 ATMA; /* Matrix ATMA( AT multiply with A) instance */ + arm_matrix_instance_f32 ATMAI; /* Matrix ATMAI(Inverse of ATMA) instance */ + arm_matrix_instance_f32 B; /* Matrix B instance */ + arm_matrix_instance_f32 X; /* Matrix X(Unknown Matrix) instance */ + + uint32_t srcRows, srcColumns; /* Temporary variables */ + arm_status status; + + /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32); + + /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32); + + /* calculation of A transpose */ + status = arm_mat_trans_f32(&A, &AT); + + + /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32); + + /* calculation of AT Multiply with A */ + status = arm_mat_mult_f32(&AT, &A, &ATMA); + + /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32); + + /* calculation of Inverse((Transpose(A) * A) */ + status = arm_mat_inverse_f32(&ATMA, &ATMAI); + + /* calculation of (Inverse((Transpose(A) * A)) * Transpose(A)) */ + status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA); + + /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32); + + /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&X, srcRows, srcColumns, X_f32); + + /* calculation ((Inverse((Transpose(A) * A)) * Transpose(A)) * B) */ + status = arm_mat_mult_f32(&ATMA, &B, &X); + + /* Comparison of reference with test output */ + snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + if ( snr > SNR_THRESHOLD) + { + status = ARM_MATH_SUCCESS; + } + else + { + status = ARM_MATH_TEST_FAILURE; + } + + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c new file mode 100644 index 0000000..4b0ee1f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h new file mode 100644 index 0000000..46b0af3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt new file mode 100644 index 0000000..0f68db7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_signal_converge_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c new file mode 100644 index 0000000..ddb1278 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c @@ -0,0 +1,269 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_signal_converge_data.c +* +* Description: Test input data for Floating point LMS Norm FIR filter +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input data for Floating point LMS Norm FIR filter +** Generated by the MATLAB randn() function +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[1536] = +{ +-0.432565, -1.665584, 0.125332, 0.287676, -1.146471, 1.190915, 1.189164, -0.037633, +0.327292, 0.174639, -0.186709, 0.725791, -0.588317, 2.183186, -0.136396, 0.113931, +1.066768, 0.059281, -0.095648, -0.832349, 0.294411, -1.336182, 0.714325, 1.623562, +-0.691776, 0.857997, 1.254001, -1.593730, -1.440964, 0.571148, -0.399886, 0.689997, +0.815622, 0.711908, 1.290250, 0.668601, 1.190838, -1.202457, -0.019790, -0.156717, +-1.604086, 0.257304, -1.056473, 1.415141, -0.805090, 0.528743, 0.219321, -0.921902, +-2.170674, -0.059188, -1.010634, 0.614463, 0.507741, 1.692430, 0.591283, -0.643595, +0.380337, -1.009116, -0.019511, -0.048221, 0.000043, -0.317859, 1.095004, -1.873990, +0.428183, 0.895638, 0.730957, 0.577857, 0.040314, 0.677089, 0.568900, -0.255645, +-0.377469, -0.295887, -1.475135, -0.234004, 0.118445, 0.314809, 1.443508, -0.350975, +0.623234, 0.799049, 0.940890, -0.992092, 0.212035, 0.237882, -1.007763, -0.742045, +1.082295, -0.131500, 0.389880, 0.087987, -0.635465, -0.559573, 0.443653, -0.949904, +0.781182, 0.568961, -0.821714, -0.265607, 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0.499826, 1.278084, +-0.547816, 0.260808, -0.013177, -0.580264, 2.136308, -0.257617, -1.409528, 1.770101, +0.325546, -1.119040, 0.620350, 1.269782, -0.896043, 0.135175, -0.139040, -1.163395, +1.183720, -0.015430, 0.536219, -0.716429, -0.655559, 0.314363, 0.106814, 1.848216, +-0.275106, 2.212554, 1.508526, -1.945079, -1.680543, -0.573534, -0.185817, 0.008934, +0.836950, -0.722271, -0.721490, -0.201181, -0.020464, 0.278890, 1.058295, 0.621673, +-1.750615, 0.697348, 0.811486, 0.636345, 1.310080, 0.327098, -0.672993, -0.149327, +-2.449018, 0.473286, 0.116946, -0.591104, -0.654708, -1.080662, -0.047731, 0.379345, +-0.330361, -0.499898, -0.035979, -0.174760, -0.957265, 1.292548, 0.440910, 1.280941, +-0.497730, -1.118717, 0.807650, 0.041200, -0.756209, -0.089129, -2.008850, 1.083918, +-0.981191, -0.688489, 1.339479, -0.909243, -0.412858, -0.506163, 1.619748, 0.080901, +-1.081056, -1.124518, 1.735676, 1.937459, 1.635068, -1.255940, -0.213538, -0.198932, +0.307499, -0.572325, -0.977648, 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-1.634939, -0.536325, 0.547223, 1.492603, -0.455243, -0.496416, 1.235260, +0.040926, 0.748467, 1.230764, 0.304903, 1.077771, 0.765151, -1.319580, -0.509191, +0.555116, -1.957625, -0.760453, -2.443886, -0.659366, -0.114779, 0.300079, -0.583996, +-3.073745, 1.551042, -0.407369, 1.428095, -1.353242, 0.903970, 0.541671, -0.465020 +}; + + + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point LMS FIR filter +* FIR high pass filter with cutoff freq 9.6kHz (transition 9.6KHz to 11.52KHz) +** ------------------------------------------------------------------- */ +float32_t lmsNormCoeff_f32[32] = { +-0.004240, 0.002301, 0.008860, -0.000000, -0.019782, -0.010543, 0.032881, 0.034736, +-0.037374, -0.069586, 0.022397, 0.102169, 0.014185, -0.115908, -0.061648, 0.101018, +0.101018, -0.061648, -0.115908, 0.014185, 0.102169, 0.022397, -0.069586, -0.037374, +0.034736, 0.032881, -0.010543, -0.019782, -0.000000, 0.008860, 0.002301, -0.004240 + +}; + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point FIR filter +* FIR low pass filter with cutoff freq 24Hz (transition 24Hz to 240Hz) +** ------------------------------------------------------------------- */ +const float32_t FIRCoeff_f32[32] = { +0.004502, 0.005074, 0.006707, 0.009356, 0.012933, 0.017303, 0.022298, 0.027717, +0.033338, 0.038930, 0.044258, 0.049098, 0.053243, 0.056519, 0.058784, 0.059941, +0.059941, 0.058784, 0.056519, 0.053243, 0.049098, 0.044258, 0.038930, 0.033338, +0.027717, 0.022298, 0.017303, 0.012933, 0.009356, 0.006707, 0.005074, 0.004502 + +}; + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c new file mode 100644 index 0000000..ae25ce9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c @@ -0,0 +1,259 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_signal_converge_example_f32.c +* +* Description: Example code demonstrating convergence of an adaptive +* filter. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SignalConvergence Signal Convergence Example + * + * \par Description: + * \par + * Demonstrates the ability of an adaptive filter to "learn" the transfer function of + * a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse + * Response (FIR) Filter, and Basic Math Functions. + * + * \par Algorithm: + * \par + * The figure below illustrates the signal flow in this example. Uniformly distributed white + * noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the + * reference input of the adaptive filter (normalized LMS filter). The white noise is input + * to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter. + * The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and + * (2) the error signal which is the difference between the adaptive filter and the reference + * output of the FIR filter. Over time as the adaptive filter learns the transfer function + * of the FIR filter, the first output approaches the reference output of the FIR filter, + * and the error signal approaches zero. + * \par + * The adaptive filter converges properly even if the input signal has a large dynamic + * range (i.e., varies from small to large values). The coefficients of the adaptive filter + * are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() + * implements the stopping condition. The function checks if all of the values of the error signal have a + * magnitude below a threshold DELTA. + * + * \par Block Diagram: + * \par + * \image html SignalFlow.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c firStateF32 points to FIR state buffer + * \li \c lmsStateF32 points to Normalised Least mean square FIR filter state buffer + * \li \c FIRCoeff_f32 points to coefficient buffer + * \li \c lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer + * \li \c wire1, wir2, wire3 temporary buffers + * \li \c errOutput, err_signal temporary error buffers + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_lms_norm_init_f32() + * - arm_fir_init_f32() + * - arm_fir_f32() + * - arm_lms_norm_f32() + * - arm_scale_f32() + * - arm_abs_f32() + * - arm_sub_f32() + * - arm_min_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_signal_converge_example_f32.c \endlink + * + */ + + +/** \example arm_signal_converge_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +** Global defines for the simulation +* ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 1536 +#define NUMTAPS 32 +#define BLOCKSIZE 32 +#define DELTA_ERROR 0.000001f +#define DELTA_COEFF 0.0001f +#define MU 0.5f + +#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE) + +/* ---------------------------------------------------------------------- +* Declare FIR state buffers and structure +* ------------------------------------------------------------------- */ + +float32_t firStateF32[NUMTAPS + BLOCKSIZE]; +arm_fir_instance_f32 LPF_instance; + +/* ---------------------------------------------------------------------- +* Declare LMSNorm state buffers and structure +* ------------------------------------------------------------------- */ + +float32_t lmsStateF32[NUMTAPS + BLOCKSIZE]; +float32_t errOutput[TEST_LENGTH_SAMPLES]; +arm_lms_norm_instance_f32 lmsNorm_instance; + + +/* ---------------------------------------------------------------------- +* Function Declarations for Signal Convergence Example +* ------------------------------------------------------------------- */ + +arm_status test_signal_converge_example( void ); + + +/* ---------------------------------------------------------------------- +* Internal functions +* ------------------------------------------------------------------- */ +arm_status test_signal_converge(float32_t* err_signal, + uint32_t blockSize); + +void getinput(float32_t* input, + uint32_t fr_cnt, + uint32_t blockSize); + +/* ---------------------------------------------------------------------- +* External Declarations for FIR F32 module Test +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32[TEST_LENGTH_SAMPLES]; +extern float32_t lmsNormCoeff_f32[32]; +extern const float32_t FIRCoeff_f32[32]; +extern arm_lms_norm_instance_f32 lmsNorm_instance; + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ + +float32_t wire1[BLOCKSIZE]; +float32_t wire2[BLOCKSIZE]; +float32_t wire3[BLOCKSIZE]; +float32_t err_signal[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Signal converge test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_status status; + uint32_t index; + float32_t minValue; + + /* Initialize the LMSNorm data structure */ + arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE); + + /* Initialize the FIR data structure */ + arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + * Loop over the frames of data and execute each of the processing + * functions in the system. + * ------------------------------------------------------------------- */ + + for(i=0; i < NUMFRAMES; i++) + { + /* Read the input data - uniformly distributed random noise - into wire1 */ + arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE); + + /* Execute the FIR processing function. Input wire1 and output wire2 */ + arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE); + + /* Execute the LMS Norm processing function*/ + + arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */ + wire1, /* Input signal */ + wire2, /* Reference Signal */ + wire3, /* Converged Signal */ + err_signal, /* Error Signal, this will become small as the signal converges */ + BLOCKSIZE); /* BlockSize */ + + /* apply overall gain */ + arm_scale_f32(wire3, 5, wire3, BLOCKSIZE); /* in-place buffer */ + } + + status = ARM_MATH_SUCCESS; + + /* ------------------------------------------------------------------------------- + * Test whether the error signal has reached towards 0. + * ----------------------------------------------------------------------------- */ + + arm_abs_f32(err_signal, err_signal, BLOCKSIZE); + arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index); + + if (minValue > DELTA_ERROR) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + * Test whether the filter coefficients have converged. + * ------------------------------------------------------------------- */ + + arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + + arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index); + + if (minValue > DELTA_COEFF) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + * Loop here if the signals did not pass the convergence check. + * This denotes a test failure + * ------------------------------------------------------------------- */ + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c new file mode 100644 index 0000000..4b0ee1f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h new file mode 100644 index 0000000..46b0af3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt new file mode 100644 index 0000000..6d9e7c7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_sin_cos_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c new file mode 100644 index 0000000..9e65b2c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.3 +* +* Project: CMSIS DSP Library +* Title: arm_sin_cos_example_f32.c +* +* Description: Example code demonstrating sin and cos calculation of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SinCosExample SineCosine Example + * + * \par Description: + * \par + * Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector + * Multiplication, and Vector Addition functions. + * + * \par Algorithm: + * \par + * Mathematically, the Pythagorean trignometric identity is defined by the following equation: + * 
sin(x) * sin(x) + cos(x) * cos(x) = 1
+ * where \c x is the angle in radians. + * + * \par Block Diagram: + * \par + * \image html sinCos.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32 array of input angle in radians + * \li \c testOutput stores sum of the squares of sine and cosine values of input angle + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cos_f32() + * - arm_sin_f32() + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_sin_cos_example_f32.c \endlink + * + */ + + +/** \example arm_sin_cos_example_f32.c + */ + +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.0001f) + + +/* ---------------------------------------------------------------------- +* Test input data for Floating point sin_cos example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +const float32_t testInput_f32[MAX_BLOCKSIZE] = +{ + -1.244916875853235400, -4.793533929171324800, 0.360705030233248850, 0.827929644170887320, -3.299532218312426900, 3.427441903227623800, 3.422401784294607700, -0.108308165334010680, + 0.941943896490312180, 0.502609575000365850, -0.537345278736373500, 2.088817392965764500, -1.693168684143455700, 6.283185307179590700, -0.392545884746175080, 0.327893095115825040, + 3.070147440456292300, 0.170611405884662230, -0.275275082396073010, -2.395492805446796300, 0.847311163536506600, -3.845517018083148800, 2.055818378415868300, 4.672594161978930800, + -1.990923030266425800, 2.469305197656249500, 3.609002606064021000, -4.586736582331667500, -4.147080139136136300, 1.643756718868359500, -1.150866392366494800, 1.985805026477433800 + + +}; + +const float32_t testRefOutput_f32 = 1.000000000; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t testOutput; +float32_t cosOutput; +float32_t sinOutput; +float32_t cosSquareOutput; +float32_t sinSquareOutput; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +arm_status status; + +int32_t main(void) +{ + float32_t diff; + uint32_t i; + + for(i=0; i< blockSize; i++) + { + cosOutput = arm_cos_f32(testInput_f32[i]); + sinOutput = arm_sin_f32(testInput_f32[i]); + + arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1); + arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1); + + arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(testRefOutput_f32 - testOutput); + + /* Comparison of sin_cos value with reference */ + if (diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if ( status == ARM_MATH_TEST_FAILURE) + { + while (1); + } + + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt new file mode 100644 index 0000000..371c79c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_variance_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt new file mode 100644 index 0000000..a2084d7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt @@ -0,0 +1,46 @@ +cmake_minimum_required (VERSION 3.6) +project (arm_variance_example VERSION 0.1) + +# Needed to include the configBoot module +list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/../../..) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_variance_example) + +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) + +include(configBoot) + +target_sources(arm_variance_example PRIVATE arm_variance_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_variance_example PRIVATE CMSISDSP) + +################################### +# +# INSTALLATION +# +################################### + +install (TARGETS arm_variance_example DESTINATION "${PROJECT_SOURCE_DIR}/varianceExampleBuild.axf") \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..3333bc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..2bf6f19 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f56b85f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..f5270c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..731facd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..abddc8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..69e2a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c new file mode 100644 index 0000000..13dde7b --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c @@ -0,0 +1,225 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_variance_example_f32.c +* +* Description: Example code demonstrating variance calculation of input sequence. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup VarianceExample Variance Example + * + * \par Description: + * \par + * Demonstrates the use of Basic Math and Support Functions to calculate the variance of an + * input sequence with N samples. Uniformly distributed white noise is taken as input. + * + * \par Algorithm: + * \par + * The variance of a sequence is the mean of the squared deviation of the sequence from its mean. + * \par + * This is denoted by the following equation: + * 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
+ * where, x[n] is the input sequence, N is the number of input samples, and + * x' is the mean value of the input sequence, x[n]. + * \par + * The mean value x' is defined as: + * 
 x' = (x[0] + x[1] + ... + x[n-1]) / N
+ * + * \par Block Diagram: + * \par + * \image html Variance.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c wire1, \c wir2, \c wire3 temporary buffers + * \li \c blockSize number of samples processed at a time + * \li \c refVarianceOut reference variance value + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_dot_prod_f32() + * - arm_mult_f32() + * - arm_sub_f32() + * - arm_fill_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_variance_example_f32.c \endlink + * + */ + + +/** \example arm_variance_example_f32.c + */ + +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t wire1[MAX_BLOCKSIZE]; +float32_t wire2[MAX_BLOCKSIZE]; +float32_t wire3[MAX_BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Variance example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +float32_t testInput_f32[32] = +{ + -0.432564811528221, -1.665584378238097, 0.125332306474831, 0.287676420358549, + -1.146471350681464, 1.190915465642999, 1.189164201652103, -0.037633276593318, + 0.327292361408654, 0.174639142820925, -0.186708577681439, 0.725790548293303, + -0.588316543014189, 2.183185818197101, -0.136395883086596, 0.113931313520810, + 1.066768211359189, 0.059281460523605, -0.095648405483669, -0.832349463650022, + 0.294410816392640, -1.336181857937804, 0.714324551818952, 1.623562064446271, + -0.691775701702287, 0.857996672828263, 1.254001421602532, -1.593729576447477, + -1.440964431901020, 0.571147623658178, -0.399885577715363, 0.689997375464345 + +}; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t refVarianceOut = 0.903941793931839; + +/* ---------------------------------------------------------------------- +* Variance calculation test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + arm_status status; + float32_t mean, oneByBlockSize; + float32_t variance; + float32_t diff; + + status = ARM_MATH_SUCCESS; + +#if defined(FILEIO) + printf("START\n"); +#endif + + + /* Calculation of mean value of input */ + + /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + + /* Fill wire1 buffer with 1.0 value */ + arm_fill_f32(1.0, wire1, blockSize); + + /* Calculate the dot product of wire1 and wire2 */ + /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */ + arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize); + + /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + arm_mult_f32(&mean, &oneByBlockSize, &mean, 1); + + + /* Calculation of variance value of input */ + + /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + + /* Fill wire2 with mean value x' */ + arm_fill_f32(mean, wire2, blockSize); + + /* wire3 contains (x-x') */ + arm_sub_f32(testInput_f32, wire2, wire3, blockSize); + + /* wire2 contains (x-x') */ + arm_copy_f32(wire3, wire2, blockSize); + + /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + arm_dot_prod_f32(wire2, wire3, blockSize, &variance); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize - 1); + + /* Calculation of variance */ + arm_mult_f32(&variance, &oneByBlockSize, &variance, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(refVarianceOut - variance); + + /* Comparison of variance value with reference */ + + if (diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + +#if !defined(FILEIO) + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +#else + if (status == ARM_MATH_SUCCESS) + { + printf("SUCCESS\n"); + } + else + { + printf("FAILURE\n"); + } +#endif +} + + /** \endlink */ + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/boot/RTE_Components.h b/Drivers/CMSIS/DSP/Examples/ARM/boot/RTE_Components.h new file mode 100644 index 0000000..db747a6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/boot/RTE_Components.h @@ -0,0 +1,5 @@ +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +#endif /* RTE_COMPONENTS_H */ \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/Include/arm_common_tables.h b/Drivers/CMSIS/DSP/Include/arm_common_tables.h new file mode 100644 index 0000000..6a4337f --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_common_tables.h @@ -0,0 +1,378 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/Drivers/CMSIS/DSP/Include/arm_const_structs.h b/Drivers/CMSIS/DSP/Include/arm_const_structs.h new file mode 100644 index 0000000..80a3e8b --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/Drivers/CMSIS/DSP/Include/arm_math.h b/Drivers/CMSIS/DSP/Include/arm_math.h new file mode 100644 index 0000000..eb37f82 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_math.h @@ -0,0 +1,7361 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.6.0 + * @date 18. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP\\Projects\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_LOOPUNROLL: + * + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + * - ARM_MATH_NEON: + * + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * + * - ARM_MATH_NEON_EXPERIMENTAL: + * + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if !defined ( _MSC_VER ) +#include "cmsis_compiler.h" +#else +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __ALIGNED(x) __declspec(align(x)) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + +#include "string.h" +#include "math.h" +#include "float.h" + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(__ARM_NEON) +#include +#endif + + +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + + memcpy (&val, pQ15, 4); + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + + memcpy (&val, *pQ15, 4); + *pQ15 += 2; + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + + memcpy (&val, *pQ15, 4); + *pQ15 -= 2; + + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; + + memcpy (*pQ15, &val, 4); + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + + memcpy (pQ15, &val, 4); +} + + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + + memcpy (&val, *pQ7, 4); + *pQ7 += 4; + + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; + + memcpy (&val, *pQ7, 4); + *pQ7 -= 4; + + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; + + memcpy (*pQ7, &val, 4); + *pQ7 += 4; +} + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#ifndef ARM_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + +#if defined(ARM_MATH_NEON) + +static inline float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +static inline int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +static inline int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +arm_status arm_rfft_32_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_64_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_128_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_256_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_512_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_1024_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_2048_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_4096_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + + + void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +void arm_biquad_cascade_df2T_compute_coefs_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   *
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + __STATIC_FORCEINLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + __STATIC_FORCEINLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + void arm_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void arm_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + + void arm_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/Drivers/CMSIS/DSP/Lib/ARM/arm_ARMv8MBLl_math.lib b/Drivers/CMSIS/DSP/Lib/ARM/arm_ARMv8MBLl_math.lib new file mode 100644 index 0000000..e263854 Binary files /dev/null and b/Drivers/CMSIS/DSP/Lib/ARM/arm_ARMv8MBLl_math.lib differ diff --git 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Wrapper + * Title: cmsismodule.c + * Description: C code for the CMSIS-DSP Python wrapper + * + * $Date: 25. March 2019 + * $Revision: V0.0.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#define NPY_NO_DEPRECATED_API NPY_1_15_API_VERSION + +#ifdef WIN +#pragma warning( disable : 4013 ) +#pragma warning( disable : 4244 ) +#endif + +#include +#define MAX(A,B) (A) < (B) ? (B) : (A) + +#define CAT1(A,B) A##B +#define CAT(A,B) CAT1(A,B) + + +#ifdef CMSISDSP +#include "arm_math.h" +#define MODNAME "cmsisdsp" +#define MODINITNAME cmsisdsp +#endif + +#include +#include + +#if PY_MAJOR_VERSION >= 3 +#define IS_PY3K +#endif + +struct module_state { + PyObject *error; +}; + +#if PY_MAJOR_VERSION >= 3 +#define GETSTATE(m) ((struct module_state*)PyModule_GetState(m)) +#else +#define GETSTATE(m) (&_state) +static struct module_state _state; +#endif + +static PyObject * +error_out(PyObject *m) { + struct module_state *st = GETSTATE(m); + PyErr_SetString(st->error, "something bad happened"); + return NULL; +} + +#define MLTYPE(name,thenewfunc,deallocfunc,initfunc,methods)\ +static PyTypeObject ml_##name##Type = { \ + PyVarObject_HEAD_INIT(NULL, 0) \ + .tp_name=MODNAME".##name", \ + .tp_basicsize = sizeof(ml_##name##Object), \ + .tp_itemsize = 0, \ + .tp_dealloc = (destructor)deallocfunc, \ + .tp_flags = Py_TPFLAGS_DEFAULT, \ + .tp_doc = #name, \ + .tp_init = (initproc)initfunc, \ + .tp_new = (newfunc)thenewfunc, \ + .tp_methods = methods \ + }; + + +#define MEMCPY(DST,SRC,NB,FORMAT) \ +for(memCpyIndex = 0; memCpyIndex < (NB) ; memCpyIndex++)\ +{ \ + (DST)[memCpyIndex] = (FORMAT)(SRC)[memCpyIndex]; \ +} + +#define GETFIELD(NAME,FIELD,FORMAT) \ +static PyObject * \ +Method_##NAME##_##FIELD(ml_##NAME##Object *self, PyObject *ignored)\ +{ \ + return(Py_BuildValue(FORMAT,self->instance->FIELD)); \ +} + +#define GETFIELDARRAY(NAME,FIELD,FORMAT) \ +static PyObject * \ +Method_##NAME##_##FIELD(ml_##NAME##Object *self, PyObject *ignored)\ +{ \ + return(specific_##NAME##_##FIELD(self->instance)); \ +} + +#define INITARRAYFIELD(FIELD,FORMAT,SRCFORMAT,DSTFORMAT) \ + if (FIELD) \ + { \ + PyArray_Descr *desct=PyArray_DescrFromType(FORMAT); \ + PyArrayObject *FIELD##c = (PyArrayObject *)PyArray_FromAny(FIELD,desct,\ + 1,0,NPY_ARRAY_C_CONTIGUOUS | NPY_ARRAY_ALIGNED | NPY_ARRAY_FORCECAST, \ + NULL); \ + if (FIELD##c) \ + { \ + uint32_t memCpyIndex; \ + SRCFORMAT *f=(SRCFORMAT*)PyArray_DATA(FIELD##c); \ + uint32_t n = PyArray_SIZE(FIELD##c); \ + self->instance->FIELD =PyMem_Malloc(sizeof(DSTFORMAT)*n); \ + MEMCPY(self->instance->FIELD ,f,n,DSTFORMAT); \ + Py_DECREF(FIELD##c); \ + } \ + } +#define GETCARRAY(PYVAR,CVAR,FORMAT,SRCFORMAT,DSTFORMAT) \ + if (PYVAR) \ + { \ + PyArray_Descr *desct=PyArray_DescrFromType(FORMAT); \ + PyArrayObject *PYVAR##c = (PyArrayObject *)PyArray_FromAny(PYVAR,desct,\ + 1,0,NPY_ARRAY_C_CONTIGUOUS | NPY_ARRAY_ALIGNED | NPY_ARRAY_FORCECAST, \ + NULL); \ + if (PYVAR##c) \ + { \ + uint32_t memCpyIndex; \ + SRCFORMAT *f=(SRCFORMAT*)PyArray_DATA(PYVAR##c); \ + uint32_t n = PyArray_SIZE(PYVAR##c); \ + CVAR =PyMem_Malloc(sizeof(DSTFORMAT)*n); \ + MEMCPY(CVAR ,f,n,DSTFORMAT); \ + Py_DECREF(PYVAR##c); \ + } \ + } + +#define GETARGUMENT(FIELD,FORMAT,SRCFORMAT,DSTFORMAT) \ + uint32_t arraySize##FIELD=0; \ + if (FIELD) \ + { \ + PyArray_Descr *desct=PyArray_DescrFromType(FORMAT); \ + PyArrayObject *FIELD##c = (PyArrayObject *)PyArray_FromAny(FIELD,desct, \ + 1,0,NPY_ARRAY_C_CONTIGUOUS | NPY_ARRAY_ALIGNED | NPY_ARRAY_FORCECAST, \ + NULL); \ + if (FIELD##c) \ + { \ + uint32_t memCpyIndex; \ + SRCFORMAT *f=(SRCFORMAT*)PyArray_DATA(FIELD##c); \ + arraySize##FIELD = PyArray_SIZE(FIELD##c); \ + FIELD##_converted =PyMem_Malloc(sizeof(DSTFORMAT)*arraySize##FIELD);\ + MEMCPY(FIELD##_converted ,f,arraySize##FIELD,DSTFORMAT); \ + Py_DECREF(FIELD##c); \ + } \ + } + +#define FREEARGUMENT(FIELD) \ + PyMem_Free(FIELD) + +#ifdef IS_PY3K +#define ADDTYPE(name) \ + if (PyType_Ready(&ml_##name##Type) < 0) \ + return; \ + \ + Py_INCREF(&ml_##name##Type); \ + PyModule_AddObject(module, #name, (PyObject *)&ml_##name##Type); +#else +#define ADDTYPE(name) \ + if (PyType_Ready(&ml_##name##Type) < 0) \ + return; \ + \ + Py_INCREF(&ml_##name##Type); \ + PyModule_AddObject(module, #name, (PyObject *)&ml_##name##Type); +#endif + +#define FLOATARRAY2(OBJ,NB1,NB2,DATA) \ + npy_intp dims[2]; \ + dims[0]=NB1; \ + dims[1]=NB2; \ + const int ND=2; \ + PyObject *OBJ=PyArray_SimpleNewFromData(ND, dims, NPY_FLOAT, DATA); + +#define FLOATARRAY1(OBJ,NB1,DATA) \ + npy_intp dims[1]; \ + dims[0]=NB1; \ + const int ND=1; \ + PyObject *OBJ=PyArray_SimpleNewFromData(ND, dims, NPY_FLOAT, DATA); + +#define FLOAT64ARRAY1(OBJ,NB1,DATA) \ + npy_intp dims[1]; \ + dims[0]=NB1; \ + const int ND=1; \ + PyObject *OBJ=PyArray_SimpleNewFromData(ND, dims, NPY_DOUBLE, DATA); + +#define UINT32ARRAY1(OBJ,NB1,DATA) \ + npy_intp dims[1]; \ + dims[0]=NB1; \ + const int ND=1; \ + PyObject *OBJ=PyArray_SimpleNewFromData(ND, dims, NPY_UINT32, DATA); + +#define INT32ARRAY1(OBJ,NB1,DATA) \ + npy_intp dims[1]; \ + dims[0]=NB1; \ + const int ND=1; \ + PyObject *OBJ=PyArray_SimpleNewFromData(ND, dims, NPY_INT32, DATA); + +#define INT16ARRAY1(OBJ,NB1,DATA) \ + npy_intp dims[1]; \ + dims[0]=NB1; \ + const int ND=1; \ + PyObject *OBJ=PyArray_SimpleNewFromData(ND, dims, NPY_INT16, DATA); + +#define INT8ARRAY1(OBJ,NB1,DATA) \ + npy_intp dims[1]; \ + dims[0]=NB1; \ + const int ND=1; \ + PyObject *OBJ=PyArray_SimpleNewFromData(ND, dims, NPY_BYTE, DATA); + + +#define MATRIXFROMNUMPY(EXT,TYP,SRCTYPE,NUMPYTYPE) \ +arm_matrix_instance_##EXT *EXT##MatrixFromNumpy(PyObject *o) \ +{ \ + arm_matrix_instance_##EXT *s; \ + \ + s=PyMem_Malloc(sizeof(arm_matrix_instance_##EXT)); \ + s->pData=NULL; \ + s->numRows=0; \ + s->numCols=0; \ + \ + PyArray_Descr *desct=PyArray_DescrFromType(NUMPYTYPE); \ + PyArrayObject *cdata = (PyArrayObject *)PyArray_FromAny(o,desct, \ + 1,0,NPY_ARRAY_C_CONTIGUOUS | NPY_ARRAY_ALIGNED | NPY_ARRAY_FORCECAST, \ + NULL); \ + if (cdata) \ + { \ + uint32_t memCpyIndex; \ + SRCTYPE *f=(SRCTYPE*)PyArray_DATA(cdata); \ + s->numRows=PyArray_DIM(cdata,0); \ + s->numCols=PyArray_DIM(cdata,1); \ + uint32_t nb = PyArray_SIZE(cdata); \ + s->pData = PyMem_Malloc(sizeof(TYP)*nb); \ + MEMCPY(s->pData ,f,nb,TYP); \ + Py_DECREF(cdata); \ + } \ + \ + \ + return(s); \ + \ +} + +MATRIXFROMNUMPY(f32,float32_t,double,NPY_DOUBLE); +MATRIXFROMNUMPY(f64,float64_t,double,NPY_DOUBLE); +MATRIXFROMNUMPY(q31,q31_t,int32_t,NPY_INT32); +MATRIXFROMNUMPY(q15,q15_t,int16_t,NPY_INT16); + +#define CREATEMATRIX(EXT,TYP) \ +arm_matrix_instance_##EXT *create##EXT##Matrix(uint32_t r,uint32_t c)\ +{ \ + arm_matrix_instance_##EXT *s; \ + \ + s=PyMem_Malloc(sizeof(arm_matrix_instance_##EXT)); \ + s->pData=PyMem_Malloc(sizeof(TYP)*r*c); \ + s->numRows=r; \ + s->numCols=c; \ + return(s); \ +} + +CREATEMATRIX(f32,float32_t); +CREATEMATRIX(f64,float64_t); +CREATEMATRIX(q31,q31_t); +CREATEMATRIX(q15,q15_t); + +#define NUMPYARRAYFROMMATRIX(EXT,NUMPYTYPE_FROMC) \ +PyObject *NumpyArrayFrom##EXT##Matrix(arm_matrix_instance_##EXT *mat) \ +{ \ + npy_intp dims[2]; \ + dims[0]=mat->numRows; \ + dims[1]=mat->numCols; \ + const int ND=2; \ + PyObject *OBJ=PyArray_SimpleNewFromData(ND, dims, NUMPYTYPE_FROMC, mat->pData);\ + return(OBJ); \ +} + +NUMPYARRAYFROMMATRIX(f32,NPY_FLOAT); +NUMPYARRAYFROMMATRIX(f64,NPY_DOUBLE); +NUMPYARRAYFROMMATRIX(q31,NPY_INT32); +NUMPYARRAYFROMMATRIX(q15,NPY_INT16); + +//#include "specific.h" +#include "cmsismodule.h" + +#if 0 +static PyObject *cmsisml_test(PyObject *obj, PyObject *args) +{ + ml_arm_svm_linear_instance_f32Object *self=NULL; + PyObject *svm, *vector=NULL; + + if (!PyArg_ParseTuple(args, "OO", &svm,&vector)) + return NULL; + + self=(ml_arm_svm_linear_instance_f32Object*)svm; + if (self) + { + if (self->instance) + { + int result; + float32_t *input=NULL; + GETCARRAY(vector,input,NPY_DOUBLE,double,float32_t); + + arm_svm_linear_predict_f32(self->instance,input,&result); + /* + printf("Dual\n"); + for(int i = 0 ; i < self->instance->nbOfSupportVectors ; i++) + { + printf("%f\n",self->instance->dualCoefficients[i]); + } + printf("Vectors\n"); + int k=0; + for(int i = 0 ; i < self->instance->nbOfSupportVectors ; i++) + { + printf("Vector %d\n",i); + for(int j = 0 ; j < self->instance->vectorDimension ; j++) + { + printf("%f\n",self->instance->supportVectors[k]); + k++; + } + } + printf("Classes\n"); + for(int i = 0 ; i < 2 ; i++) + { + printf("%d\n",self->instance->classes[i]); + } + printf("Intercept %f\n",self->instance->intercept); +*/ + PyMem_Free(input); + return(Py_BuildValue("i",result)); + } + } + return(Py_BuildValue("i",-1)); +} +#endif + +#ifdef IS_PY3K +static int cmsisml_traverse(PyObject *m, visitproc visit, void *arg) { + Py_VISIT(GETSTATE(m)->error); + return 0; +} + +static int cmsisml_clear(PyObject *m) { + Py_CLEAR(GETSTATE(m)->error); + return 0; +} + + +static struct PyModuleDef moduledef = { + PyModuleDef_HEAD_INIT, + MODNAME, + NULL, + sizeof(struct module_state), + CMSISMLMethods, + NULL, + cmsisml_traverse, + cmsisml_clear, + NULL +}; + +#define INITERROR return NULL + +PyMODINIT_FUNC +CAT(PyInit_,MODINITNAME)(void) + + +#else +#define INITERROR return + +void CAT(init,MODINITNAME)(void) +#endif +{ + import_array(); + + #ifdef IS_PY3K + PyObject *module = PyModule_Create(&moduledef); + #else + PyObject *module = Py_InitModule(MODNAME, CMSISMLMethods); + #endif + + if (module == NULL) + INITERROR; + struct module_state *st = GETSTATE(module); + + st->error = PyErr_NewException(MODNAME".Error", NULL, NULL); + if (st->error == NULL) { + Py_DECREF(module); + INITERROR; + } + + + typeRegistration(module); + + #ifdef IS_PY3K + return module; + #endif +} \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/cmsismodule.h b/Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/cmsismodule.h new file mode 100644 index 0000000..c7c7943 --- /dev/null +++ b/Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/cmsismodule.h @@ -0,0 +1,15360 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Python Wrapper + * Title: cmsismodule.h + * Description: Automatically generated C code for the CMSIS-DSP Python wrapper + * + * $Date: 25. March 2019 + * $Revision: V0.0.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +typedef struct { + PyObject_HEAD + arm_fir_instance_q7 *instance; +} ml_arm_fir_instance_q7Object; + + +static void +arm_fir_instance_q7_dealloc(ml_arm_fir_instance_q7Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_instance_q7_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_instance_q7Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_instance_q7Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_instance_q7)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_instance_q7_init(ml_arm_fir_instance_q7Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numTaps",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|h", kwlist,&self->instance->numTaps +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_instance_q7,numTaps,"h"); + + +static PyMethodDef arm_fir_instance_q7_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_fir_instance_q7_numTaps,METH_NOARGS,"numTaps"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_instance_q7,arm_fir_instance_q7_new,arm_fir_instance_q7_dealloc,arm_fir_instance_q7_init,arm_fir_instance_q7_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_instance_q15 *instance; +} ml_arm_fir_instance_q15Object; + + +static void +arm_fir_instance_q15_dealloc(ml_arm_fir_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_instance_q15)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_instance_q15_init(ml_arm_fir_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numTaps",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|h", kwlist,&self->instance->numTaps +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_instance_q15,numTaps,"h"); + + +static PyMethodDef arm_fir_instance_q15_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_fir_instance_q15_numTaps,METH_NOARGS,"numTaps"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_instance_q15,arm_fir_instance_q15_new,arm_fir_instance_q15_dealloc,arm_fir_instance_q15_init,arm_fir_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_instance_q31 *instance; +} ml_arm_fir_instance_q31Object; + + +static void +arm_fir_instance_q31_dealloc(ml_arm_fir_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_instance_q31)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_instance_q31_init(ml_arm_fir_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numTaps",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|h", kwlist,&self->instance->numTaps +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_instance_q31,numTaps,"h"); + + +static PyMethodDef arm_fir_instance_q31_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_fir_instance_q31_numTaps,METH_NOARGS,"numTaps"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_instance_q31,arm_fir_instance_q31_new,arm_fir_instance_q31_dealloc,arm_fir_instance_q31_init,arm_fir_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_instance_f32 *instance; +} ml_arm_fir_instance_f32Object; + + +static void +arm_fir_instance_f32_dealloc(ml_arm_fir_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_instance_f32)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_instance_f32_init(ml_arm_fir_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numTaps",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|h", kwlist,&self->instance->numTaps +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_instance_f32,numTaps,"h"); + + +static PyMethodDef arm_fir_instance_f32_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_fir_instance_f32_numTaps,METH_NOARGS,"numTaps"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_instance_f32,arm_fir_instance_f32_new,arm_fir_instance_f32_dealloc,arm_fir_instance_f32_init,arm_fir_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_biquad_casd_df1_inst_q15 *instance; +} ml_arm_biquad_casd_df1_inst_q15Object; + + +static void +arm_biquad_casd_df1_inst_q15_dealloc(ml_arm_biquad_casd_df1_inst_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_biquad_casd_df1_inst_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_biquad_casd_df1_inst_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_biquad_casd_df1_inst_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_biquad_casd_df1_inst_q15)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_biquad_casd_df1_inst_q15_init(ml_arm_biquad_casd_df1_inst_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numStages","postShift",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|ii", kwlist,&self->instance->numStages +,&self->instance->postShift +)) + { + + + } + return 0; +} + +GETFIELD(arm_biquad_casd_df1_inst_q15,numStages,"i"); +GETFIELD(arm_biquad_casd_df1_inst_q15,postShift,"i"); + + +static PyMethodDef arm_biquad_casd_df1_inst_q15_methods[] = { + + {"numStages", (PyCFunction) Method_arm_biquad_casd_df1_inst_q15_numStages,METH_NOARGS,"numStages"}, + {"postShift", (PyCFunction) Method_arm_biquad_casd_df1_inst_q15_postShift,METH_NOARGS,"postShift"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_biquad_casd_df1_inst_q15,arm_biquad_casd_df1_inst_q15_new,arm_biquad_casd_df1_inst_q15_dealloc,arm_biquad_casd_df1_inst_q15_init,arm_biquad_casd_df1_inst_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_biquad_casd_df1_inst_q31 *instance; +} ml_arm_biquad_casd_df1_inst_q31Object; + + +static void +arm_biquad_casd_df1_inst_q31_dealloc(ml_arm_biquad_casd_df1_inst_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_biquad_casd_df1_inst_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_biquad_casd_df1_inst_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_biquad_casd_df1_inst_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_biquad_casd_df1_inst_q31)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_biquad_casd_df1_inst_q31_init(ml_arm_biquad_casd_df1_inst_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numStages","postShift",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|ii", kwlist,&self->instance->numStages +,&self->instance->postShift +)) + { + + + } + return 0; +} + +GETFIELD(arm_biquad_casd_df1_inst_q31,numStages,"i"); +GETFIELD(arm_biquad_casd_df1_inst_q31,postShift,"i"); + + +static PyMethodDef arm_biquad_casd_df1_inst_q31_methods[] = { + + {"numStages", (PyCFunction) Method_arm_biquad_casd_df1_inst_q31_numStages,METH_NOARGS,"numStages"}, + {"postShift", (PyCFunction) Method_arm_biquad_casd_df1_inst_q31_postShift,METH_NOARGS,"postShift"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_biquad_casd_df1_inst_q31,arm_biquad_casd_df1_inst_q31_new,arm_biquad_casd_df1_inst_q31_dealloc,arm_biquad_casd_df1_inst_q31_init,arm_biquad_casd_df1_inst_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_biquad_casd_df1_inst_f32 *instance; +} ml_arm_biquad_casd_df1_inst_f32Object; + + +static void +arm_biquad_casd_df1_inst_f32_dealloc(ml_arm_biquad_casd_df1_inst_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_biquad_casd_df1_inst_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_biquad_casd_df1_inst_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_biquad_casd_df1_inst_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_biquad_casd_df1_inst_f32)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_biquad_casd_df1_inst_f32_init(ml_arm_biquad_casd_df1_inst_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numStages",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|i", kwlist,&self->instance->numStages +)) + { + + + } + return 0; +} + +GETFIELD(arm_biquad_casd_df1_inst_f32,numStages,"i"); + + +static PyMethodDef arm_biquad_casd_df1_inst_f32_methods[] = { + + {"numStages", (PyCFunction) Method_arm_biquad_casd_df1_inst_f32_numStages,METH_NOARGS,"numStages"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_biquad_casd_df1_inst_f32,arm_biquad_casd_df1_inst_f32_new,arm_biquad_casd_df1_inst_f32_dealloc,arm_biquad_casd_df1_inst_f32_init,arm_biquad_casd_df1_inst_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_matrix_instance_f32 *instance; +} ml_arm_matrix_instance_f32Object; + + +static void +arm_matrix_instance_f32_dealloc(ml_arm_matrix_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pData) + { + PyMem_Free(self->instance->pData); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_matrix_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_matrix_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_matrix_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_matrix_instance_f32)); + + self->instance->pData = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_matrix_instance_f32_init(ml_arm_matrix_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pData=NULL; +char *kwlist[] = { +"numRows","numCols","pData",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhO", kwlist,&self->instance->numRows +,&self->instance->numCols +,&pData +)) + { + + INITARRAYFIELD(pData,NPY_DOUBLE,double,float32_t); + + } + return 0; +} + +GETFIELD(arm_matrix_instance_f32,numRows,"h"); +GETFIELD(arm_matrix_instance_f32,numCols,"h"); + + +static PyMethodDef arm_matrix_instance_f32_methods[] = { + + {"numRows", (PyCFunction) Method_arm_matrix_instance_f32_numRows,METH_NOARGS,"numRows"}, + {"numCols", (PyCFunction) Method_arm_matrix_instance_f32_numCols,METH_NOARGS,"numCols"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_matrix_instance_f32,arm_matrix_instance_f32_new,arm_matrix_instance_f32_dealloc,arm_matrix_instance_f32_init,arm_matrix_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_matrix_instance_f64 *instance; +} ml_arm_matrix_instance_f64Object; + + +static void +arm_matrix_instance_f64_dealloc(ml_arm_matrix_instance_f64Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pData) + { + PyMem_Free(self->instance->pData); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_matrix_instance_f64_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_matrix_instance_f64Object *self; + //printf("New called\n"); + + self = (ml_arm_matrix_instance_f64Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_matrix_instance_f64)); + + self->instance->pData = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_matrix_instance_f64_init(ml_arm_matrix_instance_f64Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pData=NULL; +char *kwlist[] = { +"numRows","numCols","pData",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhO", kwlist,&self->instance->numRows +,&self->instance->numCols +,&pData +)) + { + + INITARRAYFIELD(pData,NPY_FLOAT64,float64_t,float64_t); + + } + return 0; +} + +GETFIELD(arm_matrix_instance_f64,numRows,"h"); +GETFIELD(arm_matrix_instance_f64,numCols,"h"); + + +static PyMethodDef arm_matrix_instance_f64_methods[] = { + + {"numRows", (PyCFunction) Method_arm_matrix_instance_f64_numRows,METH_NOARGS,"numRows"}, + {"numCols", (PyCFunction) Method_arm_matrix_instance_f64_numCols,METH_NOARGS,"numCols"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_matrix_instance_f64,arm_matrix_instance_f64_new,arm_matrix_instance_f64_dealloc,arm_matrix_instance_f64_init,arm_matrix_instance_f64_methods); + + +typedef struct { + PyObject_HEAD + arm_matrix_instance_q15 *instance; +} ml_arm_matrix_instance_q15Object; + + +static void +arm_matrix_instance_q15_dealloc(ml_arm_matrix_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pData) + { + PyMem_Free(self->instance->pData); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_matrix_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_matrix_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_matrix_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_matrix_instance_q15)); + + self->instance->pData = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_matrix_instance_q15_init(ml_arm_matrix_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pData=NULL; +char *kwlist[] = { +"numRows","numCols","pData",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhO", kwlist,&self->instance->numRows +,&self->instance->numCols +,&pData +)) + { + + INITARRAYFIELD(pData,NPY_INT16,int16_t,int16_t); + + } + return 0; +} + +GETFIELD(arm_matrix_instance_q15,numRows,"h"); +GETFIELD(arm_matrix_instance_q15,numCols,"h"); + + +static PyMethodDef arm_matrix_instance_q15_methods[] = { + + {"numRows", (PyCFunction) Method_arm_matrix_instance_q15_numRows,METH_NOARGS,"numRows"}, + {"numCols", (PyCFunction) Method_arm_matrix_instance_q15_numCols,METH_NOARGS,"numCols"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_matrix_instance_q15,arm_matrix_instance_q15_new,arm_matrix_instance_q15_dealloc,arm_matrix_instance_q15_init,arm_matrix_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_matrix_instance_q31 *instance; +} ml_arm_matrix_instance_q31Object; + + +static void +arm_matrix_instance_q31_dealloc(ml_arm_matrix_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pData) + { + PyMem_Free(self->instance->pData); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_matrix_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_matrix_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_matrix_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_matrix_instance_q31)); + + self->instance->pData = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_matrix_instance_q31_init(ml_arm_matrix_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pData=NULL; +char *kwlist[] = { +"numRows","numCols","pData",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhO", kwlist,&self->instance->numRows +,&self->instance->numCols +,&pData +)) + { + + INITARRAYFIELD(pData,NPY_INT32,int32_t,int32_t); + + } + return 0; +} + +GETFIELD(arm_matrix_instance_q31,numRows,"h"); +GETFIELD(arm_matrix_instance_q31,numCols,"h"); + + +static PyMethodDef arm_matrix_instance_q31_methods[] = { + + {"numRows", (PyCFunction) Method_arm_matrix_instance_q31_numRows,METH_NOARGS,"numRows"}, + {"numCols", (PyCFunction) Method_arm_matrix_instance_q31_numCols,METH_NOARGS,"numCols"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_matrix_instance_q31,arm_matrix_instance_q31_new,arm_matrix_instance_q31_dealloc,arm_matrix_instance_q31_init,arm_matrix_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_pid_instance_q15 *instance; +} ml_arm_pid_instance_q15Object; + + +static void +arm_pid_instance_q15_dealloc(ml_arm_pid_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_pid_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_pid_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_pid_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_pid_instance_q15)); + + + } + + + return (PyObject *)self; +} + +static int +arm_pid_instance_q15_init(ml_arm_pid_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + +char *kwlist[] = { +"A0","A1","A2","state","Kp","Ki","Kd",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhhhhhh", kwlist,&self->instance->A0 +,&self->instance->A1 +,&self->instance->A2 +,&self->instance->state +,&self->instance->Kp +,&self->instance->Ki +,&self->instance->Kd +)) + { + + + } + return 0; +} + +GETFIELD(arm_pid_instance_q15,A0,"h"); +GETFIELD(arm_pid_instance_q15,A1,"h"); +GETFIELD(arm_pid_instance_q15,A2,"h"); +GETFIELD(arm_pid_instance_q15,state,"h"); +GETFIELD(arm_pid_instance_q15,Kp,"h"); +GETFIELD(arm_pid_instance_q15,Ki,"h"); +GETFIELD(arm_pid_instance_q15,Kd,"h"); + + +static PyMethodDef arm_pid_instance_q15_methods[] = { + + {"A0", (PyCFunction) Method_arm_pid_instance_q15_A0,METH_NOARGS,"A0"}, + {"A1", (PyCFunction) Method_arm_pid_instance_q15_A1,METH_NOARGS,"A1"}, + {"A2", (PyCFunction) Method_arm_pid_instance_q15_A2,METH_NOARGS,"A2"}, + {"state", (PyCFunction) Method_arm_pid_instance_q15_state,METH_NOARGS,"state"}, + {"Kp", (PyCFunction) Method_arm_pid_instance_q15_Kp,METH_NOARGS,"Kp"}, + {"Ki", (PyCFunction) Method_arm_pid_instance_q15_Ki,METH_NOARGS,"Ki"}, + {"Kd", (PyCFunction) Method_arm_pid_instance_q15_Kd,METH_NOARGS,"Kd"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_pid_instance_q15,arm_pid_instance_q15_new,arm_pid_instance_q15_dealloc,arm_pid_instance_q15_init,arm_pid_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_pid_instance_q31 *instance; +} ml_arm_pid_instance_q31Object; + + +static void +arm_pid_instance_q31_dealloc(ml_arm_pid_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_pid_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_pid_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_pid_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_pid_instance_q31)); + + + } + + + return (PyObject *)self; +} + +static int +arm_pid_instance_q31_init(ml_arm_pid_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + +char *kwlist[] = { +"A0","A1","A2","state","Kp","Ki","Kd",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|iiiiiii", kwlist,&self->instance->A0 +,&self->instance->A1 +,&self->instance->A2 +,&self->instance->state +,&self->instance->Kp +,&self->instance->Ki +,&self->instance->Kd +)) + { + + + } + return 0; +} + +GETFIELD(arm_pid_instance_q31,A0,"i"); +GETFIELD(arm_pid_instance_q31,A1,"i"); +GETFIELD(arm_pid_instance_q31,A2,"i"); +GETFIELD(arm_pid_instance_q31,state,"i"); +GETFIELD(arm_pid_instance_q31,Kp,"i"); +GETFIELD(arm_pid_instance_q31,Ki,"i"); +GETFIELD(arm_pid_instance_q31,Kd,"i"); + + +static PyMethodDef arm_pid_instance_q31_methods[] = { + + {"A0", (PyCFunction) Method_arm_pid_instance_q31_A0,METH_NOARGS,"A0"}, + {"A1", (PyCFunction) Method_arm_pid_instance_q31_A1,METH_NOARGS,"A1"}, + {"A2", (PyCFunction) Method_arm_pid_instance_q31_A2,METH_NOARGS,"A2"}, + {"state", (PyCFunction) Method_arm_pid_instance_q31_state,METH_NOARGS,"state"}, + {"Kp", (PyCFunction) Method_arm_pid_instance_q31_Kp,METH_NOARGS,"Kp"}, + {"Ki", (PyCFunction) Method_arm_pid_instance_q31_Ki,METH_NOARGS,"Ki"}, + {"Kd", (PyCFunction) Method_arm_pid_instance_q31_Kd,METH_NOARGS,"Kd"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_pid_instance_q31,arm_pid_instance_q31_new,arm_pid_instance_q31_dealloc,arm_pid_instance_q31_init,arm_pid_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_pid_instance_f32 *instance; +} ml_arm_pid_instance_f32Object; + + +static void +arm_pid_instance_f32_dealloc(ml_arm_pid_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_pid_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_pid_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_pid_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_pid_instance_f32)); + + + } + + + return (PyObject *)self; +} + +static int +arm_pid_instance_f32_init(ml_arm_pid_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + +char *kwlist[] = { +"A0","A1","A2","state","Kp","Ki","Kd",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|fffffff", kwlist,&self->instance->A0 +,&self->instance->A1 +,&self->instance->A2 +,&self->instance->state +,&self->instance->Kp +,&self->instance->Ki +,&self->instance->Kd +)) + { + + + } + return 0; +} + +GETFIELD(arm_pid_instance_f32,A0,"f"); +GETFIELD(arm_pid_instance_f32,A1,"f"); +GETFIELD(arm_pid_instance_f32,A2,"f"); +GETFIELD(arm_pid_instance_f32,state,"f"); +GETFIELD(arm_pid_instance_f32,Kp,"f"); +GETFIELD(arm_pid_instance_f32,Ki,"f"); +GETFIELD(arm_pid_instance_f32,Kd,"f"); + + +static PyMethodDef arm_pid_instance_f32_methods[] = { + + {"A0", (PyCFunction) Method_arm_pid_instance_f32_A0,METH_NOARGS,"A0"}, + {"A1", (PyCFunction) Method_arm_pid_instance_f32_A1,METH_NOARGS,"A1"}, + {"A2", (PyCFunction) Method_arm_pid_instance_f32_A2,METH_NOARGS,"A2"}, + {"state", (PyCFunction) Method_arm_pid_instance_f32_state,METH_NOARGS,"state"}, + {"Kp", (PyCFunction) Method_arm_pid_instance_f32_Kp,METH_NOARGS,"Kp"}, + {"Ki", (PyCFunction) Method_arm_pid_instance_f32_Ki,METH_NOARGS,"Ki"}, + {"Kd", (PyCFunction) Method_arm_pid_instance_f32_Kd,METH_NOARGS,"Kd"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_pid_instance_f32,arm_pid_instance_f32_new,arm_pid_instance_f32_dealloc,arm_pid_instance_f32_init,arm_pid_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_linear_interp_instance_f32 *instance; +} ml_arm_linear_interp_instance_f32Object; + + +static void +arm_linear_interp_instance_f32_dealloc(ml_arm_linear_interp_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pYData) + { + PyMem_Free(self->instance->pYData); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_linear_interp_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_linear_interp_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_linear_interp_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_linear_interp_instance_f32)); + + self->instance->pYData = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_linear_interp_instance_f32_init(ml_arm_linear_interp_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pYData=NULL; +char *kwlist[] = { +"nValues","x1","xSpacing","pYData",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|iffO", kwlist,&self->instance->nValues +,&self->instance->x1 +,&self->instance->xSpacing +,&pYData +)) + { + + INITARRAYFIELD(pYData,NPY_DOUBLE,double,float32_t); + + } + return 0; +} + +GETFIELD(arm_linear_interp_instance_f32,nValues,"i"); +GETFIELD(arm_linear_interp_instance_f32,x1,"f"); +GETFIELD(arm_linear_interp_instance_f32,xSpacing,"f"); + + +static PyMethodDef arm_linear_interp_instance_f32_methods[] = { + + {"nValues", (PyCFunction) Method_arm_linear_interp_instance_f32_nValues,METH_NOARGS,"nValues"}, + {"x1", (PyCFunction) Method_arm_linear_interp_instance_f32_x1,METH_NOARGS,"x1"}, + {"xSpacing", (PyCFunction) Method_arm_linear_interp_instance_f32_xSpacing,METH_NOARGS,"xSpacing"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_linear_interp_instance_f32,arm_linear_interp_instance_f32_new,arm_linear_interp_instance_f32_dealloc,arm_linear_interp_instance_f32_init,arm_linear_interp_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_bilinear_interp_instance_f32 *instance; +} ml_arm_bilinear_interp_instance_f32Object; + + +static void +arm_bilinear_interp_instance_f32_dealloc(ml_arm_bilinear_interp_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pData) + { + PyMem_Free(self->instance->pData); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_bilinear_interp_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_bilinear_interp_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_bilinear_interp_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_bilinear_interp_instance_f32)); + + self->instance->pData = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_bilinear_interp_instance_f32_init(ml_arm_bilinear_interp_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pData=NULL; +char *kwlist[] = { +"numRows","numCols","pData",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhO", kwlist,&self->instance->numRows +,&self->instance->numCols +,&pData +)) + { + + INITARRAYFIELD(pData,NPY_DOUBLE,double,float32_t); + + } + return 0; +} + +GETFIELD(arm_bilinear_interp_instance_f32,numRows,"h"); +GETFIELD(arm_bilinear_interp_instance_f32,numCols,"h"); + + +static PyMethodDef arm_bilinear_interp_instance_f32_methods[] = { + + {"numRows", (PyCFunction) Method_arm_bilinear_interp_instance_f32_numRows,METH_NOARGS,"numRows"}, + {"numCols", (PyCFunction) Method_arm_bilinear_interp_instance_f32_numCols,METH_NOARGS,"numCols"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_bilinear_interp_instance_f32,arm_bilinear_interp_instance_f32_new,arm_bilinear_interp_instance_f32_dealloc,arm_bilinear_interp_instance_f32_init,arm_bilinear_interp_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_bilinear_interp_instance_q31 *instance; +} ml_arm_bilinear_interp_instance_q31Object; + + +static void +arm_bilinear_interp_instance_q31_dealloc(ml_arm_bilinear_interp_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pData) + { + PyMem_Free(self->instance->pData); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_bilinear_interp_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_bilinear_interp_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_bilinear_interp_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_bilinear_interp_instance_q31)); + + self->instance->pData = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_bilinear_interp_instance_q31_init(ml_arm_bilinear_interp_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pData=NULL; +char *kwlist[] = { +"numRows","numCols","pData",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhO", kwlist,&self->instance->numRows +,&self->instance->numCols +,&pData +)) + { + + INITARRAYFIELD(pData,NPY_INT32,int32_t,int32_t); + + } + return 0; +} + +GETFIELD(arm_bilinear_interp_instance_q31,numRows,"h"); +GETFIELD(arm_bilinear_interp_instance_q31,numCols,"h"); + + +static PyMethodDef arm_bilinear_interp_instance_q31_methods[] = { + + {"numRows", (PyCFunction) Method_arm_bilinear_interp_instance_q31_numRows,METH_NOARGS,"numRows"}, + {"numCols", (PyCFunction) Method_arm_bilinear_interp_instance_q31_numCols,METH_NOARGS,"numCols"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_bilinear_interp_instance_q31,arm_bilinear_interp_instance_q31_new,arm_bilinear_interp_instance_q31_dealloc,arm_bilinear_interp_instance_q31_init,arm_bilinear_interp_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_bilinear_interp_instance_q15 *instance; +} ml_arm_bilinear_interp_instance_q15Object; + + +static void +arm_bilinear_interp_instance_q15_dealloc(ml_arm_bilinear_interp_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pData) + { + PyMem_Free(self->instance->pData); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_bilinear_interp_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_bilinear_interp_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_bilinear_interp_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_bilinear_interp_instance_q15)); + + self->instance->pData = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_bilinear_interp_instance_q15_init(ml_arm_bilinear_interp_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pData=NULL; +char *kwlist[] = { +"numRows","numCols","pData",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhO", kwlist,&self->instance->numRows +,&self->instance->numCols +,&pData +)) + { + + INITARRAYFIELD(pData,NPY_INT16,int16_t,int16_t); + + } + return 0; +} + +GETFIELD(arm_bilinear_interp_instance_q15,numRows,"h"); +GETFIELD(arm_bilinear_interp_instance_q15,numCols,"h"); + + +static PyMethodDef arm_bilinear_interp_instance_q15_methods[] = { + + {"numRows", (PyCFunction) Method_arm_bilinear_interp_instance_q15_numRows,METH_NOARGS,"numRows"}, + {"numCols", (PyCFunction) Method_arm_bilinear_interp_instance_q15_numCols,METH_NOARGS,"numCols"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_bilinear_interp_instance_q15,arm_bilinear_interp_instance_q15_new,arm_bilinear_interp_instance_q15_dealloc,arm_bilinear_interp_instance_q15_init,arm_bilinear_interp_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_bilinear_interp_instance_q7 *instance; +} ml_arm_bilinear_interp_instance_q7Object; + + +static void +arm_bilinear_interp_instance_q7_dealloc(ml_arm_bilinear_interp_instance_q7Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pData) + { + PyMem_Free(self->instance->pData); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_bilinear_interp_instance_q7_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_bilinear_interp_instance_q7Object *self; + //printf("New called\n"); + + self = (ml_arm_bilinear_interp_instance_q7Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_bilinear_interp_instance_q7)); + + self->instance->pData = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_bilinear_interp_instance_q7_init(ml_arm_bilinear_interp_instance_q7Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pData=NULL; +char *kwlist[] = { +"numRows","numCols","pData",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhO", kwlist,&self->instance->numRows +,&self->instance->numCols +,&pData +)) + { + + INITARRAYFIELD(pData,NPY_BYTE,int8_t,q7_t); + + } + return 0; +} + +GETFIELD(arm_bilinear_interp_instance_q7,numRows,"h"); +GETFIELD(arm_bilinear_interp_instance_q7,numCols,"h"); + + +static PyMethodDef arm_bilinear_interp_instance_q7_methods[] = { + + {"numRows", (PyCFunction) Method_arm_bilinear_interp_instance_q7_numRows,METH_NOARGS,"numRows"}, + {"numCols", (PyCFunction) Method_arm_bilinear_interp_instance_q7_numCols,METH_NOARGS,"numCols"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_bilinear_interp_instance_q7,arm_bilinear_interp_instance_q7_new,arm_bilinear_interp_instance_q7_dealloc,arm_bilinear_interp_instance_q7_init,arm_bilinear_interp_instance_q7_methods); + + +typedef struct { + PyObject_HEAD + arm_cfft_radix2_instance_q15 *instance; +} ml_arm_cfft_radix2_instance_q15Object; + + +static void +arm_cfft_radix2_instance_q15_dealloc(ml_arm_cfft_radix2_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_cfft_radix2_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_cfft_radix2_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_cfft_radix2_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_cfft_radix2_instance_q15)); + + self->instance->pTwiddle = NULL; + self->instance->pBitRevTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_cfft_radix2_instance_q15_init(ml_arm_cfft_radix2_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pBitRevTable=NULL; +char *kwlist[] = { +"fftLen","ifftFlag","bitReverseFlag","twidCoefModifier","bitRevFactor",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hiihh", kwlist,&self->instance->fftLen +,&self->instance->ifftFlag +,&self->instance->bitReverseFlag +,&self->instance->twidCoefModifier +,&self->instance->bitRevFactor +)) + { + + + } + return 0; +} + +GETFIELD(arm_cfft_radix2_instance_q15,fftLen,"h"); +GETFIELD(arm_cfft_radix2_instance_q15,ifftFlag,"i"); +GETFIELD(arm_cfft_radix2_instance_q15,bitReverseFlag,"i"); +GETFIELD(arm_cfft_radix2_instance_q15,twidCoefModifier,"h"); +GETFIELD(arm_cfft_radix2_instance_q15,bitRevFactor,"h"); + + +static PyMethodDef arm_cfft_radix2_instance_q15_methods[] = { + + {"fftLen", (PyCFunction) Method_arm_cfft_radix2_instance_q15_fftLen,METH_NOARGS,"fftLen"}, + {"ifftFlag", (PyCFunction) Method_arm_cfft_radix2_instance_q15_ifftFlag,METH_NOARGS,"ifftFlag"}, + {"bitReverseFlag", (PyCFunction) Method_arm_cfft_radix2_instance_q15_bitReverseFlag,METH_NOARGS,"bitReverseFlag"}, + {"twidCoefModifier", (PyCFunction) Method_arm_cfft_radix2_instance_q15_twidCoefModifier,METH_NOARGS,"twidCoefModifier"}, + {"bitRevFactor", (PyCFunction) Method_arm_cfft_radix2_instance_q15_bitRevFactor,METH_NOARGS,"bitRevFactor"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_cfft_radix2_instance_q15,arm_cfft_radix2_instance_q15_new,arm_cfft_radix2_instance_q15_dealloc,arm_cfft_radix2_instance_q15_init,arm_cfft_radix2_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_cfft_radix4_instance_q15 *instance; +} ml_arm_cfft_radix4_instance_q15Object; + + +static void +arm_cfft_radix4_instance_q15_dealloc(ml_arm_cfft_radix4_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_cfft_radix4_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_cfft_radix4_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_cfft_radix4_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_cfft_radix4_instance_q15)); + + self->instance->pTwiddle = NULL; + self->instance->pBitRevTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_cfft_radix4_instance_q15_init(ml_arm_cfft_radix4_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pBitRevTable=NULL; +char *kwlist[] = { +"fftLen","ifftFlag","bitReverseFlag","twidCoefModifier","bitRevFactor",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hiihh", kwlist,&self->instance->fftLen +,&self->instance->ifftFlag +,&self->instance->bitReverseFlag +,&self->instance->twidCoefModifier +,&self->instance->bitRevFactor +)) + { + + + } + return 0; +} + +GETFIELD(arm_cfft_radix4_instance_q15,fftLen,"h"); +GETFIELD(arm_cfft_radix4_instance_q15,ifftFlag,"i"); +GETFIELD(arm_cfft_radix4_instance_q15,bitReverseFlag,"i"); +GETFIELD(arm_cfft_radix4_instance_q15,twidCoefModifier,"h"); +GETFIELD(arm_cfft_radix4_instance_q15,bitRevFactor,"h"); + + +static PyMethodDef arm_cfft_radix4_instance_q15_methods[] = { + + {"fftLen", (PyCFunction) Method_arm_cfft_radix4_instance_q15_fftLen,METH_NOARGS,"fftLen"}, + {"ifftFlag", (PyCFunction) Method_arm_cfft_radix4_instance_q15_ifftFlag,METH_NOARGS,"ifftFlag"}, + {"bitReverseFlag", (PyCFunction) Method_arm_cfft_radix4_instance_q15_bitReverseFlag,METH_NOARGS,"bitReverseFlag"}, + {"twidCoefModifier", (PyCFunction) Method_arm_cfft_radix4_instance_q15_twidCoefModifier,METH_NOARGS,"twidCoefModifier"}, + {"bitRevFactor", (PyCFunction) Method_arm_cfft_radix4_instance_q15_bitRevFactor,METH_NOARGS,"bitRevFactor"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_cfft_radix4_instance_q15,arm_cfft_radix4_instance_q15_new,arm_cfft_radix4_instance_q15_dealloc,arm_cfft_radix4_instance_q15_init,arm_cfft_radix4_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_cfft_radix2_instance_q31 *instance; +} ml_arm_cfft_radix2_instance_q31Object; + + +static void +arm_cfft_radix2_instance_q31_dealloc(ml_arm_cfft_radix2_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_cfft_radix2_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_cfft_radix2_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_cfft_radix2_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_cfft_radix2_instance_q31)); + + self->instance->pTwiddle = NULL; + self->instance->pBitRevTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_cfft_radix2_instance_q31_init(ml_arm_cfft_radix2_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pBitRevTable=NULL; +char *kwlist[] = { +"fftLen","ifftFlag","bitReverseFlag","twidCoefModifier","bitRevFactor",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hiihh", kwlist,&self->instance->fftLen +,&self->instance->ifftFlag +,&self->instance->bitReverseFlag +,&self->instance->twidCoefModifier +,&self->instance->bitRevFactor +)) + { + + + } + return 0; +} + +GETFIELD(arm_cfft_radix2_instance_q31,fftLen,"h"); +GETFIELD(arm_cfft_radix2_instance_q31,ifftFlag,"i"); +GETFIELD(arm_cfft_radix2_instance_q31,bitReverseFlag,"i"); +GETFIELD(arm_cfft_radix2_instance_q31,twidCoefModifier,"h"); +GETFIELD(arm_cfft_radix2_instance_q31,bitRevFactor,"h"); + + +static PyMethodDef arm_cfft_radix2_instance_q31_methods[] = { + + {"fftLen", (PyCFunction) Method_arm_cfft_radix2_instance_q31_fftLen,METH_NOARGS,"fftLen"}, + {"ifftFlag", (PyCFunction) Method_arm_cfft_radix2_instance_q31_ifftFlag,METH_NOARGS,"ifftFlag"}, + {"bitReverseFlag", (PyCFunction) Method_arm_cfft_radix2_instance_q31_bitReverseFlag,METH_NOARGS,"bitReverseFlag"}, + {"twidCoefModifier", (PyCFunction) Method_arm_cfft_radix2_instance_q31_twidCoefModifier,METH_NOARGS,"twidCoefModifier"}, + {"bitRevFactor", (PyCFunction) Method_arm_cfft_radix2_instance_q31_bitRevFactor,METH_NOARGS,"bitRevFactor"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_cfft_radix2_instance_q31,arm_cfft_radix2_instance_q31_new,arm_cfft_radix2_instance_q31_dealloc,arm_cfft_radix2_instance_q31_init,arm_cfft_radix2_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_cfft_radix4_instance_q31 *instance; +} ml_arm_cfft_radix4_instance_q31Object; + + +static void +arm_cfft_radix4_instance_q31_dealloc(ml_arm_cfft_radix4_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_cfft_radix4_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_cfft_radix4_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_cfft_radix4_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_cfft_radix4_instance_q31)); + + self->instance->pTwiddle = NULL; + self->instance->pBitRevTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_cfft_radix4_instance_q31_init(ml_arm_cfft_radix4_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pBitRevTable=NULL; +char *kwlist[] = { +"fftLen","ifftFlag","bitReverseFlag","twidCoefModifier","bitRevFactor",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hiihh", kwlist,&self->instance->fftLen +,&self->instance->ifftFlag +,&self->instance->bitReverseFlag +,&self->instance->twidCoefModifier +,&self->instance->bitRevFactor +)) + { + + + } + return 0; +} + +GETFIELD(arm_cfft_radix4_instance_q31,fftLen,"h"); +GETFIELD(arm_cfft_radix4_instance_q31,ifftFlag,"i"); +GETFIELD(arm_cfft_radix4_instance_q31,bitReverseFlag,"i"); +GETFIELD(arm_cfft_radix4_instance_q31,twidCoefModifier,"h"); +GETFIELD(arm_cfft_radix4_instance_q31,bitRevFactor,"h"); + + +static PyMethodDef arm_cfft_radix4_instance_q31_methods[] = { + + {"fftLen", (PyCFunction) Method_arm_cfft_radix4_instance_q31_fftLen,METH_NOARGS,"fftLen"}, + {"ifftFlag", (PyCFunction) Method_arm_cfft_radix4_instance_q31_ifftFlag,METH_NOARGS,"ifftFlag"}, + {"bitReverseFlag", (PyCFunction) Method_arm_cfft_radix4_instance_q31_bitReverseFlag,METH_NOARGS,"bitReverseFlag"}, + {"twidCoefModifier", (PyCFunction) Method_arm_cfft_radix4_instance_q31_twidCoefModifier,METH_NOARGS,"twidCoefModifier"}, + {"bitRevFactor", (PyCFunction) Method_arm_cfft_radix4_instance_q31_bitRevFactor,METH_NOARGS,"bitRevFactor"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_cfft_radix4_instance_q31,arm_cfft_radix4_instance_q31_new,arm_cfft_radix4_instance_q31_dealloc,arm_cfft_radix4_instance_q31_init,arm_cfft_radix4_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_cfft_radix2_instance_f32 *instance; +} ml_arm_cfft_radix2_instance_f32Object; + + +static void +arm_cfft_radix2_instance_f32_dealloc(ml_arm_cfft_radix2_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_cfft_radix2_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_cfft_radix2_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_cfft_radix2_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_cfft_radix2_instance_f32)); + + self->instance->pTwiddle = NULL; + self->instance->pBitRevTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_cfft_radix2_instance_f32_init(ml_arm_cfft_radix2_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pBitRevTable=NULL; +char *kwlist[] = { +"fftLen","ifftFlag","bitReverseFlag","twidCoefModifier","bitRevFactor","onebyfftLen",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hiihhf", kwlist,&self->instance->fftLen +,&self->instance->ifftFlag +,&self->instance->bitReverseFlag +,&self->instance->twidCoefModifier +,&self->instance->bitRevFactor +,&self->instance->onebyfftLen +)) + { + + + } + return 0; +} + +GETFIELD(arm_cfft_radix2_instance_f32,fftLen,"h"); +GETFIELD(arm_cfft_radix2_instance_f32,ifftFlag,"i"); +GETFIELD(arm_cfft_radix2_instance_f32,bitReverseFlag,"i"); +GETFIELD(arm_cfft_radix2_instance_f32,twidCoefModifier,"h"); +GETFIELD(arm_cfft_radix2_instance_f32,bitRevFactor,"h"); +GETFIELD(arm_cfft_radix2_instance_f32,onebyfftLen,"f"); + + +static PyMethodDef arm_cfft_radix2_instance_f32_methods[] = { + + {"fftLen", (PyCFunction) Method_arm_cfft_radix2_instance_f32_fftLen,METH_NOARGS,"fftLen"}, + {"ifftFlag", (PyCFunction) Method_arm_cfft_radix2_instance_f32_ifftFlag,METH_NOARGS,"ifftFlag"}, + {"bitReverseFlag", (PyCFunction) Method_arm_cfft_radix2_instance_f32_bitReverseFlag,METH_NOARGS,"bitReverseFlag"}, + {"twidCoefModifier", (PyCFunction) Method_arm_cfft_radix2_instance_f32_twidCoefModifier,METH_NOARGS,"twidCoefModifier"}, + {"bitRevFactor", (PyCFunction) Method_arm_cfft_radix2_instance_f32_bitRevFactor,METH_NOARGS,"bitRevFactor"}, + {"onebyfftLen", (PyCFunction) Method_arm_cfft_radix2_instance_f32_onebyfftLen,METH_NOARGS,"onebyfftLen"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_cfft_radix2_instance_f32,arm_cfft_radix2_instance_f32_new,arm_cfft_radix2_instance_f32_dealloc,arm_cfft_radix2_instance_f32_init,arm_cfft_radix2_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_cfft_radix4_instance_f32 *instance; +} ml_arm_cfft_radix4_instance_f32Object; + + +static void +arm_cfft_radix4_instance_f32_dealloc(ml_arm_cfft_radix4_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_cfft_radix4_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_cfft_radix4_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_cfft_radix4_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_cfft_radix4_instance_f32)); + + self->instance->pTwiddle = NULL; + self->instance->pBitRevTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_cfft_radix4_instance_f32_init(ml_arm_cfft_radix4_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pBitRevTable=NULL; +char *kwlist[] = { +"fftLen","ifftFlag","bitReverseFlag","twidCoefModifier","bitRevFactor","onebyfftLen",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hiihhf", kwlist,&self->instance->fftLen +,&self->instance->ifftFlag +,&self->instance->bitReverseFlag +,&self->instance->twidCoefModifier +,&self->instance->bitRevFactor +,&self->instance->onebyfftLen +)) + { + + + } + return 0; +} + +GETFIELD(arm_cfft_radix4_instance_f32,fftLen,"h"); +GETFIELD(arm_cfft_radix4_instance_f32,ifftFlag,"i"); +GETFIELD(arm_cfft_radix4_instance_f32,bitReverseFlag,"i"); +GETFIELD(arm_cfft_radix4_instance_f32,twidCoefModifier,"h"); +GETFIELD(arm_cfft_radix4_instance_f32,bitRevFactor,"h"); +GETFIELD(arm_cfft_radix4_instance_f32,onebyfftLen,"f"); + + +static PyMethodDef arm_cfft_radix4_instance_f32_methods[] = { + + {"fftLen", (PyCFunction) Method_arm_cfft_radix4_instance_f32_fftLen,METH_NOARGS,"fftLen"}, + {"ifftFlag", (PyCFunction) Method_arm_cfft_radix4_instance_f32_ifftFlag,METH_NOARGS,"ifftFlag"}, + {"bitReverseFlag", (PyCFunction) Method_arm_cfft_radix4_instance_f32_bitReverseFlag,METH_NOARGS,"bitReverseFlag"}, + {"twidCoefModifier", (PyCFunction) Method_arm_cfft_radix4_instance_f32_twidCoefModifier,METH_NOARGS,"twidCoefModifier"}, + {"bitRevFactor", (PyCFunction) Method_arm_cfft_radix4_instance_f32_bitRevFactor,METH_NOARGS,"bitRevFactor"}, + {"onebyfftLen", (PyCFunction) Method_arm_cfft_radix4_instance_f32_onebyfftLen,METH_NOARGS,"onebyfftLen"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_cfft_radix4_instance_f32,arm_cfft_radix4_instance_f32_new,arm_cfft_radix4_instance_f32_dealloc,arm_cfft_radix4_instance_f32_init,arm_cfft_radix4_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_cfft_instance_q15 *instance; +} ml_arm_cfft_instance_q15Object; + + +static void +arm_cfft_instance_q15_dealloc(ml_arm_cfft_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_cfft_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_cfft_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_cfft_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_cfft_instance_q15)); + + self->instance->pTwiddle = NULL; + self->instance->pBitRevTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_cfft_instance_q15_init(ml_arm_cfft_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pBitRevTable=NULL; +char *kwlist[] = { +"fftLen","bitRevLength",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hh", kwlist,&self->instance->fftLen +,&self->instance->bitRevLength +)) + { + + + } + return 0; +} + +GETFIELD(arm_cfft_instance_q15,fftLen,"h"); +GETFIELD(arm_cfft_instance_q15,bitRevLength,"h"); + + +static PyMethodDef arm_cfft_instance_q15_methods[] = { + + {"fftLen", (PyCFunction) Method_arm_cfft_instance_q15_fftLen,METH_NOARGS,"fftLen"}, + {"bitRevLength", (PyCFunction) Method_arm_cfft_instance_q15_bitRevLength,METH_NOARGS,"bitRevLength"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_cfft_instance_q15,arm_cfft_instance_q15_new,arm_cfft_instance_q15_dealloc,arm_cfft_instance_q15_init,arm_cfft_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_cfft_instance_q31 *instance; +} ml_arm_cfft_instance_q31Object; + + +static void +arm_cfft_instance_q31_dealloc(ml_arm_cfft_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_cfft_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_cfft_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_cfft_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_cfft_instance_q31)); + + self->instance->pTwiddle = NULL; + self->instance->pBitRevTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_cfft_instance_q31_init(ml_arm_cfft_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pBitRevTable=NULL; +char *kwlist[] = { +"fftLen","bitRevLength",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hh", kwlist,&self->instance->fftLen +,&self->instance->bitRevLength +)) + { + + + } + return 0; +} + +GETFIELD(arm_cfft_instance_q31,fftLen,"h"); +GETFIELD(arm_cfft_instance_q31,bitRevLength,"h"); + + +static PyMethodDef arm_cfft_instance_q31_methods[] = { + + {"fftLen", (PyCFunction) Method_arm_cfft_instance_q31_fftLen,METH_NOARGS,"fftLen"}, + {"bitRevLength", (PyCFunction) Method_arm_cfft_instance_q31_bitRevLength,METH_NOARGS,"bitRevLength"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_cfft_instance_q31,arm_cfft_instance_q31_new,arm_cfft_instance_q31_dealloc,arm_cfft_instance_q31_init,arm_cfft_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_cfft_instance_f32 *instance; +} ml_arm_cfft_instance_f32Object; + + +static void +arm_cfft_instance_f32_dealloc(ml_arm_cfft_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_cfft_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_cfft_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_cfft_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_cfft_instance_f32)); + + self->instance->pTwiddle = NULL; + self->instance->pBitRevTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_cfft_instance_f32_init(ml_arm_cfft_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pBitRevTable=NULL; +char *kwlist[] = { +"fftLen","bitRevLength",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hh", kwlist,&self->instance->fftLen +,&self->instance->bitRevLength +)) + { + + + } + return 0; +} + +GETFIELD(arm_cfft_instance_f32,fftLen,"h"); +GETFIELD(arm_cfft_instance_f32,bitRevLength,"h"); + + +static PyMethodDef arm_cfft_instance_f32_methods[] = { + + {"fftLen", (PyCFunction) Method_arm_cfft_instance_f32_fftLen,METH_NOARGS,"fftLen"}, + {"bitRevLength", (PyCFunction) Method_arm_cfft_instance_f32_bitRevLength,METH_NOARGS,"bitRevLength"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_cfft_instance_f32,arm_cfft_instance_f32_new,arm_cfft_instance_f32_dealloc,arm_cfft_instance_f32_init,arm_cfft_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_rfft_instance_q15 *instance; +} ml_arm_rfft_instance_q15Object; + + +static void +arm_rfft_instance_q15_dealloc(ml_arm_rfft_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_rfft_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_rfft_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_rfft_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_rfft_instance_q15)); + + self->instance->pTwiddleAReal = NULL; + self->instance->pTwiddleBReal = NULL; + self->instance->pCfft = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_rfft_instance_q15_init(ml_arm_rfft_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddleAReal=NULL; + PyObject *pTwiddleBReal=NULL; + PyObject *pCfft=NULL; +char *kwlist[] = { +"fftLenReal","ifftFlagR","bitReverseFlagR","twidCoefRModifier",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|iiii", kwlist,&self->instance->fftLenReal +,&self->instance->ifftFlagR +,&self->instance->bitReverseFlagR +,&self->instance->twidCoefRModifier +)) + { + + + } + return 0; +} + +GETFIELD(arm_rfft_instance_q15,fftLenReal,"i"); +GETFIELD(arm_rfft_instance_q15,ifftFlagR,"i"); +GETFIELD(arm_rfft_instance_q15,bitReverseFlagR,"i"); +GETFIELD(arm_rfft_instance_q15,twidCoefRModifier,"i"); + + +static PyMethodDef arm_rfft_instance_q15_methods[] = { + + {"fftLenReal", (PyCFunction) Method_arm_rfft_instance_q15_fftLenReal,METH_NOARGS,"fftLenReal"}, + {"ifftFlagR", (PyCFunction) Method_arm_rfft_instance_q15_ifftFlagR,METH_NOARGS,"ifftFlagR"}, + {"bitReverseFlagR", (PyCFunction) Method_arm_rfft_instance_q15_bitReverseFlagR,METH_NOARGS,"bitReverseFlagR"}, + {"twidCoefRModifier", (PyCFunction) Method_arm_rfft_instance_q15_twidCoefRModifier,METH_NOARGS,"twidCoefRModifier"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_rfft_instance_q15,arm_rfft_instance_q15_new,arm_rfft_instance_q15_dealloc,arm_rfft_instance_q15_init,arm_rfft_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_rfft_instance_q31 *instance; +} ml_arm_rfft_instance_q31Object; + + +static void +arm_rfft_instance_q31_dealloc(ml_arm_rfft_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_rfft_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_rfft_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_rfft_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_rfft_instance_q31)); + + self->instance->pTwiddleAReal = NULL; + self->instance->pTwiddleBReal = NULL; + self->instance->pCfft = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_rfft_instance_q31_init(ml_arm_rfft_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddleAReal=NULL; + PyObject *pTwiddleBReal=NULL; + PyObject *pCfft=NULL; +char *kwlist[] = { +"fftLenReal","ifftFlagR","bitReverseFlagR","twidCoefRModifier",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|iiii", kwlist,&self->instance->fftLenReal +,&self->instance->ifftFlagR +,&self->instance->bitReverseFlagR +,&self->instance->twidCoefRModifier +)) + { + + + } + return 0; +} + +GETFIELD(arm_rfft_instance_q31,fftLenReal,"i"); +GETFIELD(arm_rfft_instance_q31,ifftFlagR,"i"); +GETFIELD(arm_rfft_instance_q31,bitReverseFlagR,"i"); +GETFIELD(arm_rfft_instance_q31,twidCoefRModifier,"i"); + + +static PyMethodDef arm_rfft_instance_q31_methods[] = { + + {"fftLenReal", (PyCFunction) Method_arm_rfft_instance_q31_fftLenReal,METH_NOARGS,"fftLenReal"}, + {"ifftFlagR", (PyCFunction) Method_arm_rfft_instance_q31_ifftFlagR,METH_NOARGS,"ifftFlagR"}, + {"bitReverseFlagR", (PyCFunction) Method_arm_rfft_instance_q31_bitReverseFlagR,METH_NOARGS,"bitReverseFlagR"}, + {"twidCoefRModifier", (PyCFunction) Method_arm_rfft_instance_q31_twidCoefRModifier,METH_NOARGS,"twidCoefRModifier"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_rfft_instance_q31,arm_rfft_instance_q31_new,arm_rfft_instance_q31_dealloc,arm_rfft_instance_q31_init,arm_rfft_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_rfft_instance_f32 *instance; +} ml_arm_rfft_instance_f32Object; + + +static void +arm_rfft_instance_f32_dealloc(ml_arm_rfft_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_rfft_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_rfft_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_rfft_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_rfft_instance_f32)); + + self->instance->pTwiddleAReal = NULL; + self->instance->pTwiddleBReal = NULL; + self->instance->pCfft = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_rfft_instance_f32_init(ml_arm_rfft_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddleAReal=NULL; + PyObject *pTwiddleBReal=NULL; + PyObject *pCfft=NULL; +char *kwlist[] = { +"fftLenReal","fftLenBy2","ifftFlagR","bitReverseFlagR","twidCoefRModifier",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|ihiii", kwlist,&self->instance->fftLenReal +,&self->instance->fftLenBy2 +,&self->instance->ifftFlagR +,&self->instance->bitReverseFlagR +,&self->instance->twidCoefRModifier +)) + { + + + } + return 0; +} + +GETFIELD(arm_rfft_instance_f32,fftLenReal,"i"); +GETFIELD(arm_rfft_instance_f32,fftLenBy2,"h"); +GETFIELD(arm_rfft_instance_f32,ifftFlagR,"i"); +GETFIELD(arm_rfft_instance_f32,bitReverseFlagR,"i"); +GETFIELD(arm_rfft_instance_f32,twidCoefRModifier,"i"); + + +static PyMethodDef arm_rfft_instance_f32_methods[] = { + + {"fftLenReal", (PyCFunction) Method_arm_rfft_instance_f32_fftLenReal,METH_NOARGS,"fftLenReal"}, + {"fftLenBy2", (PyCFunction) Method_arm_rfft_instance_f32_fftLenBy2,METH_NOARGS,"fftLenBy2"}, + {"ifftFlagR", (PyCFunction) Method_arm_rfft_instance_f32_ifftFlagR,METH_NOARGS,"ifftFlagR"}, + {"bitReverseFlagR", (PyCFunction) Method_arm_rfft_instance_f32_bitReverseFlagR,METH_NOARGS,"bitReverseFlagR"}, + {"twidCoefRModifier", (PyCFunction) Method_arm_rfft_instance_f32_twidCoefRModifier,METH_NOARGS,"twidCoefRModifier"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_rfft_instance_f32,arm_rfft_instance_f32_new,arm_rfft_instance_f32_dealloc,arm_rfft_instance_f32_init,arm_rfft_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_rfft_fast_instance_f32 *instance; +} ml_arm_rfft_fast_instance_f32Object; + + +static void +arm_rfft_fast_instance_f32_dealloc(ml_arm_rfft_fast_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_rfft_fast_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_rfft_fast_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_rfft_fast_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_rfft_fast_instance_f32)); + + self->instance->pTwiddleRFFT = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_rfft_fast_instance_f32_init(ml_arm_rfft_fast_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddleRFFT=NULL; +char *kwlist[] = { +"Sint","fftLenRFFT",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|?h", kwlist,&self->instance->Sint +,&self->instance->fftLenRFFT +)) + { + + + } + return 0; +} + +GETFIELD(arm_rfft_fast_instance_f32,Sint,"?"); +GETFIELD(arm_rfft_fast_instance_f32,fftLenRFFT,"h"); + + +static PyMethodDef arm_rfft_fast_instance_f32_methods[] = { + + {"Sint", (PyCFunction) Method_arm_rfft_fast_instance_f32_Sint,METH_NOARGS,"Sint"}, + {"fftLenRFFT", (PyCFunction) Method_arm_rfft_fast_instance_f32_fftLenRFFT,METH_NOARGS,"fftLenRFFT"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_rfft_fast_instance_f32,arm_rfft_fast_instance_f32_new,arm_rfft_fast_instance_f32_dealloc,arm_rfft_fast_instance_f32_init,arm_rfft_fast_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_dct4_instance_f32 *instance; +} ml_arm_dct4_instance_f32Object; + + +static void +arm_dct4_instance_f32_dealloc(ml_arm_dct4_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_dct4_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_dct4_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_dct4_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_dct4_instance_f32)); + + self->instance->pTwiddle = NULL; + self->instance->pCosFactor = NULL; + self->instance->pRfft = NULL; + self->instance->pCfft = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_dct4_instance_f32_init(ml_arm_dct4_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pCosFactor=NULL; + PyObject *pRfft=NULL; + PyObject *pCfft=NULL; +char *kwlist[] = { +"N","Nby2","normalize",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhf", kwlist,&self->instance->N +,&self->instance->Nby2 +,&self->instance->normalize +)) + { + + + } + return 0; +} + +GETFIELD(arm_dct4_instance_f32,N,"h"); +GETFIELD(arm_dct4_instance_f32,Nby2,"h"); +GETFIELD(arm_dct4_instance_f32,normalize,"f"); + + +static PyMethodDef arm_dct4_instance_f32_methods[] = { + + {"N", (PyCFunction) Method_arm_dct4_instance_f32_N,METH_NOARGS,"N"}, + {"Nby2", (PyCFunction) Method_arm_dct4_instance_f32_Nby2,METH_NOARGS,"Nby2"}, + {"normalize", (PyCFunction) Method_arm_dct4_instance_f32_normalize,METH_NOARGS,"normalize"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_dct4_instance_f32,arm_dct4_instance_f32_new,arm_dct4_instance_f32_dealloc,arm_dct4_instance_f32_init,arm_dct4_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_dct4_instance_q31 *instance; +} ml_arm_dct4_instance_q31Object; + + +static void +arm_dct4_instance_q31_dealloc(ml_arm_dct4_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_dct4_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_dct4_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_dct4_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_dct4_instance_q31)); + + self->instance->pTwiddle = NULL; + self->instance->pCosFactor = NULL; + self->instance->pRfft = NULL; + self->instance->pCfft = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_dct4_instance_q31_init(ml_arm_dct4_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pCosFactor=NULL; + PyObject *pRfft=NULL; + PyObject *pCfft=NULL; +char *kwlist[] = { +"N","Nby2","normalize",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhi", kwlist,&self->instance->N +,&self->instance->Nby2 +,&self->instance->normalize +)) + { + + + } + return 0; +} + +GETFIELD(arm_dct4_instance_q31,N,"h"); +GETFIELD(arm_dct4_instance_q31,Nby2,"h"); +GETFIELD(arm_dct4_instance_q31,normalize,"i"); + + +static PyMethodDef arm_dct4_instance_q31_methods[] = { + + {"N", (PyCFunction) Method_arm_dct4_instance_q31_N,METH_NOARGS,"N"}, + {"Nby2", (PyCFunction) Method_arm_dct4_instance_q31_Nby2,METH_NOARGS,"Nby2"}, + {"normalize", (PyCFunction) Method_arm_dct4_instance_q31_normalize,METH_NOARGS,"normalize"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_dct4_instance_q31,arm_dct4_instance_q31_new,arm_dct4_instance_q31_dealloc,arm_dct4_instance_q31_init,arm_dct4_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_dct4_instance_q15 *instance; +} ml_arm_dct4_instance_q15Object; + + +static void +arm_dct4_instance_q15_dealloc(ml_arm_dct4_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_dct4_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_dct4_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_dct4_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_dct4_instance_q15)); + + self->instance->pTwiddle = NULL; + self->instance->pCosFactor = NULL; + self->instance->pRfft = NULL; + self->instance->pCfft = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_dct4_instance_q15_init(ml_arm_dct4_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pTwiddle=NULL; + PyObject *pCosFactor=NULL; + PyObject *pRfft=NULL; + PyObject *pCfft=NULL; +char *kwlist[] = { +"N","Nby2","normalize",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhh", kwlist,&self->instance->N +,&self->instance->Nby2 +,&self->instance->normalize +)) + { + + + } + return 0; +} + +GETFIELD(arm_dct4_instance_q15,N,"h"); +GETFIELD(arm_dct4_instance_q15,Nby2,"h"); +GETFIELD(arm_dct4_instance_q15,normalize,"h"); + + +static PyMethodDef arm_dct4_instance_q15_methods[] = { + + {"N", (PyCFunction) Method_arm_dct4_instance_q15_N,METH_NOARGS,"N"}, + {"Nby2", (PyCFunction) Method_arm_dct4_instance_q15_Nby2,METH_NOARGS,"Nby2"}, + {"normalize", (PyCFunction) Method_arm_dct4_instance_q15_normalize,METH_NOARGS,"normalize"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_dct4_instance_q15,arm_dct4_instance_q15_new,arm_dct4_instance_q15_dealloc,arm_dct4_instance_q15_init,arm_dct4_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_decimate_instance_q15 *instance; +} ml_arm_fir_decimate_instance_q15Object; + + +static void +arm_fir_decimate_instance_q15_dealloc(ml_arm_fir_decimate_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_decimate_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_decimate_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_decimate_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_decimate_instance_q15)); + + self->instance->pCoeffs = NULL; + self->instance->pState = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_decimate_instance_q15_init(ml_arm_fir_decimate_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pCoeffs=NULL; + PyObject *pState=NULL; +char *kwlist[] = { +"M","numTaps",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|ih", kwlist,&self->instance->M +,&self->instance->numTaps +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_decimate_instance_q15,M,"i"); +GETFIELD(arm_fir_decimate_instance_q15,numTaps,"h"); + + +static PyMethodDef arm_fir_decimate_instance_q15_methods[] = { + + {"M", (PyCFunction) Method_arm_fir_decimate_instance_q15_M,METH_NOARGS,"M"}, + {"numTaps", (PyCFunction) Method_arm_fir_decimate_instance_q15_numTaps,METH_NOARGS,"numTaps"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_decimate_instance_q15,arm_fir_decimate_instance_q15_new,arm_fir_decimate_instance_q15_dealloc,arm_fir_decimate_instance_q15_init,arm_fir_decimate_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_decimate_instance_q31 *instance; +} ml_arm_fir_decimate_instance_q31Object; + + +static void +arm_fir_decimate_instance_q31_dealloc(ml_arm_fir_decimate_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_decimate_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_decimate_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_decimate_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_decimate_instance_q31)); + + self->instance->pCoeffs = NULL; + self->instance->pState = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_decimate_instance_q31_init(ml_arm_fir_decimate_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pCoeffs=NULL; + PyObject *pState=NULL; +char *kwlist[] = { +"M","numTaps",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|ih", kwlist,&self->instance->M +,&self->instance->numTaps +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_decimate_instance_q31,M,"i"); +GETFIELD(arm_fir_decimate_instance_q31,numTaps,"h"); + + +static PyMethodDef arm_fir_decimate_instance_q31_methods[] = { + + {"M", (PyCFunction) Method_arm_fir_decimate_instance_q31_M,METH_NOARGS,"M"}, + {"numTaps", (PyCFunction) Method_arm_fir_decimate_instance_q31_numTaps,METH_NOARGS,"numTaps"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_decimate_instance_q31,arm_fir_decimate_instance_q31_new,arm_fir_decimate_instance_q31_dealloc,arm_fir_decimate_instance_q31_init,arm_fir_decimate_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_decimate_instance_f32 *instance; +} ml_arm_fir_decimate_instance_f32Object; + + +static void +arm_fir_decimate_instance_f32_dealloc(ml_arm_fir_decimate_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_decimate_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_decimate_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_decimate_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_decimate_instance_f32)); + + self->instance->pCoeffs = NULL; + self->instance->pState = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_decimate_instance_f32_init(ml_arm_fir_decimate_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pCoeffs=NULL; + PyObject *pState=NULL; +char *kwlist[] = { +"M","numTaps",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|ih", kwlist,&self->instance->M +,&self->instance->numTaps +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_decimate_instance_f32,M,"i"); +GETFIELD(arm_fir_decimate_instance_f32,numTaps,"h"); + + +static PyMethodDef arm_fir_decimate_instance_f32_methods[] = { + + {"M", (PyCFunction) Method_arm_fir_decimate_instance_f32_M,METH_NOARGS,"M"}, + {"numTaps", (PyCFunction) Method_arm_fir_decimate_instance_f32_numTaps,METH_NOARGS,"numTaps"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_decimate_instance_f32,arm_fir_decimate_instance_f32_new,arm_fir_decimate_instance_f32_dealloc,arm_fir_decimate_instance_f32_init,arm_fir_decimate_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_interpolate_instance_q15 *instance; +} ml_arm_fir_interpolate_instance_q15Object; + + +static void +arm_fir_interpolate_instance_q15_dealloc(ml_arm_fir_interpolate_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_interpolate_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_interpolate_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_interpolate_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_interpolate_instance_q15)); + + self->instance->pCoeffs = NULL; + self->instance->pState = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_interpolate_instance_q15_init(ml_arm_fir_interpolate_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pCoeffs=NULL; + PyObject *pState=NULL; +char *kwlist[] = { +"L","phaseLength",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|ih", kwlist,&self->instance->L +,&self->instance->phaseLength +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_interpolate_instance_q15,L,"i"); +GETFIELD(arm_fir_interpolate_instance_q15,phaseLength,"h"); + + +static PyMethodDef arm_fir_interpolate_instance_q15_methods[] = { + + {"L", (PyCFunction) Method_arm_fir_interpolate_instance_q15_L,METH_NOARGS,"L"}, + {"phaseLength", (PyCFunction) Method_arm_fir_interpolate_instance_q15_phaseLength,METH_NOARGS,"phaseLength"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_interpolate_instance_q15,arm_fir_interpolate_instance_q15_new,arm_fir_interpolate_instance_q15_dealloc,arm_fir_interpolate_instance_q15_init,arm_fir_interpolate_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_interpolate_instance_q31 *instance; +} ml_arm_fir_interpolate_instance_q31Object; + + +static void +arm_fir_interpolate_instance_q31_dealloc(ml_arm_fir_interpolate_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_interpolate_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_interpolate_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_interpolate_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_interpolate_instance_q31)); + + self->instance->pCoeffs = NULL; + self->instance->pState = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_interpolate_instance_q31_init(ml_arm_fir_interpolate_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pCoeffs=NULL; + PyObject *pState=NULL; +char *kwlist[] = { +"L","phaseLength",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|ih", kwlist,&self->instance->L +,&self->instance->phaseLength +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_interpolate_instance_q31,L,"i"); +GETFIELD(arm_fir_interpolate_instance_q31,phaseLength,"h"); + + +static PyMethodDef arm_fir_interpolate_instance_q31_methods[] = { + + {"L", (PyCFunction) Method_arm_fir_interpolate_instance_q31_L,METH_NOARGS,"L"}, + {"phaseLength", (PyCFunction) Method_arm_fir_interpolate_instance_q31_phaseLength,METH_NOARGS,"phaseLength"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_interpolate_instance_q31,arm_fir_interpolate_instance_q31_new,arm_fir_interpolate_instance_q31_dealloc,arm_fir_interpolate_instance_q31_init,arm_fir_interpolate_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_interpolate_instance_f32 *instance; +} ml_arm_fir_interpolate_instance_f32Object; + + +static void +arm_fir_interpolate_instance_f32_dealloc(ml_arm_fir_interpolate_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_interpolate_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_interpolate_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_interpolate_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_interpolate_instance_f32)); + + self->instance->pCoeffs = NULL; + self->instance->pState = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_interpolate_instance_f32_init(ml_arm_fir_interpolate_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pCoeffs=NULL; + PyObject *pState=NULL; +char *kwlist[] = { +"L","phaseLength",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|ih", kwlist,&self->instance->L +,&self->instance->phaseLength +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_interpolate_instance_f32,L,"i"); +GETFIELD(arm_fir_interpolate_instance_f32,phaseLength,"h"); + + +static PyMethodDef arm_fir_interpolate_instance_f32_methods[] = { + + {"L", (PyCFunction) Method_arm_fir_interpolate_instance_f32_L,METH_NOARGS,"L"}, + {"phaseLength", (PyCFunction) Method_arm_fir_interpolate_instance_f32_phaseLength,METH_NOARGS,"phaseLength"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_interpolate_instance_f32,arm_fir_interpolate_instance_f32_new,arm_fir_interpolate_instance_f32_dealloc,arm_fir_interpolate_instance_f32_init,arm_fir_interpolate_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_biquad_cas_df1_32x64_ins_q31 *instance; +} ml_arm_biquad_cas_df1_32x64_ins_q31Object; + + +static void +arm_biquad_cas_df1_32x64_ins_q31_dealloc(ml_arm_biquad_cas_df1_32x64_ins_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_biquad_cas_df1_32x64_ins_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_biquad_cas_df1_32x64_ins_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_biquad_cas_df1_32x64_ins_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_biquad_cas_df1_32x64_ins_q31)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_biquad_cas_df1_32x64_ins_q31_init(ml_arm_biquad_cas_df1_32x64_ins_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numStages","postShift",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|ii", kwlist,&self->instance->numStages +,&self->instance->postShift +)) + { + + + } + return 0; +} + +GETFIELD(arm_biquad_cas_df1_32x64_ins_q31,numStages,"i"); +GETFIELD(arm_biquad_cas_df1_32x64_ins_q31,postShift,"i"); + + +static PyMethodDef arm_biquad_cas_df1_32x64_ins_q31_methods[] = { + + {"numStages", (PyCFunction) Method_arm_biquad_cas_df1_32x64_ins_q31_numStages,METH_NOARGS,"numStages"}, + {"postShift", (PyCFunction) Method_arm_biquad_cas_df1_32x64_ins_q31_postShift,METH_NOARGS,"postShift"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_biquad_cas_df1_32x64_ins_q31,arm_biquad_cas_df1_32x64_ins_q31_new,arm_biquad_cas_df1_32x64_ins_q31_dealloc,arm_biquad_cas_df1_32x64_ins_q31_init,arm_biquad_cas_df1_32x64_ins_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_biquad_cascade_df2T_instance_f32 *instance; +} ml_arm_biquad_cascade_df2T_instance_f32Object; + + +static void +arm_biquad_cascade_df2T_instance_f32_dealloc(ml_arm_biquad_cascade_df2T_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_biquad_cascade_df2T_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_biquad_cascade_df2T_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_biquad_cascade_df2T_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_biquad_cascade_df2T_instance_f32)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_biquad_cascade_df2T_instance_f32_init(ml_arm_biquad_cascade_df2T_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numStages",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|i", kwlist,&self->instance->numStages +)) + { + + + } + return 0; +} + +GETFIELD(arm_biquad_cascade_df2T_instance_f32,numStages,"i"); + + +static PyMethodDef arm_biquad_cascade_df2T_instance_f32_methods[] = { + + {"numStages", (PyCFunction) Method_arm_biquad_cascade_df2T_instance_f32_numStages,METH_NOARGS,"numStages"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_biquad_cascade_df2T_instance_f32,arm_biquad_cascade_df2T_instance_f32_new,arm_biquad_cascade_df2T_instance_f32_dealloc,arm_biquad_cascade_df2T_instance_f32_init,arm_biquad_cascade_df2T_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_biquad_cascade_stereo_df2T_instance_f32 *instance; +} ml_arm_biquad_cascade_stereo_df2T_instance_f32Object; + + +static void +arm_biquad_cascade_stereo_df2T_instance_f32_dealloc(ml_arm_biquad_cascade_stereo_df2T_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_biquad_cascade_stereo_df2T_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_biquad_cascade_stereo_df2T_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_biquad_cascade_stereo_df2T_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_biquad_cascade_stereo_df2T_instance_f32)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_biquad_cascade_stereo_df2T_instance_f32_init(ml_arm_biquad_cascade_stereo_df2T_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numStages",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|i", kwlist,&self->instance->numStages +)) + { + + + } + return 0; +} + +GETFIELD(arm_biquad_cascade_stereo_df2T_instance_f32,numStages,"i"); + + +static PyMethodDef arm_biquad_cascade_stereo_df2T_instance_f32_methods[] = { + + {"numStages", (PyCFunction) Method_arm_biquad_cascade_stereo_df2T_instance_f32_numStages,METH_NOARGS,"numStages"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_biquad_cascade_stereo_df2T_instance_f32,arm_biquad_cascade_stereo_df2T_instance_f32_new,arm_biquad_cascade_stereo_df2T_instance_f32_dealloc,arm_biquad_cascade_stereo_df2T_instance_f32_init,arm_biquad_cascade_stereo_df2T_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_biquad_cascade_df2T_instance_f64 *instance; +} ml_arm_biquad_cascade_df2T_instance_f64Object; + + +static void +arm_biquad_cascade_df2T_instance_f64_dealloc(ml_arm_biquad_cascade_df2T_instance_f64Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_biquad_cascade_df2T_instance_f64_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_biquad_cascade_df2T_instance_f64Object *self; + //printf("New called\n"); + + self = (ml_arm_biquad_cascade_df2T_instance_f64Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_biquad_cascade_df2T_instance_f64)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_biquad_cascade_df2T_instance_f64_init(ml_arm_biquad_cascade_df2T_instance_f64Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numStages",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|i", kwlist,&self->instance->numStages +)) + { + + + } + return 0; +} + +GETFIELD(arm_biquad_cascade_df2T_instance_f64,numStages,"i"); + + +static PyMethodDef arm_biquad_cascade_df2T_instance_f64_methods[] = { + + {"numStages", (PyCFunction) Method_arm_biquad_cascade_df2T_instance_f64_numStages,METH_NOARGS,"numStages"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_biquad_cascade_df2T_instance_f64,arm_biquad_cascade_df2T_instance_f64_new,arm_biquad_cascade_df2T_instance_f64_dealloc,arm_biquad_cascade_df2T_instance_f64_init,arm_biquad_cascade_df2T_instance_f64_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_lattice_instance_q15 *instance; +} ml_arm_fir_lattice_instance_q15Object; + + +static void +arm_fir_lattice_instance_q15_dealloc(ml_arm_fir_lattice_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_lattice_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_lattice_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_lattice_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_lattice_instance_q15)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_lattice_instance_q15_init(ml_arm_fir_lattice_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numStages",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|h", kwlist,&self->instance->numStages +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_lattice_instance_q15,numStages,"h"); + + +static PyMethodDef arm_fir_lattice_instance_q15_methods[] = { + + {"numStages", (PyCFunction) Method_arm_fir_lattice_instance_q15_numStages,METH_NOARGS,"numStages"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_lattice_instance_q15,arm_fir_lattice_instance_q15_new,arm_fir_lattice_instance_q15_dealloc,arm_fir_lattice_instance_q15_init,arm_fir_lattice_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_lattice_instance_q31 *instance; +} ml_arm_fir_lattice_instance_q31Object; + + +static void +arm_fir_lattice_instance_q31_dealloc(ml_arm_fir_lattice_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_lattice_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_lattice_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_lattice_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_lattice_instance_q31)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_lattice_instance_q31_init(ml_arm_fir_lattice_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numStages",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|h", kwlist,&self->instance->numStages +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_lattice_instance_q31,numStages,"h"); + + +static PyMethodDef arm_fir_lattice_instance_q31_methods[] = { + + {"numStages", (PyCFunction) Method_arm_fir_lattice_instance_q31_numStages,METH_NOARGS,"numStages"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_lattice_instance_q31,arm_fir_lattice_instance_q31_new,arm_fir_lattice_instance_q31_dealloc,arm_fir_lattice_instance_q31_init,arm_fir_lattice_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_lattice_instance_f32 *instance; +} ml_arm_fir_lattice_instance_f32Object; + + +static void +arm_fir_lattice_instance_f32_dealloc(ml_arm_fir_lattice_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_lattice_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_lattice_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_lattice_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_lattice_instance_f32)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_lattice_instance_f32_init(ml_arm_fir_lattice_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numStages",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|h", kwlist,&self->instance->numStages +)) + { + + + } + return 0; +} + +GETFIELD(arm_fir_lattice_instance_f32,numStages,"h"); + + +static PyMethodDef arm_fir_lattice_instance_f32_methods[] = { + + {"numStages", (PyCFunction) Method_arm_fir_lattice_instance_f32_numStages,METH_NOARGS,"numStages"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_lattice_instance_f32,arm_fir_lattice_instance_f32_new,arm_fir_lattice_instance_f32_dealloc,arm_fir_lattice_instance_f32_init,arm_fir_lattice_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_iir_lattice_instance_q15 *instance; +} ml_arm_iir_lattice_instance_q15Object; + + +static void +arm_iir_lattice_instance_q15_dealloc(ml_arm_iir_lattice_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pkCoeffs) + { + PyMem_Free(self->instance->pkCoeffs); + } + + + if (self->instance->pvCoeffs) + { + PyMem_Free(self->instance->pvCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_iir_lattice_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_iir_lattice_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_iir_lattice_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_iir_lattice_instance_q15)); + + self->instance->pState = NULL; + self->instance->pkCoeffs = NULL; + self->instance->pvCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_iir_lattice_instance_q15_init(ml_arm_iir_lattice_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pkCoeffs=NULL; + PyObject *pvCoeffs=NULL; +char *kwlist[] = { +"numStages","pkCoeffs","pvCoeffs",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hOO", kwlist,&self->instance->numStages +,&pkCoeffs +,&pvCoeffs +)) + { + + INITARRAYFIELD(pkCoeffs,NPY_INT16,int16_t,int16_t); + INITARRAYFIELD(pvCoeffs,NPY_INT16,int16_t,int16_t); + + } + return 0; +} + +GETFIELD(arm_iir_lattice_instance_q15,numStages,"h"); + + +static PyMethodDef arm_iir_lattice_instance_q15_methods[] = { + + {"numStages", (PyCFunction) Method_arm_iir_lattice_instance_q15_numStages,METH_NOARGS,"numStages"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_iir_lattice_instance_q15,arm_iir_lattice_instance_q15_new,arm_iir_lattice_instance_q15_dealloc,arm_iir_lattice_instance_q15_init,arm_iir_lattice_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_iir_lattice_instance_q31 *instance; +} ml_arm_iir_lattice_instance_q31Object; + + +static void +arm_iir_lattice_instance_q31_dealloc(ml_arm_iir_lattice_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pkCoeffs) + { + PyMem_Free(self->instance->pkCoeffs); + } + + + if (self->instance->pvCoeffs) + { + PyMem_Free(self->instance->pvCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_iir_lattice_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_iir_lattice_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_iir_lattice_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_iir_lattice_instance_q31)); + + self->instance->pState = NULL; + self->instance->pkCoeffs = NULL; + self->instance->pvCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_iir_lattice_instance_q31_init(ml_arm_iir_lattice_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pkCoeffs=NULL; + PyObject *pvCoeffs=NULL; +char *kwlist[] = { +"numStages","pkCoeffs","pvCoeffs",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hOO", kwlist,&self->instance->numStages +,&pkCoeffs +,&pvCoeffs +)) + { + + INITARRAYFIELD(pkCoeffs,NPY_INT32,int32_t,int32_t); + INITARRAYFIELD(pvCoeffs,NPY_INT32,int32_t,int32_t); + + } + return 0; +} + +GETFIELD(arm_iir_lattice_instance_q31,numStages,"h"); + + +static PyMethodDef arm_iir_lattice_instance_q31_methods[] = { + + {"numStages", (PyCFunction) Method_arm_iir_lattice_instance_q31_numStages,METH_NOARGS,"numStages"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_iir_lattice_instance_q31,arm_iir_lattice_instance_q31_new,arm_iir_lattice_instance_q31_dealloc,arm_iir_lattice_instance_q31_init,arm_iir_lattice_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_iir_lattice_instance_f32 *instance; +} ml_arm_iir_lattice_instance_f32Object; + + +static void +arm_iir_lattice_instance_f32_dealloc(ml_arm_iir_lattice_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pkCoeffs) + { + PyMem_Free(self->instance->pkCoeffs); + } + + + if (self->instance->pvCoeffs) + { + PyMem_Free(self->instance->pvCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_iir_lattice_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_iir_lattice_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_iir_lattice_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_iir_lattice_instance_f32)); + + self->instance->pState = NULL; + self->instance->pkCoeffs = NULL; + self->instance->pvCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_iir_lattice_instance_f32_init(ml_arm_iir_lattice_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pkCoeffs=NULL; + PyObject *pvCoeffs=NULL; +char *kwlist[] = { +"numStages","pkCoeffs","pvCoeffs",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hOO", kwlist,&self->instance->numStages +,&pkCoeffs +,&pvCoeffs +)) + { + + INITARRAYFIELD(pkCoeffs,NPY_DOUBLE,double,float32_t); + INITARRAYFIELD(pvCoeffs,NPY_DOUBLE,double,float32_t); + + } + return 0; +} + +GETFIELD(arm_iir_lattice_instance_f32,numStages,"h"); + + +static PyMethodDef arm_iir_lattice_instance_f32_methods[] = { + + {"numStages", (PyCFunction) Method_arm_iir_lattice_instance_f32_numStages,METH_NOARGS,"numStages"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_iir_lattice_instance_f32,arm_iir_lattice_instance_f32_new,arm_iir_lattice_instance_f32_dealloc,arm_iir_lattice_instance_f32_init,arm_iir_lattice_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_lms_instance_f32 *instance; +} ml_arm_lms_instance_f32Object; + + +static void +arm_lms_instance_f32_dealloc(ml_arm_lms_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_lms_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_lms_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_lms_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_lms_instance_f32)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_lms_instance_f32_init(ml_arm_lms_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numTaps","mu",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hf", kwlist,&self->instance->numTaps +,&self->instance->mu +)) + { + + + } + return 0; +} + +GETFIELD(arm_lms_instance_f32,numTaps,"h"); +GETFIELD(arm_lms_instance_f32,mu,"f"); + + +static PyMethodDef arm_lms_instance_f32_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_lms_instance_f32_numTaps,METH_NOARGS,"numTaps"}, + {"mu", (PyCFunction) Method_arm_lms_instance_f32_mu,METH_NOARGS,"mu"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_lms_instance_f32,arm_lms_instance_f32_new,arm_lms_instance_f32_dealloc,arm_lms_instance_f32_init,arm_lms_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_lms_instance_q15 *instance; +} ml_arm_lms_instance_q15Object; + + +static void +arm_lms_instance_q15_dealloc(ml_arm_lms_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_lms_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_lms_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_lms_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_lms_instance_q15)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_lms_instance_q15_init(ml_arm_lms_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numTaps","mu","postShift",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhi", kwlist,&self->instance->numTaps +,&self->instance->mu +,&self->instance->postShift +)) + { + + + } + return 0; +} + +GETFIELD(arm_lms_instance_q15,numTaps,"h"); +GETFIELD(arm_lms_instance_q15,mu,"h"); +GETFIELD(arm_lms_instance_q15,postShift,"i"); + + +static PyMethodDef arm_lms_instance_q15_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_lms_instance_q15_numTaps,METH_NOARGS,"numTaps"}, + {"mu", (PyCFunction) Method_arm_lms_instance_q15_mu,METH_NOARGS,"mu"}, + {"postShift", (PyCFunction) Method_arm_lms_instance_q15_postShift,METH_NOARGS,"postShift"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_lms_instance_q15,arm_lms_instance_q15_new,arm_lms_instance_q15_dealloc,arm_lms_instance_q15_init,arm_lms_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_lms_instance_q31 *instance; +} ml_arm_lms_instance_q31Object; + + +static void +arm_lms_instance_q31_dealloc(ml_arm_lms_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_lms_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_lms_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_lms_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_lms_instance_q31)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_lms_instance_q31_init(ml_arm_lms_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numTaps","mu","postShift",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hii", kwlist,&self->instance->numTaps +,&self->instance->mu +,&self->instance->postShift +)) + { + + + } + return 0; +} + +GETFIELD(arm_lms_instance_q31,numTaps,"h"); +GETFIELD(arm_lms_instance_q31,mu,"i"); +GETFIELD(arm_lms_instance_q31,postShift,"i"); + + +static PyMethodDef arm_lms_instance_q31_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_lms_instance_q31_numTaps,METH_NOARGS,"numTaps"}, + {"mu", (PyCFunction) Method_arm_lms_instance_q31_mu,METH_NOARGS,"mu"}, + {"postShift", (PyCFunction) Method_arm_lms_instance_q31_postShift,METH_NOARGS,"postShift"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_lms_instance_q31,arm_lms_instance_q31_new,arm_lms_instance_q31_dealloc,arm_lms_instance_q31_init,arm_lms_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_lms_norm_instance_f32 *instance; +} ml_arm_lms_norm_instance_f32Object; + + +static void +arm_lms_norm_instance_f32_dealloc(ml_arm_lms_norm_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_lms_norm_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_lms_norm_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_lms_norm_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_lms_norm_instance_f32)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_lms_norm_instance_f32_init(ml_arm_lms_norm_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; +char *kwlist[] = { +"numTaps","mu","energy","x0",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hfff", kwlist,&self->instance->numTaps +,&self->instance->mu +,&self->instance->energy +,&self->instance->x0 +)) + { + + + } + return 0; +} + +GETFIELD(arm_lms_norm_instance_f32,numTaps,"h"); +GETFIELD(arm_lms_norm_instance_f32,mu,"f"); +GETFIELD(arm_lms_norm_instance_f32,energy,"f"); +GETFIELD(arm_lms_norm_instance_f32,x0,"f"); + + +static PyMethodDef arm_lms_norm_instance_f32_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_lms_norm_instance_f32_numTaps,METH_NOARGS,"numTaps"}, + {"mu", (PyCFunction) Method_arm_lms_norm_instance_f32_mu,METH_NOARGS,"mu"}, + {"energy", (PyCFunction) Method_arm_lms_norm_instance_f32_energy,METH_NOARGS,"energy"}, + {"x0", (PyCFunction) Method_arm_lms_norm_instance_f32_x0,METH_NOARGS,"x0"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_lms_norm_instance_f32,arm_lms_norm_instance_f32_new,arm_lms_norm_instance_f32_dealloc,arm_lms_norm_instance_f32_init,arm_lms_norm_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_lms_norm_instance_q31 *instance; +} ml_arm_lms_norm_instance_q31Object; + + +static void +arm_lms_norm_instance_q31_dealloc(ml_arm_lms_norm_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_lms_norm_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_lms_norm_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_lms_norm_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_lms_norm_instance_q31)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + self->instance->recipTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_lms_norm_instance_q31_init(ml_arm_lms_norm_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; + PyObject *recipTable=NULL; +char *kwlist[] = { +"numTaps","mu","postShift","energy","x0",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hiiii", kwlist,&self->instance->numTaps +,&self->instance->mu +,&self->instance->postShift +,&self->instance->energy +,&self->instance->x0 +)) + { + + + } + return 0; +} + +GETFIELD(arm_lms_norm_instance_q31,numTaps,"h"); +GETFIELD(arm_lms_norm_instance_q31,mu,"i"); +GETFIELD(arm_lms_norm_instance_q31,postShift,"i"); +GETFIELD(arm_lms_norm_instance_q31,energy,"i"); +GETFIELD(arm_lms_norm_instance_q31,x0,"i"); + + +static PyMethodDef arm_lms_norm_instance_q31_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_lms_norm_instance_q31_numTaps,METH_NOARGS,"numTaps"}, + {"mu", (PyCFunction) Method_arm_lms_norm_instance_q31_mu,METH_NOARGS,"mu"}, + {"postShift", (PyCFunction) Method_arm_lms_norm_instance_q31_postShift,METH_NOARGS,"postShift"}, + {"energy", (PyCFunction) Method_arm_lms_norm_instance_q31_energy,METH_NOARGS,"energy"}, + {"x0", (PyCFunction) Method_arm_lms_norm_instance_q31_x0,METH_NOARGS,"x0"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_lms_norm_instance_q31,arm_lms_norm_instance_q31_new,arm_lms_norm_instance_q31_dealloc,arm_lms_norm_instance_q31_init,arm_lms_norm_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_lms_norm_instance_q15 *instance; +} ml_arm_lms_norm_instance_q15Object; + + +static void +arm_lms_norm_instance_q15_dealloc(ml_arm_lms_norm_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_lms_norm_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_lms_norm_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_lms_norm_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_lms_norm_instance_q15)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + self->instance->recipTable = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_lms_norm_instance_q15_init(ml_arm_lms_norm_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; + PyObject *recipTable=NULL; +char *kwlist[] = { +"numTaps","mu","postShift","energy","x0",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhihh", kwlist,&self->instance->numTaps +,&self->instance->mu +,&self->instance->postShift +,&self->instance->energy +,&self->instance->x0 +)) + { + + + } + return 0; +} + +GETFIELD(arm_lms_norm_instance_q15,numTaps,"h"); +GETFIELD(arm_lms_norm_instance_q15,mu,"h"); +GETFIELD(arm_lms_norm_instance_q15,postShift,"i"); +GETFIELD(arm_lms_norm_instance_q15,energy,"h"); +GETFIELD(arm_lms_norm_instance_q15,x0,"h"); + + +static PyMethodDef arm_lms_norm_instance_q15_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_lms_norm_instance_q15_numTaps,METH_NOARGS,"numTaps"}, + {"mu", (PyCFunction) Method_arm_lms_norm_instance_q15_mu,METH_NOARGS,"mu"}, + {"postShift", (PyCFunction) Method_arm_lms_norm_instance_q15_postShift,METH_NOARGS,"postShift"}, + {"energy", (PyCFunction) Method_arm_lms_norm_instance_q15_energy,METH_NOARGS,"energy"}, + {"x0", (PyCFunction) Method_arm_lms_norm_instance_q15_x0,METH_NOARGS,"x0"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_lms_norm_instance_q15,arm_lms_norm_instance_q15_new,arm_lms_norm_instance_q15_dealloc,arm_lms_norm_instance_q15_init,arm_lms_norm_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_sparse_instance_f32 *instance; +} ml_arm_fir_sparse_instance_f32Object; + + +static void +arm_fir_sparse_instance_f32_dealloc(ml_arm_fir_sparse_instance_f32Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + if (self->instance->pTapDelay) + { + PyMem_Free(self->instance->pTapDelay); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_sparse_instance_f32_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_sparse_instance_f32Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_sparse_instance_f32Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_sparse_instance_f32)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + self->instance->pTapDelay = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_sparse_instance_f32_init(ml_arm_fir_sparse_instance_f32Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; + PyObject *pTapDelay=NULL; +char *kwlist[] = { +"numTaps","stateIndex","maxDelay","pTapDelay",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhhO", kwlist,&self->instance->numTaps +,&self->instance->stateIndex +,&self->instance->maxDelay +,&pTapDelay +)) + { + + INITARRAYFIELD(pTapDelay,NPY_INT32,int32_t,int32_t); + + } + return 0; +} + +GETFIELD(arm_fir_sparse_instance_f32,numTaps,"h"); +GETFIELD(arm_fir_sparse_instance_f32,stateIndex,"h"); +GETFIELD(arm_fir_sparse_instance_f32,maxDelay,"h"); + + +static PyMethodDef arm_fir_sparse_instance_f32_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_fir_sparse_instance_f32_numTaps,METH_NOARGS,"numTaps"}, + {"stateIndex", (PyCFunction) Method_arm_fir_sparse_instance_f32_stateIndex,METH_NOARGS,"stateIndex"}, + {"maxDelay", (PyCFunction) Method_arm_fir_sparse_instance_f32_maxDelay,METH_NOARGS,"maxDelay"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_sparse_instance_f32,arm_fir_sparse_instance_f32_new,arm_fir_sparse_instance_f32_dealloc,arm_fir_sparse_instance_f32_init,arm_fir_sparse_instance_f32_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_sparse_instance_q31 *instance; +} ml_arm_fir_sparse_instance_q31Object; + + +static void +arm_fir_sparse_instance_q31_dealloc(ml_arm_fir_sparse_instance_q31Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + if (self->instance->pTapDelay) + { + PyMem_Free(self->instance->pTapDelay); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_sparse_instance_q31_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_sparse_instance_q31Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_sparse_instance_q31Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_sparse_instance_q31)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + self->instance->pTapDelay = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_sparse_instance_q31_init(ml_arm_fir_sparse_instance_q31Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; + PyObject *pTapDelay=NULL; +char *kwlist[] = { +"numTaps","stateIndex","maxDelay","pTapDelay",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhhO", kwlist,&self->instance->numTaps +,&self->instance->stateIndex +,&self->instance->maxDelay +,&pTapDelay +)) + { + + INITARRAYFIELD(pTapDelay,NPY_INT32,int32_t,int32_t); + + } + return 0; +} + +GETFIELD(arm_fir_sparse_instance_q31,numTaps,"h"); +GETFIELD(arm_fir_sparse_instance_q31,stateIndex,"h"); +GETFIELD(arm_fir_sparse_instance_q31,maxDelay,"h"); + + +static PyMethodDef arm_fir_sparse_instance_q31_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_fir_sparse_instance_q31_numTaps,METH_NOARGS,"numTaps"}, + {"stateIndex", (PyCFunction) Method_arm_fir_sparse_instance_q31_stateIndex,METH_NOARGS,"stateIndex"}, + {"maxDelay", (PyCFunction) Method_arm_fir_sparse_instance_q31_maxDelay,METH_NOARGS,"maxDelay"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_sparse_instance_q31,arm_fir_sparse_instance_q31_new,arm_fir_sparse_instance_q31_dealloc,arm_fir_sparse_instance_q31_init,arm_fir_sparse_instance_q31_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_sparse_instance_q15 *instance; +} ml_arm_fir_sparse_instance_q15Object; + + +static void +arm_fir_sparse_instance_q15_dealloc(ml_arm_fir_sparse_instance_q15Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + if (self->instance->pTapDelay) + { + PyMem_Free(self->instance->pTapDelay); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_sparse_instance_q15_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_sparse_instance_q15Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_sparse_instance_q15Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_sparse_instance_q15)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + self->instance->pTapDelay = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_sparse_instance_q15_init(ml_arm_fir_sparse_instance_q15Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; + PyObject *pTapDelay=NULL; +char *kwlist[] = { +"numTaps","stateIndex","maxDelay","pTapDelay",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhhO", kwlist,&self->instance->numTaps +,&self->instance->stateIndex +,&self->instance->maxDelay +,&pTapDelay +)) + { + + INITARRAYFIELD(pTapDelay,NPY_INT32,int32_t,int32_t); + + } + return 0; +} + +GETFIELD(arm_fir_sparse_instance_q15,numTaps,"h"); +GETFIELD(arm_fir_sparse_instance_q15,stateIndex,"h"); +GETFIELD(arm_fir_sparse_instance_q15,maxDelay,"h"); + + +static PyMethodDef arm_fir_sparse_instance_q15_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_fir_sparse_instance_q15_numTaps,METH_NOARGS,"numTaps"}, + {"stateIndex", (PyCFunction) Method_arm_fir_sparse_instance_q15_stateIndex,METH_NOARGS,"stateIndex"}, + {"maxDelay", (PyCFunction) Method_arm_fir_sparse_instance_q15_maxDelay,METH_NOARGS,"maxDelay"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_sparse_instance_q15,arm_fir_sparse_instance_q15_new,arm_fir_sparse_instance_q15_dealloc,arm_fir_sparse_instance_q15_init,arm_fir_sparse_instance_q15_methods); + + +typedef struct { + PyObject_HEAD + arm_fir_sparse_instance_q7 *instance; +} ml_arm_fir_sparse_instance_q7Object; + + +static void +arm_fir_sparse_instance_q7_dealloc(ml_arm_fir_sparse_instance_q7Object* self) +{ + //printf("Dealloc called\n"); + if (self->instance) + { + + + if (self->instance->pState) + { + PyMem_Free(self->instance->pState); + } + + + if (self->instance->pCoeffs) + { + PyMem_Free(self->instance->pCoeffs); + } + + + if (self->instance->pTapDelay) + { + PyMem_Free(self->instance->pTapDelay); + } + + + PyMem_Free(self->instance); + } + + Py_TYPE(self)->tp_free((PyObject*)self); +} + + +static PyObject * +arm_fir_sparse_instance_q7_new(PyTypeObject *type, PyObject *args, PyObject *kwds) +{ + ml_arm_fir_sparse_instance_q7Object *self; + //printf("New called\n"); + + self = (ml_arm_fir_sparse_instance_q7Object *)type->tp_alloc(type, 0); + //printf("alloc called\n"); + + if (self != NULL) { + + self->instance = PyMem_Malloc(sizeof(arm_fir_sparse_instance_q7)); + + self->instance->pState = NULL; + self->instance->pCoeffs = NULL; + self->instance->pTapDelay = NULL; + + } + + + return (PyObject *)self; +} + +static int +arm_fir_sparse_instance_q7_init(ml_arm_fir_sparse_instance_q7Object *self, PyObject *args, PyObject *kwds) +{ + + PyObject *pState=NULL; + PyObject *pCoeffs=NULL; + PyObject *pTapDelay=NULL; +char *kwlist[] = { +"numTaps","stateIndex","maxDelay","pTapDelay",NULL +}; + +if (PyArg_ParseTupleAndKeywords(args, kwds, "|hhhO", kwlist,&self->instance->numTaps +,&self->instance->stateIndex +,&self->instance->maxDelay +,&pTapDelay +)) + { + + INITARRAYFIELD(pTapDelay,NPY_INT32,int32_t,int32_t); + + } + return 0; +} + +GETFIELD(arm_fir_sparse_instance_q7,numTaps,"h"); +GETFIELD(arm_fir_sparse_instance_q7,stateIndex,"h"); +GETFIELD(arm_fir_sparse_instance_q7,maxDelay,"h"); + + +static PyMethodDef arm_fir_sparse_instance_q7_methods[] = { + + {"numTaps", (PyCFunction) Method_arm_fir_sparse_instance_q7_numTaps,METH_NOARGS,"numTaps"}, + {"stateIndex", (PyCFunction) Method_arm_fir_sparse_instance_q7_stateIndex,METH_NOARGS,"stateIndex"}, + {"maxDelay", (PyCFunction) Method_arm_fir_sparse_instance_q7_maxDelay,METH_NOARGS,"maxDelay"}, + + {NULL} /* Sentinel */ +}; + + +MLTYPE(arm_fir_sparse_instance_q7,arm_fir_sparse_instance_q7_new,arm_fir_sparse_instance_q7_dealloc,arm_fir_sparse_instance_q7_init,arm_fir_sparse_instance_q7_methods); + + +void typeRegistration(PyObject *module) { + + ADDTYPE(arm_fir_instance_q7); + ADDTYPE(arm_fir_instance_q15); + ADDTYPE(arm_fir_instance_q31); + ADDTYPE(arm_fir_instance_f32); + ADDTYPE(arm_biquad_casd_df1_inst_q15); + ADDTYPE(arm_biquad_casd_df1_inst_q31); + ADDTYPE(arm_biquad_casd_df1_inst_f32); + ADDTYPE(arm_matrix_instance_f32); + ADDTYPE(arm_matrix_instance_f64); + ADDTYPE(arm_matrix_instance_q15); + ADDTYPE(arm_matrix_instance_q31); + ADDTYPE(arm_pid_instance_q15); + ADDTYPE(arm_pid_instance_q31); + ADDTYPE(arm_pid_instance_f32); + ADDTYPE(arm_linear_interp_instance_f32); + ADDTYPE(arm_bilinear_interp_instance_f32); + ADDTYPE(arm_bilinear_interp_instance_q31); + ADDTYPE(arm_bilinear_interp_instance_q15); + ADDTYPE(arm_bilinear_interp_instance_q7); + ADDTYPE(arm_cfft_radix2_instance_q15); + ADDTYPE(arm_cfft_radix4_instance_q15); + ADDTYPE(arm_cfft_radix2_instance_q31); + ADDTYPE(arm_cfft_radix4_instance_q31); + ADDTYPE(arm_cfft_radix2_instance_f32); + ADDTYPE(arm_cfft_radix4_instance_f32); + ADDTYPE(arm_cfft_instance_q15); + ADDTYPE(arm_cfft_instance_q31); + ADDTYPE(arm_cfft_instance_f32); + ADDTYPE(arm_rfft_instance_q15); + ADDTYPE(arm_rfft_instance_q31); + ADDTYPE(arm_rfft_instance_f32); + ADDTYPE(arm_rfft_fast_instance_f32); + ADDTYPE(arm_dct4_instance_f32); + ADDTYPE(arm_dct4_instance_q31); + ADDTYPE(arm_dct4_instance_q15); + ADDTYPE(arm_fir_decimate_instance_q15); + ADDTYPE(arm_fir_decimate_instance_q31); + ADDTYPE(arm_fir_decimate_instance_f32); + ADDTYPE(arm_fir_interpolate_instance_q15); + ADDTYPE(arm_fir_interpolate_instance_q31); + ADDTYPE(arm_fir_interpolate_instance_f32); + ADDTYPE(arm_biquad_cas_df1_32x64_ins_q31); + ADDTYPE(arm_biquad_cascade_df2T_instance_f32); + ADDTYPE(arm_biquad_cascade_stereo_df2T_instance_f32); + ADDTYPE(arm_biquad_cascade_df2T_instance_f64); + ADDTYPE(arm_fir_lattice_instance_q15); + ADDTYPE(arm_fir_lattice_instance_q31); + ADDTYPE(arm_fir_lattice_instance_f32); + ADDTYPE(arm_iir_lattice_instance_q15); + ADDTYPE(arm_iir_lattice_instance_q31); + ADDTYPE(arm_iir_lattice_instance_f32); + ADDTYPE(arm_lms_instance_f32); + ADDTYPE(arm_lms_instance_q15); + ADDTYPE(arm_lms_instance_q31); + ADDTYPE(arm_lms_norm_instance_f32); + ADDTYPE(arm_lms_norm_instance_q31); + ADDTYPE(arm_lms_norm_instance_q15); + ADDTYPE(arm_fir_sparse_instance_f32); + ADDTYPE(arm_fir_sparse_instance_q31); + ADDTYPE(arm_fir_sparse_instance_q15); + ADDTYPE(arm_fir_sparse_instance_q7); + +} + + +static PyObject * +cmsis_arm_recip_q31(PyObject *obj, PyObject *args) +{ + + q31_t in; // input + q31_t *dst=NULL; // output + PyObject *pRecipTable=NULL; // input + q31_t *pRecipTable_converted=NULL; // input + + if (PyArg_ParseTuple(args,"iO",&in,&pRecipTable)) + { + + GETARGUMENT(pRecipTable,NPY_INT32,int32_t,int32_t); + + dst=PyMem_Malloc(sizeof(q31_t)*1); + + + uint32_t returnValue = arm_recip_q31(in,dst,pRecipTable_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* dstOBJ=Py_BuildValue("i",*dst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,dstOBJ); + + Py_DECREF(theReturnOBJ); + Py_DECREF(dstOBJ); + FREEARGUMENT(pRecipTable_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_recip_q15(PyObject *obj, PyObject *args) +{ + + q15_t in; // input + q15_t *dst=NULL; // output + PyObject *pRecipTable=NULL; // input + q15_t *pRecipTable_converted=NULL; // input + + if (PyArg_ParseTuple(args,"hO",&in,&pRecipTable)) + { + + GETARGUMENT(pRecipTable,NPY_INT16,int16_t,int16_t); + + dst=PyMem_Malloc(sizeof(q15_t)*1); + + + uint32_t returnValue = arm_recip_q15(in,dst,pRecipTable_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* dstOBJ=Py_BuildValue("h",*dst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,dstOBJ); + + Py_DECREF(theReturnOBJ); + Py_DECREF(dstOBJ); + FREEARGUMENT(pRecipTable_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_q7(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_instance_q7Object *selfS = (ml_arm_fir_instance_q7Object *)S; + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_fir_q7(selfS->instance,pSrc_converted,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_init_q7(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q7_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q7_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOO",&S,&numTaps,&pCoeffs,&pState)) + { + + ml_arm_fir_instance_q7Object *selfS = (ml_arm_fir_instance_q7Object *)S; + GETARGUMENT(pCoeffs,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pState,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_fir_init_q7(selfS->instance,numTaps,pCoeffs_converted,pState_converted,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_instance_q15Object *selfS = (ml_arm_fir_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_fir_q15(selfS->instance,pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_fast_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_instance_q15Object *selfS = (ml_arm_fir_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_fir_fast_q15(selfS->instance,pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q15_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOO",&S,&numTaps,&pCoeffs,&pState)) + { + + ml_arm_fir_instance_q15Object *selfS = (ml_arm_fir_instance_q15Object *)S; + GETARGUMENT(pCoeffs,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_status returnValue = arm_fir_init_q15(selfS->instance,numTaps,pCoeffs_converted,pState_converted,blockSize); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_instance_q31Object *selfS = (ml_arm_fir_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_fir_q31(selfS->instance,pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_fast_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_instance_q31Object *selfS = (ml_arm_fir_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_fir_fast_q31(selfS->instance,pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q31_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q31_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOO",&S,&numTaps,&pCoeffs,&pState)) + { + + ml_arm_fir_instance_q31Object *selfS = (ml_arm_fir_instance_q31Object *)S; + GETARGUMENT(pCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pState,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_fir_init_q31(selfS->instance,numTaps,pCoeffs_converted,pState_converted,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_instance_f32Object *selfS = (ml_arm_fir_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_fir_f32(selfS->instance,pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + float32_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOO",&S,&numTaps,&pCoeffs,&pState)) + { + + ml_arm_fir_instance_f32Object *selfS = (ml_arm_fir_instance_f32Object *)S; + GETARGUMENT(pCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_fir_init_f32(selfS->instance,numTaps,pCoeffs_converted,pState_converted,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df1_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_biquad_casd_df1_inst_q15Object *selfS = (ml_arm_biquad_casd_df1_inst_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_biquad_cascade_df1_q15(selfS->instance,pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df1_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t numStages; // input + PyObject *pCoeffs=NULL; // input + q15_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + int32_t postShift; // input + + if (PyArg_ParseTuple(args,"OiOOi",&S,&numStages,&pCoeffs,&pState,&postShift)) + { + + ml_arm_biquad_casd_df1_inst_q15Object *selfS = (ml_arm_biquad_casd_df1_inst_q15Object *)S; + GETARGUMENT(pCoeffs,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + + arm_biquad_cascade_df1_init_q15(selfS->instance,(uint8_t)numStages,pCoeffs_converted,pState_converted,(int8_t)postShift); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df1_fast_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_biquad_casd_df1_inst_q15Object *selfS = (ml_arm_biquad_casd_df1_inst_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_biquad_cascade_df1_fast_q15(selfS->instance,pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df1_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_biquad_casd_df1_inst_q31Object *selfS = (ml_arm_biquad_casd_df1_inst_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_biquad_cascade_df1_q31(selfS->instance,pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df1_fast_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_biquad_casd_df1_inst_q31Object *selfS = (ml_arm_biquad_casd_df1_inst_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_biquad_cascade_df1_fast_q31(selfS->instance,pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df1_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t numStages; // input + PyObject *pCoeffs=NULL; // input + q31_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q31_t *pState_converted=NULL; // input + int32_t postShift; // input + + if (PyArg_ParseTuple(args,"OiOOi",&S,&numStages,&pCoeffs,&pState,&postShift)) + { + + ml_arm_biquad_casd_df1_inst_q31Object *selfS = (ml_arm_biquad_casd_df1_inst_q31Object *)S; + GETARGUMENT(pCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pState,NPY_INT32,int32_t,int32_t); + + arm_biquad_cascade_df1_init_q31(selfS->instance,(uint8_t)numStages,pCoeffs_converted,pState_converted,(int8_t)postShift); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df1_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_biquad_casd_df1_inst_f32Object *selfS = (ml_arm_biquad_casd_df1_inst_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_biquad_cascade_df1_f32(selfS->instance,pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df1_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t numStages; // input + PyObject *pCoeffs=NULL; // input + float32_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOO",&S,&numStages,&pCoeffs,&pState)) + { + + ml_arm_biquad_casd_df1_inst_f32Object *selfS = (ml_arm_biquad_casd_df1_inst_f32Object *)S; + GETARGUMENT(pCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + + arm_biquad_cascade_df1_init_f32(selfS->instance,(uint8_t)numStages,pCoeffs_converted,pState_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_add_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_f32 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_f32 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_f32 *pSrcA_converted = f32MatrixFromNumpy(pSrcA); + arm_matrix_instance_f32 *pSrcB_converted = f32MatrixFromNumpy(pSrcB); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_f32 *pDst_converted = createf32Matrix(row,column); + + arm_status returnValue = arm_mat_add_f32(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromf32Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_add_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_q15 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_q15 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_q15 *pSrcA_converted = q15MatrixFromNumpy(pSrcA); + arm_matrix_instance_q15 *pSrcB_converted = q15MatrixFromNumpy(pSrcB); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_q15 *pDst_converted = createq15Matrix(row,column); + + arm_status returnValue = arm_mat_add_q15(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq15Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_add_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_q31 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_q31 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_q31 *pSrcA_converted = q31MatrixFromNumpy(pSrcA); + arm_matrix_instance_q31 *pSrcB_converted = q31MatrixFromNumpy(pSrcB); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_q31 *pDst_converted = createq31Matrix(row,column); + + arm_status returnValue = arm_mat_add_q31(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq31Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_cmplx_mult_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_f32 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_f32 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_f32 *pSrcA_converted = f32MatrixFromNumpy(pSrcA); + arm_matrix_instance_f32 *pSrcB_converted = f32MatrixFromNumpy(pSrcB); + pSrcA_converted->numCols = pSrcA_converted->numCols / 2; + pSrcB_converted->numCols = pSrcB_converted->numCols / 2; + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols * 2; + arm_matrix_instance_f32 *pDst_converted = createf32Matrix(row,column); + + arm_status returnValue = arm_mat_cmplx_mult_f32(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromf32Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_cmplx_mult_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_q15 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_q15 *pSrcB_converted=NULL; // input + PyObject *pScratch=NULL; // input + q15_t *pScratch_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OOO",&pSrcA,&pSrcB,&pScratch)) + { + + arm_matrix_instance_q15 *pSrcA_converted = q15MatrixFromNumpy(pSrcA); + arm_matrix_instance_q15 *pSrcB_converted = q15MatrixFromNumpy(pSrcB); + GETARGUMENT(pScratch,NPY_INT16,int16_t,int16_t); + pSrcA_converted->numCols = pSrcA_converted->numCols / 2; + pSrcB_converted->numCols = pSrcB_converted->numCols / 2; + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols * 2; + arm_matrix_instance_q15 *pDst_converted = createq15Matrix(row,column); + + arm_status returnValue = arm_mat_cmplx_mult_q15(pSrcA_converted,pSrcB_converted,pDst_converted,pScratch_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq15Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratch_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_cmplx_mult_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_q31 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_q31 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_q31 *pSrcA_converted = q31MatrixFromNumpy(pSrcA); + arm_matrix_instance_q31 *pSrcB_converted = q31MatrixFromNumpy(pSrcB); + pSrcA_converted->numCols = pSrcA_converted->numCols / 2; + pSrcB_converted->numCols = pSrcB_converted->numCols / 2; + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols * 2; + arm_matrix_instance_q31 *pDst_converted = createq31Matrix(row,column); + + arm_status returnValue = arm_mat_cmplx_mult_q31(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq31Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_trans_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + arm_matrix_instance_f32 *pSrc_converted=NULL; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + arm_matrix_instance_f32 *pSrc_converted = f32MatrixFromNumpy(pSrc); + uint32_t row = pSrc_converted->numCols ; + uint32_t column = pSrc_converted->numRows ; + arm_matrix_instance_f32 *pDst_converted = createf32Matrix(row,column); + + arm_status returnValue = arm_mat_trans_f32(pSrc_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromf32Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_trans_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + arm_matrix_instance_q15 *pSrc_converted=NULL; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + arm_matrix_instance_q15 *pSrc_converted = q15MatrixFromNumpy(pSrc); + uint32_t row = pSrc_converted->numCols ; + uint32_t column = pSrc_converted->numRows ; + arm_matrix_instance_q15 *pDst_converted = createq15Matrix(row,column); + + arm_status returnValue = arm_mat_trans_q15(pSrc_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq15Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_trans_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + arm_matrix_instance_q31 *pSrc_converted=NULL; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + arm_matrix_instance_q31 *pSrc_converted = q31MatrixFromNumpy(pSrc); + uint32_t row = pSrc_converted->numCols ; + uint32_t column = pSrc_converted->numRows ; + arm_matrix_instance_q31 *pDst_converted = createq31Matrix(row,column); + + arm_status returnValue = arm_mat_trans_q31(pSrc_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq31Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_mult_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_f32 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_f32 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_f32 *pSrcA_converted = f32MatrixFromNumpy(pSrcA); + arm_matrix_instance_f32 *pSrcB_converted = f32MatrixFromNumpy(pSrcB); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_f32 *pDst_converted = createf32Matrix(row,column); + + arm_status returnValue = arm_mat_mult_f32(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromf32Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_mult_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_q15 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_q15 *pSrcB_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OOO",&pSrcA,&pSrcB,&pState)) + { + + arm_matrix_instance_q15 *pSrcA_converted = q15MatrixFromNumpy(pSrcA); + arm_matrix_instance_q15 *pSrcB_converted = q15MatrixFromNumpy(pSrcB); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_q15 *pDst_converted = createq15Matrix(row,column); + + arm_status returnValue = arm_mat_mult_q15(pSrcA_converted,pSrcB_converted,pDst_converted,pState_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq15Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pState_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_mult_fast_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_q15 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_q15 *pSrcB_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OOO",&pSrcA,&pSrcB,&pState)) + { + + arm_matrix_instance_q15 *pSrcA_converted = q15MatrixFromNumpy(pSrcA); + arm_matrix_instance_q15 *pSrcB_converted = q15MatrixFromNumpy(pSrcB); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_q15 *pDst_converted = createq15Matrix(row,column); + + arm_status returnValue = arm_mat_mult_fast_q15(pSrcA_converted,pSrcB_converted,pDst_converted,pState_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq15Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pState_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_mult_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_q31 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_q31 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_q31 *pSrcA_converted = q31MatrixFromNumpy(pSrcA); + arm_matrix_instance_q31 *pSrcB_converted = q31MatrixFromNumpy(pSrcB); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_q31 *pDst_converted = createq31Matrix(row,column); + + arm_status returnValue = arm_mat_mult_q31(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq31Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_mult_fast_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_q31 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_q31 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_q31 *pSrcA_converted = q31MatrixFromNumpy(pSrcA); + arm_matrix_instance_q31 *pSrcB_converted = q31MatrixFromNumpy(pSrcB); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_q31 *pDst_converted = createq31Matrix(row,column); + + arm_status returnValue = arm_mat_mult_fast_q31(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq31Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_sub_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_f32 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_f32 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_f32 *pSrcA_converted = f32MatrixFromNumpy(pSrcA); + arm_matrix_instance_f32 *pSrcB_converted = f32MatrixFromNumpy(pSrcB); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_f32 *pDst_converted = createf32Matrix(row,column); + + arm_status returnValue = arm_mat_sub_f32(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromf32Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_sub_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_q15 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_q15 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_q15 *pSrcA_converted = q15MatrixFromNumpy(pSrcA); + arm_matrix_instance_q15 *pSrcB_converted = q15MatrixFromNumpy(pSrcB); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_q15 *pDst_converted = createq15Matrix(row,column); + + arm_status returnValue = arm_mat_sub_q15(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq15Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_sub_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + arm_matrix_instance_q31 *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + arm_matrix_instance_q31 *pSrcB_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + arm_matrix_instance_q31 *pSrcA_converted = q31MatrixFromNumpy(pSrcA); + arm_matrix_instance_q31 *pSrcB_converted = q31MatrixFromNumpy(pSrcB); + uint32_t row = pSrcA_converted->numRows ; + uint32_t column = pSrcB_converted->numCols ; + arm_matrix_instance_q31 *pDst_converted = createq31Matrix(row,column); + + arm_status returnValue = arm_mat_sub_q31(pSrcA_converted,pSrcB_converted,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq31Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_scale_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + arm_matrix_instance_f32 *pSrc_converted=NULL; // input + float32_t scale; // input + + if (PyArg_ParseTuple(args,"Of",&pSrc,&scale)) + { + + arm_matrix_instance_f32 *pSrc_converted = f32MatrixFromNumpy(pSrc); + uint32_t row = pSrc_converted->numRows ; + uint32_t column = pSrc_converted->numCols ; + arm_matrix_instance_f32 *pDst_converted = createf32Matrix(row,column); + + arm_status returnValue = arm_mat_scale_f32(pSrc_converted,scale,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromf32Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_scale_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + arm_matrix_instance_q15 *pSrc_converted=NULL; // input + q15_t scaleFract; // input + int32_t shift; // input + + if (PyArg_ParseTuple(args,"Ohi",&pSrc,&scaleFract,&shift)) + { + + arm_matrix_instance_q15 *pSrc_converted = q15MatrixFromNumpy(pSrc); + uint32_t row = pSrc_converted->numRows ; + uint32_t column = pSrc_converted->numCols ; + arm_matrix_instance_q15 *pDst_converted = createq15Matrix(row,column); + + arm_status returnValue = arm_mat_scale_q15(pSrc_converted,scaleFract,shift,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq15Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_scale_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + arm_matrix_instance_q31 *pSrc_converted=NULL; // input + q31_t scaleFract; // input + int32_t shift; // input + + if (PyArg_ParseTuple(args,"Oii",&pSrc,&scaleFract,&shift)) + { + + arm_matrix_instance_q31 *pSrc_converted = q31MatrixFromNumpy(pSrc); + uint32_t row = pSrc_converted->numRows ; + uint32_t column = pSrc_converted->numCols ; + arm_matrix_instance_q31 *pDst_converted = createq31Matrix(row,column); + + arm_status returnValue = arm_mat_scale_q31(pSrc_converted,scaleFract,shift,pDst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pDstOBJ=NumpyArrayFromq31Matrix(pDst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_pid_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + int32_t resetStateFlag; // input + + if (PyArg_ParseTuple(args,"Oi",&S,&resetStateFlag)) + { + + ml_arm_pid_instance_f32Object *selfS = (ml_arm_pid_instance_f32Object *)S; + + arm_pid_init_f32(selfS->instance,resetStateFlag); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_pid_reset_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_pid_instance_f32Object *selfS = (ml_arm_pid_instance_f32Object *)S; + + arm_pid_reset_f32(selfS->instance); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_pid_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + int32_t resetStateFlag; // input + + if (PyArg_ParseTuple(args,"Oi",&S,&resetStateFlag)) + { + + ml_arm_pid_instance_q31Object *selfS = (ml_arm_pid_instance_q31Object *)S; + + arm_pid_init_q31(selfS->instance,resetStateFlag); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_pid_reset_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_pid_instance_q31Object *selfS = (ml_arm_pid_instance_q31Object *)S; + + arm_pid_reset_q31(selfS->instance); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_pid_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + int32_t resetStateFlag; // input + + if (PyArg_ParseTuple(args,"Oi",&S,&resetStateFlag)) + { + + ml_arm_pid_instance_q15Object *selfS = (ml_arm_pid_instance_q15Object *)S; + + arm_pid_init_q15(selfS->instance,resetStateFlag); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_pid_reset_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_pid_instance_q15Object *selfS = (ml_arm_pid_instance_q15Object *)S; + + arm_pid_reset_q15(selfS->instance); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mult_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q7_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q7_t *pSrcB_converted=NULL; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pSrcB,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_mult_q7(pSrcA_converted,pSrcB_converted,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mult_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_mult_q15(pSrcA_converted,pSrcB_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mult_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_mult_q31(pSrcA_converted,pSrcB_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mult_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + float32_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + float32_t *pSrcB_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pSrcB,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_mult_f32(pSrcA_converted,pSrcB_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix2_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t fftLen; // input + uint32_t ifftFlag; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"Ohii",&S,&fftLen,&ifftFlag,&bitReverseFlag)) + { + + ml_arm_cfft_radix2_instance_q15Object *selfS = (ml_arm_cfft_radix2_instance_q15Object *)S; + + arm_status returnValue = arm_cfft_radix2_init_q15(selfS->instance,fftLen,(uint8_t)ifftFlag,(uint8_t)bitReverseFlag); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix2_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_cfft_radix2_instance_q15Object *selfS = (ml_arm_cfft_radix2_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + + arm_cfft_radix2_q15(selfS->instance,pSrc_converted); + FREEARGUMENT(pSrc_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix4_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t fftLen; // input + uint32_t ifftFlag; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"Ohii",&S,&fftLen,&ifftFlag,&bitReverseFlag)) + { + + ml_arm_cfft_radix4_instance_q15Object *selfS = (ml_arm_cfft_radix4_instance_q15Object *)S; + + arm_status returnValue = arm_cfft_radix4_init_q15(selfS->instance,fftLen,(uint8_t)ifftFlag,(uint8_t)bitReverseFlag); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix4_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_cfft_radix4_instance_q15Object *selfS = (ml_arm_cfft_radix4_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + + arm_cfft_radix4_q15(selfS->instance,pSrc_converted); + FREEARGUMENT(pSrc_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix2_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t fftLen; // input + uint32_t ifftFlag; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"Ohii",&S,&fftLen,&ifftFlag,&bitReverseFlag)) + { + + ml_arm_cfft_radix2_instance_q31Object *selfS = (ml_arm_cfft_radix2_instance_q31Object *)S; + + arm_status returnValue = arm_cfft_radix2_init_q31(selfS->instance,fftLen,(uint8_t)ifftFlag,(uint8_t)bitReverseFlag); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix2_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_cfft_radix2_instance_q31Object *selfS = (ml_arm_cfft_radix2_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + + arm_cfft_radix2_q31(selfS->instance,pSrc_converted); + FREEARGUMENT(pSrc_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix4_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_cfft_radix4_instance_q31Object *selfS = (ml_arm_cfft_radix4_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + + arm_cfft_radix4_q31(selfS->instance,pSrc_converted); + FREEARGUMENT(pSrc_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix4_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t fftLen; // input + uint32_t ifftFlag; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"Ohii",&S,&fftLen,&ifftFlag,&bitReverseFlag)) + { + + ml_arm_cfft_radix4_instance_q31Object *selfS = (ml_arm_cfft_radix4_instance_q31Object *)S; + + arm_status returnValue = arm_cfft_radix4_init_q31(selfS->instance,fftLen,(uint8_t)ifftFlag,(uint8_t)bitReverseFlag); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix2_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t fftLen; // input + uint32_t ifftFlag; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"Ohii",&S,&fftLen,&ifftFlag,&bitReverseFlag)) + { + + ml_arm_cfft_radix2_instance_f32Object *selfS = (ml_arm_cfft_radix2_instance_f32Object *)S; + + arm_status returnValue = arm_cfft_radix2_init_f32(selfS->instance,fftLen,(uint8_t)ifftFlag,(uint8_t)bitReverseFlag); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix2_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_cfft_radix2_instance_f32Object *selfS = (ml_arm_cfft_radix2_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + + arm_cfft_radix2_f32(selfS->instance,pSrc_converted); + FREEARGUMENT(pSrc_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix4_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t fftLen; // input + uint32_t ifftFlag; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"Ohii",&S,&fftLen,&ifftFlag,&bitReverseFlag)) + { + + ml_arm_cfft_radix4_instance_f32Object *selfS = (ml_arm_cfft_radix4_instance_f32Object *)S; + + arm_status returnValue = arm_cfft_radix4_init_f32(selfS->instance,fftLen,(uint8_t)ifftFlag,(uint8_t)bitReverseFlag); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_radix4_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_cfft_radix4_instance_f32Object *selfS = (ml_arm_cfft_radix4_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + + arm_cfft_radix4_f32(selfS->instance,pSrc_converted); + FREEARGUMENT(pSrc_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *p1=NULL; // input + q15_t *p1_converted=NULL; // input + uint32_t ifftFlag; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"OOii",&S,&p1,&ifftFlag,&bitReverseFlag)) + { + + ml_arm_cfft_instance_q15Object *selfS = (ml_arm_cfft_instance_q15Object *)S; + GETARGUMENT(p1,NPY_INT16,int16_t,int16_t); + + arm_cfft_q15(selfS->instance,p1_converted,(uint8_t)ifftFlag,(uint8_t)bitReverseFlag); + INT16ARRAY1(p1OBJ,2*selfS->instance->fftLen,p1_converted); + + PyObject *pythonResult = Py_BuildValue("O",p1OBJ); + + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *p1=NULL; // input + q31_t *p1_converted=NULL; // input + uint32_t ifftFlag; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"OOii",&S,&p1,&ifftFlag,&bitReverseFlag)) + { + + ml_arm_cfft_instance_q31Object *selfS = (ml_arm_cfft_instance_q31Object *)S; + GETARGUMENT(p1,NPY_INT32,int32_t,int32_t); + + arm_cfft_q31(selfS->instance,p1_converted,(uint8_t)ifftFlag,(uint8_t)bitReverseFlag); + INT32ARRAY1(p1OBJ,2*selfS->instance->fftLen,p1_converted); + + PyObject *pythonResult = Py_BuildValue("O",p1OBJ); + + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *p1=NULL; // input + float32_t *p1_converted=NULL; // input + uint32_t ifftFlag; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"OOii",&S,&p1,&ifftFlag,&bitReverseFlag)) + { + + ml_arm_cfft_instance_f32Object *selfS = (ml_arm_cfft_instance_f32Object *)S; + GETARGUMENT(p1,NPY_DOUBLE,double,float32_t); + + arm_cfft_f32(selfS->instance,p1_converted,(uint8_t)ifftFlag,(uint8_t)bitReverseFlag); + FLOATARRAY1(p1OBJ,2*selfS->instance->fftLen,p1_converted); + + PyObject *pythonResult = Py_BuildValue("O",p1OBJ); + + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t fftLenReal; // input + uint32_t ifftFlagR; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"Oiii",&S,&fftLenReal,&ifftFlagR,&bitReverseFlag)) + { + + ml_arm_rfft_instance_q15Object *selfS = (ml_arm_rfft_instance_q15Object *)S; + + arm_status returnValue = arm_rfft_init_q15(selfS->instance,fftLenReal,ifftFlagR,bitReverseFlag); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_rfft_instance_q15Object *selfS = (ml_arm_rfft_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + + pDst=PyMem_Malloc(sizeof(q15_t)*2*selfS->instance->fftLenReal); + + + arm_rfft_q15(selfS->instance,pSrc_converted,pDst); + INT16ARRAY1(pDstOBJ,2*selfS->instance->fftLenReal,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t fftLenReal; // input + uint32_t ifftFlagR; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"Oiii",&S,&fftLenReal,&ifftFlagR,&bitReverseFlag)) + { + + ml_arm_rfft_instance_q31Object *selfS = (ml_arm_rfft_instance_q31Object *)S; + + arm_status returnValue = arm_rfft_init_q31(selfS->instance,fftLenReal,ifftFlagR,bitReverseFlag); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_rfft_instance_q31Object *selfS = (ml_arm_rfft_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + + pDst=PyMem_Malloc(sizeof(q31_t)*2*selfS->instance->fftLenReal); + + + arm_rfft_q31(selfS->instance,pSrc_converted,pDst); + INT32ARRAY1(pDstOBJ,2*selfS->instance->fftLenReal,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *S_CFFT=NULL; // input + uint32_t fftLenReal; // input + uint32_t ifftFlagR; // input + uint32_t bitReverseFlag; // input + + if (PyArg_ParseTuple(args,"OOiii",&S,&S_CFFT,&fftLenReal,&ifftFlagR,&bitReverseFlag)) + { + + ml_arm_rfft_instance_f32Object *selfS = (ml_arm_rfft_instance_f32Object *)S; + ml_arm_cfft_radix4_instance_f32Object *selfS_CFFT = (ml_arm_cfft_radix4_instance_f32Object *)S_CFFT; + + arm_status returnValue = arm_rfft_init_f32(selfS->instance,selfS_CFFT->instance,fftLenReal,ifftFlagR,bitReverseFlag); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_rfft_instance_f32Object *selfS = (ml_arm_rfft_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + + pDst=PyMem_Malloc(sizeof(float32_t)*2*selfS->instance->fftLenReal); + + + arm_rfft_f32(selfS->instance,pSrc_converted,pDst); + FLOATARRAY1(pDstOBJ,2*selfS->instance->fftLenReal,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_fast_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t fftLen; // input + + if (PyArg_ParseTuple(args,"Oh",&S,&fftLen)) + { + + ml_arm_rfft_fast_instance_f32Object *selfS = (ml_arm_rfft_fast_instance_f32Object *)S; + + arm_status returnValue = arm_rfft_fast_init_f32(selfS->instance,fftLen); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_32_fast_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_rfft_fast_instance_f32Object *selfS = (ml_arm_rfft_fast_instance_f32Object *)S; + + arm_status returnValue = arm_rfft_32_fast_init_f32(selfS->instance); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_64_fast_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_rfft_fast_instance_f32Object *selfS = (ml_arm_rfft_fast_instance_f32Object *)S; + + arm_status returnValue = arm_rfft_64_fast_init_f32(selfS->instance); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_128_fast_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_rfft_fast_instance_f32Object *selfS = (ml_arm_rfft_fast_instance_f32Object *)S; + + arm_status returnValue = arm_rfft_128_fast_init_f32(selfS->instance); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_256_fast_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_rfft_fast_instance_f32Object *selfS = (ml_arm_rfft_fast_instance_f32Object *)S; + + arm_status returnValue = arm_rfft_256_fast_init_f32(selfS->instance); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_512_fast_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_rfft_fast_instance_f32Object *selfS = (ml_arm_rfft_fast_instance_f32Object *)S; + + arm_status returnValue = arm_rfft_512_fast_init_f32(selfS->instance); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_1024_fast_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_rfft_fast_instance_f32Object *selfS = (ml_arm_rfft_fast_instance_f32Object *)S; + + arm_status returnValue = arm_rfft_1024_fast_init_f32(selfS->instance); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_2048_fast_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_rfft_fast_instance_f32Object *selfS = (ml_arm_rfft_fast_instance_f32Object *)S; + + arm_status returnValue = arm_rfft_2048_fast_init_f32(selfS->instance); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_4096_fast_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + + if (PyArg_ParseTuple(args,"O",&S)) + { + + ml_arm_rfft_fast_instance_f32Object *selfS = (ml_arm_rfft_fast_instance_f32Object *)S; + + arm_status returnValue = arm_rfft_4096_fast_init_f32(selfS->instance); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rfft_fast_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *p=NULL; // input + float32_t *p_converted=NULL; // input + float32_t *pOut=NULL; // output + uint32_t ifftFlag; // input + + if (PyArg_ParseTuple(args,"OOi",&S,&p,&ifftFlag)) + { + + ml_arm_rfft_fast_instance_f32Object *selfS = (ml_arm_rfft_fast_instance_f32Object *)S; + GETARGUMENT(p,NPY_DOUBLE,double,float32_t); + + pOut=PyMem_Malloc(sizeof(float32_t)*2*selfS->instance->fftLenRFFT); + + + arm_rfft_fast_f32(selfS->instance,p_converted,pOut,(uint8_t)ifftFlag); + FLOATARRAY1(pOutOBJ,2*selfS->instance->fftLenRFFT,pOut); + + PyObject *pythonResult = Py_BuildValue("O",pOutOBJ); + + FREEARGUMENT(p_converted); + Py_DECREF(pOutOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_dct4_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *S_RFFT=NULL; // input + PyObject *S_CFFT=NULL; // input + uint16_t N; // input + uint16_t Nby2; // input + float32_t normalize; // input + + if (PyArg_ParseTuple(args,"OOOhhf",&S,&S_RFFT,&S_CFFT,&N,&Nby2,&normalize)) + { + + ml_arm_dct4_instance_f32Object *selfS = (ml_arm_dct4_instance_f32Object *)S; + ml_arm_rfft_instance_f32Object *selfS_RFFT = (ml_arm_rfft_instance_f32Object *)S_RFFT; + ml_arm_cfft_radix4_instance_f32Object *selfS_CFFT = (ml_arm_cfft_radix4_instance_f32Object *)S_CFFT; + uint32_t outputLength = selfS->instance->N ; + + arm_status returnValue = arm_dct4_init_f32(selfS->instance,selfS_RFFT->instance,selfS_CFFT->instance,N,Nby2,normalize); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_dct4_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + PyObject *pInlineBuffer=NULL; // input + float32_t *pInlineBuffer_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OOO",&S,&pState,&pInlineBuffer)) + { + + ml_arm_dct4_instance_f32Object *selfS = (ml_arm_dct4_instance_f32Object *)S; + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pInlineBuffer,NPY_DOUBLE,double,float32_t); + uint32_t outputLength = selfS->instance->N ; + + arm_dct4_f32(selfS->instance,pState_converted,pInlineBuffer_converted); + FLOATARRAY1(pInlineBufferOBJ,outputLength,pInlineBuffer_converted); + + PyObject *pythonResult = Py_BuildValue("O",pInlineBufferOBJ); + + FREEARGUMENT(pState_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_dct4_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *S_RFFT=NULL; // input + PyObject *S_CFFT=NULL; // input + uint16_t N; // input + uint16_t Nby2; // input + q31_t normalize; // input + + if (PyArg_ParseTuple(args,"OOOhhi",&S,&S_RFFT,&S_CFFT,&N,&Nby2,&normalize)) + { + + ml_arm_dct4_instance_q31Object *selfS = (ml_arm_dct4_instance_q31Object *)S; + ml_arm_rfft_instance_q31Object *selfS_RFFT = (ml_arm_rfft_instance_q31Object *)S_RFFT; + ml_arm_cfft_radix4_instance_q31Object *selfS_CFFT = (ml_arm_cfft_radix4_instance_q31Object *)S_CFFT; + uint32_t outputLength = selfS->instance->N ; + + arm_status returnValue = arm_dct4_init_q31(selfS->instance,selfS_RFFT->instance,selfS_CFFT->instance,N,Nby2,normalize); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_dct4_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pState=NULL; // input + q31_t *pState_converted=NULL; // input + PyObject *pInlineBuffer=NULL; // input + q31_t *pInlineBuffer_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OOO",&S,&pState,&pInlineBuffer)) + { + + ml_arm_dct4_instance_q31Object *selfS = (ml_arm_dct4_instance_q31Object *)S; + GETARGUMENT(pState,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pInlineBuffer,NPY_INT32,int32_t,int32_t); + uint32_t outputLength = selfS->instance->N ; + + arm_dct4_q31(selfS->instance,pState_converted,pInlineBuffer_converted); + INT32ARRAY1(pInlineBufferOBJ,outputLength,pInlineBuffer_converted); + + PyObject *pythonResult = Py_BuildValue("O",pInlineBufferOBJ); + + FREEARGUMENT(pState_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_dct4_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *S_RFFT=NULL; // input + PyObject *S_CFFT=NULL; // input + uint16_t N; // input + uint16_t Nby2; // input + q15_t normalize; // input + + if (PyArg_ParseTuple(args,"OOOhhh",&S,&S_RFFT,&S_CFFT,&N,&Nby2,&normalize)) + { + + ml_arm_dct4_instance_q15Object *selfS = (ml_arm_dct4_instance_q15Object *)S; + ml_arm_rfft_instance_q15Object *selfS_RFFT = (ml_arm_rfft_instance_q15Object *)S_RFFT; + ml_arm_cfft_radix4_instance_q15Object *selfS_CFFT = (ml_arm_cfft_radix4_instance_q15Object *)S_CFFT; + uint32_t outputLength = selfS->instance->N ; + + arm_status returnValue = arm_dct4_init_q15(selfS->instance,selfS_RFFT->instance,selfS_CFFT->instance,N,Nby2,normalize); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_dct4_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + PyObject *pInlineBuffer=NULL; // input + q15_t *pInlineBuffer_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OOO",&S,&pState,&pInlineBuffer)) + { + + ml_arm_dct4_instance_q15Object *selfS = (ml_arm_dct4_instance_q15Object *)S; + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pInlineBuffer,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = selfS->instance->N ; + + arm_dct4_q15(selfS->instance,pState_converted,pInlineBuffer_converted); + INT16ARRAY1(pInlineBufferOBJ,outputLength,pInlineBuffer_converted); + + PyObject *pythonResult = Py_BuildValue("O",pInlineBufferOBJ); + + FREEARGUMENT(pState_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_add_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + float32_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + float32_t *pSrcB_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pSrcB,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_add_f32(pSrcA_converted,pSrcB_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_add_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q7_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q7_t *pSrcB_converted=NULL; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pSrcB,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_add_q7(pSrcA_converted,pSrcB_converted,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_add_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_add_q15(pSrcA_converted,pSrcB_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_add_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_add_q31(pSrcA_converted,pSrcB_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sub_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + float32_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + float32_t *pSrcB_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pSrcB,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_sub_f32(pSrcA_converted,pSrcB_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sub_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q7_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q7_t *pSrcB_converted=NULL; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pSrcB,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_sub_q7(pSrcA_converted,pSrcB_converted,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sub_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_sub_q15(pSrcA_converted,pSrcB_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sub_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrcA ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_sub_q31(pSrcA_converted,pSrcB_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_scale_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t scale; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Of",&pSrc,&scale)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_scale_f32(pSrc_converted,scale,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_scale_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + int32_t scaleFract; // input + int32_t shift; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Oii",&pSrc,&scaleFract,&shift)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_scale_q7(pSrc_converted,(q7_t)scaleFract,(int8_t)shift,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_scale_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t scaleFract; // input + int32_t shift; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Ohi",&pSrc,&scaleFract,&shift)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_scale_q15(pSrc_converted,scaleFract,(int8_t)shift,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_scale_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t scaleFract; // input + int32_t shift; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Oii",&pSrc,&scaleFract,&shift)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_scale_q31(pSrc_converted,scaleFract,(int8_t)shift,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_abs_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_abs_q7(pSrc_converted,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_abs_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_abs_f32(pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_abs_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_abs_q15(pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_abs_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_abs_q31(pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_dot_prod_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + float32_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + float32_t *pSrcB_converted=NULL; // input + uint32_t blockSize; // input + float32_t *result=NULL; // output + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pSrcB,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrcA ; + + result=PyMem_Malloc(sizeof(float32_t)*1); + + + arm_dot_prod_f32(pSrcA_converted,pSrcB_converted,blockSize,result); + PyObject* resultOBJ=Py_BuildValue("f",*result); + + PyObject *pythonResult = Py_BuildValue("O",resultOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(resultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_dot_prod_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q7_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q7_t *pSrcB_converted=NULL; // input + uint32_t blockSize; // input + q31_t *result=NULL; // output + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pSrcB,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrcA ; + + result=PyMem_Malloc(sizeof(q31_t)*1); + + + arm_dot_prod_q7(pSrcA_converted,pSrcB_converted,blockSize,result); + PyObject* resultOBJ=Py_BuildValue("i",*result); + + PyObject *pythonResult = Py_BuildValue("O",resultOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(resultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_dot_prod_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t blockSize; // input + q63_t *result=NULL; // output + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrcA ; + + result=PyMem_Malloc(sizeof(q63_t)*1); + + + arm_dot_prod_q15(pSrcA_converted,pSrcB_converted,blockSize,result); + PyObject* resultOBJ=Py_BuildValue("L",*result); + + PyObject *pythonResult = Py_BuildValue("O",resultOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(resultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_dot_prod_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + uint32_t blockSize; // input + q63_t *result=NULL; // output + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrcA ; + + result=PyMem_Malloc(sizeof(q63_t)*1); + + + arm_dot_prod_q31(pSrcA_converted,pSrcB_converted,blockSize,result); + PyObject* resultOBJ=Py_BuildValue("L",*result); + + PyObject *pythonResult = Py_BuildValue("O",resultOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(resultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_shift_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + int32_t shiftBits; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Oi",&pSrc,&shiftBits)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_shift_q7(pSrc_converted,(int8_t)shiftBits,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_shift_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + int32_t shiftBits; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Oi",&pSrc,&shiftBits)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_shift_q15(pSrc_converted,(int8_t)shiftBits,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_shift_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + int32_t shiftBits; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Oi",&pSrc,&shiftBits)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_shift_q31(pSrc_converted,(int8_t)shiftBits,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_offset_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t offset; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Of",&pSrc,&offset)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_offset_f32(pSrc_converted,offset,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_offset_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + int32_t offset; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Oi",&pSrc,&offset)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_offset_q7(pSrc_converted,(q7_t)offset,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_offset_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t offset; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Oh",&pSrc,&offset)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_offset_q15(pSrc_converted,offset,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_offset_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t offset; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"Oi",&pSrc,&offset)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_offset_q31(pSrc_converted,offset,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_negate_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_negate_f32(pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_negate_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_negate_q7(pSrc_converted,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_negate_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_negate_q15(pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_negate_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_negate_q31(pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_copy_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_copy_f32(pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_copy_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_copy_q7(pSrc_converted,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_copy_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_copy_q15(pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_copy_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_copy_q31(pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + float32_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + float32_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + float32_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pSrcB,NPY_DOUBLE,double,float32_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(float32_t)*outputLength); + + + arm_conv_f32(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + FLOATARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_opt_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + PyObject *pScratch1=NULL; // input + q15_t *pScratch1_converted=NULL; // input + PyObject *pScratch2=NULL; // input + q15_t *pScratch2_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOiOO",&pSrcA,&srcALen,&pSrcB,&srcBLen,&pScratch1,&pScratch2)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch1,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch2,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_conv_opt_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,pScratch1_converted,pScratch2_converted); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratch1_converted); + FREEARGUMENT(pScratch2_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_conv_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_fast_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_conv_fast_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_fast_opt_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + PyObject *pScratch1=NULL; // input + q15_t *pScratch1_converted=NULL; // input + PyObject *pScratch2=NULL; // input + q15_t *pScratch2_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOiOO",&pSrcA,&srcALen,&pSrcB,&srcBLen,&pScratch1,&pScratch2)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch1,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch2,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_conv_fast_opt_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,pScratch1_converted,pScratch2_converted); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratch1_converted); + FREEARGUMENT(pScratch2_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q31_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q31_t)*outputLength); + + + arm_conv_q31(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + INT32ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_fast_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q31_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q31_t)*outputLength); + + + arm_conv_fast_q31(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + INT32ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_opt_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q7_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q7_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q7_t *pDst=NULL; // output + PyObject *pScratch1=NULL; // input + q15_t *pScratch1_converted=NULL; // input + PyObject *pScratch2=NULL; // input + q15_t *pScratch2_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOiOO",&pSrcA,&srcALen,&pSrcB,&srcBLen,&pScratch1,&pScratch2)) + { + + GETARGUMENT(pSrcA,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pSrcB,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pScratch1,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch2,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q7_t)*outputLength); + + + arm_conv_opt_q7(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,pScratch1_converted,pScratch2_converted); + INT8ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratch1_converted); + FREEARGUMENT(pScratch2_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q7_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q7_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q7_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pSrcB,NPY_BYTE,int8_t,q7_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q7_t)*outputLength); + + + arm_conv_q7(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + INT8ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_partial_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + float32_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + float32_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + float32_t *pDst=NULL; // output + uint32_t firstIndex; // input + uint32_t numPoints; // input + + if (PyArg_ParseTuple(args,"OiOiii",&pSrcA,&srcALen,&pSrcB,&srcBLen,&firstIndex,&numPoints)) + { + + GETARGUMENT(pSrcA,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pSrcB,NPY_DOUBLE,double,float32_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(float32_t)*outputLength); + + + arm_status returnValue = arm_conv_partial_f32(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,firstIndex,numPoints); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + FLOATARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_partial_opt_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + uint32_t firstIndex; // input + uint32_t numPoints; // input + PyObject *pScratch1=NULL; // input + q15_t *pScratch1_converted=NULL; // input + PyObject *pScratch2=NULL; // input + q15_t *pScratch2_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOiiiOO",&pSrcA,&srcALen,&pSrcB,&srcBLen,&firstIndex,&numPoints,&pScratch1,&pScratch2)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch1,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch2,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_status returnValue = arm_conv_partial_opt_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,firstIndex,numPoints,pScratch1_converted,pScratch2_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratch1_converted); + FREEARGUMENT(pScratch2_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_partial_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + uint32_t firstIndex; // input + uint32_t numPoints; // input + + if (PyArg_ParseTuple(args,"OiOiii",&pSrcA,&srcALen,&pSrcB,&srcBLen,&firstIndex,&numPoints)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_status returnValue = arm_conv_partial_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,firstIndex,numPoints); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_partial_fast_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + uint32_t firstIndex; // input + uint32_t numPoints; // input + + if (PyArg_ParseTuple(args,"OiOiii",&pSrcA,&srcALen,&pSrcB,&srcBLen,&firstIndex,&numPoints)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_status returnValue = arm_conv_partial_fast_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,firstIndex,numPoints); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_partial_fast_opt_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + uint32_t firstIndex; // input + uint32_t numPoints; // input + PyObject *pScratch1=NULL; // input + q15_t *pScratch1_converted=NULL; // input + PyObject *pScratch2=NULL; // input + q15_t *pScratch2_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOiiiOO",&pSrcA,&srcALen,&pSrcB,&srcBLen,&firstIndex,&numPoints,&pScratch1,&pScratch2)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch1,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch2,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_status returnValue = arm_conv_partial_fast_opt_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,firstIndex,numPoints,pScratch1_converted,pScratch2_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratch1_converted); + FREEARGUMENT(pScratch2_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_partial_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q31_t *pDst=NULL; // output + uint32_t firstIndex; // input + uint32_t numPoints; // input + + if (PyArg_ParseTuple(args,"OiOiii",&pSrcA,&srcALen,&pSrcB,&srcBLen,&firstIndex,&numPoints)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q31_t)*outputLength); + + + arm_status returnValue = arm_conv_partial_q31(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,firstIndex,numPoints); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + INT32ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_partial_fast_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q31_t *pDst=NULL; // output + uint32_t firstIndex; // input + uint32_t numPoints; // input + + if (PyArg_ParseTuple(args,"OiOiii",&pSrcA,&srcALen,&pSrcB,&srcBLen,&firstIndex,&numPoints)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q31_t)*outputLength); + + + arm_status returnValue = arm_conv_partial_fast_q31(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,firstIndex,numPoints); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + INT32ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_partial_opt_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q7_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q7_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q7_t *pDst=NULL; // output + uint32_t firstIndex; // input + uint32_t numPoints; // input + PyObject *pScratch1=NULL; // input + q15_t *pScratch1_converted=NULL; // input + PyObject *pScratch2=NULL; // input + q15_t *pScratch2_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOiiiOO",&pSrcA,&srcALen,&pSrcB,&srcBLen,&firstIndex,&numPoints,&pScratch1,&pScratch2)) + { + + GETARGUMENT(pSrcA,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pSrcB,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pScratch1,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch2,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q7_t)*outputLength); + + + arm_status returnValue = arm_conv_partial_opt_q7(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,firstIndex,numPoints,pScratch1_converted,pScratch2_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + INT8ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratch1_converted); + FREEARGUMENT(pScratch2_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_conv_partial_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q7_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q7_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q7_t *pDst=NULL; // output + uint32_t firstIndex; // input + uint32_t numPoints; // input + + if (PyArg_ParseTuple(args,"OiOiii",&pSrcA,&srcALen,&pSrcB,&srcBLen,&firstIndex,&numPoints)) + { + + GETARGUMENT(pSrcA,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pSrcB,NPY_BYTE,int8_t,q7_t); + uint32_t outputLength = srcALen + srcBLen - 1 ; + + pDst=PyMem_Malloc(sizeof(q7_t)*outputLength); + + + arm_status returnValue = arm_conv_partial_q7(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,firstIndex,numPoints); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + INT8ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pDstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_decimate_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_decimate_instance_f32Object *selfS = (ml_arm_fir_decimate_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_fir_decimate_f32(selfS->instance,pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_decimate_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + uint32_t M; // input + PyObject *pCoeffs=NULL; // input + float32_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhiOO",&S,&numTaps,&M,&pCoeffs,&pState)) + { + + ml_arm_fir_decimate_instance_f32Object *selfS = (ml_arm_fir_decimate_instance_f32Object *)S; + GETARGUMENT(pCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_status returnValue = arm_fir_decimate_init_f32(selfS->instance,numTaps,(uint8_t)M,pCoeffs_converted,pState_converted,blockSize); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_decimate_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_decimate_instance_q15Object *selfS = (ml_arm_fir_decimate_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_fir_decimate_q15(selfS->instance,pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_decimate_fast_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_decimate_instance_q15Object *selfS = (ml_arm_fir_decimate_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_fir_decimate_fast_q15(selfS->instance,pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_decimate_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + uint32_t M; // input + PyObject *pCoeffs=NULL; // input + q15_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhiOO",&S,&numTaps,&M,&pCoeffs,&pState)) + { + + ml_arm_fir_decimate_instance_q15Object *selfS = (ml_arm_fir_decimate_instance_q15Object *)S; + GETARGUMENT(pCoeffs,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_status returnValue = arm_fir_decimate_init_q15(selfS->instance,numTaps,(uint8_t)M,pCoeffs_converted,pState_converted,blockSize); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_decimate_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_decimate_instance_q31Object *selfS = (ml_arm_fir_decimate_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_fir_decimate_q31(selfS->instance,pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_decimate_fast_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_decimate_instance_q31Object *selfS = (ml_arm_fir_decimate_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_fir_decimate_fast_q31(selfS->instance,pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_decimate_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + uint32_t M; // input + PyObject *pCoeffs=NULL; // input + q31_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q31_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhiOO",&S,&numTaps,&M,&pCoeffs,&pState)) + { + + ml_arm_fir_decimate_instance_q31Object *selfS = (ml_arm_fir_decimate_instance_q31Object *)S; + GETARGUMENT(pCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pState,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_status returnValue = arm_fir_decimate_init_q31(selfS->instance,numTaps,(uint8_t)M,pCoeffs_converted,pState_converted,blockSize); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_interpolate_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_interpolate_instance_q15Object *selfS = (ml_arm_fir_interpolate_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_fir_interpolate_q15(selfS->instance,pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_interpolate_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t L; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q15_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OihOO",&S,&L,&numTaps,&pCoeffs,&pState)) + { + + ml_arm_fir_interpolate_instance_q15Object *selfS = (ml_arm_fir_interpolate_instance_q15Object *)S; + GETARGUMENT(pCoeffs,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_status returnValue = arm_fir_interpolate_init_q15(selfS->instance,(uint8_t)L,numTaps,pCoeffs_converted,pState_converted,blockSize); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_interpolate_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_interpolate_instance_q31Object *selfS = (ml_arm_fir_interpolate_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_fir_interpolate_q31(selfS->instance,pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_interpolate_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t L; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q31_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q31_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OihOO",&S,&L,&numTaps,&pCoeffs,&pState)) + { + + ml_arm_fir_interpolate_instance_q31Object *selfS = (ml_arm_fir_interpolate_instance_q31Object *)S; + GETARGUMENT(pCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pState,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_status returnValue = arm_fir_interpolate_init_q31(selfS->instance,(uint8_t)L,numTaps,pCoeffs_converted,pState_converted,blockSize); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_interpolate_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_interpolate_instance_f32Object *selfS = (ml_arm_fir_interpolate_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_fir_interpolate_f32(selfS->instance,pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_interpolate_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t L; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + float32_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OihOO",&S,&L,&numTaps,&pCoeffs,&pState)) + { + + ml_arm_fir_interpolate_instance_f32Object *selfS = (ml_arm_fir_interpolate_instance_f32Object *)S; + GETARGUMENT(pCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_status returnValue = arm_fir_interpolate_init_f32(selfS->instance,(uint8_t)L,numTaps,pCoeffs_converted,pState_converted,blockSize); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cas_df1_32x64_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + arm_biquad_cas_df1_32x64_ins_q31 *S_converted=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_biquad_cas_df1_32x64_q31(S_converted,pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cas_df1_32x64_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + arm_biquad_cas_df1_32x64_ins_q31 *S_converted=NULL; // input + uint32_t numStages; // input + PyObject *pCoeffs=NULL; // input + q31_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q63_t *pState_converted=NULL; // input + uint32_t postShift; // input + + if (PyArg_ParseTuple(args,"OiOOi",&S,&numStages,&pCoeffs,&pState,&postShift)) + { + + GETARGUMENT(pCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pState,NPY_INT64,q63_t,q63_t); + + arm_biquad_cas_df1_32x64_init_q31(S_converted,(uint8_t)numStages,pCoeffs_converted,pState_converted,(uint8_t)postShift); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df2T_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_biquad_cascade_df2T_instance_f32Object *selfS = (ml_arm_biquad_cascade_df2T_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_biquad_cascade_df2T_f32(selfS->instance,pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_stereo_df2T_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_biquad_cascade_stereo_df2T_instance_f32Object *selfS = (ml_arm_biquad_cascade_stereo_df2T_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_biquad_cascade_stereo_df2T_f32(selfS->instance,pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df2T_f64(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float64_t *pSrc_converted=NULL; // input + float64_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_biquad_cascade_df2T_instance_f64Object *selfS = (ml_arm_biquad_cascade_df2T_instance_f64Object *)S; + GETARGUMENT(pSrc,NPY_FLOAT64,float64_t,float64_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float64_t)*blockSize); + + + arm_biquad_cascade_df2T_f64(selfS->instance,pSrc_converted,pDst,blockSize); + FLOAT64ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df2T_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t numStages; // input + PyObject *pCoeffs=NULL; // input + float32_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOO",&S,&numStages,&pCoeffs,&pState)) + { + + ml_arm_biquad_cascade_df2T_instance_f32Object *selfS = (ml_arm_biquad_cascade_df2T_instance_f32Object *)S; + GETARGUMENT(pCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + + arm_biquad_cascade_df2T_init_f32(selfS->instance,(uint8_t)numStages,pCoeffs_converted,pState_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_stereo_df2T_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t numStages; // input + PyObject *pCoeffs=NULL; // input + float32_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOO",&S,&numStages,&pCoeffs,&pState)) + { + + ml_arm_biquad_cascade_stereo_df2T_instance_f32Object *selfS = (ml_arm_biquad_cascade_stereo_df2T_instance_f32Object *)S; + GETARGUMENT(pCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + + arm_biquad_cascade_stereo_df2T_init_f32(selfS->instance,(uint8_t)numStages,pCoeffs_converted,pState_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_biquad_cascade_df2T_init_f64(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint32_t numStages; // input + PyObject *pCoeffs=NULL; // input + float64_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float64_t *pState_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOO",&S,&numStages,&pCoeffs,&pState)) + { + + ml_arm_biquad_cascade_df2T_instance_f64Object *selfS = (ml_arm_biquad_cascade_df2T_instance_f64Object *)S; + GETARGUMENT(pCoeffs,NPY_FLOAT64,float64_t,float64_t); + GETARGUMENT(pState,NPY_FLOAT64,float64_t,float64_t); + + arm_biquad_cascade_df2T_init_f64(selfS->instance,(uint8_t)numStages,pCoeffs_converted,pState_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_lattice_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numStages; // input + PyObject *pCoeffs=NULL; // input + q15_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OhOO",&S,&numStages,&pCoeffs,&pState)) + { + + ml_arm_fir_lattice_instance_q15Object *selfS = (ml_arm_fir_lattice_instance_q15Object *)S; + GETARGUMENT(pCoeffs,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + + arm_fir_lattice_init_q15(selfS->instance,numStages,pCoeffs_converted,pState_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_lattice_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_lattice_instance_q15Object *selfS = (ml_arm_fir_lattice_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_fir_lattice_q15(selfS->instance,pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_lattice_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numStages; // input + PyObject *pCoeffs=NULL; // input + q31_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q31_t *pState_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OhOO",&S,&numStages,&pCoeffs,&pState)) + { + + ml_arm_fir_lattice_instance_q31Object *selfS = (ml_arm_fir_lattice_instance_q31Object *)S; + GETARGUMENT(pCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pState,NPY_INT32,int32_t,int32_t); + + arm_fir_lattice_init_q31(selfS->instance,numStages,pCoeffs_converted,pState_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_lattice_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_lattice_instance_q31Object *selfS = (ml_arm_fir_lattice_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_fir_lattice_q31(selfS->instance,pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_lattice_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numStages; // input + PyObject *pCoeffs=NULL; // input + float32_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OhOO",&S,&numStages,&pCoeffs,&pState)) + { + + ml_arm_fir_lattice_instance_f32Object *selfS = (ml_arm_fir_lattice_instance_f32Object *)S; + GETARGUMENT(pCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + + arm_fir_lattice_init_f32(selfS->instance,numStages,pCoeffs_converted,pState_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_lattice_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_fir_lattice_instance_f32Object *selfS = (ml_arm_fir_lattice_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_fir_lattice_f32(selfS->instance,pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_iir_lattice_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_iir_lattice_instance_f32Object *selfS = (ml_arm_iir_lattice_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_iir_lattice_f32(selfS->instance,pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_iir_lattice_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numStages; // input + PyObject *pkCoeffs=NULL; // input + float32_t *pkCoeffs_converted=NULL; // input + PyObject *pvCoeffs=NULL; // input + float32_t *pvCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOOO",&S,&numStages,&pkCoeffs,&pvCoeffs,&pState)) + { + + ml_arm_iir_lattice_instance_f32Object *selfS = (ml_arm_iir_lattice_instance_f32Object *)S; + GETARGUMENT(pkCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pvCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepkCoeffs ; + + arm_iir_lattice_init_f32(selfS->instance,numStages,pkCoeffs_converted,pvCoeffs_converted,pState_converted,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_iir_lattice_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_iir_lattice_instance_q31Object *selfS = (ml_arm_iir_lattice_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_iir_lattice_q31(selfS->instance,pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_iir_lattice_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numStages; // input + PyObject *pkCoeffs=NULL; // input + q31_t *pkCoeffs_converted=NULL; // input + PyObject *pvCoeffs=NULL; // input + q31_t *pvCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q31_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOOO",&S,&numStages,&pkCoeffs,&pvCoeffs,&pState)) + { + + ml_arm_iir_lattice_instance_q31Object *selfS = (ml_arm_iir_lattice_instance_q31Object *)S; + GETARGUMENT(pkCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pvCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pState,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepkCoeffs ; + + arm_iir_lattice_init_q31(selfS->instance,numStages,pkCoeffs_converted,pvCoeffs_converted,pState_converted,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_iir_lattice_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OO",&S,&pSrc)) + { + + ml_arm_iir_lattice_instance_q15Object *selfS = (ml_arm_iir_lattice_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_iir_lattice_q15(selfS->instance,pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_iir_lattice_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numStages; // input + PyObject *pkCoeffs=NULL; // input + q15_t *pkCoeffs_converted=NULL; // input + PyObject *pvCoeffs=NULL; // input + q15_t *pvCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOOO",&S,&numStages,&pkCoeffs,&pvCoeffs,&pState)) + { + + ml_arm_iir_lattice_instance_q15Object *selfS = (ml_arm_iir_lattice_instance_q15Object *)S; + GETARGUMENT(pkCoeffs,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pvCoeffs,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepkCoeffs ; + + arm_iir_lattice_init_q15(selfS->instance,numStages,pkCoeffs_converted,pvCoeffs_converted,pState_converted,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t fftLen; // input + + if (PyArg_ParseTuple(args,"Oh",&S,&fftLen)) + { + + ml_arm_cfft_instance_f32Object *selfS = (ml_arm_cfft_instance_f32Object *)S; + + arm_status returnValue = arm_cfft_init_f32(selfS->instance,fftLen); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t fftLen; // input + + if (PyArg_ParseTuple(args,"Oh",&S,&fftLen)) + { + + ml_arm_cfft_instance_q31Object *selfS = (ml_arm_cfft_instance_q31Object *)S; + + arm_status returnValue = arm_cfft_init_q31(selfS->instance,fftLen); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cfft_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t fftLen; // input + + if (PyArg_ParseTuple(args,"Oh",&S,&fftLen)) + { + + ml_arm_cfft_instance_q15Object *selfS = (ml_arm_cfft_instance_q15Object *)S; + + arm_status returnValue = arm_cfft_init_q15(selfS->instance,fftLen); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + PyObject *pRef=NULL; // input + float32_t *pRef_converted=NULL; // input + float32_t *pOut=NULL; // output + PyObject *pErr=NULL; // input + float32_t *pErr_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OOOO",&S,&pSrc,&pRef,&pErr)) + { + + ml_arm_lms_instance_f32Object *selfS = (ml_arm_lms_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pRef,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pErr,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pOut=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_lms_f32(selfS->instance,pSrc_converted,pRef_converted,pOut,pErr_converted,blockSize); + FLOATARRAY1(pOutOBJ,blockSize,pOut); + + PyObject *pythonResult = Py_BuildValue("O",pOutOBJ); + + FREEARGUMENT(pSrc_converted); + FREEARGUMENT(pRef_converted); + Py_DECREF(pOutOBJ); + FREEARGUMENT(pErr_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + float32_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + float32_t mu; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOOf",&S,&numTaps,&pCoeffs,&pState,&mu)) + { + + ml_arm_lms_instance_f32Object *selfS = (ml_arm_lms_instance_f32Object *)S; + GETARGUMENT(pCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1 ; + + arm_lms_init_f32(selfS->instance,numTaps,pCoeffs_converted,pState_converted,mu,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q15_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + q15_t mu; // input + uint32_t blockSize; // input + uint32_t postShift; // input + + if (PyArg_ParseTuple(args,"OhOOhi",&S,&numTaps,&pCoeffs,&pState,&mu,&postShift)) + { + + ml_arm_lms_instance_q15Object *selfS = (ml_arm_lms_instance_q15Object *)S; + GETARGUMENT(pCoeffs,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepState - arraySizepCoeffs + 1 ; + + arm_lms_init_q15(selfS->instance,numTaps,pCoeffs_converted,pState_converted,mu,blockSize,postShift); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + PyObject *pRef=NULL; // input + q15_t *pRef_converted=NULL; // input + q15_t *pOut=NULL; // output + PyObject *pErr=NULL; // input + q15_t *pErr_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OOOO",&S,&pSrc,&pRef,&pErr)) + { + + ml_arm_lms_instance_q15Object *selfS = (ml_arm_lms_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pRef,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pErr,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pOut=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_lms_q15(selfS->instance,pSrc_converted,pRef_converted,pOut,pErr_converted,blockSize); + INT16ARRAY1(pOutOBJ,blockSize,pOut); + + PyObject *pythonResult = Py_BuildValue("O",pOutOBJ); + + FREEARGUMENT(pSrc_converted); + FREEARGUMENT(pRef_converted); + Py_DECREF(pOutOBJ); + FREEARGUMENT(pErr_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + PyObject *pRef=NULL; // input + q31_t *pRef_converted=NULL; // input + q31_t *pOut=NULL; // output + PyObject *pErr=NULL; // input + q31_t *pErr_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OOOO",&S,&pSrc,&pRef,&pErr)) + { + + ml_arm_lms_instance_q31Object *selfS = (ml_arm_lms_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pRef,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pErr,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pOut=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_lms_q31(selfS->instance,pSrc_converted,pRef_converted,pOut,pErr_converted,blockSize); + INT32ARRAY1(pOutOBJ,blockSize,pOut); + + PyObject *pythonResult = Py_BuildValue("O",pOutOBJ); + + FREEARGUMENT(pSrc_converted); + FREEARGUMENT(pRef_converted); + Py_DECREF(pOutOBJ); + FREEARGUMENT(pErr_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q31_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q31_t *pState_converted=NULL; // input + q31_t mu; // input + uint32_t blockSize; // input + uint32_t postShift; // input + + if (PyArg_ParseTuple(args,"OhOOii",&S,&numTaps,&pCoeffs,&pState,&mu,&postShift)) + { + + ml_arm_lms_instance_q31Object *selfS = (ml_arm_lms_instance_q31Object *)S; + GETARGUMENT(pCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pState,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1 ; + + arm_lms_init_q31(selfS->instance,numTaps,pCoeffs_converted,pState_converted,mu,blockSize,postShift); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_norm_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + PyObject *pRef=NULL; // input + float32_t *pRef_converted=NULL; // input + float32_t *pOut=NULL; // output + PyObject *pErr=NULL; // input + float32_t *pErr_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OOOO",&S,&pSrc,&pRef,&pErr)) + { + + ml_arm_lms_norm_instance_f32Object *selfS = (ml_arm_lms_norm_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pRef,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pErr,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pOut=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_lms_norm_f32(selfS->instance,pSrc_converted,pRef_converted,pOut,pErr_converted,blockSize); + FLOATARRAY1(pOutOBJ,blockSize,pOut); + + PyObject *pythonResult = Py_BuildValue("O",pOutOBJ); + + FREEARGUMENT(pSrc_converted); + FREEARGUMENT(pRef_converted); + Py_DECREF(pOutOBJ); + FREEARGUMENT(pErr_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_norm_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + float32_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + float32_t mu; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOOf",&S,&numTaps,&pCoeffs,&pState,&mu)) + { + + ml_arm_lms_norm_instance_f32Object *selfS = (ml_arm_lms_norm_instance_f32Object *)S; + GETARGUMENT(pCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1 ; + + arm_lms_norm_init_f32(selfS->instance,numTaps,pCoeffs_converted,pState_converted,mu,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_norm_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + PyObject *pRef=NULL; // input + q31_t *pRef_converted=NULL; // input + q31_t *pOut=NULL; // output + PyObject *pErr=NULL; // input + q31_t *pErr_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OOOO",&S,&pSrc,&pRef,&pErr)) + { + + ml_arm_lms_norm_instance_q31Object *selfS = (ml_arm_lms_norm_instance_q31Object *)S; + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pRef,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pErr,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pOut=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_lms_norm_q31(selfS->instance,pSrc_converted,pRef_converted,pOut,pErr_converted,blockSize); + INT32ARRAY1(pOutOBJ,blockSize,pOut); + + PyObject *pythonResult = Py_BuildValue("O",pOutOBJ); + + FREEARGUMENT(pSrc_converted); + FREEARGUMENT(pRef_converted); + Py_DECREF(pOutOBJ); + FREEARGUMENT(pErr_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_norm_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q31_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q31_t *pState_converted=NULL; // input + q31_t mu; // input + uint32_t blockSize; // input + uint32_t postShift; // input + + if (PyArg_ParseTuple(args,"OhOOii",&S,&numTaps,&pCoeffs,&pState,&mu,&postShift)) + { + + ml_arm_lms_norm_instance_q31Object *selfS = (ml_arm_lms_norm_instance_q31Object *)S; + GETARGUMENT(pCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pState,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1 ; + + arm_lms_norm_init_q31(selfS->instance,numTaps,pCoeffs_converted,pState_converted,mu,blockSize,(uint8_t)postShift); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_norm_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + PyObject *pRef=NULL; // input + q15_t *pRef_converted=NULL; // input + q15_t *pOut=NULL; // output + PyObject *pErr=NULL; // input + q15_t *pErr_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OOOO",&S,&pSrc,&pRef,&pErr)) + { + + ml_arm_lms_norm_instance_q15Object *selfS = (ml_arm_lms_norm_instance_q15Object *)S; + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pRef,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pErr,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pOut=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_lms_norm_q15(selfS->instance,pSrc_converted,pRef_converted,pOut,pErr_converted,blockSize); + INT16ARRAY1(pOutOBJ,blockSize,pOut); + + PyObject *pythonResult = Py_BuildValue("O",pOutOBJ); + + FREEARGUMENT(pSrc_converted); + FREEARGUMENT(pRef_converted); + Py_DECREF(pOutOBJ); + FREEARGUMENT(pErr_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_lms_norm_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q15_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + q15_t mu; // input + uint32_t blockSize; // input + uint32_t postShift; // input + + if (PyArg_ParseTuple(args,"OhOOhi",&S,&numTaps,&pCoeffs,&pState,&mu,&postShift)) + { + + ml_arm_lms_norm_instance_q15Object *selfS = (ml_arm_lms_norm_instance_q15Object *)S; + GETARGUMENT(pCoeffs,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepState - arraySizepCoeffs + 1 ; + + arm_lms_norm_init_q15(selfS->instance,numTaps,pCoeffs_converted,pState_converted,mu,blockSize,(uint8_t)postShift); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_correlate_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + float32_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + float32_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + float32_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pSrcB,NPY_DOUBLE,double,float32_t); + uint32_t outputLength = 2*MAX(srcALen,srcBLen) - 1 ; + + pDst=PyMem_Malloc(sizeof(float32_t)*outputLength); + + + arm_correlate_f32(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + FLOATARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_correlate_opt_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + PyObject *pScratch=NULL; // input + q15_t *pScratch_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOiO",&pSrcA,&srcALen,&pSrcB,&srcBLen,&pScratch)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = 2*MAX(srcALen,srcBLen) - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_correlate_opt_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,pScratch_converted); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratch_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_correlate_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = 2*MAX(srcALen,srcBLen) - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_correlate_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_correlate_fast_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = 2*MAX(srcALen,srcBLen) - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_correlate_fast_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_correlate_fast_opt_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q15_t *pDst=NULL; // output + PyObject *pScratch=NULL; // input + q15_t *pScratch_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOiO",&pSrcA,&srcALen,&pSrcB,&srcBLen,&pScratch)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = 2*MAX(srcALen,srcBLen) - 1 ; + + pDst=PyMem_Malloc(sizeof(q15_t)*outputLength); + + + arm_correlate_fast_opt_q15(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,pScratch_converted); + INT16ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratch_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_correlate_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q31_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + uint32_t outputLength = 2*MAX(srcALen,srcBLen) - 1 ; + + pDst=PyMem_Malloc(sizeof(q31_t)*outputLength); + + + arm_correlate_q31(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + INT32ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_correlate_fast_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q31_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + uint32_t outputLength = 2*MAX(srcALen,srcBLen) - 1 ; + + pDst=PyMem_Malloc(sizeof(q31_t)*outputLength); + + + arm_correlate_fast_q31(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + INT32ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_correlate_opt_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q7_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q7_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q7_t *pDst=NULL; // output + PyObject *pScratch1=NULL; // input + q15_t *pScratch1_converted=NULL; // input + PyObject *pScratch2=NULL; // input + q15_t *pScratch2_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OiOiOO",&pSrcA,&srcALen,&pSrcB,&srcBLen,&pScratch1,&pScratch2)) + { + + GETARGUMENT(pSrcA,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pSrcB,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pScratch1,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pScratch2,NPY_INT16,int16_t,int16_t); + uint32_t outputLength = 2*MAX(srcALen,srcBLen) - 1 ; + + pDst=PyMem_Malloc(sizeof(q7_t)*outputLength); + + + arm_correlate_opt_q7(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst,pScratch1_converted,pScratch2_converted); + INT8ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratch1_converted); + FREEARGUMENT(pScratch2_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_correlate_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q7_t *pSrcA_converted=NULL; // input + uint32_t srcALen; // input + PyObject *pSrcB=NULL; // input + q7_t *pSrcB_converted=NULL; // input + uint32_t srcBLen; // input + q7_t *pDst=NULL; // output + + if (PyArg_ParseTuple(args,"OiOi",&pSrcA,&srcALen,&pSrcB,&srcBLen)) + { + + GETARGUMENT(pSrcA,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pSrcB,NPY_BYTE,int8_t,q7_t); + uint32_t outputLength = 2*MAX(srcALen,srcBLen) - 1 ; + + pDst=PyMem_Malloc(sizeof(q7_t)*outputLength); + + + arm_correlate_q7(pSrcA_converted,srcALen,pSrcB_converted,srcBLen,pDst); + INT8ARRAY1(pDstOBJ,outputLength,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_sparse_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + PyObject *pScratchIn=NULL; // input + float32_t *pScratchIn_converted=NULL; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OOO",&S,&pSrc,&pScratchIn)) + { + + ml_arm_fir_sparse_instance_f32Object *selfS = (ml_arm_fir_sparse_instance_f32Object *)S; + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pScratchIn,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_fir_sparse_f32(selfS->instance,pSrc_converted,pDst,pScratchIn_converted,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + FREEARGUMENT(pScratchIn_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_sparse_init_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + float32_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + float32_t *pState_converted=NULL; // input + PyObject *pTapDelay=NULL; // input + int32_t *pTapDelay_converted=NULL; // input + uint16_t maxDelay; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOOOh",&S,&numTaps,&pCoeffs,&pState,&pTapDelay,&maxDelay)) + { + + ml_arm_fir_sparse_instance_f32Object *selfS = (ml_arm_fir_sparse_instance_f32Object *)S; + GETARGUMENT(pCoeffs,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pState,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pTapDelay,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_fir_sparse_init_f32(selfS->instance,numTaps,pCoeffs_converted,pState_converted,pTapDelay_converted,maxDelay,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_sparse_init_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q31_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q31_t *pState_converted=NULL; // input + PyObject *pTapDelay=NULL; // input + int32_t *pTapDelay_converted=NULL; // input + uint16_t maxDelay; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOOOh",&S,&numTaps,&pCoeffs,&pState,&pTapDelay,&maxDelay)) + { + + ml_arm_fir_sparse_instance_q31Object *selfS = (ml_arm_fir_sparse_instance_q31Object *)S; + GETARGUMENT(pCoeffs,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pState,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pTapDelay,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_fir_sparse_init_q31(selfS->instance,numTaps,pCoeffs_converted,pState_converted,pTapDelay_converted,maxDelay,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_sparse_init_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q15_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q15_t *pState_converted=NULL; // input + PyObject *pTapDelay=NULL; // input + int32_t *pTapDelay_converted=NULL; // input + uint16_t maxDelay; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOOOh",&S,&numTaps,&pCoeffs,&pState,&pTapDelay,&maxDelay)) + { + + ml_arm_fir_sparse_instance_q15Object *selfS = (ml_arm_fir_sparse_instance_q15Object *)S; + GETARGUMENT(pCoeffs,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pState,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pTapDelay,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_fir_sparse_init_q15(selfS->instance,numTaps,pCoeffs_converted,pState_converted,pTapDelay_converted,maxDelay,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_fir_sparse_init_q7(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + uint16_t numTaps; // input + PyObject *pCoeffs=NULL; // input + q7_t *pCoeffs_converted=NULL; // input + PyObject *pState=NULL; // input + q7_t *pState_converted=NULL; // input + PyObject *pTapDelay=NULL; // input + int32_t *pTapDelay_converted=NULL; // input + uint16_t maxDelay; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OhOOOh",&S,&numTaps,&pCoeffs,&pState,&pTapDelay,&maxDelay)) + { + + ml_arm_fir_sparse_instance_q7Object *selfS = (ml_arm_fir_sparse_instance_q7Object *)S; + GETARGUMENT(pCoeffs,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pState,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(pTapDelay,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepState - arraySizepCoeffs + 1; + + arm_fir_sparse_init_q7(selfS->instance,numTaps,pCoeffs_converted,pState_converted,pTapDelay_converted,maxDelay,blockSize); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sin_cos_f32(PyObject *obj, PyObject *args) +{ + + float32_t theta; // input + PyObject *pSinVal=NULL; // input + float32_t *pSinVal_converted=NULL; // input + PyObject *pCosVal=NULL; // input + float32_t *pCosVal_converted=NULL; // input + + if (PyArg_ParseTuple(args,"fOO",&theta,&pSinVal,&pCosVal)) + { + + GETARGUMENT(pSinVal,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pCosVal,NPY_DOUBLE,double,float32_t); + + arm_sin_cos_f32(theta,pSinVal_converted,pCosVal_converted); + FREEARGUMENT(pSinVal_converted); + FREEARGUMENT(pCosVal_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sin_cos_q31(PyObject *obj, PyObject *args) +{ + + q31_t theta; // input + PyObject *pSinVal=NULL; // input + q31_t *pSinVal_converted=NULL; // input + PyObject *pCosVal=NULL; // input + q31_t *pCosVal_converted=NULL; // input + + if (PyArg_ParseTuple(args,"iOO",&theta,&pSinVal,&pCosVal)) + { + + GETARGUMENT(pSinVal,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pCosVal,NPY_INT32,int32_t,int32_t); + + arm_sin_cos_q31(theta,pSinVal_converted,pCosVal_converted); + FREEARGUMENT(pSinVal_converted); + FREEARGUMENT(pCosVal_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_conj_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + numSamples = arraySizepSrc ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(float32_t)*2*numSamples); + + + arm_cmplx_conj_f32(pSrc_converted,pDst,numSamples); + FLOATARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_conj_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + numSamples = arraySizepSrc ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(q31_t)*2*numSamples); + + + arm_cmplx_conj_q31(pSrc_converted,pDst,numSamples); + INT32ARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_conj_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + numSamples = arraySizepSrc ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(q15_t)*2*numSamples); + + + arm_cmplx_conj_q15(pSrc_converted,pDst,numSamples); + INT16ARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mag_squared_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + numSamples = arraySizepSrc ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(float32_t)*2*numSamples); + + + arm_cmplx_mag_squared_f32(pSrc_converted,pDst,numSamples); + FLOATARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mag_squared_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + numSamples = arraySizepSrc ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(q31_t)*2*numSamples); + + + arm_cmplx_mag_squared_q31(pSrc_converted,pDst,numSamples); + INT32ARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mag_squared_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + numSamples = arraySizepSrc ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(q15_t)*2*numSamples); + + + arm_cmplx_mag_squared_q15(pSrc_converted,pDst,numSamples); + INT16ARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_pid_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + float32_t in; // input + + if (PyArg_ParseTuple(args,"Of",&S,&in)) + { + + ml_arm_pid_instance_f32Object *selfS = (ml_arm_pid_instance_f32Object *)S; + + float32_t returnValue = arm_pid_f32(selfS->instance,in); + PyObject* theReturnOBJ=Py_BuildValue("f",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_pid_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + q31_t in; // input + + if (PyArg_ParseTuple(args,"Oi",&S,&in)) + { + + ml_arm_pid_instance_q31Object *selfS = (ml_arm_pid_instance_q31Object *)S; + + q31_t returnValue = arm_pid_q31(selfS->instance,in); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_pid_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + q15_t in; // input + + if (PyArg_ParseTuple(args,"Oh",&S,&in)) + { + + ml_arm_pid_instance_q15Object *selfS = (ml_arm_pid_instance_q15Object *)S; + + q15_t returnValue = arm_pid_q15(selfS->instance,in); + PyObject* theReturnOBJ=Py_BuildValue("h",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_inverse_f32(PyObject *obj, PyObject *args) +{ + + PyObject *src=NULL; // input + arm_matrix_instance_f32 *src_converted=NULL; // input + + if (PyArg_ParseTuple(args,"O",&src)) + { + + arm_matrix_instance_f32 *src_converted = f32MatrixFromNumpy(src); + uint32_t row = src_converted->numCols ; + uint32_t column = src_converted->numRows ; + arm_matrix_instance_f32 *dst_converted = createf32Matrix(row,column); + + arm_status returnValue = arm_mat_inverse_f32(src_converted,dst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* dstOBJ=NumpyArrayFromf32Matrix(dst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,dstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(src_converted); + Py_DECREF(dstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mat_inverse_f64(PyObject *obj, PyObject *args) +{ + + PyObject *src=NULL; // input + arm_matrix_instance_f64 *src_converted=NULL; // input + + if (PyArg_ParseTuple(args,"O",&src)) + { + + arm_matrix_instance_f64 *src_converted = f64MatrixFromNumpy(src); + uint32_t row = src_converted->numCols ; + uint32_t column = src_converted->numRows ; + arm_matrix_instance_f64 *dst_converted = createf64Matrix(row,column); + + arm_status returnValue = arm_mat_inverse_f64(src_converted,dst_converted); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* dstOBJ=NumpyArrayFromf64Matrix(dst_converted); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,dstOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(src_converted); + Py_DECREF(dstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_clarke_f32(PyObject *obj, PyObject *args) +{ + + float32_t Ia; // input + float32_t Ib; // input + PyObject *pIalpha=NULL; // input + float32_t *pIalpha_converted=NULL; // input + PyObject *pIbeta=NULL; // input + float32_t *pIbeta_converted=NULL; // input + + if (PyArg_ParseTuple(args,"ffOO",&Ia,&Ib,&pIalpha,&pIbeta)) + { + + GETARGUMENT(pIalpha,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pIbeta,NPY_DOUBLE,double,float32_t); + + arm_clarke_f32(Ia,Ib,pIalpha_converted,pIbeta_converted); + FREEARGUMENT(pIalpha_converted); + FREEARGUMENT(pIbeta_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_clarke_q31(PyObject *obj, PyObject *args) +{ + + q31_t Ia; // input + q31_t Ib; // input + PyObject *pIalpha=NULL; // input + q31_t *pIalpha_converted=NULL; // input + PyObject *pIbeta=NULL; // input + q31_t *pIbeta_converted=NULL; // input + + if (PyArg_ParseTuple(args,"iiOO",&Ia,&Ib,&pIalpha,&pIbeta)) + { + + GETARGUMENT(pIalpha,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pIbeta,NPY_INT32,int32_t,int32_t); + + arm_clarke_q31(Ia,Ib,pIalpha_converted,pIbeta_converted); + FREEARGUMENT(pIalpha_converted); + FREEARGUMENT(pIbeta_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_q7_to_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_q7_to_q31(pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_inv_clarke_f32(PyObject *obj, PyObject *args) +{ + + float32_t Ialpha; // input + float32_t Ibeta; // input + PyObject *pIa=NULL; // input + float32_t *pIa_converted=NULL; // input + PyObject *pIb=NULL; // input + float32_t *pIb_converted=NULL; // input + + if (PyArg_ParseTuple(args,"ffOO",&Ialpha,&Ibeta,&pIa,&pIb)) + { + + GETARGUMENT(pIa,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pIb,NPY_DOUBLE,double,float32_t); + + arm_inv_clarke_f32(Ialpha,Ibeta,pIa_converted,pIb_converted); + FREEARGUMENT(pIa_converted); + FREEARGUMENT(pIb_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_inv_clarke_q31(PyObject *obj, PyObject *args) +{ + + q31_t Ialpha; // input + q31_t Ibeta; // input + PyObject *pIa=NULL; // input + q31_t *pIa_converted=NULL; // input + PyObject *pIb=NULL; // input + q31_t *pIb_converted=NULL; // input + + if (PyArg_ParseTuple(args,"iiOO",&Ialpha,&Ibeta,&pIa,&pIb)) + { + + GETARGUMENT(pIa,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pIb,NPY_INT32,int32_t,int32_t); + + arm_inv_clarke_q31(Ialpha,Ibeta,pIa_converted,pIb_converted); + FREEARGUMENT(pIa_converted); + FREEARGUMENT(pIb_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_q7_to_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_q7_to_q15(pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_park_f32(PyObject *obj, PyObject *args) +{ + + float32_t Ialpha; // input + float32_t Ibeta; // input + PyObject *pId=NULL; // input + float32_t *pId_converted=NULL; // input + PyObject *pIq=NULL; // input + float32_t *pIq_converted=NULL; // input + float32_t sinVal; // input + float32_t cosVal; // input + + if (PyArg_ParseTuple(args,"ffOOff",&Ialpha,&Ibeta,&pId,&pIq,&sinVal,&cosVal)) + { + + GETARGUMENT(pId,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pIq,NPY_DOUBLE,double,float32_t); + + arm_park_f32(Ialpha,Ibeta,pId_converted,pIq_converted,sinVal,cosVal); + FREEARGUMENT(pId_converted); + FREEARGUMENT(pIq_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_park_q31(PyObject *obj, PyObject *args) +{ + + q31_t Ialpha; // input + q31_t Ibeta; // input + PyObject *pId=NULL; // input + q31_t *pId_converted=NULL; // input + PyObject *pIq=NULL; // input + q31_t *pIq_converted=NULL; // input + q31_t sinVal; // input + q31_t cosVal; // input + + if (PyArg_ParseTuple(args,"iiOOii",&Ialpha,&Ibeta,&pId,&pIq,&sinVal,&cosVal)) + { + + GETARGUMENT(pId,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pIq,NPY_INT32,int32_t,int32_t); + + arm_park_q31(Ialpha,Ibeta,pId_converted,pIq_converted,sinVal,cosVal); + FREEARGUMENT(pId_converted); + FREEARGUMENT(pIq_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_q7_to_float(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_q7_to_float(pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_inv_park_f32(PyObject *obj, PyObject *args) +{ + + float32_t Id; // input + float32_t Iq; // input + PyObject *pIalpha=NULL; // input + float32_t *pIalpha_converted=NULL; // input + PyObject *pIbeta=NULL; // input + float32_t *pIbeta_converted=NULL; // input + float32_t sinVal; // input + float32_t cosVal; // input + + if (PyArg_ParseTuple(args,"ffOOff",&Id,&Iq,&pIalpha,&pIbeta,&sinVal,&cosVal)) + { + + GETARGUMENT(pIalpha,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pIbeta,NPY_DOUBLE,double,float32_t); + + arm_inv_park_f32(Id,Iq,pIalpha_converted,pIbeta_converted,sinVal,cosVal); + FREEARGUMENT(pIalpha_converted); + FREEARGUMENT(pIbeta_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_inv_park_q31(PyObject *obj, PyObject *args) +{ + + q31_t Id; // input + q31_t Iq; // input + PyObject *pIalpha=NULL; // input + q31_t *pIalpha_converted=NULL; // input + PyObject *pIbeta=NULL; // input + q31_t *pIbeta_converted=NULL; // input + q31_t sinVal; // input + q31_t cosVal; // input + + if (PyArg_ParseTuple(args,"iiOOii",&Id,&Iq,&pIalpha,&pIbeta,&sinVal,&cosVal)) + { + + GETARGUMENT(pIalpha,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pIbeta,NPY_INT32,int32_t,int32_t); + + arm_inv_park_q31(Id,Iq,pIalpha_converted,pIbeta_converted,sinVal,cosVal); + FREEARGUMENT(pIalpha_converted); + FREEARGUMENT(pIbeta_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_q31_to_float(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_q31_to_float(pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_linear_interp_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + float32_t x; // input + + if (PyArg_ParseTuple(args,"Of",&S,&x)) + { + + ml_arm_linear_interp_instance_f32Object *selfS = (ml_arm_linear_interp_instance_f32Object *)S; + + float32_t returnValue = arm_linear_interp_f32(selfS->instance,x); + PyObject* theReturnOBJ=Py_BuildValue("f",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_linear_interp_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pYData=NULL; // input + q31_t *pYData_converted=NULL; // input + q31_t x; // input + uint32_t nValues; // input + + if (PyArg_ParseTuple(args,"Oii",&pYData,&x,&nValues)) + { + + GETARGUMENT(pYData,NPY_INT32,int32_t,int32_t); + + q31_t returnValue = arm_linear_interp_q31(pYData_converted,x,nValues); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pYData_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_linear_interp_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pYData=NULL; // input + q15_t *pYData_converted=NULL; // input + q31_t x; // input + uint32_t nValues; // input + + if (PyArg_ParseTuple(args,"Oii",&pYData,&x,&nValues)) + { + + GETARGUMENT(pYData,NPY_INT16,int16_t,int16_t); + + q15_t returnValue = arm_linear_interp_q15(pYData_converted,x,nValues); + PyObject* theReturnOBJ=Py_BuildValue("h",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pYData_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_linear_interp_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pYData=NULL; // input + q7_t *pYData_converted=NULL; // input + q31_t x; // input + uint32_t nValues; // input + + if (PyArg_ParseTuple(args,"Oii",&pYData,&x,&nValues)) + { + + GETARGUMENT(pYData,NPY_BYTE,int8_t,q7_t); + + q7_t returnValue = arm_linear_interp_q7(pYData_converted,x,nValues); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + FREEARGUMENT(pYData_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sin_f32(PyObject *obj, PyObject *args) +{ + + float32_t x; // input + + if (PyArg_ParseTuple(args,"f",&x)) + { + + + float32_t returnValue = arm_sin_f32(x); + PyObject* theReturnOBJ=Py_BuildValue("f",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sin_q31(PyObject *obj, PyObject *args) +{ + + q31_t x; // input + + if (PyArg_ParseTuple(args,"i",&x)) + { + + + q31_t returnValue = arm_sin_q31(x); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sin_q15(PyObject *obj, PyObject *args) +{ + + q15_t x; // input + + if (PyArg_ParseTuple(args,"h",&x)) + { + + + q15_t returnValue = arm_sin_q15(x); + PyObject* theReturnOBJ=Py_BuildValue("h",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cos_f32(PyObject *obj, PyObject *args) +{ + + float32_t x; // input + + if (PyArg_ParseTuple(args,"f",&x)) + { + + + float32_t returnValue = arm_cos_f32(x); + PyObject* theReturnOBJ=Py_BuildValue("f",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cos_q31(PyObject *obj, PyObject *args) +{ + + q31_t x; // input + + if (PyArg_ParseTuple(args,"i",&x)) + { + + + q31_t returnValue = arm_cos_q31(x); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cos_q15(PyObject *obj, PyObject *args) +{ + + q15_t x; // input + + if (PyArg_ParseTuple(args,"h",&x)) + { + + + q15_t returnValue = arm_cos_q15(x); + PyObject* theReturnOBJ=Py_BuildValue("h",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sqrt_f32(PyObject *obj, PyObject *args) +{ + + float32_t in; // input + float32_t *pOut=NULL; // output + + if (PyArg_ParseTuple(args,"f",&in)) + { + + + pOut=PyMem_Malloc(sizeof(float32_t)*1); + + + arm_status returnValue = arm_sqrt_f32(in,pOut); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pOutOBJ=Py_BuildValue("f",*pOut); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pOutOBJ); + + Py_DECREF(theReturnOBJ); + Py_DECREF(pOutOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sqrt_q31(PyObject *obj, PyObject *args) +{ + + q31_t in; // input + q31_t *pOut=NULL; // output + + if (PyArg_ParseTuple(args,"i",&in)) + { + + + pOut=PyMem_Malloc(sizeof(q31_t)*1); + + + arm_status returnValue = arm_sqrt_q31(in,pOut); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pOutOBJ=Py_BuildValue("i",*pOut); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pOutOBJ); + + Py_DECREF(theReturnOBJ); + Py_DECREF(pOutOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_sqrt_q15(PyObject *obj, PyObject *args) +{ + + q15_t in; // input + q15_t *pOut=NULL; // output + + if (PyArg_ParseTuple(args,"h",&in)) + { + + + pOut=PyMem_Malloc(sizeof(q15_t)*1); + + + arm_status returnValue = arm_sqrt_q15(in,pOut); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + PyObject* pOutOBJ=Py_BuildValue("h",*pOut); + + PyObject *pythonResult = Py_BuildValue("OO",theReturnOBJ,pOutOBJ); + + Py_DECREF(theReturnOBJ); + Py_DECREF(pOutOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_circularWrite_f32(PyObject *obj, PyObject *args) +{ + + PyObject *circBuffer=NULL; // input + int32_t *circBuffer_converted=NULL; // input + int32_t L; // input + PyObject *writeOffset=NULL; // input + uint16_t *writeOffset_converted=NULL; // input + int32_t bufferInc; // input + PyObject *src=NULL; // input + int32_t *src_converted=NULL; // input + int32_t srcInc; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OiOiOi",&circBuffer,&L,&writeOffset,&bufferInc,&src,&srcInc)) + { + + GETARGUMENT(circBuffer,NPY_INT32,int32_t,int32_t); + GETARGUMENT(writeOffset,NPY_UINT16,uint16_t,uint16_t); + GETARGUMENT(src,NPY_INT32,int32_t,int32_t); + blockSize = arraySizecircBuffer ; + + arm_circularWrite_f32(circBuffer_converted,L,writeOffset_converted,bufferInc,src_converted,srcInc,blockSize); + FREEARGUMENT(circBuffer_converted); + FREEARGUMENT(writeOffset_converted); + FREEARGUMENT(src_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_circularWrite_q15(PyObject *obj, PyObject *args) +{ + + PyObject *circBuffer=NULL; // input + q15_t *circBuffer_converted=NULL; // input + int32_t L; // input + PyObject *writeOffset=NULL; // input + uint16_t *writeOffset_converted=NULL; // input + int32_t bufferInc; // input + PyObject *src=NULL; // input + q15_t *src_converted=NULL; // input + int32_t srcInc; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OiOiOi",&circBuffer,&L,&writeOffset,&bufferInc,&src,&srcInc)) + { + + GETARGUMENT(circBuffer,NPY_INT16,int16_t,int16_t); + GETARGUMENT(writeOffset,NPY_UINT16,uint16_t,uint16_t); + GETARGUMENT(src,NPY_INT16,int16_t,int16_t); + blockSize = arraySizecircBuffer ; + + arm_circularWrite_q15(circBuffer_converted,L,writeOffset_converted,bufferInc,src_converted,srcInc,blockSize); + FREEARGUMENT(circBuffer_converted); + FREEARGUMENT(writeOffset_converted); + FREEARGUMENT(src_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_circularWrite_q7(PyObject *obj, PyObject *args) +{ + + PyObject *circBuffer=NULL; // input + q7_t *circBuffer_converted=NULL; // input + int32_t L; // input + PyObject *writeOffset=NULL; // input + uint16_t *writeOffset_converted=NULL; // input + int32_t bufferInc; // input + PyObject *src=NULL; // input + q7_t *src_converted=NULL; // input + int32_t srcInc; // input + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"OiOiOi",&circBuffer,&L,&writeOffset,&bufferInc,&src,&srcInc)) + { + + GETARGUMENT(circBuffer,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(writeOffset,NPY_UINT16,uint16_t,uint16_t); + GETARGUMENT(src,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizecircBuffer ; + + arm_circularWrite_q7(circBuffer_converted,L,writeOffset_converted,bufferInc,src_converted,srcInc,blockSize); + FREEARGUMENT(circBuffer_converted); + FREEARGUMENT(writeOffset_converted); + FREEARGUMENT(src_converted); + Py_RETURN_NONE; + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_power_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q63_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q63_t)*1); + + + arm_power_q31(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("L",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_power_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + float32_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(float32_t)*1); + + + arm_power_f32(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("f",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_power_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q63_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q63_t)*1); + + + arm_power_q15(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("L",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_power_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q31_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q31_t)*1); + + + arm_power_q7(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("i",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mean_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q7_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q7_t)*1); + + + arm_mean_q7(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("i",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mean_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q15_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q15_t)*1); + + + arm_mean_q15(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("h",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mean_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q31_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q31_t)*1); + + + arm_mean_q31(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("i",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_mean_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + float32_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(float32_t)*1); + + + arm_mean_f32(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("f",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_var_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + float32_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(float32_t)*1); + + + arm_var_f32(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("f",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_var_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q31_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q31_t)*1); + + + arm_var_q31(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("i",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_var_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q15_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q15_t)*1); + + + arm_var_q15(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("h",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rms_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + float32_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(float32_t)*1); + + + arm_rms_f32(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("f",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rms_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q31_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q31_t)*1); + + + arm_rms_q31(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("i",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_rms_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q15_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q15_t)*1); + + + arm_rms_q15(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("h",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_std_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + float32_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(float32_t)*1); + + + arm_std_f32(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("f",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_std_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q31_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q31_t)*1); + + + arm_std_q31(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("i",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_std_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q15_t *pResult=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q15_t)*1); + + + arm_std_q15(pSrc_converted,blockSize,pResult); + PyObject* pResultOBJ=Py_BuildValue("h",*pResult); + + PyObject *pythonResult = Py_BuildValue("O",pResultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mag_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + numSamples = arraySizepSrc ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(float32_t)*2*numSamples); + + + arm_cmplx_mag_f32(pSrc_converted,pDst,numSamples); + FLOATARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mag_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + numSamples = arraySizepSrc ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(q31_t)*2*numSamples); + + + arm_cmplx_mag_q31(pSrc_converted,pDst,numSamples); + INT32ARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mag_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + numSamples = arraySizepSrc ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(q15_t)*2*numSamples); + + + arm_cmplx_mag_q15(pSrc_converted,pDst,numSamples); + INT16ARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_dot_prod_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + uint32_t numSamples; // input + q31_t *realResult=NULL; // output + q31_t *imagResult=NULL; // output + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + numSamples = arraySizepSrcA ; + numSamples = numSamples / 2; + + realResult=PyMem_Malloc(sizeof(q31_t)*1); + + + imagResult=PyMem_Malloc(sizeof(q31_t)*1); + + + arm_cmplx_dot_prod_q15(pSrcA_converted,pSrcB_converted,numSamples,realResult,imagResult); + PyObject* realResultOBJ=Py_BuildValue("i",*realResult); + PyObject* imagResultOBJ=Py_BuildValue("i",*imagResult); + + PyObject *pythonResult = Py_BuildValue("OO",realResultOBJ,imagResultOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(realResultOBJ); + Py_DECREF(imagResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_dot_prod_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + uint32_t numSamples; // input + q63_t *realResult=NULL; // output + q63_t *imagResult=NULL; // output + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + numSamples = arraySizepSrcA ; + numSamples = numSamples / 2; + + realResult=PyMem_Malloc(sizeof(q63_t)*1); + + + imagResult=PyMem_Malloc(sizeof(q63_t)*1); + + + arm_cmplx_dot_prod_q31(pSrcA_converted,pSrcB_converted,numSamples,realResult,imagResult); + PyObject* realResultOBJ=Py_BuildValue("L",*realResult); + PyObject* imagResultOBJ=Py_BuildValue("L",*imagResult); + + PyObject *pythonResult = Py_BuildValue("OO",realResultOBJ,imagResultOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(realResultOBJ); + Py_DECREF(imagResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_dot_prod_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + float32_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + float32_t *pSrcB_converted=NULL; // input + uint32_t numSamples; // input + float32_t *realResult=NULL; // output + float32_t *imagResult=NULL; // output + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pSrcB,NPY_DOUBLE,double,float32_t); + numSamples = arraySizepSrcA ; + numSamples = numSamples / 2; + + realResult=PyMem_Malloc(sizeof(float32_t)*1); + + + imagResult=PyMem_Malloc(sizeof(float32_t)*1); + + + arm_cmplx_dot_prod_f32(pSrcA_converted,pSrcB_converted,numSamples,realResult,imagResult); + PyObject* realResultOBJ=Py_BuildValue("f",*realResult); + PyObject* imagResultOBJ=Py_BuildValue("f",*imagResult); + + PyObject *pythonResult = Py_BuildValue("OO",realResultOBJ,imagResultOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(realResultOBJ); + Py_DECREF(imagResultOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mult_real_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcCmplx=NULL; // input + q15_t *pSrcCmplx_converted=NULL; // input + PyObject *pSrcReal=NULL; // input + q15_t *pSrcReal_converted=NULL; // input + q15_t *pCmplxDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcCmplx,&pSrcReal)) + { + + GETARGUMENT(pSrcCmplx,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcReal,NPY_INT16,int16_t,int16_t); + numSamples = arraySizepSrcCmplx ; + numSamples = numSamples / 2; + + pCmplxDst=PyMem_Malloc(sizeof(q15_t)*2*numSamples); + + + arm_cmplx_mult_real_q15(pSrcCmplx_converted,pSrcReal_converted,pCmplxDst,numSamples); + INT16ARRAY1(pCmplxDstOBJ,2*numSamples,pCmplxDst); + + PyObject *pythonResult = Py_BuildValue("O",pCmplxDstOBJ); + + FREEARGUMENT(pSrcCmplx_converted); + FREEARGUMENT(pSrcReal_converted); + Py_DECREF(pCmplxDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mult_real_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcCmplx=NULL; // input + q31_t *pSrcCmplx_converted=NULL; // input + PyObject *pSrcReal=NULL; // input + q31_t *pSrcReal_converted=NULL; // input + q31_t *pCmplxDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcCmplx,&pSrcReal)) + { + + GETARGUMENT(pSrcCmplx,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcReal,NPY_INT32,int32_t,int32_t); + numSamples = arraySizepSrcCmplx ; + numSamples = numSamples / 2; + + pCmplxDst=PyMem_Malloc(sizeof(q31_t)*2*numSamples); + + + arm_cmplx_mult_real_q31(pSrcCmplx_converted,pSrcReal_converted,pCmplxDst,numSamples); + INT32ARRAY1(pCmplxDstOBJ,2*numSamples,pCmplxDst); + + PyObject *pythonResult = Py_BuildValue("O",pCmplxDstOBJ); + + FREEARGUMENT(pSrcCmplx_converted); + FREEARGUMENT(pSrcReal_converted); + Py_DECREF(pCmplxDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mult_real_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcCmplx=NULL; // input + float32_t *pSrcCmplx_converted=NULL; // input + PyObject *pSrcReal=NULL; // input + float32_t *pSrcReal_converted=NULL; // input + float32_t *pCmplxDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcCmplx,&pSrcReal)) + { + + GETARGUMENT(pSrcCmplx,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pSrcReal,NPY_DOUBLE,double,float32_t); + numSamples = arraySizepSrcCmplx ; + numSamples = numSamples / 2; + + pCmplxDst=PyMem_Malloc(sizeof(float32_t)*2*numSamples); + + + arm_cmplx_mult_real_f32(pSrcCmplx_converted,pSrcReal_converted,pCmplxDst,numSamples); + FLOATARRAY1(pCmplxDstOBJ,2*numSamples,pCmplxDst); + + PyObject *pythonResult = Py_BuildValue("O",pCmplxDstOBJ); + + FREEARGUMENT(pSrcCmplx_converted); + FREEARGUMENT(pSrcReal_converted); + Py_DECREF(pCmplxDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_min_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q7_t *result=NULL; // output + PyObject *index=NULL; // input + uint32_t *index_converted=NULL; // input + + if (PyArg_ParseTuple(args,"OO",&pSrc,&index)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + GETARGUMENT(index,NPY_UINT32,uint32_t,uint32_t); + blockSize = arraySizepSrc ; + + result=PyMem_Malloc(sizeof(q7_t)*1); + + + arm_min_q7(pSrc_converted,blockSize,result,index_converted); + PyObject* resultOBJ=Py_BuildValue("i",*result); + + PyObject *pythonResult = Py_BuildValue("O",resultOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(resultOBJ); + FREEARGUMENT(index_converted); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_min_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q15_t *pResult=NULL; // output + uint32_t *pIndex=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q15_t)*1); + + + pIndex=PyMem_Malloc(sizeof(uint32_t)*1); + + + arm_min_q15(pSrc_converted,blockSize,pResult,pIndex); + PyObject* pResultOBJ=Py_BuildValue("h",*pResult); + PyObject* pIndexOBJ=Py_BuildValue("i",*pIndex); + + PyObject *pythonResult = Py_BuildValue("OO",pResultOBJ,pIndexOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + Py_DECREF(pIndexOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_min_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q31_t *pResult=NULL; // output + uint32_t *pIndex=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q31_t)*1); + + + pIndex=PyMem_Malloc(sizeof(uint32_t)*1); + + + arm_min_q31(pSrc_converted,blockSize,pResult,pIndex); + PyObject* pResultOBJ=Py_BuildValue("i",*pResult); + PyObject* pIndexOBJ=Py_BuildValue("i",*pIndex); + + PyObject *pythonResult = Py_BuildValue("OO",pResultOBJ,pIndexOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + Py_DECREF(pIndexOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_min_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + float32_t *pResult=NULL; // output + uint32_t *pIndex=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(float32_t)*1); + + + pIndex=PyMem_Malloc(sizeof(uint32_t)*1); + + + arm_min_f32(pSrc_converted,blockSize,pResult,pIndex); + PyObject* pResultOBJ=Py_BuildValue("f",*pResult); + PyObject* pIndexOBJ=Py_BuildValue("i",*pIndex); + + PyObject *pythonResult = Py_BuildValue("OO",pResultOBJ,pIndexOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + Py_DECREF(pIndexOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_max_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q7_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q7_t *pResult=NULL; // output + uint32_t *pIndex=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_BYTE,int8_t,q7_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q7_t)*1); + + + pIndex=PyMem_Malloc(sizeof(uint32_t)*1); + + + arm_max_q7(pSrc_converted,blockSize,pResult,pIndex); + PyObject* pResultOBJ=Py_BuildValue("i",*pResult); + PyObject* pIndexOBJ=Py_BuildValue("i",*pIndex); + + PyObject *pythonResult = Py_BuildValue("OO",pResultOBJ,pIndexOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + Py_DECREF(pIndexOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_max_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q15_t *pResult=NULL; // output + uint32_t *pIndex=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q15_t)*1); + + + pIndex=PyMem_Malloc(sizeof(uint32_t)*1); + + + arm_max_q15(pSrc_converted,blockSize,pResult,pIndex); + PyObject* pResultOBJ=Py_BuildValue("h",*pResult); + PyObject* pIndexOBJ=Py_BuildValue("i",*pIndex); + + PyObject *pythonResult = Py_BuildValue("OO",pResultOBJ,pIndexOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + Py_DECREF(pIndexOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_max_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + q31_t *pResult=NULL; // output + uint32_t *pIndex=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(q31_t)*1); + + + pIndex=PyMem_Malloc(sizeof(uint32_t)*1); + + + arm_max_q31(pSrc_converted,blockSize,pResult,pIndex); + PyObject* pResultOBJ=Py_BuildValue("i",*pResult); + PyObject* pIndexOBJ=Py_BuildValue("i",*pIndex); + + PyObject *pythonResult = Py_BuildValue("OO",pResultOBJ,pIndexOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + Py_DECREF(pIndexOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_max_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + uint32_t blockSize; // input + float32_t *pResult=NULL; // output + uint32_t *pIndex=NULL; // output + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pResult=PyMem_Malloc(sizeof(float32_t)*1); + + + pIndex=PyMem_Malloc(sizeof(uint32_t)*1); + + + arm_max_f32(pSrc_converted,blockSize,pResult,pIndex); + PyObject* pResultOBJ=Py_BuildValue("f",*pResult); + PyObject* pIndexOBJ=Py_BuildValue("i",*pIndex); + + PyObject *pythonResult = Py_BuildValue("OO",pResultOBJ,pIndexOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pResultOBJ); + Py_DECREF(pIndexOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mult_cmplx_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q15_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q15_t *pSrcB_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT16,int16_t,int16_t); + GETARGUMENT(pSrcB,NPY_INT16,int16_t,int16_t); + numSamples = arraySizepSrcA ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(q15_t)*2*numSamples); + + + arm_cmplx_mult_cmplx_q15(pSrcA_converted,pSrcB_converted,pDst,numSamples); + INT16ARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mult_cmplx_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + q31_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + q31_t *pSrcB_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_INT32,int32_t,int32_t); + GETARGUMENT(pSrcB,NPY_INT32,int32_t,int32_t); + numSamples = arraySizepSrcA ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(q31_t)*2*numSamples); + + + arm_cmplx_mult_cmplx_q31(pSrcA_converted,pSrcB_converted,pDst,numSamples); + INT32ARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_cmplx_mult_cmplx_f32(PyObject *obj, PyObject *args) +{ + + PyObject *pSrcA=NULL; // input + float32_t *pSrcA_converted=NULL; // input + PyObject *pSrcB=NULL; // input + float32_t *pSrcB_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t numSamples; // input + + if (PyArg_ParseTuple(args,"OO",&pSrcA,&pSrcB)) + { + + GETARGUMENT(pSrcA,NPY_DOUBLE,double,float32_t); + GETARGUMENT(pSrcB,NPY_DOUBLE,double,float32_t); + numSamples = arraySizepSrcA ; + numSamples = numSamples / 2; + + pDst=PyMem_Malloc(sizeof(float32_t)*2*numSamples); + + + arm_cmplx_mult_cmplx_f32(pSrcA_converted,pSrcB_converted,pDst,numSamples); + FLOATARRAY1(pDstOBJ,2*numSamples,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrcA_converted); + FREEARGUMENT(pSrcB_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_float_to_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_float_to_q31(pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_float_to_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_float_to_q15(pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_float_to_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + float32_t *pSrc_converted=NULL; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_DOUBLE,double,float32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_float_to_q7(pSrc_converted,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_q31_to_q15(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q15_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q15_t)*blockSize); + + + arm_q31_to_q15(pSrc_converted,pDst,blockSize); + INT16ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_q31_to_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q31_t *pSrc_converted=NULL; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT32,int32_t,int32_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_q31_to_q7(pSrc_converted,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_q15_to_float(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + float32_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(float32_t)*blockSize); + + + arm_q15_to_float(pSrc_converted,pDst,blockSize); + FLOATARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_q15_to_q31(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q31_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q31_t)*blockSize); + + + arm_q15_to_q31(pSrc_converted,pDst,blockSize); + INT32ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_q15_to_q7(PyObject *obj, PyObject *args) +{ + + PyObject *pSrc=NULL; // input + q15_t *pSrc_converted=NULL; // input + q7_t *pDst=NULL; // output + uint32_t blockSize; // input + + if (PyArg_ParseTuple(args,"O",&pSrc)) + { + + GETARGUMENT(pSrc,NPY_INT16,int16_t,int16_t); + blockSize = arraySizepSrc ; + + pDst=PyMem_Malloc(sizeof(q7_t)*blockSize); + + + arm_q15_to_q7(pSrc_converted,pDst,blockSize); + INT8ARRAY1(pDstOBJ,blockSize,pDst); + + PyObject *pythonResult = Py_BuildValue("O",pDstOBJ); + + FREEARGUMENT(pSrc_converted); + Py_DECREF(pDstOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_bilinear_interp_f32(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + float32_t X; // input + float32_t Y; // input + + if (PyArg_ParseTuple(args,"Off",&S,&X,&Y)) + { + + ml_arm_bilinear_interp_instance_f32Object *selfS = (ml_arm_bilinear_interp_instance_f32Object *)S; + + float32_t returnValue = arm_bilinear_interp_f32(selfS->instance,X,Y); + PyObject* theReturnOBJ=Py_BuildValue("f",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_bilinear_interp_q31(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + q31_t X; // input + q31_t Y; // input + + if (PyArg_ParseTuple(args,"Oii",&S,&X,&Y)) + { + + ml_arm_bilinear_interp_instance_q31Object *selfS = (ml_arm_bilinear_interp_instance_q31Object *)S; + + q31_t returnValue = arm_bilinear_interp_q31(selfS->instance,X,Y); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_bilinear_interp_q15(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + q31_t X; // input + q31_t Y; // input + + if (PyArg_ParseTuple(args,"Oii",&S,&X,&Y)) + { + + ml_arm_bilinear_interp_instance_q15Object *selfS = (ml_arm_bilinear_interp_instance_q15Object *)S; + + q15_t returnValue = arm_bilinear_interp_q15(selfS->instance,X,Y); + PyObject* theReturnOBJ=Py_BuildValue("h",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyObject * +cmsis_arm_bilinear_interp_q7(PyObject *obj, PyObject *args) +{ + + PyObject *S=NULL; // input + q31_t X; // input + q31_t Y; // input + + if (PyArg_ParseTuple(args,"Oii",&S,&X,&Y)) + { + + ml_arm_bilinear_interp_instance_q7Object *selfS = (ml_arm_bilinear_interp_instance_q7Object *)S; + + q7_t returnValue = arm_bilinear_interp_q7(selfS->instance,X,Y); + PyObject* theReturnOBJ=Py_BuildValue("i",returnValue); + + PyObject *pythonResult = Py_BuildValue("O",theReturnOBJ); + + Py_DECREF(theReturnOBJ); + return(pythonResult); + + } + return(NULL); +} + + +static PyMethodDef CMSISMLMethods[] = { + +{"arm_recip_q31", cmsis_arm_recip_q31, METH_VARARGS,""}, +{"arm_recip_q15", cmsis_arm_recip_q15, METH_VARARGS,""}, +{"arm_fir_q7", cmsis_arm_fir_q7, METH_VARARGS,""}, +{"arm_fir_init_q7", cmsis_arm_fir_init_q7, METH_VARARGS,""}, +{"arm_fir_q15", cmsis_arm_fir_q15, METH_VARARGS,""}, +{"arm_fir_fast_q15", cmsis_arm_fir_fast_q15, METH_VARARGS,""}, +{"arm_fir_init_q15", cmsis_arm_fir_init_q15, METH_VARARGS,""}, +{"arm_fir_q31", cmsis_arm_fir_q31, METH_VARARGS,""}, +{"arm_fir_fast_q31", cmsis_arm_fir_fast_q31, METH_VARARGS,""}, +{"arm_fir_init_q31", cmsis_arm_fir_init_q31, METH_VARARGS,""}, +{"arm_fir_f32", cmsis_arm_fir_f32, METH_VARARGS,""}, +{"arm_fir_init_f32", cmsis_arm_fir_init_f32, METH_VARARGS,""}, +{"arm_biquad_cascade_df1_q15", cmsis_arm_biquad_cascade_df1_q15, METH_VARARGS,""}, +{"arm_biquad_cascade_df1_init_q15", cmsis_arm_biquad_cascade_df1_init_q15, METH_VARARGS,""}, +{"arm_biquad_cascade_df1_fast_q15", cmsis_arm_biquad_cascade_df1_fast_q15, METH_VARARGS,""}, +{"arm_biquad_cascade_df1_q31", cmsis_arm_biquad_cascade_df1_q31, METH_VARARGS,""}, +{"arm_biquad_cascade_df1_fast_q31", cmsis_arm_biquad_cascade_df1_fast_q31, METH_VARARGS,""}, +{"arm_biquad_cascade_df1_init_q31", cmsis_arm_biquad_cascade_df1_init_q31, METH_VARARGS,""}, +{"arm_biquad_cascade_df1_f32", cmsis_arm_biquad_cascade_df1_f32, METH_VARARGS,""}, +{"arm_biquad_cascade_df1_init_f32", cmsis_arm_biquad_cascade_df1_init_f32, METH_VARARGS,""}, +{"arm_mat_add_f32", cmsis_arm_mat_add_f32, METH_VARARGS,""}, +{"arm_mat_add_q15", cmsis_arm_mat_add_q15, METH_VARARGS,""}, +{"arm_mat_add_q31", cmsis_arm_mat_add_q31, METH_VARARGS,""}, +{"arm_mat_cmplx_mult_f32", cmsis_arm_mat_cmplx_mult_f32, METH_VARARGS,""}, +{"arm_mat_cmplx_mult_q15", cmsis_arm_mat_cmplx_mult_q15, METH_VARARGS,""}, +{"arm_mat_cmplx_mult_q31", cmsis_arm_mat_cmplx_mult_q31, METH_VARARGS,""}, +{"arm_mat_trans_f32", cmsis_arm_mat_trans_f32, METH_VARARGS,""}, +{"arm_mat_trans_q15", cmsis_arm_mat_trans_q15, METH_VARARGS,""}, +{"arm_mat_trans_q31", cmsis_arm_mat_trans_q31, METH_VARARGS,""}, +{"arm_mat_mult_f32", cmsis_arm_mat_mult_f32, METH_VARARGS,""}, +{"arm_mat_mult_q15", cmsis_arm_mat_mult_q15, METH_VARARGS,""}, +{"arm_mat_mult_fast_q15", cmsis_arm_mat_mult_fast_q15, METH_VARARGS,""}, +{"arm_mat_mult_q31", cmsis_arm_mat_mult_q31, METH_VARARGS,""}, +{"arm_mat_mult_fast_q31", cmsis_arm_mat_mult_fast_q31, METH_VARARGS,""}, +{"arm_mat_sub_f32", cmsis_arm_mat_sub_f32, METH_VARARGS,""}, +{"arm_mat_sub_q15", cmsis_arm_mat_sub_q15, METH_VARARGS,""}, +{"arm_mat_sub_q31", cmsis_arm_mat_sub_q31, METH_VARARGS,""}, +{"arm_mat_scale_f32", cmsis_arm_mat_scale_f32, METH_VARARGS,""}, +{"arm_mat_scale_q15", cmsis_arm_mat_scale_q15, METH_VARARGS,""}, +{"arm_mat_scale_q31", cmsis_arm_mat_scale_q31, METH_VARARGS,""}, +{"arm_pid_init_f32", cmsis_arm_pid_init_f32, METH_VARARGS,""}, +{"arm_pid_reset_f32", cmsis_arm_pid_reset_f32, METH_VARARGS,""}, +{"arm_pid_init_q31", cmsis_arm_pid_init_q31, METH_VARARGS,""}, +{"arm_pid_reset_q31", cmsis_arm_pid_reset_q31, METH_VARARGS,""}, +{"arm_pid_init_q15", cmsis_arm_pid_init_q15, METH_VARARGS,""}, +{"arm_pid_reset_q15", cmsis_arm_pid_reset_q15, METH_VARARGS,""}, +{"arm_mult_q7", cmsis_arm_mult_q7, METH_VARARGS,""}, +{"arm_mult_q15", cmsis_arm_mult_q15, METH_VARARGS,""}, +{"arm_mult_q31", cmsis_arm_mult_q31, METH_VARARGS,""}, +{"arm_mult_f32", cmsis_arm_mult_f32, METH_VARARGS,""}, +{"arm_cfft_radix2_init_q15", cmsis_arm_cfft_radix2_init_q15, METH_VARARGS,""}, +{"arm_cfft_radix2_q15", cmsis_arm_cfft_radix2_q15, METH_VARARGS,""}, +{"arm_cfft_radix4_init_q15", cmsis_arm_cfft_radix4_init_q15, METH_VARARGS,""}, +{"arm_cfft_radix4_q15", cmsis_arm_cfft_radix4_q15, METH_VARARGS,""}, +{"arm_cfft_radix2_init_q31", cmsis_arm_cfft_radix2_init_q31, METH_VARARGS,""}, +{"arm_cfft_radix2_q31", cmsis_arm_cfft_radix2_q31, METH_VARARGS,""}, +{"arm_cfft_radix4_q31", cmsis_arm_cfft_radix4_q31, METH_VARARGS,""}, +{"arm_cfft_radix4_init_q31", cmsis_arm_cfft_radix4_init_q31, METH_VARARGS,""}, +{"arm_cfft_radix2_init_f32", cmsis_arm_cfft_radix2_init_f32, METH_VARARGS,""}, +{"arm_cfft_radix2_f32", cmsis_arm_cfft_radix2_f32, METH_VARARGS,""}, +{"arm_cfft_radix4_init_f32", cmsis_arm_cfft_radix4_init_f32, METH_VARARGS,""}, +{"arm_cfft_radix4_f32", cmsis_arm_cfft_radix4_f32, METH_VARARGS,""}, +{"arm_cfft_q15", cmsis_arm_cfft_q15, METH_VARARGS,""}, +{"arm_cfft_q31", cmsis_arm_cfft_q31, METH_VARARGS,""}, +{"arm_cfft_f32", cmsis_arm_cfft_f32, METH_VARARGS,""}, +{"arm_rfft_init_q15", cmsis_arm_rfft_init_q15, METH_VARARGS,""}, +{"arm_rfft_q15", cmsis_arm_rfft_q15, METH_VARARGS,""}, +{"arm_rfft_init_q31", cmsis_arm_rfft_init_q31, METH_VARARGS,""}, +{"arm_rfft_q31", cmsis_arm_rfft_q31, METH_VARARGS,""}, +{"arm_rfft_init_f32", cmsis_arm_rfft_init_f32, METH_VARARGS,""}, +{"arm_rfft_f32", cmsis_arm_rfft_f32, METH_VARARGS,""}, +{"arm_rfft_fast_init_f32", cmsis_arm_rfft_fast_init_f32, METH_VARARGS,""}, +{"arm_rfft_32_fast_init_f32", cmsis_arm_rfft_32_fast_init_f32, METH_VARARGS,""}, +{"arm_rfft_64_fast_init_f32", cmsis_arm_rfft_64_fast_init_f32, METH_VARARGS,""}, +{"arm_rfft_128_fast_init_f32", cmsis_arm_rfft_128_fast_init_f32, METH_VARARGS,""}, +{"arm_rfft_256_fast_init_f32", cmsis_arm_rfft_256_fast_init_f32, METH_VARARGS,""}, +{"arm_rfft_512_fast_init_f32", cmsis_arm_rfft_512_fast_init_f32, METH_VARARGS,""}, +{"arm_rfft_1024_fast_init_f32", cmsis_arm_rfft_1024_fast_init_f32, METH_VARARGS,""}, +{"arm_rfft_2048_fast_init_f32", cmsis_arm_rfft_2048_fast_init_f32, METH_VARARGS,""}, +{"arm_rfft_4096_fast_init_f32", cmsis_arm_rfft_4096_fast_init_f32, METH_VARARGS,""}, +{"arm_rfft_fast_f32", cmsis_arm_rfft_fast_f32, METH_VARARGS,""}, +{"arm_dct4_init_f32", cmsis_arm_dct4_init_f32, METH_VARARGS,""}, +{"arm_dct4_f32", cmsis_arm_dct4_f32, METH_VARARGS,""}, +{"arm_dct4_init_q31", cmsis_arm_dct4_init_q31, METH_VARARGS,""}, +{"arm_dct4_q31", cmsis_arm_dct4_q31, METH_VARARGS,""}, +{"arm_dct4_init_q15", cmsis_arm_dct4_init_q15, METH_VARARGS,""}, +{"arm_dct4_q15", cmsis_arm_dct4_q15, METH_VARARGS,""}, +{"arm_add_f32", cmsis_arm_add_f32, METH_VARARGS,""}, +{"arm_add_q7", cmsis_arm_add_q7, METH_VARARGS,""}, +{"arm_add_q15", cmsis_arm_add_q15, METH_VARARGS,""}, +{"arm_add_q31", cmsis_arm_add_q31, METH_VARARGS,""}, +{"arm_sub_f32", cmsis_arm_sub_f32, METH_VARARGS,""}, +{"arm_sub_q7", cmsis_arm_sub_q7, METH_VARARGS,""}, +{"arm_sub_q15", cmsis_arm_sub_q15, METH_VARARGS,""}, +{"arm_sub_q31", cmsis_arm_sub_q31, METH_VARARGS,""}, +{"arm_scale_f32", cmsis_arm_scale_f32, METH_VARARGS,""}, +{"arm_scale_q7", cmsis_arm_scale_q7, METH_VARARGS,""}, +{"arm_scale_q15", cmsis_arm_scale_q15, METH_VARARGS,""}, +{"arm_scale_q31", cmsis_arm_scale_q31, METH_VARARGS,""}, +{"arm_abs_q7", cmsis_arm_abs_q7, METH_VARARGS,""}, +{"arm_abs_f32", cmsis_arm_abs_f32, METH_VARARGS,""}, +{"arm_abs_q15", cmsis_arm_abs_q15, METH_VARARGS,""}, +{"arm_abs_q31", cmsis_arm_abs_q31, METH_VARARGS,""}, +{"arm_dot_prod_f32", cmsis_arm_dot_prod_f32, METH_VARARGS,""}, +{"arm_dot_prod_q7", cmsis_arm_dot_prod_q7, METH_VARARGS,""}, +{"arm_dot_prod_q15", cmsis_arm_dot_prod_q15, METH_VARARGS,""}, +{"arm_dot_prod_q31", cmsis_arm_dot_prod_q31, METH_VARARGS,""}, +{"arm_shift_q7", cmsis_arm_shift_q7, METH_VARARGS,""}, +{"arm_shift_q15", cmsis_arm_shift_q15, METH_VARARGS,""}, +{"arm_shift_q31", cmsis_arm_shift_q31, METH_VARARGS,""}, +{"arm_offset_f32", cmsis_arm_offset_f32, METH_VARARGS,""}, +{"arm_offset_q7", cmsis_arm_offset_q7, METH_VARARGS,""}, +{"arm_offset_q15", cmsis_arm_offset_q15, METH_VARARGS,""}, +{"arm_offset_q31", cmsis_arm_offset_q31, METH_VARARGS,""}, +{"arm_negate_f32", cmsis_arm_negate_f32, METH_VARARGS,""}, +{"arm_negate_q7", cmsis_arm_negate_q7, METH_VARARGS,""}, +{"arm_negate_q15", cmsis_arm_negate_q15, METH_VARARGS,""}, +{"arm_negate_q31", cmsis_arm_negate_q31, METH_VARARGS,""}, +{"arm_copy_f32", cmsis_arm_copy_f32, METH_VARARGS,""}, +{"arm_copy_q7", cmsis_arm_copy_q7, METH_VARARGS,""}, +{"arm_copy_q15", cmsis_arm_copy_q15, METH_VARARGS,""}, +{"arm_copy_q31", cmsis_arm_copy_q31, METH_VARARGS,""}, +{"arm_conv_f32", cmsis_arm_conv_f32, METH_VARARGS,""}, +{"arm_conv_opt_q15", cmsis_arm_conv_opt_q15, METH_VARARGS,""}, +{"arm_conv_q15", cmsis_arm_conv_q15, METH_VARARGS,""}, +{"arm_conv_fast_q15", cmsis_arm_conv_fast_q15, METH_VARARGS,""}, +{"arm_conv_fast_opt_q15", cmsis_arm_conv_fast_opt_q15, METH_VARARGS,""}, +{"arm_conv_q31", cmsis_arm_conv_q31, METH_VARARGS,""}, +{"arm_conv_fast_q31", cmsis_arm_conv_fast_q31, METH_VARARGS,""}, +{"arm_conv_opt_q7", cmsis_arm_conv_opt_q7, METH_VARARGS,""}, +{"arm_conv_q7", cmsis_arm_conv_q7, METH_VARARGS,""}, +{"arm_conv_partial_f32", cmsis_arm_conv_partial_f32, METH_VARARGS,""}, +{"arm_conv_partial_opt_q15", cmsis_arm_conv_partial_opt_q15, METH_VARARGS,""}, +{"arm_conv_partial_q15", cmsis_arm_conv_partial_q15, METH_VARARGS,""}, +{"arm_conv_partial_fast_q15", cmsis_arm_conv_partial_fast_q15, METH_VARARGS,""}, +{"arm_conv_partial_fast_opt_q15", cmsis_arm_conv_partial_fast_opt_q15, METH_VARARGS,""}, +{"arm_conv_partial_q31", cmsis_arm_conv_partial_q31, METH_VARARGS,""}, +{"arm_conv_partial_fast_q31", cmsis_arm_conv_partial_fast_q31, METH_VARARGS,""}, +{"arm_conv_partial_opt_q7", cmsis_arm_conv_partial_opt_q7, METH_VARARGS,""}, +{"arm_conv_partial_q7", cmsis_arm_conv_partial_q7, METH_VARARGS,""}, +{"arm_fir_decimate_f32", cmsis_arm_fir_decimate_f32, METH_VARARGS,""}, +{"arm_fir_decimate_init_f32", cmsis_arm_fir_decimate_init_f32, METH_VARARGS,""}, +{"arm_fir_decimate_q15", cmsis_arm_fir_decimate_q15, METH_VARARGS,""}, +{"arm_fir_decimate_fast_q15", cmsis_arm_fir_decimate_fast_q15, METH_VARARGS,""}, +{"arm_fir_decimate_init_q15", cmsis_arm_fir_decimate_init_q15, METH_VARARGS,""}, +{"arm_fir_decimate_q31", cmsis_arm_fir_decimate_q31, METH_VARARGS,""}, +{"arm_fir_decimate_fast_q31", cmsis_arm_fir_decimate_fast_q31, METH_VARARGS,""}, +{"arm_fir_decimate_init_q31", cmsis_arm_fir_decimate_init_q31, METH_VARARGS,""}, +{"arm_fir_interpolate_q15", cmsis_arm_fir_interpolate_q15, METH_VARARGS,""}, +{"arm_fir_interpolate_init_q15", cmsis_arm_fir_interpolate_init_q15, METH_VARARGS,""}, +{"arm_fir_interpolate_q31", cmsis_arm_fir_interpolate_q31, METH_VARARGS,""}, +{"arm_fir_interpolate_init_q31", cmsis_arm_fir_interpolate_init_q31, METH_VARARGS,""}, +{"arm_fir_interpolate_f32", cmsis_arm_fir_interpolate_f32, METH_VARARGS,""}, +{"arm_fir_interpolate_init_f32", cmsis_arm_fir_interpolate_init_f32, METH_VARARGS,""}, +{"arm_biquad_cas_df1_32x64_q31", cmsis_arm_biquad_cas_df1_32x64_q31, METH_VARARGS,""}, +{"arm_biquad_cas_df1_32x64_init_q31", cmsis_arm_biquad_cas_df1_32x64_init_q31, METH_VARARGS,""}, +{"arm_biquad_cascade_df2T_f32", cmsis_arm_biquad_cascade_df2T_f32, METH_VARARGS,""}, +{"arm_biquad_cascade_stereo_df2T_f32", cmsis_arm_biquad_cascade_stereo_df2T_f32, METH_VARARGS,""}, +{"arm_biquad_cascade_df2T_f64", cmsis_arm_biquad_cascade_df2T_f64, METH_VARARGS,""}, +{"arm_biquad_cascade_df2T_init_f32", cmsis_arm_biquad_cascade_df2T_init_f32, METH_VARARGS,""}, +{"arm_biquad_cascade_stereo_df2T_init_f32", cmsis_arm_biquad_cascade_stereo_df2T_init_f32, METH_VARARGS,""}, +{"arm_biquad_cascade_df2T_init_f64", cmsis_arm_biquad_cascade_df2T_init_f64, METH_VARARGS,""}, +{"arm_fir_lattice_init_q15", cmsis_arm_fir_lattice_init_q15, METH_VARARGS,""}, +{"arm_fir_lattice_q15", cmsis_arm_fir_lattice_q15, METH_VARARGS,""}, +{"arm_fir_lattice_init_q31", cmsis_arm_fir_lattice_init_q31, METH_VARARGS,""}, +{"arm_fir_lattice_q31", cmsis_arm_fir_lattice_q31, METH_VARARGS,""}, +{"arm_fir_lattice_init_f32", cmsis_arm_fir_lattice_init_f32, METH_VARARGS,""}, +{"arm_fir_lattice_f32", cmsis_arm_fir_lattice_f32, METH_VARARGS,""}, +{"arm_iir_lattice_f32", cmsis_arm_iir_lattice_f32, METH_VARARGS,""}, +{"arm_iir_lattice_init_f32", cmsis_arm_iir_lattice_init_f32, METH_VARARGS,""}, +{"arm_iir_lattice_q31", cmsis_arm_iir_lattice_q31, METH_VARARGS,""}, +{"arm_iir_lattice_init_q31", cmsis_arm_iir_lattice_init_q31, METH_VARARGS,""}, +{"arm_iir_lattice_q15", cmsis_arm_iir_lattice_q15, METH_VARARGS,""}, +{"arm_iir_lattice_init_q15", cmsis_arm_iir_lattice_init_q15, METH_VARARGS,""}, +{"arm_cfft_init_f32", cmsis_arm_cfft_init_f32, METH_VARARGS,""}, +{"arm_cfft_init_q31", cmsis_arm_cfft_init_q31, METH_VARARGS,""}, +{"arm_cfft_init_q15", cmsis_arm_cfft_init_q15, METH_VARARGS,""}, +{"arm_lms_f32", cmsis_arm_lms_f32, METH_VARARGS,""}, +{"arm_lms_init_f32", cmsis_arm_lms_init_f32, METH_VARARGS,""}, +{"arm_lms_init_q15", cmsis_arm_lms_init_q15, METH_VARARGS,""}, +{"arm_lms_q15", cmsis_arm_lms_q15, METH_VARARGS,""}, +{"arm_lms_q31", cmsis_arm_lms_q31, METH_VARARGS,""}, +{"arm_lms_init_q31", cmsis_arm_lms_init_q31, METH_VARARGS,""}, +{"arm_lms_norm_f32", cmsis_arm_lms_norm_f32, METH_VARARGS,""}, +{"arm_lms_norm_init_f32", cmsis_arm_lms_norm_init_f32, METH_VARARGS,""}, +{"arm_lms_norm_q31", cmsis_arm_lms_norm_q31, METH_VARARGS,""}, +{"arm_lms_norm_init_q31", cmsis_arm_lms_norm_init_q31, METH_VARARGS,""}, +{"arm_lms_norm_q15", cmsis_arm_lms_norm_q15, METH_VARARGS,""}, +{"arm_lms_norm_init_q15", cmsis_arm_lms_norm_init_q15, METH_VARARGS,""}, +{"arm_correlate_f32", cmsis_arm_correlate_f32, METH_VARARGS,""}, +{"arm_correlate_opt_q15", cmsis_arm_correlate_opt_q15, METH_VARARGS,""}, +{"arm_correlate_q15", cmsis_arm_correlate_q15, METH_VARARGS,""}, +{"arm_correlate_fast_q15", cmsis_arm_correlate_fast_q15, METH_VARARGS,""}, +{"arm_correlate_fast_opt_q15", cmsis_arm_correlate_fast_opt_q15, METH_VARARGS,""}, +{"arm_correlate_q31", cmsis_arm_correlate_q31, METH_VARARGS,""}, +{"arm_correlate_fast_q31", cmsis_arm_correlate_fast_q31, METH_VARARGS,""}, +{"arm_correlate_opt_q7", cmsis_arm_correlate_opt_q7, METH_VARARGS,""}, +{"arm_correlate_q7", cmsis_arm_correlate_q7, METH_VARARGS,""}, +{"arm_fir_sparse_f32", cmsis_arm_fir_sparse_f32, METH_VARARGS,""}, +{"arm_fir_sparse_init_f32", cmsis_arm_fir_sparse_init_f32, METH_VARARGS,""}, +{"arm_fir_sparse_init_q31", cmsis_arm_fir_sparse_init_q31, METH_VARARGS,""}, +{"arm_fir_sparse_init_q15", cmsis_arm_fir_sparse_init_q15, METH_VARARGS,""}, +{"arm_fir_sparse_init_q7", cmsis_arm_fir_sparse_init_q7, METH_VARARGS,""}, +{"arm_sin_cos_f32", cmsis_arm_sin_cos_f32, METH_VARARGS,""}, +{"arm_sin_cos_q31", cmsis_arm_sin_cos_q31, METH_VARARGS,""}, +{"arm_cmplx_conj_f32", cmsis_arm_cmplx_conj_f32, METH_VARARGS,""}, +{"arm_cmplx_conj_q31", cmsis_arm_cmplx_conj_q31, METH_VARARGS,""}, +{"arm_cmplx_conj_q15", cmsis_arm_cmplx_conj_q15, METH_VARARGS,""}, +{"arm_cmplx_mag_squared_f32", cmsis_arm_cmplx_mag_squared_f32, METH_VARARGS,""}, +{"arm_cmplx_mag_squared_q31", cmsis_arm_cmplx_mag_squared_q31, METH_VARARGS,""}, +{"arm_cmplx_mag_squared_q15", cmsis_arm_cmplx_mag_squared_q15, METH_VARARGS,""}, +{"arm_pid_f32", cmsis_arm_pid_f32, METH_VARARGS,""}, +{"arm_pid_q31", cmsis_arm_pid_q31, METH_VARARGS,""}, +{"arm_pid_q15", cmsis_arm_pid_q15, METH_VARARGS,""}, +{"arm_mat_inverse_f32", cmsis_arm_mat_inverse_f32, METH_VARARGS,""}, +{"arm_mat_inverse_f64", cmsis_arm_mat_inverse_f64, METH_VARARGS,""}, +{"arm_clarke_f32", cmsis_arm_clarke_f32, METH_VARARGS,""}, +{"arm_clarke_q31", cmsis_arm_clarke_q31, METH_VARARGS,""}, +{"arm_q7_to_q31", cmsis_arm_q7_to_q31, METH_VARARGS,""}, +{"arm_inv_clarke_f32", cmsis_arm_inv_clarke_f32, METH_VARARGS,""}, +{"arm_inv_clarke_q31", cmsis_arm_inv_clarke_q31, METH_VARARGS,""}, +{"arm_q7_to_q15", cmsis_arm_q7_to_q15, METH_VARARGS,""}, +{"arm_park_f32", cmsis_arm_park_f32, METH_VARARGS,""}, +{"arm_park_q31", cmsis_arm_park_q31, METH_VARARGS,""}, +{"arm_q7_to_float", cmsis_arm_q7_to_float, METH_VARARGS,""}, +{"arm_inv_park_f32", cmsis_arm_inv_park_f32, METH_VARARGS,""}, +{"arm_inv_park_q31", cmsis_arm_inv_park_q31, METH_VARARGS,""}, +{"arm_q31_to_float", cmsis_arm_q31_to_float, METH_VARARGS,""}, +{"arm_linear_interp_f32", cmsis_arm_linear_interp_f32, METH_VARARGS,""}, +{"arm_linear_interp_q31", cmsis_arm_linear_interp_q31, METH_VARARGS,""}, +{"arm_linear_interp_q15", cmsis_arm_linear_interp_q15, METH_VARARGS,""}, +{"arm_linear_interp_q7", cmsis_arm_linear_interp_q7, METH_VARARGS,""}, +{"arm_sin_f32", cmsis_arm_sin_f32, METH_VARARGS,""}, +{"arm_sin_q31", cmsis_arm_sin_q31, METH_VARARGS,""}, +{"arm_sin_q15", cmsis_arm_sin_q15, METH_VARARGS,""}, +{"arm_cos_f32", cmsis_arm_cos_f32, METH_VARARGS,""}, +{"arm_cos_q31", cmsis_arm_cos_q31, METH_VARARGS,""}, +{"arm_cos_q15", cmsis_arm_cos_q15, METH_VARARGS,""}, +{"arm_sqrt_f32", cmsis_arm_sqrt_f32, METH_VARARGS,""}, +{"arm_sqrt_q31", cmsis_arm_sqrt_q31, METH_VARARGS,""}, +{"arm_sqrt_q15", cmsis_arm_sqrt_q15, METH_VARARGS,""}, +{"arm_circularWrite_f32", cmsis_arm_circularWrite_f32, METH_VARARGS,""}, +{"arm_circularWrite_q15", cmsis_arm_circularWrite_q15, METH_VARARGS,""}, +{"arm_circularWrite_q7", cmsis_arm_circularWrite_q7, METH_VARARGS,""}, +{"arm_power_q31", cmsis_arm_power_q31, METH_VARARGS,""}, +{"arm_power_f32", cmsis_arm_power_f32, METH_VARARGS,""}, +{"arm_power_q15", cmsis_arm_power_q15, METH_VARARGS,""}, +{"arm_power_q7", cmsis_arm_power_q7, METH_VARARGS,""}, +{"arm_mean_q7", cmsis_arm_mean_q7, METH_VARARGS,""}, +{"arm_mean_q15", cmsis_arm_mean_q15, METH_VARARGS,""}, +{"arm_mean_q31", cmsis_arm_mean_q31, METH_VARARGS,""}, +{"arm_mean_f32", cmsis_arm_mean_f32, METH_VARARGS,""}, +{"arm_var_f32", cmsis_arm_var_f32, METH_VARARGS,""}, +{"arm_var_q31", cmsis_arm_var_q31, METH_VARARGS,""}, +{"arm_var_q15", cmsis_arm_var_q15, METH_VARARGS,""}, +{"arm_rms_f32", cmsis_arm_rms_f32, METH_VARARGS,""}, +{"arm_rms_q31", cmsis_arm_rms_q31, METH_VARARGS,""}, +{"arm_rms_q15", cmsis_arm_rms_q15, METH_VARARGS,""}, +{"arm_std_f32", cmsis_arm_std_f32, METH_VARARGS,""}, +{"arm_std_q31", cmsis_arm_std_q31, METH_VARARGS,""}, +{"arm_std_q15", cmsis_arm_std_q15, METH_VARARGS,""}, +{"arm_cmplx_mag_f32", cmsis_arm_cmplx_mag_f32, METH_VARARGS,""}, +{"arm_cmplx_mag_q31", cmsis_arm_cmplx_mag_q31, METH_VARARGS,""}, +{"arm_cmplx_mag_q15", cmsis_arm_cmplx_mag_q15, METH_VARARGS,""}, +{"arm_cmplx_dot_prod_q15", cmsis_arm_cmplx_dot_prod_q15, METH_VARARGS,""}, +{"arm_cmplx_dot_prod_q31", cmsis_arm_cmplx_dot_prod_q31, METH_VARARGS,""}, +{"arm_cmplx_dot_prod_f32", cmsis_arm_cmplx_dot_prod_f32, METH_VARARGS,""}, +{"arm_cmplx_mult_real_q15", cmsis_arm_cmplx_mult_real_q15, METH_VARARGS,""}, +{"arm_cmplx_mult_real_q31", cmsis_arm_cmplx_mult_real_q31, METH_VARARGS,""}, +{"arm_cmplx_mult_real_f32", cmsis_arm_cmplx_mult_real_f32, METH_VARARGS,""}, +{"arm_min_q7", cmsis_arm_min_q7, METH_VARARGS,""}, +{"arm_min_q15", cmsis_arm_min_q15, METH_VARARGS,""}, +{"arm_min_q31", cmsis_arm_min_q31, METH_VARARGS,""}, +{"arm_min_f32", cmsis_arm_min_f32, METH_VARARGS,""}, +{"arm_max_q7", cmsis_arm_max_q7, METH_VARARGS,""}, +{"arm_max_q15", cmsis_arm_max_q15, METH_VARARGS,""}, +{"arm_max_q31", cmsis_arm_max_q31, METH_VARARGS,""}, +{"arm_max_f32", cmsis_arm_max_f32, METH_VARARGS,""}, +{"arm_cmplx_mult_cmplx_q15", cmsis_arm_cmplx_mult_cmplx_q15, METH_VARARGS,""}, +{"arm_cmplx_mult_cmplx_q31", cmsis_arm_cmplx_mult_cmplx_q31, METH_VARARGS,""}, +{"arm_cmplx_mult_cmplx_f32", cmsis_arm_cmplx_mult_cmplx_f32, METH_VARARGS,""}, +{"arm_float_to_q31", cmsis_arm_float_to_q31, METH_VARARGS,""}, +{"arm_float_to_q15", cmsis_arm_float_to_q15, METH_VARARGS,""}, +{"arm_float_to_q7", cmsis_arm_float_to_q7, METH_VARARGS,""}, +{"arm_q31_to_q15", cmsis_arm_q31_to_q15, METH_VARARGS,""}, +{"arm_q31_to_q7", cmsis_arm_q31_to_q7, METH_VARARGS,""}, +{"arm_q15_to_float", cmsis_arm_q15_to_float, METH_VARARGS,""}, +{"arm_q15_to_q31", cmsis_arm_q15_to_q31, METH_VARARGS,""}, +{"arm_q15_to_q7", cmsis_arm_q15_to_q7, METH_VARARGS,""}, +{"arm_bilinear_interp_f32", cmsis_arm_bilinear_interp_f32, METH_VARARGS,""}, +{"arm_bilinear_interp_q31", cmsis_arm_bilinear_interp_q31, METH_VARARGS,""}, +{"arm_bilinear_interp_q15", cmsis_arm_bilinear_interp_q15, METH_VARARGS,""}, +{"arm_bilinear_interp_q7", cmsis_arm_bilinear_interp_q7, METH_VARARGS,""}, + + {"error_out", (PyCFunction)error_out, METH_NOARGS, NULL}, + {NULL, NULL, 0, NULL} /* Sentinel */ +}; + diff --git a/Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/fftinit.c b/Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/fftinit.c new file mode 100644 index 0000000..9845a05 --- /dev/null +++ b/Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/fftinit.c @@ -0,0 +1,262 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Python Wrapper + * Title: fftinit.c + * Description: FFT init functions for the Python wrapper + * + * $Date: 25. March 2019 + * $Revision: V0.0.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + +#define FFTINIT(SIZE) \ + S->bitRevLength = arm_cfft_sR_f32_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_f32_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_f32_len##SIZE.pTwiddle; + +#define FFTFXTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *)twiddleCoef_4096; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(4096); + break; + + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(2048); + + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(1024); + + break; + + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(512); + break; + + case 256U: + FFTINIT(256); + break; + + case 128U: + FFTINIT(128); + break; + + case 64U: + FFTINIT(64); + break; + + case 32U: + FFTINIT(32); + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(16); + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *)twiddleCoef_4096; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTFXTINIT(q31,4096); + break; + + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTFXTINIT(q31,2048); + + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTFXTINIT(q31,1024); + + break; + + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTFXTINIT(q31,512); + break; + + case 256U: + FFTFXTINIT(q31,256); + break; + + case 128U: + FFTFXTINIT(q31,128); + break; + + case 64U: + FFTFXTINIT(q31,64); + break; + + case 32U: + FFTFXTINIT(q31,32); + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTFXTINIT(q31,16); + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *)twiddleCoef_4096; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTFXTINIT(q15,4096); + break; + + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTFXTINIT(q15,2048); + + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTFXTINIT(q15,1024); + + break; + + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTFXTINIT(q15,512); + break; + + case 256U: + FFTFXTINIT(q15,256); + break; + + case 128U: + FFTFXTINIT(q15,128); + break; + + case 64U: + FFTFXTINIT(q15,64); + break; + + case 32U: + FFTFXTINIT(q15,32); + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTFXTINIT(q15,16); + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c new file mode 100644 index 0000000..b444c11 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BasicMathFunctions.c + * Description: Combination of all basic math function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_abs_f32.c" +#include "arm_abs_q15.c" +#include "arm_abs_q31.c" +#include "arm_abs_q7.c" +#include "arm_add_f32.c" +#include "arm_add_q15.c" +#include "arm_add_q31.c" +#include "arm_add_q7.c" +#include "arm_dot_prod_f32.c" +#include "arm_dot_prod_q15.c" +#include "arm_dot_prod_q31.c" +#include "arm_dot_prod_q7.c" +#include "arm_mult_f32.c" +#include "arm_mult_q15.c" +#include "arm_mult_q31.c" +#include "arm_mult_q7.c" +#include "arm_negate_f32.c" +#include "arm_negate_q15.c" +#include "arm_negate_q31.c" +#include "arm_negate_q7.c" +#include "arm_offset_f32.c" +#include "arm_offset_q15.c" +#include "arm_offset_q31.c" +#include "arm_offset_q7.c" +#include "arm_scale_f32.c" +#include "arm_scale_q15.c" +#include "arm_scale_q31.c" +#include "arm_scale_q7.c" +#include "arm_shift_q15.c" +#include "arm_shift_q31.c" +#include "arm_shift_q7.c" +#include "arm_sub_f32.c" +#include "arm_sub_q15.c" +#include "arm_sub_q31.c" +#include "arm_sub_q7.c" diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt new file mode 100644 index 0000000..717669f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt @@ -0,0 +1,16 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSPBasicMath) + + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPBasicMath STATIC ${SRC}) + +configdsp(CMSISDSPBasicMath ..) + +### Includes +target_include_directories(CMSISDSPBasicMath PUBLIC "${DSP}/../../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c new file mode 100644 index 0000000..a7d2624 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f32.c + * Description: Floating-point vector absolute value + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAbs Vector Absolute Value + + Computes the absolute value of a vector on an element-by-element basis. + + 
+      pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) + float32x4_t vec1; + float32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vabsq_f32(vec1); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c new file mode 100644 index 0000000..eb944ce --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q15.c + * Description: Q15 vector absolute value + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q15 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c new file mode 100644 index 0000000..bf7608b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q31.c + * Description: Q31 vector absolute value + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q31 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c new file mode 100644 index 0000000..a6c4a6c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q7.c + * Description: Q7 vector absolute value + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q7 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Conditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q7_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t) __QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c new file mode 100644 index 0000000..1c66a24 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f32.c + * Description: Floating-point vector addition + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAdd Vector Addition + + Element-by-element addition of two vectors. + + 
+      pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vaddq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c new file mode 100644 index 0000000..bc62937 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q15.c + * Description: Q15 vector addition + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q15 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t inB1, inB2; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia ((q15_t **) &pSrcA); + inA2 = read_q15x2_ia ((q15_t **) &pSrcA); + /* read 2 times 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia ((q15_t **) &pSrcB); + inB2 = read_q15x2_ia ((q15_t **) &pSrcB); + + /* Add and store 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, __QADD16(inA1, inB1)); + write_q15x2_ia (&pDst, __QADD16(inA2, inB2)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c new file mode 100644 index 0000000..3c1cbc2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q31.c + * Description: Q31 vector addition + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q31 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c new file mode 100644 index 0000000..f9c4a95 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q7.c + * Description: Q7 vector addition + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q7 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + +#if defined (ARM_MATH_DSP) + /* Add and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QADD8 (read_q7x4_ia ((q7_t **) &pSrcA), read_q7x4_ia ((q7_t **) &pSrcB))); +#else + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ + *pSrcB++, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c new file mode 100644 index 0000000..3eee3b9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c @@ -0,0 +1,163 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f32.c + * Description: Floating-point dot product + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicDotProd Vector Dot Product + + Computes the dot product of two vectors. + The vectors are multiplied element-by-element and then summed. + + 
+      sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary return variable */ + +#if defined(ARM_MATH_NEON) + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + float32x4_t accum = vdupq_n_f32(0); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + + while (blkCnt > 0U) + { + /* C = A[0]*B[0] + A[1]*B[1] + A[2]*B[2] + ... + A[blockSize-1]*B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + + accum = vmlaq_f32(accum, vec1, vec2); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + + /* Decrement the loop counter */ + blkCnt--; + } + +#if __aarch64__ + sum = vpadds_f32(vpadd_f32(vget_low_f32(accum), vget_high_f32(accum))); +#else + sum = (vpadd_f32(vget_low_f32(accum), vget_high_f32(accum)))[0] + (vpadd_f32(vget_low_f32(accum), vget_high_f32(accum)))[1]; +#endif + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} + +/** + @} end of BasicDotProd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c new file mode 100644 index 0000000..e303b09 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q15.c + * Description: Q15 dot product + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] result output result returned here + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these + results are added to a 64-bit accumulator in 34.30 format. + Nonsaturating additions are used and given that there are 33 guard bits in the accumulator + there is no risk of overflow. + The return result is in 34.30 format. + */ + +void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + +#if defined (ARM_MATH_DSP) + /* Calculate dot product and store result in a temporary buffer. */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &pSrcA), read_q15x2_ia ((q15_t **) &pSrcB), sum); + sum = __SMLALD(read_q15x2_ia ((q15_t **) &pSrcA), read_q15x2_ia ((q15_t **) &pSrcB), sum); +#else + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +//#if defined (ARM_MATH_DSP) +// sum = __SMLALD(*pSrcA++, *pSrcB++, sum); +//#else + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); +//#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 34.30 format */ + *result = sum; +} + +/** + @} end of BasicDotProd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c new file mode 100644 index 0000000..76cd577 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c @@ -0,0 +1,115 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q31.c + * Description: Q31 dot product + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q31 vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these + are truncated to 2.48 format by discarding the lower 14 bits. + The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + There are 15 guard bits in the accumulator and there is no risk of overflow as long as + the length of the vectors is less than 2^16 elements. + The return result is in 16.48 format. + */ + +void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 16.48 format */ + *result = sum; +} + +/** + @} end of BasicDotProd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c new file mode 100644 index 0000000..8e18a73 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q7.c + * Description: Q7 dot product + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] result output result returned here + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these + results are added to an accumulator in 18.14 format. + Nonsaturating additions are used and there is no danger of wrap around as long as + the vectors are less than 2^18 elements long. + The return result is in 18.14 format. + */ + +void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t input1, input2; /* Temporary variables */ + q31_t inA1, inA2, inB1, inB2; /* Temporary variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + +#if defined (ARM_MATH_DSP) + /* read 4 samples at a time from sourceA */ + input1 = read_q7x4_ia ((q7_t **) &pSrcA); + /* read 4 samples at a time from sourceB */ + input2 = read_q7x4_ia ((q7_t **) &pSrcB); + + /* extract two q7_t samples to q15_t samples */ + inA1 = __SXTB16(__ROR(input1, 8)); + /* extract reminaing two samples */ + inA2 = __SXTB16(input1); + /* extract two q7_t samples to q15_t samples */ + inB1 = __SXTB16(__ROR(input2, 8)); + /* extract reminaing two samples */ + inB2 = __SXTB16(input2); + + /* multiply and accumulate two samples at a time */ + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); +#else + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +//#if defined (ARM_MATH_DSP) +// sum = __SMLAD(*pSrcA++, *pSrcB++, sum); +//#else + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); +//#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 18.14 format */ + *result = sum; +} + +/** + @} end of BasicDotProd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c new file mode 100644 index 0000000..53ad73c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f32.c + * Description: Floating-point vector multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicMult Vector Multiplication + + Element-by-element multiplication of two vectors. + + 
+      pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply the inputs and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vmulq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c new file mode 100644 index 0000000..37aa924 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q15.c + * Description: Q15 vector multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q15 vector multiplication + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2, inB1, inB2; /* Temporary input variables */ + q15_t out1, out2, out3, out4; /* Temporary output variables */ + q31_t mul1, mul2, mul3, mul4; /* Temporary variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia ((q15_t **) &pSrcA); + /* read 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia ((q15_t **) &pSrcB); + /* read 2 samples at a time from sourceA */ + inA2 = read_q15x2_ia ((q15_t **) &pSrcA); + /* read 2 samples at a time from sourceB */ + inB2 = read_q15x2_ia ((q15_t **) &pSrcB); + + /* multiply mul = sourceA * sourceB */ + mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul2 = (q31_t) ((q15_t) (inA1 ) * (q15_t) (inB1 )); + mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 ) * (q15_t) (inB2 )); + + /* saturate result to 16 bit */ + out1 = (q15_t) __SSAT(mul1 >> 15, 16); + out2 = (q15_t) __SSAT(mul2 >> 15, 16); + out3 = (q15_t) __SSAT(mul3 >> 15, 16); + out4 = (q15_t) __SSAT(mul4 >> 15, 16); + + /* store result to destination */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(out2, out1, 16)); + write_q15x2_ia (&pDst, __PKHBT(out4, out3, 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pDst, __PKHBT(out3, out4, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c new file mode 100644 index 0000000..9592684 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q31.c + * Description: Q31 vector multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q31 vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + */ + +void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t out; /* Temporary output variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c new file mode 100644 index 0000000..5587ce5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q7.c + * Description: Q7 vector multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q7 vector multiplication + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t out1, out2, out3, out4; /* Temporary output variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + +#if defined (ARM_MATH_DSP) + /* Multiply inputs and store results in temporary variables */ + out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); +#else + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c new file mode 100644 index 0000000..f807112 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f32.c + * Description: Negates floating-point vectors + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicNegate Vector Negate + + Negates the elements of a vector. + + 
+      pDst[n] = -pSrc[n],   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) + float32x4_t vec1; + float32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vnegq_f32(vec1); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicNegate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c new file mode 100644 index 0000000..267e4cc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q15.c + * Description: Negates Q15 vectors + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q15 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Conditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t in1; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + +#if defined (ARM_MATH_DSP) + /* Negate and store result in destination buffer (2 samples at a time). */ + in1 = read_q15x2_ia ((q15_t **) &pSrc); + write_q15x2_ia (&pDst, __QSUB16(0, in1)); + + in1 = read_q15x2_ia ((q15_t **) &pSrc); + write_q15x2_ia (&pDst, __QSUB16(0, in1)); +#else + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicNegate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c new file mode 100644 index 0000000..645fb0a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q31.c + * Description: Negates Q31 vectors + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q31 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicNegate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c new file mode 100644 index 0000000..40a373e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q7.c + * Description: Negates Q7 vectors + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q7 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q7 value -1 (0x80) is saturated to the maximum allowable positive value 0x7F. + */ + +void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q7_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t in1; /* Temporary input variable */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + +#if defined (ARM_MATH_DSP) + /* Negate and store result in destination buffer (4 samples at a time). */ + in1 = read_q7x4_ia ((q7_t **) &pSrc); + write_q7x4_ia (&pDst, __QSUB8(0, in1)); +#else + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; + +#if defined (ARM_MATH_DSP) + *pDst++ = (q7_t) __QSUB(0, in); +#else + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicNegate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c new file mode 100644 index 0000000..b10e3f1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f32.c + * Description: Floating-point vector offset + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicOffset Vector Offset + + Adds a constant offset to each element of a vector. + + 
+      pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) + float32x4_t vec1; + float32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vaddq_f32(vec1,vdupq_n_f32(offset)); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicOffset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c new file mode 100644 index 0000000..cd2f22b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q15.c + * Description: Q15 vector offset + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t offset_packed; /* Offset packed to 32 bit */ + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PKHBT(offset, offset, 16); +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + +#if defined (ARM_MATH_DSP) + /* Add offset and store result in destination buffer (2 samples at a time). */ + write_q15x2_ia (&pDst, __QADD16(read_q15x2_ia ((q15_t **) &pSrc), offset_packed)); + write_q15x2_ia (&pDst, __QADD16(read_q15x2_ia ((q15_t **) &pSrc), offset_packed)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QADD16(*pSrc++, offset); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicOffset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c new file mode 100644 index 0000000..5de36b4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q31.c + * Description: Q31 vector offset + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = __QADD(*pSrc++, offset); +#else + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); +#endif + +#if defined (ARM_MATH_DSP) + *pDst++ = __QADD(*pSrc++, offset); +#else + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); +#endif + +#if defined (ARM_MATH_DSP) + *pDst++ = __QADD(*pSrc++, offset); +#else + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); +#endif + +#if defined (ARM_MATH_DSP) + *pDst++ = __QADD(*pSrc++, offset); +#else + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = __QADD(*pSrc++, offset); +#else + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicOffset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c new file mode 100644 index 0000000..f67db45 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q7.c + * Description: Q7 vector offset + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t offset_packed; /* Offset packed to 32 bit */ + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PACKq7(offset, offset, offset, offset); +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + +#if defined (ARM_MATH_DSP) + /* Add offset and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QADD8(read_q7x4_ia ((q7_t **) &pSrc), offset_packed)); +#else + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicOffset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c new file mode 100644 index 0000000..72ecbe5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f32.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicScale Vector Scale + + Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + + 
+      pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.
+
+ + In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The algorithm used with fixed-point data is: + + 
+      pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.
+
+ + The overall scale factor applied to the fixed-point data is + 
+      scale = scaleFract * 2^shift.
+
+ + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_scale_f32( + const float32_t *pSrc, + float32_t scale, + float32_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ +#if defined(ARM_MATH_NEON_EXPERIMENTAL) + float32x4_t vec1; + float32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale the input and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vmulq_f32(vec1, vdupq_n_f32(scale)); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + *pDst++ = (*pSrc++) * scale; + + *pDst++ = (*pSrc++) * scale; + + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c new file mode 100644 index 0000000..039b93d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q15.c + * Description: Multiplies a Q15 vector by a scalar + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q15 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.15 format. + These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ + +void arm_scale_q15( + const q15_t *pSrc, + q15_t scaleFract, + int8_t shift, + q15_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + int8_t kShift = 15 - shift; /* Shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t out1, out2, out3, out4; /* Temporary output variables */ + q15_t in1, in2, in3, in4; /* Temporary input variables */ +#endif +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from source */ + inA1 = read_q15x2_ia ((q15_t **) &pSrc); + inA2 = read_q15x2_ia ((q15_t **) &pSrc); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pDst, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pDst, __PKHBT(in4, in3, 16)); +#else + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c new file mode 100644 index 0000000..d762ca7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q31.c + * Description: Multiplies a Q31 vector by a scalar + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q31 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.31 format. + These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. + */ + +void arm_scale_q31( + const q31_t *pSrc, + q31_t scaleFract, + int8_t shift, + q31_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in, out; /* Temporary variables */ + int8_t kShift = shift + 1; /* Shift to apply after scaling */ + int8_t sign = (kShift & 0x80); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; /* read input from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in << kShift; /* apply shifting */ + if (in != (out >> kShift)) /* saturate the result */ + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; /* Store result destination */ + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; /* read four inputs from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in >> -kShift; /* apply shifting */ + *pDst++ = out; /* Store result destination */ + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + +} + +/** + @} end of BasicScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c new file mode 100644 index 0000000..cb967d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q7.c + * Description: Multiplies a Q7 vector by a scalar + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q7 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.7 format. + These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. + */ + +void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + int8_t kShift = 7 - shift; /* Shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t in1, in2, in3, in4; /* Temporary input variables */ + q7_t out1, out2, out3, out4; /* Temporary output variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + +#if defined (ARM_MATH_DSP) + /* Reading 4 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Scale inputs and store result in the temporary variable. */ + out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); + out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); + out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); + out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); +#else + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c new file mode 100644 index 0000000..8a15155 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c @@ -0,0 +1,201 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q15.c + * Description: Shifts the elements of a Q15 vector by a specified number of bits + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q15 vector a specified number of bits + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q15_t in1, in2; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT((in1 << shiftBits), 16), + __SSAT((in2 << shiftBits), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((in2 << shiftBits), 16), + __SSAT((in1 << shiftBits), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT((in1 << shiftBits), 16), + __SSAT((in2 << shiftBits), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((in2 << shiftBits), 16), + __SSAT((in1 << shiftBits), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} + +/** + @} end of BasicShift group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c new file mode 100644 index 0000000..db6060a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q31.c + * Description: Shifts the elements of a Q31 vector by a specified number of bits + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ +/** + @defgroup BasicShift Vector Shift + + Shifts the elements of a fixed-point vector by a specified number of bits. + There are separate functions for Q7, Q15, and Q31 data types. + The underlying algorithm used is: + + 
+      pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.
+
+ + If shift is positive then the elements of the vector are shifted to the left. + If shift is negative then the elements of the vector are shifted to the right. + + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q31 vector a specified number of bits. + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q31_t in, out; /* Temporary variables */ + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store results in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = clip_q63_to_q31((q63_t) *pSrc++ << shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} + +/** + @} end of BasicShift group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c new file mode 100644 index 0000000..c4163fc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c @@ -0,0 +1,175 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q7.c + * Description: Processing function for the Q7 Shifting + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q7 vector a specified number of bits + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par onditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t in1, in2, in3, in4; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + +#if defined (ARM_MATH_DSP) + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(__SSAT((in1 << shiftBits), 8), + __SSAT((in2 << shiftBits), 8), + __SSAT((in3 << shiftBits), 8), + __SSAT((in4 << shiftBits), 8) )); +#else + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + +#if defined (ARM_MATH_DSP) + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7((in1 >> -shiftBits), + (in2 >> -shiftBits), + (in3 >> -shiftBits), + (in4 >> -shiftBits) )); +#else + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} + +/** + @} end of BasicShift group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c new file mode 100644 index 0000000..4c97af3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f32.c + * Description: Floating-point vector subtraction + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicSub Vector Subtraction + + Element-by-element subtraction of two vectors. + + 
+      pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vsubq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c new file mode 100644 index 0000000..835917e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q15.c + * Description: Q15 vector subtraction + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q15 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t inB1, inB2; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia ((q15_t **) &pSrcA); + inA2 = read_q15x2_ia ((q15_t **) &pSrcA); + /* read 2 times 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia ((q15_t **) &pSrcB); + inB2 = read_q15x2_ia ((q15_t **) &pSrcB); + + /* Subtract and store 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, __QSUB16(inA1, inB1)); + write_q15x2_ia (&pDst, __QSUB16(inA2, inB2)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c new file mode 100644 index 0000000..bac1927 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q31.c + * Description: Q31 vector subtraction + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q31 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c new file mode 100644 index 0000000..a55a8fd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q7.c + * Description: Q7 vector subtraction + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q7 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + +#if defined (ARM_MATH_DSP) + /* Subtract and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QSUB8(read_q7x4_ia ((q7_t **) &pSrcA), read_q7x4_ia ((q7_t **) &pSrcB))); +#else + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/CMakeLists.txt new file mode 100644 index 0000000..f5c58a7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CMakeLists.txt @@ -0,0 +1,223 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSP) + +# Needed to find the config modules +list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/..) + +# Select which parts of the CMSIS-DSP must be compiled. +# There are some dependencies between the parts but they are not tracked +# by this cmake. So, enabling some functions may require to enable some +# other ones. +option(BASICMATH "Basic Math Functions" ON) +option(COMPLEXMATH "Complex Math Functions" ON) +option(CONTROLLER "Controller Functions" ON) +option(FASTMATH "Fast Math Functions" ON) +option(FILTERING "Filtering Functions" ON) +option(MATRIX "Matrix Functions" ON) +option(STATISTICS "Statistics Functions" ON) +option(SUPPORT "Support Functions" ON) +option(TRANSFORM "Transform Functions" ON) + +# When OFF it is the default behavior : all tables are included. +option(CONFIGTABLE "Configuration of table allowed" OFF) + +# When CONFIGTABLE is ON, select if all interpolation tables must be included +option(ALLFAST "All interpolation tables included" OFF) +# When CONFIGTABLE is ON, select if all FFT tables must be included +option(ALLFFT "All fft tables included" OFF) + +# Features which require inclusion of a data table. +# Since some tables may be big, the corresponding feature can be +# disabled. +# Those options are taken into account only when CONFIGTABLE is ON +option(ARM_COS_F32 "cos f32" OFF) +option(ARM_COS_Q31 "cos q31" OFF) +option(ARM_COS_Q15 "cos q15" OFF) +option(ARM_SIN_F32 "sin f32" OFF) +option(ARM_SIN_Q31 "sin q31" OFF) +option(ARM_SIN_Q15 "sin q15" OFF) +option(ARM_SIN_COS_F32 "sin cos f32" OFF) +option(ARM_SIN_COS_Q31 "sin cos q31" OFF) + +option(ARM_LMS_NORM_Q31 "lms norm q31" OFF) +option(ARM_LMS_NORM_Q15 "lms norm q15" OFF) + +option(CFFT_F32_16 "cfft f32 16" OFF) +option(CFFT_F32_32 "cfft f32 32" OFF) +option(CFFT_F32_64 "cfft f32 64" OFF) +option(CFFT_F32_128 "cfft f32 128" OFF) +option(CFFT_F32_256 "cfft f32 256" OFF) +option(CFFT_F32_512 "cfft f32 512" OFF) +option(CFFT_F32_1024 "cfft f32 1024" OFF) +option(CFFT_F32_2048 "cfft f32 2048" OFF) +option(CFFT_F32_4096 "cfft f32 4096" OFF) + +option(CFFT_Q31_16 "cfft q31 16" OFF) +option(CFFT_Q31_32 "cfft q31 32" OFF) +option(CFFT_Q31_64 "cfft q31 64" OFF) +option(CFFT_Q31_128 "cfft q31 128" OFF) +option(CFFT_Q31_256 "cfft q31 256" OFF) +option(CFFT_Q31_512 "cfft q31 512" OFF) +option(CFFT_Q31_1024 "cfft q31 1024" OFF) +option(CFFT_Q31_2048 "cfft q31 2048" OFF) +option(CFFT_Q31_4096 "cfft q31 4096" OFF) + +option(CFFT_Q15_16 "cfft q15 16" OFF) +option(CFFT_Q15_32 "cfft q15 32" OFF) +option(CFFT_Q15_64 "cfft q15 64" OFF) +option(CFFT_Q15_128 "cfft q15 128" OFF) +option(CFFT_Q15_256 "cfft q15 256" OFF) +option(CFFT_Q15_512 "cfft q15 512" OFF) +option(CFFT_Q15_1024 "cfft q15 1024" OFF) +option(CFFT_Q15_2048 "cfft q15 2048" OFF) +option(CFFT_Q15_4096 "cfft q15 4096" OFF) + +option(RFFT_FAST_F32_32 "rfft fast f32 32" OFF) +option(RFFT_FAST_F32_64 "rfft fast f32 64" OFF) +option(RFFT_FAST_F32_128 "rfft fast f32 128" OFF) +option(RFFT_FAST_F32_256 "rfft fast f32 256" OFF) +option(RFFT_FAST_F32_512 "rfft fast f32 512" OFF) +option(RFFT_FAST_F32_1024 "rfft fast f32 1024" OFF) +option(RFFT_FAST_F32_2048 "rfft fast f32 2048" OFF) +option(RFFT_FAST_F32_4096 "rfft fast f32 4096" OFF) + + +option(RFFT_F32_128 "rfft f32 128" OFF) +option(RFFT_F32_512 "rfft f32 512" OFF) +option(RFFT_F32_2048 "rfft f32 2048" OFF) +option(RFFT_F32_8192 "rfft f32 8192" OFF) + +option(RFFT_Q31_32 "rfft q31 32" OFF) +option(RFFT_Q31_64 "rfft q31 64" OFF) +option(RFFT_Q31_128 "rfft q31 128" OFF) +option(RFFT_Q31_256 "rfft q31 256" OFF) +option(RFFT_Q31_512 "rfft q31 512" OFF) +option(RFFT_Q31_1024 "rfft q31 1024" OFF) +option(RFFT_Q31_2048 "rfft q31 2048" OFF) +option(RFFT_Q31_4096 "rfft q31 4096" OFF) +option(RFFT_Q31_8192 "rfft q31 8192" OFF) + +option(RFFT_Q15_32 "rfft q15 32" OFF) +option(RFFT_Q15_64 "rfft q15 64" OFF) +option(RFFT_Q15_128 "rfft q15 128" OFF) +option(RFFT_Q15_256 "rfft q15 256" OFF) +option(RFFT_Q15_512 "rfft q15 512" OFF) +option(RFFT_Q15_1024 "rfft q15 1024" OFF) +option(RFFT_Q15_2048 "rfft q15 2048" OFF) +option(RFFT_Q15_4096 "rfft q15 4096" OFF) +option(RFFT_Q15_8192 "rfft q15 8192" OFF) + +option(DCT4_F32_128 "dct4 f32 128" OFF) +option(DCT4_F32_512 "dct4 f32 512" OFF) +option(DCT4_F32_2048 "dct4 f32 2048" OFF) +option(DCT4_F32_8192 "dct4 f32 8192" OFF) + +option(DCT4_Q31_128 "dct4 q31 128" OFF) +option(DCT4_Q31_512 "dct4 q31 512" OFF) +option(DCT4_Q31_2048 "dct4 q31 2048" OFF) +option(DCT4_Q31_8192 "dct4 q31 8192" OFF) + +option(DCT4_Q15_128 "dct4 q15 128" OFF) +option(DCT4_Q15_512 "dct4 q15 512" OFF) +option(DCT4_Q15_2048 "dct4 q15 2048" OFF) +option(DCT4_Q15_8192 "dct4 q15 8192" OFF) + + +########################### +# +# CMSIS DSP +# +########################### + +# DSP Sources +SET(DSP ".") + +add_library(CMSISDSP INTERFACE) + +include(config) + + +if (BASICMATH) + add_subdirectory(BasicMathFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPBasicMath) +endif() + +if (COMPLEXMATH) + add_subdirectory(ComplexMathFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPComplexMath) +endif() + +if (CONTROLLER) + add_subdirectory(ControllerFunctions) + # Fast tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPController PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPController) +endif() + +if (FASTMATH) + add_subdirectory(FastMathFunctions) + # Fast tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPFastMath PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPFastMath) +endif() + +if (FILTERING) + add_subdirectory(FilteringFunctions) + # Fast tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPFiltering PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPFiltering) +endif() + +if (MATRIX) + add_subdirectory(MatrixFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPMatrix) +endif() + +if (STATISTICS) + add_subdirectory(StatisticsFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPStatistics) +endif() + +if (SUPPORT) + add_subdirectory(SupportFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPSupport) +endif() + +if (TRANSFORM) + add_subdirectory(TransformFunctions) + # FFT tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_FFT_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPTransform) +endif() + +if (FILTERING OR CONTROLLER OR FASTMATH OR TRANSFORM) + add_subdirectory(CommonTables) + if (TRANSFORM) + # FFT tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_FFT_ALLOW_TABLES) + endif() + endif() + if (FILTERING OR CONTROLLER OR FASTMATH) + # Select which tables to include + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPCommon) +endif() + +### Includes +target_include_directories(CMSISDSP INTERFACE "${DSP}/../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/CommonTables/CMakeLists.txt new file mode 100644 index 0000000..7bdad93 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/CMakeLists.txt @@ -0,0 +1,31 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSPCommon) + + + +add_library(CMSISDSPCommon STATIC arm_common_tables.c) + +if (CONFIGTABLE AND ALLFFT) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_ALL_FFT_TABLES) +endif() + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_ALL_FAST_TABLES) +endif() + +include(fft) +fft(CMSISDSPCommon) + +include(interpol) +interpol(CMSISDSPCommon) + +target_sources(CMSISDSPCommon PRIVATE arm_const_structs.c) + +configdsp(CMSISDSPCommon ..) + +### Includes +target_include_directories(CMSISDSPCommon PUBLIC "${DSP}/../../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.c b/Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.c new file mode 100644 index 0000000..acda9f8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.c @@ -0,0 +1,31 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: CommonTables.c + * Description: Combination of all common table source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_common_tables.c" +#include "arm_const_structs.c" + diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c b/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c new file mode 100644 index 0000000..4b49b34 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c @@ -0,0 +1,57215 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup ComplexFFT + */ + +/** + @addtogroup CFFT_CIFFT Complex FFT Tables + @{ + */ + +/** + @par + Pseudo code for Generation of Bit reversal Table is + @par + 
for (l = 1; l <= N/4; l++)
+  {
+    for (i = 0; i< logN2; i++)
+    {
+      a[i] = l & (1 << i);
+    }
+    for (j = 0; j < logN2; j++)
+    {
+      if (a[j] != 0)
+      y[l] += (1 << ((logN2 - 1) - j));
+    }
+    y[l] = y[l] >> 1;
+   }
+ @par + where N = 4096, logN2 = 12 + @par + N is the maximum FFT Size supported +*/ + +/** + @brief Table for bit reversal process +*/ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) +const uint16_t armBitRevTable[1024] = { + 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x080, 0x480, 0x280, + 0x680, 0x180, 0x580, 0x380, 0x780, 0x040, 0x440, 0x240, 0x640, 0x140, + 0x540, 0x340, 0x740, 0x0c0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0, + 0x7c0, 0x020, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0x0a0, + 0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x060, 0x460, 0x260, + 0x660, 0x160, 0x560, 0x360, 0x760, 0x0e0, 0x4e0, 0x2e0, 0x6e0, 0x1e0, + 0x5e0, 0x3e0, 0x7e0, 0x010, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, + 0x710, 0x090, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x050, + 0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0x0d0, 0x4d0, 0x2d0, + 0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x030, 0x430, 0x230, 0x630, 0x130, + 0x530, 0x330, 0x730, 0x0b0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, + 0x7b0, 0x070, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0x0f0, + 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x008, 0x408, 0x208, + 0x608, 0x108, 0x508, 0x308, 0x708, 0x088, 0x488, 0x288, 0x688, 0x188, + 0x588, 0x388, 0x788, 0x048, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348, + 0x748, 0x0c8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x028, + 0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0x0a8, 0x4a8, 0x2a8, + 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x068, 0x468, 0x268, 0x668, 0x168, + 0x568, 0x368, 0x768, 0x0e8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8, + 0x7e8, 0x018, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x098, + 0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x058, 0x458, 0x258, + 0x658, 0x158, 0x558, 0x358, 0x758, 0x0d8, 0x4d8, 0x2d8, 0x6d8, 0x1d8, + 0x5d8, 0x3d8, 0x7d8, 0x038, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, + 0x738, 0x0b8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x078, + 0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0x0f8, 0x4f8, 0x2f8, + 0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x004, 0x404, 0x204, 0x604, 0x104, + 0x504, 0x304, 0x704, 0x084, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384, + 0x784, 0x044, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0x0c4, + 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x024, 0x424, 0x224, + 0x624, 0x124, 0x524, 0x324, 0x724, 0x0a4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, + 0x5a4, 0x3a4, 0x7a4, 0x064, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364, + 0x764, 0x0e4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x014, + 0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x094, 0x494, 0x294, + 0x694, 0x194, 0x594, 0x394, 0x794, 0x054, 0x454, 0x254, 0x654, 0x154, + 0x554, 0x354, 0x754, 0x0d4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, + 0x7d4, 0x034, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0x0b4, + 0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x074, 0x474, 0x274, + 0x674, 0x174, 0x574, 0x374, 0x774, 0x0f4, 0x4f4, 0x2f4, 0x6f4, 0x1f4, + 0x5f4, 0x3f4, 0x7f4, 0x00c, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, + 0x70c, 0x08c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x04c, + 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0x0cc, 0x4cc, 0x2cc, + 0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x02c, 0x42c, 0x22c, 0x62c, 0x12c, + 0x52c, 0x32c, 0x72c, 0x0ac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac, + 0x7ac, 0x06c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0x0ec, + 0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x01c, 0x41c, 0x21c, + 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x09c, 0x49c, 0x29c, 0x69c, 0x19c, + 0x59c, 0x39c, 0x79c, 0x05c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c, + 0x75c, 0x0dc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x03c, + 0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0x0bc, 0x4bc, 0x2bc, + 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x07c, 0x47c, 0x27c, 0x67c, 0x17c, + 0x57c, 0x37c, 0x77c, 0x0fc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, + 0x7fc, 0x002, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x082, + 0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x042, 0x442, 0x242, + 0x642, 0x142, 0x542, 0x342, 0x742, 0x0c2, 0x4c2, 0x2c2, 0x6c2, 0x1c2, + 0x5c2, 0x3c2, 0x7c2, 0x022, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322, + 0x722, 0x0a2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x062, + 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0x0e2, 0x4e2, 0x2e2, + 0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x012, 0x412, 0x212, 0x612, 0x112, + 0x512, 0x312, 0x712, 0x092, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392, + 0x792, 0x052, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0x0d2, + 0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x032, 0x432, 0x232, + 0x632, 0x132, 0x532, 0x332, 0x732, 0x0b2, 0x4b2, 0x2b2, 0x6b2, 0x1b2, + 0x5b2, 0x3b2, 0x7b2, 0x072, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, + 0x772, 0x0f2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0x00a, + 0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x08a, 0x48a, 0x28a, + 0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x04a, 0x44a, 0x24a, 0x64a, 0x14a, + 0x54a, 0x34a, 0x74a, 0x0ca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, + 0x7ca, 0x02a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 0x0aa, + 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, 0x7aa, 0x06a, 0x46a, 0x26a, + 0x66a, 0x16a, 0x56a, 0x36a, 0x76a, 0x0ea, 0x4ea, 0x2ea, 0x6ea, 0x1ea, + 0x5ea, 0x3ea, 0x7ea, 0x01a, 0x41a, 0x21a, 0x61a, 0x11a, 0x51a, 0x31a, + 0x71a, 0x09a, 0x49a, 0x29a, 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, + 0x45a, 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0x0da, 0x4da, 0x2da, + 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, 0x03a, 0x43a, 0x23a, 0x63a, 0x13a, + 0x53a, 0x33a, 0x73a, 0x0ba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, 0x3ba, + 0x7ba, 0x07a, 0x47a, 0x27a, 0x67a, 0x17a, 0x57a, 0x37a, 0x77a, 0x0fa, + 0x4fa, 0x2fa, 0x6fa, 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x006, 0x406, 0x206, + 0x606, 0x106, 0x506, 0x306, 0x706, 0x086, 0x486, 0x286, 0x686, 0x186, + 0x586, 0x386, 0x786, 0x046, 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, + 0x746, 0x0c6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, 0x7c6, 0x026, + 0x426, 0x226, 0x626, 0x126, 0x526, 0x326, 0x726, 0x0a6, 0x4a6, 0x2a6, + 0x6a6, 0x1a6, 0x5a6, 0x3a6, 0x7a6, 0x066, 0x466, 0x266, 0x666, 0x166, + 0x566, 0x366, 0x766, 0x0e6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6, + 0x7e6, 0x016, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x096, + 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x056, 0x456, 0x256, + 0x656, 0x156, 0x556, 0x356, 0x756, 0x0d6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, + 0x5d6, 0x3d6, 0x7d6, 0x036, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336, + 0x736, 0x0b6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x076, + 0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0x0f6, 0x4f6, 0x2f6, + 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0x00e, 0x40e, 0x20e, 0x60e, 0x10e, + 0x50e, 0x30e, 0x70e, 0x08e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e, + 0x78e, 0x04e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0x0ce, + 0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x02e, 0x42e, 0x22e, + 0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0x0ae, 0x4ae, 0x2ae, 0x6ae, 0x1ae, + 0x5ae, 0x3ae, 0x7ae, 0x06e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, + 0x76e, 0x0ee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x01e, + 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x09e, 0x49e, 0x29e, + 0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x05e, 0x45e, 0x25e, 0x65e, 0x15e, + 0x55e, 0x35e, 0x75e, 0x0de, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de, + 0x7de, 0x03e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0x0be, + 0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x07e, 0x47e, 0x27e, + 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0x0fe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, + 0x5fe, 0x3fe, 0x7fe, 0x001 +}; +#endif +/** + @brief Floating-point Twiddle factors Table Generation +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_16[32] = { + 1.000000000f, 0.000000000f, + 0.923879533f, 0.382683432f, + 0.707106781f, 0.707106781f, + 0.382683432f, 0.923879533f, + 0.000000000f, 1.000000000f, + -0.382683432f, 0.923879533f, + -0.707106781f, 0.707106781f, + -0.923879533f, 0.382683432f, + -1.000000000f, 0.000000000f, + -0.923879533f, -0.382683432f, + -0.707106781f, -0.707106781f, + -0.382683432f, -0.923879533f, + -0.000000000f, -1.000000000f, + 0.382683432f, -0.923879533f, + 0.707106781f, -0.707106781f, + 0.923879533f, -0.382683432f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_32[64] = { + 1.000000000f, 0.000000000f, + 0.980785280f, 0.195090322f, + 0.923879533f, 0.382683432f, + 0.831469612f, 0.555570233f, + 0.707106781f, 0.707106781f, + 0.555570233f, 0.831469612f, + 0.382683432f, 0.923879533f, + 0.195090322f, 0.980785280f, + 0.000000000f, 1.000000000f, + -0.195090322f, 0.980785280f, + -0.382683432f, 0.923879533f, + -0.555570233f, 0.831469612f, + -0.707106781f, 0.707106781f, + -0.831469612f, 0.555570233f, + -0.923879533f, 0.382683432f, + -0.980785280f, 0.195090322f, + -1.000000000f, 0.000000000f, + -0.980785280f, -0.195090322f, + -0.923879533f, -0.382683432f, + -0.831469612f, -0.555570233f, + -0.707106781f, -0.707106781f, + -0.555570233f, -0.831469612f, + -0.382683432f, -0.923879533f, + -0.195090322f, -0.980785280f, + -0.000000000f, -1.000000000f, + 0.195090322f, -0.980785280f, + 0.382683432f, -0.923879533f, + 0.555570233f, -0.831469612f, + 0.707106781f, -0.707106781f, + 0.831469612f, -0.555570233f, + 0.923879533f, -0.382683432f, + 0.980785280f, -0.195090322f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_64[128] = { + 1.000000000f, 0.000000000f, + 0.995184727f, 0.098017140f, + 0.980785280f, 0.195090322f, + 0.956940336f, 0.290284677f, + 0.923879533f, 0.382683432f, + 0.881921264f, 0.471396737f, + 0.831469612f, 0.555570233f, + 0.773010453f, 0.634393284f, + 0.707106781f, 0.707106781f, + 0.634393284f, 0.773010453f, + 0.555570233f, 0.831469612f, + 0.471396737f, 0.881921264f, + 0.382683432f, 0.923879533f, + 0.290284677f, 0.956940336f, + 0.195090322f, 0.980785280f, + 0.098017140f, 0.995184727f, + 0.000000000f, 1.000000000f, + -0.098017140f, 0.995184727f, + -0.195090322f, 0.980785280f, + -0.290284677f, 0.956940336f, + -0.382683432f, 0.923879533f, + -0.471396737f, 0.881921264f, + -0.555570233f, 0.831469612f, + -0.634393284f, 0.773010453f, + -0.707106781f, 0.707106781f, + -0.773010453f, 0.634393284f, + -0.831469612f, 0.555570233f, + -0.881921264f, 0.471396737f, + -0.923879533f, 0.382683432f, + -0.956940336f, 0.290284677f, + -0.980785280f, 0.195090322f, + -0.995184727f, 0.098017140f, + -1.000000000f, 0.000000000f, + -0.995184727f, -0.098017140f, + -0.980785280f, -0.195090322f, + -0.956940336f, -0.290284677f, + -0.923879533f, -0.382683432f, + -0.881921264f, -0.471396737f, + -0.831469612f, -0.555570233f, + -0.773010453f, -0.634393284f, + -0.707106781f, -0.707106781f, + -0.634393284f, -0.773010453f, + -0.555570233f, -0.831469612f, + -0.471396737f, -0.881921264f, + -0.382683432f, -0.923879533f, + -0.290284677f, -0.956940336f, + -0.195090322f, -0.980785280f, + -0.098017140f, -0.995184727f, + -0.000000000f, -1.000000000f, + 0.098017140f, -0.995184727f, + 0.195090322f, -0.980785280f, + 0.290284677f, -0.956940336f, + 0.382683432f, -0.923879533f, + 0.471396737f, -0.881921264f, + 0.555570233f, -0.831469612f, + 0.634393284f, -0.773010453f, + 0.707106781f, -0.707106781f, + 0.773010453f, -0.634393284f, + 0.831469612f, -0.555570233f, + 0.881921264f, -0.471396737f, + 0.923879533f, -0.382683432f, + 0.956940336f, -0.290284677f, + 0.980785280f, -0.195090322f, + 0.995184727f, -0.098017140f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_128[256] = { + 1.000000000f, 0.000000000f, + 0.998795456f, 0.049067674f, + 0.995184727f, 0.098017140f, + 0.989176510f, 0.146730474f, + 0.980785280f, 0.195090322f, + 0.970031253f, 0.242980180f, + 0.956940336f, 0.290284677f, + 0.941544065f, 0.336889853f, + 0.923879533f, 0.382683432f, + 0.903989293f, 0.427555093f, + 0.881921264f, 0.471396737f, + 0.857728610f, 0.514102744f, + 0.831469612f, 0.555570233f, + 0.803207531f, 0.595699304f, + 0.773010453f, 0.634393284f, + 0.740951125f, 0.671558955f, + 0.707106781f, 0.707106781f, + 0.671558955f, 0.740951125f, + 0.634393284f, 0.773010453f, + 0.595699304f, 0.803207531f, + 0.555570233f, 0.831469612f, + 0.514102744f, 0.857728610f, + 0.471396737f, 0.881921264f, + 0.427555093f, 0.903989293f, + 0.382683432f, 0.923879533f, + 0.336889853f, 0.941544065f, + 0.290284677f, 0.956940336f, + 0.242980180f, 0.970031253f, + 0.195090322f, 0.980785280f, + 0.146730474f, 0.989176510f, + 0.098017140f, 0.995184727f, + 0.049067674f, 0.998795456f, + 0.000000000f, 1.000000000f, + -0.049067674f, 0.998795456f, + -0.098017140f, 0.995184727f, + -0.146730474f, 0.989176510f, + -0.195090322f, 0.980785280f, + -0.242980180f, 0.970031253f, + -0.290284677f, 0.956940336f, + -0.336889853f, 0.941544065f, + -0.382683432f, 0.923879533f, + -0.427555093f, 0.903989293f, + -0.471396737f, 0.881921264f, + -0.514102744f, 0.857728610f, + -0.555570233f, 0.831469612f, + -0.595699304f, 0.803207531f, + -0.634393284f, 0.773010453f, + -0.671558955f, 0.740951125f, + -0.707106781f, 0.707106781f, + -0.740951125f, 0.671558955f, + -0.773010453f, 0.634393284f, + -0.803207531f, 0.595699304f, + -0.831469612f, 0.555570233f, + -0.857728610f, 0.514102744f, + -0.881921264f, 0.471396737f, + -0.903989293f, 0.427555093f, + -0.923879533f, 0.382683432f, + -0.941544065f, 0.336889853f, + -0.956940336f, 0.290284677f, + -0.970031253f, 0.242980180f, + -0.980785280f, 0.195090322f, + -0.989176510f, 0.146730474f, + -0.995184727f, 0.098017140f, + -0.998795456f, 0.049067674f, + -1.000000000f, 0.000000000f, + -0.998795456f, -0.049067674f, + -0.995184727f, -0.098017140f, + -0.989176510f, -0.146730474f, + -0.980785280f, -0.195090322f, + -0.970031253f, -0.242980180f, + -0.956940336f, -0.290284677f, + -0.941544065f, -0.336889853f, + -0.923879533f, -0.382683432f, + -0.903989293f, -0.427555093f, + -0.881921264f, -0.471396737f, + -0.857728610f, -0.514102744f, + -0.831469612f, -0.555570233f, + -0.803207531f, -0.595699304f, + -0.773010453f, -0.634393284f, + -0.740951125f, -0.671558955f, + -0.707106781f, -0.707106781f, + -0.671558955f, -0.740951125f, + -0.634393284f, -0.773010453f, + -0.595699304f, -0.803207531f, + -0.555570233f, -0.831469612f, + -0.514102744f, -0.857728610f, + -0.471396737f, -0.881921264f, + -0.427555093f, -0.903989293f, + -0.382683432f, -0.923879533f, + -0.336889853f, -0.941544065f, + -0.290284677f, -0.956940336f, + -0.242980180f, -0.970031253f, + -0.195090322f, -0.980785280f, + -0.146730474f, -0.989176510f, + -0.098017140f, -0.995184727f, + -0.049067674f, -0.998795456f, + -0.000000000f, -1.000000000f, + 0.049067674f, -0.998795456f, + 0.098017140f, -0.995184727f, + 0.146730474f, -0.989176510f, + 0.195090322f, -0.980785280f, + 0.242980180f, -0.970031253f, + 0.290284677f, -0.956940336f, + 0.336889853f, -0.941544065f, + 0.382683432f, -0.923879533f, + 0.427555093f, -0.903989293f, + 0.471396737f, -0.881921264f, + 0.514102744f, -0.857728610f, + 0.555570233f, -0.831469612f, + 0.595699304f, -0.803207531f, + 0.634393284f, -0.773010453f, + 0.671558955f, -0.740951125f, + 0.707106781f, -0.707106781f, + 0.740951125f, -0.671558955f, + 0.773010453f, -0.634393284f, + 0.803207531f, -0.595699304f, + 0.831469612f, -0.555570233f, + 0.857728610f, -0.514102744f, + 0.881921264f, -0.471396737f, + 0.903989293f, -0.427555093f, + 0.923879533f, -0.382683432f, + 0.941544065f, -0.336889853f, + 0.956940336f, -0.290284677f, + 0.970031253f, -0.242980180f, + 0.980785280f, -0.195090322f, + 0.989176510f, -0.146730474f, + 0.995184727f, -0.098017140f, + 0.998795456f, -0.049067674f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_256[512] = { + 1.000000000f, 0.000000000f, + 0.999698819f, 0.024541229f, + 0.998795456f, 0.049067674f, + 0.997290457f, 0.073564564f, + 0.995184727f, 0.098017140f, + 0.992479535f, 0.122410675f, + 0.989176510f, 0.146730474f, + 0.985277642f, 0.170961889f, + 0.980785280f, 0.195090322f, + 0.975702130f, 0.219101240f, + 0.970031253f, 0.242980180f, + 0.963776066f, 0.266712757f, + 0.956940336f, 0.290284677f, + 0.949528181f, 0.313681740f, + 0.941544065f, 0.336889853f, + 0.932992799f, 0.359895037f, + 0.923879533f, 0.382683432f, + 0.914209756f, 0.405241314f, + 0.903989293f, 0.427555093f, + 0.893224301f, 0.449611330f, + 0.881921264f, 0.471396737f, + 0.870086991f, 0.492898192f, + 0.857728610f, 0.514102744f, + 0.844853565f, 0.534997620f, + 0.831469612f, 0.555570233f, + 0.817584813f, 0.575808191f, + 0.803207531f, 0.595699304f, + 0.788346428f, 0.615231591f, + 0.773010453f, 0.634393284f, + 0.757208847f, 0.653172843f, + 0.740951125f, 0.671558955f, + 0.724247083f, 0.689540545f, + 0.707106781f, 0.707106781f, + 0.689540545f, 0.724247083f, + 0.671558955f, 0.740951125f, + 0.653172843f, 0.757208847f, + 0.634393284f, 0.773010453f, + 0.615231591f, 0.788346428f, + 0.595699304f, 0.803207531f, + 0.575808191f, 0.817584813f, + 0.555570233f, 0.831469612f, + 0.534997620f, 0.844853565f, + 0.514102744f, 0.857728610f, + 0.492898192f, 0.870086991f, + 0.471396737f, 0.881921264f, + 0.449611330f, 0.893224301f, + 0.427555093f, 0.903989293f, + 0.405241314f, 0.914209756f, + 0.382683432f, 0.923879533f, + 0.359895037f, 0.932992799f, + 0.336889853f, 0.941544065f, + 0.313681740f, 0.949528181f, + 0.290284677f, 0.956940336f, + 0.266712757f, 0.963776066f, + 0.242980180f, 0.970031253f, + 0.219101240f, 0.975702130f, + 0.195090322f, 0.980785280f, + 0.170961889f, 0.985277642f, + 0.146730474f, 0.989176510f, + 0.122410675f, 0.992479535f, + 0.098017140f, 0.995184727f, + 0.073564564f, 0.997290457f, + 0.049067674f, 0.998795456f, + 0.024541229f, 0.999698819f, + 0.000000000f, 1.000000000f, + -0.024541229f, 0.999698819f, + -0.049067674f, 0.998795456f, + -0.073564564f, 0.997290457f, + -0.098017140f, 0.995184727f, + -0.122410675f, 0.992479535f, + -0.146730474f, 0.989176510f, + -0.170961889f, 0.985277642f, + -0.195090322f, 0.980785280f, + -0.219101240f, 0.975702130f, + -0.242980180f, 0.970031253f, + -0.266712757f, 0.963776066f, + -0.290284677f, 0.956940336f, + -0.313681740f, 0.949528181f, + -0.336889853f, 0.941544065f, + -0.359895037f, 0.932992799f, + -0.382683432f, 0.923879533f, + -0.405241314f, 0.914209756f, + -0.427555093f, 0.903989293f, + -0.449611330f, 0.893224301f, + -0.471396737f, 0.881921264f, + -0.492898192f, 0.870086991f, + -0.514102744f, 0.857728610f, + -0.534997620f, 0.844853565f, + -0.555570233f, 0.831469612f, + -0.575808191f, 0.817584813f, + -0.595699304f, 0.803207531f, + -0.615231591f, 0.788346428f, + -0.634393284f, 0.773010453f, + -0.653172843f, 0.757208847f, + -0.671558955f, 0.740951125f, + -0.689540545f, 0.724247083f, + -0.707106781f, 0.707106781f, + -0.724247083f, 0.689540545f, + -0.740951125f, 0.671558955f, + -0.757208847f, 0.653172843f, + -0.773010453f, 0.634393284f, + -0.788346428f, 0.615231591f, + -0.803207531f, 0.595699304f, + -0.817584813f, 0.575808191f, + -0.831469612f, 0.555570233f, + -0.844853565f, 0.534997620f, + -0.857728610f, 0.514102744f, + -0.870086991f, 0.492898192f, + -0.881921264f, 0.471396737f, + -0.893224301f, 0.449611330f, + -0.903989293f, 0.427555093f, + -0.914209756f, 0.405241314f, + -0.923879533f, 0.382683432f, + -0.932992799f, 0.359895037f, + -0.941544065f, 0.336889853f, + -0.949528181f, 0.313681740f, + -0.956940336f, 0.290284677f, + -0.963776066f, 0.266712757f, + -0.970031253f, 0.242980180f, + -0.975702130f, 0.219101240f, + -0.980785280f, 0.195090322f, + -0.985277642f, 0.170961889f, + -0.989176510f, 0.146730474f, + -0.992479535f, 0.122410675f, + -0.995184727f, 0.098017140f, + -0.997290457f, 0.073564564f, + -0.998795456f, 0.049067674f, + -0.999698819f, 0.024541229f, + -1.000000000f, 0.000000000f, + -0.999698819f, -0.024541229f, + -0.998795456f, -0.049067674f, + -0.997290457f, -0.073564564f, + -0.995184727f, -0.098017140f, + -0.992479535f, -0.122410675f, + -0.989176510f, -0.146730474f, + -0.985277642f, -0.170961889f, + -0.980785280f, -0.195090322f, + -0.975702130f, -0.219101240f, + -0.970031253f, -0.242980180f, + -0.963776066f, -0.266712757f, + -0.956940336f, -0.290284677f, + -0.949528181f, -0.313681740f, + -0.941544065f, -0.336889853f, + -0.932992799f, -0.359895037f, + -0.923879533f, -0.382683432f, + -0.914209756f, -0.405241314f, + -0.903989293f, -0.427555093f, + -0.893224301f, -0.449611330f, + -0.881921264f, -0.471396737f, + -0.870086991f, -0.492898192f, + -0.857728610f, -0.514102744f, + -0.844853565f, -0.534997620f, + -0.831469612f, -0.555570233f, + -0.817584813f, -0.575808191f, + -0.803207531f, -0.595699304f, + -0.788346428f, -0.615231591f, + -0.773010453f, -0.634393284f, + -0.757208847f, -0.653172843f, + -0.740951125f, -0.671558955f, + -0.724247083f, -0.689540545f, + -0.707106781f, -0.707106781f, + -0.689540545f, -0.724247083f, + -0.671558955f, -0.740951125f, + -0.653172843f, -0.757208847f, + -0.634393284f, -0.773010453f, + -0.615231591f, -0.788346428f, + -0.595699304f, -0.803207531f, + -0.575808191f, -0.817584813f, + -0.555570233f, -0.831469612f, + -0.534997620f, -0.844853565f, + -0.514102744f, -0.857728610f, + -0.492898192f, -0.870086991f, + -0.471396737f, -0.881921264f, + -0.449611330f, -0.893224301f, + -0.427555093f, -0.903989293f, + -0.405241314f, -0.914209756f, + -0.382683432f, -0.923879533f, + -0.359895037f, -0.932992799f, + -0.336889853f, -0.941544065f, + -0.313681740f, -0.949528181f, + -0.290284677f, -0.956940336f, + -0.266712757f, -0.963776066f, + -0.242980180f, -0.970031253f, + -0.219101240f, -0.975702130f, + -0.195090322f, -0.980785280f, + -0.170961889f, -0.985277642f, + -0.146730474f, -0.989176510f, + -0.122410675f, -0.992479535f, + -0.098017140f, -0.995184727f, + -0.073564564f, -0.997290457f, + -0.049067674f, -0.998795456f, + -0.024541229f, -0.999698819f, + -0.000000000f, -1.000000000f, + 0.024541229f, -0.999698819f, + 0.049067674f, -0.998795456f, + 0.073564564f, -0.997290457f, + 0.098017140f, -0.995184727f, + 0.122410675f, -0.992479535f, + 0.146730474f, -0.989176510f, + 0.170961889f, -0.985277642f, + 0.195090322f, -0.980785280f, + 0.219101240f, -0.975702130f, + 0.242980180f, -0.970031253f, + 0.266712757f, -0.963776066f, + 0.290284677f, -0.956940336f, + 0.313681740f, -0.949528181f, + 0.336889853f, -0.941544065f, + 0.359895037f, -0.932992799f, + 0.382683432f, -0.923879533f, + 0.405241314f, -0.914209756f, + 0.427555093f, -0.903989293f, + 0.449611330f, -0.893224301f, + 0.471396737f, -0.881921264f, + 0.492898192f, -0.870086991f, + 0.514102744f, -0.857728610f, + 0.534997620f, -0.844853565f, + 0.555570233f, -0.831469612f, + 0.575808191f, -0.817584813f, + 0.595699304f, -0.803207531f, + 0.615231591f, -0.788346428f, + 0.634393284f, -0.773010453f, + 0.653172843f, -0.757208847f, + 0.671558955f, -0.740951125f, + 0.689540545f, -0.724247083f, + 0.707106781f, -0.707106781f, + 0.724247083f, -0.689540545f, + 0.740951125f, -0.671558955f, + 0.757208847f, -0.653172843f, + 0.773010453f, -0.634393284f, + 0.788346428f, -0.615231591f, + 0.803207531f, -0.595699304f, + 0.817584813f, -0.575808191f, + 0.831469612f, -0.555570233f, + 0.844853565f, -0.534997620f, + 0.857728610f, -0.514102744f, + 0.870086991f, -0.492898192f, + 0.881921264f, -0.471396737f, + 0.893224301f, -0.449611330f, + 0.903989293f, -0.427555093f, + 0.914209756f, -0.405241314f, + 0.923879533f, -0.382683432f, + 0.932992799f, -0.359895037f, + 0.941544065f, -0.336889853f, + 0.949528181f, -0.313681740f, + 0.956940336f, -0.290284677f, + 0.963776066f, -0.266712757f, + 0.970031253f, -0.242980180f, + 0.975702130f, -0.219101240f, + 0.980785280f, -0.195090322f, + 0.985277642f, -0.170961889f, + 0.989176510f, -0.146730474f, + 0.992479535f, -0.122410675f, + 0.995184727f, -0.098017140f, + 0.997290457f, -0.073564564f, + 0.998795456f, -0.049067674f, + 0.999698819f, -0.024541229f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_512[1024] = { + 1.000000000f, 0.000000000f, + 0.999924702f, 0.012271538f, + 0.999698819f, 0.024541229f, + 0.999322385f, 0.036807223f, + 0.998795456f, 0.049067674f, + 0.998118113f, 0.061320736f, + 0.997290457f, 0.073564564f, + 0.996312612f, 0.085797312f, + 0.995184727f, 0.098017140f, + 0.993906970f, 0.110222207f, + 0.992479535f, 0.122410675f, + 0.990902635f, 0.134580709f, + 0.989176510f, 0.146730474f, + 0.987301418f, 0.158858143f, + 0.985277642f, 0.170961889f, + 0.983105487f, 0.183039888f, + 0.980785280f, 0.195090322f, + 0.978317371f, 0.207111376f, + 0.975702130f, 0.219101240f, + 0.972939952f, 0.231058108f, + 0.970031253f, 0.242980180f, + 0.966976471f, 0.254865660f, + 0.963776066f, 0.266712757f, + 0.960430519f, 0.278519689f, + 0.956940336f, 0.290284677f, + 0.953306040f, 0.302005949f, + 0.949528181f, 0.313681740f, + 0.945607325f, 0.325310292f, + 0.941544065f, 0.336889853f, + 0.937339012f, 0.348418680f, + 0.932992799f, 0.359895037f, + 0.928506080f, 0.371317194f, + 0.923879533f, 0.382683432f, + 0.919113852f, 0.393992040f, + 0.914209756f, 0.405241314f, + 0.909167983f, 0.416429560f, + 0.903989293f, 0.427555093f, + 0.898674466f, 0.438616239f, + 0.893224301f, 0.449611330f, + 0.887639620f, 0.460538711f, + 0.881921264f, 0.471396737f, + 0.876070094f, 0.482183772f, + 0.870086991f, 0.492898192f, + 0.863972856f, 0.503538384f, + 0.857728610f, 0.514102744f, + 0.851355193f, 0.524589683f, + 0.844853565f, 0.534997620f, + 0.838224706f, 0.545324988f, + 0.831469612f, 0.555570233f, + 0.824589303f, 0.565731811f, + 0.817584813f, 0.575808191f, + 0.810457198f, 0.585797857f, + 0.803207531f, 0.595699304f, + 0.795836905f, 0.605511041f, + 0.788346428f, 0.615231591f, + 0.780737229f, 0.624859488f, + 0.773010453f, 0.634393284f, + 0.765167266f, 0.643831543f, + 0.757208847f, 0.653172843f, + 0.749136395f, 0.662415778f, + 0.740951125f, 0.671558955f, + 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0.405241314f, 0.914209756f, + 0.393992040f, 0.919113852f, + 0.382683432f, 0.923879533f, + 0.371317194f, 0.928506080f, + 0.359895037f, 0.932992799f, + 0.348418680f, 0.937339012f, + 0.336889853f, 0.941544065f, + 0.325310292f, 0.945607325f, + 0.313681740f, 0.949528181f, + 0.302005949f, 0.953306040f, + 0.290284677f, 0.956940336f, + 0.278519689f, 0.960430519f, + 0.266712757f, 0.963776066f, + 0.254865660f, 0.966976471f, + 0.242980180f, 0.970031253f, + 0.231058108f, 0.972939952f, + 0.219101240f, 0.975702130f, + 0.207111376f, 0.978317371f, + 0.195090322f, 0.980785280f, + 0.183039888f, 0.983105487f, + 0.170961889f, 0.985277642f, + 0.158858143f, 0.987301418f, + 0.146730474f, 0.989176510f, + 0.134580709f, 0.990902635f, + 0.122410675f, 0.992479535f, + 0.110222207f, 0.993906970f, + 0.098017140f, 0.995184727f, + 0.085797312f, 0.996312612f, + 0.073564564f, 0.997290457f, + 0.061320736f, 0.998118113f, + 0.049067674f, 0.998795456f, + 0.036807223f, 0.999322385f, + 0.024541229f, 0.999698819f, + 0.012271538f, 0.999924702f, + 0.000000000f, 1.000000000f, + -0.012271538f, 0.999924702f, + -0.024541229f, 0.999698819f, + -0.036807223f, 0.999322385f, + -0.049067674f, 0.998795456f, + -0.061320736f, 0.998118113f, + -0.073564564f, 0.997290457f, + -0.085797312f, 0.996312612f, + -0.098017140f, 0.995184727f, + -0.110222207f, 0.993906970f, + -0.122410675f, 0.992479535f, + -0.134580709f, 0.990902635f, + -0.146730474f, 0.989176510f, + -0.158858143f, 0.987301418f, + -0.170961889f, 0.985277642f, + -0.183039888f, 0.983105487f, + -0.195090322f, 0.980785280f, + -0.207111376f, 0.978317371f, + -0.219101240f, 0.975702130f, + -0.231058108f, 0.972939952f, + -0.242980180f, 0.970031253f, + -0.254865660f, 0.966976471f, + -0.266712757f, 0.963776066f, + -0.278519689f, 0.960430519f, + -0.290284677f, 0.956940336f, + -0.302005949f, 0.953306040f, + -0.313681740f, 0.949528181f, + -0.325310292f, 0.945607325f, + -0.336889853f, 0.941544065f, + -0.348418680f, 0.937339012f, + -0.359895037f, 0.932992799f, + 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0.998118113f, -0.061320736f, + 0.998795456f, -0.049067674f, + 0.999322385f, -0.036807223f, + 0.999698819f, -0.024541229f, + 0.999924702f, -0.012271538f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_1024[2048] = { + 1.000000000f, 0.000000000f, + 0.999981175f, 0.006135885f, + 0.999924702f, 0.012271538f, + 0.999830582f, 0.018406730f, + 0.999698819f, 0.024541229f, + 0.999529418f, 0.030674803f, + 0.999322385f, 0.036807223f, + 0.999077728f, 0.042938257f, + 0.998795456f, 0.049067674f, + 0.998475581f, 0.055195244f, + 0.998118113f, 0.061320736f, + 0.997723067f, 0.067443920f, + 0.997290457f, 0.073564564f, + 0.996820299f, 0.079682438f, + 0.996312612f, 0.085797312f, + 0.995767414f, 0.091908956f, + 0.995184727f, 0.098017140f, + 0.994564571f, 0.104121634f, + 0.993906970f, 0.110222207f, + 0.993211949f, 0.116318631f, + 0.992479535f, 0.122410675f, + 0.991709754f, 0.128498111f, + 0.990902635f, 0.134580709f, + 0.990058210f, 0.140658239f, + 0.989176510f, 0.146730474f, + 0.988257568f, 0.152797185f, + 0.987301418f, 0.158858143f, + 0.986308097f, 0.164913120f, + 0.985277642f, 0.170961889f, + 0.984210092f, 0.177004220f, + 0.983105487f, 0.183039888f, + 0.981963869f, 0.189068664f, + 0.980785280f, 0.195090322f, + 0.979569766f, 0.201104635f, + 0.978317371f, 0.207111376f, + 0.977028143f, 0.213110320f, + 0.975702130f, 0.219101240f, + 0.974339383f, 0.225083911f, + 0.972939952f, 0.231058108f, + 0.971503891f, 0.237023606f, + 0.970031253f, 0.242980180f, + 0.968522094f, 0.248927606f, + 0.966976471f, 0.254865660f, + 0.965394442f, 0.260794118f, + 0.963776066f, 0.266712757f, + 0.962121404f, 0.272621355f, + 0.960430519f, 0.278519689f, + 0.958703475f, 0.284407537f, + 0.956940336f, 0.290284677f, + 0.955141168f, 0.296150888f, + 0.953306040f, 0.302005949f, + 0.951435021f, 0.307849640f, + 0.949528181f, 0.313681740f, + 0.947585591f, 0.319502031f, + 0.945607325f, 0.325310292f, + 0.943593458f, 0.331106306f, + 0.941544065f, 0.336889853f, + 0.939459224f, 0.342660717f, + 0.937339012f, 0.348418680f, + 0.935183510f, 0.354163525f, + 0.932992799f, 0.359895037f, + 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0.999529418f, -0.030674803f, + 0.999698819f, -0.024541229f, + 0.999830582f, -0.018406730f, + 0.999924702f, -0.012271538f, + 0.999981175f, -0.006135885f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_2048[4096] = { + 1.000000000f, 0.000000000f, + 0.999995294f, 0.003067957f, + 0.999981175f, 0.006135885f, + 0.999957645f, 0.009203755f, + 0.999924702f, 0.012271538f, + 0.999882347f, 0.015339206f, + 0.999830582f, 0.018406730f, + 0.999769405f, 0.021474080f, + 0.999698819f, 0.024541229f, + 0.999618822f, 0.027608146f, + 0.999529418f, 0.030674803f, + 0.999430605f, 0.033741172f, + 0.999322385f, 0.036807223f, + 0.999204759f, 0.039872928f, + 0.999077728f, 0.042938257f, + 0.998941293f, 0.046003182f, + 0.998795456f, 0.049067674f, + 0.998640218f, 0.052131705f, + 0.998475581f, 0.055195244f, + 0.998301545f, 0.058258265f, + 0.998118113f, 0.061320736f, + 0.997925286f, 0.064382631f, + 0.997723067f, 0.067443920f, + 0.997511456f, 0.070504573f, + 0.997290457f, 0.073564564f, + 0.997060070f, 0.076623861f, + 0.996820299f, 0.079682438f, + 0.996571146f, 0.082740265f, + 0.996312612f, 0.085797312f, + 0.996044701f, 0.088853553f, + 0.995767414f, 0.091908956f, + 0.995480755f, 0.094963495f, + 0.995184727f, 0.098017140f, + 0.994879331f, 0.101069863f, + 0.994564571f, 0.104121634f, + 0.994240449f, 0.107172425f, + 0.993906970f, 0.110222207f, + 0.993564136f, 0.113270952f, + 0.993211949f, 0.116318631f, + 0.992850414f, 0.119365215f, + 0.992479535f, 0.122410675f, + 0.992099313f, 0.125454983f, + 0.991709754f, 0.128498111f, + 0.991310860f, 0.131540029f, + 0.990902635f, 0.134580709f, + 0.990485084f, 0.137620122f, + 0.990058210f, 0.140658239f, + 0.989622017f, 0.143695033f, + 0.989176510f, 0.146730474f, + 0.988721692f, 0.149764535f, + 0.988257568f, 0.152797185f, + 0.987784142f, 0.155828398f, + 0.987301418f, 0.158858143f, + 0.986809402f, 0.161886394f, + 0.986308097f, 0.164913120f, + 0.985797509f, 0.167938295f, + 0.985277642f, 0.170961889f, + 0.984748502f, 0.173983873f, + 0.984210092f, 0.177004220f, + 0.983662419f, 0.180022901f, + 0.983105487f, 0.183039888f, + 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0.999882347f, -0.015339206f, + 0.999924702f, -0.012271538f, + 0.999957645f, -0.009203755f, + 0.999981175f, -0.006135885f, + 0.999995294f, -0.003067957f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_4096[8192] = { + 1.000000000f, 0.000000000f, + 0.999998823f, 0.001533980f, + 0.999995294f, 0.003067957f, + 0.999989411f, 0.004601926f, + 0.999981175f, 0.006135885f, + 0.999970586f, 0.007669829f, + 0.999957645f, 0.009203755f, + 0.999942350f, 0.010737659f, + 0.999924702f, 0.012271538f, + 0.999904701f, 0.013805389f, + 0.999882347f, 0.015339206f, + 0.999857641f, 0.016872988f, + 0.999830582f, 0.018406730f, + 0.999801170f, 0.019940429f, + 0.999769405f, 0.021474080f, + 0.999735288f, 0.023007681f, + 0.999698819f, 0.024541229f, + 0.999659997f, 0.026074718f, + 0.999618822f, 0.027608146f, + 0.999575296f, 0.029141509f, + 0.999529418f, 0.030674803f, + 0.999481187f, 0.032208025f, + 0.999430605f, 0.033741172f, + 0.999377670f, 0.035274239f, + 0.999322385f, 0.036807223f, + 0.999264747f, 0.038340120f, + 0.999204759f, 0.039872928f, + 0.999142419f, 0.041405641f, + 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0.999957645f, -0.009203755f, + 0.999970586f, -0.007669829f, + 0.999981175f, -0.006135885f, + 0.999989411f, -0.004601926f, + 0.999995294f, -0.003067957f, + 0.999998823f, -0.001533980f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +/** + @brief Q31 Twiddle factors Table +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
 for(i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_16_q31[24] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_32_q31[48] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xB8E31319, (q31_t)0x9592675B, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xE70747C3, (q31_t)0x8275A0C0 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_64_q31[96] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xF3742CA1, (q31_t)0x809DC970 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i < 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_128_q31[192] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF9B82683, (q31_t)0x80277872 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_256_q31[384] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xED37EF91, + (q31_t)0x7E9D55FC, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE3F47D95, + (q31_t)0x7CE3CEB1, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xD7D946D7, (q31_t)0x798A23B1, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD1EEF59E, + (q31_t)0x776C4EDB, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xC945DFEC, + (q31_t)0x73B5EBD0, (q31_t)0xC67322CD, (q31_t)0x72552C84, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC0E8B648, + (q31_t)0x6F5F02B1, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xB64BEACC, (q31_t)0x68A69E81, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB140175B, + (q31_t)0x64E88926, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAA0A5B2D, + (q31_t)0x5ED77C89, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA34BDF20, + (q31_t)0x5842DD54, (q31_t)0xA1288376, (q31_t)0x55F5A4D2, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9759617E, + (q31_t)0x49B41533, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9235F2EB, + (q31_t)0x41CE1E64, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8DAAD37B, + (q31_t)0x398CDD32, (q31_t)0x8C4A142F, (q31_t)0x36BA2013, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8893B124, (q31_t)0x2E110A62, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8675DC4E, + (q31_t)0x2826B928, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x83D60411, + (q31_t)0x1F19F97B, (q31_t)0x831C314E, (q31_t)0x1C0B826A, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x81E26C16, + (q31_t)0x15E21444, (q31_t)0x8162AA03, (q31_t)0x12C8106E, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x8058C94C, (q31_t)0x096A9049, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8009DE7D, + (q31_t)0x03242ABF, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80277872, + (q31_t)0xF9B82683, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_512_q31[768] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + 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(q31_t)0x812A1A39, (q31_t)0x1139F0CE, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80C7A80A, + (q31_t)0x0E1BC2E3, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x8058C94C, + (q31_t)0x096A9049, (q31_t)0x803DAA69, (q31_t)0x07D95B9E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80163440, + (q31_t)0x04B6195D, (q31_t)0x8009DE7D, (q31_t)0x03242ABF, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80163440, + (q31_t)0xFB49E6A2, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8058C94C, + (q31_t)0xF6956FB6, (q31_t)0x8078D40D, (q31_t)0xF50497FA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80C7A80A, + (q31_t)0xF1E43D1C, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82299971, + (q31_t)0xE8922621, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x831C314E, + (q31_t)0xE3F47D95, (q31_t)0x8376B422, (q31_t)0xE26CB01A, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x843A1D70, + (q31_t)0xDF608FE3, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x85FA1152, (q31_t)0xD957DE7A, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86F656D3, + (q31_t)0xD65C3B7B, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8893B124, + (q31_t)0xD1EEF59E, (q31_t)0x8926B677, (q31_t)0xD078AD9D, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A5A7A30, + (q31_t)0xCD91AB38, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E61D32D, + (q31_t)0xC50D1148, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x90A0FD4E, + (q31_t)0xC0E8B648, (q31_t)0x91695663, (q31_t)0xBF8C0DE2, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9306CB04, + (q31_t)0xBCDA3ECA, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x9673DB94, (q31_t)0xB796199B, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x9842F043, + (q31_t)0xB5049368, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9B1776D9, + (q31_t)0xB140175B, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9E0EFFC1, + (q31_t)0xAD96ED91, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA2386283, (q31_t)0xA8E21106, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA462EEAC, + (q31_t)0xA69B9B68, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA7BD22AB, + (q31_t)0xA34BDF20, (q31_t)0xA8E21106, (q31_t)0xA2386283, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAB35F5B5, + (q31_t)0xA01C4C72, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB27E9D3B, + (q31_t)0x9A22042C, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB64BEACC, + (q31_t)0x9759617E, (q31_t)0xB796199B, (q31_t)0x9673DB94, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBA32CA70, + (q31_t)0x94B50D87, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_1024_q31[1536] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2191B4, + (q31_t)0x0EE38765, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7ED5E5C6, + (q31_t)0x1139F0CE, (q31_t)0x7EBA3A39, (q31_t)0x120116D4, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E7F3956, + (q31_t)0x138EDBB0, (q31_t)0x7E5FE493, (q31_t)0x145576B1, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7DFA98A7, (q31_t)0x16A81305, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DB0FDF7, + (q31_t)0x183366E8, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D3980EC, + (q31_t)0x1A82A025, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CB72724, + (q31_t)0x1CCF8CB3, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B920B89, + (q31_t)0x2161B39F, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7AEF6323, + (q31_t)0x23A6887E, (q31_t)0x7AB6CBA3, (q31_t)0x24677757, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A4210D8, + (q31_t)0x25E845B5, (q31_t)0x7A05EEAD, (q31_t)0x26A82185, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x794A7C11, (q31_t)0x28E5714A, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78C7ABA1, + (q31_t)0x2A61B101, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x77FAB988, + (q31_t)0x2C98FBBA, (q31_t)0x77B417DF, (q31_t)0x2D553AFB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x77235F2D, + (q31_t)0x2ECC681E, (q31_t)0x76D94988, (q31_t)0x2F875262, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7555BD4B, + (q31_t)0x3326E2C2, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x745F9DD1, + (q31_t)0x354D9056, (q31_t)0x740B53FA, (q31_t)0x36041AD9, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x735F6626, + (q31_t)0x376F9E46, (q31_t)0x7307C3D0, (q31_t)0x382493B0, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x71FA3948, (q31_t)0x3A402DD1, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x71410804, + (q31_t)0x3BA51E29, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70231099, + (q31_t)0x3DB832A5, (q31_t)0x6FC19385, (q31_t)0x3E680B2C, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6EFB5F12, + (q31_t)0x3FC5EC97, (q31_t)0x6E96A99C, (q31_t)0x4073F21D, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6D6227FA, (q31_t)0x427A41D0, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C8F351C, + (q31_t)0x43D09AEC, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B4AF278, + (q31_t)0x45CD358F, (q31_t)0x6ADCC964, (q31_t)0x46756827, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x69FD614A, + (q31_t)0x47C3C22E, (q31_t)0x698C246C, (q31_t)0x4869E664, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x683257AA, (q31_t)0x4A581C9D, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x6746C7D7, + (q31_t)0x4B9E038F, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x65DDFBD3, + (q31_t)0x4D8162C4, (q31_t)0x6563BF92, (q31_t)0x4E210617, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x646C59BF, + (q31_t)0x4F5E08E3, (q31_t)0x63EF328F, (q31_t)0x4FFB654D, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x6271FA69, (q31_t)0x51CED46E, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x616F146B, + (q31_t)0x53028517, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x5FE3B38D, + (q31_t)0x54CA0A4A, (q31_t)0x5F5E0DB3, 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(q31_t)0xF8EF5CBB, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x804A9C4D, + (q31_t)0xF75DFF65, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x8078D40D, + (q31_t)0xF50497FA, (q31_t)0x808AB180, (q31_t)0xF43C53CA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80B21BAF, + (q31_t)0xF2AC246D, (q31_t)0x80C7A80A, (q31_t)0xF1E43D1C, + (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x810FA7A0, (q31_t)0xEF8D5FB8, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8145C5C6, + (q31_t)0xEDFEE92B, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81A01B6C, + (q31_t)0xEBAA894E, (q31_t)0x81C0A801, (q31_t)0xEAE4207A, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82056758, + (q31_t)0xE957ECFB, (q31_t)0x82299971, (q31_t)0xE8922621, + (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x829D753A, (q31_t)0xE642340D, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82F0BDE8, + (q31_t)0xE4B8CD10, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x8376B422, + (q31_t)0xE26CB01A, (q31_t)0x83A5C2B0, (q31_t)0xE1A935E1, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x840777CF, + (q31_t)0xE02323E5, (q31_t)0x843A1D70, (q31_t)0xDF608FE3, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x84D934B0, (q31_t)0xDD1ABE51, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8549345C, + (q31_t)0xDB9888A8, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85FA1152, + (q31_t)0xD957DE7A, (q31_t)0x86376092, (q31_t)0xD898620C, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86B583EE, + (q31_t)0xD71A8EB5, (q31_t)0x86F656D3, (q31_t)0xD65C3B7B, + (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x87BFCCD7, (q31_t)0xD423B190, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x884BE820, + (q31_t)0xD2AAC504, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x8926B677, + (q31_t)0xD078AD9D, (q31_t)0x8971F15A, (q31_t)0xCFBE389F, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A0BD3F5, + (q31_t)0xCE4AB5A2, (q31_t)0x8A5A7A30, (q31_t)0xCD91AB38, + (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8B4D377C, (q31_t)0xCB697DB0, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BF4AC05, + (q31_t)0xC9FBE527, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CF83C30, + (q31_t)0xC7DB6C50, (q31_t)0x8D50FA59, (q31_t)0xC727016C, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E05C6B7, + (q31_t)0xC5BFD22E, (q31_t)0x8E61D32D, (q31_t)0xC50D1148, + (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x8F7C8701, (q31_t)0xC2F83E2A, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x903E6C7A, + (q31_t)0xC197F4D3, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x91695663, + (q31_t)0xBF8C0DE2, (q31_t)0x91CF1CB6, (q31_t)0xBEDEA765, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x929DD805, + (q31_t)0xBD85BE2F, (q31_t)0x9306CB04, (q31_t)0xBCDA3ECA, + (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9447ED2F, (q31_t)0xBADBA943, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9523369B, + (q31_t)0xB98A97D8, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x9673DB94, + (q31_t)0xB796199B, (q31_t)0x96E61CDF, (q31_t)0xB6F0A811, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x97CDA855, + (q31_t)0xB5A7E362, (q31_t)0x9842F043, (q31_t)0xB5049368, + (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x99A8C344, (q31_t)0xB31EFFCB, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A9C406D, + (q31_t)0xB1DEF9E8, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9C10CD70, + (q31_t)0xB0049AB2, (q31_t)0x9C8EEB33, (q31_t)0xAF6803A1, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D8E0596, + (q31_t)0xAE312B91, (q31_t)0x9E0EFFC1, (q31_t)0xAD96ED91, + (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0x9F979331, (q31_t)0xABCCFD82, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA0A1F24C, + (q31_t)0xAA9FBF1D, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA2386283, + (q31_t)0xA8E21106, (q31_t)0xA2C1ADC9, (q31_t)0xA84F2DA9, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3D6F533, + (q31_t)0xA72BF173, (q31_t)0xA462EEAC, (q31_t)0xA69B9B68, + (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA60C21ED, (q31_t)0xA4EFCA31, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA72BF173, + (q31_t)0xA3D6F533, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8E21106, + (q31_t)0xA2386283, (q31_t)0xA975CB56, (q31_t)0xA1AFFEA2, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA9FBF1D, + (q31_t)0xA0A1F24C, (q31_t)0xAB35F5B5, (q31_t)0xA01C4C72, + (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xACFD7AE8, (q31_t)0x9E90EB94, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAE312B91, + (q31_t)0x9D8E0596, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xB0049AB2, + (q31_t)0x9C10CD70, (q31_t)0xB0A1F71C, (q31_t)0x9B93A640, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB1DEF9E8, + (q31_t)0x9A9C406D, (q31_t)0xB27E9D3B, (q31_t)0x9A22042C, + (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB461FC70, (q31_t)0x98B93828, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB5A7E362, + (q31_t)0x97CDA855, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB796199B, + (q31_t)0x9673DB94, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB98A97D8, + (q31_t)0x9523369B, (q31_t)0xBA32CA70, (q31_t)0x94B50D87, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD85BE2F, + (q31_t)0x929DD805, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF8C0DE2, + (q31_t)0x91695663, (q31_t)0xC03A1368, (q31_t)0x9104A0ED, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC197F4D3, + (q31_t)0x903E6C7A, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5BFD22E, + (q31_t)0x8E05C6B7, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7DB6C50, + (q31_t)0x8CF83C30, (q31_t)0xC89061BA, (q31_t)0x8CA099D9, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9FBE527, + (q31_t)0x8BF4AC05, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCE4AB5A2, + (q31_t)0x8A0BD3F5, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD078AD9D, + (q31_t)0x8926B677, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD2AAC504, + (q31_t)0x884BE820, (q31_t)0xD3670445, (q31_t)0x88054677, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD59E4EFE, (q31_t)0x8738545E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD71A8EB5, + (q31_t)0x86B583EE, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD957DE7A, + (q31_t)0x85FA1152, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB9888A8, + (q31_t)0x8549345C, (q31_t)0xDC597781, (q31_t)0x85109CDC, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xDE9E4C60, (q31_t)0x846DF476, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE02323E5, + (q31_t)0x840777CF, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE26CB01A, + (q31_t)0x8376B422, (q31_t)0xE330734C, (q31_t)0x8348D8DB, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4B8CD10, + (q31_t)0x82F0BDE8, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xE7CC9917, (q31_t)0x824F0208, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE957ECFB, + (q31_t)0x82056758, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFF36F078, (q31_t)0x80009DE9 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_2048_q31[3072] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFD885, + (q31_t)0x006487E3, (q31_t)0x7FFF6216, (q31_t)0x00C90F88, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FFC250F, (q31_t)0x01F6A296, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF871A1, + (q31_t)0x02BFA9A4, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF09477, + (q31_t)0x03ED26E6, (q31_t)0x7FED5790, (q31_t)0x0451A176, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE5F108, + (q31_t)0x051A8E5C, (q31_t)0x7FE1C76B, (q31_t)0x057F0034, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FD37152, (q31_t)0x06AC406F, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC85853, + (q31_t)0x077501BE, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB563B2, + (q31_t)0x08A2009A, (q31_t)0x7FAE7494, (q31_t)0x09064B3A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F9FAA15, + (q31_t)0x09CECF89, (q31_t)0x7F97CEBC, (q31_t)0x0A3308BC, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F7E648B, (q31_t)0x0B5F8D9F, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F6BE9D4, + (q31_t)0x0C27C389, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F4DE450, + (q31_t)0x0D53DB92, (q31_t)0x7F434563, (q31_t)0x0DB7D376, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2D1C0E, + (q31_t)0x0E7FA99D, (q31_t)0x7F2191B4, (q31_t)0x0EE38765, + (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7EFD1C3C, (q31_t)0x100EE8AD, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE34635, + (q31_t)0x10D64DBC, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EBA3A39, + (q31_t)0x120116D4, (q31_t)0x7EABEF2C, (q31_t)0x1264994E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E8E6EB1, + (q31_t)0x132B7BF9, (q31_t)0x7E7F3956, (q31_t)0x138EDBB0, + (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E4FC53E, (q31_t)0x14B8B17F, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E2E9CDF, + (q31_t)0x157F0086, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7DFA98A7, + (q31_t)0x16A81305, (q31_t)0x7DE8A670, (q31_t)0x170AFD8D, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DC3D90D, + (q31_t)0x17D0A7BB, (q31_t)0x7DB0FDF7, (q31_t)0x183366E8, + (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D769BB5, (q31_t)0x195B49E9, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D4E2C7E, + (q31_t)0x1A203E1B, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D0F4218, + (q31_t)0x1B4732EF, (q31_t)0x7CF9AEF0, (q31_t)0x1BA96334, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CCDA168, + (q31_t)0x1C6D9053, (q31_t)0x7CB72724, (q31_t)0x1CCF8CB3, + (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C71EAF8, (q31_t)0x1DF5163F, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4242F2, + (q31_t)0x1EB86B46, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7BF88830, + (q31_t)0x1FDCDC1A, (q31_t)0x7BDF5B94, (q31_t)0x203E300D, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BAC1D31, + (q31_t)0x21009C0B, (q31_t)0x7B920B89, (q31_t)0x2161B39F, + (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7B420D7A, (q31_t)0x22847DDF, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B0B3D2C, + (q31_t)0x2345EFF7, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AB6CBA3, + (q31_t)0x24677757, (q31_t)0x7A9A0E4F, (q31_t)0x24C7CD32, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A5FB0D8, + (q31_t)0x2588349D, (q31_t)0x7A4210D8, (q31_t)0x25E845B5, + (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x79E76CA6, (q31_t)0x2707EBC6, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79A98715, + (q31_t)0x27C737D2, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x794A7C11, + (q31_t)0x28E5714A, (q31_t)0x792A37FE, (q31_t)0x2944A7A2, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78E8CFB1, + (q31_t)0x2A02C7B8, (q31_t)0x78C7ABA1, (q31_t)0x2A61B101, + (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x786280BF, (q31_t)0x2B7DCF17, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x781D9B64, + (q31_t)0x2C3AB2B9, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77B417DF, + (q31_t)0x2D553AFB, (q31_t)0x7790583D, (q31_t)0x2DB330C7, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7747FBCE, + (q31_t)0x2E6EC792, (q31_t)0x77235F2D, (q31_t)0x2ECC681E, + (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x76B3D0B3, (q31_t)0x2FE49BA6, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x76680376, + (q31_t)0x309ED555, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x761B1211, (q31_t)0x3158970D, (q31_t)0x75F42C0A, + (q31_t)0x31B54A5D, (q31_t)0x75CCFD42, (q31_t)0x3211DF03, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x757DC5CA, + (q31_t)0x32CAAB6F, (q31_t)0x7555BD4B, (q31_t)0x3326E2C2, + (q31_t)0x752D6C6C, (q31_t)0x3382FA88, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x74DBF1EF, (q31_t)0x343ACA87, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x7489571B, + (q31_t)0x34F219A7, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x74359CBD, (q31_t)0x35A8E624, (q31_t)0x740B53FA, + (q31_t)0x36041AD9, (q31_t)0x73E0C3A3, (q31_t)0x365F2E3B, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x738ACC9E, + (q31_t)0x3714F02A, (q31_t)0x735F6626, (q31_t)0x376F9E46, + (q31_t)0x7333B883, (q31_t)0x37CA2A30, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72DB8828, (q31_t)0x387EDA8E, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72823C66, + (q31_t)0x3932FF87, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x7227D61C, (q31_t)0x39E6975D, (q31_t)0x71FA3948, + (q31_t)0x3A402DD1, (q31_t)0x71CC5626, (q31_t)0x3A99A057, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x716FBD68, + (q31_t)0x3B4C18BA, (q31_t)0x71410804, (q31_t)0x3BA51E29, + (q31_t)0x71120CC5, (q31_t)0x3BFDFECD, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70B34524, (q31_t)0x3CAF50DA, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70536771, + (q31_t)0x3D600D2B, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6FF27496, (q31_t)0x3E10320D, (q31_t)0x6FC19385, + (q31_t)0x3E680B2C, (q31_t)0x6F906D84, (q31_t)0x3EBFBDCC, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6F2D532C, + (q31_t)0x3F6EAEB8, (q31_t)0x6EFB5F12, (q31_t)0x3FC5EC97, + (q31_t)0x6EC92682, (q31_t)0x401D0320, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6E63E87F, (q31_t)0x40CAB957, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DFD9A1B, + (q31_t)0x4177CFB0, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6D963C54, (q31_t)0x42244480, (q31_t)0x6D6227FA, + (q31_t)0x427A41D0, (q31_t)0x6D2DD027, (q31_t)0x42D0161E, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6CC45697, + (q31_t)0x437B42E1, (q31_t)0x6C8F351C, (q31_t)0x43D09AEC, + (q31_t)0x6C59D0A9, (q31_t)0x4425C923, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6BEE3F62, (q31_t)0x44CFA73F, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B81A3CD, + (q31_t)0x4578DB93, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6B13FEF5, (q31_t)0x4621647C, (q31_t)0x6ADCC964, + (q31_t)0x46756827, (q31_t)0x6AA551E8, (q31_t)0x46C9405C, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x6A359DB9, + (q31_t)0x47706D93, (q31_t)0x69FD614A, (q31_t)0x47C3C22E, + (q31_t)0x69C4E37A, (q31_t)0x4816EA85, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x69532442, (q31_t)0x48BCB598, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68E06129, + (q31_t)0x4961CD32, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x686C9B4B, (q31_t)0x4A062FBD, (q31_t)0x683257AA, + (q31_t)0x4A581C9D, (q31_t)0x67F7D3C4, (q31_t)0x4AA9DBA1, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x67820BB6, + (q31_t)0x4B4CCF4D, (q31_t)0x6746C7D7, (q31_t)0x4B9E038F, + (q31_t)0x670B4443, (q31_t)0x4BEF092D, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x66937E90, (q31_t)0x4C9087B1, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x661ABBC5, + (q31_t)0x4D31494B, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x65A0FD0B, (q31_t)0x4DD14C6E, (q31_t)0x6563BF92, + (q31_t)0x4E210617, (q31_t)0x6526438E, (q31_t)0x4E708F8F, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x64AA907F, + (q31_t)0x4F0F1126, (q31_t)0x646C59BF, (q31_t)0x4F5E08E3, + (q31_t)0x642DE50D, (q31_t)0x4FACCFAB, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x63B0426D, (q31_t)0x5049C999, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x6331A9D4, + (q31_t)0x50E5FD6C, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x62B21C7B, (q31_t)0x518169A4, (q31_t)0x6271FA69, + (q31_t)0x51CED46E, (q31_t)0x62319B9D, (q31_t)0x521C0CC1, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x61B02876, + (q31_t)0x52B5E545, (q31_t)0x616F146B, (q31_t)0x53028517, + (q31_t)0x612DC446, (q31_t)0x534EF1B5, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x60AA704F, (q31_t)0x53E73097, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x60262DD5, + (q31_t)0x547EA073, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5FA0FE1E, (q31_t)0x55153FD4, (q31_t)0x5F5E0DB3, + (q31_t)0x556040E2, (q31_t)0x5F1AE273, (q31_t)0x55AB0D46, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5E93DC1F, + (q31_t)0x56400757, (q31_t)0x5E50015D, (q31_t)0x568A34A9, + (q31_t)0x5E0BEC6E, (q31_t)0x56D42C99, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5D8314B0, (q31_t)0x57677B9D, + (q31_t)0x5D3E5236, (q31_t)0x57B0D256, (q31_t)0x5CF95638, + (q31_t)0x57F9F2F7, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5C6EB258, (q31_t)0x588B913F, (q31_t)0x5C290ACC, + (q31_t)0x58D40E8C, (q31_t)0x5BE32A67, (q31_t)0x591C550E, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5B56BFBD, + (q31_t)0x59AC3CFD, (q31_t)0x5B1035CF, (q31_t)0x59F3DE12, + (q31_t)0x5AC973B4, (q31_t)0x5A3B47AA, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x5A3B47AA, (q31_t)0x5AC973B4, + (q31_t)0x59F3DE12, (q31_t)0x5B1035CF, (q31_t)0x59AC3CFD, + (q31_t)0x5B56BFBD, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x591C550E, (q31_t)0x5BE32A67, (q31_t)0x58D40E8C, + (q31_t)0x5C290ACC, (q31_t)0x588B913F, (q31_t)0x5C6EB258, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x57F9F2F7, + (q31_t)0x5CF95638, (q31_t)0x57B0D256, (q31_t)0x5D3E5236, + (q31_t)0x57677B9D, (q31_t)0x5D8314B0, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x56D42C99, (q31_t)0x5E0BEC6E, + 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(q31_t)0x9447ED2F, (q31_t)0xBB3058C0, + (q31_t)0x9411C09D, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC2F6513, + (q31_t)0x9370CAE4, (q31_t)0xBC84BD1E, (q31_t)0x933BA968, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD2FE9E1, + (q31_t)0x92D22FD8, (q31_t)0xBD85BE2F, (q31_t)0x929DD805, + (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBE88304F, (q31_t)0x920265E4, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF3546A8, + (q31_t)0x919C1780, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC03A1368, + (q31_t)0x9104A0ED, (q31_t)0xC0915147, (q31_t)0x90D2ACD3, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1404233, + (q31_t)0x906F927B, (q31_t)0xC197F4D3, (q31_t)0x903E6C7A, + (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC29FF2D4, (q31_t)0x8FAC988E, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC350AF25, + (q31_t)0x8F4CBADB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC45AE1D7, + (q31_t)0x8EBEF7FB, (q31_t)0xC4B3E746, (q31_t)0x8E904298, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5665FA8, + (q31_t)0x8E33A9D9, (q31_t)0xC5BFD22E, (q31_t)0x8E05C6B7, + (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC6CD0079, (q31_t)0x8D7DC399, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7812571, + (q31_t)0x8D2477D8, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC89061BA, + (q31_t)0x8CA099D9, (q31_t)0xC8EB0FD6, (q31_t)0x8C753361, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9A0D1C4, + (q31_t)0x8C1F3C5C, (q31_t)0xC9FBE527, (q31_t)0x8BF4AC05, + (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCB0DE658, (q31_t)0x8B76A8E4, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCBC53578, + (q31_t)0x8B240E10, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCD91D3D, + (q31_t)0x8AAA42B4, (q31_t)0xCD355490, (q31_t)0x8A823A35, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDEE20FC, + (q31_t)0x8A3302BD, (q31_t)0xCE4AB5A2, (q31_t)0x8A0BD3F5, + (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xCF612AAA, (q31_t)0x8997FC89, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD01B6459, + (q31_t)0x894C2F4C, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD13397E1, + (q31_t)0x88DCA0D3, (q31_t)0xD191386D, (q31_t)0x88B80431, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD24CCF38, + (q31_t)0x886FA7C2, (q31_t)0xD2AAC504, (q31_t)0x884BE820, + (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD3C54D46, (q31_t)0x87E2649B, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD48230E8, + (q31_t)0x879D7F40, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD59E4EFE, + (q31_t)0x8738545E, (q31_t)0xD5FD3847, (q31_t)0x8717304E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD6BB585D, + (q31_t)0x86D5C802, (q31_t)0xD71A8EB5, (q31_t)0x86B583EE, + (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD838C82D, (q31_t)0x865678EA, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8F81439, + (q31_t)0x86189359, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xDA17BA4A, + (q31_t)0x85BDEF27, (q31_t)0xDA77CB62, (q31_t)0x85A04F28, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB3832CD, + (q31_t)0x8565F1B0, (q31_t)0xDB9888A8, (q31_t)0x8549345C, + (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDCBA1008, (q31_t)0x84F4C2D3, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD7B8220, + (q31_t)0x84BDF285, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE9E4C60, + (q31_t)0x846DF476, (q31_t)0xDEFF63F4, (q31_t)0x8453E2CE, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDFC1CFF2, + (q31_t)0x8420A46B, (q31_t)0xE02323E5, (q31_t)0x840777CF, + (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE14794B9, (q31_t)0x83BDBD0D, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE20AE9C1, + (q31_t)0x838E1507, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE330734C, + (q31_t)0x8348D8DB, (q31_t)0xE3926FAC, (q31_t)0x83325E97, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4569CCB, + (q31_t)0x8306510F, (q31_t)0xE4B8CD10, (q31_t)0x82F0BDE8, + (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE5DFC1E4, (q31_t)0x82B1D381, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6A4B616, + (q31_t)0x8289644A, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE7CC9917, + (q31_t)0x824F0208, (q31_t)0xE82F5844, (q31_t)0x823C26F2, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8F50273, + (q31_t)0x8217598F, (q31_t)0xE957ECFB, (q31_t)0x82056758, + (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEA80FF79, (q31_t)0x81D16320, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB474E80, + (q31_t)0x81B03AC1, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC71244F, + (q31_t)0x8180C6A9, (q31_t)0xECD48406, (q31_t)0x8171914E, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED9B66B2, + (q31_t)0x815410D3, (q31_t)0xEDFEE92B, (q31_t)0x8145C5C6, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xEF29B243, (q31_t)0x811CB9CA, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFF11752, + (q31_t)0x8102E3C3, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF11C789A, + (q31_t)0x80DE6E4C, (q31_t)0xF1805662, (q31_t)0x80D2E3F1, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2482C89, + (q31_t)0x80BCBA9C, (q31_t)0xF2AC246D, (q31_t)0x80B21BAF, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF3D83C76, (q31_t)0x8094162B, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF4A07260, + (q31_t)0x80819B74, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF5CCF743, + (q31_t)0x80683143, (q31_t)0xF6313076, (q31_t)0x806055EA, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6F9B4C5, + (q31_t)0x80518B6B, (q31_t)0xF75DFF65, (q31_t)0x804A9C4D, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF88AFE41, (q31_t)0x8037A7AC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF953BF90, + (q31_t)0x802C8EAD, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA80FFCB, + (q31_t)0x801E3894, (q31_t)0xFAE571A4, (q31_t)0x801A0EF7, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFBAE5E89, + (q31_t)0x8012A86F, (q31_t)0xFC12D919, (q31_t)0x800F6B88, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFD40565B, (q31_t)0x80078E5E, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE095D69, + (q31_t)0x8003DAF0, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF36F078, + (q31_t)0x80009DE9, (q31_t)0xFF9B781D, (q31_t)0x8000277A +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_4096_q31[6144] = +{ + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFF621, + (q31_t)0x003243F5, (q31_t)0x7FFFD885, (q31_t)0x006487E3, + (q31_t)0x7FFFA72C, (q31_t)0x0096CBC1, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFF0942, (q31_t)0x00FB532F, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFE1C64, + (q31_t)0x015FDA03, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFCE093, (q31_t)0x01C45FFE, (q31_t)0x7FFC250F, + (q31_t)0x01F6A296, (q31_t)0x7FFB55CE, (q31_t)0x0228E4E1, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF97C17, + (q31_t)0x028D6870, (q31_t)0x7FF871A1, (q31_t)0x02BFA9A4, + (q31_t)0x7FF7536F, (q31_t)0x02F1EA6B, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF4DBD8, (q31_t)0x03566A96, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF21553, + (q31_t)0x03BAE8B1, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FEEFFE1, (q31_t)0x041F647F, (q31_t)0x7FED5790, + (q31_t)0x0451A176, (q31_t)0x7FEB9B85, (q31_t)0x0483DDC3, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE7E840, + (q31_t)0x04E8543D, (q31_t)0x7FE5F108, (q31_t)0x051A8E5C, + (q31_t)0x7FE3E616, (q31_t)0x054CC7B0, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FDF9508, (q31_t)0x05B137DF, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FDAF518, + (q31_t)0x0615A48A, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FD6064B, (q31_t)0x067A0D75, (q31_t)0x7FD37152, + (q31_t)0x06AC406F, (q31_t)0x7FD0C8A3, (q31_t)0x06DE7261, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FCB3C23, + (q31_t)0x0742D310, (q31_t)0x7FC85853, (q31_t)0x077501BE, + (q31_t)0x7FC560CF, (q31_t)0x07A72F45, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FBF36A9, (q31_t)0x080B86C1, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB8BDB7, + (q31_t)0x086FD947, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FB1F5FC, (q31_t)0x08D42698, (q31_t)0x7FAE7494, + (q31_t)0x09064B3A, (q31_t)0x7FAADF7C, (q31_t)0x09386E77, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7FA37A3C, + (q31_t)0x099CB0A7, (q31_t)0x7F9FAA15, (q31_t)0x09CECF89, + (q31_t)0x7F9BC63F, (q31_t)0x0A00ECE8, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F93C38C, (q31_t)0x0A6522FE, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F8B7226, + (q31_t)0x0AC952AA, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F82D214, (q31_t)0x0B2D7BAE, (q31_t)0x7F7E648B, + (q31_t)0x0B5F8D9F, (q31_t)0x7F79E35A, (q31_t)0x0B919DCE, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F70A5FD, + (q31_t)0x0BF5B8CB, (q31_t)0x7F6BE9D4, (q31_t)0x0C27C389, + (q31_t)0x7F671A04, (q31_t)0x0C59CC67, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F5D3F75, (q31_t)0x0CBDD865, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F531654, + (q31_t)0x0D21DC87, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + 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(q31_t)0x81F3C2D7, (q31_t)0xE9EC66E8, + (q31_t)0x81EB0DBD, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEA4F73EE, (q31_t)0x81D9DDE1, (q31_t)0xEA80FF79, + (q31_t)0x81D16320, (q31_t)0xEAB28E55, (q31_t)0x81C8FBD5, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB15B5E0, + (q31_t)0x81B867A4, (q31_t)0xEB474E80, (q31_t)0x81B03AC1, + (q31_t)0xEB78EA52, (q31_t)0x81A82159, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEBDC2B6D, (q31_t)0x819828FD, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC3F78F5, + (q31_t)0x81887E9A, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xECA2D2AC, (q31_t)0x8179223A, (q31_t)0xECD48406, + (q31_t)0x8171914E, (q31_t)0xED063855, (q31_t)0x816A13E6, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED69A9B2, + (q31_t)0x815B53A8, (q31_t)0xED9B66B2, (q31_t)0x815410D3, + (q31_t)0xEDCD2687, (q31_t)0x814CE188, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEE30AE95, (q31_t)0x813EBD90, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEE9441A0, + (q31_t)0x8130E7C8, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEEF7DF6A, (q31_t)0x81236039, (q31_t)0xEF29B243, + (q31_t)0x811CB9CA, (q31_t)0xEF5B87B5, (q31_t)0x811626EC, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFBF3A44, + (q31_t)0x81093BE8, (q31_t)0xEFF11752, (q31_t)0x8102E3C3, + (q31_t)0xF022F6DA, (q31_t)0x80FC9F35, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF086BD39, (q31_t)0x80F050DB, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF0EA8D23, + (q31_t)0x80E450E2, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF14E665C, (q31_t)0x80D89F51, (q31_t)0xF1805662, + (q31_t)0x80D2E3F1, (q31_t)0xF1B248A5, (q31_t)0x80CD3C2F, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF21633C0, + (q31_t)0x80C22783, (q31_t)0xF2482C89, (q31_t)0x80BCBA9C, + (q31_t)0xF27A2770, (q31_t)0x80B76155, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF2DE2378, (q31_t)0x80ACE9AB, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF342279A, + (q31_t)0x80A2C08B, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF3A63398, (q31_t)0x8098E5FB, (q31_t)0xF3D83C76, + (q31_t)0x8094162B, (q31_t)0xF40A4734, (q31_t)0x808F5A02, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF46E6231, + (q31_t)0x80861CA5, (q31_t)0xF4A07260, (q31_t)0x80819B74, + (q31_t)0xF4D28451, (q31_t)0x807D2DEB, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF536AD55, (q31_t)0x80748DD9, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF59ADD01, + (q31_t)0x806C3C73, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF5FF1317, (q31_t)0x806439C0, (q31_t)0xF6313076, + (q31_t)0x806055EA, (q31_t)0xF6634F58, (q31_t)0x805C85C3, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6C79188, + (q31_t)0x80552083, (q31_t)0xF6F9B4C5, (q31_t)0x80518B6B, + (q31_t)0xF72BD967, (q31_t)0x804E0A03, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF79026B8, (q31_t)0x80474248, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF7F4793E, + (q31_t)0x8040C956, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF858D0BA, (q31_t)0x803A9F31, (q31_t)0xF88AFE41, + (q31_t)0x8037A7AC, (q31_t)0xF8BD2CEF, (q31_t)0x8034C3DC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9218D9E, + (q31_t)0x802F375C, (q31_t)0xF953BF90, (q31_t)0x802C8EAD, + (q31_t)0xF985F28A, (q31_t)0x8029F9B4, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xF9EA5B75, (q31_t)0x80250AE7, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA4EC820, + (q31_t)0x80206AF8, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFAB3384F, (q31_t)0x801C19E9, (q31_t)0xFAE571A4, + (q31_t)0x801A0EF7, (q31_t)0xFB17ABC2, (q31_t)0x801817BF, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFB7C223C, + (q31_t)0x8014647A, (q31_t)0xFBAE5E89, (q31_t)0x8012A86F, + (q31_t)0xFBE09B80, (q31_t)0x8011001E, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFC45174E, (q31_t)0x800DEAAC, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCA99569, + (q31_t)0x800B2427, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFD0E1594, (q31_t)0x8008AC90, (q31_t)0xFD40565B, + (q31_t)0x80078E5E, (q31_t)0xFD72978F, (q31_t)0x800683E8, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFDD71B1E, + (q31_t)0x8004AA31, (q31_t)0xFE095D69, (q31_t)0x8003DAF0, + (q31_t)0xFE3BA001, (q31_t)0x80031F6C, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFEA025FC, (q31_t)0x8001E39B, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF04ACD0, + (q31_t)0x8000F6BD, (q31_t)0xFF36F078, (q31_t)0x80009DE9, + (q31_t)0xFF69343E, (q31_t)0x800058D3, (q31_t)0xFF9B781D, + (q31_t)0x8000277A, (q31_t)0xFFCDBC0A, (q31_t)0x800009DE +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +/** + @brief q15 Twiddle factors Table +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
fori = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_16_q15[24] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xCF04, (q15_t)0x89BE +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_32_q15[48] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7D8A, (q15_t)0x18F8, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x6A6D, (q15_t)0x471C, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x471C, (q15_t)0x6A6D, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x18F8, (q15_t)0x7D8A, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xE707, (q15_t)0x7D8A, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xB8E3, (q15_t)0x6A6D, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x9592, (q15_t)0x471C, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8275, (q15_t)0x18F8, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x8275, (q15_t)0xE707, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0x9592, (q15_t)0xB8E3, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xB8E3, (q15_t)0x9592, + (q15_t)0xCF04, (q15_t)0x89BE, + (q15_t)0xE707, (q15_t)0x8275 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_64_q15[96] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7F62, (q15_t)0x0C8B, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7A7D, (q15_t)0x2528, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x70E2, (q15_t)0x3C56, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x62F2, (q15_t)0x5133, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5133, (q15_t)0x62F2, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x3C56, (q15_t)0x70E2, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2528, (q15_t)0x7A7D, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x0C8B, (q15_t)0x7F62, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF374, (q15_t)0x7F62, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xDAD7, (q15_t)0x7A7D, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC3A9, (q15_t)0x70E2, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xAECC, (q15_t)0x62F2, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0x9D0D, (q15_t)0x5133, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x8F1D, (q15_t)0x3C56, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8582, (q15_t)0x2528, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x809D, (q15_t)0x0C8B, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x809D, (q15_t)0xF374, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8582, (q15_t)0xDAD7, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8F1D, (q15_t)0xC3A9, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9D0D, (q15_t)0xAECC, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAECC, (q15_t)0x9D0D, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xC3A9, (q15_t)0x8F1D, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xDAD7, (q15_t)0x8582, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xF374, (q15_t)0x809D +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_128_q15[192] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FD8, (q15_t)0x0647, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7E9D, (q15_t)0x12C8, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7C29, (q15_t)0x1F19, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7884, (q15_t)0x2B1F, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x73B5, (q15_t)0x36BA, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6DCA, (q15_t)0x41CE, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x66CF, (q15_t)0x4C3F, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x5ED7, (q15_t)0x55F5, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x55F5, (q15_t)0x5ED7, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4C3F, (q15_t)0x66CF, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x41CE, (q15_t)0x6DCA, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x36BA, (q15_t)0x73B5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2B1F, (q15_t)0x7884, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x1F19, (q15_t)0x7C29, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x12C8, (q15_t)0x7E9D, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0647, (q15_t)0x7FD8, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF9B8, (q15_t)0x7FD8, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xED37, (q15_t)0x7E9D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE0E6, (q15_t)0x7C29, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD4E0, (q15_t)0x7884, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC945, (q15_t)0x73B5, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xBE31, (q15_t)0x6DCA, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB3C0, (q15_t)0x66CF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAA0A, (q15_t)0x5ED7, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA128, (q15_t)0x55F5, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9930, (q15_t)0x4C3F, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9235, (q15_t)0x41CE, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8C4A, (q15_t)0x36BA, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x877B, (q15_t)0x2B1F, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x83D6, (q15_t)0x1F19, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8162, (q15_t)0x12C8, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8027, (q15_t)0x0647, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8027, (q15_t)0xF9B8, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x8162, (q15_t)0xED37, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x83D6, (q15_t)0xE0E6, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x877B, (q15_t)0xD4E0, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8C4A, (q15_t)0xC945, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x9235, (q15_t)0xBE31, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9930, (q15_t)0xB3C0, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0xA128, (q15_t)0xAA0A, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAA0A, (q15_t)0xA128, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB3C0, (q15_t)0x9930, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBE31, (q15_t)0x9235, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC945, (q15_t)0x8C4A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD4E0, (q15_t)0x877B, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xE0E6, (q15_t)0x83D6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xED37, (q15_t)0x8162, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF9B8, (q15_t)0x8027 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_256_q15[384] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FF6, (q15_t)0x0324, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FA7, (q15_t)0x096A, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F09, (q15_t)0x0FAB, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E1D, (q15_t)0x15E2, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7CE3, (q15_t)0x1C0B, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7B5D, (q15_t)0x2223, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x798A, (q15_t)0x2826, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x776C, (q15_t)0x2E11, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x7504, (q15_t)0x33DE, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7255, (q15_t)0x398C, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6F5F, (q15_t)0x3F17, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6C24, (q15_t)0x447A, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x68A6, (q15_t)0x49B4, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x64E8, (q15_t)0x4EBF, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x60EC, (q15_t)0x539B, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5CB4, (q15_t)0x5842, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5842, (q15_t)0x5CB4, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x539B, (q15_t)0x60EC, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4EBF, (q15_t)0x64E8, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x49B4, (q15_t)0x68A6, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x447A, (q15_t)0x6C24, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x3F17, (q15_t)0x6F5F, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x398C, (q15_t)0x7255, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x33DE, (q15_t)0x7504, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2E11, (q15_t)0x776C, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2826, (q15_t)0x798A, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2223, (q15_t)0x7B5D, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1C0B, (q15_t)0x7CE3, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x15E2, (q15_t)0x7E1D, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x0FAB, (q15_t)0x7F09, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x096A, (q15_t)0x7FA7, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0324, (q15_t)0x7FF6, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFCDB, (q15_t)0x7FF6, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF695, (q15_t)0x7FA7, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF054, (q15_t)0x7F09, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEA1D, (q15_t)0x7E1D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE3F4, (q15_t)0x7CE3, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDDDC, (q15_t)0x7B5D, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD7D9, (q15_t)0x798A, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD1EE, (q15_t)0x776C, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCC21, (q15_t)0x7504, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC673, (q15_t)0x7255, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC0E8, (q15_t)0x6F5F, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBB85, (q15_t)0x6C24, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB64B, (q15_t)0x68A6, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB140, (q15_t)0x64E8, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAC64, (q15_t)0x60EC, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA7BD, (q15_t)0x5CB4, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA34B, (q15_t)0x5842, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0x9F13, (q15_t)0x539B, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9B17, (q15_t)0x4EBF, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9759, (q15_t)0x49B4, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x93DB, (q15_t)0x447A, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x90A0, (q15_t)0x3F17, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8DAA, (q15_t)0x398C, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8AFB, (q15_t)0x33DE, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8893, (q15_t)0x2E11, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8675, (q15_t)0x2826, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x84A2, (q15_t)0x2223, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x831C, (q15_t)0x1C0B, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x81E2, (q15_t)0x15E2, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x80F6, (q15_t)0x0FAB, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8058, (q15_t)0x096A, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8009, (q15_t)0x0324, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8009, (q15_t)0xFCDB, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8058, (q15_t)0xF695, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80F6, (q15_t)0xF054, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81E2, (q15_t)0xEA1D, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x831C, (q15_t)0xE3F4, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x84A2, (q15_t)0xDDDC, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8675, (q15_t)0xD7D9, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8893, (q15_t)0xD1EE, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8AFB, (q15_t)0xCC21, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8DAA, (q15_t)0xC673, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x90A0, (q15_t)0xC0E8, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x93DB, (q15_t)0xBB85, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9759, (q15_t)0xB64B, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9B17, (q15_t)0xB140, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9F13, (q15_t)0xAC64, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA34B, (q15_t)0xA7BD, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA7BD, (q15_t)0xA34B, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAC64, (q15_t)0x9F13, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB140, (q15_t)0x9B17, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB64B, (q15_t)0x9759, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBB85, (q15_t)0x93DB, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xC0E8, (q15_t)0x90A0, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC673, (q15_t)0x8DAA, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCC21, (q15_t)0x8AFB, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD1EE, (q15_t)0x8893, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD7D9, (q15_t)0x8675, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDDDC, (q15_t)0x84A2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE3F4, (q15_t)0x831C, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xEA1D, (q15_t)0x81E2, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xF054, (q15_t)0x80F6, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF695, (q15_t)0x8058, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFCDB, (q15_t)0x8009 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_512_q15[768] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFD, (q15_t)0x0192, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FE9, (q15_t)0x04B6, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FC2, (q15_t)0x07D9, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F87, (q15_t)0x0AFB, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F38, (q15_t)0x0E1B, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7ED5, (q15_t)0x1139, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E5F, (q15_t)0x1455, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DD6, (q15_t)0x176D, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D39, (q15_t)0x1A82, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7C89, (q15_t)0x1D93, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BC5, (q15_t)0x209F, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7AEF, (q15_t)0x23A6, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A05, (q15_t)0x26A8, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x7909, (q15_t)0x29A3, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x77FA, (q15_t)0x2C98, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x76D9, (q15_t)0x2F87, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75A5, (q15_t)0x326E, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x745F, (q15_t)0x354D, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7307, (q15_t)0x3824, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x719E, (q15_t)0x3AF2, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7023, (q15_t)0x3DB8, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6E96, (q15_t)0x4073, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6CF9, (q15_t)0x4325, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6B4A, (q15_t)0x45CD, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x698C, (q15_t)0x4869, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x67BD, (q15_t)0x4AFB, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x65DD, (q15_t)0x4D81, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x63EF, (q15_t)0x4FFB, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x61F1, (q15_t)0x5269, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x5FE3, (q15_t)0x54CA, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5DC7, (q15_t)0x571D, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5B9D, (q15_t)0x5964, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5964, (q15_t)0x5B9D, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x571D, (q15_t)0x5DC7, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x54CA, (q15_t)0x5FE3, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5269, (q15_t)0x61F1, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4FFB, (q15_t)0x63EF, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4D81, (q15_t)0x65DD, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4AFB, (q15_t)0x67BD, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4869, (q15_t)0x698C, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x45CD, (q15_t)0x6B4A, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4325, (q15_t)0x6CF9, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4073, (q15_t)0x6E96, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3DB8, (q15_t)0x7023, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3AF2, (q15_t)0x719E, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3824, (q15_t)0x7307, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x354D, (q15_t)0x745F, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x326E, (q15_t)0x75A5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2F87, (q15_t)0x76D9, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2C98, (q15_t)0x77FA, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x29A3, (q15_t)0x7909, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x26A8, (q15_t)0x7A05, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x23A6, (q15_t)0x7AEF, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x209F, (q15_t)0x7BC5, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1D93, (q15_t)0x7C89, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1A82, (q15_t)0x7D39, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x176D, (q15_t)0x7DD6, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x1455, (q15_t)0x7E5F, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1139, (q15_t)0x7ED5, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0E1B, (q15_t)0x7F38, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0AFB, (q15_t)0x7F87, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x07D9, (q15_t)0x7FC2, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x04B6, (q15_t)0x7FE9, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x0192, (q15_t)0x7FFD, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFE6D, (q15_t)0x7FFD, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFB49, (q15_t)0x7FE9, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF826, (q15_t)0x7FC2, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF504, (q15_t)0x7F87, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF1E4, (q15_t)0x7F38, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEEC6, (q15_t)0x7ED5, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEBAA, (q15_t)0x7E5F, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE892, (q15_t)0x7DD6, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE57D, (q15_t)0x7D39, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE26C, (q15_t)0x7C89, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDF60, (q15_t)0x7BC5, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDC59, (q15_t)0x7AEF, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD957, (q15_t)0x7A05, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD65C, (q15_t)0x7909, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD367, (q15_t)0x77FA, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD078, (q15_t)0x76D9, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCD91, (q15_t)0x75A5, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCAB2, (q15_t)0x745F, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC7DB, (q15_t)0x7307, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC50D, (q15_t)0x719E, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC247, (q15_t)0x7023, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xBF8C, (q15_t)0x6E96, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBCDA, (q15_t)0x6CF9, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBA32, (q15_t)0x6B4A, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB796, (q15_t)0x698C, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB504, (q15_t)0x67BD, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB27E, (q15_t)0x65DD, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB004, (q15_t)0x63EF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAD96, (q15_t)0x61F1, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAB35, (q15_t)0x5FE3, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA8E2, (q15_t)0x5DC7, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA69B, (q15_t)0x5B9D, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA462, (q15_t)0x5964, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA238, (q15_t)0x571D, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA01C, (q15_t)0x54CA, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E0E, (q15_t)0x5269, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C10, (q15_t)0x4FFB, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A22, (q15_t)0x4D81, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9842, (q15_t)0x4AFB, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x9673, (q15_t)0x4869, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x94B5, (q15_t)0x45CD, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9306, (q15_t)0x4325, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9169, (q15_t)0x4073, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x8FDC, (q15_t)0x3DB8, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8E61, (q15_t)0x3AF2, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8CF8, (q15_t)0x3824, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BA0, (q15_t)0x354D, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8A5A, (q15_t)0x326E, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8926, (q15_t)0x2F87, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x8805, (q15_t)0x2C98, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x86F6, (q15_t)0x29A3, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x85FA, (q15_t)0x26A8, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8510, (q15_t)0x23A6, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x843A, (q15_t)0x209F, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x8376, (q15_t)0x1D93, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82C6, (q15_t)0x1A82, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8229, (q15_t)0x176D, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81A0, (q15_t)0x1455, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x812A, (q15_t)0x1139, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80C7, (q15_t)0x0E1B, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8078, (q15_t)0x0AFB, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x803D, (q15_t)0x07D9, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8016, (q15_t)0x04B6, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8002, (q15_t)0x0192, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8002, (q15_t)0xFE6D, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x8016, (q15_t)0xFB49, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x803D, (q15_t)0xF826, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8078, (q15_t)0xF504, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80C7, (q15_t)0xF1E4, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x812A, (q15_t)0xEEC6, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81A0, (q15_t)0xEBAA, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8229, (q15_t)0xE892, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x82C6, (q15_t)0xE57D, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8376, (q15_t)0xE26C, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x843A, (q15_t)0xDF60, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x8510, (q15_t)0xDC59, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85FA, (q15_t)0xD957, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86F6, (q15_t)0xD65C, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8805, (q15_t)0xD367, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x8926, (q15_t)0xD078, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A5A, (q15_t)0xCD91, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8BA0, (q15_t)0xCAB2, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CF8, (q15_t)0xC7DB, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E61, (q15_t)0xC50D, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8FDC, (q15_t)0xC247, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9169, (q15_t)0xBF8C, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9306, (q15_t)0xBCDA, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x94B5, (q15_t)0xBA32, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9673, (q15_t)0xB796, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9842, (q15_t)0xB504, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9A22, (q15_t)0xB27E, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9C10, (q15_t)0xB004, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9E0E, (q15_t)0xAD96, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0xA01C, (q15_t)0xAB35, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA238, (q15_t)0xA8E2, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA462, (q15_t)0xA69B, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA69B, (q15_t)0xA462, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA8E2, (q15_t)0xA238, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAB35, (q15_t)0xA01C, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAD96, (q15_t)0x9E0E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB004, (q15_t)0x9C10, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB27E, (q15_t)0x9A22, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB504, (q15_t)0x9842, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB796, (q15_t)0x9673, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBA32, (q15_t)0x94B5, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBCDA, (q15_t)0x9306, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBF8C, (q15_t)0x9169, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC247, (q15_t)0x8FDC, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC50D, (q15_t)0x8E61, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC7DB, (q15_t)0x8CF8, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCAB2, (q15_t)0x8BA0, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCD91, (q15_t)0x8A5A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD078, (q15_t)0x8926, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD367, (q15_t)0x8805, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD65C, (q15_t)0x86F6, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD957, (q15_t)0x85FA, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDC59, (q15_t)0x8510, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDF60, (q15_t)0x843A, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE26C, (q15_t)0x8376, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE57D, (q15_t)0x82C6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE892, (q15_t)0x8229, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEBAA, (q15_t)0x81A0, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEEC6, (q15_t)0x812A, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF1E4, (q15_t)0x80C7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF504, (q15_t)0x8078, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF826, (q15_t)0x803D, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFB49, (q15_t)0x8016, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFE6D, (q15_t)0x8002 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + + */ +const q15_t twiddleCoef_1024_q15[1536] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x00C9, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFA, (q15_t)0x025B, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF0, (q15_t)0x03ED, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE1, (q15_t)0x057F, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FCE, (q15_t)0x0710, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FB5, (q15_t)0x08A2, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F97, (q15_t)0x0A33, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F75, (q15_t)0x0BC3, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F4D, (q15_t)0x0D53, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F21, (q15_t)0x0EE3, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EF0, (q15_t)0x1072, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EBA, (q15_t)0x1201, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E7F, (q15_t)0x138E, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E3F, (q15_t)0x151B, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DFA, (q15_t)0x16A8, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DB0, (q15_t)0x1833, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D62, (q15_t)0x19BD, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D0F, (q15_t)0x1B47, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CB7, (q15_t)0x1CCF, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C5A, (q15_t)0x1E56, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BF8, (q15_t)0x1FDC, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7B92, (q15_t)0x2161, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B26, (q15_t)0x22E5, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AB6, (q15_t)0x2467, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A42, (q15_t)0x25E8, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79C8, (q15_t)0x2767, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x794A, (q15_t)0x28E5, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78C7, (q15_t)0x2A61, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7840, (q15_t)0x2BDC, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77B4, (q15_t)0x2D55, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7723, (q15_t)0x2ECC, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x768E, (q15_t)0x3041, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75F4, (q15_t)0x31B5, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7555, (q15_t)0x3326, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74B2, (q15_t)0x3496, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x740B, (q15_t)0x3604, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x735F, (q15_t)0x376F, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72AF, (q15_t)0x38D8, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x71FA, (q15_t)0x3A40, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7141, (q15_t)0x3BA5, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7083, (q15_t)0x3D07, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FC1, (q15_t)0x3E68, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6EFB, (q15_t)0x3FC5, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E30, (q15_t)0x4121, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D62, (q15_t)0x427A, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6C8F, (q15_t)0x43D0, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BB8, (q15_t)0x4524, + (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6ADC, (q15_t)0x4675, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x69FD, (q15_t)0x47C3, + (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6919, (q15_t)0x490F, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x6832, (q15_t)0x4A58, + (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6746, (q15_t)0x4B9E, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6657, (q15_t)0x4CE1, + (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x6563, (q15_t)0x4E21, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x646C, (q15_t)0x4F5E, + (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x6371, (q15_t)0x5097, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x6271, (q15_t)0x51CE, + (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x616F, (q15_t)0x5302, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x6068, (q15_t)0x5433, + (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5F5E, (q15_t)0x5560, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E50, (q15_t)0x568A, + (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D3E, (q15_t)0x57B0, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C29, (q15_t)0x58D4, + (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B10, (q15_t)0x59F3, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x59F3, (q15_t)0x5B10, + (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x58D4, (q15_t)0x5C29, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57B0, (q15_t)0x5D3E, + (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x568A, (q15_t)0x5E50, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x5560, (q15_t)0x5F5E, + (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x5433, (q15_t)0x6068, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5302, (q15_t)0x616F, + (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x51CE, (q15_t)0x6271, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x5097, (q15_t)0x6371, + (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4F5E, (q15_t)0x646C, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E21, (q15_t)0x6563, + (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4CE1, (q15_t)0x6657, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4B9E, (q15_t)0x6746, + (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4A58, (q15_t)0x6832, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x490F, (q15_t)0x6919, + (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x47C3, (q15_t)0x69FD, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x4675, (q15_t)0x6ADC, + (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4524, (q15_t)0x6BB8, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x43D0, (q15_t)0x6C8F, + (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x427A, (q15_t)0x6D62, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4121, (q15_t)0x6E30, + (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x3FC5, (q15_t)0x6EFB, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3E68, (q15_t)0x6FC1, + (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D07, (q15_t)0x7083, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BA5, (q15_t)0x7141, + (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A40, (q15_t)0x71FA, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x38D8, (q15_t)0x72AF, + (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x376F, (q15_t)0x735F, + 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(q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA1AF, (q15_t)0xA975, + (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA2C1, (q15_t)0xA84F, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA3D6, (q15_t)0xA72B, + (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4EF, (q15_t)0xA60C, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA60C, (q15_t)0xA4EF, + (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA72B, (q15_t)0xA3D6, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA84F, (q15_t)0xA2C1, + (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA975, (q15_t)0xA1AF, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA9F, (q15_t)0xA0A1, + (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xABCC, (q15_t)0x9F97, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACFD, (q15_t)0x9E90, + (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xAE31, (q15_t)0x9D8E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF68, (q15_t)0x9C8E, + (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB0A1, (q15_t)0x9B93, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB1DE, (q15_t)0x9A9C, + (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB31E, (q15_t)0x99A8, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB461, (q15_t)0x98B9, + (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB5A7, (q15_t)0x97CD, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB6F0, (q15_t)0x96E6, + (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB83C, (q15_t)0x9602, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB98A, (q15_t)0x9523, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBADB, (q15_t)0x9447, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBC2F, (q15_t)0x9370, + (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD85, (q15_t)0x929D, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBEDE, (q15_t)0x91CF, + (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xC03A, (q15_t)0x9104, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC197, (q15_t)0x903E, + (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC2F8, (q15_t)0x8F7C, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC45A, (q15_t)0x8EBE, + (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC5BF, (q15_t)0x8E05, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC727, (q15_t)0x8D50, + (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC890, (q15_t)0x8CA0, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9FB, (q15_t)0x8BF4, + (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB69, (q15_t)0x8B4D, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCCD9, (q15_t)0x8AAA, + (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCE4A, (q15_t)0x8A0B, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCFBE, (q15_t)0x8971, + (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD133, (q15_t)0x88DC, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD2AA, (q15_t)0x884B, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD423, (q15_t)0x87BF, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD59E, (q15_t)0x8738, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD71A, (q15_t)0x86B5, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD898, (q15_t)0x8637, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xDA17, (q15_t)0x85BD, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB98, (q15_t)0x8549, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDD1A, (q15_t)0x84D9, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE9E, (q15_t)0x846D, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xE023, (q15_t)0x8407, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE1A9, (q15_t)0x83A5, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE330, (q15_t)0x8348, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE4B8, (q15_t)0x82F0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE642, (q15_t)0x829D, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE7CC, (q15_t)0x824F, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE957, (q15_t)0x8205, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEAE4, (q15_t)0x81C0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC71, (q15_t)0x8180, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEDFE, (q15_t)0x8145, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF8D, (q15_t)0x810F, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF11C, (q15_t)0x80DE, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF2AC, (q15_t)0x80B2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF43C, (q15_t)0x808A, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF5CC, (q15_t)0x8068, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF75D, (q15_t)0x804A, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF8EF, (q15_t)0x8031, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA80, (q15_t)0x801E, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFC12, (q15_t)0x800F, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFDA4, (q15_t)0x8005, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFF36, (q15_t)0x8000 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_2048_q15[3072] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0064, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFE, (q15_t)0x012D, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01F6, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF8, (q15_t)0x02BF, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF3, (q15_t)0x0388, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FED, (q15_t)0x0451, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE5, (q15_t)0x051A, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDD, (q15_t)0x05E3, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD3, (q15_t)0x06AC, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FC8, (q15_t)0x0775, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBC, (q15_t)0x083D, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FAE, (q15_t)0x0906, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F9F, (q15_t)0x09CE, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F8F, (q15_t)0x0A97, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F7E, (q15_t)0x0B5F, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F6B, (q15_t)0x0C27, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F58, (q15_t)0x0CEF, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F43, (q15_t)0x0DB7, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F2D, (q15_t)0x0E7F, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F15, (q15_t)0x0F47, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EFD, (q15_t)0x100E, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE3, (q15_t)0x10D6, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EC8, (q15_t)0x119D, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EAB, (q15_t)0x1264, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E8E, (q15_t)0x132B, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E6F, (q15_t)0x13F2, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E4F, (q15_t)0x14B8, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E2E, (q15_t)0x157F, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E0C, (q15_t)0x1645, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DE8, (q15_t)0x170A, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DC3, (q15_t)0x17D0, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7D9D, (q15_t)0x1896, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D76, (q15_t)0x195B, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D4E, (q15_t)0x1A20, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D24, (q15_t)0x1AE4, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7CF9, (q15_t)0x1BA9, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CCD, (q15_t)0x1C6D, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CA0, (q15_t)0x1D31, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C71, (q15_t)0x1DF5, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C42, (q15_t)0x1EB8, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C11, (q15_t)0x1F7B, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BDF, (q15_t)0x203E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BAC, (q15_t)0x2100, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B77, (q15_t)0x21C2, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B42, (q15_t)0x2284, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B0B, (q15_t)0x2345, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AD3, (q15_t)0x2407, + (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7A9A, (q15_t)0x24C7, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A5F, (q15_t)0x2588, + (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A24, (q15_t)0x2648, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79E7, (q15_t)0x2707, + (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79A9, (q15_t)0x27C7, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x796A, (q15_t)0x2886, + (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x792A, (q15_t)0x2944, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78E8, (q15_t)0x2A02, + (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78A6, (q15_t)0x2AC0, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7862, (q15_t)0x2B7D, + (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x781D, (q15_t)0x2C3A, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77D7, (q15_t)0x2CF7, + (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x7790, (q15_t)0x2DB3, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7747, (q15_t)0x2E6E, + (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x76FE, (q15_t)0x2F29, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76B3, (q15_t)0x2FE4, + (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x7668, (q15_t)0x309E, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x761B, (q15_t)0x3158, + (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75CC, (q15_t)0x3211, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x757D, (q15_t)0x32CA, + (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x752D, (q15_t)0x3382, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74DB, (q15_t)0x343A, + (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x7489, (q15_t)0x34F2, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x7435, (q15_t)0x35A8, + (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73E0, (q15_t)0x365F, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x738A, (q15_t)0x3714, + (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7333, (q15_t)0x37CA, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72DB, (q15_t)0x387E, + (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7282, (q15_t)0x3932, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x7227, (q15_t)0x39E6, + (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71CC, (q15_t)0x3A99, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x716F, (q15_t)0x3B4C, + (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7112, (q15_t)0x3BFD, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x70B3, (q15_t)0x3CAF, + (q15_t)0x7083, (q15_t)0x3D07, (q15_t)0x7053, (q15_t)0x3D60, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FF2, (q15_t)0x3E10, + (q15_t)0x6FC1, (q15_t)0x3E68, (q15_t)0x6F90, (q15_t)0x3EBF, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6F2D, (q15_t)0x3F6E, + (q15_t)0x6EFB, (q15_t)0x3FC5, (q15_t)0x6EC9, (q15_t)0x401D, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E63, (q15_t)0x40CA, + (q15_t)0x6E30, (q15_t)0x4121, (q15_t)0x6DFD, (q15_t)0x4177, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D96, (q15_t)0x4224, + (q15_t)0x6D62, (q15_t)0x427A, (q15_t)0x6D2D, (q15_t)0x42D0, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6CC4, (q15_t)0x437B, + (q15_t)0x6C8F, (q15_t)0x43D0, (q15_t)0x6C59, (q15_t)0x4425, + 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(q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE456, (q15_t)0x8306, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE51B, (q15_t)0x82DB, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5DF, (q15_t)0x82B1, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE6A4, (q15_t)0x8289, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE769, (q15_t)0x8262, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE82F, (q15_t)0x823C, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8F5, (q15_t)0x8217, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE9BA, (q15_t)0x81F3, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA80, (q15_t)0x81D1, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB47, (q15_t)0x81B0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC0D, (q15_t)0x8190, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECD4, (q15_t)0x8171, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED9B, (q15_t)0x8154, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE62, (q15_t)0x8137, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF29, (q15_t)0x811C, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFF1, (q15_t)0x8102, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF0B8, (q15_t)0x80EA, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF180, (q15_t)0x80D2, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF248, (q15_t)0x80BC, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF310, (q15_t)0x80A7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3D8, (q15_t)0x8094, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF4A0, (q15_t)0x8081, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF568, (q15_t)0x8070, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF631, (q15_t)0x8060, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6F9, (q15_t)0x8051, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF7C2, (q15_t)0x8043, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF88A, (q15_t)0x8037, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF953, (q15_t)0x802C, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA1C, (q15_t)0x8022, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAE5, (q15_t)0x801A, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFBAE, (q15_t)0x8012, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC77, (q15_t)0x800C, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD40, (q15_t)0x8007, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFE09, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFED2, (q15_t)0x8001, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_4096_q15[6144] = +{ + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0032, + (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0096, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x00FB, + (q15_t)0x7FFE, (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x015F, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01C4, + (q15_t)0x7FFC, (q15_t)0x01F6, (q15_t)0x7FFB, (q15_t)0x0228, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF9, (q15_t)0x028D, + (q15_t)0x7FF8, (q15_t)0x02BF, (q15_t)0x7FF7, (q15_t)0x02F1, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF4, (q15_t)0x0356, + (q15_t)0x7FF3, (q15_t)0x0388, (q15_t)0x7FF2, (q15_t)0x03BA, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FEE, (q15_t)0x041F, + (q15_t)0x7FED, (q15_t)0x0451, (q15_t)0x7FEB, (q15_t)0x0483, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE7, (q15_t)0x04E8, + (q15_t)0x7FE5, (q15_t)0x051A, (q15_t)0x7FE3, (q15_t)0x054C, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDF, (q15_t)0x05B1, + (q15_t)0x7FDD, (q15_t)0x05E3, (q15_t)0x7FDA, (q15_t)0x0615, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD6, (q15_t)0x067A, + (q15_t)0x7FD3, (q15_t)0x06AC, (q15_t)0x7FD0, (q15_t)0x06DE, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FCB, (q15_t)0x0742, + (q15_t)0x7FC8, (q15_t)0x0775, (q15_t)0x7FC5, (q15_t)0x07A7, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBF, (q15_t)0x080B, + (q15_t)0x7FBC, (q15_t)0x083D, (q15_t)0x7FB8, (q15_t)0x086F, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FB1, (q15_t)0x08D4, + (q15_t)0x7FAE, (q15_t)0x0906, (q15_t)0x7FAA, (q15_t)0x0938, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7FA3, (q15_t)0x099C, + (q15_t)0x7F9F, (q15_t)0x09CE, (q15_t)0x7F9B, (q15_t)0x0A00, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F93, (q15_t)0x0A65, + (q15_t)0x7F8F, (q15_t)0x0A97, (q15_t)0x7F8B, (q15_t)0x0AC9, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F82, (q15_t)0x0B2D, + (q15_t)0x7F7E, (q15_t)0x0B5F, (q15_t)0x7F79, (q15_t)0x0B91, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F70, (q15_t)0x0BF5, + (q15_t)0x7F6B, (q15_t)0x0C27, (q15_t)0x7F67, (q15_t)0x0C59, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F5D, (q15_t)0x0CBD, + (q15_t)0x7F58, (q15_t)0x0CEF, (q15_t)0x7F53, (q15_t)0x0D21, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F48, (q15_t)0x0D85, + (q15_t)0x7F43, (q15_t)0x0DB7, (q15_t)0x7F3D, (q15_t)0x0DE9, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F32, (q15_t)0x0E4D, + (q15_t)0x7F2D, (q15_t)0x0E7F, (q15_t)0x7F27, (q15_t)0x0EB1, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F1B, (q15_t)0x0F15, + (q15_t)0x7F15, (q15_t)0x0F47, (q15_t)0x7F0F, (q15_t)0x0F79, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7F03, (q15_t)0x0FDD, + (q15_t)0x7EFD, (q15_t)0x100E, (q15_t)0x7EF6, (q15_t)0x1040, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE9, (q15_t)0x10A4, + (q15_t)0x7EE3, (q15_t)0x10D6, (q15_t)0x7EDC, (q15_t)0x1108, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7ECF, (q15_t)0x116B, + (q15_t)0x7EC8, (q15_t)0x119D, (q15_t)0x7EC1, (q15_t)0x11CF, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EB3, (q15_t)0x1232, + (q15_t)0x7EAB, (q15_t)0x1264, (q15_t)0x7EA4, (q15_t)0x1296, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E95, (q15_t)0x12F9, + (q15_t)0x7E8E, (q15_t)0x132B, (q15_t)0x7E86, (q15_t)0x135D, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E77, (q15_t)0x13C0, + (q15_t)0x7E6F, (q15_t)0x13F2, (q15_t)0x7E67, (q15_t)0x1423, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E57, (q15_t)0x1487, + (q15_t)0x7E4F, (q15_t)0x14B8, (q15_t)0x7E47, (q15_t)0x14EA, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E37, (q15_t)0x154D, + (q15_t)0x7E2E, (q15_t)0x157F, (q15_t)0x7E26, (q15_t)0x15B0, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E14, (q15_t)0x1613, + (q15_t)0x7E0C, (q15_t)0x1645, (q15_t)0x7E03, (q15_t)0x1676, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DF1, (q15_t)0x16D9, + (q15_t)0x7DE8, (q15_t)0x170A, (q15_t)0x7DDF, (q15_t)0x173C, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DCD, (q15_t)0x179F, + (q15_t)0x7DC3, (q15_t)0x17D0, (q15_t)0x7DBA, (q15_t)0x1802, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7DA7, (q15_t)0x1864, + (q15_t)0x7D9D, (q15_t)0x1896, (q15_t)0x7D94, (q15_t)0x18C7, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D80, (q15_t)0x192A, + (q15_t)0x7D76, (q15_t)0x195B, (q15_t)0x7D6C, (q15_t)0x198C, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D58, (q15_t)0x19EF, + (q15_t)0x7D4E, (q15_t)0x1A20, (q15_t)0x7D43, (q15_t)0x1A51, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D2F, (q15_t)0x1AB3, + (q15_t)0x7D24, (q15_t)0x1AE4, (q15_t)0x7D19, (q15_t)0x1B16, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7D04, (q15_t)0x1B78, + (q15_t)0x7CF9, (q15_t)0x1BA9, (q15_t)0x7CEE, (q15_t)0x1BDA, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CD8, (q15_t)0x1C3C, + (q15_t)0x7CCD, (q15_t)0x1C6D, (q15_t)0x7CC2, (q15_t)0x1C9E, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CAB, (q15_t)0x1D00, + (q15_t)0x7CA0, (q15_t)0x1D31, (q15_t)0x7C94, (q15_t)0x1D62, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C7D, (q15_t)0x1DC4, + (q15_t)0x7C71, (q15_t)0x1DF5, (q15_t)0x7C66, (q15_t)0x1E25, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C4E, (q15_t)0x1E87, + (q15_t)0x7C42, (q15_t)0x1EB8, (q15_t)0x7C36, (q15_t)0x1EE9, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C1D, (q15_t)0x1F4A, + (q15_t)0x7C11, (q15_t)0x1F7B, (q15_t)0x7C05, (q15_t)0x1FAC, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BEB, (q15_t)0x200D, + (q15_t)0x7BDF, (q15_t)0x203E, (q15_t)0x7BD2, (q15_t)0x206E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BB9, (q15_t)0x20D0, + (q15_t)0x7BAC, (q15_t)0x2100, (q15_t)0x7B9F, (q15_t)0x2131, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B84, (q15_t)0x2192, + (q15_t)0x7B77, (q15_t)0x21C2, (q15_t)0x7B6A, (q15_t)0x21F3, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B4F, (q15_t)0x2254, + (q15_t)0x7B42, (q15_t)0x2284, (q15_t)0x7B34, (q15_t)0x22B4, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B19, (q15_t)0x2315, + (q15_t)0x7B0B, (q15_t)0x2345, (q15_t)0x7AFD, (q15_t)0x2376, + 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(q15_t)0x9842, (q15_t)0xB504, (q15_t)0x9860, (q15_t)0xB4DB, + (q15_t)0x987D, (q15_t)0xB4B3, (q15_t)0x989B, (q15_t)0xB48A, + (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98D6, (q15_t)0xB439, + (q15_t)0x98F4, (q15_t)0xB410, (q15_t)0x9912, (q15_t)0xB3E8, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x994E, (q15_t)0xB397, + (q15_t)0x996C, (q15_t)0xB36F, (q15_t)0x998A, (q15_t)0xB347, + (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99C6, (q15_t)0xB2F6, + (q15_t)0x99E5, (q15_t)0xB2CE, (q15_t)0x9A03, (q15_t)0xB2A6, + (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A40, (q15_t)0xB256, + (q15_t)0x9A5F, (q15_t)0xB22E, (q15_t)0x9A7D, (q15_t)0xB206, + (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9ABA, (q15_t)0xB1B7, + (q15_t)0x9AD9, (q15_t)0xB18F, (q15_t)0x9AF8, (q15_t)0xB167, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B36, (q15_t)0xB118, + (q15_t)0x9B55, (q15_t)0xB0F0, (q15_t)0x9B74, (q15_t)0xB0C9, + (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BB2, (q15_t)0xB07A, + (q15_t)0x9BD2, (q15_t)0xB053, (q15_t)0x9BF1, (q15_t)0xB02B, + (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C30, (q15_t)0xAFDD, + (q15_t)0x9C4F, (q15_t)0xAFB6, (q15_t)0x9C6F, (q15_t)0xAF8F, + (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CAE, (q15_t)0xAF40, + (q15_t)0x9CCE, (q15_t)0xAF1A, (q15_t)0x9CEE, (q15_t)0xAEF3, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D2D, (q15_t)0xAEA5, + (q15_t)0x9D4D, (q15_t)0xAE7E, (q15_t)0x9D6D, (q15_t)0xAE57, + (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DAE, (q15_t)0xAE0A, + (q15_t)0x9DCE, (q15_t)0xADE3, (q15_t)0x9DEE, (q15_t)0xADBD, + (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E2F, (q15_t)0xAD70, + (q15_t)0x9E4F, (q15_t)0xAD4A, (q15_t)0x9E70, (q15_t)0xAD23, + (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9EB1, (q15_t)0xACD7, + (q15_t)0x9ED2, (q15_t)0xACB1, (q15_t)0x9EF2, (q15_t)0xAC8A, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F34, (q15_t)0xAC3E, + (q15_t)0x9F55, (q15_t)0xAC18, (q15_t)0x9F76, (q15_t)0xABF2, + (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FB8, (q15_t)0xABA7, + (q15_t)0x9FD9, (q15_t)0xAB81, (q15_t)0x9FFB, (q15_t)0xAB5B, + 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(q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7BF, (q15_t)0x9657, + (q15_t)0xB7E9, (q15_t)0x963B, (q15_t)0xB812, (q15_t)0x961E, + (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB865, (q15_t)0x95E6, + (q15_t)0xB88F, (q15_t)0x95CA, (q15_t)0xB8B9, (q15_t)0x95AE, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB90C, (q15_t)0x9576, + (q15_t)0xB936, (q15_t)0x955A, (q15_t)0xB960, (q15_t)0x953E, + (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9B4, (q15_t)0x9507, + (q15_t)0xB9DE, (q15_t)0x94EC, (q15_t)0xBA08, (q15_t)0x94D0, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA5C, (q15_t)0x9499, + (q15_t)0xBA87, (q15_t)0x947E, (q15_t)0xBAB1, (q15_t)0x9463, + (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB05, (q15_t)0x942C, + (q15_t)0xBB30, (q15_t)0x9411, (q15_t)0xBB5A, (q15_t)0x93F6, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBAF, (q15_t)0x93C0, + (q15_t)0xBBDA, (q15_t)0x93A6, (q15_t)0xBC04, (q15_t)0x938B, + (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC5A, (q15_t)0x9356, + (q15_t)0xBC84, (q15_t)0x933B, (q15_t)0xBCAF, (q15_t)0x9321, + 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(q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD396, (q15_t)0x87F3, + (q15_t)0xD3C5, (q15_t)0x87E2, (q15_t)0xD3F4, (q15_t)0x87D1, + (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD452, (q15_t)0x87AE, + (q15_t)0xD482, (q15_t)0x879D, (q15_t)0xD4B1, (q15_t)0x878C, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD510, (q15_t)0x876A, + (q15_t)0xD53F, (q15_t)0x8759, (q15_t)0xD56E, (q15_t)0x8749, + (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5CD, (q15_t)0x8727, + (q15_t)0xD5FD, (q15_t)0x8717, (q15_t)0xD62C, (q15_t)0x8706, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD68B, (q15_t)0x86E6, + (q15_t)0xD6BB, (q15_t)0x86D5, (q15_t)0xD6EA, (q15_t)0x86C5, + (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD74A, (q15_t)0x86A5, + (q15_t)0xD779, (q15_t)0x8695, (q15_t)0xD7A9, (q15_t)0x8685, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD809, (q15_t)0x8666, + (q15_t)0xD838, (q15_t)0x8656, (q15_t)0xD868, (q15_t)0x8646, + (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8C8, (q15_t)0x8627, + (q15_t)0xD8F8, (q15_t)0x8618, (q15_t)0xD927, (q15_t)0x8609, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD987, (q15_t)0x85EA, + (q15_t)0xD9B7, (q15_t)0x85DB, (q15_t)0xD9E7, (q15_t)0x85CC, + (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA47, (q15_t)0x85AF, + (q15_t)0xDA77, (q15_t)0x85A0, (q15_t)0xDAA7, (q15_t)0x8591, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB08, (q15_t)0x8574, + (q15_t)0xDB38, (q15_t)0x8565, (q15_t)0xDB68, (q15_t)0x8557, + (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBC8, (q15_t)0x853A, + (q15_t)0xDBF8, (q15_t)0x852C, (q15_t)0xDC29, (q15_t)0x851E, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDC89, (q15_t)0x8502, + (q15_t)0xDCBA, (q15_t)0x84F4, (q15_t)0xDCEA, (q15_t)0x84E6, + (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD4B, (q15_t)0x84CB, + (q15_t)0xDD7B, (q15_t)0x84BD, (q15_t)0xDDAB, (q15_t)0x84B0, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE0C, (q15_t)0x8495, + (q15_t)0xDE3D, (q15_t)0x8488, (q15_t)0xDE6D, (q15_t)0x847B, + (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDECE, (q15_t)0x8460, + (q15_t)0xDEFF, (q15_t)0x8453, (q15_t)0xDF2F, (q15_t)0x8446, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDF91, (q15_t)0x842D, + (q15_t)0xDFC1, (q15_t)0x8420, (q15_t)0xDFF2, (q15_t)0x8414, + (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE053, (q15_t)0x83FA, + (q15_t)0xE084, (q15_t)0x83EE, (q15_t)0xE0B5, (q15_t)0x83E2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE116, (q15_t)0x83C9, + (q15_t)0xE147, (q15_t)0x83BD, (q15_t)0xE178, (q15_t)0x83B1, + (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE1DA, (q15_t)0x8399, + (q15_t)0xE20A, (q15_t)0x838E, (q15_t)0xE23B, (q15_t)0x8382, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE29D, (q15_t)0x836B, + (q15_t)0xE2CE, (q15_t)0x835F, (q15_t)0xE2FF, (q15_t)0x8354, + (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE361, (q15_t)0x833D, + (q15_t)0xE392, (q15_t)0x8332, (q15_t)0xE3C3, (q15_t)0x8327, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE425, (q15_t)0x8311, + (q15_t)0xE456, (q15_t)0x8306, (q15_t)0xE487, (q15_t)0x82FB, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE4E9, (q15_t)0x82E6, + (q15_t)0xE51B, (q15_t)0x82DB, (q15_t)0xE54C, (q15_t)0x82D0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5AE, (q15_t)0x82BC, + (q15_t)0xE5DF, (q15_t)0x82B1, (q15_t)0xE610, (q15_t)0x82A7, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE673, (q15_t)0x8293, + (q15_t)0xE6A4, (q15_t)0x8289, (q15_t)0xE6D5, (q15_t)0x827F, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE738, (q15_t)0x826B, + (q15_t)0xE769, (q15_t)0x8262, (q15_t)0xE79B, (q15_t)0x8258, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE7FD, (q15_t)0x8245, + (q15_t)0xE82F, (q15_t)0x823C, (q15_t)0xE860, (q15_t)0x8232, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8C3, (q15_t)0x8220, + (q15_t)0xE8F5, (q15_t)0x8217, (q15_t)0xE926, (q15_t)0x820E, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE989, (q15_t)0x81FC, + (q15_t)0xE9BA, (q15_t)0x81F3, (q15_t)0xE9EC, (q15_t)0x81EB, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA4F, (q15_t)0x81D9, + (q15_t)0xEA80, (q15_t)0x81D1, (q15_t)0xEAB2, (q15_t)0x81C8, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB15, (q15_t)0x81B8, + (q15_t)0xEB47, (q15_t)0x81B0, (q15_t)0xEB78, (q15_t)0x81A8, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEBDC, (q15_t)0x8198, + (q15_t)0xEC0D, (q15_t)0x8190, (q15_t)0xEC3F, (q15_t)0x8188, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECA2, (q15_t)0x8179, + (q15_t)0xECD4, (q15_t)0x8171, (q15_t)0xED06, (q15_t)0x816A, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED69, (q15_t)0x815B, + (q15_t)0xED9B, (q15_t)0x8154, (q15_t)0xEDCD, (q15_t)0x814C, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE30, (q15_t)0x813E, + (q15_t)0xEE62, (q15_t)0x8137, (q15_t)0xEE94, (q15_t)0x8130, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEEF7, (q15_t)0x8123, + (q15_t)0xEF29, (q15_t)0x811C, (q15_t)0xEF5B, (q15_t)0x8116, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFBF, (q15_t)0x8109, + (q15_t)0xEFF1, (q15_t)0x8102, (q15_t)0xF022, (q15_t)0x80FC, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF086, (q15_t)0x80F0, + (q15_t)0xF0B8, (q15_t)0x80EA, (q15_t)0xF0EA, (q15_t)0x80E4, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF14E, (q15_t)0x80D8, + (q15_t)0xF180, (q15_t)0x80D2, (q15_t)0xF1B2, (q15_t)0x80CD, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF216, (q15_t)0x80C2, + (q15_t)0xF248, (q15_t)0x80BC, (q15_t)0xF27A, (q15_t)0x80B7, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF2DE, (q15_t)0x80AC, + (q15_t)0xF310, (q15_t)0x80A7, (q15_t)0xF342, (q15_t)0x80A2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3A6, (q15_t)0x8098, + (q15_t)0xF3D8, (q15_t)0x8094, (q15_t)0xF40A, (q15_t)0x808F, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF46E, (q15_t)0x8086, + (q15_t)0xF4A0, (q15_t)0x8081, (q15_t)0xF4D2, (q15_t)0x807D, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF536, (q15_t)0x8074, + (q15_t)0xF568, (q15_t)0x8070, (q15_t)0xF59A, (q15_t)0x806C, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF5FF, (q15_t)0x8064, + (q15_t)0xF631, (q15_t)0x8060, (q15_t)0xF663, (q15_t)0x805C, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6C7, (q15_t)0x8055, + (q15_t)0xF6F9, (q15_t)0x8051, (q15_t)0xF72B, (q15_t)0x804E, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF790, (q15_t)0x8047, + (q15_t)0xF7C2, (q15_t)0x8043, (q15_t)0xF7F4, (q15_t)0x8040, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF858, (q15_t)0x803A, + (q15_t)0xF88A, (q15_t)0x8037, (q15_t)0xF8BD, (q15_t)0x8034, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF921, (q15_t)0x802F, + (q15_t)0xF953, (q15_t)0x802C, (q15_t)0xF985, (q15_t)0x8029, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xF9EA, (q15_t)0x8025, + (q15_t)0xFA1C, (q15_t)0x8022, (q15_t)0xFA4E, (q15_t)0x8020, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAB3, (q15_t)0x801C, + (q15_t)0xFAE5, (q15_t)0x801A, (q15_t)0xFB17, (q15_t)0x8018, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFB7C, (q15_t)0x8014, + (q15_t)0xFBAE, (q15_t)0x8012, (q15_t)0xFBE0, (q15_t)0x8011, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC45, (q15_t)0x800D, + (q15_t)0xFC77, (q15_t)0x800C, (q15_t)0xFCA9, (q15_t)0x800B, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD0E, (q15_t)0x8008, + (q15_t)0xFD40, (q15_t)0x8007, (q15_t)0xFD72, (q15_t)0x8006, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFDD7, (q15_t)0x8004, + (q15_t)0xFE09, (q15_t)0x8003, (q15_t)0xFE3B, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFEA0, (q15_t)0x8001, + (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFF04, (q15_t)0x8000, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF69, (q15_t)0x8000, + (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFFCD, (q15_t)0x8000 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +/** + @} end of CFFT_CIFFT group +*/ + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + +const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH] = +{ + /* 8x2, size 20 */ + 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + +const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH] = +{ + /* 8x4, size 48 */ + 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208, + 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208, + 152,224, 176,208, 184,232, 216,240, 200,224, 232,240 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + +const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH] = +{ + /* radix 8, size 56 */ + 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200, + 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400, + 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480, + 368,424, 376,488, 440,496 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + +const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] = +{ + /* 8x2, size 208 */ + 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768, + 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520, + 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776, + 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320, + 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400, + 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584, + 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600, + 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608, + 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864, + 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808, + 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832, + 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008, + 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + +const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] = +{ + /* 8x4, size 440 */ + 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640, + 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768, + 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384, + 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984, + 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608, + 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736, + 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864, + 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992, + 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104, + 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720, + 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160, + 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936, + 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048, + 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808, + 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544, + 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880, + 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496, + 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120, + 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552, + 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824, + 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672, + 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016, + 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640, + 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432, + 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936, + 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960, + 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648, + 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936, + 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928, + 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840, + 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888, + 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032, + 1960,1968, 2008,2032, 1992,2016, 2024,2032 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + +const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] = +{ + /* radix 8, size 448 */ + 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576, + 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152, + 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216, + 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280, + 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344, + 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408, + 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472, + 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544, + 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120, + 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696, + 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272, + 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848, + 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416, + 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992, + 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576, + 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152, + 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728, + 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808, + 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384, + 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960, + 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536, + 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136, + 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224, + 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328, + 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416, + 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520, + 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616, + 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744, + 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872, + 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000, + 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176, + 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368, + 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560, + 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888, + 3448,3952, 3512,4016, 3576,4080 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + +const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH] = +{ + /* 8x2, size 1800 */ + 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048, + 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048, + 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696, + 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648, + 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248, + 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200, + 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800, + 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752, + 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352, + 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304, + 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936, + 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856, + 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488, + 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408, + 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040, + 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960, + 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592, + 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096, + 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544, + 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080, + 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400, + 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120, + 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656, + 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168, + 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696, + 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208, + 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736, + 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272, + 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480, + 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312, + 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848, + 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280, + 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888, + 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288, + 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928, + 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464, + 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592, + 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504, + 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040, + 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136, + 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088, + 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816, + 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576, + 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664, + 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264, + 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800, + 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304, + 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840, + 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376, + 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392, + 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344, + 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944, + 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480, + 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016, + 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032, + 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984, + 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584, + 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632, + 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632, + 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168, + 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704, + 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208, + 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744, + 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248, + 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784, + 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320, + 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824, + 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360, + 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896, + 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400, + 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936, + 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440, + 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976, + 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512, + 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016, + 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552, + 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088, + 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592, + 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128, + 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160, + 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176, + 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712, + 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216, + 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752, + 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416, + 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304, + 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624, + 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296, + 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680, + 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208, + 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400, + 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808, + 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688, + 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976, + 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160, + 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344, + 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728, + 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736, + 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928, + 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872, + 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672, + 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208, + 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456, + 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248, + 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784, + 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448, + 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824, + 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240, + 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504, + 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168, + 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264, + 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456, + 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552, + 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312, + 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576, + 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248, + 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504, + 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360, + 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624, + 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384, + 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264, + 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664, + 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520, + 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280, + 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536, + 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048, + 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752, + 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992, + 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280, + 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856, + 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024, + 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624, + 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104, + 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664, + 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280, + 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688, + 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952, + 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456, + 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864, + 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784, + 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048, + 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728, + 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096, + 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112, + 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984, + 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160, + 8112,8136, 8120,8168, 8136,8160, 8152,8176 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + +const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH] = +{ + /* 8x2, size 3808 */ + 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024, + 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824, + 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752, + 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680, + 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576, + 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376, + 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304, + 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232, + 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048, + 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928, + 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856, + 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784, + 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712, + 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480, + 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408, + 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336, + 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264, + 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064, + 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960, + 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792, + 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496, + 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328, + 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032, + 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928, + 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856, + 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560, + 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392, + 1480,7488, 1488,11584, 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2176,4104, 2184,6152, 2192,10248, + 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080, + 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784, + 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248, + 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288, + 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128, + 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824, + 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656, + 2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328, + 2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400, + 2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864, + 2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280, + 2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400, + 2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168, + 2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904, + 2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552, + 2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440, + 2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272, + 3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976, + 3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288, + 3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480, + 3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168, + 3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016, + 3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848, + 3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520, + 3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440, + 3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056, + 3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320, + 3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 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4216,13840, 4224,8200, 4232,6160, 4240,10256, 4248,14352, 4256,8328, + 4264,6672, 4272,10768, 4280,14864, 4288,8456, 4296,7184, 4304,11280, + 4312,15376, 4320,8584, 4328,7696, 4336,11792, 4344,15888, 4352,9216, + 4360,9232, 4368,8272, 4376,12368, 4384,9344, 4392,4688, 4400,8784, + 4408,12880, 4416,9472, 4424,5200, 4432,9296, 4440,13392, 4448,9600, + 4456,5712, 4464,9808, 4472,13904, 4480,9224, 4488,6224, 4496,10320, + 4504,14416, 4512,9352, 4520,6736, 4528,10832, 4536,14928, 4544,9480, + 4552,7248, 4560,11344, 4568,15440, 4576,9608, 4584,7760, 4592,11856, + 4600,15952, 4608,10240, 4616,10256, 4624,8336, 4632,12432, 4640,10368, + 4648,4752, 4656,8848, 4664,12944, 4672,10496, 4680,5264, 4688,9360, + 4696,13456, 4704,10624, 4712,5776, 4720,9872, 4728,13968, 4736,10248, + 4744,6288, 4752,10384, 4760,14480, 4768,10376, 4776,6800, 4784,10896, + 4792,14992, 4800,10504, 4808,7312, 4816,11408, 4824,15504, 4832,10632, + 4840,7824, 4848,11920, 4856,16016, 4864,11264, 4872,11280, 4880,8400, + 4888,12496, 4896,11392, 4904,11408, 4912,8912, 4920,13008, 4928,11520, + 4936,5328, 4944,9424, 4952,13520, 4960,11648, 4968,5840, 4976,9936, + 4984,14032, 4992,11272, 5000,6352, 5008,10448, 5016,14544, 5024,11400, + 5032,6864, 5040,10960, 5048,15056, 5056,11528, 5064,7376, 5072,11472, + 5080,15568, 5088,11656, 5096,7888, 5104,11984, 5112,16080, 5120,8256, + 5128,8272, 5136,8464, 5144,12560, 5152,8384, 5160,8400, 5168,8976, + 5176,13072, 5184,8512, 5192,5392, 5200,9488, 5208,13584, 5216,8640, + 5224,5904, 5232,10000, 5240,14096, 5248,8264, 5256,6416, 5264,10512, + 5272,14608, 5280,8392, 5288,6928, 5296,11024, 5304,15120, 5312,8520, + 5320,7440, 5328,11536, 5336,15632, 5344,8648, 5352,7952, 5360,12048, + 5368,16144, 5376,9280, 5384,9296, 5392,8528, 5400,12624, 5408,9408, + 5416,9424, 5424,9040, 5432,13136, 5440,9536, 5448,5456, 5456,9552, + 5464,13648, 5472,9664, 5480,5968, 5488,10064, 5496,14160, 5504,9288, + 5512,6480, 5520,10576, 5528,14672, 5536,9416, 5544,6992, 5552,11088, + 5560,15184, 5568,9544, 5576,7504, 5584,11600, 5592,15696, 5600,9672, + 5608,8016, 5616,12112, 5624,16208, 5632,10304, 5640,10320, 5648,8592, + 5656,12688, 5664,10432, 5672,10448, 5680,9104, 5688,13200, 5696,10560, + 5704,10576, 5712,9616, 5720,13712, 5728,10688, 5736,6032, 5744,10128, + 5752,14224, 5760,10312, 5768,6544, 5776,10640, 5784,14736, 5792,10440, + 5800,7056, 5808,11152, 5816,15248, 5824,10568, 5832,7568, 5840,11664, + 5848,15760, 5856,10696, 5864,8080, 5872,12176, 5880,16272, 5888,11328, + 5896,11344, 5904,8656, 5912,12752, 5920,11456, 5928,11472, 5936,9168, + 5944,13264, 5952,11584, 5960,11600, 5968,9680, 5976,13776, 5984,11712, + 5992,6096, 6000,10192, 6008,14288, 6016,11336, 6024,6608, 6032,10704, + 6040,14800, 6048,11464, 6056,7120, 6064,11216, 6072,15312, 6080,11592, + 6088,7632, 6096,11728, 6104,15824, 6112,11720, 6120,8144, 6128,12240, + 6136,16336, 6144,12288, 6152,12304, 6160,8216, 6168,12312, 6176,12416, + 6184,12432, 6192,8728, 6200,12824, 6208,12544, 6216,12560, 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15256,15704, 15264,19800, 15272,23896, 15280,27992, 15288,32088, + 15320,16216, 15328,20312, 15336,24408, 15344,28504, 15352,32600, + 15392,16792, 15400,20888, 15408,24984, 15416,29080, 15456,17304, + 15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912, + 15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520, + 15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128, + 15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864, + 15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376, + 15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952, + 15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560, + 15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168, + 16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904, + 16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512, + 16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120, + 16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728, + 16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024, + 16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632, + 16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240, + 16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976, + 16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584, + 16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192, + 16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088, + 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696, + 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304, + 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040, + 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648, + 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256, + 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152, + 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856, + 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592, + 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200, + 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808, + 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416, + 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312, + 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240, + 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848, + 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456, + 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192, + 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864, + 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792, + 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496, + 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328, + 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936, + 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544, + 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440, + 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368, + 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072, + 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904, + 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512, + 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408, + 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112, + 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040, + 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968, + 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576, + 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472, + 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176, + 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104, + 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032, + 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736, + 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224, + 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152, + 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080, + 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784, + 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776, + 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800, + 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728, + 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656, + 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360, + 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768, + 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696, + 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400, + 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328, + 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416, + 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760, + 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464, + 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392, + 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480, + 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920, + 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848, + 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552, + 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960, + 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080, + 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104, + 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096, + 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536, + 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656, + 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680, + 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088, + 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208, + 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648, + 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648, + 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768, + 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208, + 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808, + 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248, + 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368, + 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384, + 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824, + 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424, + 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376, + 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496, + 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024, + 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464, + 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576, + 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528, + 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640, + 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688, + 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216, + 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752, + 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312, + 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864, + 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928, + 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504, + 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632, + 32248,32696 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + +const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH] = +{ + /* radix 4, size 12 */ + 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) +const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH] = +{ + /* 4x2, size 24 */ + 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, + 88,208, 104,176, 120,240, 152,200, 184,232 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) +const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH] = +{ + /* radix 4, size 56 */ + 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, + 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, + 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) +const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH] = +{ + /* 4x2, size 112 */ + 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, + 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, + 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, + 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, + 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, + 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) +const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH] = +{ + /* radix 4, size 240 */ + 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, + 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, + 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, + 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, + 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, + 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, + 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, + 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, + 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, + 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, + 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, + 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, + 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, + 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) +const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH] = +{ + /* 4x2, size 480 */ + 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, + 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, + 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, + 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, + 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, + 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, + 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, + 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, + 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, + 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, + 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, + 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, + 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, + 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, + 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, + 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, + 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, + 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, + 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, + 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, + 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, + 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, + 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, + 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, + 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, + 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, + 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, + 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, + 3512,3800, 3576,4056, 3704,3896, 3832,4024 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) +const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] = +{ + /* radix 4, size 992 */ + 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, + 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, + 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, + 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, + 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, + 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, + 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, + 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, + 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, + 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, + 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, + 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, + 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, + 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, + 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, + 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, + 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, + 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, + 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, + 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, + 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, + 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, + 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, + 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, + 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, + 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, + 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, + 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, + 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, + 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, + 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, + 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, + 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, + 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, + 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, + 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, + 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, + 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, + 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, + 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, + 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, + 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, + 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, + 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, + 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, + 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, + 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, + 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, + 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, + 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, + 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, + 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, + 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, + 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, + 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, + 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, + 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, + 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, + 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, + 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, + 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, + 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, + 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, + 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, + 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, + 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, + 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, + 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, + 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) +const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] = +{ + /* 4x2, size 1984 */ + 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, + 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, + 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, + 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, + 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, + 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, + 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, + 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, + 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, + 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, + 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, + 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, + 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, + 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, + 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, + 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, + 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, + 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, + 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, + 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, + 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, + 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, + 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, + 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, + 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, + 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, + 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, + 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, + 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, + 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, + 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, + 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, + 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, + 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, + 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, + 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, + 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, + 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, + 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, + 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, + 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, + 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, + 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, + 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, + 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, + 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, + 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, + 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, + 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, + 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, + 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, + 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, + 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, + 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, + 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, + 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, + 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, + 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, + 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, + 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, + 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, + 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, + 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, + 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, + 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, + 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, + 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, + 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, + 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, + 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, + 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, + 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, + 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, + 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, + 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, + 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, + 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, + 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, + 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, + 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, + 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, + 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, + 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, + 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, + 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, + 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, + 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, + 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, + 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, + 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, + 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, + 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, + 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, + 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, + 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 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11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, + 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, + 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, + 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, + 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, + 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, + 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, + 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, + 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, + 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, + 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, + 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, + 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, + 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, + 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, + 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) +const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] = +{ + /* radix 4, size 4032 */ + 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, + 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, + 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, + 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, + 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, + 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, + 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, + 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, + 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, + 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, + 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, + 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, + 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, + 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, + 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, + 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, + 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, + 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, + 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, + 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, + 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, + 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, + 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, + 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, + 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, + 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, + 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, + 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, + 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, + 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, + 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, + 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, + 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, + 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, + 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, + 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, + 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, + 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, + 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, + 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, + 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, + 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, + 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, + 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, + 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, + 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, + 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, + 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, + 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, + 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, + 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, + 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, + 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, + 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, + 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, + 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, + 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, + 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, + 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, + 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, + 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, + 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, + 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, + 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, + 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, + 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, + 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, + 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, + 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, + 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, + 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, + 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, + 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, + 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, + 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, + 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, + 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464, + 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752, + 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344, + 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584, + 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640, + 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168, + 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760, + 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000, + 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288, + 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960, + 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624, + 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792, + 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456, + 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376, + 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424, + 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016, + 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256, + 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544, + 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832, + 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496, + 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472, + 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712, + 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152, + 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816, + 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25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264, + 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, + 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, + 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, + 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, + 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, + 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, + 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, + 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, + 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, + 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, + 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, + 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, + 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, + 31480,32120, 31736,32632, 32248,32504 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) +/** + @par + Example code for Floating-point RFFT Twiddle factors Generation: + @par + 
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).'
+ @par + Real and Imag values are in interleaved fashion +*/ +const float32_t twiddleCoef_rfft_32[32] = { + 0.000000000f, 1.000000000f, + 0.195090322f, 0.980785280f, + 0.382683432f, 0.923879533f, + 0.555570233f, 0.831469612f, + 0.707106781f, 0.707106781f, + 0.831469612f, 0.555570233f, + 0.923879533f, 0.382683432f, + 0.980785280f, 0.195090322f, + 1.000000000f, 0.000000000f, + 0.980785280f, -0.195090322f, + 0.923879533f, -0.382683432f, + 0.831469612f, -0.555570233f, + 0.707106781f, -0.707106781f, + 0.555570233f, -0.831469612f, + 0.382683432f, -0.923879533f, + 0.195090322f, -0.980785280f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) +const float32_t twiddleCoef_rfft_64[64] = { + 0.000000000000000f, 1.000000000000000f, + 0.098017140329561f, 0.995184726672197f, + 0.195090322016128f, 0.980785280403230f, + 0.290284677254462f, 0.956940335732209f, + 0.382683432365090f, 0.923879532511287f, + 0.471396736825998f, 0.881921264348355f, + 0.555570233019602f, 0.831469612302545f, + 0.634393284163645f, 0.773010453362737f, + 0.707106781186547f, 0.707106781186548f, + 0.773010453362737f, 0.634393284163645f, + 0.831469612302545f, 0.555570233019602f, + 0.881921264348355f, 0.471396736825998f, + 0.923879532511287f, 0.382683432365090f, + 0.956940335732209f, 0.290284677254462f, + 0.980785280403230f, 0.195090322016128f, + 0.995184726672197f, 0.098017140329561f, + 1.000000000000000f, 0.000000000000000f, + 0.995184726672197f, -0.098017140329561f, + 0.980785280403230f, -0.195090322016128f, + 0.956940335732209f, -0.290284677254462f, + 0.923879532511287f, -0.382683432365090f, + 0.881921264348355f, -0.471396736825998f, + 0.831469612302545f, -0.555570233019602f, + 0.773010453362737f, -0.634393284163645f, + 0.707106781186548f, -0.707106781186547f, + 0.634393284163645f, -0.773010453362737f, + 0.555570233019602f, -0.831469612302545f, + 0.471396736825998f, -0.881921264348355f, + 0.382683432365090f, -0.923879532511287f, + 0.290284677254462f, -0.956940335732209f, + 0.195090322016129f, -0.980785280403230f, + 0.098017140329561f, -0.995184726672197f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) +const float32_t twiddleCoef_rfft_128[128] = { + 0.000000000f, 1.000000000f, + 0.049067674f, 0.998795456f, + 0.098017140f, 0.995184727f, + 0.146730474f, 0.989176510f, + 0.195090322f, 0.980785280f, + 0.242980180f, 0.970031253f, + 0.290284677f, 0.956940336f, + 0.336889853f, 0.941544065f, + 0.382683432f, 0.923879533f, + 0.427555093f, 0.903989293f, + 0.471396737f, 0.881921264f, + 0.514102744f, 0.857728610f, + 0.555570233f, 0.831469612f, + 0.595699304f, 0.803207531f, + 0.634393284f, 0.773010453f, + 0.671558955f, 0.740951125f, + 0.707106781f, 0.707106781f, + 0.740951125f, 0.671558955f, + 0.773010453f, 0.634393284f, + 0.803207531f, 0.595699304f, + 0.831469612f, 0.555570233f, + 0.857728610f, 0.514102744f, + 0.881921264f, 0.471396737f, + 0.903989293f, 0.427555093f, + 0.923879533f, 0.382683432f, + 0.941544065f, 0.336889853f, + 0.956940336f, 0.290284677f, + 0.970031253f, 0.242980180f, + 0.980785280f, 0.195090322f, + 0.989176510f, 0.146730474f, + 0.995184727f, 0.098017140f, + 0.998795456f, 0.049067674f, + 1.000000000f, 0.000000000f, + 0.998795456f, -0.049067674f, + 0.995184727f, -0.098017140f, + 0.989176510f, -0.146730474f, + 0.980785280f, -0.195090322f, + 0.970031253f, -0.242980180f, + 0.956940336f, -0.290284677f, + 0.941544065f, -0.336889853f, + 0.923879533f, -0.382683432f, + 0.903989293f, -0.427555093f, + 0.881921264f, -0.471396737f, + 0.857728610f, -0.514102744f, + 0.831469612f, -0.555570233f, + 0.803207531f, -0.595699304f, + 0.773010453f, -0.634393284f, + 0.740951125f, -0.671558955f, + 0.707106781f, -0.707106781f, + 0.671558955f, -0.740951125f, + 0.634393284f, -0.773010453f, + 0.595699304f, -0.803207531f, + 0.555570233f, -0.831469612f, + 0.514102744f, -0.857728610f, + 0.471396737f, -0.881921264f, + 0.427555093f, -0.903989293f, + 0.382683432f, -0.923879533f, + 0.336889853f, -0.941544065f, + 0.290284677f, -0.956940336f, + 0.242980180f, -0.970031253f, + 0.195090322f, -0.980785280f, + 0.146730474f, -0.989176510f, + 0.098017140f, -0.995184727f, + 0.049067674f, -0.998795456f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) +const float32_t twiddleCoef_rfft_256[256] = { + 0.000000000f, 1.000000000f, + 0.024541229f, 0.999698819f, + 0.049067674f, 0.998795456f, + 0.073564564f, 0.997290457f, + 0.098017140f, 0.995184727f, + 0.122410675f, 0.992479535f, + 0.146730474f, 0.989176510f, + 0.170961889f, 0.985277642f, + 0.195090322f, 0.980785280f, + 0.219101240f, 0.975702130f, + 0.242980180f, 0.970031253f, + 0.266712757f, 0.963776066f, + 0.290284677f, 0.956940336f, + 0.313681740f, 0.949528181f, + 0.336889853f, 0.941544065f, + 0.359895037f, 0.932992799f, + 0.382683432f, 0.923879533f, + 0.405241314f, 0.914209756f, + 0.427555093f, 0.903989293f, + 0.449611330f, 0.893224301f, + 0.471396737f, 0.881921264f, + 0.492898192f, 0.870086991f, + 0.514102744f, 0.857728610f, + 0.534997620f, 0.844853565f, + 0.555570233f, 0.831469612f, + 0.575808191f, 0.817584813f, + 0.595699304f, 0.803207531f, + 0.615231591f, 0.788346428f, + 0.634393284f, 0.773010453f, + 0.653172843f, 0.757208847f, + 0.671558955f, 0.740951125f, + 0.689540545f, 0.724247083f, + 0.707106781f, 0.707106781f, + 0.724247083f, 0.689540545f, + 0.740951125f, 0.671558955f, + 0.757208847f, 0.653172843f, + 0.773010453f, 0.634393284f, + 0.788346428f, 0.615231591f, + 0.803207531f, 0.595699304f, + 0.817584813f, 0.575808191f, + 0.831469612f, 0.555570233f, + 0.844853565f, 0.534997620f, + 0.857728610f, 0.514102744f, + 0.870086991f, 0.492898192f, + 0.881921264f, 0.471396737f, + 0.893224301f, 0.449611330f, + 0.903989293f, 0.427555093f, + 0.914209756f, 0.405241314f, + 0.923879533f, 0.382683432f, + 0.932992799f, 0.359895037f, + 0.941544065f, 0.336889853f, + 0.949528181f, 0.313681740f, + 0.956940336f, 0.290284677f, + 0.963776066f, 0.266712757f, + 0.970031253f, 0.242980180f, + 0.975702130f, 0.219101240f, + 0.980785280f, 0.195090322f, + 0.985277642f, 0.170961889f, + 0.989176510f, 0.146730474f, + 0.992479535f, 0.122410675f, + 0.995184727f, 0.098017140f, + 0.997290457f, 0.073564564f, + 0.998795456f, 0.049067674f, + 0.999698819f, 0.024541229f, + 1.000000000f, 0.000000000f, + 0.999698819f, -0.024541229f, + 0.998795456f, -0.049067674f, + 0.997290457f, -0.073564564f, + 0.995184727f, -0.098017140f, + 0.992479535f, -0.122410675f, + 0.989176510f, -0.146730474f, + 0.985277642f, -0.170961889f, + 0.980785280f, -0.195090322f, + 0.975702130f, -0.219101240f, + 0.970031253f, -0.242980180f, + 0.963776066f, -0.266712757f, + 0.956940336f, -0.290284677f, + 0.949528181f, -0.313681740f, + 0.941544065f, -0.336889853f, + 0.932992799f, -0.359895037f, + 0.923879533f, -0.382683432f, + 0.914209756f, -0.405241314f, + 0.903989293f, -0.427555093f, + 0.893224301f, -0.449611330f, + 0.881921264f, -0.471396737f, + 0.870086991f, -0.492898192f, + 0.857728610f, -0.514102744f, + 0.844853565f, -0.534997620f, + 0.831469612f, -0.555570233f, + 0.817584813f, -0.575808191f, + 0.803207531f, -0.595699304f, + 0.788346428f, -0.615231591f, + 0.773010453f, -0.634393284f, + 0.757208847f, -0.653172843f, + 0.740951125f, -0.671558955f, + 0.724247083f, -0.689540545f, + 0.707106781f, -0.707106781f, + 0.689540545f, -0.724247083f, + 0.671558955f, -0.740951125f, + 0.653172843f, -0.757208847f, + 0.634393284f, -0.773010453f, + 0.615231591f, -0.788346428f, + 0.595699304f, -0.803207531f, + 0.575808191f, -0.817584813f, + 0.555570233f, -0.831469612f, + 0.534997620f, -0.844853565f, + 0.514102744f, -0.857728610f, + 0.492898192f, -0.870086991f, + 0.471396737f, -0.881921264f, + 0.449611330f, -0.893224301f, + 0.427555093f, -0.903989293f, + 0.405241314f, -0.914209756f, + 0.382683432f, -0.923879533f, + 0.359895037f, -0.932992799f, + 0.336889853f, -0.941544065f, + 0.313681740f, -0.949528181f, + 0.290284677f, -0.956940336f, + 0.266712757f, -0.963776066f, + 0.242980180f, -0.970031253f, + 0.219101240f, -0.975702130f, + 0.195090322f, -0.980785280f, + 0.170961889f, -0.985277642f, + 0.146730474f, -0.989176510f, + 0.122410675f, -0.992479535f, + 0.098017140f, -0.995184727f, + 0.073564564f, -0.997290457f, + 0.049067674f, -0.998795456f, + 0.024541229f, -0.999698819f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) +const float32_t twiddleCoef_rfft_512[512] = { + 0.000000000f, 1.000000000f, + 0.012271538f, 0.999924702f, + 0.024541229f, 0.999698819f, + 0.036807223f, 0.999322385f, + 0.049067674f, 0.998795456f, + 0.061320736f, 0.998118113f, + 0.073564564f, 0.997290457f, + 0.085797312f, 0.996312612f, + 0.098017140f, 0.995184727f, + 0.110222207f, 0.993906970f, + 0.122410675f, 0.992479535f, + 0.134580709f, 0.990902635f, + 0.146730474f, 0.989176510f, + 0.158858143f, 0.987301418f, + 0.170961889f, 0.985277642f, + 0.183039888f, 0.983105487f, + 0.195090322f, 0.980785280f, + 0.207111376f, 0.978317371f, + 0.219101240f, 0.975702130f, + 0.231058108f, 0.972939952f, + 0.242980180f, 0.970031253f, + 0.254865660f, 0.966976471f, + 0.266712757f, 0.963776066f, + 0.278519689f, 0.960430519f, + 0.290284677f, 0.956940336f, + 0.302005949f, 0.953306040f, + 0.313681740f, 0.949528181f, + 0.325310292f, 0.945607325f, + 0.336889853f, 0.941544065f, + 0.348418680f, 0.937339012f, + 0.359895037f, 0.932992799f, + 0.371317194f, 0.928506080f, + 0.382683432f, 0.923879533f, + 0.393992040f, 0.919113852f, + 0.405241314f, 0.914209756f, + 0.416429560f, 0.909167983f, + 0.427555093f, 0.903989293f, + 0.438616239f, 0.898674466f, + 0.449611330f, 0.893224301f, + 0.460538711f, 0.887639620f, + 0.471396737f, 0.881921264f, + 0.482183772f, 0.876070094f, + 0.492898192f, 0.870086991f, + 0.503538384f, 0.863972856f, + 0.514102744f, 0.857728610f, + 0.524589683f, 0.851355193f, + 0.534997620f, 0.844853565f, + 0.545324988f, 0.838224706f, + 0.555570233f, 0.831469612f, + 0.565731811f, 0.824589303f, + 0.575808191f, 0.817584813f, + 0.585797857f, 0.810457198f, + 0.595699304f, 0.803207531f, + 0.605511041f, 0.795836905f, + 0.615231591f, 0.788346428f, + 0.624859488f, 0.780737229f, + 0.634393284f, 0.773010453f, + 0.643831543f, 0.765167266f, + 0.653172843f, 0.757208847f, + 0.662415778f, 0.749136395f, + 0.671558955f, 0.740951125f, + 0.680600998f, 0.732654272f, + 0.689540545f, 0.724247083f, + 0.698376249f, 0.715730825f, + 0.707106781f, 0.707106781f, + 0.715730825f, 0.698376249f, + 0.724247083f, 0.689540545f, + 0.732654272f, 0.680600998f, + 0.740951125f, 0.671558955f, + 0.749136395f, 0.662415778f, + 0.757208847f, 0.653172843f, + 0.765167266f, 0.643831543f, + 0.773010453f, 0.634393284f, + 0.780737229f, 0.624859488f, + 0.788346428f, 0.615231591f, + 0.795836905f, 0.605511041f, + 0.803207531f, 0.595699304f, + 0.810457198f, 0.585797857f, + 0.817584813f, 0.575808191f, + 0.824589303f, 0.565731811f, + 0.831469612f, 0.555570233f, + 0.838224706f, 0.545324988f, + 0.844853565f, 0.534997620f, + 0.851355193f, 0.524589683f, + 0.857728610f, 0.514102744f, + 0.863972856f, 0.503538384f, + 0.870086991f, 0.492898192f, + 0.876070094f, 0.482183772f, + 0.881921264f, 0.471396737f, + 0.887639620f, 0.460538711f, + 0.893224301f, 0.449611330f, + 0.898674466f, 0.438616239f, + 0.903989293f, 0.427555093f, + 0.909167983f, 0.416429560f, + 0.914209756f, 0.405241314f, + 0.919113852f, 0.393992040f, + 0.923879533f, 0.382683432f, + 0.928506080f, 0.371317194f, + 0.932992799f, 0.359895037f, + 0.937339012f, 0.348418680f, + 0.941544065f, 0.336889853f, + 0.945607325f, 0.325310292f, + 0.949528181f, 0.313681740f, + 0.953306040f, 0.302005949f, + 0.956940336f, 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-0.960430519f, + 0.266712757f, -0.963776066f, + 0.254865660f, -0.966976471f, + 0.242980180f, -0.970031253f, + 0.231058108f, -0.972939952f, + 0.219101240f, -0.975702130f, + 0.207111376f, -0.978317371f, + 0.195090322f, -0.980785280f, + 0.183039888f, -0.983105487f, + 0.170961889f, -0.985277642f, + 0.158858143f, -0.987301418f, + 0.146730474f, -0.989176510f, + 0.134580709f, -0.990902635f, + 0.122410675f, -0.992479535f, + 0.110222207f, -0.993906970f, + 0.098017140f, -0.995184727f, + 0.085797312f, -0.996312612f, + 0.073564564f, -0.997290457f, + 0.061320736f, -0.998118113f, + 0.049067674f, -0.998795456f, + 0.036807223f, -0.999322385f, + 0.024541229f, -0.999698819f, + 0.012271538f, -0.999924702f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) +const float32_t twiddleCoef_rfft_1024[1024] = { + 0.000000000f, 1.000000000f, + 0.006135885f, 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-0.990058210f, + 0.134580709f, -0.990902635f, + 0.128498111f, -0.991709754f, + 0.122410675f, -0.992479535f, + 0.116318631f, -0.993211949f, + 0.110222207f, -0.993906970f, + 0.104121634f, -0.994564571f, + 0.098017140f, -0.995184727f, + 0.091908956f, -0.995767414f, + 0.085797312f, -0.996312612f, + 0.079682438f, -0.996820299f, + 0.073564564f, -0.997290457f, + 0.067443920f, -0.997723067f, + 0.061320736f, -0.998118113f, + 0.055195244f, -0.998475581f, + 0.049067674f, -0.998795456f, + 0.042938257f, -0.999077728f, + 0.036807223f, -0.999322385f, + 0.030674803f, -0.999529418f, + 0.024541229f, -0.999698819f, + 0.018406730f, -0.999830582f, + 0.012271538f, -0.999924702f, + 0.006135885f, -0.999981175f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) +const float32_t twiddleCoef_rfft_2048[2048] = { + 0.000000000f, 1.000000000f, + 0.003067957f, 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-0.999322385f, + 0.035274239f, -0.999377670f, + 0.033741172f, -0.999430605f, + 0.032208025f, -0.999481187f, + 0.030674803f, -0.999529418f, + 0.029141509f, -0.999575296f, + 0.027608146f, -0.999618822f, + 0.026074718f, -0.999659997f, + 0.024541229f, -0.999698819f, + 0.023007681f, -0.999735288f, + 0.021474080f, -0.999769405f, + 0.019940429f, -0.999801170f, + 0.018406730f, -0.999830582f, + 0.016872988f, -0.999857641f, + 0.015339206f, -0.999882347f, + 0.013805389f, -0.999904701f, + 0.012271538f, -0.999924702f, + 0.010737659f, -0.999942350f, + 0.009203755f, -0.999957645f, + 0.007669829f, -0.999970586f, + 0.006135885f, -0.999981175f, + 0.004601926f, -0.999989411f, + 0.003067957f, -0.999995294f, + 0.001533980f, -0.999998823f +}; + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALL_TABLES) */ + +/** + @ingroup RealFFT + */ + +/** + @addtogroup RealFFT_Table Real FFT Tables + @{ + */ + +/** + @par + Generation of realCoefA array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) +const float32_t realCoefA[8192] = { + 0.500000000000000f, -0.500000000000000f, 0.499616503715515f, -0.499999850988388f, + 0.499233007431030f, -0.499999403953552f, 0.498849511146545f, -0.499998688697815f, + 0.498466014862061f, -0.499997645616531f, 0.498082518577576f, -0.499996334314346f, + 0.497699022293091f, -0.499994695186615f, 0.497315555810928f, -0.499992787837982f, + 0.496932059526443f, -0.499990582466125f, 0.496548563241959f, -0.499988079071045f, + 0.496165096759796f, -0.499985307455063f, 0.495781600475311f, -0.499982208013535f, + 0.495398133993149f, -0.499978810548782f, 0.495014637708664f, -0.499975144863129f, + 0.494631171226501f, -0.499971181154251f, 0.494247704744339f, -0.499966919422150f, + 0.493864238262177f, -0.499962359666824f, 0.493480771780014f, -0.499957501888275f, + 0.493097305297852f, -0.499952346086502f, 0.492713838815689f, -0.499946922063828f, + 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0.485045909881592f, 0.499776333570480f, + 0.485429257154465f, 0.499787658452988f, 0.485812574625015f, 0.499798685312271f, + 0.486195921897888f, 0.499809414148331f, 0.486579269170761f, 0.499819844961166f, + 0.486962646245956f, 0.499830007553101f, 0.487346023321152f, 0.499839842319489f, + 0.487729400396347f, 0.499849408864975f, 0.488112777471542f, 0.499858677387238f, + 0.488496154546738f, 0.499867647886276f, 0.488879561424255f, 0.499876320362091f, + 0.489262968301773f, 0.499884694814682f, 0.489646375179291f, 0.499892801046371f, + 0.490029782056808f, 0.499900579452515f, 0.490413218736649f, 0.499908089637756f, + 0.490796625614166f, 0.499915301799774f, 0.491180062294006f, 0.499922215938568f, + 0.491563498973846f, 0.499928832054138f, 0.491946935653687f, 0.499935150146484f, + 0.492330402135849f, 0.499941170215607f, 0.492713838815689f, 0.499946922063828f, + 0.493097305297852f, 0.499952346086502f, 0.493480771780014f, 0.499957501888275f, + 0.493864238262177f, 0.499962359666824f, 0.494247704744339f, 0.499966919422150f, + 0.494631171226501f, 0.499971181154251f, 0.495014637708664f, 0.499975144863129f, + 0.495398133993149f, 0.499978810548782f, 0.495781600475311f, 0.499982208013535f, + 0.496165096759796f, 0.499985307455063f, 0.496548563241959f, 0.499988079071045f, + 0.496932059526443f, 0.499990582466125f, 0.497315555810928f, 0.499992787837982f, + 0.497699022293091f, 0.499994695186615f, 0.498082518577576f, 0.499996334314346f, + 0.498466014862061f, 0.499997645616531f, 0.498849511146545f, 0.499998688697815f, + 0.499233007431030f, 0.499999403953552f, 0.499616503715515f, 0.499999850988388f, +}; + + +/** + @par + Generation of realCoefB array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ */ + +const float32_t realCoefB[8192] = { + 0.500000000000000f, 0.500000000000000f, 0.500383496284485f, 0.499999850988388f, + 0.500766992568970f, 0.499999403953552f, 0.501150488853455f, 0.499998688697815f, + 0.501533985137939f, 0.499997645616531f, 0.501917481422424f, 0.499996334314346f, + 0.502300977706909f, 0.499994695186615f, 0.502684473991394f, 0.499992787837982f, + 0.503067970275879f, 0.499990582466125f, 0.503451406955719f, 0.499988079071045f, + 0.503834903240204f, 0.499985307455063f, 0.504218399524689f, 0.499982208013535f, + 0.504601895809174f, 0.499978810548782f, 0.504985332489014f, 0.499975144863129f, + 0.505368828773499f, 0.499971181154251f, 0.505752325057983f, 0.499966919422150f, + 0.506135761737823f, 0.499962359666824f, 0.506519258022308f, 0.499957501888275f, + 0.506902694702148f, 0.499952346086502f, 0.507286131381989f, 0.499946922063828f, + 0.507669627666473f, 0.499941170215607f, 0.508053064346313f, 0.499935150146484f, + 0.508436501026154f, 0.499928832054138f, 0.508819937705994f, 0.499922215938568f, + 0.509203374385834f, 0.499915301799774f, 0.509586811065674f, 0.499908089637756f, + 0.509970188140869f, 0.499900579452515f, 0.510353624820709f, 0.499892801046371f, + 0.510737061500549f, 0.499884694814682f, 0.511120438575745f, 0.499876320362091f, + 0.511503815650940f, 0.499867647886276f, 0.511887252330780f, 0.499858677387238f, + 0.512270629405975f, 0.499849408864975f, 0.512654006481171f, 0.499839842319489f, + 0.513037383556366f, 0.499830007553101f, 0.513420701026917f, 0.499819844961166f, + 0.513804078102112f, 0.499809414148331f, 0.514187395572662f, 0.499798685312271f, + 0.514570772647858f, 0.499787658452988f, 0.514954090118408f, 0.499776333570480f, + 0.515337407588959f, 0.499764710664749f, 0.515720725059509f, 0.499752789735794f, + 0.516103982925415f, 0.499740600585938f, 0.516487300395966f, 0.499728083610535f, + 0.516870558261871f, 0.499715298414230f, 0.517253875732422f, 0.499702215194702f, + 0.517637133598328f, 0.499688833951950f, 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for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q31 format + round(pATable[i] * pow(2, 31)) +*/ +const q31_t realCoefAQ31[8192] = { + (q31_t)0x40000000, (q31_t)0xc0000000, (q31_t)0x3ff36f02, (q31_t)0xc000013c, + (q31_t)0x3fe6de05, (q31_t)0xc00004ef, (q31_t)0x3fda4d09, (q31_t)0xc0000b1a, + (q31_t)0x3fcdbc0f, (q31_t)0xc00013bd, (q31_t)0x3fc12b16, (q31_t)0xc0001ed8, + (q31_t)0x3fb49a1f, (q31_t)0xc0002c6a, (q31_t)0x3fa8092c, (q31_t)0xc0003c74, + (q31_t)0x3f9b783c, (q31_t)0xc0004ef5, (q31_t)0x3f8ee750, (q31_t)0xc00063ee, + (q31_t)0x3f825668, (q31_t)0xc0007b5f, (q31_t)0x3f75c585, (q31_t)0xc0009547, + (q31_t)0x3f6934a8, (q31_t)0xc000b1a7, (q31_t)0x3f5ca3d0, (q31_t)0xc000d07e, + (q31_t)0x3f5012fe, (q31_t)0xc000f1ce, (q31_t)0x3f438234, (q31_t)0xc0011594, + (q31_t)0x3f36f170, (q31_t)0xc0013bd3, (q31_t)0x3f2a60b4, (q31_t)0xc0016489, + (q31_t)0x3f1dd001, (q31_t)0xc0018fb6, (q31_t)0x3f113f56, (q31_t)0xc001bd5c, + (q31_t)0x3f04aeb5, (q31_t)0xc001ed78, (q31_t)0x3ef81e1d, (q31_t)0xc002200d, + (q31_t)0x3eeb8d8f, (q31_t)0xc0025519, (q31_t)0x3edefd0c, (q31_t)0xc0028c9c, + (q31_t)0x3ed26c94, (q31_t)0xc002c697, (q31_t)0x3ec5dc28, (q31_t)0xc003030a, + (q31_t)0x3eb94bc8, (q31_t)0xc00341f4, (q31_t)0x3eacbb74, (q31_t)0xc0038356, + (q31_t)0x3ea02b2e, (q31_t)0xc003c72f, (q31_t)0x3e939af5, (q31_t)0xc0040d80, + (q31_t)0x3e870aca, (q31_t)0xc0045648, (q31_t)0x3e7a7aae, (q31_t)0xc004a188, + (q31_t)0x3e6deaa1, (q31_t)0xc004ef3f, (q31_t)0x3e615aa3, (q31_t)0xc0053f6e, + (q31_t)0x3e54cab5, (q31_t)0xc0059214, (q31_t)0x3e483ad8, (q31_t)0xc005e731, + (q31_t)0x3e3bab0b, (q31_t)0xc0063ec6, (q31_t)0x3e2f1b50, (q31_t)0xc00698d3, + (q31_t)0x3e228ba7, (q31_t)0xc006f556, (q31_t)0x3e15fc11, (q31_t)0xc0075452, + (q31_t)0x3e096c8d, (q31_t)0xc007b5c4, (q31_t)0x3dfcdd1d, (q31_t)0xc00819ae, + (q31_t)0x3df04dc0, (q31_t)0xc008800f, (q31_t)0x3de3be78, (q31_t)0xc008e8e8, + (q31_t)0x3dd72f45, (q31_t)0xc0095438, (q31_t)0x3dcaa027, (q31_t)0xc009c1ff, + (q31_t)0x3dbe111e, (q31_t)0xc00a323d, (q31_t)0x3db1822c, (q31_t)0xc00aa4f3, + (q31_t)0x3da4f351, (q31_t)0xc00b1a20, (q31_t)0x3d98648d, (q31_t)0xc00b91c4, + (q31_t)0x3d8bd5e1, (q31_t)0xc00c0be0, (q31_t)0x3d7f474d, (q31_t)0xc00c8872, + (q31_t)0x3d72b8d2, (q31_t)0xc00d077c, (q31_t)0x3d662a70, (q31_t)0xc00d88fd, + (q31_t)0x3d599c28, (q31_t)0xc00e0cf5, (q31_t)0x3d4d0df9, (q31_t)0xc00e9364, + (q31_t)0x3d407fe6, (q31_t)0xc00f1c4a, (q31_t)0x3d33f1ed, (q31_t)0xc00fa7a8, + (q31_t)0x3d276410, (q31_t)0xc010357c, (q31_t)0x3d1ad650, (q31_t)0xc010c5c7, + (q31_t)0x3d0e48ab, (q31_t)0xc011588a, (q31_t)0x3d01bb24, (q31_t)0xc011edc3, + (q31_t)0x3cf52dbb, (q31_t)0xc0128574, (q31_t)0x3ce8a06f, (q31_t)0xc0131f9b, + (q31_t)0x3cdc1342, (q31_t)0xc013bc39, (q31_t)0x3ccf8634, (q31_t)0xc0145b4e, + (q31_t)0x3cc2f945, (q31_t)0xc014fcda, (q31_t)0x3cb66c77, (q31_t)0xc015a0dd, + (q31_t)0x3ca9dfc8, (q31_t)0xc0164757, (q31_t)0x3c9d533b, (q31_t)0xc016f047, + (q31_t)0x3c90c6cf, (q31_t)0xc0179bae, (q31_t)0x3c843a85, (q31_t)0xc018498c, + (q31_t)0x3c77ae5e, (q31_t)0xc018f9e1, (q31_t)0x3c6b2259, (q31_t)0xc019acac, + (q31_t)0x3c5e9678, (q31_t)0xc01a61ee, (q31_t)0x3c520aba, (q31_t)0xc01b19a7, + (q31_t)0x3c457f21, (q31_t)0xc01bd3d6, (q31_t)0x3c38f3ac, (q31_t)0xc01c907c, + (q31_t)0x3c2c685d, (q31_t)0xc01d4f99, (q31_t)0x3c1fdd34, (q31_t)0xc01e112b, + (q31_t)0x3c135231, (q31_t)0xc01ed535, (q31_t)0x3c06c754, (q31_t)0xc01f9bb5, + (q31_t)0x3bfa3c9f, (q31_t)0xc02064ab, (q31_t)0x3bedb212, (q31_t)0xc0213018, + (q31_t)0x3be127ac, (q31_t)0xc021fdfb, (q31_t)0x3bd49d70, (q31_t)0xc022ce54, + (q31_t)0x3bc8135c, (q31_t)0xc023a124, (q31_t)0x3bbb8973, (q31_t)0xc024766a, + (q31_t)0x3baeffb3, (q31_t)0xc0254e27, (q31_t)0x3ba2761e, (q31_t)0xc0262859, + (q31_t)0x3b95ecb4, (q31_t)0xc0270502, (q31_t)0x3b896375, (q31_t)0xc027e421, + (q31_t)0x3b7cda63, (q31_t)0xc028c5b6, (q31_t)0x3b70517d, (q31_t)0xc029a9c1, + (q31_t)0x3b63c8c4, (q31_t)0xc02a9042, (q31_t)0x3b574039, (q31_t)0xc02b7939, + (q31_t)0x3b4ab7db, (q31_t)0xc02c64a6, (q31_t)0x3b3e2fac, (q31_t)0xc02d5289, + (q31_t)0x3b31a7ac, (q31_t)0xc02e42e2, (q31_t)0x3b251fdc, (q31_t)0xc02f35b1, + (q31_t)0x3b18983b, (q31_t)0xc0302af5, (q31_t)0x3b0c10cb, (q31_t)0xc03122b0, + (q31_t)0x3aff898c, (q31_t)0xc0321ce0, (q31_t)0x3af3027e, (q31_t)0xc0331986, + (q31_t)0x3ae67ba2, (q31_t)0xc03418a2, (q31_t)0x3ad9f4f8, (q31_t)0xc0351a33, + (q31_t)0x3acd6e81, (q31_t)0xc0361e3a, (q31_t)0x3ac0e83d, (q31_t)0xc03724b6, + (q31_t)0x3ab4622d, (q31_t)0xc0382da8, (q31_t)0x3aa7dc52, (q31_t)0xc0393910, + (q31_t)0x3a9b56ab, (q31_t)0xc03a46ed, (q31_t)0x3a8ed139, (q31_t)0xc03b573f, + (q31_t)0x3a824bfd, (q31_t)0xc03c6a07, (q31_t)0x3a75c6f8, (q31_t)0xc03d7f44, + (q31_t)0x3a694229, (q31_t)0xc03e96f6, (q31_t)0x3a5cbd91, (q31_t)0xc03fb11d, + (q31_t)0x3a503930, (q31_t)0xc040cdba, (q31_t)0x3a43b508, (q31_t)0xc041eccc, + (q31_t)0x3a373119, (q31_t)0xc0430e53, (q31_t)0x3a2aad62, (q31_t)0xc044324f, + (q31_t)0x3a1e29e5, (q31_t)0xc04558c0, (q31_t)0x3a11a6a3, (q31_t)0xc04681a6, + (q31_t)0x3a05239a, (q31_t)0xc047ad01, (q31_t)0x39f8a0cd, (q31_t)0xc048dad1, + (q31_t)0x39ec1e3b, (q31_t)0xc04a0b16, (q31_t)0x39df9be6, (q31_t)0xc04b3dcf, + (q31_t)0x39d319cc, (q31_t)0xc04c72fe, (q31_t)0x39c697f0, (q31_t)0xc04daaa1, + (q31_t)0x39ba1651, (q31_t)0xc04ee4b8, (q31_t)0x39ad94f0, (q31_t)0xc0502145, + (q31_t)0x39a113cd, (q31_t)0xc0516045, (q31_t)0x399492ea, (q31_t)0xc052a1bb, + (q31_t)0x39881245, (q31_t)0xc053e5a5, (q31_t)0x397b91e1, (q31_t)0xc0552c03, + (q31_t)0x396f11bc, (q31_t)0xc05674d6, (q31_t)0x396291d9, (q31_t)0xc057c01d, + (q31_t)0x39561237, (q31_t)0xc0590dd8, (q31_t)0x394992d7, (q31_t)0xc05a5e07, + (q31_t)0x393d13b8, (q31_t)0xc05bb0ab, (q31_t)0x393094dd, (q31_t)0xc05d05c3, + (q31_t)0x39241645, (q31_t)0xc05e5d4e, (q31_t)0x391797f0, (q31_t)0xc05fb74e, + (q31_t)0x390b19e0, (q31_t)0xc06113c2, (q31_t)0x38fe9c15, (q31_t)0xc06272aa, + (q31_t)0x38f21e8e, (q31_t)0xc063d405, (q31_t)0x38e5a14d, (q31_t)0xc06537d4, + (q31_t)0x38d92452, (q31_t)0xc0669e18, (q31_t)0x38cca79e, (q31_t)0xc06806ce, + (q31_t)0x38c02b31, (q31_t)0xc06971f9, (q31_t)0x38b3af0c, (q31_t)0xc06adf97, + (q31_t)0x38a7332e, (q31_t)0xc06c4fa8, (q31_t)0x389ab799, (q31_t)0xc06dc22e, + (q31_t)0x388e3c4d, (q31_t)0xc06f3726, (q31_t)0x3881c14b, (q31_t)0xc070ae92, + (q31_t)0x38754692, (q31_t)0xc0722871, (q31_t)0x3868cc24, (q31_t)0xc073a4c3, + (q31_t)0x385c5201, (q31_t)0xc0752389, (q31_t)0x384fd829, (q31_t)0xc076a4c2, + (q31_t)0x38435e9d, (q31_t)0xc078286e, (q31_t)0x3836e55d, (q31_t)0xc079ae8c, + (q31_t)0x382a6c6a, (q31_t)0xc07b371e, (q31_t)0x381df3c5, (q31_t)0xc07cc223, + (q31_t)0x38117b6d, (q31_t)0xc07e4f9b, (q31_t)0x38050364, (q31_t)0xc07fdf85, + (q31_t)0x37f88ba9, (q31_t)0xc08171e2, (q31_t)0x37ec143e, (q31_t)0xc08306b2, + (q31_t)0x37df9d22, (q31_t)0xc0849df4, (q31_t)0x37d32657, (q31_t)0xc08637a9, + (q31_t)0x37c6afdc, (q31_t)0xc087d3d0, (q31_t)0x37ba39b3, (q31_t)0xc089726a, + (q31_t)0x37adc3db, (q31_t)0xc08b1376, (q31_t)0x37a14e55, (q31_t)0xc08cb6f5, + (q31_t)0x3794d922, (q31_t)0xc08e5ce5, (q31_t)0x37886442, (q31_t)0xc0900548, + (q31_t)0x377befb5, (q31_t)0xc091b01d, (q31_t)0x376f7b7d, (q31_t)0xc0935d64, + (q31_t)0x37630799, (q31_t)0xc0950d1d, (q31_t)0x3756940a, (q31_t)0xc096bf48, + (q31_t)0x374a20d0, (q31_t)0xc09873e4, (q31_t)0x373daded, (q31_t)0xc09a2af3, + (q31_t)0x37313b60, (q31_t)0xc09be473, (q31_t)0x3724c92a, (q31_t)0xc09da065, + (q31_t)0x3718574b, (q31_t)0xc09f5ec8, (q31_t)0x370be5c4, (q31_t)0xc0a11f9d, + (q31_t)0x36ff7496, (q31_t)0xc0a2e2e3, (q31_t)0x36f303c0, (q31_t)0xc0a4a89b, + (q31_t)0x36e69344, (q31_t)0xc0a670c4, (q31_t)0x36da2321, (q31_t)0xc0a83b5e, + (q31_t)0x36cdb359, (q31_t)0xc0aa086a, (q31_t)0x36c143ec, (q31_t)0xc0abd7e6, + (q31_t)0x36b4d4d9, (q31_t)0xc0ada9d4, (q31_t)0x36a86623, (q31_t)0xc0af7e33, + (q31_t)0x369bf7c9, (q31_t)0xc0b15502, (q31_t)0x368f89cb, (q31_t)0xc0b32e42, + (q31_t)0x36831c2b, (q31_t)0xc0b509f3, (q31_t)0x3676aee8, (q31_t)0xc0b6e815, + (q31_t)0x366a4203, (q31_t)0xc0b8c8a7, (q31_t)0x365dd57d, (q31_t)0xc0baabaa, + (q31_t)0x36516956, (q31_t)0xc0bc911d, (q31_t)0x3644fd8f, (q31_t)0xc0be7901, + (q31_t)0x36389228, (q31_t)0xc0c06355, (q31_t)0x362c2721, (q31_t)0xc0c25019, + (q31_t)0x361fbc7b, (q31_t)0xc0c43f4d, (q31_t)0x36135237, (q31_t)0xc0c630f2, + (q31_t)0x3606e854, (q31_t)0xc0c82506, (q31_t)0x35fa7ed4, (q31_t)0xc0ca1b8a, + (q31_t)0x35ee15b7, (q31_t)0xc0cc147f, (q31_t)0x35e1acfd, (q31_t)0xc0ce0fe3, + (q31_t)0x35d544a7, (q31_t)0xc0d00db6, (q31_t)0x35c8dcb6, (q31_t)0xc0d20dfa, + (q31_t)0x35bc7529, (q31_t)0xc0d410ad, (q31_t)0x35b00e02, (q31_t)0xc0d615cf, + (q31_t)0x35a3a740, (q31_t)0xc0d81d61, (q31_t)0x359740e5, (q31_t)0xc0da2762, + (q31_t)0x358adaf0, (q31_t)0xc0dc33d2, (q31_t)0x357e7563, (q31_t)0xc0de42b2, + (q31_t)0x3572103d, (q31_t)0xc0e05401, (q31_t)0x3565ab80, (q31_t)0xc0e267be, + (q31_t)0x3559472b, (q31_t)0xc0e47deb, (q31_t)0x354ce33f, (q31_t)0xc0e69686, + (q31_t)0x35407fbd, (q31_t)0xc0e8b190, (q31_t)0x35341ca5, (q31_t)0xc0eacf09, + (q31_t)0x3527b9f7, (q31_t)0xc0eceef1, (q31_t)0x351b57b5, (q31_t)0xc0ef1147, + (q31_t)0x350ef5de, (q31_t)0xc0f1360b, (q31_t)0x35029473, (q31_t)0xc0f35d3e, + (q31_t)0x34f63374, (q31_t)0xc0f586df, (q31_t)0x34e9d2e3, (q31_t)0xc0f7b2ee, + (q31_t)0x34dd72be, (q31_t)0xc0f9e16b, (q31_t)0x34d11308, (q31_t)0xc0fc1257, + (q31_t)0x34c4b3c0, (q31_t)0xc0fe45b0, (q31_t)0x34b854e7, (q31_t)0xc1007b77, + (q31_t)0x34abf67e, (q31_t)0xc102b3ac, (q31_t)0x349f9884, (q31_t)0xc104ee4f, + (q31_t)0x34933afa, (q31_t)0xc1072b5f, (q31_t)0x3486dde1, (q31_t)0xc1096add, + (q31_t)0x347a8139, (q31_t)0xc10bacc8, (q31_t)0x346e2504, (q31_t)0xc10df120, + (q31_t)0x3461c940, (q31_t)0xc11037e6, (q31_t)0x34556def, (q31_t)0xc1128119, + (q31_t)0x34491311, (q31_t)0xc114ccb9, (q31_t)0x343cb8a7, (q31_t)0xc1171ac6, + (q31_t)0x34305eb0, (q31_t)0xc1196b3f, (q31_t)0x3424052f, (q31_t)0xc11bbe26, + (q31_t)0x3417ac22, (q31_t)0xc11e1379, (q31_t)0x340b538b, (q31_t)0xc1206b39, + (q31_t)0x33fefb6a, (q31_t)0xc122c566, (q31_t)0x33f2a3bf, (q31_t)0xc12521ff, + (q31_t)0x33e64c8c, (q31_t)0xc1278104, (q31_t)0x33d9f5cf, (q31_t)0xc129e276, + (q31_t)0x33cd9f8b, (q31_t)0xc12c4653, (q31_t)0x33c149bf, (q31_t)0xc12eac9d, + (q31_t)0x33b4f46c, (q31_t)0xc1311553, (q31_t)0x33a89f92, (q31_t)0xc1338075, + (q31_t)0x339c4b32, (q31_t)0xc135ee02, (q31_t)0x338ff74d, (q31_t)0xc1385dfb, + (q31_t)0x3383a3e2, (q31_t)0xc13ad060, (q31_t)0x337750f2, (q31_t)0xc13d4530, + (q31_t)0x336afe7e, (q31_t)0xc13fbc6c, (q31_t)0x335eac86, (q31_t)0xc1423613, + (q31_t)0x33525b0b, (q31_t)0xc144b225, (q31_t)0x33460a0d, (q31_t)0xc14730a3, + (q31_t)0x3339b98d, (q31_t)0xc149b18b, (q31_t)0x332d698a, (q31_t)0xc14c34df, + (q31_t)0x33211a07, (q31_t)0xc14eba9d, (q31_t)0x3314cb02, (q31_t)0xc15142c6, + (q31_t)0x33087c7d, (q31_t)0xc153cd5a, (q31_t)0x32fc2e77, (q31_t)0xc1565a58, + (q31_t)0x32efe0f2, (q31_t)0xc158e9c1, (q31_t)0x32e393ef, (q31_t)0xc15b7b94, + (q31_t)0x32d7476c, (q31_t)0xc15e0fd1, (q31_t)0x32cafb6b, (q31_t)0xc160a678, + (q31_t)0x32beafed, (q31_t)0xc1633f8a, (q31_t)0x32b264f2, (q31_t)0xc165db05, + (q31_t)0x32a61a7a, (q31_t)0xc16878eb, (q31_t)0x3299d085, (q31_t)0xc16b193a, + (q31_t)0x328d8715, (q31_t)0xc16dbbf3, (q31_t)0x32813e2a, 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(q31_t)0x3acd6e81, (q31_t)0x3fc9e1c6, (q31_t)0x3ad9f4f8, (q31_t)0x3fcae5cd, + (q31_t)0x3ae67ba2, (q31_t)0x3fcbe75e, (q31_t)0x3af3027e, (q31_t)0x3fcce67a, + (q31_t)0x3aff898c, (q31_t)0x3fcde320, (q31_t)0x3b0c10cb, (q31_t)0x3fcedd50, + (q31_t)0x3b18983b, (q31_t)0x3fcfd50b, (q31_t)0x3b251fdc, (q31_t)0x3fd0ca4f, + (q31_t)0x3b31a7ac, (q31_t)0x3fd1bd1e, (q31_t)0x3b3e2fac, (q31_t)0x3fd2ad77, + (q31_t)0x3b4ab7db, (q31_t)0x3fd39b5a, (q31_t)0x3b574039, (q31_t)0x3fd486c7, + (q31_t)0x3b63c8c4, (q31_t)0x3fd56fbe, (q31_t)0x3b70517d, (q31_t)0x3fd6563f, + (q31_t)0x3b7cda63, (q31_t)0x3fd73a4a, (q31_t)0x3b896375, (q31_t)0x3fd81bdf, + (q31_t)0x3b95ecb4, (q31_t)0x3fd8fafe, (q31_t)0x3ba2761e, (q31_t)0x3fd9d7a7, + (q31_t)0x3baeffb3, (q31_t)0x3fdab1d9, (q31_t)0x3bbb8973, (q31_t)0x3fdb8996, + (q31_t)0x3bc8135c, (q31_t)0x3fdc5edc, (q31_t)0x3bd49d70, (q31_t)0x3fdd31ac, + (q31_t)0x3be127ac, (q31_t)0x3fde0205, (q31_t)0x3bedb212, (q31_t)0x3fdecfe8, + (q31_t)0x3bfa3c9f, (q31_t)0x3fdf9b55, (q31_t)0x3c06c754, (q31_t)0x3fe0644b, + (q31_t)0x3c135231, (q31_t)0x3fe12acb, (q31_t)0x3c1fdd34, (q31_t)0x3fe1eed5, + (q31_t)0x3c2c685d, (q31_t)0x3fe2b067, (q31_t)0x3c38f3ac, (q31_t)0x3fe36f84, + (q31_t)0x3c457f21, (q31_t)0x3fe42c2a, (q31_t)0x3c520aba, (q31_t)0x3fe4e659, + (q31_t)0x3c5e9678, (q31_t)0x3fe59e12, (q31_t)0x3c6b2259, (q31_t)0x3fe65354, + (q31_t)0x3c77ae5e, (q31_t)0x3fe7061f, (q31_t)0x3c843a85, (q31_t)0x3fe7b674, + (q31_t)0x3c90c6cf, (q31_t)0x3fe86452, (q31_t)0x3c9d533b, (q31_t)0x3fe90fb9, + (q31_t)0x3ca9dfc8, (q31_t)0x3fe9b8a9, (q31_t)0x3cb66c77, (q31_t)0x3fea5f23, + (q31_t)0x3cc2f945, (q31_t)0x3feb0326, (q31_t)0x3ccf8634, (q31_t)0x3feba4b2, + (q31_t)0x3cdc1342, (q31_t)0x3fec43c7, (q31_t)0x3ce8a06f, (q31_t)0x3fece065, + (q31_t)0x3cf52dbb, (q31_t)0x3fed7a8c, (q31_t)0x3d01bb24, (q31_t)0x3fee123d, + (q31_t)0x3d0e48ab, (q31_t)0x3feea776, (q31_t)0x3d1ad650, (q31_t)0x3fef3a39, + (q31_t)0x3d276410, (q31_t)0x3fefca84, (q31_t)0x3d33f1ed, (q31_t)0x3ff05858, + (q31_t)0x3d407fe6, (q31_t)0x3ff0e3b6, (q31_t)0x3d4d0df9, (q31_t)0x3ff16c9c, + (q31_t)0x3d599c28, (q31_t)0x3ff1f30b, (q31_t)0x3d662a70, (q31_t)0x3ff27703, + (q31_t)0x3d72b8d2, (q31_t)0x3ff2f884, (q31_t)0x3d7f474d, (q31_t)0x3ff3778e, + (q31_t)0x3d8bd5e1, (q31_t)0x3ff3f420, (q31_t)0x3d98648d, (q31_t)0x3ff46e3c, + (q31_t)0x3da4f351, (q31_t)0x3ff4e5e0, (q31_t)0x3db1822c, (q31_t)0x3ff55b0d, + (q31_t)0x3dbe111e, (q31_t)0x3ff5cdc3, (q31_t)0x3dcaa027, (q31_t)0x3ff63e01, + (q31_t)0x3dd72f45, (q31_t)0x3ff6abc8, (q31_t)0x3de3be78, (q31_t)0x3ff71718, + (q31_t)0x3df04dc0, (q31_t)0x3ff77ff1, (q31_t)0x3dfcdd1d, (q31_t)0x3ff7e652, + (q31_t)0x3e096c8d, (q31_t)0x3ff84a3c, (q31_t)0x3e15fc11, (q31_t)0x3ff8abae, + (q31_t)0x3e228ba7, (q31_t)0x3ff90aaa, (q31_t)0x3e2f1b50, (q31_t)0x3ff9672d, + (q31_t)0x3e3bab0b, (q31_t)0x3ff9c13a, (q31_t)0x3e483ad8, (q31_t)0x3ffa18cf, + (q31_t)0x3e54cab5, (q31_t)0x3ffa6dec, (q31_t)0x3e615aa3, (q31_t)0x3ffac092, + (q31_t)0x3e6deaa1, (q31_t)0x3ffb10c1, (q31_t)0x3e7a7aae, (q31_t)0x3ffb5e78, + (q31_t)0x3e870aca, (q31_t)0x3ffba9b8, (q31_t)0x3e939af5, (q31_t)0x3ffbf280, + (q31_t)0x3ea02b2e, (q31_t)0x3ffc38d1, (q31_t)0x3eacbb74, (q31_t)0x3ffc7caa, + (q31_t)0x3eb94bc8, (q31_t)0x3ffcbe0c, (q31_t)0x3ec5dc28, (q31_t)0x3ffcfcf6, + (q31_t)0x3ed26c94, (q31_t)0x3ffd3969, (q31_t)0x3edefd0c, (q31_t)0x3ffd7364, + (q31_t)0x3eeb8d8f, (q31_t)0x3ffdaae7, (q31_t)0x3ef81e1d, (q31_t)0x3ffddff3, + (q31_t)0x3f04aeb5, (q31_t)0x3ffe1288, (q31_t)0x3f113f56, (q31_t)0x3ffe42a4, + (q31_t)0x3f1dd001, (q31_t)0x3ffe704a, (q31_t)0x3f2a60b4, (q31_t)0x3ffe9b77, + (q31_t)0x3f36f170, (q31_t)0x3ffec42d, (q31_t)0x3f438234, (q31_t)0x3ffeea6c, + (q31_t)0x3f5012fe, (q31_t)0x3fff0e32, (q31_t)0x3f5ca3d0, (q31_t)0x3fff2f82, + (q31_t)0x3f6934a8, (q31_t)0x3fff4e59, (q31_t)0x3f75c585, (q31_t)0x3fff6ab9, + (q31_t)0x3f825668, (q31_t)0x3fff84a1, (q31_t)0x3f8ee750, (q31_t)0x3fff9c12, + (q31_t)0x3f9b783c, (q31_t)0x3fffb10b, (q31_t)0x3fa8092c, (q31_t)0x3fffc38c, + (q31_t)0x3fb49a1f, (q31_t)0x3fffd396, (q31_t)0x3fc12b16, (q31_t)0x3fffe128, + (q31_t)0x3fcdbc0f, (q31_t)0x3fffec43, (q31_t)0x3fda4d09, (q31_t)0x3ffff4e6, + (q31_t)0x3fe6de05, (q31_t)0x3ffffb11, (q31_t)0x3ff36f02, (q31_t)0x3ffffec4, +}; + + +/** + @par + Generation of realCoefBQ31 array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q31 format + round(pBTable[i] * pow(2, 31)) + */ + +const q31_t realCoefBQ31[8192] = { + (q31_t)0x40000000, (q31_t)0x40000000, (q31_t)0x400c90fe, (q31_t)0x3ffffec4, + (q31_t)0x401921fb, (q31_t)0x3ffffb11, (q31_t)0x4025b2f7, (q31_t)0x3ffff4e6, + (q31_t)0x403243f1, (q31_t)0x3fffec43, (q31_t)0x403ed4ea, (q31_t)0x3fffe128, + (q31_t)0x404b65e1, (q31_t)0x3fffd396, (q31_t)0x4057f6d4, (q31_t)0x3fffc38c, + (q31_t)0x406487c4, (q31_t)0x3fffb10b, (q31_t)0x407118b0, (q31_t)0x3fff9c12, + (q31_t)0x407da998, (q31_t)0x3fff84a1, (q31_t)0x408a3a7b, (q31_t)0x3fff6ab9, + (q31_t)0x4096cb58, (q31_t)0x3fff4e59, (q31_t)0x40a35c30, (q31_t)0x3fff2f82, + (q31_t)0x40afed02, (q31_t)0x3fff0e32, (q31_t)0x40bc7dcc, (q31_t)0x3ffeea6c, + (q31_t)0x40c90e90, (q31_t)0x3ffec42d, (q31_t)0x40d59f4c, (q31_t)0x3ffe9b77, + (q31_t)0x40e22fff, (q31_t)0x3ffe704a, (q31_t)0x40eec0aa, (q31_t)0x3ffe42a4, + (q31_t)0x40fb514b, (q31_t)0x3ffe1288, (q31_t)0x4107e1e3, (q31_t)0x3ffddff3, + (q31_t)0x41147271, (q31_t)0x3ffdaae7, (q31_t)0x412102f4, (q31_t)0x3ffd7364, + (q31_t)0x412d936c, (q31_t)0x3ffd3969, (q31_t)0x413a23d8, (q31_t)0x3ffcfcf6, + (q31_t)0x4146b438, (q31_t)0x3ffcbe0c, (q31_t)0x4153448c, (q31_t)0x3ffc7caa, + (q31_t)0x415fd4d2, (q31_t)0x3ffc38d1, (q31_t)0x416c650b, (q31_t)0x3ffbf280, + (q31_t)0x4178f536, (q31_t)0x3ffba9b8, (q31_t)0x41858552, (q31_t)0x3ffb5e78, + (q31_t)0x4192155f, (q31_t)0x3ffb10c1, (q31_t)0x419ea55d, (q31_t)0x3ffac092, + (q31_t)0x41ab354b, (q31_t)0x3ffa6dec, (q31_t)0x41b7c528, (q31_t)0x3ffa18cf, + (q31_t)0x41c454f5, (q31_t)0x3ff9c13a, (q31_t)0x41d0e4b0, (q31_t)0x3ff9672d, + (q31_t)0x41dd7459, (q31_t)0x3ff90aaa, (q31_t)0x41ea03ef, (q31_t)0x3ff8abae, + (q31_t)0x41f69373, (q31_t)0x3ff84a3c, (q31_t)0x420322e3, (q31_t)0x3ff7e652, + (q31_t)0x420fb240, (q31_t)0x3ff77ff1, (q31_t)0x421c4188, (q31_t)0x3ff71718, + (q31_t)0x4228d0bb, (q31_t)0x3ff6abc8, (q31_t)0x42355fd9, (q31_t)0x3ff63e01, + (q31_t)0x4241eee2, (q31_t)0x3ff5cdc3, (q31_t)0x424e7dd4, (q31_t)0x3ff55b0d, + (q31_t)0x425b0caf, (q31_t)0x3ff4e5e0, (q31_t)0x42679b73, (q31_t)0x3ff46e3c, + (q31_t)0x42742a1f, (q31_t)0x3ff3f420, (q31_t)0x4280b8b3, (q31_t)0x3ff3778e, + (q31_t)0x428d472e, (q31_t)0x3ff2f884, (q31_t)0x4299d590, (q31_t)0x3ff27703, + (q31_t)0x42a663d8, (q31_t)0x3ff1f30b, (q31_t)0x42b2f207, (q31_t)0x3ff16c9c, + (q31_t)0x42bf801a, (q31_t)0x3ff0e3b6, (q31_t)0x42cc0e13, (q31_t)0x3ff05858, + (q31_t)0x42d89bf0, (q31_t)0x3fefca84, (q31_t)0x42e529b0, (q31_t)0x3fef3a39, + (q31_t)0x42f1b755, (q31_t)0x3feea776, (q31_t)0x42fe44dc, (q31_t)0x3fee123d, + (q31_t)0x430ad245, (q31_t)0x3fed7a8c, (q31_t)0x43175f91, (q31_t)0x3fece065, + (q31_t)0x4323ecbe, (q31_t)0x3fec43c7, (q31_t)0x433079cc, (q31_t)0x3feba4b2, + (q31_t)0x433d06bb, (q31_t)0x3feb0326, (q31_t)0x43499389, (q31_t)0x3fea5f23, + (q31_t)0x43562038, (q31_t)0x3fe9b8a9, (q31_t)0x4362acc5, (q31_t)0x3fe90fb9, + (q31_t)0x436f3931, (q31_t)0x3fe86452, (q31_t)0x437bc57b, (q31_t)0x3fe7b674, + (q31_t)0x438851a2, (q31_t)0x3fe7061f, (q31_t)0x4394dda7, (q31_t)0x3fe65354, + (q31_t)0x43a16988, (q31_t)0x3fe59e12, (q31_t)0x43adf546, (q31_t)0x3fe4e659, + (q31_t)0x43ba80df, (q31_t)0x3fe42c2a, (q31_t)0x43c70c54, (q31_t)0x3fe36f84, + (q31_t)0x43d397a3, (q31_t)0x3fe2b067, (q31_t)0x43e022cc, (q31_t)0x3fe1eed5, + (q31_t)0x43ecadcf, (q31_t)0x3fe12acb, (q31_t)0x43f938ac, (q31_t)0x3fe0644b, + (q31_t)0x4405c361, (q31_t)0x3fdf9b55, (q31_t)0x44124dee, (q31_t)0x3fdecfe8, + (q31_t)0x441ed854, (q31_t)0x3fde0205, (q31_t)0x442b6290, (q31_t)0x3fdd31ac, + (q31_t)0x4437eca4, (q31_t)0x3fdc5edc, (q31_t)0x4444768d, (q31_t)0x3fdb8996, + (q31_t)0x4451004d, (q31_t)0x3fdab1d9, (q31_t)0x445d89e2, (q31_t)0x3fd9d7a7, + (q31_t)0x446a134c, (q31_t)0x3fd8fafe, (q31_t)0x44769c8b, (q31_t)0x3fd81bdf, + (q31_t)0x4483259d, (q31_t)0x3fd73a4a, (q31_t)0x448fae83, (q31_t)0x3fd6563f, + (q31_t)0x449c373c, (q31_t)0x3fd56fbe, (q31_t)0x44a8bfc7, (q31_t)0x3fd486c7, + (q31_t)0x44b54825, (q31_t)0x3fd39b5a, (q31_t)0x44c1d054, (q31_t)0x3fd2ad77, + (q31_t)0x44ce5854, (q31_t)0x3fd1bd1e, (q31_t)0x44dae024, (q31_t)0x3fd0ca4f, + (q31_t)0x44e767c5, (q31_t)0x3fcfd50b, (q31_t)0x44f3ef35, (q31_t)0x3fcedd50, + (q31_t)0x45007674, (q31_t)0x3fcde320, (q31_t)0x450cfd82, (q31_t)0x3fcce67a, + (q31_t)0x4519845e, (q31_t)0x3fcbe75e, (q31_t)0x45260b08, (q31_t)0x3fcae5cd, + (q31_t)0x4532917f, (q31_t)0x3fc9e1c6, (q31_t)0x453f17c3, (q31_t)0x3fc8db4a, + (q31_t)0x454b9dd3, (q31_t)0x3fc7d258, (q31_t)0x455823ae, (q31_t)0x3fc6c6f0, + (q31_t)0x4564a955, (q31_t)0x3fc5b913, (q31_t)0x45712ec7, (q31_t)0x3fc4a8c1, + (q31_t)0x457db403, (q31_t)0x3fc395f9, (q31_t)0x458a3908, (q31_t)0x3fc280bc, + (q31_t)0x4596bdd7, (q31_t)0x3fc1690a, (q31_t)0x45a3426f, (q31_t)0x3fc04ee3, + (q31_t)0x45afc6d0, (q31_t)0x3fbf3246, (q31_t)0x45bc4af8, (q31_t)0x3fbe1334, + (q31_t)0x45c8cee7, (q31_t)0x3fbcf1ad, (q31_t)0x45d5529e, (q31_t)0x3fbbcdb1, + (q31_t)0x45e1d61b, (q31_t)0x3fbaa740, (q31_t)0x45ee595d, (q31_t)0x3fb97e5a, + (q31_t)0x45fadc66, (q31_t)0x3fb852ff, (q31_t)0x46075f33, (q31_t)0x3fb7252f, + (q31_t)0x4613e1c5, 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(q31_t)0x4596bdd7, (q31_t)0xc03e96f6, (q31_t)0x458a3908, (q31_t)0xc03d7f44, + (q31_t)0x457db403, (q31_t)0xc03c6a07, (q31_t)0x45712ec7, (q31_t)0xc03b573f, + (q31_t)0x4564a955, (q31_t)0xc03a46ed, (q31_t)0x455823ae, (q31_t)0xc0393910, + (q31_t)0x454b9dd3, (q31_t)0xc0382da8, (q31_t)0x453f17c3, (q31_t)0xc03724b6, + (q31_t)0x4532917f, (q31_t)0xc0361e3a, (q31_t)0x45260b08, (q31_t)0xc0351a33, + (q31_t)0x4519845e, (q31_t)0xc03418a2, (q31_t)0x450cfd82, (q31_t)0xc0331986, + (q31_t)0x45007674, (q31_t)0xc0321ce0, (q31_t)0x44f3ef35, (q31_t)0xc03122b0, + (q31_t)0x44e767c5, (q31_t)0xc0302af5, (q31_t)0x44dae024, (q31_t)0xc02f35b1, + (q31_t)0x44ce5854, (q31_t)0xc02e42e2, (q31_t)0x44c1d054, (q31_t)0xc02d5289, + (q31_t)0x44b54825, (q31_t)0xc02c64a6, (q31_t)0x44a8bfc7, (q31_t)0xc02b7939, + (q31_t)0x449c373c, (q31_t)0xc02a9042, (q31_t)0x448fae83, (q31_t)0xc029a9c1, + (q31_t)0x4483259d, (q31_t)0xc028c5b6, (q31_t)0x44769c8b, (q31_t)0xc027e421, + (q31_t)0x446a134c, (q31_t)0xc0270502, (q31_t)0x445d89e2, (q31_t)0xc0262859, + (q31_t)0x4451004d, (q31_t)0xc0254e27, (q31_t)0x4444768d, (q31_t)0xc024766a, + (q31_t)0x4437eca4, (q31_t)0xc023a124, (q31_t)0x442b6290, (q31_t)0xc022ce54, + (q31_t)0x441ed854, (q31_t)0xc021fdfb, (q31_t)0x44124dee, (q31_t)0xc0213018, + (q31_t)0x4405c361, (q31_t)0xc02064ab, (q31_t)0x43f938ac, (q31_t)0xc01f9bb5, + (q31_t)0x43ecadcf, (q31_t)0xc01ed535, (q31_t)0x43e022cc, (q31_t)0xc01e112b, + (q31_t)0x43d397a3, (q31_t)0xc01d4f99, (q31_t)0x43c70c54, (q31_t)0xc01c907c, + (q31_t)0x43ba80df, (q31_t)0xc01bd3d6, (q31_t)0x43adf546, (q31_t)0xc01b19a7, + (q31_t)0x43a16988, (q31_t)0xc01a61ee, (q31_t)0x4394dda7, (q31_t)0xc019acac, + (q31_t)0x438851a2, (q31_t)0xc018f9e1, (q31_t)0x437bc57b, (q31_t)0xc018498c, + (q31_t)0x436f3931, (q31_t)0xc0179bae, (q31_t)0x4362acc5, (q31_t)0xc016f047, + (q31_t)0x43562038, (q31_t)0xc0164757, (q31_t)0x43499389, (q31_t)0xc015a0dd, + (q31_t)0x433d06bb, (q31_t)0xc014fcda, (q31_t)0x433079cc, (q31_t)0xc0145b4e, + (q31_t)0x4323ecbe, (q31_t)0xc013bc39, (q31_t)0x43175f91, (q31_t)0xc0131f9b, + (q31_t)0x430ad245, (q31_t)0xc0128574, (q31_t)0x42fe44dc, (q31_t)0xc011edc3, + (q31_t)0x42f1b755, (q31_t)0xc011588a, (q31_t)0x42e529b0, (q31_t)0xc010c5c7, + (q31_t)0x42d89bf0, (q31_t)0xc010357c, (q31_t)0x42cc0e13, (q31_t)0xc00fa7a8, + (q31_t)0x42bf801a, (q31_t)0xc00f1c4a, (q31_t)0x42b2f207, (q31_t)0xc00e9364, + (q31_t)0x42a663d8, (q31_t)0xc00e0cf5, (q31_t)0x4299d590, (q31_t)0xc00d88fd, + (q31_t)0x428d472e, (q31_t)0xc00d077c, (q31_t)0x4280b8b3, (q31_t)0xc00c8872, + (q31_t)0x42742a1f, (q31_t)0xc00c0be0, (q31_t)0x42679b73, (q31_t)0xc00b91c4, + (q31_t)0x425b0caf, (q31_t)0xc00b1a20, (q31_t)0x424e7dd4, (q31_t)0xc00aa4f3, + (q31_t)0x4241eee2, (q31_t)0xc00a323d, (q31_t)0x42355fd9, (q31_t)0xc009c1ff, + (q31_t)0x4228d0bb, (q31_t)0xc0095438, (q31_t)0x421c4188, (q31_t)0xc008e8e8, + (q31_t)0x420fb240, (q31_t)0xc008800f, (q31_t)0x420322e3, (q31_t)0xc00819ae, + (q31_t)0x41f69373, (q31_t)0xc007b5c4, (q31_t)0x41ea03ef, (q31_t)0xc0075452, + (q31_t)0x41dd7459, (q31_t)0xc006f556, (q31_t)0x41d0e4b0, (q31_t)0xc00698d3, + (q31_t)0x41c454f5, (q31_t)0xc0063ec6, (q31_t)0x41b7c528, (q31_t)0xc005e731, + (q31_t)0x41ab354b, (q31_t)0xc0059214, (q31_t)0x419ea55d, (q31_t)0xc0053f6e, + (q31_t)0x4192155f, (q31_t)0xc004ef3f, (q31_t)0x41858552, (q31_t)0xc004a188, + (q31_t)0x4178f536, (q31_t)0xc0045648, (q31_t)0x416c650b, (q31_t)0xc0040d80, + (q31_t)0x415fd4d2, (q31_t)0xc003c72f, (q31_t)0x4153448c, (q31_t)0xc0038356, + (q31_t)0x4146b438, (q31_t)0xc00341f4, (q31_t)0x413a23d8, (q31_t)0xc003030a, + (q31_t)0x412d936c, (q31_t)0xc002c697, (q31_t)0x412102f4, (q31_t)0xc0028c9c, + (q31_t)0x41147271, (q31_t)0xc0025519, (q31_t)0x4107e1e3, (q31_t)0xc002200d, + (q31_t)0x40fb514b, (q31_t)0xc001ed78, (q31_t)0x40eec0aa, (q31_t)0xc001bd5c, + (q31_t)0x40e22fff, (q31_t)0xc0018fb6, (q31_t)0x40d59f4c, (q31_t)0xc0016489, + (q31_t)0x40c90e90, (q31_t)0xc0013bd3, (q31_t)0x40bc7dcc, (q31_t)0xc0011594, + (q31_t)0x40afed02, (q31_t)0xc000f1ce, (q31_t)0x40a35c30, (q31_t)0xc000d07e, + (q31_t)0x4096cb58, (q31_t)0xc000b1a7, (q31_t)0x408a3a7b, (q31_t)0xc0009547, + (q31_t)0x407da998, (q31_t)0xc0007b5f, (q31_t)0x407118b0, (q31_t)0xc00063ee, + (q31_t)0x406487c4, (q31_t)0xc0004ef5, (q31_t)0x4057f6d4, (q31_t)0xc0003c74, + (q31_t)0x404b65e1, (q31_t)0xc0002c6a, (q31_t)0x403ed4ea, (q31_t)0xc0001ed8, + (q31_t)0x403243f1, (q31_t)0xc00013bd, (q31_t)0x4025b2f7, (q31_t)0xc0000b1a, + (q31_t)0x401921fb, (q31_t)0xc00004ef, (q31_t)0x400c90fe, (q31_t)0xc000013c, +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) +/** + @par + Generation fixed-point realCoefAQ15 array in Q15 format: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q15 format + round(pATable[i] * pow(2, 15)) + */ +const q15_t __ALIGNED(4) realCoefAQ15[8192] = { + (q15_t)0x4000, (q15_t)0xc000, (q15_t)0x3ff3, (q15_t)0xc000, (q15_t)0x3fe7, (q15_t)0xc000, (q15_t)0x3fda, (q15_t)0xc000, + (q15_t)0x3fce, (q15_t)0xc000, (q15_t)0x3fc1, (q15_t)0xc000, (q15_t)0x3fb5, (q15_t)0xc000, (q15_t)0x3fa8, (q15_t)0xc000, + (q15_t)0x3f9b, (q15_t)0xc000, (q15_t)0x3f8f, (q15_t)0xc000, (q15_t)0x3f82, (q15_t)0xc000, (q15_t)0x3f76, (q15_t)0xc001, + (q15_t)0x3f69, (q15_t)0xc001, (q15_t)0x3f5d, (q15_t)0xc001, (q15_t)0x3f50, (q15_t)0xc001, (q15_t)0x3f44, (q15_t)0xc001, + (q15_t)0x3f37, (q15_t)0xc001, (q15_t)0x3f2a, (q15_t)0xc001, (q15_t)0x3f1e, (q15_t)0xc002, (q15_t)0x3f11, (q15_t)0xc002, + (q15_t)0x3f05, (q15_t)0xc002, (q15_t)0x3ef8, (q15_t)0xc002, (q15_t)0x3eec, (q15_t)0xc002, (q15_t)0x3edf, (q15_t)0xc003, + (q15_t)0x3ed2, (q15_t)0xc003, (q15_t)0x3ec6, (q15_t)0xc003, (q15_t)0x3eb9, (q15_t)0xc003, (q15_t)0x3ead, (q15_t)0xc004, + (q15_t)0x3ea0, (q15_t)0xc004, (q15_t)0x3e94, (q15_t)0xc004, (q15_t)0x3e87, (q15_t)0xc004, (q15_t)0x3e7a, (q15_t)0xc005, + (q15_t)0x3e6e, (q15_t)0xc005, (q15_t)0x3e61, (q15_t)0xc005, (q15_t)0x3e55, (q15_t)0xc006, (q15_t)0x3e48, (q15_t)0xc006, + (q15_t)0x3e3c, (q15_t)0xc006, (q15_t)0x3e2f, (q15_t)0xc007, (q15_t)0x3e23, (q15_t)0xc007, (q15_t)0x3e16, (q15_t)0xc007, + (q15_t)0x3e09, (q15_t)0xc008, (q15_t)0x3dfd, (q15_t)0xc008, (q15_t)0x3df0, (q15_t)0xc009, (q15_t)0x3de4, (q15_t)0xc009, + (q15_t)0x3dd7, (q15_t)0xc009, (q15_t)0x3dcb, (q15_t)0xc00a, (q15_t)0x3dbe, (q15_t)0xc00a, (q15_t)0x3db2, (q15_t)0xc00b, + (q15_t)0x3da5, (q15_t)0xc00b, (q15_t)0x3d98, (q15_t)0xc00c, (q15_t)0x3d8c, (q15_t)0xc00c, (q15_t)0x3d7f, (q15_t)0xc00d, + (q15_t)0x3d73, (q15_t)0xc00d, (q15_t)0x3d66, (q15_t)0xc00e, (q15_t)0x3d5a, (q15_t)0xc00e, (q15_t)0x3d4d, (q15_t)0xc00f, + (q15_t)0x3d40, (q15_t)0xc00f, (q15_t)0x3d34, (q15_t)0xc010, (q15_t)0x3d27, (q15_t)0xc010, (q15_t)0x3d1b, (q15_t)0xc011, + (q15_t)0x3d0e, (q15_t)0xc011, (q15_t)0x3d02, (q15_t)0xc012, (q15_t)0x3cf5, (q15_t)0xc013, (q15_t)0x3ce9, (q15_t)0xc013, + (q15_t)0x3cdc, (q15_t)0xc014, (q15_t)0x3cd0, (q15_t)0xc014, (q15_t)0x3cc3, (q15_t)0xc015, (q15_t)0x3cb6, (q15_t)0xc016, + (q15_t)0x3caa, (q15_t)0xc016, (q15_t)0x3c9d, (q15_t)0xc017, (q15_t)0x3c91, (q15_t)0xc018, (q15_t)0x3c84, (q15_t)0xc018, + (q15_t)0x3c78, (q15_t)0xc019, (q15_t)0x3c6b, (q15_t)0xc01a, (q15_t)0x3c5f, (q15_t)0xc01a, (q15_t)0x3c52, (q15_t)0xc01b, + (q15_t)0x3c45, (q15_t)0xc01c, (q15_t)0x3c39, (q15_t)0xc01d, (q15_t)0x3c2c, (q15_t)0xc01d, (q15_t)0x3c20, (q15_t)0xc01e, + (q15_t)0x3c13, (q15_t)0xc01f, (q15_t)0x3c07, (q15_t)0xc020, (q15_t)0x3bfa, (q15_t)0xc020, (q15_t)0x3bee, (q15_t)0xc021, + (q15_t)0x3be1, (q15_t)0xc022, (q15_t)0x3bd5, (q15_t)0xc023, (q15_t)0x3bc8, (q15_t)0xc024, (q15_t)0x3bbc, (q15_t)0xc024, + (q15_t)0x3baf, (q15_t)0xc025, (q15_t)0x3ba2, (q15_t)0xc026, (q15_t)0x3b96, (q15_t)0xc027, (q15_t)0x3b89, (q15_t)0xc028, + (q15_t)0x3b7d, (q15_t)0xc029, (q15_t)0x3b70, (q15_t)0xc02a, (q15_t)0x3b64, (q15_t)0xc02b, (q15_t)0x3b57, (q15_t)0xc02b, + (q15_t)0x3b4b, (q15_t)0xc02c, (q15_t)0x3b3e, (q15_t)0xc02d, (q15_t)0x3b32, (q15_t)0xc02e, (q15_t)0x3b25, (q15_t)0xc02f, + (q15_t)0x3b19, (q15_t)0xc030, (q15_t)0x3b0c, (q15_t)0xc031, (q15_t)0x3b00, (q15_t)0xc032, (q15_t)0x3af3, (q15_t)0xc033, + (q15_t)0x3ae6, (q15_t)0xc034, (q15_t)0x3ada, (q15_t)0xc035, (q15_t)0x3acd, (q15_t)0xc036, (q15_t)0x3ac1, (q15_t)0xc037, + (q15_t)0x3ab4, (q15_t)0xc038, (q15_t)0x3aa8, (q15_t)0xc039, (q15_t)0x3a9b, (q15_t)0xc03a, (q15_t)0x3a8f, (q15_t)0xc03b, + (q15_t)0x3a82, (q15_t)0xc03c, (q15_t)0x3a76, (q15_t)0xc03d, (q15_t)0x3a69, (q15_t)0xc03f, (q15_t)0x3a5d, (q15_t)0xc040, + (q15_t)0x3a50, (q15_t)0xc041, (q15_t)0x3a44, (q15_t)0xc042, (q15_t)0x3a37, (q15_t)0xc043, (q15_t)0x3a2b, (q15_t)0xc044, + (q15_t)0x3a1e, (q15_t)0xc045, (q15_t)0x3a12, (q15_t)0xc047, (q15_t)0x3a05, (q15_t)0xc048, (q15_t)0x39f9, (q15_t)0xc049, + (q15_t)0x39ec, (q15_t)0xc04a, (q15_t)0x39e0, (q15_t)0xc04b, (q15_t)0x39d3, (q15_t)0xc04c, (q15_t)0x39c7, (q15_t)0xc04e, + (q15_t)0x39ba, (q15_t)0xc04f, (q15_t)0x39ae, (q15_t)0xc050, (q15_t)0x39a1, (q15_t)0xc051, (q15_t)0x3995, (q15_t)0xc053, + (q15_t)0x3988, (q15_t)0xc054, (q15_t)0x397c, (q15_t)0xc055, (q15_t)0x396f, (q15_t)0xc056, (q15_t)0x3963, (q15_t)0xc058, + (q15_t)0x3956, (q15_t)0xc059, (q15_t)0x394a, (q15_t)0xc05a, (q15_t)0x393d, (q15_t)0xc05c, (q15_t)0x3931, (q15_t)0xc05d, + (q15_t)0x3924, (q15_t)0xc05e, (q15_t)0x3918, (q15_t)0xc060, (q15_t)0x390b, (q15_t)0xc061, (q15_t)0x38ff, (q15_t)0xc062, + (q15_t)0x38f2, (q15_t)0xc064, (q15_t)0x38e6, (q15_t)0xc065, (q15_t)0x38d9, (q15_t)0xc067, (q15_t)0x38cd, (q15_t)0xc068, + (q15_t)0x38c0, (q15_t)0xc069, (q15_t)0x38b4, (q15_t)0xc06b, (q15_t)0x38a7, (q15_t)0xc06c, (q15_t)0x389b, (q15_t)0xc06e, + (q15_t)0x388e, (q15_t)0xc06f, (q15_t)0x3882, (q15_t)0xc071, (q15_t)0x3875, (q15_t)0xc072, (q15_t)0x3869, (q15_t)0xc074, + (q15_t)0x385c, (q15_t)0xc075, (q15_t)0x3850, (q15_t)0xc077, (q15_t)0x3843, (q15_t)0xc078, (q15_t)0x3837, (q15_t)0xc07a, + (q15_t)0x382a, (q15_t)0xc07b, (q15_t)0x381e, (q15_t)0xc07d, (q15_t)0x3811, (q15_t)0xc07e, (q15_t)0x3805, (q15_t)0xc080, + (q15_t)0x37f9, (q15_t)0xc081, (q15_t)0x37ec, (q15_t)0xc083, (q15_t)0x37e0, (q15_t)0xc085, (q15_t)0x37d3, (q15_t)0xc086, + (q15_t)0x37c7, (q15_t)0xc088, (q15_t)0x37ba, (q15_t)0xc089, (q15_t)0x37ae, (q15_t)0xc08b, (q15_t)0x37a1, (q15_t)0xc08d, + (q15_t)0x3795, (q15_t)0xc08e, (q15_t)0x3788, (q15_t)0xc090, (q15_t)0x377c, (q15_t)0xc092, (q15_t)0x376f, (q15_t)0xc093, + (q15_t)0x3763, (q15_t)0xc095, (q15_t)0x3757, (q15_t)0xc097, (q15_t)0x374a, (q15_t)0xc098, (q15_t)0x373e, (q15_t)0xc09a, + (q15_t)0x3731, (q15_t)0xc09c, (q15_t)0x3725, (q15_t)0xc09e, (q15_t)0x3718, (q15_t)0xc09f, (q15_t)0x370c, (q15_t)0xc0a1, + (q15_t)0x36ff, (q15_t)0xc0a3, (q15_t)0x36f3, (q15_t)0xc0a5, (q15_t)0x36e7, (q15_t)0xc0a6, (q15_t)0x36da, (q15_t)0xc0a8, + (q15_t)0x36ce, (q15_t)0xc0aa, (q15_t)0x36c1, (q15_t)0xc0ac, (q15_t)0x36b5, (q15_t)0xc0ae, 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(q15_t)0x3fc6, (q15_t)0x3aa8, (q15_t)0x3fc7, + (q15_t)0x3ab4, (q15_t)0x3fc8, (q15_t)0x3ac1, (q15_t)0x3fc9, (q15_t)0x3acd, (q15_t)0x3fca, (q15_t)0x3ada, (q15_t)0x3fcb, + (q15_t)0x3ae6, (q15_t)0x3fcc, (q15_t)0x3af3, (q15_t)0x3fcd, (q15_t)0x3b00, (q15_t)0x3fce, (q15_t)0x3b0c, (q15_t)0x3fcf, + (q15_t)0x3b19, (q15_t)0x3fd0, (q15_t)0x3b25, (q15_t)0x3fd1, (q15_t)0x3b32, (q15_t)0x3fd2, (q15_t)0x3b3e, (q15_t)0x3fd3, + (q15_t)0x3b4b, (q15_t)0x3fd4, (q15_t)0x3b57, (q15_t)0x3fd5, (q15_t)0x3b64, (q15_t)0x3fd5, (q15_t)0x3b70, (q15_t)0x3fd6, + (q15_t)0x3b7d, (q15_t)0x3fd7, (q15_t)0x3b89, (q15_t)0x3fd8, (q15_t)0x3b96, (q15_t)0x3fd9, (q15_t)0x3ba2, (q15_t)0x3fda, + (q15_t)0x3baf, (q15_t)0x3fdb, (q15_t)0x3bbc, (q15_t)0x3fdc, (q15_t)0x3bc8, (q15_t)0x3fdc, (q15_t)0x3bd5, (q15_t)0x3fdd, + (q15_t)0x3be1, (q15_t)0x3fde, (q15_t)0x3bee, (q15_t)0x3fdf, (q15_t)0x3bfa, (q15_t)0x3fe0, (q15_t)0x3c07, (q15_t)0x3fe0, + (q15_t)0x3c13, (q15_t)0x3fe1, (q15_t)0x3c20, (q15_t)0x3fe2, (q15_t)0x3c2c, (q15_t)0x3fe3, (q15_t)0x3c39, (q15_t)0x3fe3, + (q15_t)0x3c45, (q15_t)0x3fe4, (q15_t)0x3c52, (q15_t)0x3fe5, (q15_t)0x3c5f, (q15_t)0x3fe6, (q15_t)0x3c6b, (q15_t)0x3fe6, + (q15_t)0x3c78, (q15_t)0x3fe7, (q15_t)0x3c84, (q15_t)0x3fe8, (q15_t)0x3c91, (q15_t)0x3fe8, (q15_t)0x3c9d, (q15_t)0x3fe9, + (q15_t)0x3caa, (q15_t)0x3fea, (q15_t)0x3cb6, (q15_t)0x3fea, (q15_t)0x3cc3, (q15_t)0x3feb, (q15_t)0x3cd0, (q15_t)0x3fec, + (q15_t)0x3cdc, (q15_t)0x3fec, (q15_t)0x3ce9, (q15_t)0x3fed, (q15_t)0x3cf5, (q15_t)0x3fed, (q15_t)0x3d02, (q15_t)0x3fee, + (q15_t)0x3d0e, (q15_t)0x3fef, (q15_t)0x3d1b, (q15_t)0x3fef, (q15_t)0x3d27, (q15_t)0x3ff0, (q15_t)0x3d34, (q15_t)0x3ff0, + (q15_t)0x3d40, (q15_t)0x3ff1, (q15_t)0x3d4d, (q15_t)0x3ff1, (q15_t)0x3d5a, (q15_t)0x3ff2, (q15_t)0x3d66, (q15_t)0x3ff2, + (q15_t)0x3d73, (q15_t)0x3ff3, (q15_t)0x3d7f, (q15_t)0x3ff3, (q15_t)0x3d8c, (q15_t)0x3ff4, (q15_t)0x3d98, (q15_t)0x3ff4, + (q15_t)0x3da5, (q15_t)0x3ff5, (q15_t)0x3db2, (q15_t)0x3ff5, (q15_t)0x3dbe, (q15_t)0x3ff6, (q15_t)0x3dcb, (q15_t)0x3ff6, + (q15_t)0x3dd7, (q15_t)0x3ff7, (q15_t)0x3de4, (q15_t)0x3ff7, (q15_t)0x3df0, (q15_t)0x3ff7, (q15_t)0x3dfd, (q15_t)0x3ff8, + (q15_t)0x3e09, (q15_t)0x3ff8, (q15_t)0x3e16, (q15_t)0x3ff9, (q15_t)0x3e23, (q15_t)0x3ff9, (q15_t)0x3e2f, (q15_t)0x3ff9, + (q15_t)0x3e3c, (q15_t)0x3ffa, (q15_t)0x3e48, (q15_t)0x3ffa, (q15_t)0x3e55, (q15_t)0x3ffa, (q15_t)0x3e61, (q15_t)0x3ffb, + (q15_t)0x3e6e, (q15_t)0x3ffb, (q15_t)0x3e7a, (q15_t)0x3ffb, (q15_t)0x3e87, (q15_t)0x3ffc, (q15_t)0x3e94, (q15_t)0x3ffc, + (q15_t)0x3ea0, (q15_t)0x3ffc, (q15_t)0x3ead, (q15_t)0x3ffc, (q15_t)0x3eb9, (q15_t)0x3ffd, (q15_t)0x3ec6, (q15_t)0x3ffd, + (q15_t)0x3ed2, (q15_t)0x3ffd, (q15_t)0x3edf, (q15_t)0x3ffd, (q15_t)0x3eec, (q15_t)0x3ffe, (q15_t)0x3ef8, (q15_t)0x3ffe, + (q15_t)0x3f05, (q15_t)0x3ffe, (q15_t)0x3f11, (q15_t)0x3ffe, (q15_t)0x3f1e, (q15_t)0x3ffe, (q15_t)0x3f2a, (q15_t)0x3fff, + (q15_t)0x3f37, (q15_t)0x3fff, (q15_t)0x3f44, (q15_t)0x3fff, (q15_t)0x3f50, (q15_t)0x3fff, (q15_t)0x3f5d, (q15_t)0x3fff, + (q15_t)0x3f69, (q15_t)0x3fff, (q15_t)0x3f76, (q15_t)0x3fff, (q15_t)0x3f82, (q15_t)0x4000, (q15_t)0x3f8f, (q15_t)0x4000, + (q15_t)0x3f9b, (q15_t)0x4000, (q15_t)0x3fa8, (q15_t)0x4000, (q15_t)0x3fb5, (q15_t)0x4000, (q15_t)0x3fc1, (q15_t)0x4000, + (q15_t)0x3fce, (q15_t)0x4000, (q15_t)0x3fda, (q15_t)0x4000, (q15_t)0x3fe7, (q15_t)0x4000, (q15_t)0x3ff3, (q15_t)0x4000, +}; + +/** + @par + Generation of real_CoefB array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q15 format + round(pBTable[i] * pow(2, 15)) +*/ +const q15_t __ALIGNED(4) realCoefBQ15[8192] = { + (q15_t)0x4000, (q15_t)0x4000, (q15_t)0x400d, (q15_t)0x4000, (q15_t)0x4019, (q15_t)0x4000, (q15_t)0x4026, (q15_t)0x4000, + (q15_t)0x4032, (q15_t)0x4000, (q15_t)0x403f, (q15_t)0x4000, (q15_t)0x404b, (q15_t)0x4000, (q15_t)0x4058, (q15_t)0x4000, + (q15_t)0x4065, (q15_t)0x4000, (q15_t)0x4071, (q15_t)0x4000, (q15_t)0x407e, (q15_t)0x4000, (q15_t)0x408a, (q15_t)0x3fff, + (q15_t)0x4097, (q15_t)0x3fff, (q15_t)0x40a3, (q15_t)0x3fff, (q15_t)0x40b0, (q15_t)0x3fff, (q15_t)0x40bc, (q15_t)0x3fff, + (q15_t)0x40c9, (q15_t)0x3fff, (q15_t)0x40d6, (q15_t)0x3fff, (q15_t)0x40e2, (q15_t)0x3ffe, (q15_t)0x40ef, (q15_t)0x3ffe, + (q15_t)0x40fb, (q15_t)0x3ffe, (q15_t)0x4108, (q15_t)0x3ffe, (q15_t)0x4114, (q15_t)0x3ffe, (q15_t)0x4121, (q15_t)0x3ffd, + (q15_t)0x412e, (q15_t)0x3ffd, (q15_t)0x413a, (q15_t)0x3ffd, (q15_t)0x4147, (q15_t)0x3ffd, (q15_t)0x4153, (q15_t)0x3ffc, + (q15_t)0x4160, (q15_t)0x3ffc, (q15_t)0x416c, (q15_t)0x3ffc, (q15_t)0x4179, (q15_t)0x3ffc, (q15_t)0x4186, (q15_t)0x3ffb, + (q15_t)0x4192, (q15_t)0x3ffb, (q15_t)0x419f, (q15_t)0x3ffb, (q15_t)0x41ab, (q15_t)0x3ffa, (q15_t)0x41b8, (q15_t)0x3ffa, + (q15_t)0x41c4, (q15_t)0x3ffa, (q15_t)0x41d1, (q15_t)0x3ff9, (q15_t)0x41dd, (q15_t)0x3ff9, (q15_t)0x41ea, (q15_t)0x3ff9, + (q15_t)0x41f7, (q15_t)0x3ff8, (q15_t)0x4203, (q15_t)0x3ff8, (q15_t)0x4210, (q15_t)0x3ff7, (q15_t)0x421c, (q15_t)0x3ff7, + (q15_t)0x4229, (q15_t)0x3ff7, (q15_t)0x4235, (q15_t)0x3ff6, (q15_t)0x4242, (q15_t)0x3ff6, (q15_t)0x424e, (q15_t)0x3ff5, + (q15_t)0x425b, (q15_t)0x3ff5, (q15_t)0x4268, (q15_t)0x3ff4, (q15_t)0x4274, (q15_t)0x3ff4, (q15_t)0x4281, (q15_t)0x3ff3, + (q15_t)0x428d, (q15_t)0x3ff3, (q15_t)0x429a, (q15_t)0x3ff2, (q15_t)0x42a6, (q15_t)0x3ff2, (q15_t)0x42b3, (q15_t)0x3ff1, + (q15_t)0x42c0, (q15_t)0x3ff1, (q15_t)0x42cc, (q15_t)0x3ff0, (q15_t)0x42d9, (q15_t)0x3ff0, (q15_t)0x42e5, (q15_t)0x3fef, + (q15_t)0x42f2, (q15_t)0x3fef, (q15_t)0x42fe, (q15_t)0x3fee, (q15_t)0x430b, (q15_t)0x3fed, (q15_t)0x4317, (q15_t)0x3fed, + (q15_t)0x4324, (q15_t)0x3fec, (q15_t)0x4330, (q15_t)0x3fec, (q15_t)0x433d, (q15_t)0x3feb, (q15_t)0x434a, (q15_t)0x3fea, + (q15_t)0x4356, (q15_t)0x3fea, (q15_t)0x4363, (q15_t)0x3fe9, (q15_t)0x436f, (q15_t)0x3fe8, (q15_t)0x437c, (q15_t)0x3fe8, + (q15_t)0x4388, (q15_t)0x3fe7, (q15_t)0x4395, (q15_t)0x3fe6, (q15_t)0x43a1, (q15_t)0x3fe6, (q15_t)0x43ae, (q15_t)0x3fe5, + (q15_t)0x43bb, (q15_t)0x3fe4, (q15_t)0x43c7, (q15_t)0x3fe3, (q15_t)0x43d4, (q15_t)0x3fe3, (q15_t)0x43e0, (q15_t)0x3fe2, + (q15_t)0x43ed, (q15_t)0x3fe1, (q15_t)0x43f9, (q15_t)0x3fe0, (q15_t)0x4406, (q15_t)0x3fe0, (q15_t)0x4412, (q15_t)0x3fdf, + (q15_t)0x441f, (q15_t)0x3fde, (q15_t)0x442b, (q15_t)0x3fdd, (q15_t)0x4438, (q15_t)0x3fdc, (q15_t)0x4444, (q15_t)0x3fdc, + (q15_t)0x4451, (q15_t)0x3fdb, (q15_t)0x445e, (q15_t)0x3fda, (q15_t)0x446a, (q15_t)0x3fd9, (q15_t)0x4477, (q15_t)0x3fd8, + (q15_t)0x4483, (q15_t)0x3fd7, (q15_t)0x4490, (q15_t)0x3fd6, (q15_t)0x449c, (q15_t)0x3fd5, (q15_t)0x44a9, (q15_t)0x3fd5, + (q15_t)0x44b5, (q15_t)0x3fd4, (q15_t)0x44c2, (q15_t)0x3fd3, (q15_t)0x44ce, (q15_t)0x3fd2, (q15_t)0x44db, (q15_t)0x3fd1, + (q15_t)0x44e7, (q15_t)0x3fd0, (q15_t)0x44f4, (q15_t)0x3fcf, (q15_t)0x4500, (q15_t)0x3fce, (q15_t)0x450d, (q15_t)0x3fcd, + (q15_t)0x451a, (q15_t)0x3fcc, (q15_t)0x4526, (q15_t)0x3fcb, (q15_t)0x4533, (q15_t)0x3fca, (q15_t)0x453f, (q15_t)0x3fc9, + (q15_t)0x454c, (q15_t)0x3fc8, (q15_t)0x4558, (q15_t)0x3fc7, (q15_t)0x4565, (q15_t)0x3fc6, (q15_t)0x4571, (q15_t)0x3fc5, + (q15_t)0x457e, (q15_t)0x3fc4, (q15_t)0x458a, (q15_t)0x3fc3, (q15_t)0x4597, (q15_t)0x3fc1, (q15_t)0x45a3, (q15_t)0x3fc0, + (q15_t)0x45b0, (q15_t)0x3fbf, (q15_t)0x45bc, (q15_t)0x3fbe, (q15_t)0x45c9, (q15_t)0x3fbd, (q15_t)0x45d5, (q15_t)0x3fbc, + (q15_t)0x45e2, (q15_t)0x3fbb, (q15_t)0x45ee, (q15_t)0x3fb9, (q15_t)0x45fb, (q15_t)0x3fb8, (q15_t)0x4607, (q15_t)0x3fb7, + (q15_t)0x4614, (q15_t)0x3fb6, (q15_t)0x4620, (q15_t)0x3fb5, (q15_t)0x462d, (q15_t)0x3fb4, (q15_t)0x4639, (q15_t)0x3fb2, + (q15_t)0x4646, (q15_t)0x3fb1, (q15_t)0x4652, (q15_t)0x3fb0, (q15_t)0x465f, (q15_t)0x3faf, (q15_t)0x466b, (q15_t)0x3fad, + (q15_t)0x4678, (q15_t)0x3fac, (q15_t)0x4684, (q15_t)0x3fab, (q15_t)0x4691, (q15_t)0x3faa, (q15_t)0x469d, (q15_t)0x3fa8, + (q15_t)0x46aa, (q15_t)0x3fa7, (q15_t)0x46b6, (q15_t)0x3fa6, (q15_t)0x46c3, (q15_t)0x3fa4, (q15_t)0x46cf, (q15_t)0x3fa3, + (q15_t)0x46dc, (q15_t)0x3fa2, (q15_t)0x46e8, (q15_t)0x3fa0, (q15_t)0x46f5, (q15_t)0x3f9f, (q15_t)0x4701, (q15_t)0x3f9e, + (q15_t)0x470e, (q15_t)0x3f9c, (q15_t)0x471a, (q15_t)0x3f9b, (q15_t)0x4727, (q15_t)0x3f99, (q15_t)0x4733, (q15_t)0x3f98, + (q15_t)0x4740, (q15_t)0x3f97, (q15_t)0x474c, (q15_t)0x3f95, (q15_t)0x4759, (q15_t)0x3f94, (q15_t)0x4765, (q15_t)0x3f92, + (q15_t)0x4772, (q15_t)0x3f91, (q15_t)0x477e, (q15_t)0x3f8f, (q15_t)0x478b, (q15_t)0x3f8e, (q15_t)0x4797, (q15_t)0x3f8c, + (q15_t)0x47a4, (q15_t)0x3f8b, (q15_t)0x47b0, (q15_t)0x3f89, (q15_t)0x47bd, (q15_t)0x3f88, (q15_t)0x47c9, (q15_t)0x3f86, + (q15_t)0x47d6, (q15_t)0x3f85, (q15_t)0x47e2, (q15_t)0x3f83, (q15_t)0x47ef, (q15_t)0x3f82, (q15_t)0x47fb, (q15_t)0x3f80, + (q15_t)0x4807, (q15_t)0x3f7f, (q15_t)0x4814, (q15_t)0x3f7d, (q15_t)0x4820, (q15_t)0x3f7b, (q15_t)0x482d, (q15_t)0x3f7a, + (q15_t)0x4839, (q15_t)0x3f78, (q15_t)0x4846, (q15_t)0x3f77, (q15_t)0x4852, (q15_t)0x3f75, (q15_t)0x485f, (q15_t)0x3f73, + (q15_t)0x486b, (q15_t)0x3f72, (q15_t)0x4878, (q15_t)0x3f70, (q15_t)0x4884, (q15_t)0x3f6e, (q15_t)0x4891, (q15_t)0x3f6d, + (q15_t)0x489d, (q15_t)0x3f6b, (q15_t)0x48a9, (q15_t)0x3f69, (q15_t)0x48b6, (q15_t)0x3f68, (q15_t)0x48c2, (q15_t)0x3f66, + (q15_t)0x48cf, (q15_t)0x3f64, (q15_t)0x48db, (q15_t)0x3f62, (q15_t)0x48e8, (q15_t)0x3f61, (q15_t)0x48f4, (q15_t)0x3f5f, + (q15_t)0x4901, (q15_t)0x3f5d, (q15_t)0x490d, (q15_t)0x3f5b, (q15_t)0x4919, (q15_t)0x3f5a, (q15_t)0x4926, (q15_t)0x3f58, + (q15_t)0x4932, (q15_t)0x3f56, (q15_t)0x493f, (q15_t)0x3f54, (q15_t)0x494b, (q15_t)0x3f52, (q15_t)0x4958, (q15_t)0x3f51, + (q15_t)0x4964, (q15_t)0x3f4f, (q15_t)0x4970, (q15_t)0x3f4d, (q15_t)0x497d, (q15_t)0x3f4b, (q15_t)0x4989, (q15_t)0x3f49, + (q15_t)0x4996, (q15_t)0x3f47, (q15_t)0x49a2, (q15_t)0x3f45, (q15_t)0x49af, (q15_t)0x3f43, (q15_t)0x49bb, (q15_t)0x3f42, + (q15_t)0x49c7, (q15_t)0x3f40, (q15_t)0x49d4, (q15_t)0x3f3e, (q15_t)0x49e0, (q15_t)0x3f3c, (q15_t)0x49ed, (q15_t)0x3f3a, + (q15_t)0x49f9, (q15_t)0x3f38, (q15_t)0x4a06, (q15_t)0x3f36, (q15_t)0x4a12, (q15_t)0x3f34, (q15_t)0x4a1e, (q15_t)0x3f32, + (q15_t)0x4a2b, (q15_t)0x3f30, (q15_t)0x4a37, (q15_t)0x3f2e, (q15_t)0x4a44, (q15_t)0x3f2c, (q15_t)0x4a50, (q15_t)0x3f2a, + (q15_t)0x4a5c, (q15_t)0x3f28, (q15_t)0x4a69, (q15_t)0x3f26, (q15_t)0x4a75, (q15_t)0x3f24, (q15_t)0x4a82, (q15_t)0x3f22, + (q15_t)0x4a8e, (q15_t)0x3f20, (q15_t)0x4a9a, (q15_t)0x3f1e, (q15_t)0x4aa7, (q15_t)0x3f1c, (q15_t)0x4ab3, (q15_t)0x3f19, + (q15_t)0x4ac0, (q15_t)0x3f17, (q15_t)0x4acc, (q15_t)0x3f15, (q15_t)0x4ad8, (q15_t)0x3f13, (q15_t)0x4ae5, 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(q15_t)0x493f, (q15_t)0xc0ac, + (q15_t)0x4932, (q15_t)0xc0aa, (q15_t)0x4926, (q15_t)0xc0a8, (q15_t)0x4919, (q15_t)0xc0a6, (q15_t)0x490d, (q15_t)0xc0a5, + (q15_t)0x4901, (q15_t)0xc0a3, (q15_t)0x48f4, (q15_t)0xc0a1, (q15_t)0x48e8, (q15_t)0xc09f, (q15_t)0x48db, (q15_t)0xc09e, + (q15_t)0x48cf, (q15_t)0xc09c, (q15_t)0x48c2, (q15_t)0xc09a, (q15_t)0x48b6, (q15_t)0xc098, (q15_t)0x48a9, (q15_t)0xc097, + (q15_t)0x489d, (q15_t)0xc095, (q15_t)0x4891, (q15_t)0xc093, (q15_t)0x4884, (q15_t)0xc092, (q15_t)0x4878, (q15_t)0xc090, + (q15_t)0x486b, (q15_t)0xc08e, (q15_t)0x485f, (q15_t)0xc08d, (q15_t)0x4852, (q15_t)0xc08b, (q15_t)0x4846, (q15_t)0xc089, + (q15_t)0x4839, (q15_t)0xc088, (q15_t)0x482d, (q15_t)0xc086, (q15_t)0x4820, (q15_t)0xc085, (q15_t)0x4814, (q15_t)0xc083, + (q15_t)0x4807, (q15_t)0xc081, (q15_t)0x47fb, (q15_t)0xc080, (q15_t)0x47ef, (q15_t)0xc07e, (q15_t)0x47e2, (q15_t)0xc07d, + (q15_t)0x47d6, (q15_t)0xc07b, (q15_t)0x47c9, (q15_t)0xc07a, (q15_t)0x47bd, (q15_t)0xc078, (q15_t)0x47b0, (q15_t)0xc077, + (q15_t)0x47a4, (q15_t)0xc075, (q15_t)0x4797, (q15_t)0xc074, (q15_t)0x478b, (q15_t)0xc072, (q15_t)0x477e, (q15_t)0xc071, + (q15_t)0x4772, (q15_t)0xc06f, (q15_t)0x4765, (q15_t)0xc06e, (q15_t)0x4759, (q15_t)0xc06c, (q15_t)0x474c, (q15_t)0xc06b, + (q15_t)0x4740, (q15_t)0xc069, (q15_t)0x4733, (q15_t)0xc068, (q15_t)0x4727, (q15_t)0xc067, (q15_t)0x471a, (q15_t)0xc065, + (q15_t)0x470e, (q15_t)0xc064, (q15_t)0x4701, (q15_t)0xc062, (q15_t)0x46f5, (q15_t)0xc061, (q15_t)0x46e8, (q15_t)0xc060, + (q15_t)0x46dc, (q15_t)0xc05e, (q15_t)0x46cf, (q15_t)0xc05d, (q15_t)0x46c3, (q15_t)0xc05c, (q15_t)0x46b6, (q15_t)0xc05a, + (q15_t)0x46aa, (q15_t)0xc059, (q15_t)0x469d, (q15_t)0xc058, (q15_t)0x4691, (q15_t)0xc056, (q15_t)0x4684, (q15_t)0xc055, + (q15_t)0x4678, (q15_t)0xc054, (q15_t)0x466b, (q15_t)0xc053, (q15_t)0x465f, (q15_t)0xc051, (q15_t)0x4652, (q15_t)0xc050, + (q15_t)0x4646, (q15_t)0xc04f, (q15_t)0x4639, (q15_t)0xc04e, (q15_t)0x462d, (q15_t)0xc04c, (q15_t)0x4620, (q15_t)0xc04b, + (q15_t)0x4614, (q15_t)0xc04a, (q15_t)0x4607, (q15_t)0xc049, (q15_t)0x45fb, (q15_t)0xc048, (q15_t)0x45ee, (q15_t)0xc047, + (q15_t)0x45e2, (q15_t)0xc045, (q15_t)0x45d5, (q15_t)0xc044, (q15_t)0x45c9, (q15_t)0xc043, (q15_t)0x45bc, (q15_t)0xc042, + (q15_t)0x45b0, (q15_t)0xc041, (q15_t)0x45a3, (q15_t)0xc040, (q15_t)0x4597, (q15_t)0xc03f, (q15_t)0x458a, (q15_t)0xc03d, + (q15_t)0x457e, (q15_t)0xc03c, (q15_t)0x4571, (q15_t)0xc03b, (q15_t)0x4565, (q15_t)0xc03a, (q15_t)0x4558, (q15_t)0xc039, + (q15_t)0x454c, (q15_t)0xc038, (q15_t)0x453f, (q15_t)0xc037, (q15_t)0x4533, (q15_t)0xc036, (q15_t)0x4526, (q15_t)0xc035, + (q15_t)0x451a, (q15_t)0xc034, (q15_t)0x450d, (q15_t)0xc033, (q15_t)0x4500, (q15_t)0xc032, (q15_t)0x44f4, (q15_t)0xc031, + (q15_t)0x44e7, (q15_t)0xc030, (q15_t)0x44db, (q15_t)0xc02f, (q15_t)0x44ce, (q15_t)0xc02e, (q15_t)0x44c2, (q15_t)0xc02d, + (q15_t)0x44b5, (q15_t)0xc02c, (q15_t)0x44a9, (q15_t)0xc02b, (q15_t)0x449c, (q15_t)0xc02b, (q15_t)0x4490, (q15_t)0xc02a, + (q15_t)0x4483, (q15_t)0xc029, (q15_t)0x4477, (q15_t)0xc028, (q15_t)0x446a, (q15_t)0xc027, (q15_t)0x445e, (q15_t)0xc026, + (q15_t)0x4451, (q15_t)0xc025, (q15_t)0x4444, (q15_t)0xc024, (q15_t)0x4438, (q15_t)0xc024, (q15_t)0x442b, (q15_t)0xc023, + (q15_t)0x441f, (q15_t)0xc022, (q15_t)0x4412, (q15_t)0xc021, (q15_t)0x4406, (q15_t)0xc020, (q15_t)0x43f9, (q15_t)0xc020, + (q15_t)0x43ed, (q15_t)0xc01f, (q15_t)0x43e0, (q15_t)0xc01e, (q15_t)0x43d4, (q15_t)0xc01d, (q15_t)0x43c7, (q15_t)0xc01d, + (q15_t)0x43bb, (q15_t)0xc01c, (q15_t)0x43ae, (q15_t)0xc01b, (q15_t)0x43a1, (q15_t)0xc01a, (q15_t)0x4395, (q15_t)0xc01a, + (q15_t)0x4388, (q15_t)0xc019, (q15_t)0x437c, (q15_t)0xc018, (q15_t)0x436f, (q15_t)0xc018, (q15_t)0x4363, (q15_t)0xc017, + (q15_t)0x4356, (q15_t)0xc016, (q15_t)0x434a, (q15_t)0xc016, (q15_t)0x433d, (q15_t)0xc015, (q15_t)0x4330, (q15_t)0xc014, + (q15_t)0x4324, (q15_t)0xc014, (q15_t)0x4317, (q15_t)0xc013, (q15_t)0x430b, (q15_t)0xc013, (q15_t)0x42fe, (q15_t)0xc012, + (q15_t)0x42f2, (q15_t)0xc011, (q15_t)0x42e5, (q15_t)0xc011, (q15_t)0x42d9, (q15_t)0xc010, (q15_t)0x42cc, (q15_t)0xc010, + (q15_t)0x42c0, (q15_t)0xc00f, (q15_t)0x42b3, (q15_t)0xc00f, (q15_t)0x42a6, (q15_t)0xc00e, (q15_t)0x429a, (q15_t)0xc00e, + (q15_t)0x428d, (q15_t)0xc00d, (q15_t)0x4281, (q15_t)0xc00d, (q15_t)0x4274, (q15_t)0xc00c, (q15_t)0x4268, (q15_t)0xc00c, + (q15_t)0x425b, (q15_t)0xc00b, (q15_t)0x424e, (q15_t)0xc00b, (q15_t)0x4242, (q15_t)0xc00a, (q15_t)0x4235, (q15_t)0xc00a, + (q15_t)0x4229, (q15_t)0xc009, (q15_t)0x421c, (q15_t)0xc009, (q15_t)0x4210, (q15_t)0xc009, (q15_t)0x4203, (q15_t)0xc008, + (q15_t)0x41f7, (q15_t)0xc008, (q15_t)0x41ea, (q15_t)0xc007, (q15_t)0x41dd, (q15_t)0xc007, (q15_t)0x41d1, (q15_t)0xc007, + (q15_t)0x41c4, (q15_t)0xc006, (q15_t)0x41b8, (q15_t)0xc006, (q15_t)0x41ab, (q15_t)0xc006, (q15_t)0x419f, (q15_t)0xc005, + (q15_t)0x4192, (q15_t)0xc005, (q15_t)0x4186, (q15_t)0xc005, (q15_t)0x4179, (q15_t)0xc004, (q15_t)0x416c, (q15_t)0xc004, + (q15_t)0x4160, (q15_t)0xc004, (q15_t)0x4153, (q15_t)0xc004, (q15_t)0x4147, (q15_t)0xc003, (q15_t)0x413a, (q15_t)0xc003, + (q15_t)0x412e, (q15_t)0xc003, (q15_t)0x4121, (q15_t)0xc003, (q15_t)0x4114, (q15_t)0xc002, (q15_t)0x4108, (q15_t)0xc002, + (q15_t)0x40fb, (q15_t)0xc002, (q15_t)0x40ef, (q15_t)0xc002, (q15_t)0x40e2, (q15_t)0xc002, (q15_t)0x40d6, (q15_t)0xc001, + (q15_t)0x40c9, (q15_t)0xc001, (q15_t)0x40bc, (q15_t)0xc001, (q15_t)0x40b0, (q15_t)0xc001, (q15_t)0x40a3, (q15_t)0xc001, + (q15_t)0x4097, (q15_t)0xc001, (q15_t)0x408a, (q15_t)0xc001, (q15_t)0x407e, (q15_t)0xc000, (q15_t)0x4071, (q15_t)0xc000, + (q15_t)0x4065, (q15_t)0xc000, (q15_t)0x4058, (q15_t)0xc000, (q15_t)0x404b, (q15_t)0xc000, (q15_t)0x403f, (q15_t)0xc000, + (q15_t)0x4032, (q15_t)0xc000, (q15_t)0x4026, (q15_t)0xc000, (q15_t)0x4019, (q15_t)0xc000, (q15_t)0x400d, (q15_t)0xc000, +}; + +#endif +/** + @} end of RealFFT_Table group + */ + +/** + @ingroup DCT4_IDCT4 + */ + +/** + @addtogroup DCT4_IDCT4_Table DCT Type IV Tables + @{ + */ + +/** + @brief Weights Table + */ + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for(i = 0; i< N; i++)
+  {
+    weights[(2*i)]   =  cos (i*c);
+    weights[(2*i)+1] = -sin (i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + + +/** + @par + cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + @par + 
 for(i = 0; i< N; i++)
+  {
+     cos_factors[i]= 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) +*/ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + const float32_t Weights_128[256] = { + 1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f, -0.012271538285719925f, + 0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f, -0.036807222941358832f, + 0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f, -0.061320736302208578f, + 0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f, -0.085797312344439894f, + 0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f, -0.110222207293883060f, + 0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f, -0.134580708507126170f, + 0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f, -0.158858143333861450f, + 0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f, -0.183039887955140950f, + 0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f, -0.207111376192218560f, + 0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f, -0.231058108280671110f, + 0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f, -0.254865659604514570f, + 0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f, -0.278519689385053060f, + 0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f, -0.302005949319228080f, + 0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f, -0.325310292162262930f, + 0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f, -0.348418680249434560f, + 0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f, -0.371317193951837540f, + 0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f, -0.393992040061048100f, + 0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f, -0.416429560097637150f, + 0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f, -0.438616238538527660f, + 0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f, -0.460538710958240010f, + 0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f, -0.482183772079122720f, + 0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f, -0.503538383725717580f, + 0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f, -0.524589682678468950f, + 0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f, -0.545324988422046460f, + 0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f, -0.565731810783613120f, + 0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f, -0.585797857456438860f, + 0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f, -0.605511041404325550f, + 0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f, -0.624859488142386340f, + 0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f, -0.643831542889791390f, + 0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f, -0.662415777590171780f, + 0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f, -0.680600997795453020f, + 0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f, -0.698376249408972920f, + 0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f, -0.715730825283818590f, + 0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f, -0.732654271672412820f, + 0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f, -0.749136394523459260f, + 0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f, -0.765167265622458960f, + 0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f, -0.780737228572094380f, + 0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f, -0.795836904608883460f, + 0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f, 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0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f, -0.937339011912574960f, + 0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f, -0.945607325380521280f, + 0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f, -0.953306040354193750f, + 0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f, -0.960430519415565790f, + 0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f, -0.966976471044852070f, + 0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f, -0.972939952205560070f, + 0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f, -0.978317370719627650f, + 0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f, -0.983105487431216290f, + 0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f, -0.987301418157858430f, + 0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f, -0.990902635427780010f, + 0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f, -0.993906970002356060f, + 0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f, -0.996312612182778000f, + 0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f, -0.998118112900149180f, + 0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f, -0.999322384588349540f, + 0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f, -0.999924701839144500f +}; + + const float32_t cos_factors_128[128] = { + 0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f, + 0.999077727752645360f, + 0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f, + 0.995767414467659820f, + 0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f, + 0.990058210262297120f, + 0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f, + 0.981963869109555240f, + 0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f, + 0.971503890986251780f, + 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0.000191747598192208f +}; + #endif + +/** + @brief Weights Table + */ + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for(i = 0; i< N; i++)
+  { 
+    weights[(2*i)]   =  cos(i*c);
+    weights[(2*i)+1] = -sin(i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + Converted the output to q15 format by multiplying with 2^31 and saturated if required. + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + +/** + @par + cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    cos_factors[i] = 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) + @par + Then converted to q15 format by multiplying with 2^31 and saturated if required. +*/ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + const q15_t __ALIGNED(4) WeightsQ15_128[256] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7fe9, (q15_t)0xfb4a, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f87, (q15_t)0xf505, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7ed5, (q15_t)0xeec7, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7dd6, (q15_t)0xe893, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7c89, (q15_t)0xe26d, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7aef, (q15_t)0xdc5a, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7909, (q15_t)0xd65d, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x76d9, (q15_t)0xd079, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x745f, (q15_t)0xcab3, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x719e, (q15_t)0xc50e, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6e96, (q15_t)0xbf8d, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6b4a, (q15_t)0xba33, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x67bd, (q15_t)0xb505, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x63ef, (q15_t)0xb005, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x5fe3, (q15_t)0xab36, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5b9d, (q15_t)0xa69c, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x571d, (q15_t)0xa239, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5269, (q15_t)0x9e0f, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4d81, (q15_t)0x9a23, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x4869, (q15_t)0x9674, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4325, (q15_t)0x9307, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3db8, (q15_t)0x8fdd, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3824, (q15_t)0x8cf9, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x326e, (q15_t)0x8a5b, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2c98, (q15_t)0x8806, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x26a8, (q15_t)0x85fb, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x209f, (q15_t)0x843b, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1a82, (q15_t)0x82c7, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x1455, (q15_t)0x81a1, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1139, (q15_t)0x812b, (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xe1b, (q15_t)0x80c8, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xafb, (q15_t)0x8079, (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x7d9, (q15_t)0x803e, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x324, (q15_t)0x800a, (q15_t)0x192, (q15_t)0x8003 +}; + const q15_t __ALIGNED(4) cos_factorsQ15_128[128] = { + (q15_t)0x7fff, (q15_t)0x7ffa, (q15_t)0x7ff0, (q15_t)0x7fe1, (q15_t)0x7fce, (q15_t)0x7fb5, (q15_t)0x7f97, (q15_t)0x7f75, + (q15_t)0x7f4d, (q15_t)0x7f21, (q15_t)0x7ef0, (q15_t)0x7eba, (q15_t)0x7e7f, (q15_t)0x7e3f, (q15_t)0x7dfa, (q15_t)0x7db0, + (q15_t)0x7d62, (q15_t)0x7d0f, (q15_t)0x7cb7, (q15_t)0x7c5a, (q15_t)0x7bf8, (q15_t)0x7b92, (q15_t)0x7b26, (q15_t)0x7ab6, + (q15_t)0x7a42, (q15_t)0x79c8, (q15_t)0x794a, (q15_t)0x78c7, (q15_t)0x7840, (q15_t)0x77b4, (q15_t)0x7723, (q15_t)0x768e, + (q15_t)0x75f4, (q15_t)0x7555, (q15_t)0x74b2, (q15_t)0x740b, (q15_t)0x735f, (q15_t)0x72af, (q15_t)0x71fa, (q15_t)0x7141, + (q15_t)0x7083, (q15_t)0x6fc1, (q15_t)0x6efb, (q15_t)0x6e30, (q15_t)0x6d62, (q15_t)0x6c8f, (q15_t)0x6bb8, (q15_t)0x6adc, + (q15_t)0x69fd, (q15_t)0x6919, (q15_t)0x6832, (q15_t)0x6746, (q15_t)0x6657, (q15_t)0x6563, (q15_t)0x646c, (q15_t)0x6371, + (q15_t)0x6271, (q15_t)0x616f, (q15_t)0x6068, (q15_t)0x5f5e, (q15_t)0x5e50, (q15_t)0x5d3e, (q15_t)0x5c29, (q15_t)0x5b10, + (q15_t)0x59f3, (q15_t)0x58d4, (q15_t)0x57b0, (q15_t)0x568a, (q15_t)0x5560, (q15_t)0x5433, (q15_t)0x5302, (q15_t)0x51ce, + (q15_t)0x5097, (q15_t)0x4f5e, (q15_t)0x4e21, (q15_t)0x4ce1, (q15_t)0x4b9e, (q15_t)0x4a58, (q15_t)0x490f, (q15_t)0x47c3, + (q15_t)0x4675, (q15_t)0x4524, (q15_t)0x43d0, (q15_t)0x427a, (q15_t)0x4121, (q15_t)0x3fc5, (q15_t)0x3e68, (q15_t)0x3d07, + (q15_t)0x3ba5, (q15_t)0x3a40, (q15_t)0x38d8, (q15_t)0x376f, (q15_t)0x3604, (q15_t)0x3496, (q15_t)0x3326, (q15_t)0x31b5, + (q15_t)0x3041, (q15_t)0x2ecc, (q15_t)0x2d55, (q15_t)0x2bdc, (q15_t)0x2a61, (q15_t)0x28e5, (q15_t)0x2767, (q15_t)0x25e8, + (q15_t)0x2467, (q15_t)0x22e5, (q15_t)0x2161, (q15_t)0x1fdc, (q15_t)0x1e56, (q15_t)0x1ccf, (q15_t)0x1b47, (q15_t)0x19bd, + (q15_t)0x1833, (q15_t)0x16a8, (q15_t)0x151b, (q15_t)0x138e, (q15_t)0x1201, (q15_t)0x1072, (q15_t)0xee3, (q15_t)0xd53, + (q15_t)0xbc3, (q15_t)0xa33, (q15_t)0x8a2, (q15_t)0x710, (q15_t)0x57f, (q15_t)0x3ed, (q15_t)0x25b, (q15_t)0xc9 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + const q15_t __ALIGNED(4) WeightsQ15_512[1024] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7ffe, (q15_t)0xfed3, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff8, (q15_t)0xfd41, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fed, (q15_t)0xfbaf, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fdd, (q15_t)0xfa1d, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fc8, (q15_t)0xf88b, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fae, (q15_t)0xf6fa, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f8f, (q15_t)0xf569, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f6b, (q15_t)0xf3d9, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f43, (q15_t)0xf249, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f15, (q15_t)0xf0b9, + (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7ee3, (q15_t)0xef2a, + (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eab, (q15_t)0xed9c, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e6f, (q15_t)0xec0e, + (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e2e, (q15_t)0xea81, + (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7de8, (q15_t)0xe8f6, + (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7d9d, (q15_t)0xe76a, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d4e, (q15_t)0xe5e0, + (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7cf9, (q15_t)0xe457, + (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7ca0, (q15_t)0xe2cf, + (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c42, (q15_t)0xe148, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bdf, (q15_t)0xdfc2, + (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b77, (q15_t)0xde3e, + (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b0b, (q15_t)0xdcbb, + (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7a9a, (q15_t)0xdb39, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a24, (q15_t)0xd9b8, + (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79a9, (q15_t)0xd839, + (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x792a, (q15_t)0xd6bc, + (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78a6, (q15_t)0xd540, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x781d, (q15_t)0xd3c6, + (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x7790, (q15_t)0xd24d, + (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x76fe, (q15_t)0xd0d7, + (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x7668, (q15_t)0xcf62, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75cc, (q15_t)0xcdef, + (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x752d, (q15_t)0xcc7e, + (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x7489, (q15_t)0xcb0e, + (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x73e0, (q15_t)0xc9a1, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x7333, (q15_t)0xc836, + (q15_t)0x7307, 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(q15_t)0x90d3, + (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e10, (q15_t)0x900e, + (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3caf, (q15_t)0x8f4d, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b4c, (q15_t)0x8e91, + (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x39e6, (q15_t)0x8dd9, + (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x387e, (q15_t)0x8d25, + (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3714, (q15_t)0x8c76, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35a8, (q15_t)0x8bcb, + (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x343a, (q15_t)0x8b25, + (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x32ca, (q15_t)0x8a83, + (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x3158, (q15_t)0x89e5, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x2fe4, (q15_t)0x894d, + (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2e6e, (q15_t)0x88b9, + (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2cf7, (q15_t)0x8829, + (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2b7d, (q15_t)0x879e, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a02, (q15_t)0x8718, + (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x2886, (q15_t)0x8696, + (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x2707, (q15_t)0x8619, + (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x2588, (q15_t)0x85a1, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x2407, (q15_t)0x852d, + (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x2284, (q15_t)0x84be, + (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x2100, (q15_t)0x8454, + (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1f7b, (q15_t)0x83ef, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1df5, (q15_t)0x838f, + (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1c6d, (q15_t)0x8333, + (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1ae4, (q15_t)0x82dc, + (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x195b, (q15_t)0x828a, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x17d0, (q15_t)0x823d, + (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x1645, (q15_t)0x81f4, + (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x14b8, (q15_t)0x81b1, + (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x132b, (q15_t)0x8172, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x119d, (q15_t)0x8138, + (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x100e, (q15_t)0x8103, + (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xe7f, (q15_t)0x80d3, + (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xcef, (q15_t)0x80a8, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xb5f, (q15_t)0x8082, + (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa33, (q15_t)0x8069, (q15_t)0x9ce, (q15_t)0x8061, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x83d, (q15_t)0x8044, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x775, (q15_t)0x8038, (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6ac, (q15_t)0x802d, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x51a, (q15_t)0x801b, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x451, (q15_t)0x8013, (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x388, (q15_t)0x800d, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x1f6, (q15_t)0x8004, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x12d, (q15_t)0x8002, (q15_t)0xc9, (q15_t)0x8001, (q15_t)0x64, (q15_t)0x8001 +}; + + const q15_t __ALIGNED(4) cos_factorsQ15_512[512] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ff9, (q15_t)0x7ff7, + (q15_t)0x7ff4, (q15_t)0x7ff2, (q15_t)0x7fee, (q15_t)0x7feb, (q15_t)0x7fe7, (q15_t)0x7fe3, (q15_t)0x7fdf, (q15_t)0x7fda, + (q15_t)0x7fd6, (q15_t)0x7fd0, (q15_t)0x7fcb, (q15_t)0x7fc5, (q15_t)0x7fbf, (q15_t)0x7fb8, (q15_t)0x7fb1, (q15_t)0x7faa, + (q15_t)0x7fa3, (q15_t)0x7f9b, (q15_t)0x7f93, (q15_t)0x7f8b, (q15_t)0x7f82, (q15_t)0x7f79, (q15_t)0x7f70, (q15_t)0x7f67, + (q15_t)0x7f5d, (q15_t)0x7f53, (q15_t)0x7f48, (q15_t)0x7f3d, (q15_t)0x7f32, (q15_t)0x7f27, (q15_t)0x7f1b, (q15_t)0x7f0f, + (q15_t)0x7f03, (q15_t)0x7ef6, (q15_t)0x7ee9, (q15_t)0x7edc, (q15_t)0x7ecf, (q15_t)0x7ec1, (q15_t)0x7eb3, (q15_t)0x7ea4, + (q15_t)0x7e95, (q15_t)0x7e86, (q15_t)0x7e77, (q15_t)0x7e67, (q15_t)0x7e57, (q15_t)0x7e47, (q15_t)0x7e37, (q15_t)0x7e26, + (q15_t)0x7e14, (q15_t)0x7e03, (q15_t)0x7df1, (q15_t)0x7ddf, (q15_t)0x7dcd, (q15_t)0x7dba, (q15_t)0x7da7, (q15_t)0x7d94, + (q15_t)0x7d80, (q15_t)0x7d6c, (q15_t)0x7d58, (q15_t)0x7d43, (q15_t)0x7d2f, (q15_t)0x7d19, (q15_t)0x7d04, (q15_t)0x7cee, + (q15_t)0x7cd8, (q15_t)0x7cc2, (q15_t)0x7cab, (q15_t)0x7c94, (q15_t)0x7c7d, (q15_t)0x7c66, (q15_t)0x7c4e, (q15_t)0x7c36, + (q15_t)0x7c1d, (q15_t)0x7c05, (q15_t)0x7beb, (q15_t)0x7bd2, (q15_t)0x7bb9, (q15_t)0x7b9f, (q15_t)0x7b84, (q15_t)0x7b6a, + (q15_t)0x7b4f, (q15_t)0x7b34, (q15_t)0x7b19, (q15_t)0x7afd, (q15_t)0x7ae1, (q15_t)0x7ac5, (q15_t)0x7aa8, (q15_t)0x7a8b, + (q15_t)0x7a6e, (q15_t)0x7a50, (q15_t)0x7a33, (q15_t)0x7a15, (q15_t)0x79f6, (q15_t)0x79d8, (q15_t)0x79b9, (q15_t)0x7999, + (q15_t)0x797a, (q15_t)0x795a, (q15_t)0x793a, (q15_t)0x7919, (q15_t)0x78f9, (q15_t)0x78d8, (q15_t)0x78b6, (q15_t)0x7895, + (q15_t)0x7873, (q15_t)0x7851, (q15_t)0x782e, (q15_t)0x780c, (q15_t)0x77e9, (q15_t)0x77c5, (q15_t)0x77a2, (q15_t)0x777e, + (q15_t)0x775a, (q15_t)0x7735, (q15_t)0x7710, (q15_t)0x76eb, (q15_t)0x76c6, (q15_t)0x76a0, (q15_t)0x767b, (q15_t)0x7654, + (q15_t)0x762e, (q15_t)0x7607, (q15_t)0x75e0, (q15_t)0x75b9, (q15_t)0x7591, (q15_t)0x7569, (q15_t)0x7541, (q15_t)0x7519, + (q15_t)0x74f0, (q15_t)0x74c7, (q15_t)0x749e, (q15_t)0x7474, (q15_t)0x744a, (q15_t)0x7420, (q15_t)0x73f6, (q15_t)0x73cb, + (q15_t)0x73a0, (q15_t)0x7375, (q15_t)0x7349, (q15_t)0x731d, (q15_t)0x72f1, (q15_t)0x72c5, (q15_t)0x7298, (q15_t)0x726b, + (q15_t)0x723e, (q15_t)0x7211, (q15_t)0x71e3, (q15_t)0x71b5, (q15_t)0x7186, (q15_t)0x7158, (q15_t)0x7129, (q15_t)0x70fa, + (q15_t)0x70cb, (q15_t)0x709b, (q15_t)0x706b, (q15_t)0x703b, (q15_t)0x700a, (q15_t)0x6fda, (q15_t)0x6fa9, (q15_t)0x6f77, + (q15_t)0x6f46, (q15_t)0x6f14, (q15_t)0x6ee2, (q15_t)0x6eaf, (q15_t)0x6e7d, (q15_t)0x6e4a, (q15_t)0x6e17, (q15_t)0x6de3, + (q15_t)0x6db0, (q15_t)0x6d7c, (q15_t)0x6d48, (q15_t)0x6d13, (q15_t)0x6cde, (q15_t)0x6ca9, (q15_t)0x6c74, (q15_t)0x6c3f, + (q15_t)0x6c09, (q15_t)0x6bd3, (q15_t)0x6b9c, (q15_t)0x6b66, (q15_t)0x6b2f, (q15_t)0x6af8, (q15_t)0x6ac1, (q15_t)0x6a89, + (q15_t)0x6a51, (q15_t)0x6a19, (q15_t)0x69e1, (q15_t)0x69a8, (q15_t)0x696f, (q15_t)0x6936, (q15_t)0x68fd, (q15_t)0x68c3, + (q15_t)0x6889, (q15_t)0x684f, (q15_t)0x6815, (q15_t)0x67da, (q15_t)0x679f, (q15_t)0x6764, (q15_t)0x6729, (q15_t)0x66ed, + (q15_t)0x66b1, (q15_t)0x6675, (q15_t)0x6639, (q15_t)0x65fc, (q15_t)0x65bf, (q15_t)0x6582, (q15_t)0x6545, (q15_t)0x6507, + (q15_t)0x64c9, (q15_t)0x648b, (q15_t)0x644d, (q15_t)0x640e, (q15_t)0x63cf, (q15_t)0x6390, (q15_t)0x6351, (q15_t)0x6311, + (q15_t)0x62d2, (q15_t)0x6292, (q15_t)0x6251, (q15_t)0x6211, (q15_t)0x61d0, (q15_t)0x618f, (q15_t)0x614e, (q15_t)0x610d, + (q15_t)0x60cb, (q15_t)0x6089, (q15_t)0x6047, (q15_t)0x6004, (q15_t)0x5fc2, (q15_t)0x5f7f, (q15_t)0x5f3c, (q15_t)0x5ef9, + (q15_t)0x5eb5, (q15_t)0x5e71, (q15_t)0x5e2d, (q15_t)0x5de9, (q15_t)0x5da5, (q15_t)0x5d60, (q15_t)0x5d1b, (q15_t)0x5cd6, + (q15_t)0x5c91, (q15_t)0x5c4b, (q15_t)0x5c06, (q15_t)0x5bc0, (q15_t)0x5b79, (q15_t)0x5b33, (q15_t)0x5aec, (q15_t)0x5aa5, + (q15_t)0x5a5e, (q15_t)0x5a17, (q15_t)0x59d0, (q15_t)0x5988, (q15_t)0x5940, (q15_t)0x58f8, (q15_t)0x58af, (q15_t)0x5867, + (q15_t)0x581e, (q15_t)0x57d5, (q15_t)0x578c, (q15_t)0x5742, (q15_t)0x56f9, (q15_t)0x56af, (q15_t)0x5665, (q15_t)0x561a, + (q15_t)0x55d0, (q15_t)0x5585, (q15_t)0x553a, (q15_t)0x54ef, (q15_t)0x54a4, (q15_t)0x5458, (q15_t)0x540d, (q15_t)0x53c1, + (q15_t)0x5375, (q15_t)0x5328, (q15_t)0x52dc, (q15_t)0x528f, (q15_t)0x5242, (q15_t)0x51f5, (q15_t)0x51a8, (q15_t)0x515a, + (q15_t)0x510c, (q15_t)0x50bf, (q15_t)0x5070, (q15_t)0x5022, (q15_t)0x4fd4, (q15_t)0x4f85, (q15_t)0x4f36, (q15_t)0x4ee7, + (q15_t)0x4e98, (q15_t)0x4e48, (q15_t)0x4df9, (q15_t)0x4da9, (q15_t)0x4d59, (q15_t)0x4d09, (q15_t)0x4cb8, (q15_t)0x4c68, + (q15_t)0x4c17, (q15_t)0x4bc6, (q15_t)0x4b75, (q15_t)0x4b24, (q15_t)0x4ad2, (q15_t)0x4a81, (q15_t)0x4a2f, (q15_t)0x49dd, + (q15_t)0x498a, (q15_t)0x4938, (q15_t)0x48e6, (q15_t)0x4893, (q15_t)0x4840, (q15_t)0x47ed, (q15_t)0x479a, (q15_t)0x4746, + (q15_t)0x46f3, (q15_t)0x469f, (q15_t)0x464b, (q15_t)0x45f7, (q15_t)0x45a3, (q15_t)0x454e, (q15_t)0x44fa, (q15_t)0x44a5, + (q15_t)0x4450, (q15_t)0x43fb, (q15_t)0x43a5, (q15_t)0x4350, (q15_t)0x42fa, (q15_t)0x42a5, (q15_t)0x424f, (q15_t)0x41f9, + (q15_t)0x41a2, (q15_t)0x414c, (q15_t)0x40f6, (q15_t)0x409f, (q15_t)0x4048, (q15_t)0x3ff1, (q15_t)0x3f9a, (q15_t)0x3f43, + (q15_t)0x3eeb, (q15_t)0x3e93, (q15_t)0x3e3c, (q15_t)0x3de4, (q15_t)0x3d8c, (q15_t)0x3d33, (q15_t)0x3cdb, (q15_t)0x3c83, + (q15_t)0x3c2a, (q15_t)0x3bd1, (q15_t)0x3b78, (q15_t)0x3b1f, (q15_t)0x3ac6, (q15_t)0x3a6c, (q15_t)0x3a13, (q15_t)0x39b9, + (q15_t)0x395f, (q15_t)0x3906, (q15_t)0x38ab, (q15_t)0x3851, (q15_t)0x37f7, (q15_t)0x379c, (q15_t)0x3742, (q15_t)0x36e7, + (q15_t)0x368c, (q15_t)0x3631, (q15_t)0x35d6, (q15_t)0x357b, (q15_t)0x351f, (q15_t)0x34c4, (q15_t)0x3468, (q15_t)0x340c, + (q15_t)0x33b0, (q15_t)0x3354, (q15_t)0x32f8, (q15_t)0x329c, (q15_t)0x3240, (q15_t)0x31e3, (q15_t)0x3186, (q15_t)0x312a, + (q15_t)0x30cd, (q15_t)0x3070, (q15_t)0x3013, (q15_t)0x2fb5, (q15_t)0x2f58, (q15_t)0x2efb, (q15_t)0x2e9d, (q15_t)0x2e3f, + (q15_t)0x2de2, (q15_t)0x2d84, (q15_t)0x2d26, (q15_t)0x2cc8, (q15_t)0x2c69, (q15_t)0x2c0b, (q15_t)0x2bad, (q15_t)0x2b4e, + (q15_t)0x2aef, (q15_t)0x2a91, (q15_t)0x2a32, (q15_t)0x29d3, (q15_t)0x2974, (q15_t)0x2915, (q15_t)0x28b5, (q15_t)0x2856, + (q15_t)0x27f6, (q15_t)0x2797, (q15_t)0x2737, (q15_t)0x26d8, (q15_t)0x2678, (q15_t)0x2618, (q15_t)0x25b8, (q15_t)0x2558, + (q15_t)0x24f7, (q15_t)0x2497, (q15_t)0x2437, (q15_t)0x23d6, (q15_t)0x2376, (q15_t)0x2315, (q15_t)0x22b4, (q15_t)0x2254, + (q15_t)0x21f3, (q15_t)0x2192, (q15_t)0x2131, (q15_t)0x20d0, (q15_t)0x206e, (q15_t)0x200d, (q15_t)0x1fac, (q15_t)0x1f4a, + (q15_t)0x1ee9, (q15_t)0x1e87, (q15_t)0x1e25, (q15_t)0x1dc4, (q15_t)0x1d62, (q15_t)0x1d00, (q15_t)0x1c9e, (q15_t)0x1c3c, + (q15_t)0x1bda, (q15_t)0x1b78, (q15_t)0x1b16, (q15_t)0x1ab3, (q15_t)0x1a51, (q15_t)0x19ef, (q15_t)0x198c, (q15_t)0x192a, + (q15_t)0x18c7, (q15_t)0x1864, (q15_t)0x1802, (q15_t)0x179f, (q15_t)0x173c, (q15_t)0x16d9, (q15_t)0x1676, (q15_t)0x1613, + (q15_t)0x15b0, (q15_t)0x154d, (q15_t)0x14ea, (q15_t)0x1487, (q15_t)0x1423, (q15_t)0x13c0, (q15_t)0x135d, (q15_t)0x12f9, + (q15_t)0x1296, (q15_t)0x1232, (q15_t)0x11cf, (q15_t)0x116b, (q15_t)0x1108, (q15_t)0x10a4, (q15_t)0x1040, (q15_t)0xfdd, + (q15_t)0xf79, (q15_t)0xf15, (q15_t)0xeb1, (q15_t)0xe4d, (q15_t)0xde9, (q15_t)0xd85, (q15_t)0xd21, (q15_t)0xcbd, + (q15_t)0xc59, (q15_t)0xbf5, (q15_t)0xb91, (q15_t)0xb2d, (q15_t)0xac9, (q15_t)0xa65, (q15_t)0xa00, (q15_t)0x99c, + (q15_t)0x938, (q15_t)0x8d4, (q15_t)0x86f, (q15_t)0x80b, (q15_t)0x7a7, (q15_t)0x742, (q15_t)0x6de, (q15_t)0x67a, + (q15_t)0x615, (q15_t)0x5b1, (q15_t)0x54c, (q15_t)0x4e8, (q15_t)0x483, (q15_t)0x41f, (q15_t)0x3ba, (q15_t)0x356, + (q15_t)0x2f1, (q15_t)0x28d, (q15_t)0x228, (q15_t)0x1c4, (q15_t)0x15f, (q15_t)0xfb, (q15_t)0x96, (q15_t)0x32 +}; + + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + const q15_t __ALIGNED(4) WeightsQ15_2048[4096] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffb5, + (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff51, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeec, + (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffd, (q15_t)0xfe88, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe23, + (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffa, (q15_t)0xfdbe, + (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff8, (q15_t)0xfd5a, + (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff6, (q15_t)0xfcf5, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfc91, + (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc2c, + (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbc8, + (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7fea, (q15_t)0xfb64, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe6, (q15_t)0xfaff, + (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe2, (q15_t)0xfa9b, + (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fde, (q15_t)0xfa36, + (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fd9, (q15_t)0xf9d2, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd4, (q15_t)0xf96d, + (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fcf, (q15_t)0xf909, + (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fc9, (q15_t)0xf8a5, + (q15_t)0x7fc8, (q15_t)0xf88b, (q15_t)0x7fc6, (q15_t)0xf872, (q15_t)0x7fc5, (q15_t)0xf859, (q15_t)0x7fc3, (q15_t)0xf840, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fc0, (q15_t)0xf80e, (q15_t)0x7fbf, (q15_t)0xf7f5, (q15_t)0x7fbd, (q15_t)0xf7dc, + (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fba, (q15_t)0xf7aa, (q15_t)0x7fb8, (q15_t)0xf791, (q15_t)0x7fb7, (q15_t)0xf778, + (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fb3, (q15_t)0xf745, (q15_t)0x7fb1, (q15_t)0xf72c, (q15_t)0x7fb0, (q15_t)0xf713, + (q15_t)0x7fae, (q15_t)0xf6fa, (q15_t)0x7fac, (q15_t)0xf6e1, (q15_t)0x7faa, (q15_t)0xf6c8, (q15_t)0x7fa9, (q15_t)0xf6af, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7fa5, (q15_t)0xf67d, (q15_t)0x7fa3, (q15_t)0xf664, (q15_t)0x7fa1, (q15_t)0xf64b, + (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f9d, (q15_t)0xf619, (q15_t)0x7f9b, (q15_t)0xf600, (q15_t)0x7f99, (q15_t)0xf5e7, + (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f95, (q15_t)0xf5b4, (q15_t)0x7f93, (q15_t)0xf59b, (q15_t)0x7f91, (q15_t)0xf582, + (q15_t)0x7f8f, (q15_t)0xf569, (q15_t)0x7f8d, (q15_t)0xf550, (q15_t)0x7f8b, (q15_t)0xf537, (q15_t)0x7f89, (q15_t)0xf51e, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f85, (q15_t)0xf4ec, (q15_t)0x7f82, (q15_t)0xf4d3, (q15_t)0x7f80, (q15_t)0xf4ba, + (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f7c, (q15_t)0xf488, (q15_t)0x7f79, (q15_t)0xf46f, (q15_t)0x7f77, (q15_t)0xf456, + (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f72, (q15_t)0xf424, (q15_t)0x7f70, (q15_t)0xf40b, (q15_t)0x7f6e, (q15_t)0xf3f2, + (q15_t)0x7f6b, (q15_t)0xf3d9, (q15_t)0x7f69, (q15_t)0xf3c0, (q15_t)0x7f67, (q15_t)0xf3a7, (q15_t)0x7f64, (q15_t)0xf38e, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f5f, (q15_t)0xf35c, (q15_t)0x7f5d, (q15_t)0xf343, (q15_t)0x7f5a, (q15_t)0xf32a, + (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f55, (q15_t)0xf2f8, (q15_t)0x7f53, (q15_t)0xf2df, (q15_t)0x7f50, (q15_t)0xf2c6, + (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f4b, (q15_t)0xf294, (q15_t)0x7f48, (q15_t)0xf27b, (q15_t)0x7f45, (q15_t)0xf262, + (q15_t)0x7f43, (q15_t)0xf249, (q15_t)0x7f40, (q15_t)0xf230, (q15_t)0x7f3d, (q15_t)0xf217, (q15_t)0x7f3b, (q15_t)0xf1fe, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f35, (q15_t)0xf1cc, (q15_t)0x7f32, (q15_t)0xf1b3, (q15_t)0x7f2f, (q15_t)0xf19a, + (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f2a, (q15_t)0xf168, (q15_t)0x7f27, (q15_t)0xf14f, (q15_t)0x7f24, (q15_t)0xf136, + (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f1e, (q15_t)0xf104, (q15_t)0x7f1b, (q15_t)0xf0eb, (q15_t)0x7f18, (q15_t)0xf0d2, + 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(q15_t)0x8067, (q15_t)0xa00, (q15_t)0x8065, (q15_t)0x9e7, (q15_t)0x8063, + (q15_t)0x9ce, (q15_t)0x8061, (q15_t)0x9b5, (q15_t)0x805f, (q15_t)0x99c, (q15_t)0x805d, (q15_t)0x983, (q15_t)0x805b, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x951, (q15_t)0x8057, (q15_t)0x938, (q15_t)0x8056, (q15_t)0x91f, (q15_t)0x8054, + (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8ed, (q15_t)0x8050, (q15_t)0x8d4, (q15_t)0x804f, (q15_t)0x8bb, (q15_t)0x804d, + (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x888, (q15_t)0x8049, (q15_t)0x86f, (q15_t)0x8048, (q15_t)0x856, (q15_t)0x8046, + (q15_t)0x83d, (q15_t)0x8044, (q15_t)0x824, (q15_t)0x8043, (q15_t)0x80b, (q15_t)0x8041, (q15_t)0x7f2, (q15_t)0x8040, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x7c0, (q15_t)0x803d, (q15_t)0x7a7, (q15_t)0x803b, (q15_t)0x78e, (q15_t)0x803a, + (q15_t)0x775, (q15_t)0x8038, (q15_t)0x75b, (q15_t)0x8037, (q15_t)0x742, (q15_t)0x8035, (q15_t)0x729, (q15_t)0x8034, + (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6f7, (q15_t)0x8031, (q15_t)0x6de, (q15_t)0x8030, (q15_t)0x6c5, (q15_t)0x802e, + (q15_t)0x6ac, (q15_t)0x802d, (q15_t)0x693, (q15_t)0x802c, (q15_t)0x67a, (q15_t)0x802a, (q15_t)0x660, (q15_t)0x8029, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x62e, (q15_t)0x8027, (q15_t)0x615, (q15_t)0x8026, (q15_t)0x5fc, (q15_t)0x8024, + (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x5ca, (q15_t)0x8022, (q15_t)0x5b1, (q15_t)0x8021, (q15_t)0x598, (q15_t)0x8020, + (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x565, (q15_t)0x801e, (q15_t)0x54c, (q15_t)0x801d, (q15_t)0x533, (q15_t)0x801c, + (q15_t)0x51a, (q15_t)0x801b, (q15_t)0x501, (q15_t)0x801a, (q15_t)0x4e8, (q15_t)0x8019, (q15_t)0x4cf, (q15_t)0x8018, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x49c, (q15_t)0x8016, (q15_t)0x483, (q15_t)0x8015, (q15_t)0x46a, (q15_t)0x8014, + (q15_t)0x451, (q15_t)0x8013, (q15_t)0x438, (q15_t)0x8012, (q15_t)0x41f, (q15_t)0x8012, (q15_t)0x406, (q15_t)0x8011, + (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3a1, (q15_t)0x800e, + (q15_t)0x388, (q15_t)0x800d, (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x356, (q15_t)0x800c, (q15_t)0x33d, (q15_t)0x800b, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2d8, (q15_t)0x8009, + (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x274, (q15_t)0x8007, + (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x242, (q15_t)0x8006, (q15_t)0x228, (q15_t)0x8005, (q15_t)0x20f, (q15_t)0x8005, + (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1ab, (q15_t)0x8003, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x178, (q15_t)0x8003, (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x146, (q15_t)0x8002, + (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x114, (q15_t)0x8002, (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xe2, (q15_t)0x8001, + (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xaf, (q15_t)0x8001, (q15_t)0x96, (q15_t)0x8001, (q15_t)0x7d, (q15_t)0x8001, + (q15_t)0x64, (q15_t)0x8001, (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x32, (q15_t)0x8001, (q15_t)0x19, (q15_t)0x8001 +}; + const q15_t __ALIGNED(4) cos_factorsQ15_2048[2048] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, + (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, + (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, + (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff1, (q15_t)0x7ff0, + (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7fea, + (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe3, (q15_t)0x7fe2, + (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fda, (q15_t)0x7fd9, + (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd0, (q15_t)0x7fce, + (q15_t)0x7fcd, (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc4, (q15_t)0x7fc3, + (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fbe, (q15_t)0x7fbc, (q15_t)0x7fbb, (q15_t)0x7fb9, (q15_t)0x7fb7, (q15_t)0x7fb6, + (q15_t)0x7fb4, (q15_t)0x7fb2, (q15_t)0x7fb1, (q15_t)0x7faf, (q15_t)0x7fad, (q15_t)0x7fab, (q15_t)0x7fa9, (q15_t)0x7fa8, + (q15_t)0x7fa6, (q15_t)0x7fa4, (q15_t)0x7fa2, (q15_t)0x7fa0, (q15_t)0x7f9e, (q15_t)0x7f9c, (q15_t)0x7f9a, (q15_t)0x7f98, + (q15_t)0x7f96, (q15_t)0x7f94, (q15_t)0x7f92, (q15_t)0x7f90, (q15_t)0x7f8e, (q15_t)0x7f8c, (q15_t)0x7f8a, (q15_t)0x7f88, + (q15_t)0x7f86, (q15_t)0x7f83, (q15_t)0x7f81, (q15_t)0x7f7f, (q15_t)0x7f7d, (q15_t)0x7f7b, (q15_t)0x7f78, (q15_t)0x7f76, + (q15_t)0x7f74, (q15_t)0x7f71, (q15_t)0x7f6f, (q15_t)0x7f6d, (q15_t)0x7f6a, (q15_t)0x7f68, (q15_t)0x7f65, (q15_t)0x7f63, + (q15_t)0x7f60, (q15_t)0x7f5e, (q15_t)0x7f5b, (q15_t)0x7f59, (q15_t)0x7f56, (q15_t)0x7f54, (q15_t)0x7f51, (q15_t)0x7f4f, + (q15_t)0x7f4c, (q15_t)0x7f49, (q15_t)0x7f47, (q15_t)0x7f44, (q15_t)0x7f41, (q15_t)0x7f3f, (q15_t)0x7f3c, (q15_t)0x7f39, + (q15_t)0x7f36, (q15_t)0x7f34, (q15_t)0x7f31, (q15_t)0x7f2e, (q15_t)0x7f2b, (q15_t)0x7f28, (q15_t)0x7f25, (q15_t)0x7f23, + (q15_t)0x7f20, (q15_t)0x7f1d, (q15_t)0x7f1a, (q15_t)0x7f17, (q15_t)0x7f14, (q15_t)0x7f11, (q15_t)0x7f0e, (q15_t)0x7f0b, + (q15_t)0x7f08, (q15_t)0x7f04, (q15_t)0x7f01, (q15_t)0x7efe, (q15_t)0x7efb, (q15_t)0x7ef8, (q15_t)0x7ef5, (q15_t)0x7ef1, + (q15_t)0x7eee, (q15_t)0x7eeb, (q15_t)0x7ee8, (q15_t)0x7ee4, (q15_t)0x7ee1, (q15_t)0x7ede, (q15_t)0x7eda, (q15_t)0x7ed7, + (q15_t)0x7ed4, (q15_t)0x7ed0, (q15_t)0x7ecd, (q15_t)0x7ec9, (q15_t)0x7ec6, (q15_t)0x7ec3, (q15_t)0x7ebf, (q15_t)0x7ebb, + (q15_t)0x7eb8, (q15_t)0x7eb4, (q15_t)0x7eb1, (q15_t)0x7ead, (q15_t)0x7eaa, (q15_t)0x7ea6, (q15_t)0x7ea2, (q15_t)0x7e9f, + (q15_t)0x7e9b, (q15_t)0x7e97, (q15_t)0x7e94, (q15_t)0x7e90, (q15_t)0x7e8c, (q15_t)0x7e88, (q15_t)0x7e84, (q15_t)0x7e81, + (q15_t)0x7e7d, (q15_t)0x7e79, (q15_t)0x7e75, (q15_t)0x7e71, (q15_t)0x7e6d, (q15_t)0x7e69, (q15_t)0x7e65, (q15_t)0x7e61, + (q15_t)0x7e5d, (q15_t)0x7e59, (q15_t)0x7e55, (q15_t)0x7e51, (q15_t)0x7e4d, (q15_t)0x7e49, (q15_t)0x7e45, (q15_t)0x7e41, + (q15_t)0x7e3d, (q15_t)0x7e39, (q15_t)0x7e34, (q15_t)0x7e30, (q15_t)0x7e2c, (q15_t)0x7e28, (q15_t)0x7e24, (q15_t)0x7e1f, + (q15_t)0x7e1b, (q15_t)0x7e17, (q15_t)0x7e12, (q15_t)0x7e0e, (q15_t)0x7e0a, (q15_t)0x7e05, (q15_t)0x7e01, (q15_t)0x7dfc, + (q15_t)0x7df8, (q15_t)0x7df3, (q15_t)0x7def, (q15_t)0x7dea, (q15_t)0x7de6, (q15_t)0x7de1, (q15_t)0x7ddd, (q15_t)0x7dd8, + (q15_t)0x7dd4, (q15_t)0x7dcf, (q15_t)0x7dca, (q15_t)0x7dc6, (q15_t)0x7dc1, (q15_t)0x7dbc, (q15_t)0x7db8, (q15_t)0x7db3, + (q15_t)0x7dae, (q15_t)0x7da9, (q15_t)0x7da5, (q15_t)0x7da0, (q15_t)0x7d9b, (q15_t)0x7d96, (q15_t)0x7d91, (q15_t)0x7d8c, + (q15_t)0x7d87, (q15_t)0x7d82, (q15_t)0x7d7e, (q15_t)0x7d79, (q15_t)0x7d74, (q15_t)0x7d6f, (q15_t)0x7d6a, (q15_t)0x7d65, + (q15_t)0x7d60, (q15_t)0x7d5a, (q15_t)0x7d55, (q15_t)0x7d50, (q15_t)0x7d4b, (q15_t)0x7d46, (q15_t)0x7d41, (q15_t)0x7d3c, + (q15_t)0x7d36, (q15_t)0x7d31, (q15_t)0x7d2c, (q15_t)0x7d27, (q15_t)0x7d21, (q15_t)0x7d1c, (q15_t)0x7d17, (q15_t)0x7d11, + (q15_t)0x7d0c, (q15_t)0x7d07, (q15_t)0x7d01, (q15_t)0x7cfc, (q15_t)0x7cf6, (q15_t)0x7cf1, (q15_t)0x7cec, (q15_t)0x7ce6, + (q15_t)0x7ce1, (q15_t)0x7cdb, (q15_t)0x7cd5, (q15_t)0x7cd0, (q15_t)0x7cca, (q15_t)0x7cc5, (q15_t)0x7cbf, (q15_t)0x7cb9, + (q15_t)0x7cb4, (q15_t)0x7cae, (q15_t)0x7ca8, (q15_t)0x7ca3, (q15_t)0x7c9d, (q15_t)0x7c97, (q15_t)0x7c91, (q15_t)0x7c8c, + (q15_t)0x7c86, (q15_t)0x7c80, (q15_t)0x7c7a, (q15_t)0x7c74, (q15_t)0x7c6e, (q15_t)0x7c69, (q15_t)0x7c63, (q15_t)0x7c5d, + (q15_t)0x7c57, (q15_t)0x7c51, (q15_t)0x7c4b, (q15_t)0x7c45, (q15_t)0x7c3f, (q15_t)0x7c39, (q15_t)0x7c33, (q15_t)0x7c2d, + (q15_t)0x7c26, (q15_t)0x7c20, (q15_t)0x7c1a, (q15_t)0x7c14, (q15_t)0x7c0e, (q15_t)0x7c08, (q15_t)0x7c01, (q15_t)0x7bfb, + (q15_t)0x7bf5, (q15_t)0x7bef, (q15_t)0x7be8, (q15_t)0x7be2, (q15_t)0x7bdc, (q15_t)0x7bd5, (q15_t)0x7bcf, (q15_t)0x7bc9, + (q15_t)0x7bc2, (q15_t)0x7bbc, (q15_t)0x7bb5, (q15_t)0x7baf, (q15_t)0x7ba8, (q15_t)0x7ba2, (q15_t)0x7b9b, (q15_t)0x7b95, + (q15_t)0x7b8e, (q15_t)0x7b88, (q15_t)0x7b81, (q15_t)0x7b7a, (q15_t)0x7b74, (q15_t)0x7b6d, (q15_t)0x7b67, (q15_t)0x7b60, + (q15_t)0x7b59, (q15_t)0x7b52, (q15_t)0x7b4c, (q15_t)0x7b45, (q15_t)0x7b3e, (q15_t)0x7b37, (q15_t)0x7b31, (q15_t)0x7b2a, + (q15_t)0x7b23, (q15_t)0x7b1c, (q15_t)0x7b15, (q15_t)0x7b0e, (q15_t)0x7b07, (q15_t)0x7b00, (q15_t)0x7af9, (q15_t)0x7af2, + (q15_t)0x7aeb, (q15_t)0x7ae4, (q15_t)0x7add, (q15_t)0x7ad6, (q15_t)0x7acf, (q15_t)0x7ac8, (q15_t)0x7ac1, (q15_t)0x7aba, + (q15_t)0x7ab3, (q15_t)0x7aac, (q15_t)0x7aa4, (q15_t)0x7a9d, (q15_t)0x7a96, (q15_t)0x7a8f, (q15_t)0x7a87, (q15_t)0x7a80, + (q15_t)0x7a79, (q15_t)0x7a72, (q15_t)0x7a6a, (q15_t)0x7a63, (q15_t)0x7a5c, (q15_t)0x7a54, (q15_t)0x7a4d, (q15_t)0x7a45, + (q15_t)0x7a3e, (q15_t)0x7a36, (q15_t)0x7a2f, (q15_t)0x7a27, (q15_t)0x7a20, (q15_t)0x7a18, (q15_t)0x7a11, (q15_t)0x7a09, + (q15_t)0x7a02, (q15_t)0x79fa, (q15_t)0x79f2, (q15_t)0x79eb, (q15_t)0x79e3, (q15_t)0x79db, (q15_t)0x79d4, (q15_t)0x79cc, + (q15_t)0x79c4, (q15_t)0x79bc, (q15_t)0x79b5, (q15_t)0x79ad, (q15_t)0x79a5, (q15_t)0x799d, (q15_t)0x7995, (q15_t)0x798e, + (q15_t)0x7986, (q15_t)0x797e, (q15_t)0x7976, (q15_t)0x796e, (q15_t)0x7966, (q15_t)0x795e, (q15_t)0x7956, (q15_t)0x794e, + (q15_t)0x7946, (q15_t)0x793e, (q15_t)0x7936, (q15_t)0x792e, (q15_t)0x7926, (q15_t)0x791e, (q15_t)0x7915, (q15_t)0x790d, + (q15_t)0x7905, (q15_t)0x78fd, (q15_t)0x78f5, (q15_t)0x78ec, (q15_t)0x78e4, (q15_t)0x78dc, (q15_t)0x78d4, (q15_t)0x78cb, + (q15_t)0x78c3, (q15_t)0x78bb, (q15_t)0x78b2, (q15_t)0x78aa, (q15_t)0x78a2, (q15_t)0x7899, (q15_t)0x7891, (q15_t)0x7888, + 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(q15_t)0x1098, (q15_t)0x107f, + (q15_t)0x1066, (q15_t)0x104d, (q15_t)0x1034, (q15_t)0x101b, (q15_t)0x1002, (q15_t)0xfe9, (q15_t)0xfd0, (q15_t)0xfb7, + (q15_t)0xf9e, (q15_t)0xf85, (q15_t)0xf6c, (q15_t)0xf53, (q15_t)0xf3a, (q15_t)0xf21, (q15_t)0xf08, (q15_t)0xef0, + (q15_t)0xed7, (q15_t)0xebe, (q15_t)0xea5, (q15_t)0xe8c, (q15_t)0xe73, (q15_t)0xe5a, (q15_t)0xe41, (q15_t)0xe28, + (q15_t)0xe0f, (q15_t)0xdf6, (q15_t)0xddd, (q15_t)0xdc4, (q15_t)0xdab, (q15_t)0xd92, (q15_t)0xd79, (q15_t)0xd60, + (q15_t)0xd47, (q15_t)0xd2e, (q15_t)0xd15, (q15_t)0xcfc, (q15_t)0xce3, (q15_t)0xcca, (q15_t)0xcb1, (q15_t)0xc98, + (q15_t)0xc7f, (q15_t)0xc66, (q15_t)0xc4d, (q15_t)0xc34, (q15_t)0xc1b, (q15_t)0xc02, (q15_t)0xbe9, (q15_t)0xbd0, + (q15_t)0xbb7, (q15_t)0xb9e, (q15_t)0xb85, (q15_t)0xb6c, (q15_t)0xb53, (q15_t)0xb3a, (q15_t)0xb20, (q15_t)0xb07, + (q15_t)0xaee, (q15_t)0xad5, (q15_t)0xabc, (q15_t)0xaa3, (q15_t)0xa8a, (q15_t)0xa71, (q15_t)0xa58, (q15_t)0xa3f, + (q15_t)0xa26, (q15_t)0xa0d, (q15_t)0x9f4, (q15_t)0x9db, (q15_t)0x9c2, (q15_t)0x9a9, (q15_t)0x990, (q15_t)0x977, + (q15_t)0x95e, (q15_t)0x944, (q15_t)0x92b, (q15_t)0x912, (q15_t)0x8f9, (q15_t)0x8e0, (q15_t)0x8c7, (q15_t)0x8ae, + (q15_t)0x895, (q15_t)0x87c, (q15_t)0x863, (q15_t)0x84a, (q15_t)0x831, (q15_t)0x818, (q15_t)0x7fe, (q15_t)0x7e5, + (q15_t)0x7cc, (q15_t)0x7b3, (q15_t)0x79a, (q15_t)0x781, (q15_t)0x768, (q15_t)0x74f, (q15_t)0x736, (q15_t)0x71d, + (q15_t)0x704, (q15_t)0x6ea, (q15_t)0x6d1, (q15_t)0x6b8, (q15_t)0x69f, (q15_t)0x686, (q15_t)0x66d, (q15_t)0x654, + (q15_t)0x63b, (q15_t)0x622, (q15_t)0x609, (q15_t)0x5ef, (q15_t)0x5d6, (q15_t)0x5bd, (q15_t)0x5a4, (q15_t)0x58b, + (q15_t)0x572, (q15_t)0x559, (q15_t)0x540, (q15_t)0x527, (q15_t)0x50d, (q15_t)0x4f4, (q15_t)0x4db, (q15_t)0x4c2, + (q15_t)0x4a9, (q15_t)0x490, (q15_t)0x477, (q15_t)0x45e, (q15_t)0x445, (q15_t)0x42b, (q15_t)0x412, (q15_t)0x3f9, + (q15_t)0x3e0, (q15_t)0x3c7, (q15_t)0x3ae, (q15_t)0x395, (q15_t)0x37c, (q15_t)0x362, (q15_t)0x349, (q15_t)0x330, + (q15_t)0x317, (q15_t)0x2fe, (q15_t)0x2e5, (q15_t)0x2cc, (q15_t)0x2b3, (q15_t)0x299, (q15_t)0x280, (q15_t)0x267, + (q15_t)0x24e, (q15_t)0x235, (q15_t)0x21c, (q15_t)0x203, (q15_t)0x1ea, (q15_t)0x1d0, (q15_t)0x1b7, (q15_t)0x19e, + (q15_t)0x185, (q15_t)0x16c, (q15_t)0x153, (q15_t)0x13a, (q15_t)0x121, (q15_t)0x107, (q15_t)0xee, (q15_t)0xd5, + (q15_t)0xbc, (q15_t)0xa3, (q15_t)0x8a, (q15_t)0x71, (q15_t)0x57, (q15_t)0x3e, (q15_t)0x25, (q15_t)0xc + +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + const q15_t __ALIGNED(4) WeightsQ15_8192[16384] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xfffa, (q15_t)0x7fff, (q15_t)0xfff4, (q15_t)0x7fff, (q15_t)0xffee, + (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffe1, (q15_t)0x7fff, (q15_t)0xffdb, (q15_t)0x7fff, (q15_t)0xffd5, + (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffc8, (q15_t)0x7fff, (q15_t)0xffc2, (q15_t)0x7fff, (q15_t)0xffbb, + (q15_t)0x7fff, (q15_t)0xffb5, (q15_t)0x7fff, (q15_t)0xffaf, (q15_t)0x7fff, (q15_t)0xffa9, (q15_t)0x7fff, (q15_t)0xffa2, + (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff96, (q15_t)0x7fff, (q15_t)0xff8f, (q15_t)0x7fff, (q15_t)0xff89, + (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff7d, (q15_t)0x7fff, (q15_t)0xff76, (q15_t)0x7fff, (q15_t)0xff70, + (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff63, (q15_t)0x7fff, (q15_t)0xff5d, (q15_t)0x7fff, (q15_t)0xff57, + (q15_t)0x7fff, (q15_t)0xff51, (q15_t)0x7fff, (q15_t)0xff4a, (q15_t)0x7fff, (q15_t)0xff44, (q15_t)0x7fff, (q15_t)0xff3e, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff31, (q15_t)0x7fff, (q15_t)0xff2b, (q15_t)0x7fff, (q15_t)0xff25, + (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff18, (q15_t)0x7fff, (q15_t)0xff12, (q15_t)0x7fff, (q15_t)0xff0b, + (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeff, (q15_t)0x7ffe, (q15_t)0xfef9, (q15_t)0x7ffe, (q15_t)0xfef2, + (q15_t)0x7ffe, (q15_t)0xfeec, (q15_t)0x7ffe, (q15_t)0xfee6, (q15_t)0x7ffe, (q15_t)0xfedf, (q15_t)0x7ffe, (q15_t)0xfed9, + (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfecd, (q15_t)0x7ffe, (q15_t)0xfec6, (q15_t)0x7ffe, (q15_t)0xfec0, + (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfeb3, (q15_t)0x7ffe, (q15_t)0xfead, (q15_t)0x7ffe, (q15_t)0xfea7, + (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffe, (q15_t)0xfe9a, (q15_t)0x7ffd, (q15_t)0xfe94, (q15_t)0x7ffd, (q15_t)0xfe8e, + (q15_t)0x7ffd, (q15_t)0xfe88, (q15_t)0x7ffd, (q15_t)0xfe81, (q15_t)0x7ffd, (q15_t)0xfe7b, (q15_t)0x7ffd, (q15_t)0xfe75, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe68, (q15_t)0x7ffd, (q15_t)0xfe62, (q15_t)0x7ffd, (q15_t)0xfe5c, + (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffd, (q15_t)0xfe4f, (q15_t)0x7ffd, (q15_t)0xfe49, (q15_t)0x7ffc, (q15_t)0xfe42, + (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe36, (q15_t)0x7ffc, (q15_t)0xfe30, (q15_t)0x7ffc, (q15_t)0xfe29, + (q15_t)0x7ffc, (q15_t)0xfe23, (q15_t)0x7ffc, (q15_t)0xfe1d, (q15_t)0x7ffc, (q15_t)0xfe16, (q15_t)0x7ffc, (q15_t)0xfe10, + (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffc, (q15_t)0xfe04, (q15_t)0x7ffb, (q15_t)0xfdfd, (q15_t)0x7ffb, (q15_t)0xfdf7, + (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdea, (q15_t)0x7ffb, (q15_t)0xfde4, (q15_t)0x7ffb, (q15_t)0xfdde, + (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffb, (q15_t)0xfdd1, (q15_t)0x7ffb, (q15_t)0xfdcb, (q15_t)0x7ffb, (q15_t)0xfdc5, + (q15_t)0x7ffa, (q15_t)0xfdbe, (q15_t)0x7ffa, (q15_t)0xfdb8, (q15_t)0x7ffa, (q15_t)0xfdb2, (q15_t)0x7ffa, (q15_t)0xfdac, + (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ffa, (q15_t)0xfd9f, (q15_t)0x7ffa, (q15_t)0xfd99, (q15_t)0x7ffa, (q15_t)0xfd93, + (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd86, (q15_t)0x7ff9, (q15_t)0xfd80, (q15_t)0x7ff9, (q15_t)0xfd79, + (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff9, (q15_t)0xfd6d, (q15_t)0x7ff9, (q15_t)0xfd67, (q15_t)0x7ff9, (q15_t)0xfd60, + (q15_t)0x7ff8, (q15_t)0xfd5a, (q15_t)0x7ff8, (q15_t)0xfd54, (q15_t)0x7ff8, (q15_t)0xfd4d, (q15_t)0x7ff8, (q15_t)0xfd47, + (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff8, (q15_t)0xfd3b, (q15_t)0x7ff8, (q15_t)0xfd34, (q15_t)0x7ff8, (q15_t)0xfd2e, + (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd21, (q15_t)0x7ff7, (q15_t)0xfd1b, (q15_t)0x7ff7, (q15_t)0xfd15, + (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff7, (q15_t)0xfd08, (q15_t)0x7ff7, (q15_t)0xfd02, (q15_t)0x7ff6, (q15_t)0xfcfc, + (q15_t)0x7ff6, (q15_t)0xfcf5, (q15_t)0x7ff6, (q15_t)0xfcef, (q15_t)0x7ff6, (q15_t)0xfce9, (q15_t)0x7ff6, (q15_t)0xfce3, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcd6, (q15_t)0x7ff5, (q15_t)0xfcd0, (q15_t)0x7ff5, (q15_t)0xfcc9, + (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff5, (q15_t)0xfcbd, (q15_t)0x7ff5, (q15_t)0xfcb7, (q15_t)0x7ff5, (q15_t)0xfcb0, + (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfca4, (q15_t)0x7ff4, (q15_t)0xfc9e, (q15_t)0x7ff4, (q15_t)0xfc97, + (q15_t)0x7ff4, (q15_t)0xfc91, (q15_t)0x7ff4, (q15_t)0xfc8b, (q15_t)0x7ff3, (q15_t)0xfc84, (q15_t)0x7ff3, (q15_t)0xfc7e, + (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff3, (q15_t)0xfc72, (q15_t)0x7ff3, (q15_t)0xfc6b, (q15_t)0x7ff2, (q15_t)0xfc65, + (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc58, (q15_t)0x7ff2, (q15_t)0xfc52, (q15_t)0x7ff2, (q15_t)0xfc4c, + (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc3f, (q15_t)0x7ff1, (q15_t)0xfc39, (q15_t)0x7ff1, (q15_t)0xfc33, + (q15_t)0x7ff1, (q15_t)0xfc2c, (q15_t)0x7ff1, (q15_t)0xfc26, (q15_t)0x7ff0, (q15_t)0xfc20, (q15_t)0x7ff0, (q15_t)0xfc1a, + (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7ff0, (q15_t)0xfc0d, (q15_t)0x7ff0, (q15_t)0xfc07, (q15_t)0x7fef, (q15_t)0xfc01, + (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fef, (q15_t)0xfbf4, (q15_t)0x7fef, (q15_t)0xfbee, (q15_t)0x7fef, (q15_t)0xfbe7, + (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbdb, (q15_t)0x7fee, (q15_t)0xfbd5, (q15_t)0x7fee, (q15_t)0xfbce, + (q15_t)0x7fee, (q15_t)0xfbc8, (q15_t)0x7fed, (q15_t)0xfbc2, (q15_t)0x7fed, (q15_t)0xfbbb, (q15_t)0x7fed, (q15_t)0xfbb5, + (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fed, (q15_t)0xfba9, (q15_t)0x7fec, (q15_t)0xfba2, (q15_t)0x7fec, (q15_t)0xfb9c, + (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7fec, (q15_t)0xfb8f, (q15_t)0x7fec, (q15_t)0xfb89, (q15_t)0x7feb, (q15_t)0xfb83, + (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7feb, (q15_t)0xfb76, (q15_t)0x7feb, (q15_t)0xfb70, (q15_t)0x7fea, (q15_t)0xfb6a, + (q15_t)0x7fea, (q15_t)0xfb64, (q15_t)0x7fea, (q15_t)0xfb5d, (q15_t)0x7fea, (q15_t)0xfb57, (q15_t)0x7fea, (q15_t)0xfb51, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe9, (q15_t)0xfb44, (q15_t)0x7fe9, (q15_t)0xfb3e, (q15_t)0x7fe9, (q15_t)0xfb38, + (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe8, (q15_t)0xfb2b, (q15_t)0x7fe8, (q15_t)0xfb25, (q15_t)0x7fe8, (q15_t)0xfb1e, + (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe7, (q15_t)0xfb12, (q15_t)0x7fe7, (q15_t)0xfb0c, (q15_t)0x7fe7, (q15_t)0xfb05, + (q15_t)0x7fe6, (q15_t)0xfaff, (q15_t)0x7fe6, (q15_t)0xfaf9, (q15_t)0x7fe6, (q15_t)0xfaf3, (q15_t)0x7fe6, (q15_t)0xfaec, + (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe5, (q15_t)0xfae0, (q15_t)0x7fe5, (q15_t)0xfad9, (q15_t)0x7fe5, (q15_t)0xfad3, + (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe4, (q15_t)0xfac7, (q15_t)0x7fe4, (q15_t)0xfac0, (q15_t)0x7fe4, (q15_t)0xfaba, + (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe3, (q15_t)0xfaad, (q15_t)0x7fe3, (q15_t)0xfaa7, (q15_t)0x7fe3, (q15_t)0xfaa1, + (q15_t)0x7fe2, (q15_t)0xfa9b, (q15_t)0x7fe2, (q15_t)0xfa94, (q15_t)0x7fe2, (q15_t)0xfa8e, (q15_t)0x7fe2, (q15_t)0xfa88, + (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe1, (q15_t)0xfa7b, (q15_t)0x7fe1, (q15_t)0xfa75, (q15_t)0x7fe0, (q15_t)0xfa6f, + (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fe0, (q15_t)0xfa62, (q15_t)0x7fe0, (q15_t)0xfa5c, (q15_t)0x7fdf, (q15_t)0xfa56, + (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fdf, (q15_t)0xfa49, (q15_t)0x7fdf, (q15_t)0xfa43, (q15_t)0x7fde, (q15_t)0xfa3c, + (q15_t)0x7fde, (q15_t)0xfa36, (q15_t)0x7fde, (q15_t)0xfa30, (q15_t)0x7fdd, (q15_t)0xfa2a, (q15_t)0x7fdd, (q15_t)0xfa23, + (q15_t)0x7fdd, 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(q15_t)0x356, (q15_t)0x800c, (q15_t)0x350, (q15_t)0x800b, (q15_t)0x349, (q15_t)0x800b, (q15_t)0x343, (q15_t)0x800b, + (q15_t)0x33d, (q15_t)0x800b, (q15_t)0x337, (q15_t)0x800b, (q15_t)0x330, (q15_t)0x800b, (q15_t)0x32a, (q15_t)0x800b, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x31d, (q15_t)0x800a, (q15_t)0x317, (q15_t)0x800a, (q15_t)0x311, (q15_t)0x800a, + (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x304, (q15_t)0x800a, (q15_t)0x2fe, (q15_t)0x8009, (q15_t)0x2f8, (q15_t)0x8009, + (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2eb, (q15_t)0x8009, (q15_t)0x2e5, (q15_t)0x8009, (q15_t)0x2df, (q15_t)0x8009, + (q15_t)0x2d8, (q15_t)0x8009, (q15_t)0x2d2, (q15_t)0x8008, (q15_t)0x2cc, (q15_t)0x8008, (q15_t)0x2c5, (q15_t)0x8008, + (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2b9, (q15_t)0x8008, (q15_t)0x2b3, (q15_t)0x8008, (q15_t)0x2ac, (q15_t)0x8008, + (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x2a0, (q15_t)0x8007, (q15_t)0x299, (q15_t)0x8007, (q15_t)0x293, (q15_t)0x8007, + (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x287, (q15_t)0x8007, (q15_t)0x280, (q15_t)0x8007, (q15_t)0x27a, (q15_t)0x8007, + (q15_t)0x274, (q15_t)0x8007, (q15_t)0x26d, (q15_t)0x8006, (q15_t)0x267, (q15_t)0x8006, (q15_t)0x261, (q15_t)0x8006, + (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x254, (q15_t)0x8006, (q15_t)0x24e, (q15_t)0x8006, (q15_t)0x248, (q15_t)0x8006, + (q15_t)0x242, (q15_t)0x8006, (q15_t)0x23b, (q15_t)0x8005, (q15_t)0x235, (q15_t)0x8005, (q15_t)0x22f, (q15_t)0x8005, + (q15_t)0x228, (q15_t)0x8005, (q15_t)0x222, (q15_t)0x8005, (q15_t)0x21c, (q15_t)0x8005, (q15_t)0x216, (q15_t)0x8005, + (q15_t)0x20f, (q15_t)0x8005, (q15_t)0x209, (q15_t)0x8005, (q15_t)0x203, (q15_t)0x8005, (q15_t)0x1fc, (q15_t)0x8004, + (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1f0, (q15_t)0x8004, (q15_t)0x1ea, (q15_t)0x8004, (q15_t)0x1e3, (q15_t)0x8004, + (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1d7, (q15_t)0x8004, (q15_t)0x1d0, (q15_t)0x8004, (q15_t)0x1ca, (q15_t)0x8004, + (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1be, (q15_t)0x8004, (q15_t)0x1b7, (q15_t)0x8003, (q15_t)0x1b1, (q15_t)0x8003, + (q15_t)0x1ab, (q15_t)0x8003, (q15_t)0x1a4, (q15_t)0x8003, (q15_t)0x19e, (q15_t)0x8003, (q15_t)0x198, (q15_t)0x8003, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x18b, (q15_t)0x8003, (q15_t)0x185, (q15_t)0x8003, (q15_t)0x17f, (q15_t)0x8003, + (q15_t)0x178, (q15_t)0x8003, (q15_t)0x172, (q15_t)0x8003, (q15_t)0x16c, (q15_t)0x8003, (q15_t)0x166, (q15_t)0x8002, + (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x159, (q15_t)0x8002, (q15_t)0x153, (q15_t)0x8002, (q15_t)0x14d, (q15_t)0x8002, + (q15_t)0x146, (q15_t)0x8002, (q15_t)0x140, (q15_t)0x8002, (q15_t)0x13a, (q15_t)0x8002, (q15_t)0x133, (q15_t)0x8002, + (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x127, (q15_t)0x8002, (q15_t)0x121, (q15_t)0x8002, (q15_t)0x11a, (q15_t)0x8002, + (q15_t)0x114, (q15_t)0x8002, (q15_t)0x10e, (q15_t)0x8002, (q15_t)0x107, (q15_t)0x8002, (q15_t)0x101, (q15_t)0x8002, + (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xf5, (q15_t)0x8001, (q15_t)0xee, (q15_t)0x8001, (q15_t)0xe8, (q15_t)0x8001, + (q15_t)0xe2, (q15_t)0x8001, (q15_t)0xdb, (q15_t)0x8001, (q15_t)0xd5, (q15_t)0x8001, (q15_t)0xcf, (q15_t)0x8001, + (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xc2, (q15_t)0x8001, (q15_t)0xbc, (q15_t)0x8001, (q15_t)0xb6, (q15_t)0x8001, + (q15_t)0xaf, (q15_t)0x8001, (q15_t)0xa9, (q15_t)0x8001, (q15_t)0xa3, (q15_t)0x8001, (q15_t)0x9d, (q15_t)0x8001, + (q15_t)0x96, (q15_t)0x8001, (q15_t)0x90, (q15_t)0x8001, (q15_t)0x8a, (q15_t)0x8001, (q15_t)0x83, (q15_t)0x8001, + (q15_t)0x7d, (q15_t)0x8001, (q15_t)0x77, (q15_t)0x8001, (q15_t)0x71, (q15_t)0x8001, (q15_t)0x6a, (q15_t)0x8001, + (q15_t)0x64, (q15_t)0x8001, (q15_t)0x5e, (q15_t)0x8001, (q15_t)0x57, (q15_t)0x8001, (q15_t)0x51, (q15_t)0x8001, + (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x45, (q15_t)0x8001, (q15_t)0x3e, (q15_t)0x8001, (q15_t)0x38, (q15_t)0x8001, + (q15_t)0x32, (q15_t)0x8001, (q15_t)0x2b, (q15_t)0x8001, (q15_t)0x25, (q15_t)0x8001, (q15_t)0x1f, (q15_t)0x8001, + (q15_t)0x19, (q15_t)0x8001, (q15_t)0x12, (q15_t)0x8001, (q15_t)0xc, (q15_t)0x8001, (q15_t)0x6, (q15_t)0x8001 +}; + + const q15_t __ALIGNED(4) cos_factorsQ15_8192[8192] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, + (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, + (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, + (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, + (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, + (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, + (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, + (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, + (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, + (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, + (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, + (q15_t)0x7ff6, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, + (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, + (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, + (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff0, (q15_t)0x7ff0, + (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, + (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fed, + (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7feb, + (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fe9, + (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, + (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, + (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, + (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe1, + (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdf, + (q15_t)0x7fdf, (q15_t)0x7fdf, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fdd, (q15_t)0x7fdd, + (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, + (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd8, (q15_t)0x7fd8, + (q15_t)0x7fd8, (q15_t)0x7fd8, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd6, (q15_t)0x7fd6, + (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd3, (q15_t)0x7fd3, + (q15_t)0x7fd3, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd0, + (q15_t)0x7fd0, (q15_t)0x7fd0, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fce, (q15_t)0x7fce, (q15_t)0x7fce, + (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcb, (q15_t)0x7fcb, + (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc8, (q15_t)0x7fc8, + (q15_t)0x7fc8, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc6, (q15_t)0x7fc5, (q15_t)0x7fc5, + (q15_t)0x7fc5, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc3, (q15_t)0x7fc3, (q15_t)0x7fc2, (q15_t)0x7fc2, + (q15_t)0x7fc2, (q15_t)0x7fc1, (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fbf, (q15_t)0x7fbf, + (q15_t)0x7fbf, (q15_t)0x7fbe, (q15_t)0x7fbe, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbc, (q15_t)0x7fbc, + (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fba, (q15_t)0x7fba, (q15_t)0x7fb9, (q15_t)0x7fb9, (q15_t)0x7fb8, + (q15_t)0x7fb8, (q15_t)0x7fb8, (q15_t)0x7fb7, (q15_t)0x7fb7, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb5, + (q15_t)0x7fb5, (q15_t)0x7fb4, (q15_t)0x7fb4, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb2, (q15_t)0x7fb2, + (q15_t)0x7fb1, (q15_t)0x7fb1, (q15_t)0x7fb0, (q15_t)0x7fb0, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7fae, + (q15_t)0x7fae, (q15_t)0x7fad, (q15_t)0x7fad, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fab, (q15_t)0x7fab, + (q15_t)0x7faa, (q15_t)0x7faa, (q15_t)0x7fa9, (q15_t)0x7fa9, (q15_t)0x7fa8, (q15_t)0x7fa8, (q15_t)0x7fa7, (q15_t)0x7fa7, + (q15_t)0x7fa6, (q15_t)0x7fa6, (q15_t)0x7fa6, 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(q15_t)0xe50, + (q15_t)0xe4a, (q15_t)0xe44, (q15_t)0xe3e, (q15_t)0xe37, (q15_t)0xe31, (q15_t)0xe2b, (q15_t)0xe25, (q15_t)0xe1e, + (q15_t)0xe18, (q15_t)0xe12, (q15_t)0xe0c, (q15_t)0xe05, (q15_t)0xdff, (q15_t)0xdf9, (q15_t)0xdf3, (q15_t)0xdec, + (q15_t)0xde6, (q15_t)0xde0, (q15_t)0xdda, (q15_t)0xdd3, (q15_t)0xdcd, (q15_t)0xdc7, (q15_t)0xdc1, (q15_t)0xdba, + (q15_t)0xdb4, (q15_t)0xdae, (q15_t)0xda8, (q15_t)0xda1, (q15_t)0xd9b, (q15_t)0xd95, (q15_t)0xd8f, (q15_t)0xd88, + (q15_t)0xd82, (q15_t)0xd7c, (q15_t)0xd76, (q15_t)0xd6f, (q15_t)0xd69, (q15_t)0xd63, (q15_t)0xd5d, (q15_t)0xd56, + (q15_t)0xd50, (q15_t)0xd4a, (q15_t)0xd44, (q15_t)0xd3d, (q15_t)0xd37, (q15_t)0xd31, (q15_t)0xd2b, (q15_t)0xd24, + (q15_t)0xd1e, (q15_t)0xd18, (q15_t)0xd12, (q15_t)0xd0b, (q15_t)0xd05, (q15_t)0xcff, (q15_t)0xcf9, (q15_t)0xcf2, + (q15_t)0xcec, (q15_t)0xce6, (q15_t)0xce0, (q15_t)0xcd9, (q15_t)0xcd3, (q15_t)0xccd, (q15_t)0xcc7, (q15_t)0xcc0, + (q15_t)0xcba, (q15_t)0xcb4, (q15_t)0xcae, (q15_t)0xca7, (q15_t)0xca1, (q15_t)0xc9b, (q15_t)0xc95, (q15_t)0xc8e, + (q15_t)0xc88, (q15_t)0xc82, (q15_t)0xc7c, (q15_t)0xc75, (q15_t)0xc6f, (q15_t)0xc69, (q15_t)0xc63, (q15_t)0xc5c, + (q15_t)0xc56, (q15_t)0xc50, (q15_t)0xc4a, (q15_t)0xc43, (q15_t)0xc3d, (q15_t)0xc37, (q15_t)0xc31, (q15_t)0xc2a, + (q15_t)0xc24, (q15_t)0xc1e, (q15_t)0xc18, (q15_t)0xc11, (q15_t)0xc0b, (q15_t)0xc05, (q15_t)0xbff, (q15_t)0xbf8, + (q15_t)0xbf2, (q15_t)0xbec, (q15_t)0xbe6, (q15_t)0xbdf, (q15_t)0xbd9, (q15_t)0xbd3, (q15_t)0xbcd, (q15_t)0xbc6, + (q15_t)0xbc0, (q15_t)0xbba, (q15_t)0xbb4, (q15_t)0xbad, (q15_t)0xba7, (q15_t)0xba1, (q15_t)0xb9b, (q15_t)0xb94, + (q15_t)0xb8e, (q15_t)0xb88, (q15_t)0xb81, (q15_t)0xb7b, (q15_t)0xb75, (q15_t)0xb6f, (q15_t)0xb68, (q15_t)0xb62, + (q15_t)0xb5c, (q15_t)0xb56, (q15_t)0xb4f, (q15_t)0xb49, (q15_t)0xb43, (q15_t)0xb3d, (q15_t)0xb36, (q15_t)0xb30, + (q15_t)0xb2a, (q15_t)0xb24, (q15_t)0xb1d, (q15_t)0xb17, (q15_t)0xb11, (q15_t)0xb0b, (q15_t)0xb04, (q15_t)0xafe, + (q15_t)0xaf8, (q15_t)0xaf2, (q15_t)0xaeb, (q15_t)0xae5, (q15_t)0xadf, (q15_t)0xad8, (q15_t)0xad2, (q15_t)0xacc, + (q15_t)0xac6, (q15_t)0xabf, (q15_t)0xab9, (q15_t)0xab3, (q15_t)0xaad, (q15_t)0xaa6, (q15_t)0xaa0, (q15_t)0xa9a, + (q15_t)0xa94, (q15_t)0xa8d, (q15_t)0xa87, (q15_t)0xa81, (q15_t)0xa7b, (q15_t)0xa74, (q15_t)0xa6e, (q15_t)0xa68, + (q15_t)0xa62, (q15_t)0xa5b, (q15_t)0xa55, (q15_t)0xa4f, (q15_t)0xa48, (q15_t)0xa42, (q15_t)0xa3c, (q15_t)0xa36, + (q15_t)0xa2f, (q15_t)0xa29, (q15_t)0xa23, (q15_t)0xa1d, (q15_t)0xa16, (q15_t)0xa10, (q15_t)0xa0a, (q15_t)0xa04, + (q15_t)0x9fd, (q15_t)0x9f7, (q15_t)0x9f1, (q15_t)0x9eb, (q15_t)0x9e4, (q15_t)0x9de, (q15_t)0x9d8, (q15_t)0x9d1, + (q15_t)0x9cb, (q15_t)0x9c5, (q15_t)0x9bf, (q15_t)0x9b8, (q15_t)0x9b2, (q15_t)0x9ac, (q15_t)0x9a6, (q15_t)0x99f, + (q15_t)0x999, (q15_t)0x993, (q15_t)0x98d, (q15_t)0x986, (q15_t)0x980, (q15_t)0x97a, (q15_t)0x973, (q15_t)0x96d, + (q15_t)0x967, (q15_t)0x961, (q15_t)0x95a, (q15_t)0x954, (q15_t)0x94e, (q15_t)0x948, (q15_t)0x941, (q15_t)0x93b, + (q15_t)0x935, (q15_t)0x92f, (q15_t)0x928, (q15_t)0x922, (q15_t)0x91c, (q15_t)0x915, (q15_t)0x90f, (q15_t)0x909, + (q15_t)0x903, (q15_t)0x8fc, (q15_t)0x8f6, (q15_t)0x8f0, (q15_t)0x8ea, (q15_t)0x8e3, (q15_t)0x8dd, (q15_t)0x8d7, + (q15_t)0x8d1, (q15_t)0x8ca, (q15_t)0x8c4, (q15_t)0x8be, (q15_t)0x8b7, (q15_t)0x8b1, (q15_t)0x8ab, (q15_t)0x8a5, + (q15_t)0x89e, (q15_t)0x898, (q15_t)0x892, (q15_t)0x88c, (q15_t)0x885, (q15_t)0x87f, (q15_t)0x879, (q15_t)0x872, + (q15_t)0x86c, (q15_t)0x866, (q15_t)0x860, (q15_t)0x859, (q15_t)0x853, (q15_t)0x84d, (q15_t)0x847, (q15_t)0x840, + (q15_t)0x83a, (q15_t)0x834, (q15_t)0x82e, (q15_t)0x827, (q15_t)0x821, (q15_t)0x81b, (q15_t)0x814, (q15_t)0x80e, + (q15_t)0x808, (q15_t)0x802, (q15_t)0x7fb, (q15_t)0x7f5, (q15_t)0x7ef, (q15_t)0x7e9, (q15_t)0x7e2, (q15_t)0x7dc, + (q15_t)0x7d6, (q15_t)0x7cf, (q15_t)0x7c9, (q15_t)0x7c3, (q15_t)0x7bd, (q15_t)0x7b6, (q15_t)0x7b0, (q15_t)0x7aa, + (q15_t)0x7a4, (q15_t)0x79d, (q15_t)0x797, (q15_t)0x791, (q15_t)0x78a, (q15_t)0x784, (q15_t)0x77e, (q15_t)0x778, + (q15_t)0x771, (q15_t)0x76b, (q15_t)0x765, (q15_t)0x75f, (q15_t)0x758, (q15_t)0x752, (q15_t)0x74c, (q15_t)0x745, + (q15_t)0x73f, (q15_t)0x739, (q15_t)0x733, (q15_t)0x72c, (q15_t)0x726, (q15_t)0x720, (q15_t)0x71a, (q15_t)0x713, + (q15_t)0x70d, (q15_t)0x707, (q15_t)0x700, (q15_t)0x6fa, (q15_t)0x6f4, (q15_t)0x6ee, (q15_t)0x6e7, (q15_t)0x6e1, + (q15_t)0x6db, (q15_t)0x6d5, (q15_t)0x6ce, (q15_t)0x6c8, (q15_t)0x6c2, (q15_t)0x6bb, (q15_t)0x6b5, (q15_t)0x6af, + (q15_t)0x6a9, (q15_t)0x6a2, (q15_t)0x69c, (q15_t)0x696, (q15_t)0x690, (q15_t)0x689, (q15_t)0x683, (q15_t)0x67d, + (q15_t)0x676, (q15_t)0x670, (q15_t)0x66a, (q15_t)0x664, (q15_t)0x65d, (q15_t)0x657, (q15_t)0x651, (q15_t)0x64a, + (q15_t)0x644, (q15_t)0x63e, (q15_t)0x638, (q15_t)0x631, (q15_t)0x62b, (q15_t)0x625, (q15_t)0x61f, (q15_t)0x618, + (q15_t)0x612, (q15_t)0x60c, (q15_t)0x605, (q15_t)0x5ff, (q15_t)0x5f9, (q15_t)0x5f3, (q15_t)0x5ec, (q15_t)0x5e6, + (q15_t)0x5e0, (q15_t)0x5da, (q15_t)0x5d3, (q15_t)0x5cd, (q15_t)0x5c7, (q15_t)0x5c0, (q15_t)0x5ba, (q15_t)0x5b4, + (q15_t)0x5ae, (q15_t)0x5a7, (q15_t)0x5a1, (q15_t)0x59b, (q15_t)0x594, (q15_t)0x58e, (q15_t)0x588, (q15_t)0x582, + (q15_t)0x57b, (q15_t)0x575, (q15_t)0x56f, (q15_t)0x569, (q15_t)0x562, (q15_t)0x55c, (q15_t)0x556, (q15_t)0x54f, + (q15_t)0x549, (q15_t)0x543, (q15_t)0x53d, (q15_t)0x536, (q15_t)0x530, (q15_t)0x52a, (q15_t)0x523, (q15_t)0x51d, + (q15_t)0x517, (q15_t)0x511, (q15_t)0x50a, (q15_t)0x504, (q15_t)0x4fe, (q15_t)0x4f8, (q15_t)0x4f1, (q15_t)0x4eb, + (q15_t)0x4e5, (q15_t)0x4de, (q15_t)0x4d8, (q15_t)0x4d2, (q15_t)0x4cc, (q15_t)0x4c5, (q15_t)0x4bf, (q15_t)0x4b9, + (q15_t)0x4b2, (q15_t)0x4ac, (q15_t)0x4a6, (q15_t)0x4a0, (q15_t)0x499, (q15_t)0x493, (q15_t)0x48d, (q15_t)0x487, + (q15_t)0x480, (q15_t)0x47a, (q15_t)0x474, (q15_t)0x46d, (q15_t)0x467, (q15_t)0x461, (q15_t)0x45b, (q15_t)0x454, + (q15_t)0x44e, (q15_t)0x448, (q15_t)0x441, (q15_t)0x43b, (q15_t)0x435, (q15_t)0x42f, (q15_t)0x428, (q15_t)0x422, + (q15_t)0x41c, (q15_t)0x415, (q15_t)0x40f, (q15_t)0x409, (q15_t)0x403, (q15_t)0x3fc, (q15_t)0x3f6, (q15_t)0x3f0, + (q15_t)0x3ea, (q15_t)0x3e3, (q15_t)0x3dd, (q15_t)0x3d7, (q15_t)0x3d0, (q15_t)0x3ca, (q15_t)0x3c4, (q15_t)0x3be, + (q15_t)0x3b7, (q15_t)0x3b1, (q15_t)0x3ab, (q15_t)0x3a4, (q15_t)0x39e, (q15_t)0x398, (q15_t)0x392, (q15_t)0x38b, + (q15_t)0x385, (q15_t)0x37f, (q15_t)0x378, (q15_t)0x372, (q15_t)0x36c, (q15_t)0x366, (q15_t)0x35f, (q15_t)0x359, + (q15_t)0x353, (q15_t)0x34c, (q15_t)0x346, (q15_t)0x340, (q15_t)0x33a, (q15_t)0x333, (q15_t)0x32d, (q15_t)0x327, + (q15_t)0x321, (q15_t)0x31a, (q15_t)0x314, (q15_t)0x30e, (q15_t)0x307, (q15_t)0x301, (q15_t)0x2fb, (q15_t)0x2f5, + (q15_t)0x2ee, (q15_t)0x2e8, (q15_t)0x2e2, (q15_t)0x2db, (q15_t)0x2d5, (q15_t)0x2cf, (q15_t)0x2c9, (q15_t)0x2c2, + (q15_t)0x2bc, (q15_t)0x2b6, (q15_t)0x2af, (q15_t)0x2a9, (q15_t)0x2a3, (q15_t)0x29d, (q15_t)0x296, (q15_t)0x290, + (q15_t)0x28a, (q15_t)0x283, (q15_t)0x27d, (q15_t)0x277, (q15_t)0x271, (q15_t)0x26a, (q15_t)0x264, (q15_t)0x25e, + (q15_t)0x258, (q15_t)0x251, (q15_t)0x24b, (q15_t)0x245, (q15_t)0x23e, (q15_t)0x238, (q15_t)0x232, (q15_t)0x22c, + (q15_t)0x225, (q15_t)0x21f, (q15_t)0x219, (q15_t)0x212, (q15_t)0x20c, (q15_t)0x206, (q15_t)0x200, (q15_t)0x1f9, + (q15_t)0x1f3, (q15_t)0x1ed, (q15_t)0x1e6, (q15_t)0x1e0, (q15_t)0x1da, (q15_t)0x1d4, (q15_t)0x1cd, (q15_t)0x1c7, + (q15_t)0x1c1, (q15_t)0x1ba, (q15_t)0x1b4, (q15_t)0x1ae, (q15_t)0x1a8, (q15_t)0x1a1, (q15_t)0x19b, (q15_t)0x195, + (q15_t)0x18e, (q15_t)0x188, (q15_t)0x182, (q15_t)0x17c, (q15_t)0x175, (q15_t)0x16f, (q15_t)0x169, (q15_t)0x162, + (q15_t)0x15c, (q15_t)0x156, (q15_t)0x150, (q15_t)0x149, (q15_t)0x143, (q15_t)0x13d, (q15_t)0x137, (q15_t)0x130, + (q15_t)0x12a, (q15_t)0x124, (q15_t)0x11d, (q15_t)0x117, (q15_t)0x111, (q15_t)0x10b, (q15_t)0x104, (q15_t)0xfe, + (q15_t)0xf8, (q15_t)0xf1, (q15_t)0xeb, (q15_t)0xe5, (q15_t)0xdf, (q15_t)0xd8, (q15_t)0xd2, (q15_t)0xcc, + (q15_t)0xc5, (q15_t)0xbf, (q15_t)0xb9, (q15_t)0xb3, (q15_t)0xac, (q15_t)0xa6, (q15_t)0xa0, (q15_t)0x99, + (q15_t)0x93, (q15_t)0x8d, (q15_t)0x87, (q15_t)0x80, (q15_t)0x7a, (q15_t)0x74, (q15_t)0x6d, (q15_t)0x67, + (q15_t)0x61, (q15_t)0x5b, (q15_t)0x54, (q15_t)0x4e, (q15_t)0x48, (q15_t)0x41, (q15_t)0x3b, (q15_t)0x35, + (q15_t)0x2f, (q15_t)0x28, (q15_t)0x22, (q15_t)0x1c, (q15_t)0x15, (q15_t)0xf, (q15_t)0x9, (q15_t)0x3 +}; + #endif + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    weights[(2*i)]   =  cos(i*c);
+    weights[(2*i)+1] = -sin(i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + Convert the output to q31 format by multiplying with 2^31 and saturated if required. + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + +/** + @par + cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    cos_factors[i] = 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) + @par + Then converted to q31 format by multiplying with 2^31 and saturated if required. +*/ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + const q31_t WeightsQ31_128[256] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f872bf3, (q31_t)0xf50497fb, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7dd6668f, (q31_t)0xe8922622, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7c894bde, (q31_t)0xe26cb01b, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7aef6323, (q31_t)0xdc597781, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x76d94989, (q31_t)0xd078ad9e, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x719e2cd2, (q31_t)0xc50d1149, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6b4af279, (q31_t)0xba32ca71, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x67bd0fbd, (q31_t)0xb5049368, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x63ef3290, (q31_t)0xb0049ab3, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x571deefa, (q31_t)0xa2386284, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x5269126e, (q31_t)0x9e0effc1, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4d8162c4, (q31_t)0x9a22042d, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4869e665, (q31_t)0x9673db94, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4325c135, (q31_t)0x9306cb04, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3db832a6, (q31_t)0x8fdcef66, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x382493b0, (q31_t)0x8cf83c30, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2c98fbba, (q31_t)0x88054677, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x26a82186, (q31_t)0x85fa1153, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x209f701c, (q31_t)0x843a1d70, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1a82a026, (q31_t)0x82c67f14, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x145576b1, (q31_t)0x81a01b6d, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x0fab272b, (q31_t)0x80f66e3c, (q31_t)0x0e1bc2e4, (q31_t)0x80c7a80a, + (q31_t)0x0c8bd35e, (q31_t)0x809dc971, (q31_t)0x0afb6805, (q31_t)0x8078d40d, (q31_t)0x096a9049, (q31_t)0x8058c94c, (q31_t)0x07d95b9e, (q31_t)0x803daa6a, + (q31_t)0x0647d97c, (q31_t)0x80277872, (q31_t)0x04b6195d, (q31_t)0x80163440, (q31_t)0x03242abf, (q31_t)0x8009de7e, (q31_t)0x01921d20, (q31_t)0x800277a6 +}; + const q31_t cos_factorsQ31_128[128] = { + (q31_t)0x7fff6216, (q31_t)0x7ffa72d1, (q31_t)0x7ff09478, (q31_t)0x7fe1c76b, (q31_t)0x7fce0c3e, (q31_t)0x7fb563b3, + (q31_t)0x7f97cebd, (q31_t)0x7f754e80, + (q31_t)0x7f4de451, (q31_t)0x7f2191b4, (q31_t)0x7ef05860, (q31_t)0x7eba3a39, (q31_t)0x7e7f3957, (q31_t)0x7e3f57ff, + (q31_t)0x7dfa98a8, (q31_t)0x7db0fdf8, + (q31_t)0x7d628ac6, (q31_t)0x7d0f4218, (q31_t)0x7cb72724, (q31_t)0x7c5a3d50, (q31_t)0x7bf88830, (q31_t)0x7b920b89, + (q31_t)0x7b26cb4f, (q31_t)0x7ab6cba4, + (q31_t)0x7a4210d8, (q31_t)0x79c89f6e, (q31_t)0x794a7c12, (q31_t)0x78c7aba2, (q31_t)0x78403329, (q31_t)0x77b417df, + (q31_t)0x77235f2d, (q31_t)0x768e0ea6, + (q31_t)0x75f42c0b, (q31_t)0x7555bd4c, (q31_t)0x74b2c884, (q31_t)0x740b53fb, (q31_t)0x735f6626, (q31_t)0x72af05a7, + (q31_t)0x71fa3949, (q31_t)0x71410805, + (q31_t)0x708378ff, (q31_t)0x6fc19385, (q31_t)0x6efb5f12, (q31_t)0x6e30e34a, (q31_t)0x6d6227fa, (q31_t)0x6c8f351c, + (q31_t)0x6bb812d1, (q31_t)0x6adcc964, + (q31_t)0x69fd614a, (q31_t)0x6919e320, (q31_t)0x683257ab, (q31_t)0x6746c7d8, (q31_t)0x66573cbb, (q31_t)0x6563bf92, + (q31_t)0x646c59bf, (q31_t)0x637114cc, + (q31_t)0x6271fa69, (q31_t)0x616f146c, (q31_t)0x60686ccf, (q31_t)0x5f5e0db3, (q31_t)0x5e50015d, (q31_t)0x5d3e5237, + (q31_t)0x5c290acc, (q31_t)0x5b1035cf, + (q31_t)0x59f3de12, (q31_t)0x58d40e8c, (q31_t)0x57b0d256, (q31_t)0x568a34a9, (q31_t)0x556040e2, (q31_t)0x5433027d, + (q31_t)0x53028518, (q31_t)0x51ced46e, + (q31_t)0x5097fc5e, (q31_t)0x4f5e08e3, (q31_t)0x4e210617, (q31_t)0x4ce10034, (q31_t)0x4b9e0390, (q31_t)0x4a581c9e, + (q31_t)0x490f57ee, (q31_t)0x47c3c22f, + (q31_t)0x46756828, (q31_t)0x452456bd, (q31_t)0x43d09aed, (q31_t)0x427a41d0, (q31_t)0x4121589b, (q31_t)0x3fc5ec98, + (q31_t)0x3e680b2c, (q31_t)0x3d07c1d6, + (q31_t)0x3ba51e29, (q31_t)0x3a402dd2, (q31_t)0x38d8fe93, (q31_t)0x376f9e46, (q31_t)0x36041ad9, (q31_t)0x34968250, + (q31_t)0x3326e2c3, (q31_t)0x31b54a5e, + (q31_t)0x3041c761, (q31_t)0x2ecc681e, (q31_t)0x2d553afc, (q31_t)0x2bdc4e6f, (q31_t)0x2a61b101, (q31_t)0x28e5714b, + (q31_t)0x27679df4, (q31_t)0x25e845b6, + (q31_t)0x24677758, (q31_t)0x22e541af, (q31_t)0x2161b3a0, (q31_t)0x1fdcdc1b, (q31_t)0x1e56ca1e, (q31_t)0x1ccf8cb3, + (q31_t)0x1b4732ef, (q31_t)0x19bdcbf3, + (q31_t)0x183366e9, (q31_t)0x16a81305, (q31_t)0x151bdf86, (q31_t)0x138edbb1, (q31_t)0x120116d5, (q31_t)0x1072a048, + (q31_t)0xee38766, (q31_t)0xd53db92, + (q31_t)0xbc3ac35, (q31_t)0xa3308bd, (q31_t)0x8a2009a, (q31_t)0x710a345, (q31_t)0x57f0035, (q31_t)0x3ed26e6, (q31_t)0x25b26d7, + (q31_t)0xc90f88 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + const q31_t WeightsQ31_512[1024] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff871a2, (q31_t)0xfd40565c, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fed5791, (q31_t)0xfbae5e89, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fc85854, (q31_t)0xf88afe42, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f434563, (q31_t)0xf2482c8a, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7ee34636, (q31_t)0xef29b243, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7de8a670, (q31_t)0xe8f50273, + (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5, + (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb, + (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3, + (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c71eaf9, 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(q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59ac3cfd, (q31_t)0xa4a94043, + (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x588b9140, (q31_t)0xa3914da8, + (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x57677b9d, (q31_t)0xa27ceb4f, + (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x56d42c99, (q31_t)0xa1f41392, (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x56400758, (q31_t)0xa16c23e1, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x55ab0d46, (q31_t)0xa0e51d8c, (q31_t)0x556040e2, (q31_t)0xa0a1f24d, (q31_t)0x55153fd4, (q31_t)0xa05f01e1, + (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x547ea073, (q31_t)0x9fd9d22a, (q31_t)0x5433027d, (q31_t)0x9f979331, (q31_t)0x53e73097, (q31_t)0x9f558fb0, + (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x534ef1b5, (q31_t)0x9ed23bb9, (q31_t)0x53028518, (q31_t)0x9e90eb94, (q31_t)0x52b5e546, (q31_t)0x9e4fd78a, + (q31_t)0x5269126e, (q31_t)0x9e0effc1, (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x518169a5, (q31_t)0x9d4de385, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x5049c999, (q31_t)0x9c4fbd93, + (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f0f1126, (q31_t)0x9b556f81, + (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, + (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4c9087b1, (q31_t)0x996c816f, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b4ccf4d, (q31_t)0x987df449, + (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a062fbd, (q31_t)0x979364b5, + (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x48bcb599, (q31_t)0x96acdbbe, + (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47706d93, (q31_t)0x95ca6247, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x4621647d, (q31_t)0x94ec010b, + (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x44cfa740, (q31_t)0x9411c09e, + (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x437b42e1, (q31_t)0x933ba968, + (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x42244481, (q31_t)0x9269c3ac, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x40cab958, (q31_t)0x919c1781, + (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, + (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e10320d, (q31_t)0x900d8b69, + (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b4c18ba, (q31_t)0x8e904298, + (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x39e6975e, (q31_t)0x8dd829e4, + (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x387eda8e, (q31_t)0x8d2477d8, + (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3714f02a, (q31_t)0x8c753362, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36041ad9, (q31_t)0x8bf4ac05, (q31_t)0x35a8e625, (q31_t)0x8bca6343, + (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x34f219a8, (q31_t)0x8b76a8e4, (q31_t)0x34968250, (q31_t)0x8b4d377c, (q31_t)0x343aca87, (q31_t)0x8b240e11, + (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x3382fa88, (q31_t)0x8ad29394, (q31_t)0x3326e2c3, (q31_t)0x8aaa42b4, (q31_t)0x32caab6f, (q31_t)0x8a823a36, + (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, (q31_t)0x3211df04, (q31_t)0x8a3302be, (q31_t)0x31b54a5e, (q31_t)0x8a0bd3f5, (q31_t)0x3158970e, (q31_t)0x89e4edef, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c, + (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2e6ec792, (q31_t)0x88b80432, + (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2cf72939, (q31_t)0x88287256, + (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2b7dcf17, (q31_t)0x879d7f41, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a02c7b8, (q31_t)0x8717304e, + (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x288621b9, (q31_t)0x86958aac, + (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x2707ebc7, (q31_t)0x86189359, + (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x2588349d, (q31_t)0x85a04f28, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x24070b08, (q31_t)0x852cc2bb, + (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22847de0, (q31_t)0x84bdf286, + (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x21009c0c, (q31_t)0x8453e2cf, + (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1df5163f, (q31_t)0x838e1507, + (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1c6d9053, (q31_t)0x83325e97, + (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, + (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x195b49ea, (q31_t)0x8289644b, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x16451a83, (q31_t)0x81f3c2d7, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x132b7bf9, (q31_t)0x8171914e, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x119d8941, (q31_t)0x8137c8e6, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, + (q31_t)0x0fab272b, (q31_t)0x80f66e3c, (q31_t)0x0f475bff, (q31_t)0x80ea4712, (q31_t)0x0ee38766, (q31_t)0x80de6e4c, (q31_t)0x0e7fa99e, (q31_t)0x80d2e3f2, + (q31_t)0x0e1bc2e4, (q31_t)0x80c7a80a, (q31_t)0x0db7d376, (q31_t)0x80bcba9d, (q31_t)0x0d53db92, (q31_t)0x80b21baf, (q31_t)0x0cefdb76, (q31_t)0x80a7cb49, + (q31_t)0x0c8bd35e, (q31_t)0x809dc971, (q31_t)0x0c27c389, (q31_t)0x8094162c, (q31_t)0x0bc3ac35, (q31_t)0x808ab180, (q31_t)0x0b5f8d9f, (q31_t)0x80819b74, + (q31_t)0x0afb6805, (q31_t)0x8078d40d, (q31_t)0x0a973ba5, (q31_t)0x80705b50, (q31_t)0x0a3308bd, (q31_t)0x80683143, (q31_t)0x09cecf89, (q31_t)0x806055eb, + (q31_t)0x096a9049, (q31_t)0x8058c94c, (q31_t)0x09064b3a, (q31_t)0x80518b6b, (q31_t)0x08a2009a, (q31_t)0x804a9c4d, (q31_t)0x083db0a7, (q31_t)0x8043fbf6, + (q31_t)0x07d95b9e, (q31_t)0x803daa6a, (q31_t)0x077501be, (q31_t)0x8037a7ac, (q31_t)0x0710a345, (q31_t)0x8031f3c2, (q31_t)0x06ac406f, (q31_t)0x802c8ead, + (q31_t)0x0647d97c, (q31_t)0x80277872, (q31_t)0x05e36ea9, (q31_t)0x8022b114, (q31_t)0x057f0035, (q31_t)0x801e3895, (q31_t)0x051a8e5c, (q31_t)0x801a0ef8, + (q31_t)0x04b6195d, (q31_t)0x80163440, (q31_t)0x0451a177, (q31_t)0x8012a86f, (q31_t)0x03ed26e6, (q31_t)0x800f6b88, (q31_t)0x0388a9ea, (q31_t)0x800c7d8c, + (q31_t)0x03242abf, (q31_t)0x8009de7e, (q31_t)0x02bfa9a4, (q31_t)0x80078e5e, (q31_t)0x025b26d7, (q31_t)0x80058d2f, (q31_t)0x01f6a297, (q31_t)0x8003daf1, + (q31_t)0x01921d20, (q31_t)0x800277a6, (q31_t)0x012d96b1, (q31_t)0x8001634e, (q31_t)0x00c90f88, (q31_t)0x80009dea, (q31_t)0x006487e3, (q31_t)0x8000277a +}; + const q31_t cos_factorsQ31_512[512] = { + (q31_t)0x7ffff621, (q31_t)0x7fffa72c, (q31_t)0x7fff0943, (q31_t)0x7ffe1c65, (q31_t)0x7ffce093, (q31_t)0x7ffb55ce, + (q31_t)0x7ff97c18, (q31_t)0x7ff75370, + (q31_t)0x7ff4dbd9, (q31_t)0x7ff21553, (q31_t)0x7feeffe1, (q31_t)0x7feb9b85, (q31_t)0x7fe7e841, (q31_t)0x7fe3e616, + (q31_t)0x7fdf9508, (q31_t)0x7fdaf519, + (q31_t)0x7fd6064c, (q31_t)0x7fd0c8a3, (q31_t)0x7fcb3c23, (q31_t)0x7fc560cf, (q31_t)0x7fbf36aa, (q31_t)0x7fb8bdb8, + (q31_t)0x7fb1f5fc, (q31_t)0x7faadf7c, + (q31_t)0x7fa37a3c, (q31_t)0x7f9bc640, (q31_t)0x7f93c38c, (q31_t)0x7f8b7227, (q31_t)0x7f82d214, (q31_t)0x7f79e35a, + (q31_t)0x7f70a5fe, (q31_t)0x7f671a05, + (q31_t)0x7f5d3f75, (q31_t)0x7f531655, (q31_t)0x7f489eaa, (q31_t)0x7f3dd87c, (q31_t)0x7f32c3d1, (q31_t)0x7f2760af, + (q31_t)0x7f1baf1e, (q31_t)0x7f0faf25, + (q31_t)0x7f0360cb, (q31_t)0x7ef6c418, (q31_t)0x7ee9d914, (q31_t)0x7edc9fc6, (q31_t)0x7ecf1837, (q31_t)0x7ec14270, + (q31_t)0x7eb31e78, (q31_t)0x7ea4ac58, + (q31_t)0x7e95ec1a, (q31_t)0x7e86ddc6, (q31_t)0x7e778166, (q31_t)0x7e67d703, (q31_t)0x7e57dea7, (q31_t)0x7e47985b, + (q31_t)0x7e37042a, (q31_t)0x7e26221f, + (q31_t)0x7e14f242, (q31_t)0x7e0374a0, (q31_t)0x7df1a942, (q31_t)0x7ddf9034, (q31_t)0x7dcd2981, (q31_t)0x7dba7534, + (q31_t)0x7da77359, (q31_t)0x7d9423fc, + (q31_t)0x7d808728, (q31_t)0x7d6c9ce9, (q31_t)0x7d58654d, (q31_t)0x7d43e05e, (q31_t)0x7d2f0e2b, (q31_t)0x7d19eebf, + (q31_t)0x7d048228, (q31_t)0x7ceec873, + (q31_t)0x7cd8c1ae, (q31_t)0x7cc26de5, (q31_t)0x7cabcd28, (q31_t)0x7c94df83, (q31_t)0x7c7da505, (q31_t)0x7c661dbc, + (q31_t)0x7c4e49b7, (q31_t)0x7c362904, + (q31_t)0x7c1dbbb3, (q31_t)0x7c0501d2, (q31_t)0x7bebfb70, (q31_t)0x7bd2a89e, (q31_t)0x7bb9096b, (q31_t)0x7b9f1de6, + (q31_t)0x7b84e61f, (q31_t)0x7b6a6227, + (q31_t)0x7b4f920e, (q31_t)0x7b3475e5, (q31_t)0x7b190dbc, (q31_t)0x7afd59a4, (q31_t)0x7ae159ae, (q31_t)0x7ac50dec, + (q31_t)0x7aa8766f, (q31_t)0x7a8b9348, + (q31_t)0x7a6e648a, (q31_t)0x7a50ea47, (q31_t)0x7a332490, (q31_t)0x7a151378, (q31_t)0x79f6b711, (q31_t)0x79d80f6f, + (q31_t)0x79b91ca4, (q31_t)0x7999dec4, + (q31_t)0x797a55e0, (q31_t)0x795a820e, (q31_t)0x793a6361, (q31_t)0x7919f9ec, (q31_t)0x78f945c3, (q31_t)0x78d846fb, + (q31_t)0x78b6fda8, (q31_t)0x789569df, + (q31_t)0x78738bb3, (q31_t)0x7851633b, (q31_t)0x782ef08b, (q31_t)0x780c33b8, (q31_t)0x77e92cd9, (q31_t)0x77c5dc01, + (q31_t)0x77a24148, (q31_t)0x777e5cc3, + (q31_t)0x775a2e89, (q31_t)0x7735b6af, (q31_t)0x7710f54c, (q31_t)0x76ebea77, (q31_t)0x76c69647, (q31_t)0x76a0f8d2, + (q31_t)0x767b1231, (q31_t)0x7654e279, + (q31_t)0x762e69c4, (q31_t)0x7607a828, (q31_t)0x75e09dbd, (q31_t)0x75b94a9c, (q31_t)0x7591aedd, (q31_t)0x7569ca99, + (q31_t)0x75419de7, (q31_t)0x751928e0, + (q31_t)0x74f06b9e, (q31_t)0x74c7663a, (q31_t)0x749e18cd, (q31_t)0x74748371, (q31_t)0x744aa63f, (q31_t)0x74208150, + (q31_t)0x73f614c0, (q31_t)0x73cb60a8, + (q31_t)0x73a06522, (q31_t)0x73752249, (q31_t)0x73499838, (q31_t)0x731dc70a, (q31_t)0x72f1aed9, (q31_t)0x72c54fc1, + (q31_t)0x7298a9dd, (q31_t)0x726bbd48, + (q31_t)0x723e8a20, (q31_t)0x7211107e, (q31_t)0x71e35080, (q31_t)0x71b54a41, (q31_t)0x7186fdde, (q31_t)0x71586b74, + (q31_t)0x7129931f, (q31_t)0x70fa74fc, + (q31_t)0x70cb1128, (q31_t)0x709b67c0, (q31_t)0x706b78e3, (q31_t)0x703b44ad, (q31_t)0x700acb3c, (q31_t)0x6fda0cae, + (q31_t)0x6fa90921, (q31_t)0x6f77c0b3, + (q31_t)0x6f463383, (q31_t)0x6f1461b0, (q31_t)0x6ee24b57, (q31_t)0x6eaff099, (q31_t)0x6e7d5193, (q31_t)0x6e4a6e66, + (q31_t)0x6e174730, (q31_t)0x6de3dc11, + (q31_t)0x6db02d29, (q31_t)0x6d7c3a98, (q31_t)0x6d48047e, (q31_t)0x6d138afb, (q31_t)0x6cdece2f, (q31_t)0x6ca9ce3b, + (q31_t)0x6c748b3f, (q31_t)0x6c3f055d, + (q31_t)0x6c093cb6, (q31_t)0x6bd3316a, (q31_t)0x6b9ce39b, (q31_t)0x6b66536b, (q31_t)0x6b2f80fb, (q31_t)0x6af86c6c, + (q31_t)0x6ac115e2, (q31_t)0x6a897d7d, + (q31_t)0x6a51a361, (q31_t)0x6a1987b0, (q31_t)0x69e12a8c, (q31_t)0x69a88c19, (q31_t)0x696fac78, (q31_t)0x69368bce, + (q31_t)0x68fd2a3d, (q31_t)0x68c387e9, + (q31_t)0x6889a4f6, (q31_t)0x684f8186, (q31_t)0x68151dbe, (q31_t)0x67da79c3, (q31_t)0x679f95b7, (q31_t)0x676471c0, + (q31_t)0x67290e02, (q31_t)0x66ed6aa1, + (q31_t)0x66b187c3, (q31_t)0x6675658c, (q31_t)0x66390422, (q31_t)0x65fc63a9, (q31_t)0x65bf8447, (q31_t)0x65826622, + (q31_t)0x6545095f, (q31_t)0x65076e25, + (q31_t)0x64c99498, (q31_t)0x648b7ce0, (q31_t)0x644d2722, (q31_t)0x640e9386, (q31_t)0x63cfc231, (q31_t)0x6390b34a, + (q31_t)0x635166f9, (q31_t)0x6311dd64, + (q31_t)0x62d216b3, (q31_t)0x6292130c, (q31_t)0x6251d298, (q31_t)0x6211557e, (q31_t)0x61d09be5, (q31_t)0x618fa5f7, + (q31_t)0x614e73da, (q31_t)0x610d05b7, + (q31_t)0x60cb5bb7, (q31_t)0x60897601, (q31_t)0x604754bf, (q31_t)0x6004f819, (q31_t)0x5fc26038, (q31_t)0x5f7f8d46, + (q31_t)0x5f3c7f6b, (q31_t)0x5ef936d1, + (q31_t)0x5eb5b3a2, (q31_t)0x5e71f606, (q31_t)0x5e2dfe29, (q31_t)0x5de9cc33, (q31_t)0x5da5604f, (q31_t)0x5d60baa7, + (q31_t)0x5d1bdb65, (q31_t)0x5cd6c2b5, + (q31_t)0x5c9170bf, (q31_t)0x5c4be5b0, (q31_t)0x5c0621b2, (q31_t)0x5bc024f0, (q31_t)0x5b79ef96, (q31_t)0x5b3381ce, + (q31_t)0x5aecdbc5, (q31_t)0x5aa5fda5, + (q31_t)0x5a5ee79a, (q31_t)0x5a1799d1, (q31_t)0x59d01475, (q31_t)0x598857b2, (q31_t)0x594063b5, (q31_t)0x58f838a9, + (q31_t)0x58afd6bd, (q31_t)0x58673e1b, + (q31_t)0x581e6ef1, (q31_t)0x57d5696d, (q31_t)0x578c2dba, (q31_t)0x5742bc06, (q31_t)0x56f9147e, (q31_t)0x56af3750, + (q31_t)0x566524aa, (q31_t)0x561adcb9, + (q31_t)0x55d05faa, (q31_t)0x5585adad, (q31_t)0x553ac6ee, (q31_t)0x54efab9c, (q31_t)0x54a45be6, (q31_t)0x5458d7f9, + (q31_t)0x540d2005, (q31_t)0x53c13439, + (q31_t)0x537514c2, (q31_t)0x5328c1d0, (q31_t)0x52dc3b92, (q31_t)0x528f8238, (q31_t)0x524295f0, (q31_t)0x51f576ea, + (q31_t)0x51a82555, (q31_t)0x515aa162, + (q31_t)0x510ceb40, (q31_t)0x50bf031f, (q31_t)0x5070e92f, (q31_t)0x50229da1, (q31_t)0x4fd420a4, (q31_t)0x4f857269, + (q31_t)0x4f369320, (q31_t)0x4ee782fb, + (q31_t)0x4e984229, (q31_t)0x4e48d0dd, (q31_t)0x4df92f46, (q31_t)0x4da95d96, (q31_t)0x4d595bfe, (q31_t)0x4d092ab0, + (q31_t)0x4cb8c9dd, (q31_t)0x4c6839b7, + (q31_t)0x4c177a6e, (q31_t)0x4bc68c36, (q31_t)0x4b756f40, (q31_t)0x4b2423be, (q31_t)0x4ad2a9e2, (q31_t)0x4a8101de, + (q31_t)0x4a2f2be6, (q31_t)0x49dd282a, + (q31_t)0x498af6df, (q31_t)0x49389836, (q31_t)0x48e60c62, (q31_t)0x48935397, (q31_t)0x48406e08, (q31_t)0x47ed5be6, + (q31_t)0x479a1d67, (q31_t)0x4746b2bc, + (q31_t)0x46f31c1a, (q31_t)0x469f59b4, (q31_t)0x464b6bbe, (q31_t)0x45f7526b, (q31_t)0x45a30df0, (q31_t)0x454e9e80, + (q31_t)0x44fa0450, (q31_t)0x44a53f93, + (q31_t)0x4450507e, (q31_t)0x43fb3746, (q31_t)0x43a5f41e, (q31_t)0x4350873c, (q31_t)0x42faf0d4, (q31_t)0x42a5311b, + (q31_t)0x424f4845, (q31_t)0x41f93689, + (q31_t)0x41a2fc1a, (q31_t)0x414c992f, (q31_t)0x40f60dfb, (q31_t)0x409f5ab6, (q31_t)0x40487f94, (q31_t)0x3ff17cca, + (q31_t)0x3f9a5290, (q31_t)0x3f430119, + (q31_t)0x3eeb889c, (q31_t)0x3e93e950, (q31_t)0x3e3c2369, (q31_t)0x3de4371f, (q31_t)0x3d8c24a8, (q31_t)0x3d33ec39, + (q31_t)0x3cdb8e09, (q31_t)0x3c830a50, + (q31_t)0x3c2a6142, (q31_t)0x3bd19318, (q31_t)0x3b78a007, (q31_t)0x3b1f8848, (q31_t)0x3ac64c0f, (q31_t)0x3a6ceb96, + (q31_t)0x3a136712, (q31_t)0x39b9bebc, + (q31_t)0x395ff2c9, (q31_t)0x39060373, (q31_t)0x38abf0ef, (q31_t)0x3851bb77, (q31_t)0x37f76341, (q31_t)0x379ce885, + (q31_t)0x37424b7b, (q31_t)0x36e78c5b, + (q31_t)0x368cab5c, (q31_t)0x3631a8b8, (q31_t)0x35d684a6, (q31_t)0x357b3f5d, (q31_t)0x351fd918, (q31_t)0x34c4520d, + (q31_t)0x3468aa76, (q31_t)0x340ce28b, + (q31_t)0x33b0fa84, (q31_t)0x3354f29b, (q31_t)0x32f8cb07, (q31_t)0x329c8402, (q31_t)0x32401dc6, (q31_t)0x31e39889, + (q31_t)0x3186f487, (q31_t)0x312a31f8, + (q31_t)0x30cd5115, (q31_t)0x30705217, (q31_t)0x30133539, (q31_t)0x2fb5fab2, (q31_t)0x2f58a2be, (q31_t)0x2efb2d95, + (q31_t)0x2e9d9b70, (q31_t)0x2e3fec8b, + (q31_t)0x2de2211e, (q31_t)0x2d843964, (q31_t)0x2d263596, (q31_t)0x2cc815ee, (q31_t)0x2c69daa6, (q31_t)0x2c0b83fa, + (q31_t)0x2bad1221, (q31_t)0x2b4e8558, + (q31_t)0x2aefddd8, (q31_t)0x2a911bdc, (q31_t)0x2a323f9e, (q31_t)0x29d34958, (q31_t)0x29743946, (q31_t)0x29150fa1, + (q31_t)0x28b5cca5, (q31_t)0x2856708d, + (q31_t)0x27f6fb92, (q31_t)0x27976df1, (q31_t)0x2737c7e3, (q31_t)0x26d809a5, (q31_t)0x26783370, (q31_t)0x26184581, + (q31_t)0x25b84012, (q31_t)0x2558235f, + (q31_t)0x24f7efa2, (q31_t)0x2497a517, (q31_t)0x243743fa, (q31_t)0x23d6cc87, (q31_t)0x23763ef7, (q31_t)0x23159b88, + (q31_t)0x22b4e274, (q31_t)0x225413f8, + (q31_t)0x21f3304f, (q31_t)0x219237b5, (q31_t)0x21312a65, (q31_t)0x20d0089c, (q31_t)0x206ed295, (q31_t)0x200d888d, + (q31_t)0x1fac2abf, (q31_t)0x1f4ab968, + (q31_t)0x1ee934c3, (q31_t)0x1e879d0d, (q31_t)0x1e25f282, (q31_t)0x1dc4355e, (q31_t)0x1d6265dd, (q31_t)0x1d00843d, + (q31_t)0x1c9e90b8, (q31_t)0x1c3c8b8c, + (q31_t)0x1bda74f6, (q31_t)0x1b784d30, (q31_t)0x1b161479, (q31_t)0x1ab3cb0d, (q31_t)0x1a517128, (q31_t)0x19ef0707, + (q31_t)0x198c8ce7, (q31_t)0x192a0304, + (q31_t)0x18c7699b, (q31_t)0x1864c0ea, (q31_t)0x1802092c, (q31_t)0x179f429f, (q31_t)0x173c6d80, (q31_t)0x16d98a0c, + (q31_t)0x1676987f, (q31_t)0x16139918, + (q31_t)0x15b08c12, (q31_t)0x154d71aa, (q31_t)0x14ea4a1f, (q31_t)0x148715ae, (q31_t)0x1423d492, (q31_t)0x13c0870a, + (q31_t)0x135d2d53, (q31_t)0x12f9c7aa, + (q31_t)0x1296564d, (q31_t)0x1232d979, (q31_t)0x11cf516a, (q31_t)0x116bbe60, (q31_t)0x11082096, (q31_t)0x10a4784b, + (q31_t)0x1040c5bb, (q31_t)0xfdd0926, + (q31_t)0xf7942c7, (q31_t)0xf1572dc, (q31_t)0xeb199a4, (q31_t)0xe4db75b, (q31_t)0xde9cc40, (q31_t)0xd85d88f, (q31_t)0xd21dc87, + (q31_t)0xcbdd865, + (q31_t)0xc59cc68, (q31_t)0xbf5b8cb, (q31_t)0xb919dcf, (q31_t)0xb2d7baf, (q31_t)0xac952aa, (q31_t)0xa6522fe, (q31_t)0xa00ece8, + (q31_t)0x99cb0a7, + (q31_t)0x9386e78, (q31_t)0x8d42699, (q31_t)0x86fd947, (q31_t)0x80b86c2, (q31_t)0x7a72f45, (q31_t)0x742d311, (q31_t)0x6de7262, + (q31_t)0x67a0d76, + (q31_t)0x615a48b, (q31_t)0x5b137df, (q31_t)0x54cc7b1, (q31_t)0x4e8543e, (q31_t)0x483ddc3, (q31_t)0x41f6480, (q31_t)0x3bae8b2, + (q31_t)0x3566a96, + (q31_t)0x2f1ea6c, (q31_t)0x28d6870, (q31_t)0x228e4e2, (q31_t)0x1c45ffe, (q31_t)0x15fda03, (q31_t)0xfb5330, (q31_t)0x96cbc1, + (q31_t)0x3243f5 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + const q31_t WeightsQ31_2048[4096] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, + (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff8719, (q31_t)0xff501258, + (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, + (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffc8549, (q31_t)0xfe227eac, + (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, + (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, + (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4319d, (q31_t)0xfc9075af, + (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, + (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7feeffe1, (q31_t)0xfbe09b80, (q31_t)0x7fee2e30, (q31_t)0xfbc77cf0, + (q31_t)0x7fed5791, (q31_t)0xfbae5e89, (q31_t)0x7fec7c02, (q31_t)0xfb95404d, (q31_t)0x7feb9b85, (q31_t)0xfb7c223d, (q31_t)0x7feab61a, (q31_t)0xfb630459, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe8dc78, (q31_t)0xfb30c91b, (q31_t)0x7fe7e841, (q31_t)0xfb17abc2, (q31_t)0x7fe6ef1c, (q31_t)0xfafe8e9b, + (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe4ee06, (q31_t)0xfacc54e0, (q31_t)0x7fe3e616, (q31_t)0xfab3384f, (q31_t)0x7fe2d938, (q31_t)0xfa9a1bf3, + (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fe0b0b1, (q31_t)0xfa67e3da, (q31_t)0x7fdf9508, (q31_t)0xfa4ec821, (q31_t)0x7fde7471, (q31_t)0xfa35ac9f, + (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, (q31_t)0x7fdc247a, (q31_t)0xfa037648, (q31_t)0x7fdaf519, (q31_t)0xf9ea5b75, (q31_t)0x7fd9c0ca, (q31_t)0xf9d140de, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd74964, (q31_t)0xf99f0c68, (q31_t)0x7fd6064c, (q31_t)0xf985f28a, (q31_t)0x7fd4be46, (q31_t)0xf96cd8ed, + (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fd21f72, (q31_t)0xf93aa676, (q31_t)0x7fd0c8a3, (q31_t)0xf9218d9e, (q31_t)0x7fcf6ce8, (q31_t)0xf908750a, + (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fcca6a7, (q31_t)0xf8d644b2, (q31_t)0x7fcb3c23, (q31_t)0xf8bd2cef, (q31_t)0x7fc9ccb2, (q31_t)0xf8a41574, + (q31_t)0x7fc85854, (q31_t)0xf88afe42, (q31_t)0x7fc6df08, (q31_t)0xf871e759, (q31_t)0x7fc560cf, (q31_t)0xf858d0bb, (q31_t)0x7fc3dda9, (q31_t)0xf83fba68, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fc0c896, (q31_t)0xf80d8ea9, (q31_t)0x7fbf36aa, (q31_t)0xf7f4793e, (q31_t)0x7fbd9fd0, (q31_t)0xf7db6423, + (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fba6357, (q31_t)0xf7a93ae0, (q31_t)0x7fb8bdb8, (q31_t)0xf79026b9, (q31_t)0x7fb7132b, (q31_t)0xf77712e5, + (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fb3af4e, (q31_t)0xf744ec3b, (q31_t)0x7fb1f5fc, (q31_t)0xf72bd967, (q31_t)0x7fb037bf, (q31_t)0xf712c6ea, + (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, (q31_t)0x7facac7f, (q31_t)0xf6e0a2fa, (q31_t)0x7faadf7c, (q31_t)0xf6c79188, (q31_t)0x7fa90d8e, (q31_t)0xf6ae8071, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7fa55aee, (q31_t)0xf67c5f59, (q31_t)0x7fa37a3c, (q31_t)0xf6634f59, (q31_t)0x7fa1949e, (q31_t)0xf64a3fb8, + (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f9dbaa0, (q31_t)0xf6182196, (q31_t)0x7f9bc640, (q31_t)0xf5ff1318, (q31_t)0x7f99ccf4, (q31_t)0xf5e604fc, + (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f95cb9a, (q31_t)0xf5b3e9f0, (q31_t)0x7f93c38c, (q31_t)0xf59add02, (q31_t)0x7f91b694, (q31_t)0xf581d07b, + (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, (q31_t)0x7f8d8de1, (q31_t)0xf54fb8a4, (q31_t)0x7f8b7227, (q31_t)0xf536ad56, (q31_t)0x7f895182, (q31_t)0xf51da273, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f850179, (q31_t)0xf4eb8def, (q31_t)0x7f82d214, (q31_t)0xf4d28451, (q31_t)0x7f809dc5, (q31_t)0xf4b97b21, + (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f7c2668, (q31_t)0xf4876a10, (q31_t)0x7f79e35a, (q31_t)0xf46e6231, (q31_t)0x7f779b62, (q31_t)0xf4555ac5, + (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f72fcb4, (q31_t)0xf4234d45, (q31_t)0x7f70a5fe, (q31_t)0xf40a4735, (q31_t)0x7f6e4a5e, (q31_t)0xf3f1419a, + (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, (q31_t)0x7f698461, (q31_t)0xf3bf37cb, (q31_t)0x7f671a05, (q31_t)0xf3a63398, (q31_t)0x7f64aabf, (q31_t)0xf38d2fe0, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5fbd77, (q31_t)0xf35b29e0, (q31_t)0x7f5d3f75, (q31_t)0xf342279b, (q31_t)0x7f5abc8a, (q31_t)0xf32925d3, + (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f55a7fa, (q31_t)0xf2f723c1, (q31_t)0x7f531655, (q31_t)0xf2de2379, (q31_t)0x7f507fc7, (q31_t)0xf2c523b2, + (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f4b43f2, (q31_t)0xf29325ad, (q31_t)0x7f489eaa, (q31_t)0xf27a2771, (q31_t)0x7f45f47b, (q31_t)0xf26129ba, + (q31_t)0x7f434563, (q31_t)0xf2482c8a, (q31_t)0x7f409164, (q31_t)0xf22f2fe1, (q31_t)0x7f3dd87c, (q31_t)0xf21633c0, (q31_t)0x7f3b1aad, (q31_t)0xf1fd3829, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f359057, (q31_t)0xf1cb429a, (q31_t)0x7f32c3d1, (q31_t)0xf1b248a5, (q31_t)0x7f2ff263, (q31_t)0xf1994f3d, + (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2a40d2, (q31_t)0xf1675e17, (q31_t)0x7f2760af, (q31_t)0xf14e665c, (q31_t)0x7f247ba5, (q31_t)0xf1356f32, + (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f1ea2dc, (q31_t)0xf1038295, (q31_t)0x7f1baf1e, (q31_t)0xf0ea8d24, (q31_t)0x7f18b679, (q31_t)0xf0d19848, + (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, (q31_t)0x7f12b67c, (q31_t)0xf09fb051, (q31_t)0x7f0faf25, (q31_t)0xf086bd39, (q31_t)0x7f0ca2e7, (q31_t)0xf06dcaba, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7f067bba, (q31_t)0xf03be78a, (q31_t)0x7f0360cb, (q31_t)0xf022f6da, (q31_t)0x7f0040f6, (q31_t)0xf00a06c8, + (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef9f29d, (q31_t)0xefd8287c, (q31_t)0x7ef6c418, (q31_t)0xefbf3a45, (q31_t)0x7ef390ae, (q31_t)0xefa64cae, + (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7eed1b2c, (q31_t)0xef747365, (q31_t)0x7ee9d914, (q31_t)0xef5b87b5, (q31_t)0x7ee69217, (q31_t)0xef429caa, + (q31_t)0x7ee34636, (q31_t)0xef29b243, (q31_t)0x7edff570, (q31_t)0xef10c883, (q31_t)0x7edc9fc6, (q31_t)0xeef7df6a, (q31_t)0x7ed94538, (q31_t)0xeedef6f9, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ed28171, (q31_t)0xeead2813, (q31_t)0x7ecf1837, (q31_t)0xee9441a0, (q31_t)0x7ecbaa1a, (q31_t)0xee7b5bd9, + (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7ec4bf36, (q31_t)0xee499253, (q31_t)0x7ec14270, (q31_t)0xee30ae96, (q31_t)0x7ebdc0c6, (q31_t)0xee17cb88, + (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eb6aeca, (q31_t)0xede60780, (q31_t)0x7eb31e78, (q31_t)0xedcd2687, (q31_t)0x7eaf8943, (q31_t)0xedb44642, + (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, (q31_t)0x7ea85033, (q31_t)0xed8287d7, (q31_t)0x7ea4ac58, (q31_t)0xed69a9b3, (q31_t)0x7ea1039b, (q31_t)0xed50cc46, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e99a37c, (q31_t)0xed1f1396, (q31_t)0x7e95ec1a, (q31_t)0xed063856, (q31_t)0x7e922fd6, (q31_t)0xeced5dd0, + (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e8aa8ac, (q31_t)0xecbbaafb, (q31_t)0x7e86ddc6, (q31_t)0xeca2d2ad, (q31_t)0x7e830dff, (q31_t)0xec89fb1e, + (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e7b5fce, (q31_t)0xec584e41, (q31_t)0x7e778166, (q31_t)0xec3f78f6, (q31_t)0x7e739e1d, (q31_t)0xec26a46d, + (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, (q31_t)0x7e6bc8eb, (q31_t)0xebf4fda8, (q31_t)0x7e67d703, (q31_t)0xebdc2b6e, (q31_t)0x7e63e03b, (q31_t)0xebc359fb, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e5be40c, (q31_t)0xeb91b96c, (q31_t)0x7e57dea7, (q31_t)0xeb78ea52, (q31_t)0x7e53d462, (q31_t)0xeb601c04, + (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e4bb13c, (q31_t)0xeb2e81ca, (q31_t)0x7e47985b, (q31_t)0xeb15b5e1, (q31_t)0x7e437a9c, (q31_t)0xeafceac6, + (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e3b3083, (q31_t)0xeacb56ff, (q31_t)0x7e37042a, (q31_t)0xeab28e56, (q31_t)0x7e32d2f4, (q31_t)0xea99c67e, + (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, (q31_t)0x7e2a61ed, (q31_t)0xea683949, (q31_t)0x7e26221f, (q31_t)0xea4f73ee, (q31_t)0x7e21dd73, (q31_t)0xea36af69, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e194584, (q31_t)0xea0528e5, (q31_t)0x7e14f242, (q31_t)0xe9ec66e8, (q31_t)0x7e109a24, (q31_t)0xe9d3a5c5, + (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7e07db52, (q31_t)0xe9a22610, (q31_t)0x7e0374a0, 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(q31_t)0x17e958ea, (q31_t)0x8240d673, + (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, (q31_t)0x17b7f5a3, (q31_t)0x82377c4c, (q31_t)0x179f429f, (q31_t)0x8232d67f, (q31_t)0x17868eb3, (q31_t)0x822e358b, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x17552422, (q31_t)0x82250232, (q31_t)0x173c6d80, (q31_t)0x82206fcc, (q31_t)0x1723b5f9, (q31_t)0x821be240, + (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16f2443e, (q31_t)0x8212d5b9, (q31_t)0x16d98a0c, (q31_t)0x820e56be, (q31_t)0x16c0cef9, (q31_t)0x8209dc9e, + (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x168f5632, (q31_t)0x8200f6ef, (q31_t)0x1676987f, (q31_t)0x81fc8b60, (q31_t)0x165dd9f0, (q31_t)0x81f824ae, + (q31_t)0x16451a83, (q31_t)0x81f3c2d7, (q31_t)0x162c5a3b, (q31_t)0x81ef65dc, (q31_t)0x16139918, (q31_t)0x81eb0dbe, (q31_t)0x15fad71b, (q31_t)0x81e6ba7c, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x15c95097, (q31_t)0x81de228d, (q31_t)0x15b08c12, (q31_t)0x81d9dde1, (q31_t)0x1597c6b7, (q31_t)0x81d59e13, + (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x15663982, (q31_t)0x81cd2d0c, (q31_t)0x154d71aa, (q31_t)0x81c8fbd6, (q31_t)0x1534a901, (q31_t)0x81c4cf7d, + (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x1503153a, (q31_t)0x81bc8564, (q31_t)0x14ea4a1f, (q31_t)0x81b867a5, (q31_t)0x14d17e36, (q31_t)0x81b44ec4, + (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, (q31_t)0x149fe3fc, (q31_t)0x81ac2b9e, (q31_t)0x148715ae, (q31_t)0x81a82159, (q31_t)0x146e4694, (q31_t)0x81a41bf4, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x143ca605, (q31_t)0x819c1fc5, (q31_t)0x1423d492, (q31_t)0x819828fd, (q31_t)0x140b0258, (q31_t)0x81943715, + (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x13d95b93, (q31_t)0x818c61e3, (q31_t)0x13c0870a, (q31_t)0x81887e9a, (q31_t)0x13a7b1bf, (q31_t)0x8184a032, + (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x137604e2, (q31_t)0x817cf201, (q31_t)0x135d2d53, (q31_t)0x8179223a, (q31_t)0x13445505, (q31_t)0x81755754, + (q31_t)0x132b7bf9, (q31_t)0x8171914e, (q31_t)0x1312a230, (q31_t)0x816dd02a, (q31_t)0x12f9c7aa, (q31_t)0x816a13e6, (q31_t)0x12e0ec6a, (q31_t)0x81665c84, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x12af33ba, (q31_t)0x815efc65, (q31_t)0x1296564d, (q31_t)0x815b53a8, (q31_t)0x127d7829, (q31_t)0x8157afcd, + (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x124bb9be, (q31_t)0x815076bd, (q31_t)0x1232d979, (q31_t)0x814ce188, (q31_t)0x1219f880, (q31_t)0x81495136, + (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x11e83478, (q31_t)0x81423f3a, (q31_t)0x11cf516a, (q31_t)0x813ebd90, (q31_t)0x11b66dad, (q31_t)0x813b40ca, + (q31_t)0x119d8941, (q31_t)0x8137c8e6, (q31_t)0x1184a427, (q31_t)0x813455e6, (q31_t)0x116bbe60, (q31_t)0x8130e7c9, (q31_t)0x1152d7ed, (q31_t)0x812d7e8f, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x11210907, (q31_t)0x8126bac8, (q31_t)0x11082096, (q31_t)0x8123603a, (q31_t)0x10ef377d, (q31_t)0x81200a90, + (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x10bd6356, (q31_t)0x81196de9, (q31_t)0x10a4784b, (q31_t)0x811626ec, (q31_t)0x108b8c9b, (q31_t)0x8112e4d4, + (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x1059b352, (q31_t)0x810c6f52, (q31_t)0x1040c5bb, (q31_t)0x81093be8, (q31_t)0x1027d784, (q31_t)0x81060d63, + (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, (q31_t)0xff5f938, (q31_t)0x80ffbf0a, (q31_t)0xfdd0926, (q31_t)0x80fc9f35, (q31_t)0xfc41876, (q31_t)0x80f98446, + (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xf923546, (q31_t)0x80f35d19, (q31_t)0xf7942c7, (q31_t)0x80f050db, (q31_t)0xf604faf, (q31_t)0x80ed4984, + (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xf2e67b8, (q31_t)0x80e74987, (q31_t)0xf1572dc, (q31_t)0x80e450e2, (q31_t)0xefc7d6b, (q31_t)0x80e15d24, + (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xeca90ce, (q31_t)0x80db845b, (q31_t)0xeb199a4, (q31_t)0x80d89f51, (q31_t)0xe98a1e9, (q31_t)0x80d5bf2e, + (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2, (q31_t)0xe66b0c3, (q31_t)0x80d00d9d, (q31_t)0xe4db75b, (q31_t)0x80cd3c2f, (q31_t)0xe34bd66, (q31_t)0x80ca6fa9, + (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xe02c7d7, (q31_t)0x80c4e553, (q31_t)0xde9cc40, (q31_t)0x80c22784, (q31_t)0xdd0d01f, (q31_t)0x80bf6e9c, + (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xd9ed646, (q31_t)0x80ba0b85, (q31_t)0xd85d88f, (q31_t)0x80b76156, (q31_t)0xd6cda53, (q31_t)0x80b4bc0e, + (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xd3adc4e, (q31_t)0x80af8039, (q31_t)0xd21dc87, (q31_t)0x80ace9ab, (q31_t)0xd08dc3f, (q31_t)0x80aa5806, + (q31_t)0xcefdb76, (q31_t)0x80a7cb49, (q31_t)0xcd6da2d, (q31_t)0x80a54376, (q31_t)0xcbdd865, (q31_t)0x80a2c08b, (q31_t)0xca4d620, (q31_t)0x80a04289, + (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc72d020, (q31_t)0x809b5541, (q31_t)0xc59cc68, (q31_t)0x8098e5fb, (q31_t)0xc40c835, (q31_t)0x80967b9f, + (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xc0ebe66, (q31_t)0x8091b5a2, (q31_t)0xbf5b8cb, (q31_t)0x808f5a02, (q31_t)0xbdcb2bb, (q31_t)0x808d034c, + (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xbaaa53b, (q31_t)0x8088649e, (q31_t)0xb919dcf, (q31_t)0x80861ca6, (q31_t)0xb7895f0, (q31_t)0x8083d998, + (q31_t)0xb5f8d9f, (q31_t)0x80819b74, (q31_t)0xb4684df, (q31_t)0x807f623b, (q31_t)0xb2d7baf, (q31_t)0x807d2dec, (q31_t)0xb147211, (q31_t)0x807afe87, + (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xae25d8d, (q31_t)0x8076ae7e, (q31_t)0xac952aa, (q31_t)0x80748dd9, (q31_t)0xab0475c, (q31_t)0x8072721f, + (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa7e2f85, (q31_t)0x806e496c, (q31_t)0xa6522fe, (q31_t)0x806c3c74, (q31_t)0xa4c1610, (q31_t)0x806a3466, + (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0xa19fb04, (q31_t)0x8066330c, (q31_t)0xa00ece8, (q31_t)0x806439c0, (q31_t)0x9e7de6a, (q31_t)0x80624560, + (q31_t)0x9cecf89, (q31_t)0x806055eb, (q31_t)0x9b5c048, (q31_t)0x805e6b62, (q31_t)0x99cb0a7, (q31_t)0x805c85c4, (q31_t)0x983a0a7, (q31_t)0x805aa512, + (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9517f8f, (q31_t)0x8056f272, (q31_t)0x9386e78, (q31_t)0x80552084, (q31_t)0x91f5d06, (q31_t)0x80535381, + (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x8ed3916, (q31_t)0x804fc841, (q31_t)0x8d42699, (q31_t)0x804e0a04, (q31_t)0x8bb13c5, (q31_t)0x804c50b2, + (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x888ed1b, (q31_t)0x8048ecd5, (q31_t)0x86fd947, (q31_t)0x80474248, (q31_t)0x856c520, (q31_t)0x80459ca9, + (q31_t)0x83db0a7, (q31_t)0x8043fbf6, (q31_t)0x8249bdd, (q31_t)0x80426030, (q31_t)0x80b86c2, (q31_t)0x8040c956, (q31_t)0x7f27157, (q31_t)0x803f376a, + (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x7c04598, (q31_t)0x803c2257, (q31_t)0x7a72f45, (q31_t)0x803a9f31, (q31_t)0x78e18a7, (q31_t)0x803920f8, + (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x75bea8c, (q31_t)0x8036334e, (q31_t)0x742d311, (q31_t)0x8034c3dd, (q31_t)0x729bb4e, (q31_t)0x80335959, + (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x6f78af6, (q31_t)0x80309318, (q31_t)0x6de7262, (q31_t)0x802f375d, (q31_t)0x6c5598a, (q31_t)0x802de08e, + (q31_t)0x6ac406f, (q31_t)0x802c8ead, (q31_t)0x6932713, (q31_t)0x802b41ba, (q31_t)0x67a0d76, (q31_t)0x8029f9b4, (q31_t)0x660f398, (q31_t)0x8028b69c, + (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x62ebf22, (q31_t)0x80263f36, (q31_t)0x615a48b, (q31_t)0x80250ae7, (q31_t)0x5fc89b8, (q31_t)0x8023db86, + (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x5ca5361, (q31_t)0x80218b8f, (q31_t)0x5b137df, (q31_t)0x80206af8, (q31_t)0x5981c26, (q31_t)0x801f4f4f, + (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x565e40d, (q31_t)0x801d26c8, (q31_t)0x54cc7b1, (q31_t)0x801c19ea, (q31_t)0x533ab20, (q31_t)0x801b11fa, + (q31_t)0x51a8e5c, (q31_t)0x801a0ef8, (q31_t)0x5017165, (q31_t)0x801910e4, (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4cf36e5, (q31_t)0x80172388, + (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x46abfb3, (q31_t)0x801383fe, + (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x40645c7, (q31_t)0x8010335c, + (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3a1c960, (q31_t)0x800d31a5, + (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x33d4abb, (q31_t)0x800a7edb, + (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2d8ca16, (q31_t)0x80081b00, + (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x27447b0, (q31_t)0x80060614, + (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x20fc3c6, (q31_t)0x8004401a, + (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1ab3e97, (q31_t)0x8002c912, + (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x146b860, (q31_t)0x8001a0fd, + (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x0fb5330, (q31_t)0x8000f6bd, (q31_t)0xe23160, (q31_t)0x8000c7dc, + (q31_t)0x0c90f88, (q31_t)0x80009dea, (q31_t)0x0afeda8, (q31_t)0x800078e7, (q31_t)0x096cbc1, (q31_t)0x800058d4, (q31_t)0x7da9d4, (q31_t)0x80003daf, + (q31_t)0x06487e3, (q31_t)0x8000277a, (q31_t)0x04b65ee, (q31_t)0x80001635, (q31_t)0x03243f5, (q31_t)0x800009df, (q31_t)0x1921fb, (q31_t)0x80000278 +}; + const q31_t cos_factorsQ31_2048[2048] = { + (q31_t)0x7fffff62, (q31_t)0x7ffffa73, (q31_t)0x7ffff094, (q31_t)0x7fffe1c6, (q31_t)0x7fffce09, (q31_t)0x7fffb55c, + (q31_t)0x7fff97c1, (q31_t)0x7fff7536, + (q31_t)0x7fff4dbb, (q31_t)0x7fff2151, (q31_t)0x7ffeeff8, (q31_t)0x7ffeb9b0, (q31_t)0x7ffe7e79, (q31_t)0x7ffe3e52, + (q31_t)0x7ffdf93c, (q31_t)0x7ffdaf37, + (q31_t)0x7ffd6042, (q31_t)0x7ffd0c5f, (q31_t)0x7ffcb38c, (q31_t)0x7ffc55ca, (q31_t)0x7ffbf319, (q31_t)0x7ffb8b78, + (q31_t)0x7ffb1ee9, (q31_t)0x7ffaad6a, + (q31_t)0x7ffa36fc, (q31_t)0x7ff9bba0, (q31_t)0x7ff93b54, (q31_t)0x7ff8b619, (q31_t)0x7ff82bef, (q31_t)0x7ff79cd6, + (q31_t)0x7ff708ce, (q31_t)0x7ff66fd7, + (q31_t)0x7ff5d1f1, (q31_t)0x7ff52f1d, (q31_t)0x7ff48759, (q31_t)0x7ff3daa6, (q31_t)0x7ff32905, (q31_t)0x7ff27275, + (q31_t)0x7ff1b6f6, (q31_t)0x7ff0f688, + (q31_t)0x7ff0312c, (q31_t)0x7fef66e1, (q31_t)0x7fee97a7, (q31_t)0x7fedc37e, (q31_t)0x7fecea67, (q31_t)0x7fec0c62, + (q31_t)0x7feb296d, (q31_t)0x7fea418b, + (q31_t)0x7fe954ba, (q31_t)0x7fe862fa, (q31_t)0x7fe76c4c, (q31_t)0x7fe670b0, (q31_t)0x7fe57025, (q31_t)0x7fe46aac, + (q31_t)0x7fe36045, (q31_t)0x7fe250ef, + (q31_t)0x7fe13cac, (q31_t)0x7fe0237a, (q31_t)0x7fdf055a, (q31_t)0x7fdde24d, (q31_t)0x7fdcba51, (q31_t)0x7fdb8d67, + (q31_t)0x7fda5b8f, (q31_t)0x7fd924ca, + (q31_t)0x7fd7e917, (q31_t)0x7fd6a875, (q31_t)0x7fd562e7, (q31_t)0x7fd4186a, (q31_t)0x7fd2c900, (q31_t)0x7fd174a8, + (q31_t)0x7fd01b63, (q31_t)0x7fcebd31, + (q31_t)0x7fcd5a11, (q31_t)0x7fcbf203, (q31_t)0x7fca8508, (q31_t)0x7fc91320, (q31_t)0x7fc79c4b, (q31_t)0x7fc62089, + (q31_t)0x7fc49fda, (q31_t)0x7fc31a3d, + (q31_t)0x7fc18fb4, (q31_t)0x7fc0003e, (q31_t)0x7fbe6bdb, (q31_t)0x7fbcd28b, (q31_t)0x7fbb344e, (q31_t)0x7fb99125, + (q31_t)0x7fb7e90f, (q31_t)0x7fb63c0d, + (q31_t)0x7fb48a1e, (q31_t)0x7fb2d343, (q31_t)0x7fb1177b, (q31_t)0x7faf56c7, (q31_t)0x7fad9127, (q31_t)0x7fabc69b, + (q31_t)0x7fa9f723, (q31_t)0x7fa822bf, + (q31_t)0x7fa6496e, (q31_t)0x7fa46b32, (q31_t)0x7fa2880b, (q31_t)0x7fa09ff7, (q31_t)0x7f9eb2f8, (q31_t)0x7f9cc10d, + (q31_t)0x7f9aca37, (q31_t)0x7f98ce76, + (q31_t)0x7f96cdc9, (q31_t)0x7f94c831, (q31_t)0x7f92bdad, (q31_t)0x7f90ae3f, (q31_t)0x7f8e99e6, (q31_t)0x7f8c80a1, + (q31_t)0x7f8a6272, (q31_t)0x7f883f58, + (q31_t)0x7f861753, (q31_t)0x7f83ea64, (q31_t)0x7f81b88a, (q31_t)0x7f7f81c6, (q31_t)0x7f7d4617, (q31_t)0x7f7b057e, + (q31_t)0x7f78bffb, (q31_t)0x7f76758e, + (q31_t)0x7f742637, (q31_t)0x7f71d1f6, (q31_t)0x7f6f78cb, (q31_t)0x7f6d1ab6, (q31_t)0x7f6ab7b8, (q31_t)0x7f684fd0, + (q31_t)0x7f65e2ff, (q31_t)0x7f637144, + (q31_t)0x7f60faa0, (q31_t)0x7f5e7f13, (q31_t)0x7f5bfe9d, (q31_t)0x7f59793e, (q31_t)0x7f56eef5, (q31_t)0x7f545fc5, + (q31_t)0x7f51cbab, (q31_t)0x7f4f32a9, + (q31_t)0x7f4c94be, (q31_t)0x7f49f1eb, (q31_t)0x7f474a30, (q31_t)0x7f449d8c, (q31_t)0x7f41ec01, (q31_t)0x7f3f358d, + (q31_t)0x7f3c7a31, (q31_t)0x7f39b9ee, + (q31_t)0x7f36f4c3, (q31_t)0x7f342ab1, (q31_t)0x7f315bb7, (q31_t)0x7f2e87d6, (q31_t)0x7f2baf0d, (q31_t)0x7f28d15d, + (q31_t)0x7f25eec7, (q31_t)0x7f230749, + (q31_t)0x7f201ae5, (q31_t)0x7f1d299a, (q31_t)0x7f1a3368, (q31_t)0x7f173850, (q31_t)0x7f143852, (q31_t)0x7f11336d, + (q31_t)0x7f0e29a3, (q31_t)0x7f0b1af2, + (q31_t)0x7f08075c, (q31_t)0x7f04eedf, (q31_t)0x7f01d17d, (q31_t)0x7efeaf36, (q31_t)0x7efb8809, (q31_t)0x7ef85bf7, + (q31_t)0x7ef52b00, (q31_t)0x7ef1f524, + (q31_t)0x7eeeba62, (q31_t)0x7eeb7abc, (q31_t)0x7ee83632, (q31_t)0x7ee4ecc3, (q31_t)0x7ee19e6f, (q31_t)0x7ede4b38, + (q31_t)0x7edaf31c, (q31_t)0x7ed7961c, + (q31_t)0x7ed43438, (q31_t)0x7ed0cd70, (q31_t)0x7ecd61c5, (q31_t)0x7ec9f137, (q31_t)0x7ec67bc5, (q31_t)0x7ec3016f, + (q31_t)0x7ebf8237, (q31_t)0x7ebbfe1c, + (q31_t)0x7eb8751e, (q31_t)0x7eb4e73d, (q31_t)0x7eb1547a, (q31_t)0x7eadbcd4, (q31_t)0x7eaa204c, (q31_t)0x7ea67ee2, + (q31_t)0x7ea2d896, (q31_t)0x7e9f2d68, + (q31_t)0x7e9b7d58, (q31_t)0x7e97c867, (q31_t)0x7e940e94, (q31_t)0x7e904fe0, (q31_t)0x7e8c8c4b, (q31_t)0x7e88c3d5, + (q31_t)0x7e84f67e, (q31_t)0x7e812447, + (q31_t)0x7e7d4d2f, (q31_t)0x7e797136, (q31_t)0x7e75905d, (q31_t)0x7e71aaa4, (q31_t)0x7e6dc00c, (q31_t)0x7e69d093, + (q31_t)0x7e65dc3b, (q31_t)0x7e61e303, + (q31_t)0x7e5de4ec, (q31_t)0x7e59e1f5, (q31_t)0x7e55da20, (q31_t)0x7e51cd6c, (q31_t)0x7e4dbbd9, (q31_t)0x7e49a567, + (q31_t)0x7e458a17, (q31_t)0x7e4169e9, + (q31_t)0x7e3d44dd, (q31_t)0x7e391af3, (q31_t)0x7e34ec2b, (q31_t)0x7e30b885, (q31_t)0x7e2c8002, (q31_t)0x7e2842a2, + (q31_t)0x7e240064, (q31_t)0x7e1fb94a, + (q31_t)0x7e1b6d53, (q31_t)0x7e171c7f, (q31_t)0x7e12c6ce, (q31_t)0x7e0e6c42, (q31_t)0x7e0a0cd9, (q31_t)0x7e05a894, + (q31_t)0x7e013f74, (q31_t)0x7dfcd178, + (q31_t)0x7df85ea0, (q31_t)0x7df3e6ee, (q31_t)0x7def6a60, (q31_t)0x7deae8f7, (q31_t)0x7de662b3, (q31_t)0x7de1d795, + (q31_t)0x7ddd479d, (q31_t)0x7dd8b2ca, + (q31_t)0x7dd4191d, (q31_t)0x7dcf7a96, (q31_t)0x7dcad736, (q31_t)0x7dc62efc, (q31_t)0x7dc181e8, (q31_t)0x7dbccffc, + (q31_t)0x7db81936, (q31_t)0x7db35d98, + (q31_t)0x7dae9d21, (q31_t)0x7da9d7d2, (q31_t)0x7da50dab, (q31_t)0x7da03eab, (q31_t)0x7d9b6ad3, (q31_t)0x7d969224, + (q31_t)0x7d91b49e, (q31_t)0x7d8cd240, + (q31_t)0x7d87eb0a, (q31_t)0x7d82fefe, (q31_t)0x7d7e0e1c, (q31_t)0x7d791862, (q31_t)0x7d741dd2, (q31_t)0x7d6f1e6c, + (q31_t)0x7d6a1a31, (q31_t)0x7d65111f, + (q31_t)0x7d600338, (q31_t)0x7d5af07b, (q31_t)0x7d55d8e9, (q31_t)0x7d50bc82, (q31_t)0x7d4b9b46, (q31_t)0x7d467536, + (q31_t)0x7d414a51, (q31_t)0x7d3c1a98, + (q31_t)0x7d36e60b, (q31_t)0x7d31acaa, (q31_t)0x7d2c6e76, (q31_t)0x7d272b6e, (q31_t)0x7d21e393, (q31_t)0x7d1c96e5, + (q31_t)0x7d174564, (q31_t)0x7d11ef11, + (q31_t)0x7d0c93eb, (q31_t)0x7d0733f3, (q31_t)0x7d01cf29, (q31_t)0x7cfc658d, (q31_t)0x7cf6f720, (q31_t)0x7cf183e1, + (q31_t)0x7cec0bd1, (q31_t)0x7ce68ef0, + (q31_t)0x7ce10d3f, (q31_t)0x7cdb86bd, (q31_t)0x7cd5fb6a, (q31_t)0x7cd06b48, (q31_t)0x7ccad656, (q31_t)0x7cc53c94, + (q31_t)0x7cbf9e03, (q31_t)0x7cb9faa2, + (q31_t)0x7cb45272, (q31_t)0x7caea574, (q31_t)0x7ca8f3a7, (q31_t)0x7ca33d0c, (q31_t)0x7c9d81a3, (q31_t)0x7c97c16b, + (q31_t)0x7c91fc66, (q31_t)0x7c8c3294, + (q31_t)0x7c8663f4, (q31_t)0x7c809088, (q31_t)0x7c7ab84e, (q31_t)0x7c74db48, (q31_t)0x7c6ef976, (q31_t)0x7c6912d7, + (q31_t)0x7c63276d, (q31_t)0x7c5d3737, + (q31_t)0x7c574236, (q31_t)0x7c514869, (q31_t)0x7c4b49d2, (q31_t)0x7c45466f, (q31_t)0x7c3f3e42, (q31_t)0x7c39314b, + (q31_t)0x7c331f8a, (q31_t)0x7c2d08ff, + (q31_t)0x7c26edab, (q31_t)0x7c20cd8d, (q31_t)0x7c1aa8a6, (q31_t)0x7c147ef6, (q31_t)0x7c0e507e, (q31_t)0x7c081d3d, + (q31_t)0x7c01e534, (q31_t)0x7bfba863, + (q31_t)0x7bf566cb, (q31_t)0x7bef206b, (q31_t)0x7be8d544, (q31_t)0x7be28556, (q31_t)0x7bdc30a1, (q31_t)0x7bd5d726, + (q31_t)0x7bcf78e5, (q31_t)0x7bc915dd, + (q31_t)0x7bc2ae10, (q31_t)0x7bbc417e, (q31_t)0x7bb5d026, (q31_t)0x7baf5a09, (q31_t)0x7ba8df28, (q31_t)0x7ba25f82, + (q31_t)0x7b9bdb18, (q31_t)0x7b9551ea, + (q31_t)0x7b8ec3f8, (q31_t)0x7b883143, (q31_t)0x7b8199ca, (q31_t)0x7b7afd8f, (q31_t)0x7b745c91, (q31_t)0x7b6db6d0, + (q31_t)0x7b670c4d, (q31_t)0x7b605d09, + (q31_t)0x7b59a902, (q31_t)0x7b52f03a, (q31_t)0x7b4c32b1, (q31_t)0x7b457068, (q31_t)0x7b3ea95d, (q31_t)0x7b37dd92, + (q31_t)0x7b310d07, (q31_t)0x7b2a37bc, + (q31_t)0x7b235db2, (q31_t)0x7b1c7ee8, (q31_t)0x7b159b5f, (q31_t)0x7b0eb318, (q31_t)0x7b07c612, (q31_t)0x7b00d44d, + (q31_t)0x7af9ddcb, (q31_t)0x7af2e28b, + (q31_t)0x7aebe28d, (q31_t)0x7ae4ddd2, (q31_t)0x7addd45b, (q31_t)0x7ad6c626, (q31_t)0x7acfb336, (q31_t)0x7ac89b89, + (q31_t)0x7ac17f20, (q31_t)0x7aba5dfc, + (q31_t)0x7ab3381d, (q31_t)0x7aac0d82, (q31_t)0x7aa4de2d, (q31_t)0x7a9daa1d, (q31_t)0x7a967153, (q31_t)0x7a8f33d0, + (q31_t)0x7a87f192, (q31_t)0x7a80aa9c, + (q31_t)0x7a795eec, (q31_t)0x7a720e84, (q31_t)0x7a6ab963, (q31_t)0x7a635f8a, (q31_t)0x7a5c00f9, (q31_t)0x7a549db0, + (q31_t)0x7a4d35b0, (q31_t)0x7a45c8f9, + (q31_t)0x7a3e578b, (q31_t)0x7a36e166, (q31_t)0x7a2f668c, (q31_t)0x7a27e6fb, (q31_t)0x7a2062b5, (q31_t)0x7a18d9b9, + (q31_t)0x7a114c09, (q31_t)0x7a09b9a4, + (q31_t)0x7a02228a, (q31_t)0x79fa86bc, (q31_t)0x79f2e63a, (q31_t)0x79eb4105, (q31_t)0x79e3971c, (q31_t)0x79dbe880, + (q31_t)0x79d43532, (q31_t)0x79cc7d31, + (q31_t)0x79c4c07e, (q31_t)0x79bcff19, (q31_t)0x79b53903, (q31_t)0x79ad6e3c, (q31_t)0x79a59ec3, (q31_t)0x799dca9a, + (q31_t)0x7995f1c1, (q31_t)0x798e1438, + (q31_t)0x798631ff, (q31_t)0x797e4b16, (q31_t)0x79765f7f, (q31_t)0x796e6f39, (q31_t)0x79667a44, (q31_t)0x795e80a1, + (q31_t)0x79568250, (q31_t)0x794e7f52, + (q31_t)0x794677a6, (q31_t)0x793e6b4e, (q31_t)0x79365a49, (q31_t)0x792e4497, (q31_t)0x79262a3a, (q31_t)0x791e0b31, + (q31_t)0x7915e77c, (q31_t)0x790dbf1d, + (q31_t)0x79059212, (q31_t)0x78fd605d, (q31_t)0x78f529fe, (q31_t)0x78eceef6, (q31_t)0x78e4af44, (q31_t)0x78dc6ae8, + (q31_t)0x78d421e4, (q31_t)0x78cbd437, + (q31_t)0x78c381e2, (q31_t)0x78bb2ae5, (q31_t)0x78b2cf41, (q31_t)0x78aa6ef5, (q31_t)0x78a20a03, (q31_t)0x7899a06a, + (q31_t)0x7891322a, (q31_t)0x7888bf45, + (q31_t)0x788047ba, (q31_t)0x7877cb89, (q31_t)0x786f4ab4, (q31_t)0x7866c53a, (q31_t)0x785e3b1c, (q31_t)0x7855ac5a, + (q31_t)0x784d18f4, (q31_t)0x784480ea, + (q31_t)0x783be43e, (q31_t)0x783342ef, (q31_t)0x782a9cfe, (q31_t)0x7821f26b, (q31_t)0x78194336, (q31_t)0x78108f60, + (q31_t)0x7807d6e9, (q31_t)0x77ff19d1, + (q31_t)0x77f65819, (q31_t)0x77ed91c0, (q31_t)0x77e4c6c9, (q31_t)0x77dbf732, (q31_t)0x77d322fc, (q31_t)0x77ca4a27, + (q31_t)0x77c16cb4, (q31_t)0x77b88aa3, + (q31_t)0x77afa3f5, (q31_t)0x77a6b8a9, (q31_t)0x779dc8c0, (q31_t)0x7794d43b, (q31_t)0x778bdb19, (q31_t)0x7782dd5c, + (q31_t)0x7779db03, (q31_t)0x7770d40f, + (q31_t)0x7767c880, (q31_t)0x775eb857, (q31_t)0x7755a394, (q31_t)0x774c8a36, (q31_t)0x77436c40, (q31_t)0x773a49b0, + (q31_t)0x77312287, (q31_t)0x7727f6c6, + (q31_t)0x771ec66e, (q31_t)0x7715917d, (q31_t)0x770c57f5, (q31_t)0x770319d6, (q31_t)0x76f9d721, (q31_t)0x76f08fd5, + (q31_t)0x76e743f4, (q31_t)0x76ddf37c, + (q31_t)0x76d49e70, (q31_t)0x76cb44cf, (q31_t)0x76c1e699, (q31_t)0x76b883d0, (q31_t)0x76af1c72, (q31_t)0x76a5b082, + (q31_t)0x769c3ffe, (q31_t)0x7692cae8, + (q31_t)0x7689513f, (q31_t)0x767fd304, (q31_t)0x76765038, (q31_t)0x766cc8db, (q31_t)0x76633ced, (q31_t)0x7659ac6f, + (q31_t)0x76501760, (q31_t)0x76467dc2, + (q31_t)0x763cdf94, (q31_t)0x76333cd8, (q31_t)0x7629958c, (q31_t)0x761fe9b3, (q31_t)0x7616394c, (q31_t)0x760c8457, + (q31_t)0x7602cad5, (q31_t)0x75f90cc7, + (q31_t)0x75ef4a2c, (q31_t)0x75e58305, (q31_t)0x75dbb753, (q31_t)0x75d1e715, (q31_t)0x75c8124d, (q31_t)0x75be38fa, + (q31_t)0x75b45b1d, (q31_t)0x75aa78b6, + (q31_t)0x75a091c6, (q31_t)0x7596a64d, (q31_t)0x758cb64c, (q31_t)0x7582c1c2, (q31_t)0x7578c8b0, (q31_t)0x756ecb18, + (q31_t)0x7564c8f8, (q31_t)0x755ac251, + (q31_t)0x7550b725, (q31_t)0x7546a772, (q31_t)0x753c933a, (q31_t)0x75327a7d, (q31_t)0x75285d3b, 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(q31_t)0x169bb4b7, (q31_t)0x1682f774, (q31_t)0x166a3953, (q31_t)0x16517a55, (q31_t)0x1638ba7a, (q31_t)0x161ff9c4, + (q31_t)0x16073834, (q31_t)0x15ee75cb, + (q31_t)0x15d5b288, (q31_t)0x15bcee6f, (q31_t)0x15a4297f, (q31_t)0x158b63b9, (q31_t)0x15729d1f, (q31_t)0x1559d5b1, + (q31_t)0x15410d70, (q31_t)0x1528445d, + (q31_t)0x150f7a7a, (q31_t)0x14f6afc7, (q31_t)0x14dde445, (q31_t)0x14c517f4, (q31_t)0x14ac4ad7, (q31_t)0x14937cee, + (q31_t)0x147aae3a, (q31_t)0x1461debc, + (q31_t)0x14490e74, (q31_t)0x14303d65, (q31_t)0x14176b8e, (q31_t)0x13fe98f1, (q31_t)0x13e5c58e, (q31_t)0x13ccf167, + (q31_t)0x13b41c7d, (q31_t)0x139b46d0, + (q31_t)0x13827062, (q31_t)0x13699933, (q31_t)0x1350c144, (q31_t)0x1337e897, (q31_t)0x131f0f2c, (q31_t)0x13063505, + (q31_t)0x12ed5a21, (q31_t)0x12d47e83, + (q31_t)0x12bba22b, (q31_t)0x12a2c51b, (q31_t)0x1289e752, (q31_t)0x127108d2, (q31_t)0x1258299c, (q31_t)0x123f49b2, + (q31_t)0x12266913, (q31_t)0x120d87c1, + (q31_t)0x11f4a5bd, (q31_t)0x11dbc307, (q31_t)0x11c2dfa2, (q31_t)0x11a9fb8d, (q31_t)0x119116c9, (q31_t)0x11783159, + (q31_t)0x115f4b3c, (q31_t)0x11466473, + (q31_t)0x112d7d00, (q31_t)0x111494e4, (q31_t)0x10fbac1e, (q31_t)0x10e2c2b2, (q31_t)0x10c9d89e, (q31_t)0x10b0ede5, + (q31_t)0x10980287, (q31_t)0x107f1686, + (q31_t)0x106629e1, (q31_t)0x104d3c9b, (q31_t)0x10344eb4, (q31_t)0x101b602d, (q31_t)0x10027107, (q31_t)0xfe98143, + (q31_t)0xfd090e1, (q31_t)0xfb79fe4, + (q31_t)0xf9eae4c, (q31_t)0xf85bc19, (q31_t)0xf6cc94e, (q31_t)0xf53d5ea, (q31_t)0xf3ae1ee, (q31_t)0xf21ed5d, (q31_t)0xf08f836, + (q31_t)0xef0027b, + (q31_t)0xed70c2c, (q31_t)0xebe154b, (q31_t)0xea51dd8, (q31_t)0xe8c25d5, (q31_t)0xe732d42, (q31_t)0xe5a3421, (q31_t)0xe413a72, + (q31_t)0xe284036, + (q31_t)0xe0f456f, (q31_t)0xdf64a1c, (q31_t)0xddd4e40, (q31_t)0xdc451dc, (q31_t)0xdab54ef, (q31_t)0xd92577b, (q31_t)0xd795982, + (q31_t)0xd605b03, + (q31_t)0xd475c00, (q31_t)0xd2e5c7b, (q31_t)0xd155c73, (q31_t)0xcfc5bea, (q31_t)0xce35ae1, (q31_t)0xcca5959, (q31_t)0xcb15752, + (q31_t)0xc9854cf, + (q31_t)0xc7f51cf, (q31_t)0xc664e53, (q31_t)0xc4d4a5d, (q31_t)0xc3445ee, (q31_t)0xc1b4107, (q31_t)0xc023ba7, (q31_t)0xbe935d2, + (q31_t)0xbd02f87, + (q31_t)0xbb728c7, (q31_t)0xb9e2193, (q31_t)0xb8519ed, (q31_t)0xb6c11d5, (q31_t)0xb53094d, (q31_t)0xb3a0055, (q31_t)0xb20f6ee, + (q31_t)0xb07ed19, + (q31_t)0xaeee2d7, (q31_t)0xad5d829, (q31_t)0xabccd11, (q31_t)0xaa3c18e, (q31_t)0xa8ab5a2, (q31_t)0xa71a94f, (q31_t)0xa589c94, + (q31_t)0xa3f8f73, + (q31_t)0xa2681ed, (q31_t)0xa0d7403, (q31_t)0x9f465b5, (q31_t)0x9db5706, (q31_t)0x9c247f5, (q31_t)0x9a93884, (q31_t)0x99028b3, + (q31_t)0x9771884, + (q31_t)0x95e07f8, (q31_t)0x944f70f, (q31_t)0x92be5ca, (q31_t)0x912d42c, (q31_t)0x8f9c233, (q31_t)0x8e0afe2, (q31_t)0x8c79d3a, + (q31_t)0x8ae8a3a, + (q31_t)0x89576e5, (q31_t)0x87c633c, (q31_t)0x8634f3e, (q31_t)0x84a3aee, (q31_t)0x831264c, (q31_t)0x8181159, (q31_t)0x7fefc16, + (q31_t)0x7e5e685, + (q31_t)0x7ccd0a5, (q31_t)0x7b3ba78, (q31_t)0x79aa400, (q31_t)0x7818d3c, (q31_t)0x768762e, (q31_t)0x74f5ed7, (q31_t)0x7364738, + (q31_t)0x71d2f52, + (q31_t)0x7041726, (q31_t)0x6eafeb4, (q31_t)0x6d1e5fe, (q31_t)0x6b8cd05, (q31_t)0x69fb3c9, (q31_t)0x6869a4c, (q31_t)0x66d808f, + (q31_t)0x6546692, + (q31_t)0x63b4c57, (q31_t)0x62231de, (q31_t)0x6091729, (q31_t)0x5effc38, (q31_t)0x5d6e10c, (q31_t)0x5bdc5a7, (q31_t)0x5a4aa09, + (q31_t)0x58b8e34, + (q31_t)0x5727228, (q31_t)0x55955e6, (q31_t)0x540396f, (q31_t)0x5271cc4, (q31_t)0x50dffe7, (q31_t)0x4f4e2d8, (q31_t)0x4dbc597, + (q31_t)0x4c2a827, + (q31_t)0x4a98a88, (q31_t)0x4906cbb, (q31_t)0x4774ec1, (q31_t)0x45e309a, (q31_t)0x4451249, (q31_t)0x42bf3cd, (q31_t)0x412d528, + (q31_t)0x3f9b65b, + (q31_t)0x3e09767, (q31_t)0x3c7784d, (q31_t)0x3ae590d, (q31_t)0x39539a9, (q31_t)0x37c1a22, (q31_t)0x362fa78, (q31_t)0x349daac, + (q31_t)0x330bac1, + (q31_t)0x3179ab5, (q31_t)0x2fe7a8c, (q31_t)0x2e55a44, (q31_t)0x2cc39e1, (q31_t)0x2b31961, (q31_t)0x299f8c7, (q31_t)0x280d813, + (q31_t)0x267b747, + (q31_t)0x24e9662, (q31_t)0x2357567, (q31_t)0x21c5457, (q31_t)0x2033331, (q31_t)0x1ea11f7, (q31_t)0x1d0f0ab, (q31_t)0x1b7cf4d, + (q31_t)0x19eaddd, + (q31_t)0x1858c5e, (q31_t)0x16c6ad0, (q31_t)0x1534934, (q31_t)0x13a278a, (q31_t)0x12105d5, (q31_t)0x107e414, (q31_t)0xeec249, + (q31_t)0xd5a075, + (q31_t)0xbc7e99, (q31_t)0xa35cb5, (q31_t)0x8a3acb, (q31_t)0x7118dc, (q31_t)0x57f6e9, (q31_t)0x3ed4f2, (q31_t)0x25b2f8, + (q31_t)0xc90fe +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + const q31_t WeightsQ31_8192[16384] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffffd9, (q31_t)0xfff9b781, (q31_t)0x7fffff62, (q31_t)0xfff36f02, (q31_t)0x7ffffe9d, (q31_t)0xffed2684, + (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffffc25, (q31_t)0xffe09586, (q31_t)0x7ffffa73, (q31_t)0xffda4d08, (q31_t)0x7ffff872, (q31_t)0xffd40489, + (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7ffff382, (q31_t)0xffc7738c, (q31_t)0x7ffff094, (q31_t)0xffc12b0e, (q31_t)0x7fffed57, (q31_t)0xffbae290, + (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, (q31_t)0x7fffe5f0, (q31_t)0xffae5195, (q31_t)0x7fffe1c6, (q31_t)0xffa80917, (q31_t)0x7fffdd4d, (q31_t)0xffa1c09a, + (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffd36f, (q31_t)0xff952fa0, (q31_t)0x7fffce09, (q31_t)0xff8ee724, (q31_t)0x7fffc854, (q31_t)0xff889ea7, + (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffbbfe, (q31_t)0xff7c0db0, (q31_t)0x7fffb55c, (q31_t)0xff75c535, (q31_t)0x7fffae6c, (q31_t)0xff6f7cba, + (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff9f9e, (q31_t)0xff62ebc5, (q31_t)0x7fff97c1, (q31_t)0xff5ca34b, (q31_t)0x7fff8f94, (q31_t)0xff565ad1, + (q31_t)0x7fff8719, (q31_t)0xff501258, (q31_t)0x7fff7e4f, (q31_t)0xff49c9df, (q31_t)0x7fff7536, (q31_t)0xff438167, (q31_t)0x7fff6bcd, (q31_t)0xff3d38ef, + (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff5810, (q31_t)0xff30a801, (q31_t)0x7fff4dbb, (q31_t)0xff2a5f8b, (q31_t)0x7fff4317, (q31_t)0xff241715, + (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff2ce2, (q31_t)0xff17862b, (q31_t)0x7fff2151, (q31_t)0xff113db7, (q31_t)0x7fff1572, (q31_t)0xff0af543, + (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffefcc5, (q31_t)0xfefe645e, (q31_t)0x7ffeeff8, (q31_t)0xfef81bec, (q31_t)0x7ffee2dd, (q31_t)0xfef1d37b, + (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, (q31_t)0x7ffec7b9, (q31_t)0xfee5429a, (q31_t)0x7ffeb9b0, (q31_t)0xfedefa2b, (q31_t)0x7ffeab59, (q31_t)0xfed8b1bd, + (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe8dbd, (q31_t)0xfecc20e2, (q31_t)0x7ffe7e79, (q31_t)0xfec5d876, (q31_t)0x7ffe6ee5, (q31_t)0xfebf900a, + (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe4ed2, (q31_t)0xfeb2ff36, (q31_t)0x7ffe3e52, (q31_t)0xfeacb6cc, (q31_t)0x7ffe2d83, (q31_t)0xfea66e64, + (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffe0af8, (q31_t)0xfe99dd96, (q31_t)0x7ffdf93c, (q31_t)0xfe939530, (q31_t)0x7ffde731, (q31_t)0xfe8d4ccb, + (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, (q31_t)0x7ffdc22e, (q31_t)0xfe80bc04, (q31_t)0x7ffdaf37, (q31_t)0xfe7a73a2, (q31_t)0x7ffd9bf0, (q31_t)0xfe742b41, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd7476, (q31_t)0xfe679a81, (q31_t)0x7ffd6042, (q31_t)0xfe615223, (q31_t)0x7ffd4bc0, (q31_t)0xfe5b09c5, + (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffd21ce, (q31_t)0xfe4e790d, (q31_t)0x7ffd0c5f, (q31_t)0xfe4830b3, (q31_t)0x7ffcf6a0, (q31_t)0xfe41e85a, + (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffcca37, (q31_t)0xfe3557ab, (q31_t)0x7ffcb38c, (q31_t)0xfe2f0f55, (q31_t)0x7ffc9c92, (q31_t)0xfe28c700, + (q31_t)0x7ffc8549, (q31_t)0xfe227eac, (q31_t)0x7ffc6db1, (q31_t)0xfe1c365a, (q31_t)0x7ffc55ca, (q31_t)0xfe15ee09, (q31_t)0x7ffc3d94, (q31_t)0xfe0fa5b8, + (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffc0c3b, (q31_t)0xfe03151c, (q31_t)0x7ffbf319, (q31_t)0xfdfccccf, (q31_t)0x7ffbd9a7, (q31_t)0xfdf68484, + (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffba5d7, (q31_t)0xfde9f3f1, (q31_t)0x7ffb8b78, (q31_t)0xfde3aba9, (q31_t)0x7ffb70cb, (q31_t)0xfddd6363, + (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffb3a83, (q31_t)0xfdd0d2db, (q31_t)0x7ffb1ee9, (q31_t)0xfdca8a99, (q31_t)0x7ffb0300, (q31_t)0xfdc44258, + (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, (q31_t)0x7ffaca40, (q31_t)0xfdb7b1da, (q31_t)0x7ffaad6a, (q31_t)0xfdb1699e, (q31_t)0x7ffa9045, (q31_t)0xfdab2162, + (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ffa550e, (q31_t)0xfd9e90f0, (q31_t)0x7ffa36fc, (q31_t)0xfd9848b9, (q31_t)0x7ffa189c, (q31_t)0xfd920084, + (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff9daed, (q31_t)0xfd85701e, (q31_t)0x7ff9bba0, (q31_t)0xfd7f27ed, (q31_t)0x7ff99c03, (q31_t)0xfd78dfbd, + (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff95bdd, (q31_t)0xfd6c4f64, (q31_t)0x7ff93b54, (q31_t)0xfd660739, (q31_t)0x7ff91a7b, (q31_t)0xfd5fbf10, + (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, (q31_t)0x7ff8d7de, (q31_t)0xfd532ec3, (q31_t)0x7ff8b619, (q31_t)0xfd4ce69f, (q31_t)0x7ff89405, (q31_t)0xfd469e7c, + (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff84ef0, (q31_t)0xfd3a0e3d, (q31_t)0x7ff82bef, (q31_t)0xfd33c61f, (q31_t)0x7ff8089f, (q31_t)0xfd2d7e04, + (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff7c113, (q31_t)0xfd20edd2, (q31_t)0x7ff79cd6, (q31_t)0xfd1aa5bc, (q31_t)0x7ff7784a, (q31_t)0xfd145da7, + (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff72e46, (q31_t)0xfd07cd83, (q31_t)0x7ff708ce, (q31_t)0xfd018574, (q31_t)0x7ff6e307, (q31_t)0xfcfb3d67, + (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, (q31_t)0x7ff6968b, (q31_t)0xfceead52, (q31_t)0x7ff66fd7, (q31_t)0xfce8654b, (q31_t)0x7ff648d4, (q31_t)0xfce21d45, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff5f9e1, (q31_t)0xfcd58d3f, (q31_t)0x7ff5d1f1, (q31_t)0xfccf453f, (q31_t)0x7ff5a9b2, (q31_t)0xfcc8fd41, + (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff55848, (q31_t)0xfcbc6d4c, (q31_t)0x7ff52f1d, (q31_t)0xfcb62554, (q31_t)0x7ff505a2, (q31_t)0xfcafdd5e, + (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4b1c0, (q31_t)0xfca34d78, (q31_t)0x7ff48759, (q31_t)0xfc9d0588, (q31_t)0x7ff45ca3, (q31_t)0xfc96bd9b, + (q31_t)0x7ff4319d, (q31_t)0xfc9075af, (q31_t)0x7ff40649, (q31_t)0xfc8a2dc6, (q31_t)0x7ff3daa6, (q31_t)0xfc83e5de, (q31_t)0x7ff3aeb4, (q31_t)0xfc7d9df9, + (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff355e4, (q31_t)0xfc710e36, (q31_t)0x7ff32905, (q31_t)0xfc6ac657, (q31_t)0x7ff2fbd7, (q31_t)0xfc647e7b, + (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff2a08f, (q31_t)0xfc57eec9, (q31_t)0x7ff27275, (q31_t)0xfc51a6f3, (q31_t)0x7ff2440b, (q31_t)0xfc4b5f20, + (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1e64c, (q31_t)0xfc3ecf80, (q31_t)0x7ff1b6f6, (q31_t)0xfc3887b3, (q31_t)0x7ff18751, (q31_t)0xfc323fe9, + (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, (q31_t)0x7ff1271a, (q31_t)0xfc25b05c, (q31_t)0x7ff0f688, (q31_t)0xfc1f6899, (q31_t)0x7ff0c5a7, (q31_t)0xfc1920d8, + (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7ff062f9, (q31_t)0xfc0c915e, (q31_t)0x7ff0312c, (q31_t)0xfc0649a5, (q31_t)0x7fefff0f, (q31_t)0xfc0001ee, + (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7fef99ea, (q31_t)0xfbf37287, (q31_t)0x7fef66e1, (q31_t)0xfbed2ad8, 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(q31_t)0x4f4e2d8, (q31_t)0x801893b4, (q31_t)0x4ee9b8c, (q31_t)0x80185592, + (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4e20cec, (q31_t)0x8017da3b, (q31_t)0x4dbc597, (q31_t)0x80179d06, (q31_t)0x4d57e40, (q31_t)0x80176020, + (q31_t)0x4cf36e5, (q31_t)0x80172388, (q31_t)0x4c8ef88, (q31_t)0x8016e740, (q31_t)0x4c2a827, (q31_t)0x8016ab46, (q31_t)0x4bc60c4, (q31_t)0x80166f9c, + (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x4afd1f4, (q31_t)0x8015f933, (q31_t)0x4a98a88, (q31_t)0x8015be75, (q31_t)0x4a34319, (q31_t)0x80158406, + (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x496b432, (q31_t)0x80151015, (q31_t)0x4906cbb, (q31_t)0x8014d693, (q31_t)0x48a2540, (q31_t)0x80149d5f, + (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x47d9643, (q31_t)0x80142be5, (q31_t)0x4774ec1, (q31_t)0x8013f39e, (q31_t)0x471073b, (q31_t)0x8013bba7, + (q31_t)0x46abfb3, (q31_t)0x801383fe, (q31_t)0x4647828, (q31_t)0x80134ca4, (q31_t)0x45e309a, (q31_t)0x80131599, (q31_t)0x457e90a, (q31_t)0x8012dedd, + (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x44b59e1, (q31_t)0x80127251, (q31_t)0x4451249, (q31_t)0x80123c82, (q31_t)0x43ecaae, (q31_t)0x80120701, + (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x4323b70, (q31_t)0x80119ced, (q31_t)0x42bf3cd, (q31_t)0x80116859, (q31_t)0x425ac28, (q31_t)0x80113414, + (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x4191cd5, (q31_t)0x8010cc78, (q31_t)0x412d528, (q31_t)0x8010991f, (q31_t)0x40c8d79, (q31_t)0x80106616, + (q31_t)0x40645c7, (q31_t)0x8010335c, (q31_t)0x3fffe12, (q31_t)0x801000f1, (q31_t)0x3f9b65b, (q31_t)0x800fced4, (q31_t)0x3f36ea2, (q31_t)0x800f9d07, + (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3e6df28, (q31_t)0x800f3a59, (q31_t)0x3e09767, (q31_t)0x800f0978, (q31_t)0x3da4fa4, (q31_t)0x800ed8e6, + (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3cdc017, (q31_t)0x800e78af, (q31_t)0x3c7784d, (q31_t)0x800e490a, (q31_t)0x3c13080, (q31_t)0x800e19b4, + (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3b4a0e0, (q31_t)0x800dbbf5, (q31_t)0x3ae590d, (q31_t)0x800d8d8b, (q31_t)0x3a81137, (q31_t)0x800d5f71, + (q31_t)0x3a1c960, (q31_t)0x800d31a5, (q31_t)0x39b8185, (q31_t)0x800d0429, (q31_t)0x39539a9, (q31_t)0x800cd6fb, (q31_t)0x38ef1ca, (q31_t)0x800caa1c, + (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x3826207, (q31_t)0x800c514c, (q31_t)0x37c1a22, (q31_t)0x800c255a, (q31_t)0x375d23a, (q31_t)0x800bf9b7, + (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3694265, (q31_t)0x800ba35d, (q31_t)0x362fa78, (q31_t)0x800b78a7, (q31_t)0x35cb288, (q31_t)0x800b4e40, + (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x35022a2, (q31_t)0x800afa5e, (q31_t)0x349daac, (q31_t)0x800ad0e3, (q31_t)0x34392b4, (q31_t)0x800aa7b8, + (q31_t)0x33d4abb, (q31_t)0x800a7edb, (q31_t)0x33702bf, (q31_t)0x800a564e, (q31_t)0x330bac1, (q31_t)0x800a2e0f, (q31_t)0x32a72c1, (q31_t)0x800a061f, + (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x31de2bb, (q31_t)0x8009b72c, (q31_t)0x3179ab5, (q31_t)0x80099029, (q31_t)0x31152ae, (q31_t)0x80096975, + (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x304c299, (q31_t)0x80091cf9, (q31_t)0x2fe7a8c, (q31_t)0x8008f732, (q31_t)0x2f8327d, (q31_t)0x8008d1ba, + (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2eba259, (q31_t)0x800887b6, (q31_t)0x2e55a44, (q31_t)0x8008632a, (q31_t)0x2df122e, (q31_t)0x80083eed, + (q31_t)0x2d8ca16, (q31_t)0x80081b00, (q31_t)0x2d281fc, (q31_t)0x8007f761, (q31_t)0x2cc39e1, (q31_t)0x8007d411, (q31_t)0x2c5f1c3, (q31_t)0x8007b110, + (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2b96184, (q31_t)0x80076bfb, (q31_t)0x2b31961, (q31_t)0x800749e7, (q31_t)0x2acd13d, (q31_t)0x80072822, + (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x2a040f0, (q31_t)0x8006e585, (q31_t)0x299f8c7, (q31_t)0x8006c4ac, (q31_t)0x293b09c, (q31_t)0x8006a423, + (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x2872043, (q31_t)0x800663fd, (q31_t)0x280d813, (q31_t)0x80064460, (q31_t)0x27a8fe2, (q31_t)0x80062513, + (q31_t)0x27447b0, (q31_t)0x80060614, (q31_t)0x26dff7c, (q31_t)0x8005e764, (q31_t)0x267b747, (q31_t)0x8005c904, (q31_t)0x2616f10, (q31_t)0x8005aaf2, + (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x254de9e, (q31_t)0x80056fbb, (q31_t)0x24e9662, (q31_t)0x80055296, (q31_t)0x2484e26, (q31_t)0x800535c0, + (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x23bbda8, (q31_t)0x8004fd00, (q31_t)0x2357567, (q31_t)0x8004e117, (q31_t)0x22f2d25, (q31_t)0x8004c57d, + (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x2229c9d, (q31_t)0x80048f35, (q31_t)0x21c5457, (q31_t)0x80047488, (q31_t)0x2160c0f, (q31_t)0x80045a29, + (q31_t)0x20fc3c6, (q31_t)0x8004401a, (q31_t)0x2097b7c, (q31_t)0x80042659, (q31_t)0x2033331, (q31_t)0x80040ce7, (q31_t)0x1fceae4, (q31_t)0x8003f3c5, + (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1f05a48, (q31_t)0x8003c26c, (q31_t)0x1ea11f7, (q31_t)0x8003aa36, (q31_t)0x1e3c9a6, (q31_t)0x8003924f, + (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1d73900, (q31_t)0x8003636e, (q31_t)0x1d0f0ab, (q31_t)0x80034c74, (q31_t)0x1caa855, (q31_t)0x800335c9, + (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1be17a6, (q31_t)0x80030960, (q31_t)0x1b7cf4d, (q31_t)0x8002f3a1, (q31_t)0x1b186f3, (q31_t)0x8002de32, + (q31_t)0x1ab3e97, (q31_t)0x8002c912, (q31_t)0x1a4f63b, (q31_t)0x8002b440, (q31_t)0x19eaddd, (q31_t)0x80029fbe, (q31_t)0x198657f, (q31_t)0x80028b8a, + (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x18bd4bf, (q31_t)0x80026410, (q31_t)0x1858c5e, (q31_t)0x800250c9, (q31_t)0x17f43fc, (q31_t)0x80023dd2, + (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x172b335, (q31_t)0x800218cf, (q31_t)0x16c6ad0, (q31_t)0x800206c4, (q31_t)0x166226a, (q31_t)0x8001f508, + (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x159919c, (q31_t)0x8001d27d, (q31_t)0x1534934, (q31_t)0x8001c1ae, (q31_t)0x14d00ca, (q31_t)0x8001b12e, + (q31_t)0x146b860, (q31_t)0x8001a0fd, (q31_t)0x1406ff6, (q31_t)0x8001911b, (q31_t)0x13a278a, (q31_t)0x80018187, (q31_t)0x133df1e, (q31_t)0x80017243, + (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x1274e43, (q31_t)0x800154a7, (q31_t)0x12105d5, (q31_t)0x80014650, (q31_t)0x11abd66, (q31_t)0x80013847, + (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x10e2c85, (q31_t)0x80011d23, (q31_t)0x107e414, (q31_t)0x80011008, (q31_t)0x1019ba2, (q31_t)0x8001033b, + (q31_t)0x0fb5330, (q31_t)0x8000f6bd, (q31_t)0x0f50abd, (q31_t)0x8000ea8e, (q31_t)0x0eec249, (q31_t)0x8000deaf, (q31_t)0x0e879d5, (q31_t)0x8000d31e, + (q31_t)0x0e23160, (q31_t)0x8000c7dc, (q31_t)0x0dbe8eb, (q31_t)0x8000bce9, (q31_t)0x0d5a075, (q31_t)0x8000b245, (q31_t)0x0cf57ff, (q31_t)0x8000a7f0, + (q31_t)0x0c90f88, (q31_t)0x80009dea, (q31_t)0x0c2c711, (q31_t)0x80009433, (q31_t)0x0bc7e99, (q31_t)0x80008aca, (q31_t)0x0b63621, (q31_t)0x800081b1, + (q31_t)0x0afeda8, (q31_t)0x800078e7, (q31_t)0x0a9a52f, (q31_t)0x8000706c, (q31_t)0x0a35cb5, (q31_t)0x8000683f, (q31_t)0x09d143b, (q31_t)0x80006062, + (q31_t)0x096cbc1, (q31_t)0x800058d4, (q31_t)0x0908346, (q31_t)0x80005194, (q31_t)0x08a3acb, (q31_t)0x80004aa4, (q31_t)0x083f250, (q31_t)0x80004402, + (q31_t)0x07da9d4, (q31_t)0x80003daf, (q31_t)0x0776159, (q31_t)0x800037ac, (q31_t)0x07118dc, (q31_t)0x800031f7, (q31_t)0x06ad060, (q31_t)0x80002c91, + (q31_t)0x06487e3, (q31_t)0x8000277a, (q31_t)0x05e3f66, (q31_t)0x800022b3, (q31_t)0x057f6e9, (q31_t)0x80001e3a, (q31_t)0x051ae6b, (q31_t)0x80001a10, + (q31_t)0x04b65ee, (q31_t)0x80001635, (q31_t)0x0451d70, (q31_t)0x800012a9, (q31_t)0x03ed4f2, (q31_t)0x80000f6c, (q31_t)0x0388c74, (q31_t)0x80000c7e, + (q31_t)0x03243f5, (q31_t)0x800009df, (q31_t)0x02bfb77, (q31_t)0x8000078e, (q31_t)0x025b2f8, (q31_t)0x8000058d, (q31_t)0x01f6a7a, (q31_t)0x800003db, + (q31_t)0x01921fb, (q31_t)0x80000278, (q31_t)0x012d97c, (q31_t)0x80000163, (q31_t)0x00c90fe, (q31_t)0x8000009e, (q31_t)0x006487f, (q31_t)0x80000027 +}; + const q31_t cos_factorsQ31_8192[8192] = { + (q31_t)0x7ffffff6, (q31_t)0x7fffffa7, (q31_t)0x7fffff09, (q31_t)0x7ffffe1c, (q31_t)0x7ffffce1, (q31_t)0x7ffffb56, (q31_t)0x7ffff97c, (q31_t)0x7ffff753, + (q31_t)0x7ffff4dc, (q31_t)0x7ffff215, (q31_t)0x7fffef00, (q31_t)0x7fffeb9b, (q31_t)0x7fffe7e8, (q31_t)0x7fffe3e5, (q31_t)0x7fffdf94, (q31_t)0x7fffdaf3, + (q31_t)0x7fffd604, (q31_t)0x7fffd0c6, (q31_t)0x7fffcb39, (q31_t)0x7fffc55c, (q31_t)0x7fffbf31, (q31_t)0x7fffb8b7, (q31_t)0x7fffb1ee, (q31_t)0x7fffaad6, + (q31_t)0x7fffa36f, (q31_t)0x7fff9bb9, (q31_t)0x7fff93b4, (q31_t)0x7fff8b61, (q31_t)0x7fff82be, (q31_t)0x7fff79cc, (q31_t)0x7fff708b, (q31_t)0x7fff66fc, + (q31_t)0x7fff5d1d, (q31_t)0x7fff52ef, (q31_t)0x7fff4873, (q31_t)0x7fff3da8, (q31_t)0x7fff328d, (q31_t)0x7fff2724, (q31_t)0x7fff1b6b, (q31_t)0x7fff0f64, + (q31_t)0x7fff030e, (q31_t)0x7ffef669, (q31_t)0x7ffee975, (q31_t)0x7ffedc31, (q31_t)0x7ffece9f, (q31_t)0x7ffec0be, (q31_t)0x7ffeb28e, (q31_t)0x7ffea40f, + (q31_t)0x7ffe9542, (q31_t)0x7ffe8625, (q31_t)0x7ffe76b9, (q31_t)0x7ffe66fe, (q31_t)0x7ffe56f5, (q31_t)0x7ffe469c, (q31_t)0x7ffe35f4, (q31_t)0x7ffe24fe, + (q31_t)0x7ffe13b8, (q31_t)0x7ffe0224, (q31_t)0x7ffdf040, (q31_t)0x7ffdde0e, (q31_t)0x7ffdcb8d, (q31_t)0x7ffdb8bc, (q31_t)0x7ffda59d, (q31_t)0x7ffd922f, + (q31_t)0x7ffd7e72, (q31_t)0x7ffd6a66, (q31_t)0x7ffd560b, (q31_t)0x7ffd4161, (q31_t)0x7ffd2c68, (q31_t)0x7ffd1720, (q31_t)0x7ffd0189, (q31_t)0x7ffceba4, + (q31_t)0x7ffcd56f, (q31_t)0x7ffcbeeb, (q31_t)0x7ffca819, (q31_t)0x7ffc90f7, (q31_t)0x7ffc7987, (q31_t)0x7ffc61c7, (q31_t)0x7ffc49b9, (q31_t)0x7ffc315b, + (q31_t)0x7ffc18af, (q31_t)0x7ffbffb4, (q31_t)0x7ffbe66a, (q31_t)0x7ffbccd0, (q31_t)0x7ffbb2e8, (q31_t)0x7ffb98b1, (q31_t)0x7ffb7e2b, (q31_t)0x7ffb6356, + (q31_t)0x7ffb4833, (q31_t)0x7ffb2cc0, (q31_t)0x7ffb10fe, (q31_t)0x7ffaf4ed, (q31_t)0x7ffad88e, (q31_t)0x7ffabbdf, (q31_t)0x7ffa9ee2, (q31_t)0x7ffa8195, + (q31_t)0x7ffa63fa, (q31_t)0x7ffa460f, (q31_t)0x7ffa27d6, (q31_t)0x7ffa094e, (q31_t)0x7ff9ea76, (q31_t)0x7ff9cb50, (q31_t)0x7ff9abdb, (q31_t)0x7ff98c17, + (q31_t)0x7ff96c04, (q31_t)0x7ff94ba2, (q31_t)0x7ff92af1, (q31_t)0x7ff909f2, (q31_t)0x7ff8e8a3, (q31_t)0x7ff8c705, (q31_t)0x7ff8a519, (q31_t)0x7ff882dd, + (q31_t)0x7ff86053, (q31_t)0x7ff83d79, (q31_t)0x7ff81a51, (q31_t)0x7ff7f6da, (q31_t)0x7ff7d313, (q31_t)0x7ff7aefe, (q31_t)0x7ff78a9a, (q31_t)0x7ff765e7, + (q31_t)0x7ff740e5, (q31_t)0x7ff71b94, (q31_t)0x7ff6f5f4, (q31_t)0x7ff6d005, (q31_t)0x7ff6a9c8, (q31_t)0x7ff6833b, (q31_t)0x7ff65c5f, (q31_t)0x7ff63535, + (q31_t)0x7ff60dbb, (q31_t)0x7ff5e5f3, (q31_t)0x7ff5bddc, (q31_t)0x7ff59576, (q31_t)0x7ff56cc0, (q31_t)0x7ff543bc, (q31_t)0x7ff51a69, (q31_t)0x7ff4f0c7, + (q31_t)0x7ff4c6d6, (q31_t)0x7ff49c96, (q31_t)0x7ff47208, (q31_t)0x7ff4472a, (q31_t)0x7ff41bfd, (q31_t)0x7ff3f082, (q31_t)0x7ff3c4b7, (q31_t)0x7ff3989e, + (q31_t)0x7ff36c36, (q31_t)0x7ff33f7e, (q31_t)0x7ff31278, (q31_t)0x7ff2e523, (q31_t)0x7ff2b77f, (q31_t)0x7ff2898c, (q31_t)0x7ff25b4a, (q31_t)0x7ff22cb9, + (q31_t)0x7ff1fdd9, (q31_t)0x7ff1ceab, (q31_t)0x7ff19f2d, (q31_t)0x7ff16f61, (q31_t)0x7ff13f45, (q31_t)0x7ff10edb, (q31_t)0x7ff0de22, (q31_t)0x7ff0ad19, + (q31_t)0x7ff07bc2, (q31_t)0x7ff04a1c, (q31_t)0x7ff01827, (q31_t)0x7fefe5e4, (q31_t)0x7fefb351, (q31_t)0x7fef806f, (q31_t)0x7fef4d3e, (q31_t)0x7fef19bf, + (q31_t)0x7feee5f0, (q31_t)0x7feeb1d3, (q31_t)0x7fee7d67, (q31_t)0x7fee48ac, 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(q31_t)0x93b90a0, + (q31_t)0x9354c4f, (q31_t)0x92f07f8, (q31_t)0x928c39b, (q31_t)0x9227f39, (q31_t)0x91c3ad2, (q31_t)0x915f664, (q31_t)0x90fb1f1, (q31_t)0x9096d79, + (q31_t)0x90328fb, (q31_t)0x8fce477, (q31_t)0x8f69fee, (q31_t)0x8f05b5f, (q31_t)0x8ea16cb, (q31_t)0x8e3d231, (q31_t)0x8dd8d92, (q31_t)0x8d748ed, + (q31_t)0x8d10443, (q31_t)0x8cabf93, (q31_t)0x8c47ade, (q31_t)0x8be3624, (q31_t)0x8b7f164, (q31_t)0x8b1ac9f, (q31_t)0x8ab67d4, (q31_t)0x8a52304, + (q31_t)0x89ede2f, (q31_t)0x8989955, (q31_t)0x8925475, (q31_t)0x88c0f90, (q31_t)0x885caa5, (q31_t)0x87f85b5, (q31_t)0x87940c1, (q31_t)0x872fbc6, + (q31_t)0x86cb6c7, (q31_t)0x86671c2, (q31_t)0x8602cb9, (q31_t)0x859e7aa, (q31_t)0x853a296, (q31_t)0x84d5d7d, (q31_t)0x847185e, (q31_t)0x840d33b, + (q31_t)0x83a8e12, (q31_t)0x83448e5, (q31_t)0x82e03b2, (q31_t)0x827be7a, (q31_t)0x821793e, (q31_t)0x81b33fc, (q31_t)0x814eeb5, (q31_t)0x80ea969, + (q31_t)0x8086419, (q31_t)0x8021ec3, (q31_t)0x7fbd968, (q31_t)0x7f59409, (q31_t)0x7ef4ea4, (q31_t)0x7e9093b, (q31_t)0x7e2c3cd, (q31_t)0x7dc7e5a, + (q31_t)0x7d638e2, (q31_t)0x7cff365, (q31_t)0x7c9ade4, (q31_t)0x7c3685d, (q31_t)0x7bd22d2, (q31_t)0x7b6dd42, (q31_t)0x7b097ad, (q31_t)0x7aa5214, + (q31_t)0x7a40c76, (q31_t)0x79dc6d3, (q31_t)0x797812b, (q31_t)0x7913b7f, (q31_t)0x78af5ce, (q31_t)0x784b019, (q31_t)0x77e6a5e, (q31_t)0x77824a0, + (q31_t)0x771dedc, (q31_t)0x76b9914, (q31_t)0x7655347, (q31_t)0x75f0d76, (q31_t)0x758c7a1, (q31_t)0x75281c6, (q31_t)0x74c3be7, (q31_t)0x745f604, + (q31_t)0x73fb01c, (q31_t)0x7396a30, (q31_t)0x733243f, (q31_t)0x72cde4a, (q31_t)0x7269851, (q31_t)0x7205253, (q31_t)0x71a0c50, (q31_t)0x713c64a, + (q31_t)0x70d803f, (q31_t)0x7073a2f, (q31_t)0x700f41b, (q31_t)0x6faae03, (q31_t)0x6f467e7, (q31_t)0x6ee21c6, (q31_t)0x6e7dba1, (q31_t)0x6e19578, + (q31_t)0x6db4f4a, (q31_t)0x6d50919, (q31_t)0x6cec2e3, (q31_t)0x6c87ca9, (q31_t)0x6c2366a, (q31_t)0x6bbf028, (q31_t)0x6b5a9e1, (q31_t)0x6af6396, + (q31_t)0x6a91d47, (q31_t)0x6a2d6f4, (q31_t)0x69c909d, (q31_t)0x6964a42, (q31_t)0x69003e3, (q31_t)0x689bd80, (q31_t)0x6837718, (q31_t)0x67d30ad, + (q31_t)0x676ea3d, (q31_t)0x670a3ca, (q31_t)0x66a5d53, (q31_t)0x66416d8, (q31_t)0x65dd058, (q31_t)0x65789d5, (q31_t)0x651434e, (q31_t)0x64afcc3, + (q31_t)0x644b634, (q31_t)0x63e6fa2, (q31_t)0x638290b, (q31_t)0x631e271, (q31_t)0x62b9bd3, (q31_t)0x6255531, (q31_t)0x61f0e8b, (q31_t)0x618c7e1, + (q31_t)0x6128134, (q31_t)0x60c3a83, (q31_t)0x605f3ce, (q31_t)0x5ffad15, (q31_t)0x5f96659, (q31_t)0x5f31f99, (q31_t)0x5ecd8d6, (q31_t)0x5e6920e, + (q31_t)0x5e04b43, (q31_t)0x5da0475, (q31_t)0x5d3bda3, (q31_t)0x5cd76cd, (q31_t)0x5c72ff4, (q31_t)0x5c0e917, (q31_t)0x5baa237, (q31_t)0x5b45b53, + (q31_t)0x5ae146b, (q31_t)0x5a7cd80, (q31_t)0x5a18692, (q31_t)0x59b3fa0, (q31_t)0x594f8aa, (q31_t)0x58eb1b2, (q31_t)0x5886ab5, (q31_t)0x58223b6, + (q31_t)0x57bdcb3, (q31_t)0x57595ac, (q31_t)0x56f4ea2, (q31_t)0x5690795, (q31_t)0x562c085, (q31_t)0x55c7971, (q31_t)0x556325a, (q31_t)0x54feb3f, + (q31_t)0x549a422, (q31_t)0x5435d01, (q31_t)0x53d15dd, (q31_t)0x536ceb5, (q31_t)0x530878a, (q31_t)0x52a405d, (q31_t)0x523f92c, (q31_t)0x51db1f7, + (q31_t)0x5176ac0, (q31_t)0x5112385, (q31_t)0x50adc48, (q31_t)0x5049507, (q31_t)0x4fe4dc3, (q31_t)0x4f8067c, (q31_t)0x4f1bf32, (q31_t)0x4eb77e5, + (q31_t)0x4e53095, (q31_t)0x4dee942, (q31_t)0x4d8a1ec, (q31_t)0x4d25a93, (q31_t)0x4cc1337, (q31_t)0x4c5cbd8, (q31_t)0x4bf8476, (q31_t)0x4b93d11, + (q31_t)0x4b2f5a9, (q31_t)0x4acae3e, (q31_t)0x4a666d1, (q31_t)0x4a01f60, (q31_t)0x499d7ed, (q31_t)0x4939077, (q31_t)0x48d48fe, (q31_t)0x4870182, + (q31_t)0x480ba04, (q31_t)0x47a7282, (q31_t)0x4742afe, (q31_t)0x46de377, (q31_t)0x4679bee, (q31_t)0x4615461, (q31_t)0x45b0cd2, (q31_t)0x454c541, + (q31_t)0x44e7dac, (q31_t)0x4483615, (q31_t)0x441ee7c, (q31_t)0x43ba6df, (q31_t)0x4355f40, (q31_t)0x42f179f, (q31_t)0x428cffb, (q31_t)0x4228854, + (q31_t)0x41c40ab, (q31_t)0x415f8ff, (q31_t)0x40fb151, (q31_t)0x40969a0, (q31_t)0x40321ed, (q31_t)0x3fcda37, (q31_t)0x3f6927f, (q31_t)0x3f04ac4, + (q31_t)0x3ea0307, (q31_t)0x3e3bb48, (q31_t)0x3dd7386, (q31_t)0x3d72bc2, (q31_t)0x3d0e3fb, (q31_t)0x3ca9c32, (q31_t)0x3c45467, (q31_t)0x3be0c99, + (q31_t)0x3b7c4c9, (q31_t)0x3b17cf7, (q31_t)0x3ab3523, (q31_t)0x3a4ed4c, (q31_t)0x39ea573, (q31_t)0x3985d97, (q31_t)0x39215ba, (q31_t)0x38bcdda, + (q31_t)0x38585f8, (q31_t)0x37f3e14, (q31_t)0x378f62e, (q31_t)0x372ae46, (q31_t)0x36c665b, (q31_t)0x3661e6f, (q31_t)0x35fd680, (q31_t)0x3598e8f, + (q31_t)0x353469c, (q31_t)0x34cfea8, (q31_t)0x346b6b1, (q31_t)0x3406eb8, (q31_t)0x33a26bd, (q31_t)0x333dec0, (q31_t)0x32d96c1, (q31_t)0x3274ec0, + (q31_t)0x32106bd, (q31_t)0x31abeb9, (q31_t)0x31476b2, (q31_t)0x30e2ea9, (q31_t)0x307e69f, (q31_t)0x3019e93, (q31_t)0x2fb5684, (q31_t)0x2f50e74, + (q31_t)0x2eec663, (q31_t)0x2e87e4f, (q31_t)0x2e2363a, (q31_t)0x2dbee22, (q31_t)0x2d5a609, (q31_t)0x2cf5def, (q31_t)0x2c915d2, (q31_t)0x2c2cdb4, + (q31_t)0x2bc8594, (q31_t)0x2b63d73, (q31_t)0x2aff54f, (q31_t)0x2a9ad2a, (q31_t)0x2a36504, (q31_t)0x29d1cdc, (q31_t)0x296d4b2, (q31_t)0x2908c87, + (q31_t)0x28a445a, (q31_t)0x283fc2b, (q31_t)0x27db3fb, (q31_t)0x2776bc9, (q31_t)0x2712396, (q31_t)0x26adb62, (q31_t)0x264932b, (q31_t)0x25e4af4, + (q31_t)0x25802bb, (q31_t)0x251ba80, (q31_t)0x24b7244, (q31_t)0x2452a07, (q31_t)0x23ee1c8, (q31_t)0x2389988, (q31_t)0x2325147, (q31_t)0x22c0904, + (q31_t)0x225c0bf, (q31_t)0x21f787a, (q31_t)0x2193033, (q31_t)0x212e7eb, (q31_t)0x20c9fa1, (q31_t)0x2065757, (q31_t)0x2000f0b, (q31_t)0x1f9c6be, + (q31_t)0x1f37e6f, (q31_t)0x1ed3620, (q31_t)0x1e6edcf, (q31_t)0x1e0a57d, (q31_t)0x1da5d2a, (q31_t)0x1d414d6, (q31_t)0x1cdcc80, (q31_t)0x1c7842a, + (q31_t)0x1c13bd2, (q31_t)0x1baf37a, (q31_t)0x1b4ab20, (q31_t)0x1ae62c5, (q31_t)0x1a81a69, (q31_t)0x1a1d20c, (q31_t)0x19b89ae, (q31_t)0x1954150, + (q31_t)0x18ef8f0, (q31_t)0x188b08f, (q31_t)0x182682d, (q31_t)0x17c1fcb, (q31_t)0x175d767, (q31_t)0x16f8f03, (q31_t)0x169469d, (q31_t)0x162fe37, + (q31_t)0x15cb5d0, (q31_t)0x1566d68, (q31_t)0x15024ff, (q31_t)0x149dc96, (q31_t)0x143942b, (q31_t)0x13d4bc0, (q31_t)0x1370354, (q31_t)0x130bae7, + (q31_t)0x12a727a, (q31_t)0x1242a0c, (q31_t)0x11de19d, (q31_t)0x117992e, (q31_t)0x11150be, (q31_t)0x10b084d, (q31_t)0x104bfdb, (q31_t)0xfe7769, + (q31_t)0xf82ef6, (q31_t)0xf1e683, (q31_t)0xeb9e0f, (q31_t)0xe5559b, (q31_t)0xdf0d26, (q31_t)0xd8c4b0, (q31_t)0xd27c3a, (q31_t)0xcc33c3, + (q31_t)0xc5eb4c, (q31_t)0xbfa2d5, (q31_t)0xb95a5d, (q31_t)0xb311e4, (q31_t)0xacc96b, (q31_t)0xa680f2, (q31_t)0xa03878, (q31_t)0x99effe, + (q31_t)0x93a784, (q31_t)0x8d5f09, (q31_t)0x87168e, (q31_t)0x80ce12, (q31_t)0x7a8597, (q31_t)0x743d1a, (q31_t)0x6df49e, (q31_t)0x67ac21, + (q31_t)0x6163a5, (q31_t)0x5b1b27, (q31_t)0x54d2aa, (q31_t)0x4e8a2c, (q31_t)0x4841af, (q31_t)0x41f931, (q31_t)0x3bb0b3, (q31_t)0x356835, + (q31_t)0x2f1fb6, (q31_t)0x28d738, (q31_t)0x228eb9, (q31_t)0x1c463b, (q31_t)0x15fdbc, (q31_t)0xfb53d, (q31_t)0x96cbe, (q31_t)0x3243f +}; + #endif + +/** + @} end of DCT4_IDCT4_Table group + */ + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) +/** + @brief Q15 table for reciprocal +*/ +const q15_t __ALIGNED(4) armRecipTableQ15[64] = { + 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, + 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, + 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, + 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, + 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, + 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, + 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, + 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, + 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, + 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, + 0x41CC, 0x4146, 0x40C2, 0x4040 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + +/** + @brief Q31 table for reciprocal +*/ +const q31_t armRecipTableQ31[64] = { + 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, + 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, + 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, + 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, + 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, + 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, + 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, + 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, + 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, + 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, + 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) +/** + @par + Example code for the generation of the floating-point sine table: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ @par + where PI value is 3.14159265358979 + */ +const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = { + 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f, + 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f, + 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f, + 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f, + 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f, + 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f, + 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f, + 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f, + 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f, + 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f, + 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f, + 0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f, + 0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f, + 0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f, + 0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f, + 0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f, + 0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f, + 0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f, + 0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f, + 0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f, + 0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f, + 0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f, + 0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f, + 0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f, + 0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f, + 0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f, + 0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f, + 0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f, + 0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f, + 0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f, + 0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f, + 0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f, + 0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f, + 0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f, + 0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f, + 0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f, + 0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f, + 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f, + 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f, + 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f, + 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f, + 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f, + 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f, + -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f, + -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f, + -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f, + -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f, + -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f, + -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f, + -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f, + -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f, + -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f, + -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f, + -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f, + -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f, + -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f, + -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f, + -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f, + -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f, + -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f, + -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f, + -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f, + -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f, + -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f, + -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f, + -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f, + -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f, + -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f, + -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f, + -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f, + -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f, + -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f, + -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f, + -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f, + -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f, + -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f, + -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f, + -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f, + -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f, + -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f, + -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f, + -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f, + -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f, + -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f, + -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f, + -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f, + -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f, + -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f, + -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f, + -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f, + -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f, + -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f, + -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f, + -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f +}; +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) +/** + @par + Table values are in Q31 (1.31 fixed-point format) and generation is done in + three steps. First, generate sin values in floating point: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ where PI value is 3.14159265358979 + @par + Second, convert floating-point to Q31 (Fixed point): + (sinTable[i] * pow(2, 31)) + @par + Finally, round to the nearest integer value: + sinTable[i] += (sinTable[i] > 0 ? 0.5 : -0.5); + */ +const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = { + 0L, 26352928L, 52701887L, 79042909L, 105372028L, 131685278L, 157978697L, + 184248325L, 210490206L, 236700388L, 262874923L, 289009871L, 315101295L, + 341145265L, 367137861L, 393075166L, 418953276L, 444768294L, 470516330L, + 496193509L, 521795963L, 547319836L, 572761285L, 598116479L, 623381598L, + 648552838L, 673626408L, 698598533L, 723465451L, 748223418L, 772868706L, + 797397602L, 821806413L, 846091463L, 870249095L, 894275671L, 918167572L, + 941921200L, 965532978L, 988999351L, 1012316784L, 1035481766L, 1058490808L, + 1081340445L, 1104027237L, 1126547765L, 1148898640L, 1171076495L, 1193077991L, + 1214899813L, 1236538675L, 1257991320L, 1279254516L, 1300325060L, 1321199781L, + 1341875533L, 1362349204L, 1382617710L, 1402678000L, 1422527051L, 1442161874L, + 1461579514L, 1480777044L, 1499751576L, 1518500250L, 1537020244L, 1555308768L, + 1573363068L, 1591180426L, 1608758157L, 1626093616L, 1643184191L, 1660027308L, + 1676620432L, 1692961062L, 1709046739L, 1724875040L, 1740443581L, 1755750017L, + 1770792044L, 1785567396L, 1800073849L, 1814309216L, 1828271356L, 1841958164L, + 1855367581L, 1868497586L, 1881346202L, 1893911494L, 1906191570L, 1918184581L, + 1929888720L, 1941302225L, 1952423377L, 1963250501L, 1973781967L, 1984016189L, + 1993951625L, 2003586779L, 2012920201L, 2021950484L, 2030676269L, 2039096241L, + 2047209133L, 2055013723L, 2062508835L, 2069693342L, 2076566160L, 2083126254L, + 2089372638L, 2095304370L, 2100920556L, 2106220352L, 2111202959L, 2115867626L, + 2120213651L, 2124240380L, 2127947206L, 2131333572L, 2134398966L, 2137142927L, + 2139565043L, 2141664948L, 2143442326L, 2144896910L, 2146028480L, 2146836866L, + 2147321946L, 2147483647L, 2147321946L, 2146836866L, 2146028480L, 2144896910L, + 2143442326L, 2141664948L, 2139565043L, 2137142927L, 2134398966L, 2131333572L, + 2127947206L, 2124240380L, 2120213651L, 2115867626L, 2111202959L, 2106220352L, + 2100920556L, 2095304370L, 2089372638L, 2083126254L, 2076566160L, 2069693342L, + 2062508835L, 2055013723L, 2047209133L, 2039096241L, 2030676269L, 2021950484L, + 2012920201L, 2003586779L, 1993951625L, 1984016189L, 1973781967L, 1963250501L, + 1952423377L, 1941302225L, 1929888720L, 1918184581L, 1906191570L, 1893911494L, + 1881346202L, 1868497586L, 1855367581L, 1841958164L, 1828271356L, 1814309216L, + 1800073849L, 1785567396L, 1770792044L, 1755750017L, 1740443581L, 1724875040L, + 1709046739L, 1692961062L, 1676620432L, 1660027308L, 1643184191L, 1626093616L, + 1608758157L, 1591180426L, 1573363068L, 1555308768L, 1537020244L, 1518500250L, + 1499751576L, 1480777044L, 1461579514L, 1442161874L, 1422527051L, 1402678000L, + 1382617710L, 1362349204L, 1341875533L, 1321199781L, 1300325060L, 1279254516L, + 1257991320L, 1236538675L, 1214899813L, 1193077991L, 1171076495L, 1148898640L, + 1126547765L, 1104027237L, 1081340445L, 1058490808L, 1035481766L, 1012316784L, + 988999351L, 965532978L, 941921200L, 918167572L, 894275671L, 870249095L, + 846091463L, 821806413L, 797397602L, 772868706L, 748223418L, 723465451L, + 698598533L, 673626408L, 648552838L, 623381598L, 598116479L, 572761285L, + 547319836L, 521795963L, 496193509L, 470516330L, 444768294L, 418953276L, + 393075166L, 367137861L, 341145265L, 315101295L, 289009871L, 262874923L, + 236700388L, 210490206L, 184248325L, 157978697L, 131685278L, 105372028L, + 79042909L, 52701887L, 26352928L, 0L, -26352928L, -52701887L, -79042909L, + -105372028L, -131685278L, -157978697L, -184248325L, -210490206L, -236700388L, + -262874923L, -289009871L, -315101295L, -341145265L, -367137861L, -393075166L, + -418953276L, -444768294L, -470516330L, -496193509L, -521795963L, -547319836L, + -572761285L, -598116479L, -623381598L, -648552838L, -673626408L, -698598533L, + -723465451L, -748223418L, -772868706L, -797397602L, -821806413L, -846091463L, + -870249095L, -894275671L, -918167572L, -941921200L, -965532978L, -988999351L, + -1012316784L, -1035481766L, -1058490808L, -1081340445L, -1104027237L, + -1126547765L, -1148898640L, -1171076495L, -1193077991L, -1214899813L, + -1236538675L, -1257991320L, -1279254516L, -1300325060L, -1321199781L, + -1341875533L, -1362349204L, -1382617710L, -1402678000L, -1422527051L, + -1442161874L, -1461579514L, -1480777044L, -1499751576L, -1518500250L, + -1537020244L, -1555308768L, -1573363068L, -1591180426L, -1608758157L, + -1626093616L, -1643184191L, -1660027308L, -1676620432L, -1692961062L, + -1709046739L, -1724875040L, -1740443581L, -1755750017L, -1770792044L, + -1785567396L, -1800073849L, -1814309216L, -1828271356L, -1841958164L, + -1855367581L, -1868497586L, -1881346202L, -1893911494L, -1906191570L, + -1918184581L, -1929888720L, -1941302225L, -1952423377L, -1963250501L, + -1973781967L, -1984016189L, -1993951625L, -2003586779L, -2012920201L, + -2021950484L, -2030676269L, -2039096241L, -2047209133L, -2055013723L, + -2062508835L, -2069693342L, -2076566160L, -2083126254L, -2089372638L, + -2095304370L, -2100920556L, -2106220352L, -2111202959L, -2115867626L, + -2120213651L, -2124240380L, -2127947206L, -2131333572L, -2134398966L, + -2137142927L, -2139565043L, -2141664948L, -2143442326L, -2144896910L, + -2146028480L, -2146836866L, -2147321946L, (q31_t)0x80000000, -2147321946L, + -2146836866L, -2146028480L, -2144896910L, -2143442326L, -2141664948L, + -2139565043L, -2137142927L, -2134398966L, -2131333572L, -2127947206L, + -2124240380L, -2120213651L, -2115867626L, -2111202959L, -2106220352L, + -2100920556L, -2095304370L, -2089372638L, -2083126254L, -2076566160L, + -2069693342L, -2062508835L, -2055013723L, -2047209133L, -2039096241L, + -2030676269L, -2021950484L, -2012920201L, -2003586779L, -1993951625L, + -1984016189L, -1973781967L, -1963250501L, -1952423377L, -1941302225L, + -1929888720L, -1918184581L, -1906191570L, -1893911494L, -1881346202L, + -1868497586L, -1855367581L, -1841958164L, -1828271356L, -1814309216L, + -1800073849L, -1785567396L, -1770792044L, -1755750017L, -1740443581L, + -1724875040L, -1709046739L, -1692961062L, -1676620432L, -1660027308L, + -1643184191L, -1626093616L, -1608758157L, -1591180426L, -1573363068L, + -1555308768L, -1537020244L, -1518500250L, -1499751576L, -1480777044L, + -1461579514L, -1442161874L, -1422527051L, -1402678000L, -1382617710L, + -1362349204L, -1341875533L, -1321199781L, -1300325060L, -1279254516L, + -1257991320L, -1236538675L, -1214899813L, -1193077991L, -1171076495L, + -1148898640L, -1126547765L, -1104027237L, -1081340445L, -1058490808L, + -1035481766L, -1012316784L, -988999351L, -965532978L, -941921200L, + -918167572L, -894275671L, -870249095L, -846091463L, -821806413L, -797397602L, + -772868706L, -748223418L, -723465451L, -698598533L, -673626408L, -648552838L, + -623381598L, -598116479L, -572761285L, -547319836L, -521795963L, -496193509L, + -470516330L, -444768294L, -418953276L, -393075166L, -367137861L, -341145265L, + -315101295L, -289009871L, -262874923L, -236700388L, -210490206L, -184248325L, + -157978697L, -131685278L, -105372028L, -79042909L, -52701887L, -26352928L, 0 +}; + +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) +/** + @par + Table values are in Q15 (1.15 fixed-point format) and generation is done in + three steps. First, generate sin values in floating point: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ where PI value is 3.14159265358979 + @par + Second, convert floating-point to Q15 (Fixed point): + (sinTable[i] * pow(2, 15)) + @par + Finally, round to the nearest integer value: + sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); + */ +const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = { + 0, 402, 804, 1206, 1608, 2009, 2411, 2811, 3212, 3612, 4011, 4410, 4808, + 5205, 5602, 5998, 6393, 6787, 7180, 7571, 7962, 8351, 8740, 9127, 9512, + 9896, 10279, 10660, 11039, 11417, 11793, 12167, 12540, 12910, 13279, + 13646, 14010, 14373, 14733, 15091, 15447, 15800, 16151, 16500, 16846, + 17190, 17531, 17869, 18205, 18538, 18868, 19195, 19520, 19841, 20160, + 20475, 20788, 21097, 21403, 21706, 22006, 22302, 22595, 22884, 23170, + 23453, 23732, 24008, 24279, 24548, 24812, 25073, 25330, 25583, 25833, + 26078, 26320, 26557, 26791, 27020, 27246, 27467, 27684, 27897, 28106, + 28311, 28511, 28707, 28899, 29086, 29269, 29448, 29622, 29792, 29957, + 30118, 30274, 30425, 30572, 30715, 30853, 30986, 31114, 31238, 31357, + 31471, 31581, 31686, 31786, 31881, 31972, 32058, 32138, 32214, 32286, + 32352, 32413, 32470, 32522, 32568, 32610, 32647, 32679, 32706, 32729, + 32746, 32758, 32766, 32767, 32766, 32758, 32746, 32729, 32706, 32679, + 32647, 32610, 32568, 32522, 32470, 32413, 32352, 32286, 32214, 32138, + 32058, 31972, 31881, 31786, 31686, 31581, 31471, 31357, 31238, 31114, + 30986, 30853, 30715, 30572, 30425, 30274, 30118, 29957, 29792, 29622, + 29448, 29269, 29086, 28899, 28707, 28511, 28311, 28106, 27897, 27684, + 27467, 27246, 27020, 26791, 26557, 26320, 26078, 25833, 25583, 25330, + 25073, 24812, 24548, 24279, 24008, 23732, 23453, 23170, 22884, 22595, + 22302, 22006, 21706, 21403, 21097, 20788, 20475, 20160, 19841, 19520, + 19195, 18868, 18538, 18205, 17869, 17531, 17190, 16846, 16500, 16151, + 15800, 15447, 15091, 14733, 14373, 14010, 13646, 13279, 12910, 12540, + 12167, 11793, 11417, 11039, 10660, 10279, 9896, 9512, 9127, 8740, 8351, + 7962, 7571, 7180, 6787, 6393, 5998, 5602, 5205, 4808, 4410, 4011, 3612, + 3212, 2811, 2411, 2009, 1608, 1206, 804, 402, 0, -402, -804, -1206, + -1608, -2009, -2411, -2811, -3212, -3612, -4011, -4410, -4808, -5205, + -5602, -5998, -6393, -6787, -7180, -7571, -7962, -8351, -8740, -9127, + -9512, -9896, -10279, -10660, -11039, -11417, -11793, -12167, -12540, + -12910, -13279, -13646, -14010, -14373, -14733, -15091, -15447, -15800, + -16151, -16500, -16846, -17190, -17531, -17869, -18205, -18538, -18868, + -19195, -19520, -19841, -20160, -20475, -20788, -21097, -21403, -21706, + -22006, -22302, -22595, -22884, -23170, -23453, -23732, -24008, -24279, + -24548, -24812, -25073, -25330, -25583, -25833, -26078, -26320, -26557, + -26791, -27020, -27246, -27467, -27684, -27897, -28106, -28311, -28511, + -28707, -28899, -29086, -29269, -29448, -29622, -29792, -29957, -30118, + -30274, -30425, -30572, -30715, -30853, -30986, -31114, -31238, -31357, + -31471, -31581, -31686, -31786, -31881, -31972, -32058, -32138, -32214, + -32286, -32352, -32413, -32470, -32522, -32568, -32610, -32647, -32679, + -32706, -32729, -32746, -32758, -32766, -32768, -32766, -32758, -32746, + -32729, -32706, -32679, -32647, -32610, -32568, -32522, -32470, -32413, + -32352, -32286, -32214, -32138, -32058, -31972, -31881, -31786, -31686, + -31581, -31471, -31357, -31238, -31114, -30986, -30853, -30715, -30572, + -30425, -30274, -30118, -29957, -29792, -29622, -29448, -29269, -29086, + -28899, -28707, -28511, -28311, -28106, -27897, -27684, -27467, -27246, + -27020, -26791, -26557, -26320, -26078, -25833, -25583, -25330, -25073, + -24812, -24548, -24279, -24008, -23732, -23453, -23170, -22884, -22595, + -22302, -22006, -21706, -21403, -21097, -20788, -20475, -20160, -19841, + -19520, -19195, -18868, -18538, -18205, -17869, -17531, -17190, -16846, + -16500, -16151, -15800, -15447, -15091, -14733, -14373, -14010, -13646, + -13279, -12910, -12540, -12167, -11793, -11417, -11039, -10660, -10279, + -9896, -9512, -9127, -8740, -8351, -7962, -7571, -7180, -6787, -6393, + -5998, -5602, -5205, -4808, -4410, -4011, -3612, -3212, -2811, -2411, + -2009, -1608, -1206, -804, -402, 0 +}; +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c b/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c new file mode 100644 index 0000000..6887da4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c @@ -0,0 +1,486 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.c + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_const_structs.h" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +/* Floating-point structs */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { + 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { + 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { + 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { + 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { + 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { + 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { + 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { + 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { + 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE_4096_TABLE_LENGTH +}; +#endif + +/* Fixed-point structs */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = { + 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = { + 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = { + 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = { + 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = { + 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = { + 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = { + 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = { + 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = { + 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = { + 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = { + 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = { + 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = { + 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = { + 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = { + 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = { + 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = { + 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = { + 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + +/* Structure for real-value inputs */ +/* Floating-point structs */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len32 = { + { 16, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_16_TABLE_LENGTH }, + 32U, + (float32_t *)twiddleCoef_rfft_32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len64 = { + { 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH }, + 64U, + (float32_t *)twiddleCoef_rfft_64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len128 = { + { 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH }, + 128U, + (float32_t *)twiddleCoef_rfft_128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len256 = { + { 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH }, + 256U, + (float32_t *)twiddleCoef_rfft_256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len512 = { + { 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH }, + 512U, + (float32_t *)twiddleCoef_rfft_512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len1024 = { + { 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH }, + 1024U, + (float32_t *)twiddleCoef_rfft_1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len2048 = { + { 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH }, + 2048U, + (float32_t *)twiddleCoef_rfft_2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len4096 = { + { 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH }, + 4096U, + (float32_t *)twiddleCoef_rfft_4096 +}; +#endif + +/* Fixed-point structs */ +/* q31_t */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len32 = { + 32U, + 0, + 1, + 256U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len16 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len64 = { + 64U, + 0, + 1, + 128U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len128 = { + 128U, + 0, + 1, + 64U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len256 = { + 256U, + 0, + 1, + 32U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len512 = { + 512U, + 0, + 1, + 16U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len1024 = { + 1024U, + 0, + 1, + 8U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len2048 = { + 2048U, + 0, + 1, + 4U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len4096 = { + 4096U, + 0, + 1, + 2U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len8192 = { + 8192U, + 0, + 1, + 1U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len4096 +}; +#endif + +/* q15_t */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len32 = { + 32U, + 0, + 1, + 256U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len16 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len64 = { + 64U, + 0, + 1, + 128U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len128 = { + 128U, + 0, + 1, + 64U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len256 = { + 256U, + 0, + 1, + 32U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len512 = { + 512U, + 0, + 1, + 16U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len1024 = { + 1024U, + 0, + 1, + 8U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len2048 = { + 2048U, + 0, + 1, + 4U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len4096 = { + 4096U, + 0, + 1, + 2U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len8192 = { + 8192U, + 0, + 1, + 1U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len4096 +}; +#endif + +#endif diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt new file mode 100644 index 0000000..16e06c6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt @@ -0,0 +1,16 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSPComplexMath) + + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPComplexMath STATIC ${SRC}) + +configdsp(CMSISDSPComplexMath ..) + +### Includes +target_include_directories(CMSISDSPComplexMath PUBLIC "${DSP}/../../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c new file mode 100644 index 0000000..2210533 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: CompexMathFunctions.c + * Description: Combination of all comlex math function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_cmplx_conj_f32.c" +#include "arm_cmplx_conj_q15.c" +#include "arm_cmplx_conj_q31.c" +#include "arm_cmplx_dot_prod_f32.c" +#include "arm_cmplx_dot_prod_q15.c" +#include "arm_cmplx_dot_prod_q31.c" +#include "arm_cmplx_mag_f32.c" +#include "arm_cmplx_mag_q15.c" +#include "arm_cmplx_mag_q31.c" +#include "arm_cmplx_mag_squared_f32.c" +#include "arm_cmplx_mag_squared_q15.c" +#include "arm_cmplx_mag_squared_q31.c" +#include "arm_cmplx_mult_cmplx_f32.c" +#include "arm_cmplx_mult_cmplx_q15.c" +#include "arm_cmplx_mult_cmplx_q31.c" +#include "arm_cmplx_mult_real_f32.c" +#include "arm_cmplx_mult_real_q15.c" +#include "arm_cmplx_mult_real_q31.c" diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c new file mode 100644 index 0000000..df5db00 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_f32.c + * Description: Floating-point complex conjugate + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_conj Complex Conjugate + + Conjugates the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the destination data where the result should be written. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)  ] =  pSrc[(2*n)  ];    // real part
+      pDst[(2*n)+1] = -pSrc[(2*n)+1];    // imag part
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Floating-point complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + */ + + +void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) + float32x4_t zero; + float32x4x2_t vec; + + zero = vdupq_n_f32(0.0); + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0]+jC[1] = A[0]+(-1)*jA[1] */ + /* Calculate Complex Conjugate and then store the results in the destination buffer. */ + vec = vld2q_f32(pSrc); + vec.val[1] = vsubq_f32(zero,vec.val[1]); + vst2q_f32(pDst,vec); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined (ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_conj group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c new file mode 100644 index 0000000..073a337 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c @@ -0,0 +1,157 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_q15.c + * Description: Q15 complex conjugate + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Q15 complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in1; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in2, in3, in4; /* Temporary input variables */ +#endif + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + + #if defined (ARM_MATH_DSP) + in1 = read_q15x2_ia ((q15_t **) &pSrc); + in2 = read_q15x2_ia ((q15_t **) &pSrc); + in3 = read_q15x2_ia ((q15_t **) &pSrc); + in4 = read_q15x2_ia ((q15_t **) &pSrc); + +#ifndef ARM_MATH_BIG_ENDIAN + in1 = __QASX(0, in1); + in2 = __QASX(0, in2); + in3 = __QASX(0, in3); + in4 = __QASX(0, in4); +#else + in1 = __QSAX(0, in1); + in2 = __QSAX(0, in2); + in3 = __QSAX(0, in3); + in4 = __QSAX(0, in4); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16); + in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16); + in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16); + in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16); + + write_q15x2_ia (&pDst, in1); + write_q15x2_ia (&pDst, in2); + write_q15x2_ia (&pDst, in3); + write_q15x2_ia (&pDst, in4); +#else + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in1 = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __SSAT(-in1, 16); +#else + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_conj group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c new file mode 100644 index 0000000..6ef1ddb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_q31.c + * Description: Q31 complex conjugate + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Q31 complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_conj group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c new file mode 100644 index 0000000..06f1bfa --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_f32.c + * Description: Floating-point complex dot product + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_dot_prod Complex Dot Product + + Computes the dot product of two complex vectors. + The vectors are multiplied element-by-element and then summed. + + The pSrcA points to the first complex input vector and + pSrcB points to the second complex input vector. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + + 
+  realResult = 0;
+  imagResult = 0;
+  for (n = 0; n < numSamples; n++) {
+      realResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      imagResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Floating-point complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + */ + +void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result variables */ + float32_t a0,b0,c0,d0; + +#if defined(ARM_MATH_NEON) + float32x4x2_t vec1,vec2,vec3,vec4; + float32x4_t accR,accI; + float32x2_t accum = vdup_n_f32(0); + + accR = vdupq_n_f32(0.0); + accI = vdupq_n_f32(0.0); + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3U; + + while (blkCnt > 0U) + { + /* C = (A[0]+jA[1])*(B[0]+jB[1]) + ... */ + /* Calculate dot product and then store the result in a temporary buffer. */ + + vec1 = vld2q_f32(pSrcA); + vec2 = vld2q_f32(pSrcB); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + accR = vmlaq_f32(accR,vec1.val[0],vec2.val[0]); + accR = vmlsq_f32(accR,vec1.val[1],vec2.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + accI = vmlaq_f32(accI,vec1.val[1],vec2.val[0]); + accI = vmlaq_f32(accI,vec1.val[0],vec2.val[1]); + + vec3 = vld2q_f32(pSrcA); + vec4 = vld2q_f32(pSrcB); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + accR = vmlaq_f32(accR,vec3.val[0],vec4.val[0]); + accR = vmlsq_f32(accR,vec3.val[1],vec4.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + accI = vmlaq_f32(accI,vec3.val[1],vec4.val[0]); + accI = vmlaq_f32(accI,vec3.val[0],vec4.val[1]); + + /* Decrement the loop counter */ + blkCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR), vget_high_f32(accR)); + real_sum += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(accI), vget_high_f32(accI)); + imag_sum += accum[0] + accum[1]; + + /* Tail */ + blkCnt = numSamples & 0x7; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in destination buffer. */ + *realResult = real_sum; + *imagResult = imag_sum; +} + +/** + @} end of cmplx_dot_prod group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c new file mode 100644 index 0000000..2ecd801 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_q15.c + * Description: Processing function for the Q15 Complex Dot product + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Q15 complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned her + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result. + These are accumulated in a 64-bit accumulator with 34.30 precision. + As a final step, the accumulators are converted to 8.24 format. + The return results realResult and imagResult are in 8.24 format. + */ + +void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */ + q15_t a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in 8.24 format */ + /* Convert real data in 34.30 to 8.24 by 6 right shifts */ + *realResult = (q31_t) (real_sum >> 6); + /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */ + *imagResult = (q31_t) (imag_sum >> 6); +} + +/** + @} end of cmplx_dot_prod group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c new file mode 100644 index 0000000..d715d98 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c @@ -0,0 +1,153 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_q31.c + * Description: Q31 complex dot product + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Q31 complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format. + The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits. + Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768. + The return results realResult and imagResult are in 16.48 format. + Input down scaling is not required. + */ + +void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */ + q31_t a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in 16.48 format */ + *realResult = real_sum; + *imagResult = imag_sum; +} + +/** + @} end of cmplx_dot_prod group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c new file mode 100644 index 0000000..84812dc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_f32.c + * Description: Floating-point complex magnitude + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag Complex Magnitude + + Computes the magnitude of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + float32_t real, imag; /* Temporary variables to hold input values */ + +#if defined(ARM_MATH_NEON) + + float32x4x2_t vecA; + float32x4_t vRealA; + float32x4_t vImagA; + float32x4_t vMagSqA; + + float32x4x2_t vecB; + float32x4_t vRealB; + float32x4_t vImagB; + float32x4_t vMagSqB; + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3; + + while (blkCnt > 0U) + { + /* out = sqrt((real * real) + (imag * imag)) */ + + vecA = vld2q_f32(pSrc); + pSrc += 8; + + vecB = vld2q_f32(pSrc); + pSrc += 8; + + vRealA = vmulq_f32(vecA.val[0], vecA.val[0]); + vImagA = vmulq_f32(vecA.val[1], vecA.val[1]); + vMagSqA = vaddq_f32(vRealA, vImagA); + + vRealB = vmulq_f32(vecB.val[0], vecB.val[0]); + vImagB = vmulq_f32(vecB.val[1], vecB.val[1]); + vMagSqB = vaddq_f32(vRealB, vImagB); + + /* Store the result in the destination buffer. */ + vst1q_f32(pDst, __arm_vec_sqrt_f32_neon(vMagSqA)); + pDst += 4; + + vst1q_f32(pDst, __arm_vec_sqrt_f32_neon(vMagSqB)); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + blkCnt = numSamples & 7; + +#else + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c new file mode 100644 index 0000000..a493274 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_q15.c + * Description: Q15 complex magnitude + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q15 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. + */ + +void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c new file mode 100644 index 0000000..873e566 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_q31.c + * Description: Q31 complex magnitude + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q31 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format. + Input down scaling is not required. + */ + +void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c new file mode 100644 index 0000000..99f051c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c @@ -0,0 +1,184 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_f32.c + * Description: Floating-point complex magnitude squared + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag_squared Complex Magnitude Squared + + Computes the magnitude squared of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t real, imag; /* Temporary input variables */ + +#if defined(ARM_MATH_NEON) + float32x4x2_t vecA; + float32x4_t vRealA; + float32x4_t vImagA; + float32x4_t vMagSqA; + + float32x4x2_t vecB; + float32x4_t vRealB; + float32x4_t vImagB; + float32x4_t vMagSqB; + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3; + + while (blkCnt > 0U) + { + /* out = sqrt((real * real) + (imag * imag)) */ + + vecA = vld2q_f32(pSrc); + pSrc += 8; + + vRealA = vmulq_f32(vecA.val[0], vecA.val[0]); + vImagA = vmulq_f32(vecA.val[1], vecA.val[1]); + vMagSqA = vaddq_f32(vRealA, vImagA); + + vecB = vld2q_f32(pSrc); + pSrc += 8; + + vRealB = vmulq_f32(vecB.val[0], vecB.val[0]); + vImagB = vmulq_f32(vecB.val[1], vecB.val[1]); + vMagSqB = vaddq_f32(vRealB, vImagB); + + /* Store the result in the destination buffer. */ + vst1q_f32(pDst, vMagSqA); + pDst += 4; + + vst1q_f32(pDst, vMagSqB); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + blkCnt = numSamples & 7; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag_squared group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c new file mode 100644 index 0000000..fa5f4e6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_q15.c + * Description: Q15 complex magnitude squared + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Q15 complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. + */ + +void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag_squared group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c new file mode 100644 index 0000000..54863ef --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_q31.c + * Description: Q31 complex magnitude squared + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Q31 complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. + Input down scaling is not required. + */ + +void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + /* store the result in 3.29 format in the destination buffer. */ + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag_squared group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c new file mode 100644 index 0000000..8d14821 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_f32.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication + + Multiplies a complex vector by another complex vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t a, b, c, d; /* Temporary variables to store real and imaginary values */ + +#if defined(ARM_MATH_NEON) + float32x4x2_t va, vb; + float32x4_t real, imag; + float32x4x2_t outCplx; + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + va = vld2q_f32(pSrcA); // load & separate real/imag pSrcA (de-interleave 2) + vb = vld2q_f32(pSrcB); // load & separate real/imag pSrcB + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + outCplx.val[0] = vmulq_f32(va.val[0], vb.val[0]); + outCplx.val[0] = vmlsq_f32(outCplx.val[0], va.val[1], vb.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + outCplx.val[1] = vmulq_f32(va.val[0], vb.val[1]); + outCplx.val[1] = vmlaq_f32(outCplx.val[1], va.val[1], vb.val[0]); + + vst2q_f32(pDst, outCplx); + + /* Increment pointer */ + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c new file mode 100644 index 0000000..6659427 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_q15.c + * Description: Q15 complex-by-complex multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Q15 complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. + */ + +void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t a, b, c, d; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c new file mode 100644 index 0000000..f6d6dc6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_q31.c + * Description: Q31 complex-by-complex multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Q31 complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. + Input down scaling is not required. + */ + +void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t a, b, c, d; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in 3.29 format in destination buffer. */ + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c new file mode 100644 index 0000000..9651999 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c @@ -0,0 +1,169 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_f32.c + * Description: Floating-point complex by real multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByRealMult Complex-by-Real Multiplication + + Multiplies a complex vector by a real vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values while the real array has a total of numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+      pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Floating-point complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t in; /* Temporary variable */ + +#if defined(ARM_MATH_NEON) + float32x4_t r; + float32x4x2_t ab,outCplx; + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + ab = vld2q_f32(pSrcCmplx); // load & separate real/imag pSrcA (de-interleave 2) + r = vld1q_f32(pSrcReal); // load & separate real/imag pSrcB + + /* Increment pointers */ + pSrcCmplx += 8; + pSrcReal += 4; + + outCplx.val[0] = vmulq_f32(ab.val[0], r); + outCplx.val[1] = vmulq_f32(ab.val[1], r); + + vst2q_f32(pCmplxDst, outCplx); + pCmplxDst += 8; + + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 3; +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++* in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByRealMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c new file mode 100644 index 0000000..4877d20 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_q15.c + * Description: Q15 complex by real multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Q15 complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; /* Temporary variables to hold input data */ + q31_t inB1; /* Temporary variables to hold input data */ + q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */ + q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + +#if defined (ARM_MATH_DSP) + /* read 2 complex numbers both real and imaginary from complex input buffer */ + inA1 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + inA2 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + /* read 2 real values at a time from real input buffer */ + inB1 = read_q15x2_ia ((q15_t **) &pSrcReal); + + /* multiply complex number with real numbers */ +#ifndef ARM_MATH_BIG_ENDIAN + mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1)); + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1)); + mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16)); +#else + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* saturate the result */ + out1 = (q15_t) __SSAT(mul1 >> 15U, 16); + out2 = (q15_t) __SSAT(mul2 >> 15U, 16); + out3 = (q15_t) __SSAT(mul3 >> 15U, 16); + out4 = (q15_t) __SSAT(mul4 >> 15U, 16); + + /* pack real and imaginary outputs and store them to destination */ + write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16)); + + inA1 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + inA2 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + inB1 = read_q15x2_ia ((q15_t **) &pSrcReal); + +#ifndef ARM_MATH_BIG_ENDIAN + mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1)); + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1)); + mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16)); +#else + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + out1 = (q15_t) __SSAT(mul1 >> 15U, 16); + out2 = (q15_t) __SSAT(mul2 >> 15U, 16); + out3 = (q15_t) __SSAT(mul3 >> 15U, 16); + out4 = (q15_t) __SSAT(mul4 >> 15U, 16); + + write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16)); +#else + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store the result in the destination buffer. */ + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByRealMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c new file mode 100644 index 0000000..906410f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_q31.c + * Description: Q31 complex by real multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Q31 complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + */ + +void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + /* store result in destination buffer. */ + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + /* store result in destination buffer. */ + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByRealMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt new file mode 100644 index 0000000..705f5b8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt @@ -0,0 +1,37 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSPController) + +add_library(CMSISDSPController STATIC) + +configdsp(CMSISDSPController ..) + +include(interpol) +interpol(CMSISDSPController) + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPController PUBLIC ARM_ALL_FAST_TABLES) +endif() + +target_sources(CMSISDSPController PRIVATE arm_pid_init_f32.c) +target_sources(CMSISDSPController PRIVATE arm_pid_init_q15.c) +target_sources(CMSISDSPController PRIVATE arm_pid_init_q31.c) +target_sources(CMSISDSPController PRIVATE arm_pid_reset_f32.c) +target_sources(CMSISDSPController PRIVATE arm_pid_reset_q15.c) +target_sources(CMSISDSPController PRIVATE arm_pid_reset_q31.c) + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_COS_F32) +target_sources(CMSISDSPController PRIVATE arm_sin_cos_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_COS_Q31) +target_sources(CMSISDSPController PRIVATE arm_sin_cos_q31.c) +endif() + + + +### Includes +target_include_directories(CMSISDSPController PUBLIC "${DSP}/../../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c new file mode 100644 index 0000000..51720bc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: ControllerFunctions.c + * Description: Combination of all controller function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_pid_init_f32.c" +#include "arm_pid_init_q15.c" +#include "arm_pid_init_q31.c" +#include "arm_pid_reset_f32.c" +#include "arm_pid_reset_q15.c" +#include "arm_pid_reset_q31.c" +#include "arm_sin_cos_f32.c" +#include "arm_sin_cos_q31.c" + diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c new file mode 100644 index 0000000..433a65a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_f32.c + * Description: Floating-point PID Control initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the floating-point PID Control. + @param[in,out] S points to an instance of the PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag) +{ + /* Derived coefficient A0 */ + S->A0 = S->Kp + S->Ki + S->Kd; + + /* Derived coefficient A1 */ + S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd); + + /* Derived coefficient A2 */ + S->A2 = S->Kd; + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(float32_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c new file mode 100644 index 0000000..c88a3d9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c @@ -0,0 +1,95 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_q15.c + * Description: Q15 PID Control initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag) +{ + +#if defined (ARM_MATH_DSP) + + /* Derived coefficient A0 */ + S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd); + + /* Derived coefficients and pack into A1 */ + +#ifndef ARM_MATH_BIG_ENDIAN + S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16); +#else + S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16); +#endif + +#else + + q31_t temp; /* to store the sum */ + + /* Derived coefficient A0 */ + temp = S->Kp + S->Ki + S->Kd; + S->A0 = (q15_t) __SSAT(temp, 16); + + /* Derived coefficients and pack into A1 */ + temp = -(S->Kd + S->Kd + S->Kp); + S->A1 = (q15_t) __SSAT(temp, 16); + S->A2 = S->Kd; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q15_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c new file mode 100644 index 0000000..1625a5f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_q31.c + * Description: Q31 PID Control initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag) +{ + +#if defined (ARM_MATH_DSP) + + /* Derived coefficient A0 */ + S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd); + + /* Derived coefficient A1 */ + S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp); + +#else + + q31_t temp; /* to store the sum */ + + /* Derived coefficient A0 */ + temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki); + S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd); + + /* Derived coefficient A1 */ + temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd); + S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Derived coefficient A2 */ + S->A2 = S->Kd; + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q31_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c new file mode 100644 index 0000000..d839e55 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_f32.c + * Description: Floating-point PID Control reset function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the floating-point PID Control. + @param[in,out] S points to an instance of the floating-point PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_f32( + arm_pid_instance_f32 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(float32_t)); +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c new file mode 100644 index 0000000..256fd8c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_q15.c + * Description: Q15 PID Control reset function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_q15( + arm_pid_instance_q15 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q15_t)); +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c new file mode 100644 index 0000000..2aa391c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_q31.c + * Description: Q31 PID Control reset function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_q31( + arm_pid_instance_q31 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q31_t)); +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c new file mode 100644 index 0000000..12a1c83 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_cos_f32.c + * Description: Sine and Cosine calculation for floating-point values + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupController + */ + +/** + @defgroup SinCos Sine Cosine + + Computes the trigonometric sine and cosine values using a combination of table lookup + and linear interpolation. + There are separate functions for Q31 and floating-point data types. + The input to the floating-point version is in degrees while the + fixed-point Q31 have a scaled input with the range + [-1 0.9999] mapping to [-180 +180] degrees. + + The floating point function also allows values that are out of the usual range. When this happens, the function will + take extra time to adjust the input value to the range of [-180 180]. + + The result is accurate to 5 digits after the decimal point. + + The implementation is based on table lookup using 360 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index. + -# Compute the fractional portion (fract) of the input. + -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1. + -# Sine value is computed as *psinVal = y0 + (fract * (y1 - y0)). + -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1. + -# Cosine value is computed as *pcosVal = y0 + (fract * (y1 - y0)). + */ + +/** + @addtogroup SinCos + @{ + */ + +/** + @brief Floating-point sin_cos function. + @param[in] theta input value in degrees + @param[out] pSinVal points to processed sine output + @param[out] pCosVal points to processed cosine output + @return none + */ + +void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal) +{ + float32_t fract, in; /* Temporary input, output variables */ + uint16_t indexS, indexC; /* Index variable */ + float32_t f1, f2, d1, d2; /* Two nearest output values */ + float32_t Dn, Df; + float32_t temp, findex; + + /* input x is in degrees */ + /* Scale input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */ + in = theta * 0.00277777777778f; + + if (in < 0.0f) + { + in = -in; + } + + in = in - (int32_t)in; + + /* Calculate the nearest index */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + indexS = ((uint16_t)findex) & 0x1ff; + indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff; + + /* Calculation of fractional value */ + fract = findex - (float32_t) indexS; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_f32[indexC ]; + f2 = sinTable_f32[indexC+1]; + d1 = -sinTable_f32[indexS ]; + d2 = -sinTable_f32[indexS+1]; + + temp = (1.0f - fract) * f1 + fract * f2; + + Dn = 0.0122718463030f; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */ + Df = f2 - f1; /* delta between the values of the functions */ + + temp = Dn * (d1 + d2) - 2 * Df; + temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn); + temp = fract * temp + d1 * Dn; + + /* Calculation of cosine value */ + *pCosVal = fract * temp + f1; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_f32[indexS ]; + f2 = sinTable_f32[indexS+1]; + d1 = sinTable_f32[indexC ]; + d2 = sinTable_f32[indexC+1]; + + temp = (1.0f - fract) * f1 + fract * f2; + + Df = f2 - f1; // delta between the values of the functions + temp = Dn * (d1 + d2) - 2 * Df; + temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn); + temp = fract * temp + d1 * Dn; + + /* Calculation of sine value */ + *pSinVal = fract * temp + f1; + + if (theta < 0.0f) + { + *pSinVal = -*pSinVal; + } +} + +/** + @} end of SinCos group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c new file mode 100644 index 0000000..84ee3d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_cos_q31.c + * Description: Cosine & Sine calculation for Q31 values + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupController + */ + +/** + @addtogroup SinCos + @{ + */ + +/** + @brief Q31 sin_cos function. + @param[in] theta scaled input value in degrees + @param[out] pSinVal points to processed sine output + @param[out] pCosVal points to processed cosine output + @return none + + The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179]. + */ + +void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal) +{ + q31_t fract; /* Temporary input, output variables */ + uint16_t indexS, indexC; /* Index variable */ + q31_t f1, f2, d1, d2; /* Two nearest output values */ + q31_t Dn, Df; + q63_t temp; + + /* Calculate the nearest index */ + indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT; + indexC = (indexS + 128) & 0x1ff; + + /* Calculation of fractional value */ + fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_q31[indexC ]; + f2 = sinTable_q31[indexC+1]; + d1 = -sinTable_q31[indexS ]; + d2 = -sinTable_q31[indexS+1]; + + Dn = 0x1921FB5; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */ + Df = f2 - f1; /* delta between the values of the functions */ + + temp = Dn * ((q63_t)d1 + d2); + temp = temp - ((q63_t)Df << 32); + temp = (q63_t)fract * (temp >> 31); + temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn); + temp = (q63_t)fract * (temp >> 31); + temp = temp + (q63_t)d1 * Dn; + temp = (q63_t)fract * (temp >> 31); + + /* Calculation of cosine value */ + *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1); + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_q31[indexS ]; + f2 = sinTable_q31[indexS+1]; + d1 = sinTable_q31[indexC ]; + d2 = sinTable_q31[indexC+1]; + + Df = f2 - f1; // delta between the values of the functions + temp = Dn * ((q63_t)d1 + d2); + temp = temp - ((q63_t)Df << 32); + temp = (q63_t)fract * (temp >> 31); + temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn); + temp = (q63_t)fract * (temp >> 31); + temp = temp + (q63_t)d1 * Dn; + temp = (q63_t)fract * (temp >> 31); + + /* Calculation of sine value */ + *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1); +} + +/** + @} end of SinCos group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt new file mode 100644 index 0000000..6719b41 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt @@ -0,0 +1,51 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSPFastMath) + + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPFastMath STATIC) + +include(interpol) +interpol(CMSISDSPFastMath) + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPFastMath PUBLIC ARM_ALL_FAST_TABLES) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_COS_F32) +target_sources(CMSISDSPFastMath PRIVATE arm_cos_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_COS_Q15) +target_sources(CMSISDSPFastMath PRIVATE arm_cos_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_COS_Q31) +target_sources(CMSISDSPFastMath PRIVATE arm_cos_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_F32) +target_sources(CMSISDSPFastMath PRIVATE arm_sin_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_Q15) +target_sources(CMSISDSPFastMath PRIVATE arm_sin_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_Q31) +target_sources(CMSISDSPFastMath PRIVATE arm_sin_q31.c) +endif() + +target_sources(CMSISDSPFastMath PRIVATE arm_sqrt_q15.c) +target_sources(CMSISDSPFastMath PRIVATE arm_sqrt_q31.c) + + +configdsp(CMSISDSPFastMath ..) + +### Includes +target_include_directories(CMSISDSPFastMath PUBLIC "${DSP}/../../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c new file mode 100644 index 0000000..abd919e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: FastMathFunctions.c + * Description: Combination of all fast math function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_cos_f32.c" +#include "arm_cos_q15.c" +#include "arm_cos_q31.c" +#include "arm_sin_f32.c" +#include "arm_sin_q15.c" +#include "arm_sin_q31.c" +#include "arm_sqrt_q15.c" +#include "arm_sqrt_q31.c" + diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c new file mode 100644 index 0000000..26bd66e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_f32.c + * Description: Fast cosine calculation for floating-point values + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @defgroup cos Cosine + + Computes the trigonometric cosine function using a combination of table lookup + and linear interpolation. There are separate functions for + Q15, Q31, and floating-point data types. + The input to the floating-point version is in radians while the + fixed-point Q15 and Q31 have a scaled input with the range + [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a + value of 2*pi wraps around to 0. + + The implementation is based on table lookup using 256 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index + -# Compute the fractional portion (fract) of the table index. + -# The final result equals (1.0f-fract)*a + fract*b; + + where + 
+     b = Table[index];
+     c = Table[index+1];
+
+ */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for floating-point data. + @param[in] x input value in radians + @return cos(x) + */ + +float32_t arm_cos_f32( + float32_t x) +{ + float32_t cosVal, fract, in; /* Temporary input, output variables */ + uint16_t index; /* Index variable */ + float32_t a, b; /* Two nearest output values */ + int32_t n; + float32_t findex; + + /* input x is in radians */ + /* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */ + in = x * 0.159154943092f + 0.25f; + + /* Calculation of floor value of input */ + n = (int32_t) in; + + /* Make negative values towards -infinity */ + if (in < 0.0f) + { + n--; + } + + /* Map input value to [0 1] */ + in = in - (float32_t) n; + + /* Calculation of index of the table */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + index = (uint16_t)findex; + + /* when "in" is exactly 1, we need to rotate the index down to 0 */ + if (index >= FAST_MATH_TABLE_SIZE) { + index = 0; + findex -= (float32_t)FAST_MATH_TABLE_SIZE; + } + + /* fractional value calculation */ + fract = findex - (float32_t) index; + + /* Read two nearest values of input value from the cos table */ + a = sinTable_f32[index]; + b = sinTable_f32[index+1]; + + /* Linear interpolation process */ + cosVal = (1.0f - fract) * a + fract * b; + + /* Return output value */ + return (cosVal); +} + +/** + @} end of cos group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c new file mode 100644 index 0000000..3bb829c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q15.c + * Description: Fast cosine calculation for Q15 values + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for Q15 data. + @param[in] x Scaled input value in radians + @return cos(x) + + The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q15_t arm_cos_q15( + q15_t x) +{ + q15_t cosVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q15_t a, b; /* Two nearest output values */ + q15_t fract; /* Temporary values for fractional values */ + + /* add 0.25 (pi/2) to read sine table */ + x = (uint16_t)x + 0x2000; + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint16_t)x + 0x8000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q15_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q15[index]; + b = sinTable_q15[index+1]; + + /* Linear interpolation process */ + cosVal = (q31_t) (0x8000 - fract) * a >> 16; + cosVal = (q15_t) ((((q31_t) cosVal << 16) + ((q31_t) fract * b)) >> 16); + + /* Return output value */ + return (cosVal << 1); +} + +/** + @} end of cos group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c new file mode 100644 index 0000000..8b7ff78 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q31.c + * Description: Fast cosine calculation for Q31 values + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for Q31 data. + @param[in] x Scaled input value in radians + @return cos(x) + + The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q31_t arm_cos_q31( + q31_t x) +{ + q31_t cosVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q31_t a, b; /* Two nearest output values */ + q31_t fract; /* Temporary values for fractional values */ + + /* add 0.25 (pi/2) to read sine table */ + x = (uint32_t)x + 0x20000000; + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint32_t)x + 0x80000000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q31_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q31[index]; + b = sinTable_q31[index+1]; + + /* Linear interpolation process */ + cosVal = (q63_t) (0x80000000 - fract) * a >> 32; + cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) fract * b)) >> 32); + + /* Return output value */ + return (cosVal << 1); +} + +/** + @} end of cos group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c new file mode 100644 index 0000000..97c6902 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_f32.c + * Description: Fast sine calculation for floating-point values + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @defgroup sin Sine + + Computes the trigonometric sine function using a combination of table lookup + and linear interpolation. There are separate functions for + Q15, Q31, and floating-point data types. + The input to the floating-point version is in radians while the + fixed-point Q15 and Q31 have a scaled input with the range + [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a + value of 2*pi wraps around to 0. + + The implementation is based on table lookup using 256 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index + -# Compute the fractional portion (fract) of the table index. + -# The final result equals (1.0f-fract)*a + fract*b; + + where + 
+     b = Table[index];
+     c = Table[index+1];
+
+ */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for floating-point data. + @param[in] x input value in radians. + @return sin(x) + */ + +float32_t arm_sin_f32( + float32_t x) +{ + float32_t sinVal, fract, in; /* Temporary input, output variables */ + uint16_t index; /* Index variable */ + float32_t a, b; /* Two nearest output values */ + int32_t n; + float32_t findex; + + /* input x is in radians */ + /* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi */ + in = x * 0.159154943092f; + + /* Calculation of floor value of input */ + n = (int32_t) in; + + /* Make negative values towards -infinity */ + if (in < 0.0f) + { + n--; + } + + /* Map input value to [0 1] */ + in = in - (float32_t) n; + + /* Calculation of index of the table */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + index = (uint16_t)findex; + + /* when "in" is exactly 1, we need to rotate the index down to 0 */ + if (index >= FAST_MATH_TABLE_SIZE) { + index = 0; + findex -= (float32_t)FAST_MATH_TABLE_SIZE; + } + + /* fractional value calculation */ + fract = findex - (float32_t) index; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_f32[index]; + b = sinTable_f32[index+1]; + + /* Linear interpolation process */ + sinVal = (1.0f - fract) * a + fract * b; + + /* Return output value */ + return (sinVal); +} + +/** + @} end of sin group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c new file mode 100644 index 0000000..1f0c2bf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_q15.c + * Description: Fast sine calculation for Q15 values + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for Q15 data. + @param[in] x Scaled input value in radians + @return sin(x) + + The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q15_t arm_sin_q15( + q15_t x) +{ + q15_t sinVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q15_t a, b; /* Two nearest output values */ + q15_t fract; /* Temporary values for fractional values */ + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q15_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q15[index]; + b = sinTable_q15[index+1]; + + /* Linear interpolation process */ + sinVal = (q31_t) (0x8000 - fract) * a >> 16; + sinVal = (q15_t) ((((q31_t) sinVal << 16) + ((q31_t) fract * b)) >> 16); + + /* Return output value */ + return (sinVal << 1); +} + +/** + @} end of sin group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c new file mode 100644 index 0000000..8cefabb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_q31.c + * Description: Fast sine calculation for Q31 values + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for Q31 data. + @param[in] x Scaled input value in radians + @return sin(x) + + The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q31_t arm_sin_q31( + q31_t x) +{ + q31_t sinVal; /* Temporary variables for input, output */ + int32_t index; /* Index variable */ + q31_t a, b; /* Two nearest output values */ + q31_t fract; /* Temporary values for fractional values */ + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q31_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q31[index]; + b = sinTable_q31[index+1]; + + /* Linear interpolation process */ + sinVal = (q63_t) (0x80000000 - fract) * a >> 32; + sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) fract * b)) >> 32); + + /* Return output value */ + return (sinVal << 1); +} + +/** + @} end of sin group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c new file mode 100644 index 0000000..fab0a32 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sqrt_q15.c + * Description: Q15 square root function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup SQRT + @{ + */ + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ + +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut) +{ + q31_t bits_val1; + q15_t number, temp1, var1, signBits1, half; + float32_t temp_float1; + union + { + q31_t fracval; + float32_t floatval; + } tempconv; + + number = in; + + /* If the input is a positive number then compute the signBits. */ + if (number > 0) + { + signBits1 = __CLZ(number) - 17; + + /* Shift by the number of signBits1 */ + if ((signBits1 % 2) == 0) + { + number = number << signBits1; + } + else + { + number = number << (signBits1 - 1); + } + + /* Calculate half value of the number */ + half = number >> 1; + /* Store the number for later use */ + temp1 = number; + + /* Convert to float */ + temp_float1 = number * 3.051757812500000e-005f; + /* Store as integer */ + tempconv.floatval = temp_float1; + bits_val1 = tempconv.fracval; + /* Subtract the shifted value from the magic number to give intial guess */ + bits_val1 = 0x5f3759df - (bits_val1 >> 1); /* gives initial guess */ + /* Store as float */ + tempconv.fracval = bits_val1; + temp_float1 = tempconv.floatval; + /* Convert to integer format */ + var1 = (q31_t) (temp_float1 * 16384); + + /* 1st iteration */ + var1 = ((q15_t) ((q31_t) var1 * (0x3000 - + ((q15_t) + ((((q15_t) + (((q31_t) var1 * var1) >> 15)) * + (q31_t) half) >> 15))) >> 15)) << 2; + /* 2nd iteration */ + var1 = ((q15_t) ((q31_t) var1 * (0x3000 - + ((q15_t) + ((((q15_t) + (((q31_t) var1 * var1) >> 15)) * + (q31_t) half) >> 15))) >> 15)) << 2; + /* 3rd iteration */ + var1 = ((q15_t) ((q31_t) var1 * (0x3000 - + ((q15_t) + ((((q15_t) + (((q31_t) var1 * var1) >> 15)) * + (q31_t) half) >> 15))) >> 15)) << 2; + + /* Multiply the inverse square root with the original value */ + var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1; + + /* Shift the output down accordingly */ + if ((signBits1 % 2) == 0) + { + var1 = var1 >> (signBits1 / 2); + } + else + { + var1 = var1 >> ((signBits1 - 1) / 2); + } + *pOut = var1; + + return (ARM_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +/** + @} end of SQRT group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c new file mode 100644 index 0000000..9889b13 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sqrt_q31.c + * Description: Q31 square root function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup SQRT + @{ + */ + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ + +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut) +{ + q31_t bits_val1; + q31_t number, temp1, var1, signBits1, half; + float32_t temp_float1; + union + { + q31_t fracval; + float32_t floatval; + } tempconv; + + number = in; + + /* If the input is a positive number then compute the signBits. */ + if (number > 0) + { + signBits1 = __CLZ(number) - 1; + + /* Shift by the number of signBits1 */ + if ((signBits1 % 2) == 0) + { + number = number << signBits1; + } + else + { + number = number << (signBits1 - 1); + } + + /* Calculate half value of the number */ + half = number >> 1; + /* Store the number for later use */ + temp1 = number; + + /* Convert to float */ + temp_float1 = number * 4.6566128731e-010f; + /* Store as integer */ + tempconv.floatval = temp_float1; + bits_val1 = tempconv.fracval; + /* Subtract the shifted value from the magic number to give intial guess */ + bits_val1 = 0x5f3759df - (bits_val1 >> 1); /* gives initial guess */ + /* Store as float */ + tempconv.fracval = bits_val1; + temp_float1 = tempconv.floatval; + /* Convert to integer format */ + var1 = (q31_t) (temp_float1 * 1073741824); + + /* 1st iteration */ + var1 = ((q31_t) ((q63_t) var1 * (0x30000000 - + ((q31_t) + ((((q31_t) + (((q63_t) var1 * var1) >> 31)) * + (q63_t) half) >> 31))) >> 31)) << 2; + /* 2nd iteration */ + var1 = ((q31_t) ((q63_t) var1 * (0x30000000 - + ((q31_t) + ((((q31_t) + (((q63_t) var1 * var1) >> 31)) * + (q63_t) half) >> 31))) >> 31)) << 2; + /* 3rd iteration */ + var1 = ((q31_t) ((q63_t) var1 * (0x30000000 - + ((q31_t) + ((((q31_t) + (((q63_t) var1 * var1) >> 31)) * + (q63_t) half) >> 31))) >> 31)) << 2; + + /* Multiply the inverse square root with the original value */ + var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1; + + /* Shift the output down accordingly */ + if ((signBits1 % 2) == 0) + { + var1 = var1 >> (signBits1 / 2); + } + else + { + var1 = var1 >> ((signBits1 - 1) / 2); + } + *pOut = var1; + + return (ARM_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +/** + @} end of SQRT group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt new file mode 100644 index 0000000..59471ad --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt @@ -0,0 +1,128 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSPFiltering) + + +add_library(CMSISDSPFiltering STATIC) + +include(interpol) +interpol(CMSISDSPFiltering) + +configdsp(CMSISDSPFiltering ..) + +if (CONFIGTABLE AND ALLFAST) +target_compile_definitions(CMSISDSPFiltering PUBLIC ARM_ALL_FAST_TABLES) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_LMS_NORM_Q31) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_init_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_LMS_NORM_Q15) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_init_q15.c) +endif() + +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_32x64_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_32x64_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_init_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_stereo_df2T_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_stereo_df2T_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_fast_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_opt_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_fast_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_opt_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_fast_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_opt_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_q31.c) + + +### Includes +target_include_directories(CMSISDSPFiltering PUBLIC "${DSP}/../../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c new file mode 100644 index 0000000..7ce0cdb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: FilteringFunctions.c + * Description: Combination of all filtering function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_biquad_cascade_df1_32x64_init_q31.c" +#include "arm_biquad_cascade_df1_32x64_q31.c" +#include "arm_biquad_cascade_df1_f32.c" +#include "arm_biquad_cascade_df1_fast_q15.c" +#include "arm_biquad_cascade_df1_fast_q31.c" +#include "arm_biquad_cascade_df1_init_f32.c" +#include "arm_biquad_cascade_df1_init_q15.c" +#include "arm_biquad_cascade_df1_init_q31.c" +#include "arm_biquad_cascade_df1_q15.c" +#include "arm_biquad_cascade_df1_q31.c" +#include "arm_biquad_cascade_df2T_f32.c" +#include "arm_biquad_cascade_df2T_f64.c" +#include "arm_biquad_cascade_df2T_init_f32.c" +#include "arm_biquad_cascade_df2T_init_f64.c" +#include "arm_biquad_cascade_stereo_df2T_f32.c" +#include "arm_biquad_cascade_stereo_df2T_init_f32.c" +#include "arm_conv_f32.c" +#include "arm_conv_fast_opt_q15.c" +#include "arm_conv_fast_q15.c" +#include "arm_conv_fast_q31.c" +#include "arm_conv_opt_q15.c" +#include "arm_conv_opt_q7.c" +#include "arm_conv_partial_f32.c" +#include "arm_conv_partial_fast_opt_q15.c" +#include "arm_conv_partial_fast_q15.c" +#include "arm_conv_partial_fast_q31.c" +#include "arm_conv_partial_opt_q15.c" +#include "arm_conv_partial_opt_q7.c" +#include "arm_conv_partial_q15.c" +#include "arm_conv_partial_q31.c" +#include "arm_conv_partial_q7.c" +#include "arm_conv_q15.c" +#include "arm_conv_q31.c" +#include "arm_conv_q7.c" +#include "arm_correlate_f32.c" +#include "arm_correlate_fast_opt_q15.c" +#include "arm_correlate_fast_q15.c" +#include "arm_correlate_fast_q31.c" +#include "arm_correlate_opt_q15.c" +#include "arm_correlate_opt_q7.c" +#include "arm_correlate_q15.c" +#include "arm_correlate_q31.c" +#include "arm_correlate_q7.c" +#include "arm_fir_decimate_f32.c" +#include "arm_fir_decimate_fast_q15.c" +#include "arm_fir_decimate_fast_q31.c" +#include "arm_fir_decimate_init_f32.c" +#include "arm_fir_decimate_init_q15.c" +#include "arm_fir_decimate_init_q31.c" +#include "arm_fir_decimate_q15.c" +#include "arm_fir_decimate_q31.c" +#include "arm_fir_f32.c" +#include "arm_fir_fast_q15.c" +#include "arm_fir_fast_q31.c" +#include "arm_fir_init_f32.c" +#include "arm_fir_init_q15.c" +#include "arm_fir_init_q31.c" +#include "arm_fir_init_q7.c" +#include "arm_fir_interpolate_f32.c" +#include "arm_fir_interpolate_init_f32.c" +#include "arm_fir_interpolate_init_q15.c" +#include "arm_fir_interpolate_init_q31.c" +#include "arm_fir_interpolate_q15.c" +#include "arm_fir_interpolate_q31.c" +#include "arm_fir_lattice_f32.c" +#include "arm_fir_lattice_init_f32.c" +#include "arm_fir_lattice_init_q15.c" +#include "arm_fir_lattice_init_q31.c" +#include "arm_fir_lattice_q15.c" +#include "arm_fir_lattice_q31.c" +#include "arm_fir_q15.c" +#include "arm_fir_q31.c" +#include "arm_fir_q7.c" +#include "arm_fir_sparse_f32.c" +#include "arm_fir_sparse_init_f32.c" +#include "arm_fir_sparse_init_q15.c" +#include "arm_fir_sparse_init_q31.c" +#include "arm_fir_sparse_init_q7.c" +#include "arm_fir_sparse_q15.c" +#include "arm_fir_sparse_q31.c" +#include "arm_fir_sparse_q7.c" +#include "arm_iir_lattice_f32.c" +#include "arm_iir_lattice_init_f32.c" +#include "arm_iir_lattice_init_q15.c" +#include "arm_iir_lattice_init_q31.c" +#include "arm_iir_lattice_q15.c" +#include "arm_iir_lattice_q31.c" +#include "arm_lms_f32.c" +#include "arm_lms_init_f32.c" +#include "arm_lms_init_q15.c" +#include "arm_lms_init_q31.c" +#include "arm_lms_norm_f32.c" +#include "arm_lms_norm_init_f32.c" +#include "arm_lms_norm_init_q15.c" +#include "arm_lms_norm_init_q31.c" +#include "arm_lms_norm_q15.c" +#include "arm_lms_norm_q31.c" +#include "arm_lms_q15.c" +#include "arm_lms_q31.c" diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c new file mode 100644 index 0000000..ac2313f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_32x64_init_q31.c + * Description: High precision Q31 Biquad cascade filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1_32x64 + @{ + */ + +/** + @brief Initialization function for the Q31 Biquad cascade 32x64 filter. + @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure + @param[in] numStages number of 2nd order stages in the filter + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState points to state variables array and size of each state variable is 1.63 format. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the state array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q63_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1_32x64 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c new file mode 100644 index 0000000..9a284b8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c @@ -0,0 +1,458 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_32x64_q31.c + * Description: High precision Q31 Biquad cascade filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter + + This function implements a high precision Biquad cascade filter which operates on + Q31 data values. The filter coefficients are in 1.31 format and the state variables + are in 1.63 format. The double precision state variables reduce quantization noise + in the filter and provide a cleaner output. + These filters are particularly useful when implementing filters in which the + singularities are close to the unit circle. This is common for low pass or high + pass filters with very low cutoff frequencies. + + The function operates on blocks of input and output data + and each call to the function processes blockSize samples through + the filter. pSrc and pDst points to input and output arrays + containing blockSize Q31 values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. + \image html Biquad.gif "Single Biquad filter stage" + Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools use the difference equation + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+
+ In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library. + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages" + A 9th order filter would be realized with numStages=5 second order stages + with the coefficients for one of the stages configured as a first order filter + (b2=0 and a2=0). + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision. + The state variables are arranged in the array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ @par + The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values of data in 1.63 format. + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + + @par Init Function + There is also an associated initialization function which performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + For example, to statically initialize the filter instance structure use + 
+      arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; + postShift shift to be applied which is described in detail below. + @par Fixed-Point Behavior + Care must be taken while using Biquad Cascade 32x64 filter function. + Following issues must be considered: + - Scaling of coefficients + - Filter gain + - Overflow and saturation + + @par + Filter coefficients are represented as fractional values and + restricted to lie in the range [-1 +1). + The processing function has an additional scaling parameter postShift + which allows the filter coefficients to exceed the range [+1 -1). + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator" + This essentially scales the filter coefficients by 2^postShift. + For example, to realize the coefficients + 
+     {1.5, -0.8, 1.2, 1.6, -0.9}
+
+ set the Coefficient array to: + 
+     {0.75, -0.4, 0.6, 0.8, -0.45}
+
+ and set postShift=1 + @par + The second thing to keep in mind is the gain through the filter. + The frequency response of a Biquad filter is a function of its coefficients. + It is possible for the gain through the filter to exceed 1.0 meaning that the + filter increases the amplitude of certain frequencies. + This means that an input signal with amplitude < 1.0 may result in an output > 1.0 + and these are saturated or overflowed based on the implementation of the filter. + To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 + or the input signal must be scaled down so that the combination of input and filter are never overflowed. + @par + The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version. + This is described in the function specific documentation below. + */ + +/** + @addtogroup BiquadCascadeDF1_32x64 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade 32x64 filter. + @param[in] S points to an instance of the high precision Q31 Biquad cascade filter + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Details + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). + After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to + 1.31 format by discarding the low 32 bits. + @par + Two related functions are provided in the CMSIS DSP library. + - \ref arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator. + - \ref arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator. + */ + +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = (q31_t) (pState[0]); + Xn2 = (q31_t) (pState[1]); + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output value that is being computed and stored in destination buffer + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* The result is converted to 1.63 , Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut = acc_h; + + /* Read the second input into Xn2, to reuse the value */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc += b1 * x[n-1] */ + acc = (q63_t) Xn * b1; + + /* acc = b0 * x[n] */ + acc += (q63_t) Xn2 * b0; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn1 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn2, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn1, a2); + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Read the third input into Xn1, to reuse the value */ + Xn1 = *pIn++; + + /* The result is converted to 1.31 */ + /* Store the output in the destination buffer. */ + *(pOut + 1U) = acc_h; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn1 * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn2 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* The result is converted to 1.63, Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *(pOut + 2U) = acc_h; + + /* Read the fourth input into Xn, to reuse the value */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn2, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn1, a2); + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *(pOut + 3U) = acc_h; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* update output pointer */ + pOut += 4U; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + /* Yn1 = acc << shift; */ + + /* Store the output in the destination buffer in 1.31 format. */ +/* *pOut++ = (q31_t) (acc >> (32 - shift)); */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +} + +/** + @} end of BiquadCascadeDF1_32x64 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c new file mode 100644 index 0000000..d28509d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_f32.c + * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure + + This set of functions implements arbitrary order recursive (IIR) filters. + The filters are implemented as a cascade of second order Biquad sections. + The functions support Q15, Q31 and floating-point data types. + Fast version of Q15 and Q31 also available. + + The functions operate on blocks of input and output data and each call to the function + processes blockSize samples through the filter. + pSrc points to the array of input data and + pDst points to the array of output data. + Both arrays contain blockSize values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. + \image html Biquad.gif "Single Biquad filter stage" + Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools use the difference equation + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+
+ In this case the feedback coefficients a1 and a2 + must be negated when used with the CMSIS DSP Library. + + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages" + A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0). + + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ + @par + The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Init Function + There is also an associated initialization function for each data type. + The initialization function performs following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+      arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+      arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; + postShift shift to be applied. + + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions. + Following issues must be considered: + - Scaling of coefficients + - Filter gain + - Overflow and saturation + + @par Scaling of coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift + which allow the filter coefficients to exceed the range [+1 -1). + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator" + This essentially scales the filter coefficients by 2^postShift. + For example, to realize the coefficients + 
+     {1.5, -0.8, 1.2, 1.6, -0.9}
+
+ set the pCoeffs array to: + 
+     {0.75, -0.4, 0.6, 0.8, -0.45}
+
+ and set postShift=1 + + @par Filter gain + The frequency response of a Biquad filter is a function of its coefficients. + It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. + This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. + To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed. + + @par Overflow and saturation + For Q15 and Q31 versions, it is described separately as part of the function specific documentation below. + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the floating-point Biquad cascade filter. + @param[in] S points to an instance of the floating-point Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_NEON) +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* Simulates the accumulator */ + + uint32_t sample, stage = S->numStages; /* loop counters */ + + float32x4_t Xn; + float32x2_t Yn; + float32x2_t a; + float32x4_t b; + + float32x4_t x,tmp; + float32x2_t t; + float32x2x2_t y; + + float32_t Xns; + + while (stage > 0U) + { + /* Reading the coefficients */ + Xn = vld1q_f32(pState); + Yn = vld1_f32(pState + 2); + + b = vld1q_f32(pCoeffs); + b = vrev64q_f32(b); + b = vcombine_f32(vget_high_f32(b), vget_low_f32(b)); + + a = vld1_f32(pCoeffs + 3); + a = vrev64_f32(a); + b[0] = 0.0; + pCoeffs += 5; + + /* Reading the pState values */ + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* The variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first 4 inputs */ + x = vld1q_f32(pIn); + + pIn += 4; + + tmp = vextq_f32(Xn, x, 1); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + tmp = vextq_f32(Xn, x, 2); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + y.val[0] = Yn; + + tmp = vextq_f32(Xn, x, 3); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + Xn = x; + t = vmul_f32(vget_high_f32(b), vget_high_f32(Xn)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(Xn)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + y.val[1] = Yn; + + tmp = vcombine_f32(y.val[0], y.val[1]); + + /* Store the 4 outputs and increment the pointer */ + vst1q_f32(pOut, tmp); + pOut += 4; + + /* Decrement the loop counter */ + sample--; + } + + /* If the block size is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + sample = blockSize & 0x3U; + + while (sample > 0U) + { + /* Read the input */ + Xns = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b[1] * Xn[2]) + (b[2] * Xn[3]) + (b[3] * Xns) + (a[0] * Yn[0]) + (a[1] * Yn[1]); + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn[2] = Xn[3]; + Xn[3] = Xns; + Yn[0] = Yn[1]; + Yn[1] = acc; + + /* Decrement the loop counter */ + sample--; + + } + + vst1q_f32(pState,vcombine_f32(vrev64_f32(vget_high_f32(Xn)),vrev64_f32(Yn))); + pState += 4; + /* Store the updated state variables back into the pState array */ + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + } +} + +#else +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t Xn; /* Temporary input */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c new file mode 100644 index 0000000..1a568d7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c @@ -0,0 +1,250 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_fast_q15.c + * Description: Fast processing function for the Q15 Biquad cascade filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q15 Biquad cascade filter (fast variant). + @param[in] S points to an instance of the Q15 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process per call + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). + The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits. + @remark + Refer to \ref arm_biquad_cascade_df1_q15() for a slower implementation of this function + which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. + Use the function \ref arm_biquad_cascade_df1_init_q15() to initialize the filter structure. + */ + +void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t acc; /* Accumulator */ + q31_t in; /* Temporary variable to hold input value */ + q31_t out; /* Temporary variable to hold output value */ + q31_t b0; /* Temporary variable to hold bo value */ + q31_t b1, a1; /* Filter coefficients */ + q31_t state_in, state_out; /* Filter state variables */ + int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Read the b0 and 0 coefficients using SIMD */ + b0 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the b1 and b2 coefficients using SIMD */ + b1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the a1 and a2 coefficients using SIMD */ + a1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the input state values from the state buffer: x[n-1], x[n-2] */ + state_in = read_q15x2_ia (&pState); + + /* Read the output state values from the state buffer: y[n-1], y[n-2] */ + state_out = read_q15x2_da (&pState); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 2 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 2 outputs at a time */ + sample = blockSize >> 1U; + + while (sample > 0U) + { + + /* Read the input */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUAD(b0, in); + /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, (in >> 16), 16); + state_out = __PKHBT(state_out >> 16, (out), 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUADX(b0, in); + /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Store the output in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(out, state_out >> 16, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in >> 16, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = (blockSize & 0x1U); + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + in = *pIn++; + + /* out = b0 * x[n] + 0 * 0 */ +#ifndef ARM_MATH_BIG_ENDIAN + out = __SMUAD(b0, in); +#else + out = __SMUADX(b0, in); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) out; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent (numStages - 1) occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Store the updated state variables back into the state array */ + write_q15x2_ia(&pState, state_in); + write_q15x2_ia(&pState, state_out); + + /* Decrement loop counter */ + stage--; + + } while (stage > 0U); +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c new file mode 100644 index 0000000..586296b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c @@ -0,0 +1,296 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_fast_q31.c + * Description: Processing function for the Q31 Fast Biquad cascade DirectFormI(DF1) filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade filter (fast variant). + @param[in] S points to an instance of the Q31 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process per call + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function + arm_biquad_cascade_df1_init_q31() to initialize filter structure. + @remark + Refer to \ref arm_biquad_cascade_df1_q31() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure. + Use the function \ref arm_biquad_cascade_df1_init_q31() to initialize the filter structure. + */ + +void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Source pointer */ + q31_t *pOut = pDst; /* Destination pointer */ + q31_t *pState = S->pState; /* pState pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t acc = 0; /* Accumulator */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + q31_t Xn; /* Temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variables acc ... acc3 hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);*/ + mult_32x32_keep32_R(acc, b1, Xn1); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b0, Xn); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 , Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Read the second input */ + Xn2 = *(pIn + 1U); + + /* Store the output in the destination buffer. */ + *pOut = Yn2; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn2); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn1); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn2); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Read the third input */ + Xn1 = *(pIn + 2U); + + /* Store the output in the destination buffer. */ + *(pOut + 1U) = Yn1; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn1); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn2); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31, Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Read the forth input */ + Xn = *(pIn + 3U); + + /* Store the output in the destination buffer. */ + *(pOut + 2U) = Yn2; + pIn += 4U; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn); + /* acc += b1 * x[n-1] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn1); + /* acc += b[2] * x[n-2] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn2); + /* acc += a2 * y[n-2] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn1); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + Xn2 = Xn1; + + /* The result is converted to 1.31, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Xn1 = Xn */ + Xn1 = Xn; + + /* Store the output in the destination buffer. */ + *(pOut + 3U) = Yn1; + pOut += 4U; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = (blockSize & 0x3U); + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn1); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 */ + acc = acc << shift; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* Store the output in the destination buffer. */ + *pOut++ = acc; + + /* decrement loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c new file mode 100644 index 0000000..f51c262 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_f32.c + * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the floating-point Biquad cascade filter. + @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c new file mode 100644 index 0000000..c2e542c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_q15.c + * Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the Q15 Biquad cascade filter. + @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 6*numStages values. + The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4. + @par + The state variables are stored in the array pState. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c new file mode 100644 index 0000000..8637889 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c @@ -0,0 +1,95 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_q31.c + * Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the Q31 Biquad cascade filter. + @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c new file mode 100644 index 0000000..9e23897 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c @@ -0,0 +1,363 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_q15.c + * Description: Processing function for the Q15 Biquad cascade DirectFormI(DF1) filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q15 Biquad cascade filter. + @param[in] S points to an instance of the Q15 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the location where the output result is written + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits. + Finally, the result is saturated to 1.15 format. + @remark + Refer to \ref arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter. + */ + +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q31_t in; /* Temporary variable to hold input value */ + q31_t out; /* Temporary variable to hold output value */ + q31_t b0; /* Temporary variable to hold bo value */ + q31_t b1, a1; /* Filter coefficients */ + q31_t state_in, state_out; /* Filter state variables */ + q31_t acc_l, acc_h; + q63_t acc; /* Accumulator */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + int32_t uShift = (32 - lShift); + + do + { + /* Read the b0 and 0 coefficients using SIMD */ + b0 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the b1 and b2 coefficients using SIMD */ + b1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the a1 and a2 coefficients using SIMD */ + a1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the input state values from the state buffer: x[n-1], x[n-2] */ + state_in = read_q15x2_ia (&pState); + + /* Read the output state values from the state buffer: y[n-1], y[n-2] */ + state_out = read_q15x2_da (&pState); + + /* Apply loop unrolling and compute 2 output values simultaneously. */ + /* The variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + sample = blockSize >> 1U; + + /* First part of the processing with loop unrolling. Compute 2 outputs at a time. + ** a second loop below computes the remaining 1 sample. */ + while (sample > 0U) + { + + /* Read the input */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUAD(b0, in); + + /* acc += b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, (in >> 16), 16); + state_out = __PKHBT(state_out >> 16, (out), 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUADX(b0, in); + /* acc += b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Store the output in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(out, state_out >> 16, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in >> 16, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + sample--; + } + + /* If the blockSize is not a multiple of 2, compute any remaining output samples here. + ** No loop unrolling is used. */ + + if ((blockSize & 0x1U) != 0U) + { + /* Read the input */ + in = *pIn++; + + /* out = b0 * x[n] + 0 * 0 */ +#ifndef ARM_MATH_BIG_ENDIAN + out = __SMUAD(b0, in); +#else + out = __SMUADX(b0, in); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* acc = b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) out; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + } + + /* The first stage goes from the input wire to the output wire. */ + /* Subsequent numStages occur in-place in the output wire */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Store the updated state variables back into the state array */ + write_q15x2_ia (&pState, state_in); + write_q15x2_ia (&pState, state_out); + + /* Decrement loop counter */ + stage--; + + } while (stage > 0U); + +#else + + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q63_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q31_t) b0 *Xn; + + /* acc += b1 * x[n-1] */ + acc += (q31_t) b1 *Xn1; + /* acc += b[2] * x[n-2] */ + acc += (q31_t) b2 *Xn2; + /* acc += a1 * y[n-1] */ + acc += (q31_t) a1 *Yn1; + /* acc += a2 * y[n-2] */ + acc += (q31_t) a2 *Yn2; + + /* The result is converted to 1.31 */ + acc = __SSAT((acc >> shift), 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c new file mode 100644 index 0000000..011e21d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c @@ -0,0 +1,247 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_q31.c + * Description: Processing function for the Q31 Biquad cascade filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade filter. + @param[in] S points to an instance of the Q31 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). + After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to + 1.31 format by discarding the low 32 bits. + @remark + Refer to \ref arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter. + */ + +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Source pointer */ + q31_t *pOut = pDst; /* Destination pointer */ + q31_t *pState = S->pState; /* pState pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q63_t acc; /* Accumulator */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + q31_t Xn; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc_l, acc_h; /* temporary output variables */ +#endif + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31 , Yn2 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn2) + ((q63_t) b1 * Xn) + ((q63_t) b2 * Xn1) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn1) + ((q63_t) b1 * Xn2) + ((q63_t) b2 * Xn) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31, Yn2 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31 */ + acc = acc >> lShift; + + /* Store output in destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q31_t) acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c new file mode 100644 index 0000000..596b434 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c @@ -0,0 +1,523 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f32.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_NEON) + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc1; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1; /* temporary input */ + float32_t d1, d2; /* state variables */ + uint32_t sample, stageCnt,stage = S->numStages; /* loop counters */ + + + float32_t Xn2, Xn3, Xn4; /* Input State variables */ + float32_t acc2, acc3, acc4; /* accumulator */ + + + float32_t p0, p1, p2, p3, p4, A1; + + float32x4_t XnV, YnV; + float32x4x2_t dV; + float32x4_t zeroV = vdupq_n_f32(0.0); + float32x4_t t1,t2,t3,t4,b1V,b2V,a1V,a2V,s; + + /* Loop unrolling. Compute 4 outputs at a time */ + stageCnt = stage >> 2; + + while (stageCnt > 0U) + { + /* Reading the coefficients */ + t1 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t2 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t3 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t4 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + b1V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + b2V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + a1V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + a2V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + /* Reading the state values */ + dV = vld2q_f32(pState); + + sample = blockSize; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + + XnV = vdupq_n_f32(*pIn++); + + s = dV.val[0]; + YnV = s; + + s = vextq_f32(zeroV,dV.val[0],3); + YnV = vmlaq_f32(YnV, t1, s); + + s = vextq_f32(zeroV,dV.val[0],2); + YnV = vmlaq_f32(YnV, t2, s); + + s = vextq_f32(zeroV,dV.val[0],1); + YnV = vmlaq_f32(YnV, t3, s); + + YnV = vmlaq_f32(YnV, t4, XnV); + + s = vextq_f32(XnV,YnV,3); + + dV.val[0] = vmlaq_f32(dV.val[1], s, b1V); + dV.val[0] = vmlaq_f32(dV.val[0], YnV, a1V); + + dV.val[1] = vmulq_f32(s, b2V); + dV.val[1] = vmlaq_f32(dV.val[1], YnV, a2V); + + *pOut++ = YnV[3]; + + sample--; + } + + /* Store the updated state variables back into the state array */ + vst2q_f32(pState,dV); + pState += 8; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stageCnt--; + + } + + /* Tail */ + stageCnt = stage & 3; + + while (stageCnt > 0U) + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn1 = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc1 = (b0 * Xn1) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = ((b1 * Xn1) + (a1 * acc1)) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn1) + (a2 * acc1); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stageCnt--; + } +} +#else +LOW_OPTIMIZATION_ENTER +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc1; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1; /* Temporary input */ + float32_t d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +LOW_OPTIMIZATION_EXIT +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c new file mode 100644 index 0000000..a8af8ce --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c @@ -0,0 +1,443 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f64.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters +*/ + +/** + @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure + + This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure. + The filters are implemented as a cascade of second order Biquad sections. + These functions provide a slight memory savings as compared to the direct form I Biquad filter functions. + Only floating-point data is supported. + + This function operate on blocks of input and output data and each call to the function + processes blockSize samples through the filter. + pSrc points to the array of input data and + pDst points to the array of output data. + Both arrays contain blockSize values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+     y[n] = b0 * x[n] + d1
+     d1 = b1 * x[n] + a1 * y[n] + d2
+     d2 = b2 * x[n] + a2 * y[n]
+
+ where d1 and d2 represent the two state values. + @par + A Biquad filter using a transposed Direct Form II structure is shown below. + \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad" + Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools flip the sign of the feedback coefficients: + 
+     y[n] = b0 * x[n] + d1;
+     d1 = b1 * x[n] - a1 * y[n] + d2;
+     d2 = b2 * x[n] - a2 * y[n];
+
+ In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library. + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + A 9th order filter would be realized with numStages=5 second order stages with the + coefficients for one of the stages configured as a first order filter (b2=0 and a2=0). + @par + pState points to the state variable array. + Each Biquad stage has 2 state variables d1 and d2. + The state variables are arranged in the pState array as: + 
+      {d11, d12, d21, d22, ...}
+
+ where d1x refers to the state variables for the first Biquad and + d2x refers to the state variables for the second Biquad. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + @par + The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II. + The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types. + That is why the Direct Form I structure supports Q15 and Q31 data types. + The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2. + Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad. + The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + + @par Init Functions + There is also an associated initialization function. + The initialization function performs following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + For example, to statically initialize the instance structure use + 
+      arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};
+      arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer. + pCoeffs is the address of the coefficient buffer; +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +LOW_OPTIMIZATION_ENTER +void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + + float64_t *pIn = pSrc; /* Source pointer */ + float64_t *pOut = pDst; /* Destination pointer */ + float64_t *pState = S->pState; /* State pointer */ + float64_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float64_t acc1; /* Accumulator */ + float64_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float64_t Xn1; /* Temporary input */ + float64_t d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +LOW_OPTIMIZATION_EXIT + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c new file mode 100644 index 0000000..23cf2d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c @@ -0,0 +1,211 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f32.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order + in the not Neon version. + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + + For Neon version, this array is bigger. If numstages = 4x + y, then the array has size: + 32*x + 5*y + and it must be initialized using the function + arm_biquad_cascade_df2T_compute_coefs_f32 which is taking the + standard array coefficient as parameters. + + But, an array of 8*numstages is a good approximation. + + Then, the initialization can be done with: + 
+                   arm_biquad_cascade_df2T_init_f32(&SNeon, nbCascade, neonCoefs, stateNeon);
+                   arm_biquad_cascade_df2T_compute_coefs_f32(&SNeon,nbCascade,coefs);
+
+ + @par In this example, neonCoefs is a bigger array of size 8 * numStages. + coefs is the standard array: + + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +#if defined(ARM_MATH_NEON) +/* + +Must be called after initializing the biquad instance. +pCoeffs has size 5 * nbCascade +Whereas the pCoeffs for the init has size (4*4 + 4*4)* nbCascade + +So this pCoeffs is the one which would be used for the not Neon version. +The pCoeffs passed in init is bigger than the one for the not Neon version. + +*/ +void arm_biquad_cascade_df2T_compute_coefs_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs) +{ + uint8_t cnt; + float32_t *pDstCoeffs; + float32_t b0[4],b1[4],b2[4],a1[4],a2[4]; + + pDstCoeffs = S->pCoeffs; + + cnt = numStages >> 2; + while(cnt > 0) + { + for(int i=0;i<4;i++) + { + b0[i] = pCoeffs[0]; + b1[i] = pCoeffs[1]; + b2[i] = pCoeffs[2]; + a1[i] = pCoeffs[3]; + a2[i] = pCoeffs[4]; + pCoeffs += 5; + } + + /* Vec 1 */ + *pDstCoeffs++ = 0; + *pDstCoeffs++ = b0[1]; + *pDstCoeffs++ = b0[2]; + *pDstCoeffs++ = b0[3]; + + /* Vec 2 */ + *pDstCoeffs++ = 0; + *pDstCoeffs++ = 0; + *pDstCoeffs++ = b0[1] * b0[2]; + *pDstCoeffs++ = b0[2] * b0[3]; + + /* Vec 3 */ + *pDstCoeffs++ = 0; + *pDstCoeffs++ = 0; + *pDstCoeffs++ = 0; + *pDstCoeffs++ = b0[1] * b0[2] * b0[3]; + + /* Vec 4 */ + *pDstCoeffs++ = b0[0]; + *pDstCoeffs++ = b0[0] * b0[1]; + *pDstCoeffs++ = b0[0] * b0[1] * b0[2]; + *pDstCoeffs++ = b0[0] * b0[1] * b0[2] * b0[3]; + + /* Vec 5 */ + *pDstCoeffs++ = b1[0]; + *pDstCoeffs++ = b1[1]; + *pDstCoeffs++ = b1[2]; + *pDstCoeffs++ = b1[3]; + + /* Vec 6 */ + *pDstCoeffs++ = b2[0]; + *pDstCoeffs++ = b2[1]; + *pDstCoeffs++ = b2[2]; + *pDstCoeffs++ = b2[3]; + + /* Vec 7 */ + *pDstCoeffs++ = a1[0]; + *pDstCoeffs++ = a1[1]; + *pDstCoeffs++ = a1[2]; + *pDstCoeffs++ = a1[3]; + + /* Vec 8 */ + *pDstCoeffs++ = a2[0]; + *pDstCoeffs++ = a2[1]; + *pDstCoeffs++ = a2[2]; + *pDstCoeffs++ = a2[3]; + + cnt--; + } + + cnt = numStages & 0x3; + while(cnt > 0) + { + *pDstCoeffs++ = *pCoeffs++; + *pDstCoeffs++ = *pCoeffs++; + *pDstCoeffs++ = *pCoeffs++; + *pDstCoeffs++ = *pCoeffs++; + *pDstCoeffs++ = *pCoeffs++; + cnt--; + } + +} +#endif + +void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c new file mode 100644 index 0000000..fe6901e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f64.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure + @param[in] numStages number of 2nd order stages in the filter + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float64_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c new file mode 100644 index 0000000..14ae008 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c @@ -0,0 +1,285 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_f32.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +LOW_OPTIMIZATION_ENTER +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc1a, acc1b; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1a, Xn1b; /* Temporary input */ + float32_t d1a, d2a, d1b, d2b; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 outputs at a time */ + sample = blockSize >> 3U; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 2 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 3 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 4 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 5 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 6 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 7 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 8 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x7U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1a; + pState[1] = d2a; + + pState[2] = d1b; + pState[3] = d2b; + + pState += 4U; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} +LOW_OPTIMIZATION_EXIT +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c new file mode 100644 index 0000000..d398f18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_init_f32.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2 for each channel. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c new file mode 100644 index 0000000..8fa1308 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c @@ -0,0 +1,816 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_f32.c + * Description: Convolution of floating-point sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup Conv Convolution + + Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector. + Convolution is similar to correlation and is frequently used in filtering and data analysis. + The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types. + The library also provides fast versions of the Q15 and Q31 functions. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and + srcBLen samples respectively. Then the convolution + 
+     c[n] = a[n] * b[n]
+
+ @par + is defined as + \image html ConvolutionEquation.gif + @par + Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2. + pSrcA points to the first input vector of length srcALen and + pSrcB points to the second input vector of length srcBLen. + The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result. + @par + Conceptually, when two signals a[n] and b[n] are convolved, + the signal b[n] slides over a[n]. + For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together. + @par + Note that convolution is a commutative operation: + 
+     a[n] * b[n] = b[n] * a[n].
+
+ @par + This means that switching the A and B arguments to the convolution functions has no effect. + + @par Fixed-Point Behavior + Convolution requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + */ + +void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const float32_t *pIn1; /* InputA pointer */ + const float32_t *pIn2; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */ + float32_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + float32_t acc0, acc1, acc2, acc3; /* Accumulators */ + float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ +#if defined(ARM_MATH_NEON) + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); +#endif /* #if defined(ARM_MATH_NEON) */ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + res = vdupq_n_f32(0) ; + accum = vdup_n_f32(0); + + /* Compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + + while (k > 0U) + { + vec1 = vld1q_f32(px); + vec2 = vld1q_f32(py-3); + vec2 = vrev64q_f32(vec2); + vec2 = vcombine_f32(vget_high_f32(vec2), vget_low_f32(vec2)); + + res = vmlaq_f32(res,vec1, vec2); + + /* Increment pointers */ + px += 4; + py -= 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count & 3; +#else + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* x[1] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* x[2] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* x[3] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#endif /* #if defined(ARM_MATH_NEON) */ + +#else + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + +#if defined(ARM_MATH_NEON) + float32x4_t c; + float32x4_t x1v; + float32x4_t x2v; + uint32x4_t x1v_u; + uint32x4_t x2v_u; + uint32x4_t x_u; + float32x4_t x; + float32x4_t res = vdupq_n_f32(0) ; +#endif /* #if defined(ARM_MATH_NEON) */ + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + +#if defined(ARM_MATH_NEON) + res = vdupq_n_f32(0) ; + + x1v = vld1q_f32(px); + x2v = vld1q_f32(px+4); + + do + { + c = vld1q_f32(py-3); + + px += 4; + x = x1v; + res = vmlaq_n_f32(res,x,c[3]); + + x = vextq_f32(x1v,x2v,1); + + res = vmlaq_n_f32(res,x,c[2]); + + x = vextq_f32(x1v,x2v,2); + + res = vmlaq_n_f32(res,x,c[1]); + + x = vextq_f32(x1v,x2v,3); + + res = vmlaq_n_f32(res,x,c[0]); + + py -= 4; + + x1v = x2v ; + x2v = vld1q_f32(px+4); + + } while (--k); + + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3; + + x1v = vld1q_f32(px); + px += 4; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *(py--); + + res = vmlaq_n_f32(res,x1v,c0); + + /* Reuse the present samples for the next MAC */ + x1v[0] = x1v[1]; + x1v[1] = x1v[2]; + x1v[2] = x1v[3]; + + x1v[3] = *(px++); + + /* Decrement the loop counter */ + k--; + } + + acc0 = res[0]; + acc1 = res[1]; + acc2 = res[2]; + acc3 = res[3]; + +#else + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 += x3 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 += x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 += x1 * c0; + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *(px + 3U); + px += 4U; + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } +#endif /* #if defined(ARM_MATH_NEON) */ + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc0; + *pOut++ = acc1; + *pOut++ = acc2; + *pOut++ = acc3; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined (ARM_MATH_NEON)*/ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined(ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + +#if defined (ARM_MATH_NEON) + float32x4_t res = vdupq_n_f32(0) ; + float32x4_t x = vdupq_n_f32(0) ; + float32x4_t y = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0) ; + + /* First part of the processing. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py-3); + + y = vrev64q_f32(y); + y = vcombine_f32(vget_high_f32(y), vget_low_f32(y)); + + res = vmlaq_f32(res,x,y); + + px += 4 ; + py -= 4 ; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3U; + +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#endif /* if defined (ARM_MATH_NEON) */ +#else + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined(ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t res = vdupq_n_f32(0) ; + float32x4_t x = vdupq_n_f32(0) ; + float32x4_t y = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0) ; + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py-3); + + y = vrev64q_f32(y); + y = vcombine_f32(vget_high_f32(y), vget_low_f32(y)); + + res = vmlaq_f32(res,x,y); + + px += 4 ; + py -= 4 ; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /* #if defined (ARM_MATH_NEON) */ + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL)*/ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ( pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c new file mode 100644 index 0000000..ed2aea9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c @@ -0,0 +1,366 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_opt_q15.c + * Description: Fast Q15 Convolution + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1 + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2 + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results + but provides only a single guard bit. There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + */ + +void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q31_t acc0; /* Accumulators */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch1 buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + + /* Initialization of pIn2 pointer */ + pIn2 = py; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumlate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumlate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumlate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c new file mode 100644 index 0000000..3102a05 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c @@ -0,0 +1,663 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_q15.c + * Description: Fast Q15 Convolution + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1 + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results + but provides only a single guard bit. There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + */ + +void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* -------------------- + * Stage2 process + * -------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLADX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLADX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLADX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLADX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLADX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLADX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLADX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py+1); + +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + + /* Read y[srcBLen - 7] */ + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD(x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((acc0 >> 15), (acc1 >> 15), 16)); + write_q15x2_ia (&pOut, __PKHBT((acc2 >> 15), (acc3 >> 15), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((acc1 >> 15), (acc0 >> 15), 16)); + write_q15x2_ia (&pOut, __PKHBT((acc3 >> 15), (acc2 >> 15), 16)); +#endif /*#ifndef ARM_MATH_BIG_ENDIAN*/ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = blockSize3 >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the loop counter */ + blockSize3--; + } + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c new file mode 100644 index 0000000..e87eddc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c @@ -0,0 +1,558 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_q31.c + * Description: Fast Q31 Convolution + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are accumulated in a 32-bit register in 2.30 format. + Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + @remark + Refer to \ref arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. + */ + +void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[1] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[2] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[3] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[srcBLen - 3] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[srcBLen - 3] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[srcBLen - 3] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 << 1); + *pOut++ = (q31_t) (acc1 << 1); + *pOut++ = (q31_t) (acc2 << 1); + *pOut++ = (q31_t) (acc3 << 1); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c new file mode 100644 index 0000000..6ad34cd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c @@ -0,0 +1,362 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_opt_q15.c + * Description: Convolution of Q15 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + @remark + Refer to \ref arm_conv_fast_q15() for a faster but less precise version of this function. + */ + +void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q63_t acc0; /* Accumulators */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch1 buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + + /* Initialization of pIn2 pointer */ + pIn2 = py; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumlate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumlate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumlate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c new file mode 100644 index 0000000..fb9e2ec --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c @@ -0,0 +1,360 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_opt_q7.c + * Description: Convolution of Q7 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + */ + +void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */ + q15_t x4; /* Temporary input variable */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + const q7_t *px; /* Temporary input1 pointer */ + q7_t *pOut = pDst; /* Output pointer */ + q7_t out0, out1, out2, out3; /* Temporary variables */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* points to smaller length sequence */ + px = pIn2 + srcBLen - 1; + + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) * pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pIn2 pointer */ + pIn2 = (q7_t *) py; + + pScr2 = py; + + /* Actual convolution process starts here */ + blkCnt = (srcALen + srcBLen - 1U) >> 2U; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumlate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumlate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + out0 = (q7_t) (__SSAT(acc0 >> 7U, 8)); + out1 = (q7_t) (__SSAT(acc1 >> 7U, 8)); + out2 = (q7_t) (__SSAT(acc2 >> 7U, 8)); + out3 = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + acc0 += (*pScr1++ * *pScr2++); + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c new file mode 100644 index 0000000..e25f9ab --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c @@ -0,0 +1,676 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_f32.c + * Description: Partial convolution of floating-point sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup PartialConv Partial Convolution + + Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated. + Each function has two additional arguments. + firstIndex specifies the starting index of the subset of output samples. + numPoints is the number of output samples to compute. + The function computes the output in the range + [firstIndex, ..., firstIndex+numPoints-1]. + The output array pDst contains numPoints values. + + The allowable range of output indices is [0 srcALen+srcBLen-2]. + If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR. + Otherwise the functions return ARM_MATH_SUCCESS. + \note Refer to \ref arm_conv_f32() for details on fixed point behavior. + + @par Fast Versions + Fast versions are supported for Q31 and Q15 of partial convolution. + Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of partial convolution + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + */ + +arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */ + float32_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3; /* Accumulator */ + float32_t x0, x1, x2, x3, c0; /* Temporary variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0; + blockSize2 = ((int32_t) check - blockSize3) - (blockSize1 + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + firstIndex; + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* x[1] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* x[2] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* x[3] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc1; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 += x3 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 += x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 += x1 * c0; + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc0; + *pOut++ = acc1; + *pOut++ = acc2; + *pOut++ = acc3; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ( pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum; + } + + /* Set status as ARM_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c new file mode 100644 index 0000000..7166b57 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c @@ -0,0 +1,387 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_opt_q15.c + * Description: Fast Q15 Partial convolution + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2 + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + q31_t acc0; /* Accumulator */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + arm_status status; /* Status variable */ + q31_t x1; /* Temporary variables to hold state and coefficient values */ + q31_t y1; /* State variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulator */ + q31_t x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y2; /* State variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Initialization of pIn2 pointer */ + pIn2 = py; + + pScratch1 += firstIndex; + + pOut = pDst + firstIndex; + + /* Actual convolution process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumlate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumlate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumlate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumlate */ + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numPoints & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numPoints; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumlate */ + acc0 = __SMLAD(x1, y1, acc0); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c new file mode 100644 index 0000000..535fbc7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c @@ -0,0 +1,700 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_q15.c + * Description: Fast Q15 Partial convolution + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + @remark + Refer to \ref arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2 - 1U; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLADX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLADX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLADX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLADX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLADX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLADX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLADX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py + 1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD (x0, c0, acc0); + acc1 = __SMLAD (x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD (x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(acc0 >> 15, acc1 >> 15, 16)); + write_q15x2_ia (&pOut, __PKHBT(acc2 >> 15, acc3 >> 15, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(acc1 >> 15, acc0 >> 15, 16)); + write_q15x2_ia (&pOut, __PKHBT(acc3 >> 15, acc2 >> 15, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + No loop unrolling is used. */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = count >> 2U; + + while ((j > 0U) && (blockSize3 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c new file mode 100644 index 0000000..f232d51 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c @@ -0,0 +1,618 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_q31.c + * Description: Fast Q31 Partial convolution + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. + */ + +arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t j, k, count, check, blkCnt; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[1] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[2] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[3] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 << 1); + *pOut++ = (q31_t) (acc1 << 1); + *pOut++ = (q31_t) (acc2 << 1); + *pOut++ = (q31_t) (acc3 << 1); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c new file mode 100644 index 0000000..21999d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c @@ -0,0 +1,386 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_opt_q15.c + * Description: Partial convolution of Q15 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q15() for a faster but less precise version of this function. + */ + +arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + q63_t acc0; /* Accumulator */ + q31_t x1; /* Temporary variables to hold state and coefficient values */ + q31_t y1; /* State variables */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + arm_status status; /* Status variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulator */ + q31_t x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y2; /* State variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Initialization of pIn2 pointer */ + pIn2 = py; + + pScratch1 += firstIndex; + + pOut = pDst + firstIndex; + + /* Actual convolution process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumlate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumlate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumlate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numPoints & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numPoints; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + + acc0 = __SMLALD(x1, y1, acc0); + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c new file mode 100644 index 0000000..811f386 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c @@ -0,0 +1,390 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_opt_q7.c + * Description: Partial convolution of Q7 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + */ + +arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */ + q15_t x4; /* Temporary input variable */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + const q7_t *px; /* Temporary input1 pointer */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulator */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + arm_status status; + q7_t *pOut = pDst; /* Output pointer */ + q7_t out0, out1, out2, out3; /* Temporary variables */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2; + + /* points to smaller length sequence */ + px = pIn2 + srcBLen - 1; + + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pIn2 pointer */ + pIn2 = (q7_t *) py; + + pScr2 = py; + + pOut = pDst + firstIndex; + + pScratch1 += firstIndex; + + /* Actual convolution process starts here */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialize temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumulators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumlate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumlate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + out0 = (q7_t) (__SSAT(acc0 >> 7U, 8)); + out1 = (q7_t) (__SSAT(acc1 >> 7U, 8)); + out2 = (q7_t) (__SSAT(acc2 >> 7U, 8)); + out3 = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (numPoints) & 0x3; + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x1, y1, acc0); + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumlate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c new file mode 100644 index 0000000..55272ea --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c @@ -0,0 +1,752 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q15.c + * Description: Partial convolution of Q15 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers. + */ + +arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */ + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt, check; + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2 - 1U; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLALDX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLALDX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLALDX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLALDX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLALDX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLALDX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py+1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD (x0, c0, acc0); + acc1 = __SMLALD (x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD (x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + No loop unrolling is used. */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = count >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c new file mode 100644 index 0000000..d0f0122 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c @@ -0,0 +1,634 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q31.c + * Description: Partial convolution of Q31 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q31() for a faster but less precise implementation of this function. + */ + +arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q63_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulator */ + q31_t x0, x1, x2, c0; /* Temporary variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py--); + + /* x[1] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py--); + + /* x[2] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py--); + + /* x[3] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll over blkCnt */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *(py); + + /* Read x[2] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += (q63_t) x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += (q63_t) x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += (q63_t) x2 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *(py - 1U); + + /* Read x[3] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += (q63_t) x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += (q63_t) x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += (q63_t) x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *(py - 2U); + + /* Read x[4] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += (q63_t) x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += (q63_t) x0 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += (q63_t) x1 * c0; + + + px += 3U; + + py -= 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += (q63_t) x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += (q63_t) x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += (q63_t) x2 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 >> 31); + *pOut++ = (q31_t) (acc1 >> 31); + *pOut++ = (q31_t) (acc2 >> 31); + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t) (sum >> 31U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c new file mode 100644 index 0000000..9b0228c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c @@ -0,0 +1,753 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q7.c + * Description: Partial convolution of Q7 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_opt_q7() for a faster implementation of this function. + */ + +arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; /* Loop counters */ + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulator */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 1] , y[srcBLen - 2] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[0] * y[srcBLen - 1] */ + /* x[1] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 3] , y[srcBLen - 4] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[2] * y[srcBLen - 3] */ + /* x[3] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read y[srcBLen - 2] sample */ + c1 = *py--; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 1] and y[srcBLen - 2] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read y[srcBLen - 4] sample */ + c1 = *py--; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 3] and y[srcBLen - 4] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q31_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q31_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q31_t) x2 * c0); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += ((q31_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB; /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * (pIn2[i - j])); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c new file mode 100644 index 0000000..ad2b629 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c @@ -0,0 +1,696 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q15.c + * Description: Convolution of Q15 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_conv_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_conv_opt_q15() for a faster implementation of this function using scratch buffers. + */ + +void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLALDX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLALDX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLALDX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLALDX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLALDX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLALDX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py + 1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD(x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + blockSize3 = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = blockSize3 >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of values */ + for (i = 0; i < (srcALen + srcBLen - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c new file mode 100644 index 0000000..39550ec --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c @@ -0,0 +1,581 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q31.c + * Description: Convolution of Q31 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_conv_fast_q31() for a faster but less precise implementation of this function. + */ + +void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q63_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py--); + + /* x[1] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py--); + + /* x[2] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py--); + + /* x[3] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll by 3 */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *(py); + /* Read x[3] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += ((q63_t) x2 * c0); + + /* Read y[srcBLen - 2] sample */ + c0 = *(py - 1U); + /* Read x[4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += ((q63_t) x1 * c0); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += ((q63_t) x2 * c0); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += ((q63_t) x0 * c0); + + /* Read y[srcBLen - 3] sample */ + c0 = *(py - 2U); + /* Read x[5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += ((q63_t) x2 * c0); + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += ((q63_t) x0 * c0); + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += ((q63_t) x1 * c0); + + /* update scratch pointers */ + px += 3U; + py -= 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 >> 31); + *pOut++ = (q31_t) (acc1 >> 31); + *pOut++ = (q31_t) (acc2 >> 31); + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t) (sum >> 31U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c new file mode 100644 index 0000000..bdd1cab --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c @@ -0,0 +1,700 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q7.c + * Description: Convolution of Q7 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + @remark + Refer to \ref arm_conv_opt_q7() for a faster implementation of this function. + */ + +void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 1] , y[srcBLen - 2] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* x[0] * y[srcBLen - 1] */ + /* x[1] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 3] , y[srcBLen - 4] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* x[2] * y[srcBLen - 3] */ + /* x[3] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read y[srcBLen - 2] sample */ + c1 = *py--; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 1] and y[srcBLen - 2] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read y[srcBLen - 4] sample */ + c1 = *py--; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 3] and y[srcBLen - 4] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q15_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q15_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q15_t) x2 * c0); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc1 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc2 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + + while (k > 0U) + { + /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB; /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c new file mode 100644 index 0000000..1096526 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c @@ -0,0 +1,893 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_f32.c + * Description: Correlation of floating-point sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup Corr Correlation + + Correlation is a mathematical operation that is similar to convolution. + As with convolution, correlation uses two signals to produce a third signal. + The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. + Correlation is commonly used to measure the similarity between two signals. + It has applications in pattern recognition, cryptanalysis, and searching. + The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. + Fast versions of the Q15 and Q31 functions are also provided. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. + The convolution of the two signals is denoted by + 
+      c[n] = a[n] * b[n]
+
+ In correlation, one of the signals is flipped in time + 
+       c[n] = a[n] * b[-n]
+
+ @par + and this is mathematically defined as + \image html CorrelateEquation.gif + @par + The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. + The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). + The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result. + + @note + The pDst should be initialized to all zeros before being used. + + @par Fixed-Point Behavior + Correlation requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of correlate + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const float32_t *pIn1; /* InputA pointer */ + const float32_t *pIn2; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1; + float32_t sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) || defined (ARM_MATH_NEON) + float32_t acc0, acc1, acc2, acc3; /* Accumulators */ + float32_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + k = count & 0x3; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += *px++ * *py++; + + /* x[1] * y[srcBLen - 3] */ + sum += *px++ * *py++; + + /* x[2] * y[srcBLen - 2] */ + sum += *px++ * *py++; + + /* x[3] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#endif /* #if defined(ARM_MATH_NEON) */ +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t c; + float32x4_t x1v; + float32x4_t x2v; + uint32x4_t x1v_u; + uint32x4_t x2v_u; + float32x4_t x; + uint32x4_t x_u; + float32x4_t res = vdupq_n_f32(0) ; +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + +#if defined(ARM_MATH_NEON) + /* Compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + res = vdupq_n_f32(0) ; + + x1v = vld1q_f32(px); + px += 4; + do + { + x2v = vld1q_f32(px); + c = vld1q_f32(py); + + py += 4; + + x = x1v; + res = vmlaq_n_f32(res,x,c[0]); + + x = vextq_f32(x1v,x2v,1); + + res = vmlaq_n_f32(res,x,c[1]); + + x = vextq_f32(x1v,x2v,2); + + res = vmlaq_n_f32(res,x,c[2]); + + x = vextq_f32(x1v,x2v,3); + + res = vmlaq_n_f32(res,x,c[3]); + + x1v = x2v; + px+=4; + x2v = vld1q_f32(px); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *(py++); + + res = vmlaq_n_f32(res,x1v,c0); + + /* Reuse the present samples for the next MAC */ + x1v[0] = x1v[1]; + x1v[1] = x1v[2]; + x1v[2] = x1v[3]; + + x1v[3] = *(px++); + + /* Decrement the loop counter */ + k--; + } + + px-=1; + + acc0 = res[0]; + acc1 = res[1]; + acc2 = res[2]; + acc3 = res[3]; +#else + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py++); + /* Read x[3] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[0] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[0] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[0] */ + acc3 += x3 * c0; + + /* Read y[1] sample */ + c0 = *(py++); + /* Read x[4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[1] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[1] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[1] */ + acc3 += x0 * c0; + + /* Read y[2] sample */ + c0 = *(py++); + /* Read x[5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[2] */ + acc3 += x1 * c0; + + /* Read y[3] sample */ + c0 = *(py++); + /* Read x[6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[3] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[3] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[3] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[3] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + /* Read x[7] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[4] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[4] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[4] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[4] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + +#endif /* #if defined(ARM_MATH_NEON) */ + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = acc0; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = acc1; + pOut += inc; + + *pOut = acc2; + pOut += inc; + + *pOut = acc3; + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } +#endif /* #if defined(ARM_MATH_NEON) */ + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + +#endif /* #if defined (ARM_MATH_NEON) */ + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we assume zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += pIn1[j] * pIn2[-((int32_t) i - j)]; + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c new file mode 100644 index 0000000..13661cb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c @@ -0,0 +1,345 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_opt_q15.c + * Description: Fast Q15 Correlation + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q31_t acc0; /* Accumulators */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch; /* Temporary pointer for scratch */ + const q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, blkCnt, outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables for holding input and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + pScr1 = pScratch; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pIn2; + + + /* Actual correlation process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumlate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumlate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumlate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ + *pOut = (__SSAT(acc0 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc1 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc2 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc3 >> 15U, 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut = (q15_t) (__SSAT((acc0 >> 15), 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 1U; + } + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c new file mode 100644 index 0000000..6898618 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c @@ -0,0 +1,614 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_q15.c + * Description: Fast Q15 Correlation + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first loop starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* x[0] * y[srcBLen - 1] */ + sum = __SMLAD(*px++, *py++, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* -------------------- + * Stage2 process + * -------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the first two inputB samples using SIMD: + * y[0] and y[1] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLAD(x0, c0, acc0); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLAD(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLAD(x2, c0, acc2); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLAD(x3, c0, acc3); + + /* Read y[2] and y[3] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLAD(x2, c0, acc0); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLAD(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLAD(x0, c0, acc2); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLAD(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[4] */ + c0 = *py; + +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD (x0, c0, acc0); + acc1 = __SMLAD (x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLAD(x3, c0, acc2); + acc3 = __SMLAD(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLAD(x3, c0, acc2); + acc3 = __SMLAD(x2, c0, acc3); + + c0 = (*py); + /* Read y[6] */ +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD (x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (acc0 >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q15_t) (acc1 >> 15); + pOut += inc; + + *pOut = (q15_t) (acc2 >> 15); + pOut += inc; + + *pOut = (q15_t) (acc3 >> 15); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) * px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c new file mode 100644 index 0000000..a5840b7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c @@ -0,0 +1,601 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_q31.c + * Description: Fast Q31 Correlation + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are accumulated in a 32-bit register in 2.30 format. + Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + + @remark + Refer to \ref arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. + */ + +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1; /* Intermediate pointers */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[1] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[3] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *py++; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[0] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[0] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[0] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + + /* Read y[1] sample */ + c0 = *py++; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + + /* Read y[2] sample */ + c0 = *py++; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + + /* Read y[3] sample */ + c0 = *py++; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[3] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[3] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[3] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *py++; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (acc0 << 1); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q31_t) (acc1 << 1); + pOut += inc; + + *pOut = (q31_t) (acc2 << 1); + pOut += inc; + + *pOut = (q31_t) (acc3 << 1); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1U; + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c new file mode 100644 index 0000000..d46d9a0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_opt_q15.c + * Description: Correlation of Q15 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_correlate_fast_q15() for a faster but less precise version of this function. + */ + +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + q63_t acc0; /* Accumulators */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1; /* Temporary pointer for scratch1 */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, blkCnt, outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Output pointer increment */ + uint32_t tapCnt; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables for holding input1 and input2 values */ + q31_t y1, y2; /* State variables */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + pScr1 = pScratch; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pIn2; + + + /* Actual correlation process starts here */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumlate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumlate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumlate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + + /* Store the results in the accumulators in the destination buffer. */ + *pOut = (__SSAT(acc0 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc1 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc2 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc3 >> 15U, 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 4U; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut = (q15_t) (__SSAT((acc0 >> 15), 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 1U; + } + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c new file mode 100644 index 0000000..035bfba --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c @@ -0,0 +1,388 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_opt_q7.c + * Description: Correlation of Q7 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + */ + +void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */ + q15_t x4; /* Temporary input variable */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + int32_t inc = 1; /* Output pointer increment */ + uint32_t outBlockSize; /* Loop counter */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + q7_t *pOut = pDst; /* Output pointer */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + + /* Copy (srcBLen) samples in scratch buffer */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) * pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pScr2 pointer */ + pScr2 = pScratch2; + + /* Actual correlation process starts here */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumlate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumlate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc1 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc2 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc3 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + acc0 += (*pScr1++ * *pScr2++); + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumlate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c new file mode 100644 index 0000000..9837875 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c @@ -0,0 +1,696 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q15.c + * Description: Correlation of Q15 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_correlate_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers. + */ + +void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first loop starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum = __SMLALD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT((sum >> 15), 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the first two inputB samples using SIMD: + * y[0] and y[1] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLALD(x0, c0, acc0); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLALD(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLALD(x2, c0, acc2); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLALD(x3, c0, acc3); + + /* Read y[2] and y[3] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLALD(x2, c0, acc0); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLALD(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLALD(x0, c0, acc2); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLALD(x1, c0, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[4] */ + c0 = *py; +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD (x0, c0, acc0); + acc1 = __SMLALD (x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALD(x3, c0, acc2); + acc3 = __SMLALD(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALD(x3, c0, acc2); + acc3 = __SMLALD(x2, c0, acc3); + + c0 = (*py); + + /* Read y[6] */ +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD (x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(acc0 >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc1 >> 15, 16)); + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc2 >> 15, 16)); + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc3 >> 15, 16)); + pOut += inc; + + /* Increment the count by 4 as 4 output values are computed */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q63_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment count by 1, as one output value is computed */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q63_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = __SMLALD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT((sum >> 15), 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of values */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t) __SSAT((sum >> 15U), 16U); + else + *pDst++ = (q15_t) __SSAT((sum >> 15U), 16U); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c new file mode 100644 index 0000000..caa2f51 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c @@ -0,0 +1,682 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q31.c + * Description: Correlation of Q31 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_correlate_fast_q31() for a faster but less precise implementation of this function. + */ + +void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1; /* Intermediate pointers */ + q63_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py++); + + /* x[1] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py++); + + /* x[2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py++); + + /* x[3] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py++); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll by 3 */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py); + /* Read x[2] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[1] * y[0] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[2] * y[0] */ + acc2 += ((q63_t) x2 * c0); + + /* Read y[1] sample */ + c0 = *(py + 1U); + /* Read x[3] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += ((q63_t) x1 * c0); + /* acc1 += x[2] * y[1] */ + acc1 += ((q63_t) x2 * c0); + /* acc2 += x[3] * y[1] */ + acc2 += ((q63_t) x0 * c0); + + /* Read y[2] sample */ + c0 = *(py + 2U); + /* Read x[4] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += ((q63_t) x2 * c0); + /* acc1 += x[3] * y[2] */ + acc1 += ((q63_t) x0 * c0); + /* acc2 += x[4] * y[2] */ + acc2 += ((q63_t) x1 * c0); + + /* update scratch pointers */ + px += 3U; + py += 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + + /* Read x[7] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[5] * y[4] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[6] * y[4] */ + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (acc0 >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q31_t) (acc1 >> 31); + pOut += inc; + + *pOut = (q31_t) (acc2 >> 31); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using correlation but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate correlation for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to correlation equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q31_t) (sum >> 31U); + else + *pDst++ = (q31_t) (sum >> 31U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c new file mode 100644 index 0000000..e5881ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c @@ -0,0 +1,800 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q7.c + * Description: Correlation of Q7 sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format. + + @remark + Refer to \ref arm_correlate_opt_q7() for a faster implementation of this function. + */ + +void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 4] , y[srcBLen - 3] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[0] * y[srcBLen - 4] */ + /* x[1] * y[srcBLen - 3] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 2] , y[srcBLen - 1] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[2] * y[srcBLen - 2] */ + /* x[3] * y[srcBLen - 1] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (q31_t) ((q15_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *py++; + /* Read y[1] sample */ + c1 = *py++; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[0] and y[1] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[2] sample */ + c0 = *py++; + /* Read y[3] sample */ + c1 = *py++; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[2] and y[3] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *py++; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 += ((q15_t) x0 * c0); + /* acc1 += x[5] * y[4] */ + acc1 += ((q15_t) x1 * c0); + /* acc2 += x[6] * y[4] */ + acc2 += ((q15_t) x2 * c0); + /* acc3 += x[7] * y[4] */ + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc1 >> 7, 8)); + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc2 >> 7, 8)); + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc3 >> 7, 8)); + pOut += inc; + + count += 4U; + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[0] , y[1] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum = __SMLAD(input1, input2, sum); + + /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[2] , y[3] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q7_t) __SSAT((sum >> 7U), 8U); + else + *pDst++ = (q7_t) __SSAT((sum >> 7U), 8U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c new file mode 100644 index 0000000..218ca34 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c @@ -0,0 +1,703 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_f32.c + * Description: FIR decimation for floating-point sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator + + These functions combine an FIR filter together with a decimator. + They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion. + Conceptually, the functions are equivalent to the block diagram below: + \image html FIRDecimator.gif "Components included in the FIR Decimator functions" + When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized + cutoff frequency of 1/M in order to prevent aliasing distortion. + The user of the function is responsible for providing the filter coefficients. + + The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner. + Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the + samples output by the decimator are computed. + The functions operate on blocks of input and output data. + pSrc points to an array of blockSize input values and + pDst points to an array of blockSize/M output values. + In order to have an integer number of output samples blockSize + must always be a multiple of the decimation factor M. + + The library provides separate functions for Q15, Q31 and floating-point data types. + + @par Algorithm: + The FIR portion of the algorithm uses the standard form filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ where, b[n] are the filter coefficients. + @par + The pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+      {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable array should be allocated separately. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + - Checks to make sure that the size of the input is a multiple of the decimation factor. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
+      arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
+      arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
+
+ where M is the decimation factor; numTaps is the number of filter coefficients in the filter; + pCoeffs is the address of the coefficient buffer; + pState is the address of the state buffer. + Be sure to set the values in the state buffer to zeros when doing static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR decimate filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_NEON) +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulator */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + uint32_t blkCntN4; + float32_t *px0, *px1, *px2, *px3; + float32_t acc0, acc1, acc2, acc3; + float32_t x1, x2, x3; + + float32x4_t accv,acc0v,acc1v,acc2v,acc3v; + float32x4_t x0v, x1v, x2v, x3v; + float32x4_t c0v; + float32x2_t temp; + float32x4_t sum0v; + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = 4 * S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0v = vdupq_n_f32(0.0); + acc1v = vdupq_n_f32(0.0); + acc2v = vdupq_n_f32(0.0); + acc3v = vdupq_n_f32(0.0); + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Loop over the number of taps. + ** Repeat until we've computed numTaps-4 coefficients. */ + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0v = vld1q_f32(pb); + pb += 4; + + /* Read x[n-numTaps-1] sample for acc0 */ + x0v = vld1q_f32(px0); + x1v = vld1q_f32(px1); + x2v = vld1q_f32(px2); + x3v = vld1q_f32(px3); + + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vmlaq_f32(acc0v, x0v, c0v); + acc1v = vmlaq_f32(acc1v, x1v, c0v); + acc2v = vmlaq_f32(acc2v, x2v, c0v); + acc3v = vmlaq_f32(acc3v, x3v, c0v); + + /* Decrement the loop counter */ + tapCnt--; + } + + temp = vpadd_f32(vget_low_f32(acc0v),vget_high_f32(acc0v)); + accv[0] = temp[0] + temp[1]; + + temp = vpadd_f32(vget_low_f32(acc1v),vget_high_f32(acc1v)); + accv[1] = temp[0] + temp[1]; + + temp = vpadd_f32(vget_low_f32(acc2v),vget_high_f32(acc2v)); + accv[2] = temp[0] + temp[1]; + + temp = vpadd_f32(vget_low_f32(acc3v),vget_high_f32(acc3v)); + accv[3] = temp[0] + temp[1]; + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + accv[0] += x0 * c0; + accv[1] += x1 * c0; + accv[2] += x2 * c0; + accv[3] += x3 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + 4 * S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + vst1q_f32(pDst,accv); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0v = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Loop over the number of taps. + ** Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + c0v = vld1q_f32(pb); + pb += 4; + + x0v = vld1q_f32(px); + px += 4; + + sum0v = vmlaq_f32(sum0v, x0v, c0v); + + /* Decrement the loop counter */ + tapCnt--; + } + + temp = vpadd_f32(vget_low_f32(sum0v),vget_high_f32(sum0v)); + sum0 = temp[0] + temp[1]; + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement the loop counter */ + blkCntN4--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = (numTaps - 1U) >> 2; + + /* Copy data */ + while (i > 0U) + { + sum0v = vld1q_f32(pState); + vst1q_f32(pStateCurnt,sum0v); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} +#else +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *px0; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + float32_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t *px1, *px2, *px3; + float32_t x1, x2, x3; + float32_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = acc0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c new file mode 100644 index 0000000..948b15c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c @@ -0,0 +1,595 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_fast_q15.c + * Description: Fast Q15 FIR Decimator + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q15 FIR decimator (fast variant). + @param[in] S points to an instance of the Q15 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2). + The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result. + @remark + Refer to \ref arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_decimate_init_q15() to initialize the filter structure. + */ + +#if defined (ARM_MATH_DSP) + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulators */ + q31_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficient */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch state variables for acc0, acc1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x0 = read_q15x2_ia (&px); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficients */ + c1 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c0, sum0); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px); + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c1, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c0, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + +} + +#else /* #if defined (ARM_MATH_DSP) */ + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulators */ + q31_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the Read b[numTaps-1] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-1] for sample 0 and for sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-3] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-3] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } +} + +#endif /* #if defined (ARM_MATH_DSP) */ + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c new file mode 100644 index 0000000..2c3a28a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c @@ -0,0 +1,390 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_fast_q31.c + * Description: Fast Q31 FIR Decimator + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q31 FIR decimator (fast variant). + @param[in] S points to an instance of the Q31 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). + + @remark + Refer to \ref arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. + Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_decimate_init_q31() to initialize the filter structure. + */ + +void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *px0; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t *px1, *px2, *px3; + q31_t x1, x2, x3; + q63_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + *pDst++ = (q31_t) (acc1 << 1); + *pDst++ = (q31_t) (acc2 << 1); + *pDst++ = (q31_t) (acc3 << 1); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c new file mode 100644 index 0000000..9382f09 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_f32.c + * Description: Floating-point FIR Decimator initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c new file mode 100644 index 0000000..f583a03 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_q15.c + * Description: Initialization function for the Q15 FIR Decimator + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the Q15 FIR decimator. + @param[in,out] S points to an instance of the Q15 FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples + to the call arm_fir_decimate_q15(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c new file mode 100644 index 0000000..5ee69c6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_q31.c + * Description: Initialization function for Q31 FIR Decimation filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the Q31 FIR decimator. + @param[in,out] S points to an instance of the Q31 FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c new file mode 100644 index 0000000..f9d92c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c @@ -0,0 +1,595 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_q15.c + * Description: Q15 FIR Decimator + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q15 FIR decimator. + @param[in] S points to an instance of the Q15 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + + @remark + Refer to \ref arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function. + */ + +#if defined (ARM_MATH_DSP) + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulators */ + q63_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficient */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch state variables for acc0, acc1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x0 = read_q15x2_ia (&px); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficients */ + c1 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c0, sum0); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px); + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c1, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c0, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + +} + +#else /* #if defined (ARM_MATH_DSP) */ + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulators */ + q63_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the Read b[numTaps-1] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-1] for sample 0 and for sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-3] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-3] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } +} + +#endif /* #if defined (ARM_MATH_DSP) */ + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c new file mode 100644 index 0000000..7af8a44 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c @@ -0,0 +1,387 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_q31.c + * Description: Q31 FIR Decimator + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q31 FIR decimator. + @param[in] S points to an instance of the Q31 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + + @remark + Refer to \ref arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function. + */ + +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *px0; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t *px1, *px2, *px3; + q31_t x1, x2, x3; + q63_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31); + *pDst++ = (q31_t) (acc1 >> 31); + *pDst++ = (q31_t) (acc2 >> 31); + *pDst++ = (q31_t) (acc3 >> 31); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c new file mode 100644 index 0000000..0531cfe --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c @@ -0,0 +1,715 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_f32.c + * Description: Floating-point FIR filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR Finite Impulse Response (FIR) Filters + + This set of functions implements Finite Impulse Response (FIR) filters + for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided. + The functions operate on blocks of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst points to input and output arrays containing blockSize values. + + @par Algorithm + The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations. + Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n]. + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ @par + \image html FIR.GIF "Finite Impulse Response filter" + @par + pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the following order. + @par + 
+      {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1. + The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 4 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 4 different data type filter instance structures + 
+      arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};
+
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_NEON) + +void arm_fir_f32( +const arm_fir_instance_f32 * S, +const float32_t * pSrc, +float32_t * pDst, +uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointers for state buffer */ + const float32_t *pb; /* Temporary pointers for coefficient buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + + float32x4_t accv0,accv1,samples0,samples1,x0,x1,x2,xa,xb,x,b,accv; + uint32x4_t x0_u,x1_u,x2_u,xa_u,xb_u; + float32_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Loop unrolling */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + /* Copy 8 samples at a time into state buffers */ + samples0 = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,samples0); + + pStateCurnt += 4; + pSrc += 4 ; + + samples1 = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,samples1); + + pStateCurnt += 4; + pSrc += 4 ; + + /* Set the accumulators to zero */ + accv0 = vdupq_n_f32(0); + accv1 = vdupq_n_f32(0); + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Loop unroling */ + i = numTaps >> 2; + + /* Perform the multiply-accumulates */ + x0 = vld1q_f32(px); + x1 = vld1q_f32(px + 4); + + while(i > 0) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + x2 = vld1q_f32(px + 8); + b = vld1q_f32(pb); + xa = x0; + xb = x1; + accv0 = vmlaq_n_f32(accv0,xa,b[0]); + accv1 = vmlaq_n_f32(accv1,xb,b[0]); + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,b[1]); + accv1 = vmlaq_n_f32(accv1,xb,b[1]); + + xa = vextq_f32(x0,x1,2); + xb = vextq_f32(x1,x2,2); + + accv0 = vmlaq_n_f32(accv0,xa,b[2]); + accv1 = vmlaq_n_f32(accv1,xb,b[2]); + + xa = vextq_f32(x0,x1,3); + xb = vextq_f32(x1,x2,3); + + accv0 = vmlaq_n_f32(accv0,xa,b[3]); + accv1 = vmlaq_n_f32(accv1,xb,b[3]); + + pb += 4; + x0 = x1; + x1 = x2; + px += 4; + i--; + + } + + /* Tail */ + i = numTaps & 3; + x2 = vld1q_f32(px + 8); + + /* Perform the multiply-accumulates */ + switch(i) + { + case 3: + { + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + pb++; + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + pb++; + + xa = vextq_f32(x0,x1,2); + xb = vextq_f32(x1,x2,2); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + } + break; + case 2: + { + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + pb++; + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + } + break; + case 1: + { + + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + } + break; + default: + break; + } + + /* The result is stored in the destination buffer. */ + vst1q_f32(pDst,accv0); + pDst += 4; + vst1q_f32(pDst,accv1); + pDst += 4; + + /* Advance state pointer by 8 for the next 8 samples */ + pState = pState + 8; + + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc += *px++ * *pb++; + i--; + + } while (i > 0U); + + /* The result is stored in the destination buffer. */ + *pDst++ = acc; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy numTaps number of values */ + tapCnt = numTaps - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else +void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */ + float32_t x0, x1, x2, x3, x4, x5, x6, x7; /* Temporary variables to hold state values */ + float32_t c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 output values simultaneously. + * The variables acc0 ... acc7 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + acc4 = 0.0f; + acc5 = 0.0f; + acc6 = 0.0f; + acc7 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* This is separated from the others to avoid + * a call to __aeabi_memmove which would be slower + */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Read the first 7 samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + x3 = *px++; + x4 = *px++; + x5 = *px++; + x6 = *px++; + + /* Loop unrolling: process 8 taps at a time. */ + tapCnt = numTaps >> 3U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample */ + x7 = *(px++); + + /* acc0 += b[numTaps-1] * x[n-numTaps] */ + acc0 += x0 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-1] */ + acc1 += x1 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-2] */ + acc2 += x2 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-3] */ + acc3 += x3 * c0; + + /* acc4 += b[numTaps-1] * x[n-numTaps-4] */ + acc4 += x4 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-5] */ + acc5 += x5 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-6] */ + acc6 += x6 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-7] */ + acc7 += x7 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c0; + acc1 += x2 * c0; + acc2 += x3 * c0; + acc3 += x4 * c0; + acc4 += x5 * c0; + acc5 += x6 * c0; + acc6 += x7 * c0; + acc7 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x2 * c0; + acc1 += x3 * c0; + acc2 += x4 * c0; + acc3 += x5 * c0; + acc4 += x6 * c0; + acc5 += x7 * c0; + acc6 += x0 * c0; + acc7 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x3 * c0; + acc1 += x4 * c0; + acc2 += x5 * c0; + acc3 += x6 * c0; + acc4 += x7 * c0; + acc5 += x0 * c0; + acc6 += x1 * c0; + acc7 += x2 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x3 = *(px++); + /* Perform the multiply-accumulates */ + acc0 += x4 * c0; + acc1 += x5 * c0; + acc2 += x6 * c0; + acc3 += x7 * c0; + acc4 += x0 * c0; + acc5 += x1 * c0; + acc6 += x2 * c0; + acc7 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x4 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x5 * c0; + acc1 += x6 * c0; + acc2 += x7 * c0; + acc3 += x0 * c0; + acc4 += x1 * c0; + acc5 += x2 * c0; + acc6 += x3 * c0; + acc7 += x4 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x5 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x6 * c0; + acc1 += x7 * c0; + acc2 += x0 * c0; + acc3 += x1 * c0; + acc4 += x2 * c0; + acc5 += x3 * c0; + acc6 += x4 * c0; + acc7 += x5 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x6 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x7 * c0; + acc1 += x0 * c0; + acc2 += x1 * c0; + acc3 += x2 * c0; + acc4 += x3 * c0; + acc5 += x4 * c0; + acc6 += x5 * c0; + acc7 += x6 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x8U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x7 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + acc4 += x4 * c0; + acc5 += x5 * c0; + acc6 += x6 * c0; + acc7 += x7 * c0; + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + x3 = x4; + x4 = x5; + x5 = x6; + x6 = x7; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 8 to process the next group of 8 samples */ + pState = pState + 8; + + /* The results in the 8 accumulators, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + *pDst++ = acc4; + *pDst++ = acc5; + *pDst++ = acc6; + *pDst++ = acc7; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x8U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += *px++ * *pb++; + + i--; + } while (i > 0U); + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +/** +* @} end of FIR group +*/ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c new file mode 100644 index 0000000..5f8df95 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c @@ -0,0 +1,332 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_fast_q15.c + * Description: Q15 Fast FIR filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q15 FIR filter (fast version). + @param[in] S points to an instance of the Q15 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result. + + @remark + Refer to \ref arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_init_q15() to initialize the filter structure. + */ + +void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */ + px = pState; + + /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */ + pb = pCoeffs; + + /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */ + x0 = read_q15x2_ia (&px); + + /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */ + x2 = read_q15x2_ia (&px); + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-(numTaps%4) coefficients. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc0 = __SMLAD(x0, c0, acc0); + + /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */ + acc2 = __SMLAD(x2, c0, acc2); + + /* pack x[n-N-1] and x[n-N-2] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read state x[n-N-4], x[n-N-5] */ + x0 = read_q15x2_ia (&px); + + /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack x[n-N-3] and x[n-N-4] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */ + acc3 = __SMLADX(x1, c0, acc3); + + /* Read coefficients b[N-2], b[N-3] */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */ + acc0 = __SMLAD(x2, c0, acc0); + + /* Read state x[n-N-6], x[n-N-7] with offset */ + x2 = read_q15x2_ia (&px); + + /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */ + acc2 = __SMLAD(x0, c0, acc2); + + /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack x[n-N-5] and x[n-N-6] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */ + acc3 = __SMLADX(x1, c0, acc3); + + /* Decrement tap count */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps. + This is always be 2 taps since the filter length is even. */ + if ((numTaps & 0x3U) != 0U) + { + /* Read last two coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc2 = __SMLAD(x2, c0, acc2); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read last state variables */ + x0 = read_q15x2 (px); + + /* Perform the multiply-accumulates */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* Perform the multiply-accumulates */ + acc3 = __SMLADX(x1, c0, acc3); + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation. + Then store the 4 outputs in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy two samples into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Use SIMD to hold states and coefficients */ + px = pState; + pb = pCoeffs; + + tapCnt = numTaps >> 1U; + + do + { + acc0 += (q31_t) *px++ * *pb++; + acc0 += (q31_t) *px++ * *pb++; + + tapCnt--; + } + while (tapCnt > 0U); + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c new file mode 100644 index 0000000..513cb72 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c @@ -0,0 +1,324 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_fast_q31.c + * Description: Processing function for the Q31 Fast FIR filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q31 FIR filter (fast version). + @param[in] S points to an instance of the Q31 structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + + @remark + Refer to \ref arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_init_q31() to initialize the filter structure. + */ + +IAR_ONLY_LOW_OPTIMIZATION_ENTER +void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 3 samples from the state buffer: + * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Loop unrolling. Process 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-3] sample */ + x3 = *px; + + /* acc0 += b[numTaps] * x[n-numTaps] */ + multAcc_32x32_keep32_R(acc0, x0, c0); + + /* acc1 += b[numTaps] * x[n-numTaps-1] */ + multAcc_32x32_keep32_R(acc1, x1, c0); + + /* acc2 += b[numTaps] * x[n-numTaps-2] */ + multAcc_32x32_keep32_R(acc2, x2, c0); + + /* acc3 += b[numTaps] * x[n-numTaps-3] */ + multAcc_32x32_keep32_R(acc3, x3, c0); + + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb + 1U); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x1, c0); + multAcc_32x32_keep32_R(acc1, x2, c0); + multAcc_32x32_keep32_R(acc2, x3, c0); + multAcc_32x32_keep32_R(acc3, x0, c0); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb + 2U); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x2, c0); + multAcc_32x32_keep32_R(acc1, x3, c0); + multAcc_32x32_keep32_R(acc2, x0, c0); + multAcc_32x32_keep32_R(acc3, x1, c0); + + /* Read the b[numTaps-3] coefficients */ + c0 = *(pb + 3U); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px + 3U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x3, c0); + multAcc_32x32_keep32_R(acc1, x0, c0); + multAcc_32x32_keep32_R(acc2, x1, c0); + multAcc_32x32_keep32_R(acc3, x2, c0); + + /* update coefficient pointer */ + pb += 4U; + px += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x3 = *(px++); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x0, c0); + multAcc_32x32_keep32_R(acc1, x1, c0); + multAcc_32x32_keep32_R(acc2, x2, c0); + multAcc_32x32_keep32_R(acc3, x3, c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.31 + Then store the 4 outputs in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + *pDst++ = (q31_t) (acc1 << 1); + *pDst++ = (q31_t) (acc2 << 1); + *pDst++ = (q31_t) (acc3 << 1); + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + multAcc_32x32_keep32_R(acc0, (*px++), (*pb++)); + i--; + } while (i > 0U); + + /* The result is in 2.30 format. Convert to 1.31 + Then store the output in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +IAR_ONLY_LOW_OPTIMIZATION_EXIT +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c new file mode 100644 index 0000000..02e82ad --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c @@ -0,0 +1,81 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_f32.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32(). + */ + +void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c new file mode 100644 index 0000000..a5b2d06 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q15.c + * Description: Q15 FIR filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q15 FIR filter. + @param[in,out] S points to an instance of the Q15 FIR filter structure. + @param[in] numTaps number of filter coefficients in the filter. Must be even and greater than or equal to 4. + @param[in] pCoeffs points to the filter coefficients buffer. + @param[in] pState points to the state buffer. + @param[in] blockSize number of samples processed per call. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : numTaps is not greater than or equal to 4 and even + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ Note that numTaps must be even and greater than or equal to 4. + To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero. + For example, to implement a filter with numTaps=3 and coefficients + 
+      {0.3, -0.8, 0.3}
+
+ set numTaps=4 and use the coefficients: + 
+      {0.3, -0.8, 0.3, 0}.
+
+ Similarly, to implement a two point filter + 
+      {0.3, -0.3}
+
+ set numTaps=4 and use the coefficients: + 
+      {0.3, -0.3, 0, 0}.
+
+ pState points to the array of state variables. + pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3 and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15(). + */ + +arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + +#if defined (ARM_MATH_DSP) + + /* The Number of filter coefficients in the filter must be even and at least 4 */ + if (numTaps & 0x1U) + { + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps ) */ + memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +#else + + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + + return (status); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c new file mode 100644 index 0000000..7d8376f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q31.c + * Description: Q31 FIR filter initialization function. + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q31 FIR filter. + @param[in,out] S points to an instance of the Q31 FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31(). + */ + +void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c new file mode 100644 index 0000000..f96d250 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c @@ -0,0 +1,81 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q7.c + * Description: Q7 FIR filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q7 FIR filter. + @param[in,out] S points to an instance of the Q7 FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7(). + */ + +void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q7_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c new file mode 100644 index 0000000..ee0ed27 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c @@ -0,0 +1,914 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_f32.c + * Description: Floating-point FIR interpolation sequences + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator + + These functions combine an upsampler (zero stuffer) and an FIR filter. + They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images. + Conceptually, the functions are equivalent to the block diagram below: + \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions" + After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized + cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum. + The user of the function is responsible for providing the filter coefficients. + + The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner. + The upsampler inserts L-1 zeros between each sample. + Instead of multiplying by these zero values, the FIR filter is designed to skip them. + This leads to an efficient implementation without any wasted effort. + The functions operate on blocks of input and output data. + pSrc points to an array of blockSize input values and + pDst points to an array of blockSize*L output values. + + The library provides separate functions for Q15, Q31, and floating-point data types. + + @par Algorithm + The functions use a polyphase filter structure: + 
+      y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
+      y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
+      ...
+      y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
+
+ This approach is more efficient than straightforward upsample-then-filter algorithms. + With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter. + @par + pCoeffs points to a coefficient array of size numTaps. + numTaps must be a multiple of the interpolation factor L and this is checked by the + initialization functions. + Internally, the function divides the FIR filter's impulse response into shorter filters of length + phaseLength=numTaps/L. + Coefficients are stored in time reversed order. + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size blockSize + phaseLength - 1. + Samples in the state buffer are stored in the order: + 
+     {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable array should be allocated separately. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + - Checks to make sure that the length of the filter is a multiple of the interpolation factor. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
+      arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
+      arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
+
+ @par + where L is the interpolation factor; phaseLength=numTaps/L is the + length of each of the shorter FIR filters used internally, + pCoeffs is the address of the coefficient buffer; + pState is the address of the state buffer. + Be sure to set the values in the state buffer to zeros when doing static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR interpolate filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for floating-point FIR interpolator. + @param[in] S points to an instance of the floating-point FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_NEON) +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointers for state buffer */ + const float32_t *ptr2; /* Temporary pointers for coefficient buffer */ + float32_t sum0; /* Accumulators */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t i, blkCnt, j; /* Loop counters */ + uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */ + float32_t acc0, acc1, acc2, acc3; + float32_t x1, x2, x3; + uint32_t blkCntN4; + float32_t c1, c2, c3; + + float32x4_t sum0v; + float32x4_t accV,accV0,accV1; + float32x4_t x0v,x1v,x2v,xa,xb; + uint32x4_t x0v_u,x1v_u,x2v_u,xa_u,xb_u; + float32x2_t tempV; + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + (phaseLen - 1U); + + /* Initialise blkCnt */ + blkCnt = blockSize >> 3; + blkCntN4 = blockSize & 7; + + /* Loop unrolling */ + while (blkCnt > 0U) + { + /* Copy new input samples into the state buffer */ + sum0v = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,sum0v); + pSrc += 4; + pStateCurnt += 4; + + sum0v = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,sum0v); + pSrc += 4; + pStateCurnt += 4; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + accV0 = vdupq_n_f32(0.0); + accV1 = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + ** Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0v = vld1q_f32(ptr1); + x1v = vld1q_f32(ptr1 + 4); + + while (tapCnt > 0U) + { + /* Read the input samples */ + x2v = vld1q_f32(ptr1 + 8); + + /* Read the coefficients */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c1 = *(ptr2 + S->L); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c1); + accV1 = vmlaq_n_f32(accV1,xb,c1); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c2 = *(ptr2 + S->L * 2); + + xa = vextq_f32(x0v,x1v,2); + xb = vextq_f32(x1v,x2v,2); + + accV0 = vmlaq_n_f32(accV0,xa,c2); + accV1 = vmlaq_n_f32(accV1,xb,c2); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c3 = *(ptr2 + S->L * 3); + + xa = vextq_f32(x0v,x1v,3); + xb = vextq_f32(x1v,x2v,3); + + accV0 = vmlaq_n_f32(accV0,xa,c3); + accV1 = vmlaq_n_f32(accV1,xb,c3); + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + ptr1 += 4; + x0v = x1v; + x1v = x2v; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + x2v = vld1q_f32(ptr1 + 8); + + switch (tapCnt) + { + case 3: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,2); + xb = vextq_f32(x1v,x2v,2); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + break; + + case 2: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + break; + + case 1: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + break; + + default: + break; + + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst = accV0[0]; + *(pDst + S->L) = accV0[1]; + *(pDst + 2 * S->L) = accV0[2]; + *(pDst + 3 * S->L) = accV0[3]; + + *(pDst + 4 * S->L) = accV1[0]; + *(pDst + 5 * S->L) = accV1[1]; + *(pDst + 6 * S->L) = accV1[2]; + *(pDst + 7 * S->L) = accV1[3]; + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 8; + + pDst += S->L * 7; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + + while (blkCntN4 > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0v = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + ** Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Read the coefficient */ + x1v[0] = *(ptr2); + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the input sample */ + x0v = vld1q_f32(ptr1); + ptr1 += 4; + + /* Read the coefficient */ + x1v[1] = *(ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the coefficient */ + x1v[2] = *(ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the coefficient */ + x1v[3] = *(ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0v = vmlaq_f32(sum0v,x0v,x1v); + + /* Decrement the loop counter */ + tapCnt--; + } + + tempV = vpadd_f32(vget_low_f32(sum0v),vget_high_f32(sum0v)); + sum0 = tempV[0] + tempV[1]; + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *(ptr1++) * (*ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCntN4--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + tapCnt = (phaseLen - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + sum0v = vld1q_f32(pState); + vst1q_f32(pStateCurnt,sum0v); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (phaseLen - 1U) % 0x04U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else + +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3; + float32_t x0, x1, x2, x3; + float32_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c1; + acc1 += x2 * c1; + acc2 += x3 * c1; + acc3 += x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x2 * c2; + acc1 += x3 * c2; + acc2 += x0 * c2; + acc3 += x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x3 * c3; + acc1 += x0 * c3; + acc2 += x1 * c3; + acc3 += x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = acc0; + *(pDst + S->L) = acc1; + *(pDst + 2 * S->L) = acc2; + *(pDst + 3 * S->L) = acc3; + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c new file mode 100644 index 0000000..287d347 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_f32.c + * Description: Floating-point FIR interpolator initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the floating-point FIR interpolator. + @param[in,out] S points to an instance of the floating-point FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ @par + The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32(). + */ + +arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c new file mode 100644 index 0000000..7f43bbf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_q15.c + * Description: Q15 FIR interpolator initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the Q15 FIR interpolator. + @param[in,out] S points to an instance of the Q15 FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15(). + */ + +arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c new file mode 100644 index 0000000..973e715 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_q31.c + * Description: Q31 FIR interpolator initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the Q31 FIR interpolator. + @param[in,out] S points to an instance of the Q31 FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31(). + */ + +arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c new file mode 100644 index 0000000..7efec94 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c @@ -0,0 +1,479 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_q15.c + * Description: Q15 FIR interpolation + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for the Q15 FIR interpolator. + @param[in] S points to an instance of the Q15 FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2, acc3; + q15_t x0, x1, x2, x3; + q15_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x1 * c1; + acc1 += (q63_t) x2 * c1; + acc2 += (q63_t) x3 * c1; + acc3 += (q63_t) x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x2 * c2; + acc1 += (q63_t) x3 * c2; + acc2 += (q63_t) x0 * c2; + acc3 += (q63_t) x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x3 * c3; + acc1 += (q63_t) x0 * c3; + acc2 += (q63_t) x1 * c3; + acc3 += (q63_t) x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = (q15_t) (__SSAT((acc0 >> 15), 16)); + *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16)); + *(pDst + 2 * S->L) = (q15_t) (__SSAT((acc2 >> 15), 16)); + *(pDst + 3 * S->L) = (q15_t) (__SSAT((acc3 >> 15), 16)); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += ((q63_t) *ptr1++ * *ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result after converting to 1.15 format in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c new file mode 100644 index 0000000..d6a8ca3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c @@ -0,0 +1,481 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_q31.c + * Description: Q31 FIR interpolation + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for the Q31 FIR interpolator. + @param[in] S points to an instance of the Q31 FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L). + since numTaps/L additions occur per output sample. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2, acc3; + q31_t x0, x1, x2, x3; + q31_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x1 * c1; + acc1 += (q63_t) x2 * c1; + acc2 += (q63_t) x3 * c1; + acc3 += (q63_t) x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x2 * c2; + acc1 += (q63_t) x3 * c2; + acc2 += (q63_t) x0 * c2; + acc3 += (q63_t) x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x3 * c3; + acc1 += (q63_t) x0 * c3; + acc2 += (q63_t) x1 * c3; + acc3 += (q63_t) x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = (q31_t) (acc0 >> 31); + *(pDst + S->L) = (q31_t) (acc1 >> 31); + *(pDst + 2 * S->L) = (q31_t) (acc2 >> 31); + *(pDst + 3 * S->L) = (q31_t) (acc3 >> 31); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += ((q63_t) *ptr1++ * *ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c new file mode 100644 index 0000000..a3d95c1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c @@ -0,0 +1,453 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_f32.c + * Description: Processing function for floating-point FIR Lattice filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters + + This set of functions implements Finite Impulse Response (FIR) lattice filters + for Q15, Q31 and floating-point data types. Lattice filters are used in a + variety of adaptive filter applications. The filter structure is feedforward and + the net impulse response is finite length. + The functions operate on blocks + of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst point to input and output arrays containing blockSize values. + + @par Algorithm + \image html FIRLattice.gif "Finite Impulse Response Lattice filter" + The following difference equation is implemented: + @par + 
+      f0[n] = g0[n] = x[n]
+      fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
+      gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
+      y[n] = fM[n]
+
+ @par + pCoeffs points to tha array of reflection coefficients of size numStages. + Reflection Coefficients are stored in the following order. + @par + 
+      {k1, k2, ..., kM}
+
+ where M is number of stages + @par + pState points to a state array of size numStages. + The state variables (g values) hold previous inputs and are stored in the following order. + 
+    {g0[n], g1[n], g2[n] ...gM-1[n]}
+
+ The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: + 
+      arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
+      arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
+      arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
+
+ @par + where numStages is the number of stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR Lattice filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for the floating-point FIR lattice filter. + @param[in] S points to an instance of the floating-point FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Temporary state pointer */ + const float32_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + float32_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + float32_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + float32_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (fcurr0 * (*pk)) + gcurr0; + + /* Process second sample for first tap */ + fnext1 = (fcurr0 * (*pk)) + fcurr1; + gnext1 = (fcurr1 * (*pk)) + fcurr0; + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (fcurr1 * (*pk)) + fcurr2; + gnext2 = (fcurr2 * (*pk)) + fcurr1; + + /* Process fourth sample for first tap */ + fnext3 = (fcurr2 * (*pk )) + fcurr3; + gnext3 = (fcurr3 * (*pk++)) + fcurr2; + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (gnext0 * (*pk)) + fcurr1; + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (gnext1 * (*pk)) + fcurr2; + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g2(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (gcurr0 * (*pk)) + fnext0; + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (gnext0 * (*pk)) + fnext1; + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (gnext1 * (*pk)) + fnext2; + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (gnext2 * (*pk)) + fnext3; + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (fnext3 * (*pk)) + gnext2; + + gnext2 = (fnext2 * (*pk)) + gnext1; + + gnext1 = (fnext1 * (*pk)) + gnext0; + + gnext0 = (fnext0 * (*pk++)) + gcurr0; + + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g3(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (gnext0 * (*pk)) + fcurr1; + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (gnext1 * (*pk)) + fcurr2; + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (gcurr0 * (*pk)) + fnext0; + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (gnext0 * (*pk)) + fnext1; + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (gnext1 * (*pk)) + fnext2; + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (gnext2 * (*pk)) + fnext3; + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (fnext3 * (*pk)) + gnext2; + + gnext2 = (fnext2 * (*pk)) + gnext1; + + gnext1 = (fnext1 * (*pk)) + gnext0; + + gnext0 = (fnext0 * (*pk++)) + gcurr0; + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + fnext1 = (gnext0 * (*pk)) + fcurr1; + + fnext2 = (gnext1 * (*pk)) + fcurr2; + + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + *pDst++ = fcurr1; + *pDst++ = fcurr2; + *pDst++ = fcurr3; + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* save g1(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c new file mode 100644 index 0000000..7929629 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_f32.c + * Description: Floating-point FIR Lattice filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the floating-point FIR lattice filter. + @param[in] S points to an instance of the floating-point FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c new file mode 100644 index 0000000..5c80dff --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_q15.c + * Description: Q15 FIR Lattice filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q15 FIR lattice filter. + @param[in] S points to an instance of the Q15 FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c new file mode 100644 index 0000000..476296d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_q31.c + * Description: Q31 FIR lattice filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q31 FIR lattice filter. + @param[in] S points to an instance of the Q31 FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c new file mode 100644 index 0000000..42e7c0d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c @@ -0,0 +1,506 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_q15.c + * Description: Q15 FIR lattice filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for Q15 FIR lattice filter. + @param[in] S points to an instance of the Q15 FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary state pointer */ + const q15_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Process second sample for first tap */ + fnext1 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr0; + gnext1 = __SSAT(gnext1, 16); + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + fcurr1; + gnext2 = __SSAT(gnext2, 16); + + /* Process fourth sample for first tap */ + fnext3 = (q31_t) ((fcurr2 * (*pk )) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + gnext3 = (q31_t) ((fcurr3 * (*pk++)) >> 15U) + fcurr2; + gnext3 = __SSAT(gnext3, 16); + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = (q15_t) fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0; + fcurr0 = __SSAT(fcurr0, 16); + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1; + fcurr1 = __SSAT(fcurr1, 16); + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2; + fcurr2 = __SSAT(fcurr2, 16); + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3; + fcurr3 = __SSAT(fcurr3, 16); + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0; + fcurr0 = __SSAT(fcurr0, 16); + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1; + fcurr1 = __SSAT(fcurr1, 16); + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2; + fcurr2 = __SSAT(fcurr2, 16); + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3; + fcurr3 = __SSAT(fcurr3, 16); + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = (q15_t) gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(fcurr0, fcurr1, 16)); + write_q15x2_ia (&pDst, __PKHBT(fcurr2, fcurr3, 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(fcurr1, fcurr0, 16)); + write_q15x2_ia (&pDst, __PKHBT(fcurr3, fcurr2, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* save g1(n) in state buffer */ + *px++ = (q15_t) fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = __SSAT(fcurr0, 16); + + blkCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* save f0(n) in state buffer */ + *px++ = (q15_t) fcurr0; + + /* f1(n) is saved in fcurr for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g1(n-1) from state buffer */ + gcurr0 = *px; + + /* save g0(n-1) in state buffer */ + *px++ = (q15_t) gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = __SSAT(fcurr0, 16); + + blkCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c new file mode 100644 index 0000000..c8d28d7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c @@ -0,0 +1,505 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_q31.c + * Description: Q31 FIR lattice filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q31 FIR lattice filter. + @param[in] S points to an instance of the Q31 FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits. + */ + +void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Temporary state pointer */ + const q31_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Process second sample for first tap */ + fnext1 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + fcurr0; + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + fcurr1; + + /* Process fourth sample for first tap */ + fnext3 = (q31_t) (((q63_t) fcurr2 * (*pk )) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk++)) >> 32U); + gnext3 = (gnext3 << 1U) + fcurr2; + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fcurr0 = (fcurr0 << 1U) + fnext0; + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fcurr1 = (fcurr1 << 1U) + fnext1; + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fcurr2 = (fcurr2 << 1U) + fnext2; + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fcurr3 = (fcurr3 << 1U) + fnext3; + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fcurr0 = (fcurr0 << 1U) + fnext0; + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fcurr1 = (fcurr1 << 1U) + fnext1; + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fcurr2 = (fcurr2 << 1U) + fnext2; + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fcurr3 = (fcurr3 << 1U) + fnext3; + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + *pDst++ = fcurr1; + *pDst++ = fcurr2; + *pDst++ = fcurr3; + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* save g1(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* save f0(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g1(n-1) from state buffer */ + gcurr0 = *px; + + /* save g0(n-1) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c new file mode 100644 index 0000000..e20798e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c @@ -0,0 +1,332 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q15.c + * Description: Q15 FIR filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q15 FIR filter. + @param[in] S points to an instance of the Q15 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + + @remark + Refer to \ref arm_fir_fast_q15() for a faster but less precise implementation of this function. + */ + +void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q63_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */ + px = pState; + + /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */ + pb = pCoeffs; + + /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */ + x0 = read_q15x2_ia (&px); + + /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */ + x2 = read_q15x2_ia (&px); + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-(numTaps%4) coefficients. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc0 = __SMLALD(x0, c0, acc0); + + /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */ + acc2 = __SMLALD(x2, c0, acc2); + + /* pack x[n-N-1] and x[n-N-2] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read state x[n-N-4], x[n-N-5] */ + x0 = read_q15x2_ia (&px); + + /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack x[n-N-3] and x[n-N-4] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + /* Read coefficients b[N-2], b[N-3] */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */ + acc0 = __SMLALD(x2, c0, acc0); + + /* Read state x[n-N-6], x[n-N-7] with offset */ + x2 = read_q15x2_ia (&px); + + /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */ + acc2 = __SMLALD(x0, c0, acc2); + + /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack x[n-N-5] and x[n-N-6] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */ + acc3 = __SMLALDX(x1, c0, acc3); + + /* Decrement tap count */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps. + This is always be 2 taps since the filter length is even. */ + if ((numTaps & 0x3U) != 0U) + { + /* Read last two coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulates */ + acc0 = __SMLALD(x0, c0, acc0); + acc2 = __SMLALD(x2, c0, acc2); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read last state variables */ + x0 = read_q15x2 (px); + + /* Perform the multiply-accumulates */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* Perform the multiply-accumulates */ + acc3 = __SMLALDX(x1, c0, acc3); + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation. + Then store the 4 outputs in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy two samples into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Use SIMD to hold states and coefficients */ + px = pState; + pb = pCoeffs; + + tapCnt = numTaps >> 1U; + + do + { + acc0 += (q31_t) *px++ * *pb++; + acc0 += (q31_t) *px++ * *pb++; + + tapCnt--; + } + while (tapCnt > 0U); + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c new file mode 100644 index 0000000..c57371b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c @@ -0,0 +1,288 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q31.c + * Description: Q31 FIR filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for Q31 FIR filter. + @param[in] S points to an instance of the Q31 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_fir_fast_q31() for a faster but less precise implementation of this filter. + */ + +void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2; /* Temporary variables to hold state values */ + q31_t c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize / 3; + + while (blkCnt > 0U) + { + /* Copy 3 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 2 samples from the state buffer: x[n-numTaps], x[n-numTaps-1] */ + x0 = *px++; + x1 = *px++; + + /* Loop unrolling: process 3 taps at a time. */ + tapCnt = numTaps / 3; + + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-2] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x0 * c0); + acc1 += ((q63_t) x1 * c0); + acc2 += ((q63_t) x2 * c0); + + /* Read the coefficient and state */ + c0 = *(pb + 1U); + x0 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x1 * c0); + acc1 += ((q63_t) x2 * c0); + acc2 += ((q63_t) x0 * c0); + + /* Read the coefficient and state */ + c0 = *(pb + 2U); + x1 = *(px++); + + /* update coefficient pointer */ + pb += 3U; + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x2 * c0); + acc1 += ((q63_t) x0 * c0); + acc2 += ((q63_t) x1 * c0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x3U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x0 * c0); + acc1 += ((q63_t) x1 * c0); + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 3 to process the next group of 3 samples */ + pState = pState + 3; + + /* The result is in 2.30 format. Convert to 1.31 and store in destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31U); + *pDst++ = (q31_t) (acc1 >> 31U); + *pDst++ = (q31_t) (acc2 >> 31U); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x3U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += (q63_t) *px++ * *pb++; + + i--; + } while (i > 0U); + + /* Result is in 2.62 format. Convert to 1.31 and store in destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31U); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c new file mode 100644 index 0000000..5f6d354 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c @@ -0,0 +1,323 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q7.c + * Description: Q7 FIR filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for Q7 FIR filter. + @param[in] S points to an instance of the Q7 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is converted to 18.7 format by discarding the low 7 bits. + Finally, the result is truncated to 1.7 format. + */ + +void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCurnt; /* Points to the current sample of the state */ + q7_t *px; /* Temporary pointer for state buffer */ + const q7_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q7_t x0, x1, x2, x3, c0; /* Temporary variables to hold state */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 3 samples from the state buffer: + * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Loop unrolling. Process 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-3] sample */ + x3 = *px; + + /* acc0 += b[numTaps] * x[n-numTaps] */ + acc0 += ((q15_t) x0 * c0); + + /* acc1 += b[numTaps] * x[n-numTaps-1] */ + acc1 += ((q15_t) x1 * c0); + + /* acc2 += b[numTaps] * x[n-numTaps-2] */ + acc2 += ((q15_t) x2 * c0); + + /* acc3 += b[numTaps] * x[n-numTaps-3] */ + acc3 += ((q15_t) x3 * c0); + + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb + 1U); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x1 * c0); + acc1 += ((q15_t) x2 * c0); + acc2 += ((q15_t) x3 * c0); + acc3 += ((q15_t) x0 * c0); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb + 2U); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x2 * c0); + acc1 += ((q15_t) x3 * c0); + acc2 += ((q15_t) x0 * c0); + acc3 += ((q15_t) x1 * c0); + + /* Read the b[numTaps-3] coefficients */ + c0 = *(pb + 3U); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px + 3U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x3 * c0); + acc1 += ((q15_t) x0 * c0); + acc2 += ((q15_t) x1 * c0); + acc3 += ((q15_t) x2 * c0); + + /* update coefficient pointer */ + pb += 4U; + px += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x3 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x0 * c0); + acc1 += ((q15_t) x1 * c0); + acc2 += ((q15_t) x2 * c0); + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The results in the 4 accumulators are in 2.62 format. Convert to 1.31 + Then store the 4 outputs in the destination buffer. */ + acc0 = __SSAT((acc0 >> 7U), 8); + *pDst++ = acc0; + acc1 = __SSAT((acc1 >> 7U), 8); + *pDst++ = acc1; + acc2 = __SSAT((acc2 >> 7U), 8); + *pDst++ = acc2; + acc3 = __SSAT((acc3 >> 7U), 8); + *pDst++ = acc3; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + acc0 += (q15_t) * (px++) * (*(pb++)); + i--; + } while (i > 0U); + + /* The result is in 2.14 format. Convert to 1.7 + Then store the output in the destination buffer. */ + *pDst++ = __SSAT((acc0 >> 7U), 8); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c new file mode 100644 index 0000000..f44f037 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_f32.c + * Description: Floating-point sparse FIR filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters + + This group of functions implements sparse FIR filters. + Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero. + Sparse filters are used for simulating reflections in communications and audio applications. + + There are separate functions for Q7, Q15, Q31, and floating-point data types. + The functions operate on blocks of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst points to input and output arrays respectively containing blockSize values. + + @par Algorithm + The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients. + This is in addition to the coefficient array b. + The implementation essentially skips the multiplications by zero and leads to an efficient realization. + 
+      y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
+
+ @par + \image html FIRSparse.gif "Sparse FIR filter. b[n] represents the filter coefficients" + @par + pCoeffs points to a coefficient array of size numTaps; + pTapDelay points to an array of nonzero indices and is also of size numTaps; + pState points to a state array of size maxDelay + blockSize, where + maxDelay is the largest offset value that is ever used in the pTapDelay array. + Some of the processing functions also require temporary working buffers. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 4 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 4 different data type filter instance structures + 
+      arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+
+ + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the sparse FIR filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the floating-point sparse FIR filter. + @param[in] S points to an instance of the floating-point sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + */ + +void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Scratch buffer pointer */ + float32_t *py = pState; /* Temporary pointers for state buffer */ + float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + float32_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + float32_t coeff = *pCoeffs++; /* Read the first coefficient value */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + *pOut++ = *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement tap loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c new file mode 100644 index 0000000..7745e71 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_f32.c + * Description: Floating-point sparse FIR filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the floating-point sparse FIR filter. + @param[in,out] S points to an instance of the floating-point sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of samples processed by the arm_fir_sparse_f32() function. + */ + +void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c new file mode 100644 index 0000000..d07d611 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q15.c + * Description: Q15 sparse FIR filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q15 sparse FIR filter. + @param[in,out] S points to an instance of the Q15 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of words processed by arm_fir_sparse_q15() function. + */ + +void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c new file mode 100644 index 0000000..7c32cea --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q31.c + * Description: Q31 sparse FIR filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q31 sparse FIR filter. + @param[in,out] S points to an instance of the Q31 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the number of words processed by arm_fir_sparse_q31() function. + */ + +void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c new file mode 100644 index 0000000..98153f3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q7.c + * Description: Q7 sparse FIR filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q7 sparse FIR filter. + @param[in,out] S points to an instance of the Q7 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of samples processed by the arm_fir_sparse_q7() function. + */ + +void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c new file mode 100644 index 0000000..9cea93e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q15.c + * Description: Q15 sparse FIR filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q15 sparse FIR filter. + @param[in] S points to an instance of the Q15 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] pScratchOut points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator. + Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator. + If the accumulator result overflows it will wrap around rather than saturate. + After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format. + In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. + */ + +void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary pointers for scratch buffer */ + q15_t *py = pState; /* Temporary pointers for state buffer */ + q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q15_t *pOut = pDst; /* Working pointer for output */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q15_t coeff = *pCoeffs++; /* Read the first coefficient value */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in1, in2; /* Temporary variables */ +#endif + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q15(py, (int32_t) delaySize, &S->stateIndex, 1,pSrc, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in1 = *pScr2++; + in2 = *pScr2++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pScr2++; + in2 = *pScr2++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c new file mode 100644 index 0000000..86d3e1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c @@ -0,0 +1,357 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q31.c + * Description: Q31 sparse FIR filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q31 sparse FIR filter. + @param[in] S points to an instance of the Q31 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The 1.31 x 1.31 multiplications are truncated to 2.30 format. + This leads to loss of precision on the intermediate multiplications and provides only a single guard bit. + If the accumulator result overflows, it wraps around rather than saturate. + In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. + */ + +void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Scratch buffer pointer */ + q31_t *py = pState; /* Temporary pointers for state buffer */ + q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q31_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t in; + q63_t out; /* Temporary output variable */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, + (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement tap loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Working output pointer is updated */ + pOut = pDst; + + /* Output is converted into 1.31 format. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c new file mode 100644 index 0000000..7a2b57f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q7.c + * Description: Q7 sparse FIR filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q7 sparse FIR filter. + @param[in] S points to an instance of the Q7 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] pScratchOut points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is then converted to 18.7 format by discarding the low 7 bits. + Finally, the result is truncated to 1.7 format. + */ + +void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *px; /* Scratch buffer pointer */ + q7_t *py = pState; /* Temporary pointers for state buffer */ + q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q7_t *pOut = pDst; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q31_t in; + q7_t coeff = *pCoeffs++; /* Read the coefficient value */ + +#if defined (ARM_MATH_LOOPUNROLL) + q7_t in1, in2, in3, in4; +#endif + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + write_q7x4_ia (&pOut, __PACKq7(in1, in2, in3, in4)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c new file mode 100644 index 0000000..c48efe3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c @@ -0,0 +1,354 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_f32.c + * Description: Floating-point IIR Lattice filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters + + This set of functions implements lattice filters + for Q15, Q31 and floating-point data types. Lattice filters are used in a + variety of adaptive filter applications. The filter structure has feedforward and + feedback components and the net impulse response is infinite length. + The functions operate on blocks + of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst point to input and output arrays containing blockSize values. + + @par Algorithm + \image html IIRLattice.gif "Infinite Impulse Response Lattice filter" + @par + 
+      fN(n)   = x(n)
+      fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ..., 1
+      gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ..., 1
+      y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
+
+ @par + pkCoeffs points to array of reflection coefficients of size numStages. + Reflection Coefficients are stored in time-reversed order. + @par + 
+     {kN, kN-1, ..., k1}
+
+ @par + pvCoeffs points to the array of ladder coefficients of size (numStages+1). + Ladder coefficients are stored in time-reversed order. + 
+      {vN, vN-1, ..., v0}
+
+ @par + pState points to a state array of size numStages + blockSize. + The state variables shown in the figure above (the g values) are stored in the pState array. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: + 
+      arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
+      arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
+      arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
+
+ @par + where numStages is the number of stages in the filter; pState points to the state buffer array; + pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the IIR lattice filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the floating-point IIR lattice filter. + @param[in] S points to an instance of the floating-point IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pStateCur; /* State current pointer */ + float32_t acc; /* Accumlator */ + float32_t fnext1, fnext2, gcurr1, gnext; /* Temporary variables for lattice stages */ + float32_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t gcurr2; /* Temporary variables for lattice stages */ + float32_t k1, k2; + float32_t v1, v2, v3, v4; +#endif + + /* initialise loop count */ + blkCnt = blockSize; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fnext2 = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0.0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages) >> 2U; + + while (tapCnt > 0U) + { + /* Read gN-1(n-1) from state buffer */ + gcurr1 = *px1; + + /* read reflection coefficient kN */ + k1 = *pk; + + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext1 = fnext2 - (k1 * gcurr1); + + /* read ladder coefficient vN */ + v1 = *pv; + + /* read next reflection coefficient kN-1 */ + k2 = *(pk + 1U); + + /* Read gN-2(n-1) from state buffer */ + gcurr2 = *(px1 + 1U); + + /* read next ladder coefficient vN-1 */ + v2 = *(pv + 1U); + + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext2 = fnext1 - (k2 * gcurr2); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = gcurr1 + (k1 * fnext1); + + /* read reflection coefficient kN-2 */ + k1 = *(pk + 2U); + + /* write gN(n) into state for next sample processing */ + *px2++ = gnext; + + /* Read gN-3(n-1) from state buffer */ + gcurr1 = *(px1 + 2U); + + /* y(n) += gN(n) * vN */ + acc += (gnext * v1); + + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fnext1 = fnext2 - (k1 * gcurr1); + + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = gcurr2 + (k2 * fnext2); + + /* Read gN-4(n-1) from state buffer */ + gcurr2 = *(px1 + 3U); + + /* y(n) += gN-1(n) * vN-1 */ + acc += (gnext * v2); + + /* read reflection coefficient kN-3 */ + k2 = *(pk + 3U); + + /* write gN-1(n) into state for next sample processing */ + *px2++ = gnext; + + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext2 = fnext1 - (k2 * gcurr2); + + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = gcurr1 + (k1 * fnext1); + + /* read ladder coefficient vN-2 */ + v3 = *(pv + 2U); + + /* y(n) += gN-2(n) * vN-2 */ + acc += (gnext * v3); + + /* write gN-2(n) into state for next sample processing */ + *px2++ = gnext; + + /* update pointer */ + pk += 4U; + + /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */ + gnext = (fnext2 * k2) + gcurr2; + + /* read next ladder coefficient vN-3 */ + v4 = *(pv + 3U); + + /* y(n) += gN-4(n) * vN-4 */ + acc += (gnext * v4); + + /* write gN-3(n) into state for next sample processing */ + *px2++ = gnext; + + /* update pointers */ + px1 += 4U; + pv += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numStages; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr1 = *px1++; + /* Process sample for last taps */ + fnext1 = fnext2 - ((*pk) * gcurr1); + gnext = (fnext1 * (*pk++)) + gcurr1; + /* Output samples for last taps */ + acc += (gnext * (*pv++)); + *px2++ = gnext; + fnext2 = fnext1; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (fnext2 * (*pv)); + + *px2++ = fnext2; + + /* write out into pDst */ + *pDst++ = acc; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* Copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = numStages; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c new file mode 100644 index 0000000..bd9f933 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_f32.c + * Description: Floating-point IIR lattice filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the floating-point IIR lattice filter. + @param[in] S points to an instance of the floating-point IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c new file mode 100644 index 0000000..01abf48 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_q15.c + * Description: Q15 IIR lattice filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q15 IIR lattice filter. + @param[in] S points to an instance of the Q15 IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c new file mode 100644 index 0000000..b472f6c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_q31.c + * Description: Initialization function for the Q31 IIR lattice filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q31 IIR lattice filter. + @param[in] S points to an instance of the Q31 IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c new file mode 100644 index 0000000..9dbea81 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c @@ -0,0 +1,396 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_q15.c + * Description: Q15 IIR Lattice filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q15 IIR lattice filter. + @param[in] S points to an instance of the Q15 IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pStateCur; /* State current pointer */ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + q15_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q15_t out; /* Temporary variable for output */ + +#if defined (ARM_MATH_DSP) && defined (ARM_MATH_LOOPUNROLL) + q15_t gnext1, gnext2; /* Temporary variables for lattice stages */ + q31_t v; /* Temporary variable for ladder coefficient */ +#endif + + /* initialise loop count */ + blkCnt = blockSize; + +#if defined (ARM_MATH_DSP) + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + /* Process sample for first tap */ + gcurr = *px1++; + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages - 1U) >> 2U; + + while (tapCnt > 0U) + { + /* Process sample for 2nd, 6th ...taps */ + /* Read gN-2(n-1) from state buffer */ + gcurr = *px1++; + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext1 = (q15_t) __SSAT(gnext, 16); + /* write gN-1(n) into state for next sample processing */ + *px2++ = (q15_t) gnext1; + + /* Process sample for 3nd, 7th ...taps */ + /* Read gN-3(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 3rd, 7th .. taps */ + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15); + fcurr = __SSAT(fcurr, 16); + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr; + gnext2 = (q15_t) __SSAT(gnext, 16); + /* write gN-2(n) into state */ + *px2++ = (q15_t) gnext2; + + /* Read vN-1 and vN-2 at a time */ + v = read_q15x2_ia (&pv); + + /* Pack gN-1(n) and gN-2(n) */ + +#ifndef ARM_MATH_BIG_ENDIAN + gnext = __PKHBT(gnext1, gnext2, 16); +#else + gnext = __PKHBT(gnext2, gnext1, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* y(n) += gN-1(n) * vN-1 */ + /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */ + /* y(n) += gN-2(n) * vN-2 */ + /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */ + acc = __SMLALD(gnext, v, acc); + + /* Process sample for 4th, 8th ...taps */ + /* Read gN-4(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 4th, 8th .. taps */ + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext1 = (q15_t) __SSAT(gnext, 16); + /* write gN-3(n) for the next sample process */ + *px2++ = (q15_t) gnext1; + + /* Process sample for 5th, 9th ...taps */ + /* Read gN-5(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 5th, 9th .. taps */ + /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */ + fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15); + fcurr = __SSAT(fcurr, 16); + /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */ + gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr; + gnext2 = (q15_t) __SSAT(gnext, 16); + /* write gN-4(n) for the next sample process */ + *px2++ = (q15_t) gnext2; + + /* Read vN-3 and vN-4 at a time */ + v = read_q15x2_ia (&pv); + + /* Pack gN-3(n) and gN-4(n) */ +#ifndef ARM_MATH_BIG_ENDIAN + gnext = __PKHBT(gnext1, gnext2, 16); +#else + gnext = __PKHBT(gnext2, gnext1, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* y(n) += gN-4(n) * vN-4 */ + /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */ + /* y(n) += gN-3(n) * vN-3 */ + /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */ + acc = __SMLALD(gnext, v, acc); + + /* Decrement loop counter */ + tapCnt--; + } + + fnext = fcurr; + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numStages - 1U) % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* Output samples for last taps */ + acc += (q31_t) (((q31_t) gnext * (*pv++))); + *px2++ = (q15_t) gnext; + fcurr = fnext; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) (((q31_t) fnext * (*pv++))); + + out = (q15_t) __SSAT(acc >> 15, 16); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - ((gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = ((fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) ((fnext * (*pv++))); + + out = (q15_t) __SSAT(acc >> 15, 16); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c new file mode 100644 index 0000000..c4b9a76 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c @@ -0,0 +1,356 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_q31.c + * Description: Q31 IIR Lattice filter processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q31 IIR lattice filter. + @param[in] S points to an instance of the Q31 IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits. + After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format. + */ + +void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pStateCur; /* State current pointer */ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + + + /* initialise loop count */ + blkCnt = blockSize; + +#if defined (ARM_MATH_DSP) + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + /* Process sample for first tap */ + gcurr = *px1++; + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages - 1U) >> 2U; + + while (tapCnt > 0U) + { + /* Process sample for 2nd, 6th ...taps */ + /* Read gN-2(n-1) from state buffer */ + gcurr = *px1++; + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + /* y(n) += gN-1(n) * vN-1 */ + /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-1(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 3nd, 7th ...taps */ + /* Read gN-3(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 3rd, 7th .. taps */ + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31)); + /* y(n) += gN-2(n) * vN-2 */ + /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-2(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 4th, 8th ...taps */ + /* Read gN-4(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 4th, 8th .. taps */ + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + /* y(n) += gN-3(n) * vN-3 */ + /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-3(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 5th, 9th ...taps */ + /* Read gN-5(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 5th, 9th .. taps */ + /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */ + fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31)); + /* y(n) += gN-4(n) * vN-4 */ + /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */ + acc += ((q63_t) gnext * *pv++); + + /* write gN-4(n) into state for next sample processing */ + *px2++ = gnext; + + /* Decrement loop counter */ + tapCnt--; + } + + fnext = fcurr; + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numStages - 1U) % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + + /* Output samples for last taps */ + acc += ((q63_t) gnext * *pv++); + *px2++ = gnext; + fcurr = fnext; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += ((q63_t) fnext * *pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* Copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = clip_q63_to_q31(((q63_t) fcurr - ((q31_t) (((q63_t) gcurr * (*pk )) >> 31)))); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = clip_q63_to_q31(((q63_t) gcurr + ((q31_t) (((q63_t) fnext * (*pk++)) >> 31)))); + + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += ((q63_t) fnext * *pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c new file mode 100644 index 0000000..4fc6e7e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c @@ -0,0 +1,533 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_f32.c + * Description: Processing function for the floating-point LMS filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LMS Least Mean Square (LMS) Filters + + LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions. + LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal. + Adaptive filters are often used in communication systems, equalizers, and noise removal. + The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types. + The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal. + + An LMS filter consists of two components as shown below. + The first component is a standard transversal or FIR filter. + The second component is a coefficient update mechanism. + The LMS filter has two input signals. + The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. + That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. + The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. + This "error signal" tends towards zero as the filter adapts. + The LMS processing functions accept the input and reference input signals and generate the filter output and error signal. + \image html LMS.gif "Internal structure of the Least Mean Square filter" + + The functions operate on blocks of data and each call to the function processes + blockSize samples through the filter. + pSrc points to input signal, pRef points to reference signal, + pOut points to output signal and pErr points to error signal. + All arrays contain blockSize values. + + The functions operate on a block-by-block basis. + Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. + The convergence of the LMS filter is slower compared to the normalized LMS algorithm. + + @par Algorithm + The output signal y[n] is computed by a standard FIR filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ + @par + The error signal equals the difference between the reference signal d[n] and the filter output: + 
+      e[n] = d[n] - y[n].
+
+ + @par + After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis: + 
+      b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1
+
+ where mu is the step size and controls the rate of coefficient convergence. + @par + In the APIs, pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. + The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed. + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter and + coefficient and state arrays cannot be shared among instances. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 3 different data type filter instance structures + 
+     arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
+     arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
+     arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
+
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients. + + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the LMS filter. + The following issues must be considered: + - Scaling of coefficients + - Overflow and saturation + + @par Scaling of Coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift. + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + This essentially scales the filter coefficients by 2^postShift and + allows the filter coefficients to exceed the range [+1 -1). + The value of postShift is set by the user based on the expected gain through the system being modeled. + + @par Overflow and Saturation + Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are + described separately as part of the function specific documentation below. + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for floating-point LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_NEON) +void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w = 0.0f; /* weight factor */ + + float32x4_t tempV, sumV, xV, bV; + float32x2_t tempV2; + + e = 0.0f; + d = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Set the accumulator to zero */ + sum = 0.0f; + sumV = vdupq_n_f32(0.0); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + sumV = vmlaq_f32(sumV, xV, bV); + + px += 4; + pb += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + tempV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = tempV2[0] + tempV2[1]; + + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result in the accumulator, store in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = (float32_t) (*pRef++); + e = d - sum; + *pErr++ = e; + + /* Calculation of Weighting factor for the updating filter coefficients */ + w = e * mu; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + px += 4; + bV = vmlaq_n_f32(bV,xV,w); + + vst1q_f32(pb,bV); + pb += 4; + + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb = *pb + (w * (*px++)); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Process 4 taps at a time for (numTaps - 1U) samples copy */ + tapCnt = (numTaps - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + tempV = vld1q_f32(pState); + vst1q_f32(pStateCurnt,tempV); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + + +} +#else +void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + float32_t acc, e; /* Accumulator, error */ + float32_t w; /* Weight factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + w = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = acc; + + /* Compute and store error */ + e = (float32_t) *pRef++ - acc; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + w = e * mu; + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c new file mode 100644 index 0000000..f418f46 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c @@ -0,0 +1,81 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_f32.c + * Description: Floating-point LMS filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for floating-point LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32(). + */ + +void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps */ + memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; +} + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c new file mode 100644 index 0000000..fe0a5c5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_q15.c + * Description: Q15 LMS filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for the Q15 LMS filter. + @param[in] S points to an instance of the Q15 LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to the array of state variables and size of array is + numTaps+blockSize-1 samples, where blockSize is the number of + input samples processed by each call to arm_lms_q15(). + */ + +void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Assign postShift value to be applied */ + S->postShift = postShift; +} + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c new file mode 100644 index 0000000..3410b9f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_q31.c + * Description: Q31 LMS filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for Q31 LMS filter. + @param[in] S points to an instance of the Q31 LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @param[in] postShift bit shift applied to coefficients + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to + arm_lms_q31(). + */ + +void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Assign postShift value to be applied */ + S->postShift = postShift; +} + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c new file mode 100644 index 0000000..28ab04a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c @@ -0,0 +1,564 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_f32.c + * Description: Processing function for the floating-point NLMS filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LMS_NORM Normalized LMS Filters + + This set of functions implements a commonly used adaptive filter. + It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization + factor which increases the adaptation rate of the filter. + The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types. + + A normalized least mean square (NLMS) filter consists of two components as shown below. + The first component is a standard transversal or FIR filter. + The second component is a coefficient update mechanism. + The NLMS filter has two input signals. + The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. + That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. + The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. + This "error signal" tends towards zero as the filter adapts. + The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal. + \image html LMS.gif "Internal structure of the NLMS adaptive filter" + + The functions operate on blocks of data and each call to the function processes + blockSize samples through the filter. + pSrc points to input signal, pRef points to reference signal, + pOut points to output signal and pErr points to error signal. + All arrays contain blockSize values. + + The functions operate on a block-by-block basis. + Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. + The convergence of the LMS filter is slower compared to the normalized LMS algorithm. + + @par Algorithm + The output signal y[n] is computed by a standard FIR filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ + @par + The error signal equals the difference between the reference signal d[n] and the filter output: + 
+      e[n] = d[n] - y[n].
+
+ + @par + After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated: + 
+     E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
+
+ The filter coefficients b[k] are then updated on a sample-by-sample basis: + 
+      b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1
+
+ where mu is the step size and controls the rate of coefficient convergence. + @par + In the APIs, pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. + The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter and + coefficient and state arrays cannot be shared among instances. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero. + For Q7, Q15, and Q31 the following fields must also be initialized; + recipTable, postShift + @par + Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter. + The following issues must be considered: + - Scaling of coefficients + - Overflow and saturation + + @par Scaling of Coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift. + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + This essentially scales the filter coefficients by 2^postShift and + allows the filter coefficients to exceed the range [+1 -1). + The value of postShift is set by the user based on the expected gain through the system being modeled. + + @par Overflow and Saturation + Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are + described separately as part of the function specific documentation below. + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for floating-point normalized LMS filter. + @param[in] S points to an instance of the floating-point normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_NEON) +void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */ + + float32x4_t tempV, sumV, xV, bV; + float32x2_t tempV2; + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + d = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + sum = 0.0f; + sumV = vdupq_n_f32(0.0); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + sumV = vmlaq_f32(sumV, xV, bV); + + px += 4; + pb += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + tempV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = tempV2[0] + tempV2[1]; + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result in the accumulator, store in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = (float32_t) (*pRef++); + e = d - sum; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = (e * mu) / (energy + 0.000000119209289f); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + px += 4; + bV = vmlaq_n_f32(bV,xV,w); + + vst1q_f32(pb,bV); + pb += 4; + + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Process 4 taps at a time for (numTaps - 1U)/4 samples copy */ + tapCnt = (numTaps - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + tempV = vld1q_f32(pState); + vst1q_f32(pStateCurnt,tempV); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else +void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + float32_t acc, e; /* Accumulator, error */ + float32_t w; /* Weight factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t x0, in; /* Temporary variable to hold input sample and state */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + acc = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = acc; + + /* Compute and store error */ + e = (float32_t) *pRef++ - acc; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = (e * mu) / (energy + 0.000000119209289f); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c new file mode 100644 index 0000000..543dc72 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_f32.c + * Description: Floating-point NLMS filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for floating-point normalized LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to arm_lms_norm_f32(). + */ + +void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialise Energy to zero */ + S->energy = 0.0f; + + /* Initialise x0 to zero */ + S->x0 = 0.0f; +} + +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c new file mode 100644 index 0000000..d581ac1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_q15.c + * Description: Q15 NLMS filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for Q15 normalized LMS filter. + @param[in] S points to an instance of the Q15 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to the array of state variables and size of array is + numTaps+blockSize-1 samples, where blockSize is the number of input samples processed + by each call to arm_lms_norm_q15(). + */ + +void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign post Shift value applied to coefficients */ + S->postShift = postShift; + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialize reciprocal pointer table */ + S->recipTable = (q15_t *) armRecipTableQ15; + + /* Initialise Energy to zero */ + S->energy = 0; + + /* Initialise x0 to zero */ + S->x0 = 0; +} + +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c new file mode 100644 index 0000000..30e78ec --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_q31.c + * Description: Q31 NLMS filter initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for Q31 normalized LMS filter. + @param[in] S points to an instance of the Q31 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to arm_lms_norm_q31(). + */ + +void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign post Shift value applied to coefficients */ + S->postShift = postShift; + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialize reciprocal pointer table */ + S->recipTable = (q31_t *) armRecipTableQ31; + + /* Initialise Energy to zero */ + S->energy = 0; + + /* Initialise x0 to zero */ + S->x0 = 0; +} + +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c new file mode 100644 index 0000000..c15ad5e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c @@ -0,0 +1,297 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_q15.c + * Description: Processing function for Q15 normalized LMS filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for Q15 normalized LMS filter. + @param[in] S points to an instance of the Q15 normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and + multiplications yield a 2.30 result. The 2.30 intermediate results are + accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full + precision of intermediate multiplications is preserved. After all additions + have been performed, the accumulator is truncated to 34.15 format by + discarding low 15 bits. Lastly, the accumulator is saturated to yield a + result in 1.15 format. + @par + In this filter, filter coefficients are updated for each sample and the + updation of filter cofficients are saturted. + */ + +void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t energy; /* Energy of the input */ + q15_t e = 0, d = 0; /* Error, reference data sample */ + q15_t w = 0, in; /* Weight factor and state */ + q15_t x0; /* Temporary variable to hold input sample */ + q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Temporary variable for coefficient */ + q31_t acc_l, acc_h; /* Temporary input */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + int32_t uShift = (32 - lShift); + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= (((q31_t) x0 * (x0)) >> 15); + energy += (((q31_t) in * (in)) >> 15); + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t) (((q31_t) (*px++) * (*pb++))); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = __SSAT(acc, 16U); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q15_t) acc; + *pErr++ = e; + + /* Calculation of 1/energy */ + postShift = arm_recip_q15((q15_t) energy + DELTA_Q15, &oneByEnergy, S->recipTable); + + /* Calculation of e * mu value */ + errorXmu = (q15_t) (((q31_t) e * mu) >> 15); + + /* Calculation of (e * mu) * (1/energy) value */ + acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift)); + + /* Weighting factor for the normalized version */ + w = (q15_t) __SSAT((q31_t) acc, 16); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + /* Decrement loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q15_t) energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c new file mode 100644 index 0000000..e26219e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c @@ -0,0 +1,311 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_q31.c + * Description: Processing function for the Q31 NLMS filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for Q31 normalized LMS filter. + @param[in] S points to an instance of the Q31 normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by + log2(numTaps) bits. The reference signal should not be scaled down. + After all multiply-accumulates are performed, the 2.62 accumulator is shifted + and saturated to 1.31 format to yield the final result. + The output signal and error signal are in 1.31 format. + @par + In this filter, filter coefficients are updated for each sample and the + updation of filter cofficients are saturted. + */ + +void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q63_t energy; /* Energy of the input */ + q31_t e = 0; /* Error data sample */ + q31_t w = 0, in; /* Weight factor and state */ + q31_t x0; /* Temporary variable to hold input sample */ + q31_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + q31_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy = (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32); + energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32); + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-1] * x[n-N-1] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-2] * x[n-N-2] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-3] * x[n-N-3] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t) acc; + *pErr++ = e; + + /* Calculates the reciprocal of energy */ + postShift = arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]); + + /* Calculation of product of (e * mu) */ + errorXmu = (q31_t) (((q63_t) e * mu) >> 31); + + /* Weighting factor for the normalized version */ + w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift)); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef is in 2.30 format */ + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + /* get coef in 1.31 format by left shifting */ + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q31_t) energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c new file mode 100644 index 0000000..0fc9878 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c @@ -0,0 +1,262 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_q15.c + * Description: Processing function for Q15 LMS filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for Q15 LMS filter. + @param[in] S points to an instance of the Q15 LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + @par + In this filter, filter coefficients are updated for each sample and + the updation of filter cofficients are saturted. + */ + +void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q15_t e = 0; /* Error of data sample */ + q15_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coefficient */ + q31_t acc_l, acc_h; /* Temporary input */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + int32_t uShift = (32 - lShift); + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t) (((q31_t) (*px++) * (*pb++))); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = __SSAT(acc, 16U); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q15_t) acc; + *pErr++ = (q15_t) e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q15_t) (((q31_t) e * (mu)) >> 15); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c new file mode 100644 index 0000000..b0c0e27 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c @@ -0,0 +1,283 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_q31.c + * Description: Processing function for the Q31 LMS filter + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for Q31 LMS filter. + @param[in] S points to an instance of the Q31 LMS filter structure. + @param[in] pSrc points to the block of input data. + @param[in] pRef points to the block of reference data. + @param[out] pOut points to the block of output data. + @param[out] pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clips. + In order to avoid overflows completely the input signal must be scaled down by + log2(numTaps) bits. + The reference signal should not be scaled down. + After all multiply-accumulates are performed, the 2.62 accumulator is shifted + and saturated to 1.31 format to yield the final result. + The output signal and error signal are in 1.31 format. + @par + In this filter, filter coefficients are updated for each sample and + the updation of filter cofficients are saturted. + */ + +void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t e = 0; /* Error of data sample */ + q31_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-1] * x[n-N-1] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-2] * x[n-N-2] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-3] * x[n-N-3] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t) acc; + *pErr++ = e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q31_t) (((q63_t) e * mu) >> 31); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef is in 2.30 format */ + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + /* get coef in 1.31 format by left shifting */ + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt new file mode 100644 index 0000000..d48d6b1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt @@ -0,0 +1,16 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSPMatrix) + + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPMatrix STATIC ${SRC}) + +configdsp(CMSISDSPMatrix ..) + +### Includes +target_include_directories(CMSISDSPMatrix PUBLIC "${DSP}/../../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c new file mode 100644 index 0000000..da721fe --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: MatrixFunctions.c + * Description: Combination of all matrix function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_mat_add_f32.c" +#include "arm_mat_add_q15.c" +#include "arm_mat_add_q31.c" +#include "arm_mat_cmplx_mult_f32.c" +#include "arm_mat_cmplx_mult_q15.c" +#include "arm_mat_cmplx_mult_q31.c" +#include "arm_mat_init_f32.c" +#include "arm_mat_init_q15.c" +#include "arm_mat_init_q31.c" +#include "arm_mat_inverse_f32.c" +#include "arm_mat_inverse_f64.c" +#include "arm_mat_mult_f32.c" +#include "arm_mat_mult_fast_q15.c" +#include "arm_mat_mult_fast_q31.c" +#include "arm_mat_mult_q15.c" +#include "arm_mat_mult_q31.c" +#include "arm_mat_scale_f32.c" +#include "arm_mat_scale_q15.c" +#include "arm_mat_scale_q31.c" +#include "arm_mat_sub_f32.c" +#include "arm_mat_sub_q15.c" +#include "arm_mat_sub_q31.c" +#include "arm_mat_trans_f32.c" +#include "arm_mat_trans_q15.c" +#include "arm_mat_trans_q31.c" diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c new file mode 100644 index 0000000..8e1246c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c @@ -0,0 +1,232 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_f32.c + * Description: Floating-point matrix addition + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixAdd Matrix Addition + + Adds two matrices. + \image html MatrixAddition.gif "Addition of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixAdd + @{ + */ + + +/** + @brief Floating-point matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_NEON) +/* + +Neon version is assuming the matrix is small enough. +So no blocking is used for taking into account cache effects. +For big matrix, there exist better libraries for Neon. + +*/ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + float32_t inA1, inA2, inB1, inB2, out1, out2; /* temporary variables */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + blkCnt = numSamples >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pIn1); + vec2 = vld1q_f32(pIn2); + res = vaddq_f32(vec1, vec2); + vst1q_f32(pOut, res); + + /* update pointers to process next samples */ + pIn1 += 4U; + pIn2 += 4U; + pOut += 4U; + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + *pOut++ = (*pIn1++) + (*pIn2++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of MatrixAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c new file mode 100644 index 0000000..2aaf849 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_q15.c + * Description: Q15 matrix addition + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixAdd + @{ + */ + +/** + @brief Q15 matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + write_q15x2_ia (&pOut, __QADD16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); + + write_q15x2_ia (&pOut, __QADD16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c new file mode 100644 index 0000000..6194809 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_q31.c + * Description: Q31 matrix addition + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixAdd + @{ + */ + +/** + @brief Q31 matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ + *pOut++ = __QADD(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c new file mode 100644 index 0000000..8e2af31 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c @@ -0,0 +1,631 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_f32.c + * Description: Floating-point matrix multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup CmplxMatrixMult Complex Matrix Multiplication + + Complex Matrix multiplication is only defined if the number of columns of the + first matrix equals the number of rows of the second matrix. + Multiplying an M x N matrix with an N x P matrix results + in an M x P matrix. + @par + When matrix size checking is enabled, the functions check: + - that the inner dimensions of pSrcA and pSrcB are equal; + - that the size of the output matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Floating-point Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_NEON) +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + float32_t sumReal1, sumImag1; /* accumulator */ + float32_t a0, b0, c0, d0; + float32_t a1, a1B,b1, b1B, c1, d1; + float32_t sumReal2, sumImag2; /* accumulator */ + + + float32x4x2_t a0V, a1V; + float32x4_t accR0,accI0, accR1,accI1,tempR, tempI; + float32x2_t accum = vdup_n_f32(0); + float32_t *pIn1B = pSrcA->pData; + + uint16_t col, i = 0U, j, rowCnt, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + float32_t sumReal1B, sumImag1B; + float32_t sumReal2B, sumImag2B; + float32_t *pxB; + +#ifdef ARM_MATH_MATRIX_CHECK + + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + + rowCnt = row >> 1; + + /* Row loop */ + while (rowCnt > 0U) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + pxB = px + 2 * numColsB; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal1 = 0.0f; + sumImag1 = 0.0f; + sumReal1B = 0.0f; + sumImag1B = 0.0f; + + sumReal2 = 0.0f; + sumImag2 = 0.0f; + sumReal2B = 0.0f; + sumImag2B = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + pIn1B = pIn1 + 2*numColsA; + + accR0 = vdupq_n_f32(0.0); + accI0 = vdupq_n_f32(0.0); + accR1 = vdupq_n_f32(0.0); + accI1 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* Reading real part of complex matrix A */ + a0V = vld2q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + a1V = vld2q_f32(pIn1B); // load & separate real/imag pSrcA (de-interleave 2) + + pIn1 += 8; + pIn1B += 8; + + tempR[0] = *pIn2; + tempI[0] = *(pIn2 + 1U); + pIn2 += 2 * numColsB; + + tempR[1] = *pIn2; + tempI[1] = *(pIn2 + 1U); + pIn2 += 2 * numColsB; + + tempR[2] = *pIn2; + tempI[2] = *(pIn2 + 1U); + pIn2 += 2 * numColsB; + + tempR[3] = *pIn2; + tempI[3] = *(pIn2 + 1U); + pIn2 += 2 * numColsB; + + accR0 = vmlaq_f32(accR0,a0V.val[0],tempR); + accR0 = vmlsq_f32(accR0,a0V.val[1],tempI); + + accI0 = vmlaq_f32(accI0,a0V.val[1],tempR); + accI0 = vmlaq_f32(accI0,a0V.val[0],tempI); + + accR1 = vmlaq_f32(accR1,a1V.val[0],tempR); + accR1 = vmlsq_f32(accR1,a1V.val[1],tempI); + + accI1 = vmlaq_f32(accI1,a1V.val[1],tempR); + accI1 = vmlaq_f32(accI1,a1V.val[0],tempI); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR0), vget_high_f32(accR0)); + sumReal1 += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(accI0), vget_high_f32(accI0)); + sumImag1 += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(accR1), vget_high_f32(accR1)); + sumReal1B += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(accI1), vget_high_f32(accI1)); + sumImag1B += accum[0] + accum[1]; + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a1 = *pIn1; + a1B = *pIn1B; + + c1 = *pIn2; + + b1 = *(pIn1 + 1U); + b1B = *(pIn1B + 1U); + + d1 = *(pIn2 + 1U); + + sumReal1 += a1 * c1; + sumImag1 += b1 * c1; + + sumReal1B += a1B * c1; + sumImag1B += b1B * c1; + + pIn1 += 2U; + pIn1B += 2U; + pIn2 += 2 * numColsB; + + sumReal2 -= b1 * d1; + sumImag2 += a1 * d1; + + sumReal2B -= b1B * d1; + sumImag2B += a1B * d1; + + /* Decrement the loop counter */ + colCnt--; + } + + sumReal1 += sumReal2; + sumImag1 += sumImag2; + + sumReal1B += sumReal2B; + sumImag1B += sumImag2B; + + /* Store the result in the destination buffer */ + *px++ = sumReal1; + *px++ = sumImag1; + *pxB++ = sumReal1B; + *pxB++ = sumImag1B; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement the column loop counter */ + col--; + } + + /* Update the pointer pInA to point to the starting address of the next 2 row */ + i = i + 2*numColsB; + pInA = pInA + 4 * numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + } + + rowCnt = row & 1; + while (rowCnt > 0U) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal1 = 0.0f; + sumImag1 = 0.0f; + + sumReal2 = 0.0f; + sumImag2 = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + + accR0 = vdupq_n_f32(0.0); + accI0 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* Reading real part of complex matrix A */ + a0V = vld2q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + pIn1 += 8; + + tempR[0] = *pIn2; + tempI[0] = *(pIn2 + 1U); + pIn2 += 2 * numColsB; + + tempR[1] = *pIn2; + tempI[1] = *(pIn2 + 1U); + pIn2 += 2 * numColsB; + + tempR[2] = *pIn2; + tempI[2] = *(pIn2 + 1U); + pIn2 += 2 * numColsB; + + tempR[3] = *pIn2; + tempI[3] = *(pIn2 + 1U); + pIn2 += 2 * numColsB; + + accR0 = vmlaq_f32(accR0,a0V.val[0],tempR); + accR0 = vmlsq_f32(accR0,a0V.val[1],tempI); + + accI0 = vmlaq_f32(accI0,a0V.val[1],tempR); + accI0 = vmlaq_f32(accI0,a0V.val[0],tempI); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR0), vget_high_f32(accR0)); + sumReal1 += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(accI0), vget_high_f32(accI0)); + sumImag1 += accum[0] + accum[1]; + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a1 = *pIn1; + c1 = *pIn2; + + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + sumReal1 += a1 * c1; + sumImag1 += b1 * c1; + + pIn1 += 2U; + pIn2 += 2 * numColsB; + + sumReal2 -= b1 * d1; + sumImag2 += a1 * d1; + + /* Decrement the loop counter */ + colCnt--; + } + + sumReal1 += sumReal2; + sumImag1 += sumImag2; + + /* Store the result in the destination buffer */ + *px++ = sumReal1; + *px++ = sumImag1; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement the column loop counter */ + col--; + + } + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + float32_t sumReal, sumImag; /* Accumulator */ + float32_t a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0f; + sumImag = 0.0f; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sumReal; + *px++ = sumImag; + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c new file mode 100644 index 0000000..4c5a45b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c @@ -0,0 +1,340 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mat_mult_q15.c + * Description: Q15 complex matrix multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Q15 Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @param[in] pScratch points to an array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Conditions for optimum performance + Input, output and state buffers should be aligned by 32-bit + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. The inputs to the + multiplications are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then + truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + */ + +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch) +{ + q15_t *pSrcBT = pScratch; /* input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + q63_t sumReal, sumImag; /* accumulator */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#if defined (ARM_MATH_DSP) + q31_t prod1, prod2; + q31_t pSourceA, pSourceB; +#else + q15_t a, b, c, d; +#endif /* #if defined (ARM_MATH_DSP) */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and exchange the columns with row elements */ + col = numColsB >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + col = numColsB; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + 2U; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + do + { + /* Set variable sum, that acts as accumulator, to zero */ + sumReal = 0; + sumImag = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i * 2; + + /* Apply loop unrolling and compute 2 MACs simultaneously. */ + colCnt = numColsA >> 1U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia ((q15_t **) &pInA); + pSourceB = read_q15x2_ia ((q15_t **) &pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia ((q15_t **) &pInA); + pSourceB = read_q15x2_ia ((q15_t **) &pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* read real and imag values from pSrcA buffer */ + a = *pInA; + b = *(pInA + 1U); + /* read real and imag values from pSrcB buffer */ + c = *pInB; + d = *(pInB + 1U); + + /* Multiply and Accumlates */ + sumReal += (q31_t) a *c; + sumImag += (q31_t) a *d; + sumReal -= (q31_t) b *d; + sumImag += (q31_t) b *c; + + /* read next real and imag values from pSrcA buffer */ + a = *(pInA + 2U); + b = *(pInA + 3U); + /* read next real and imag values from pSrcB buffer */ + c = *(pInB + 2U); + d = *(pInB + 3U); + + /* update pointer */ + pInA += 4U; + + /* Multiply and Accumlates */ + sumReal += (q31_t) a * c; + sumImag += (q31_t) a * d; + sumReal -= (q31_t) b * d; + sumImag += (q31_t) b * c; + /* update pointer */ + pInB += 4U; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process odd column samples */ + if ((numColsA & 0x1U) > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia ((q15_t **) &pInA); + pSourceB = read_q15x2_ia ((q15_t **) &pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a = *pInA++; + b = *pInA++; + c = *pInB++; + d = *pInB++; + + /* Multiply and Accumlates */ + sumReal += (q31_t) a * c; + sumImag += (q31_t) a * d; + sumReal -= (q31_t) b * d; + sumImag += (q31_t) b * c; + +#endif /* #if defined (ARM_MATH_DSP) */ + + } + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (__SSAT(sumReal >> 15, 16)); + *px++ = (q15_t) (__SSAT(sumImag >> 15, 16)); + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c new file mode 100644 index 0000000..7b458f9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c @@ -0,0 +1,283 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_q31.c + * Description: Floating-point matrix multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Q31 Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + */ + +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + q63_t sumReal, sumImag; /* Accumulator */ + q31_t a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0; + sumImag = 0.0; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a0 * c0; + sumImag += (q63_t) b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b0 * d0; + sumImag += (q63_t) a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a0 * c0; + sumImag += (q63_t) b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b0 * d0; + sumImag += (q63_t) a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = (q31_t) clip_q63_to_q31(sumReal >> 31); + *px++ = (q31_t) clip_q63_to_q31(sumImag >> 31); + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c new file mode 100644 index 0000000..ce02a25 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_f32.c + * Description: Floating-point matrix initialization + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInit Matrix Initialization + + Initializes the underlying matrix data structure. + The functions set the numRows, + numCols, and pData fields + of the matrix data structure. + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Floating-point matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c new file mode 100644 index 0000000..0275503 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c @@ -0,0 +1,67 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_q15.c + * Description: Q15 matrix initialization + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Q15 matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c new file mode 100644 index 0000000..d5c5722 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_q31.c + * Description: Q31 matrix initialization + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInit Matrix Initialization + + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Q31 matrix initialization. + @param[in,out] S points to an instance of the Q31 matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c new file mode 100644 index 0000000..d602b98 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c @@ -0,0 +1,1127 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f32.c + * Description: Floating-point matrix inverse + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInv Matrix Inverse + + Computes the inverse of a matrix. + + The inverse is defined only if the input matrix is square and non-singular (the determinant is non-zero). + The function checks that the input and output matrices are square and of the same size. + + Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix + inversion of floating-point matrices. + + @par Algorithm + The Gauss-Jordan method is used to find the inverse. + The algorithm performs a sequence of elementary row-operations until it + reduces the input matrix to an identity matrix. Applying the same sequence + of elementary row-operations to an identity matrix yields the inverse matrix. + If the input matrix is singular, then the algorithm terminates and returns error status + ARM_MATH_SINGULAR. + \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method" + */ + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point matrix inverse. + @param[in] pSrc points to input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ +#if defined(ARM_MATH_NEON) +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + + float32_t maxC; /* maximum value in the column */ + + float32_t Xchg, in = 0.0f, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + float32x4_t vec1; + float32x4_t vec2; + float32x4_t tmpV; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) + || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for column i is the greatest of the column. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is not the most significant of the columns, exchange that row with a row + * below it that does contain the most significant value in column i. If the most + * significant value of the column is zero, then an inverse to that matrix does not exist. + * The most significant value of the column is the absolute maximum. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement the loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Grab the most significant value from column l */ + maxC = 0; + + for (i = l; i < numRows; i++) + { + maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC); + pInT1 += numCols; + } + + /* Update the status if the matrix is singular */ + if (maxC == 0.0f) + { + return ARM_MATH_SINGULAR; + } + + /* Restore pInT1 */ + pInT1 = pIn; + + /* Destination pointer modifier */ + k = 1U; + + /* Check if the pivot element is the most significant of the column */ + if ( (in > 0.0f ? in : -in) != maxC) + { + /* Loop over the number rows present below */ + i = numRows - (l + 1U); + + while (i > 0U) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * l); + pOutT2 = pOutT1 + (numCols * k); + + /* Look for the most significant element to + * replace in the rows below */ + if ((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + /* Update the destination pointer modifier */ + k++; + + /* Decrement the loop counter */ + i--; + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + tmpV = vdupq_n_f32(1.0/in); + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l) >> 2; + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + vec1 = vld1q_f32(pInT1); + + vec1 = vmulq_f32(vec1, tmpV); + vst1q_f32(pInT1, vec1); + pInT1 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = (numCols - l) & 3; + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols >> 2; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + vec1 = vld1q_f32(pInT2); + + vec1 = vmulq_f32(vec1, tmpV); + vst1q_f32(pInT2, vec1); + pInT2 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = numCols & 3; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + tmpV = vdupq_n_f32(in); + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l) >> 2; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + vec1 = vld1q_f32(pInT1); + vec2 = vld1q_f32(pPRT_in); + vec1 = vmlsq_f32(vec1, tmpV, vec2); + vst1q_f32(pInT1, vec1); + pPRT_in += 4; + pInT1 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = (numCols - l) & 3; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols >> 2; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + vec1 = vld1q_f32(pInT2); + vec2 = vld1q_f32(pPRT_pDst); + vec1 = vmlsq_f32(vec1, tmpV, vec2); + vst1q_f32(pInT2, vec1); + pPRT_pDst += 4; + pInT2 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = numCols & 3; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement the loop counter */ + j--; + } + + } + + /* Increment the temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement the loop counter */ + k--; + + /* Increment the pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + +#if defined (ARM_MATH_DSP) + float32_t maxC; /* maximum value in the column */ + + float32_t Xchg, in = 0.0f, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for column i is the greatest of the column. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is not the most significant of the columns, exchange that row with a row + * below it that does contain the most significant value in column i. If the most + * significant value of the column is zero, then an inverse to that matrix does not exist. + * The most significant value of the column is the absolute maximum. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Grab the most significant value from column l */ + maxC = 0; + for (i = l; i < numRows; i++) + { + maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC); + pInT1 += numCols; + } + + /* Update the status if the matrix is singular */ + if (maxC == 0.0f) + { + return ARM_MATH_SINGULAR; + } + + /* Restore pInT1 */ + pInT1 = pIn; + + /* Destination pointer modifier */ + k = 1U; + + /* Check if the pivot element is the most significant of the column */ + if ( (in > 0.0f ? in : -in) != maxC) + { + /* Loop over the number rows present below */ + i = numRows - (l + 1U); + + while (i > 0U) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * l); + pOutT2 = pOutT1 + (numCols * k); + + /* Look for the most significant element to + * replace in the rows below */ + if ((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + /* Update the destination pointer modifier */ + k++; + + /* Decrement loop counter */ + i--; + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + +#else + + float32_t Xchg, in = 0.0f; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Destination pointer modifier */ + k = 1U; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0f) + { + /* Loop over the number rows present below */ + for (i = (l + 1U); i < numRows; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * l); + pOutT2 = pOutT1 + (numCols * k); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0f) + { + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + } + + for (j = 0U; j < numCols; j++) + { + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + /* Update the destination pointer modifier */ + k++; + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* Pivot element of the row */ + in = *(pIn + (l * numCols)); + + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + *pInT1 = *pInT1 / in; + pInT1++; + } + for (j = 0U; j < numCols; j++) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + *pOutT1 = *pOutT1 / in; + pOutT1++; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + for (j = 0U; j < (numCols - l); j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pInT1 = *pInT1 - (in * *pPRT_in++); + pInT1++; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + for (j = 0U; j < numCols; j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pOutT1 = *pOutT1 - (in * *pPRT_pDst++); + pOutT1++; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of MatrixInv group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c new file mode 100644 index 0000000..4607e07 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c @@ -0,0 +1,673 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f64.c + * Description: Floating-point matrix inverse + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point (64 bit) matrix inverse. + @param[in] pSrc points to input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ + +arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pIn = pSrc->pData; /* input data matrix pointer */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + float64_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float64_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float64_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + +#if defined (ARM_MATH_DSP) + float64_t maxC; /* maximum value in the column */ + + float64_t Xchg, in = 0.0, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for column i is the greatest of the column. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is not the most significant of the columns, exchange that row with a row + * below it that does contain the most significant value in column i. If the most + * significant value of the column is zero, then an inverse to that matrix does not exist. + * The most significant value of the column is the absolute maximum. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Grab the most significant value from column l */ + maxC = 0; + for (i = l; i < numRows; i++) + { + maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC); + pInT1 += numCols; + } + + /* Update the status if the matrix is singular */ + if (maxC == 0.0) + { + return ARM_MATH_SINGULAR; + } + + /* Restore pInT1 */ + pInT1 = pIn; + + /* Destination pointer modifier */ + k = 1U; + + /* Check if the pivot element is the most significant of the column */ + if ( (in > 0.0 ? in : -in) != maxC) + { + /* Loop over the number rows present below */ + i = numRows - (l + 1U); + + while (i > 0U) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * l); + pOutT2 = pOutT1 + (numCols * k); + + /* Look for the most significant element to + * replace in the rows below */ + if ((*pInT2 > 0.0 ? *pInT2: -*pInT2) == maxC) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + /* Update the destination pointer modifier */ + k++; + + /* Decrement loop counter */ + i--; + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + +#else + + float64_t Xchg, in = 0.0; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Destination pointer modifier */ + k = 1U; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0) + { + /* Loop over the number rows present below */ + for (i = (l + 1U); i < numRows; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * l); + pOutT2 = pOutT1 + (numCols * k); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0) + { + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + } + + for (j = 0U; j < numCols; j++) + { + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + /* Update the destination pointer modifier */ + k++; + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* Pivot element of the row */ + in = *(pIn + (l * numCols)); + + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + *pInT1 = *pInT1 / in; + pInT1++; + } + for (j = 0U; j < numCols; j++) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + *pOutT1 = *pOutT1 / in; + pOutT1++; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + for (j = 0U; j < (numCols - l); j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pInT1 = *pInT1 - (in * *pPRT_in++); + pInT1++; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + for (j = 0U; j < numCols; j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pOutT1 = *pOutT1 - (in * *pPRT_pDst++); + pOutT1++; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixInv group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c new file mode 100644 index 0000000..ffddf99 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c @@ -0,0 +1,534 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_f32.c + * Description: Floating-point matrix multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixMult Matrix Multiplication + * + * Multiplies two matrices. + * + * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices" + + * Matrix multiplication is only defined if the number of columns of the + * first matrix equals the number of rows of the second matrix. + * Multiplying an M x N matrix with an N x P matrix results + * in an M x P matrix. + * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of + * pSrcA and pSrcB are equal; and (2) that the size of the output + * matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +#if defined(ARM_MATH_NEON) + +#define GROUPOFROWS 8 + +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + float32_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + + + float32_t in1, in2, in3, in4; + uint16_t col, i = 0U, j, row = numRowsA, rowCnt, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + + float32x4_t a0V, a1V, a2V, a3V, a4V, a5V, a6V, a7V; + float32x4_t acc0,acc1,acc2,acc3,acc4,acc5,acc6,acc7,temp; + float32x2_t accum = vdup_n_f32(0); + float32_t *pIn1B = pSrcA->pData; + float32_t *pIn1C = pSrcA->pData; + float32_t *pIn1D = pSrcA->pData; + float32_t *pIn1E = pSrcA->pData; + float32_t *pIn1F = pSrcA->pData; + float32_t *pIn1G = pSrcA->pData; + float32_t *pIn1H = pSrcA->pData; + + float32_t *pxB,*pxC, *pxD, *pxE, *pxF, *pxG, *pxH; /* Temporary output data matrix pointer */ + float32_t sum0,sum1, sum2,sum3, sum4, sum5 , sum6, sum7; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* Row loop */ + rowCnt = row >> 3; + + while(rowCnt > 0) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + GROUPOFROWS*i; + pxB = px + numColsB; + pxC = px + 2*numColsB; + pxD = px + 3*numColsB; + pxE = px + 4*numColsB; + pxF = px + 5*numColsB; + pxG = px + 6*numColsB; + pxH = px + 7*numColsB; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum0 = 0.0f; + sum1 = 0.0f; + sum2 = 0.0f; + sum3 = 0.0f; + sum4 = 0.0f; + sum5 = 0.0f; + sum6 = 0.0f; + sum7 = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + pIn1B = pIn1 + numColsA; + pIn1C = pIn1 + 2*numColsA; + pIn1D = pIn1 + 3*numColsA; + pIn1E = pIn1 + 4*numColsA; + pIn1F = pIn1 + 5*numColsA; + pIn1G = pIn1 + 6*numColsA; + pIn1H = pIn1 + 7*numColsA; + + acc0 = vdupq_n_f32(0.0); + acc1 = vdupq_n_f32(0.0); + acc2 = vdupq_n_f32(0.0); + acc3 = vdupq_n_f32(0.0); + acc4 = vdupq_n_f32(0.0); + acc5 = vdupq_n_f32(0.0); + acc6 = vdupq_n_f32(0.0); + acc7 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a0V = vld1q_f32(pIn1); + a1V = vld1q_f32(pIn1B); + a2V = vld1q_f32(pIn1C); + a3V = vld1q_f32(pIn1D); + a4V = vld1q_f32(pIn1E); + a5V = vld1q_f32(pIn1F); + a6V = vld1q_f32(pIn1G); + a7V = vld1q_f32(pIn1H); + + pIn1 += 4; + pIn1B += 4; + pIn1C += 4; + pIn1D += 4; + pIn1E += 4; + pIn1F += 4; + pIn1G += 4; + pIn1H += 4; + + temp[0] = *pIn2; + pIn2 += numColsB; + temp[1] = *pIn2; + pIn2 += numColsB; + temp[2] = *pIn2; + pIn2 += numColsB; + temp[3] = *pIn2; + pIn2 += numColsB; + + acc0 = vmlaq_f32(acc0,a0V,temp); + acc1 = vmlaq_f32(acc1,a1V,temp); + acc2 = vmlaq_f32(acc2,a2V,temp); + acc3 = vmlaq_f32(acc3,a3V,temp); + acc4 = vmlaq_f32(acc4,a4V,temp); + acc5 = vmlaq_f32(acc5,a5V,temp); + acc6 = vmlaq_f32(acc6,a6V,temp); + acc7 = vmlaq_f32(acc7,a7V,temp); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum0 += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(acc1), vget_high_f32(acc1)); + sum1 += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(acc2), vget_high_f32(acc2)); + sum2 += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(acc3), vget_high_f32(acc3)); + sum3 += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(acc4), vget_high_f32(acc4)); + sum4 += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(acc5), vget_high_f32(acc5)); + sum5 += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(acc6), vget_high_f32(acc6)); + sum6 += accum[0] + accum[1]; + + accum = vpadd_f32(vget_low_f32(acc7), vget_high_f32(acc7)); + sum7 += accum[0] + accum[1]; + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + sum0 += *pIn1++ * (*pIn2); + sum1 += *pIn1B++ * (*pIn2); + sum2 += *pIn1C++ * (*pIn2); + sum3 += *pIn1D++ * (*pIn2); + sum4 += *pIn1E++ * (*pIn2); + sum5 += *pIn1F++ * (*pIn2); + sum6 += *pIn1G++ * (*pIn2); + sum7 += *pIn1H++ * (*pIn2); + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Store the result in the destination buffer */ + *px++ = sum0; + *pxB++ = sum1; + *pxC++ = sum2; + *pxD++ = sum3; + *pxE++ = sum4; + *pxF++ = sum5; + *pxG++ = sum6; + *pxH++ = sum7; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + j; + + /* Decrement the column loop counter */ + col--; + + } while (col > 0U); + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + GROUPOFROWS*numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + } + + /* + + i was the index of a group of rows computed by previous loop. + Now i is the index of a row since below code is computing row per row + and no more group of row per group of rows. + + */ + + i = GROUPOFROWS*i; + rowCnt = row & 7; + + while(rowCnt > 0) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + + acc0 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a0V = vld1q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + pIn1 += 4; + + temp[0] = *pIn2; + pIn2 += numColsB; + temp[1] = *pIn2; + pIn2 += numColsB; + temp[2] = *pIn2; + pIn2 += numColsB; + temp[3] = *pIn2; + pIn2 += numColsB; + + acc0 = vmlaq_f32(acc0,a0V,temp); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum += accum[0] + accum[1]; + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + sum += *pIn1++ * (*pIn2); + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Store the result in the destination buffer */ + *px++ = sum; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + j; + + /* Decrement the column loop counter */ + col--; + + } while (col > 0U); + + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + float32_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + * @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c new file mode 100644 index 0000000..670ace1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c @@ -0,0 +1,483 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_fast_q15.c + * Description: Q15 matrix multiplication (fast variant) + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q15 matrix multiplication (fast variant). + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The difference between the function \ref arm_mat_mult_q15() and this fast variant is that + the fast variant use a 32-bit rather than a 64-bit accumulator. + The result of each 1.15 x 1.15 multiplication is truncated to + 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 + format. Finally, the accumulator is saturated and converted to a 1.15 result. + @par + The fast version has the same overflow behavior as the standard version but provides + less precision since it discards the low 16 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, + as a total of numColsA additions are computed internally for each output element. + @remark + Refer to \ref arm_mat_mult_q15() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. + */ + +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q31_t sum; /* Accumulator */ + q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix A */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#if defined (ARM_MATH_DSP) + q31_t in; /* Temporary variable to hold the input value */ + q31_t inA1, inB1, inA2, inB2; + q31_t sum2, sum3, sum4; + q15_t *pInA2, *pInB2, *px2; + uint32_t j = 0; +#else + q15_t in; /* Temporary variable to hold the input value */ + q15_t inA1, inB1, inA2, inB2; +#endif /* #if defined (ARM_MATH_DSP) */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + + /* Apply loop unrolling and exchange columns with row elements */ + col = numColsB >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + +#if defined (ARM_MATH_DSP) + + /* Read two elements from row */ + in = read_q15x2_ia ((q15_t **) &pInB); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) in; +#else + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *px = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + in = read_q15x2_ia ((q15_t **) &pInB); +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) in; +#else + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + px += numRowsB; + +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *px = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + px += numRowsB; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Read one element from row */ + in = *pInB++; + + /* Store one element in destination */ + *px = in; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pInB++; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + +#if defined (ARM_MATH_DSP) + /* Process two rows from matrix A at a time and output two rows at a time */ + row = row >> 1U; + px2 = px + numColsB; +#endif + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + +#if defined (ARM_MATH_DSP) + /* Process two (transposed) columns from matrix B at a time */ + col = col >> 1U; + j = 0; +#endif + + /* column loop */ + while (col > 0U) + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + +#if defined (ARM_MATH_DSP) + sum2 = 0; + sum3 = 0; + sum4 = 0; + pInB = pSrcBT + j; + pInA2 = pInA + numColsA; + pInB2 = pInB + numRowsB; + + /* Read in two elements at once - alows dual MAC instruction */ + colCnt = numColsA >> 1U; +#else + colCnt = numColsA >> 2U; +#endif + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = read_q15x2_ia ((q15_t **) &pInA); + inB1 = read_q15x2_ia ((q15_t **) &pInB); + + inA2 = read_q15x2_ia ((q15_t **) &pInA2); + inB2 = read_q15x2_ia ((q15_t **) &pInB2); + + /* Multiply and Accumlates */ + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); +#else + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = *pInA++; + inB1 = *pInB++; + /* Multiply and Accumlates */ + sum += inA1 * inB1; + + inA2 = *pInA++; + inB2 = *pInB++; + sum += inA2 * inB2; + + inA1 = *pInA++; + inB1 = *pInB++; + sum += inA1 * inB1; + + inA2 = *pInA++; + inB2 = *pInB++; + sum += inA2 * inB2; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process odd column samples */ +#if defined (ARM_MATH_DSP) + if (numColsA & 1U) { + inA1 = *pInA++; + inB1 = *pInB++; + inA2 = *pInA2++; + inB2 = *pInB2++; + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + } +#else + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + sum += (q31_t) *pInA++ * *pInB++; + + /* Decrement loop counter */ + colCnt--; + } +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + +#if defined (ARM_MATH_DSP) + *px++ = (q15_t) (sum2 >> 15); + *px2++ = (q15_t) (sum3 >> 15); + *px2++ = (q15_t) (sum4 >> 15); + j += numRowsB * 2; +#endif + + /* Decrement column loop counter */ + col--; + + } + + i = i + numColsA; + +#if defined (ARM_MATH_DSP) + i = i + numColsA; + px = px2 + (numColsB & 1U); + px2 = px + numColsB; +#endif + + /* Decrement row loop counter */ + row--; + + } + + /* Compute any remaining odd row/column below */ + +#if defined (ARM_MATH_DSP) + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~0x1); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcBT + numRowsB * (numColsB-1); + + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Compute 4 columns at once */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = read_q15x2_ia ((q15_t **) &pInA); + inA2 = read_q15x2_ia ((q15_t **) &pInA); + inB1 = read_q15x2_ia ((q15_t **) &pInB); + inB2 = read_q15x2_ia ((q15_t **) &pInB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + colCnt = numColsA & 3U; + while (colCnt > 0U) { + sum += (q31_t) (*pInA++) * (*pInB++); + colCnt--; + } + + /* Store result in destination buffer */ + *px = (q15_t) (sum >> 15); + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + pInB = pSrcBT; + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; + + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Compute 4 columns at once */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = read_q15x2_ia ((q15_t **) &pInA); + inA2 = read_q15x2_ia ((q15_t **) &pInA); + inB1 = read_q15x2_ia ((q15_t **) &pInB); + inB2 = read_q15x2_ia ((q15_t **) &pInB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + colCnt = numColsA % 4U; + while (colCnt > 0U) { + sum += (q31_t) (*pInA++) * (*pInB++); + + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + + /* Decrement column loop counter */ + col--; + } + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c new file mode 100644 index 0000000..011959a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c @@ -0,0 +1,374 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_fast_q31.c + * Description: Q31 matrix multiplication (fast variant) + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication (fast variant). + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The difference between the function \ref arm_mat_mult_q31() and this fast variant is that + the fast variant use a 32-bit rather than a 64-bit accumulator. + The result of each 1.31 x 1.31 multiplication is truncated to + 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 + format. Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides + less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, + as a total of numColsA additions are computed internally for each output element. + @remark + Refer to \ref arm_mat_mult_q31() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. + */ + +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA2; + q31_t *px; /* Temporary output data matrix pointer */ + q31_t *px2; + q31_t sum1, sum2, sum3, sum4; /* Accumulator */ + q31_t inA1, inA2, inB1, inB2; + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + px = pDst->pData; + + row = row >> 1U; + px2 = px + numColsB; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pInB = pSrcB->pData; + + j = 0U; + + col = col >> 1U; + + /* column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum1 = 0; + sum2 = 0; + sum3 = 0; + sum4 = 0; + + /* Initiate data pointers */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + pInA2 = pInA + numColsA; + + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + inA1 = *pInA++; + inB1 = pInB[0]; + inA2 = *pInA2++; + inB2 = pInB[1]; + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum2 = __SMMLA(inA1, inB2, sum2); + sum3 = __SMMLA(inA2, inB1, sum3); + sum4 = __SMMLA(inA2, inB2, sum4); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum2 = (q31_t) ((((q63_t) sum2 << 32) + ((q63_t) inA1 * inB2)) >> 32); + sum3 = (q31_t) ((((q63_t) sum3 << 32) + ((q63_t) inA2 * inB1)) >> 32); + sum4 = (q31_t) ((((q63_t) sum4 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px++ = sum1 << 1; + *px++ = sum2 << 1; + *px2++ = sum3 << 1; + *px2++ = sum4 << 1; + + j += 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + (numColsA << 1U); + px = px2 + (numColsB & 1U); + px2 = px + numColsB; + + /* Decrement row loop counter */ + row--; + } + + /* Compute any remaining odd row/column below */ + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~1U); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcB->pData + numColsB-1; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 columns at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining column */ + colCnt = numColsA % 4U; + +#else + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + colCnt--; + } + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px = sum1 << 1; + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; + pInB = pSrcB->pData + i; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 columns at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = *pInA++; + inA2 = *pInA++; + inB1 = *pInB; + pInB += numColsB; + inB2 = *pInB; + pInB += numColsB; +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum1 = __SMMLA(inA2, inB2, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + inA1 = *pInA++; + inA2 = *pInA++; + inB1 = *pInB; + pInB += numColsB; + inB2 = *pInB; + pInB += numColsB; +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum1 = __SMMLA(inA2, inB2, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining column */ + colCnt = numColsA % 4U; + +#else + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1 << 1; + i++; + + /* Decrement col loop counter */ + col--; + } + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c new file mode 100644 index 0000000..1d2b69c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c @@ -0,0 +1,357 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q15.c + * Description: Q15 matrix multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q15 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results (Unused) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. The inputs to the + multiplications are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits + and then saturated to 1.15 format. + @par + Refer to \ref arm_mat_mult_fast_q15() for a faster but less precise version of this function. + */ + +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q63_t sum; /* Accumulator */ + +#if defined (ARM_MATH_DSP) /* != CM0 */ + + q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix A */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + + q31_t in; /* Temporary variable to hold the input value */ + q31_t inA1, inB1, inA2, inB2; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + + /* Apply loop unrolling and exchange columns with row elements */ + col = numColsB >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + /* Read two elements from row */ + in = read_q15x2_ia ((q15_t **) &pInB); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) in; +#else + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *px = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Read two elements from row */ + in = read_q15x2_ia ((q15_t **) &pInB); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) in; +#else + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + px += numRowsB; + +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *px = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + px += numRowsB; + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pInB++; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + do + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + + /* Apply loop unrolling and compute 2 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = read_q15x2_ia ((q15_t **) &pInA); + inB1 = read_q15x2_ia ((q15_t **) &pInB); + + inA2 = read_q15x2_ia ((q15_t **) &pInA); + inB2 = read_q15x2_ia ((q15_t **) &pInB); + + /* Multiply and Accumlates */ + sum = __SMLALD(inA1, inB1, sum); + sum = __SMLALD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + /* process remaining column samples */ + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + sum += *pInA++ * *pInB++; + + /* Decrement loop counter */ + colCnt--; + } + + /* Saturate and store result in destination buffer */ + *px = (q15_t) (__SSAT((sum >> 15), 16)); + px++; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + +#else /* #if defined (ARM_MATH_DSP) */ + + q15_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q15_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pIn1 to point to starting address of pSrcA */ + pIn1 = pInA; + + /* Matrix A columns number of MAC operations are to be performed */ + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform multiply-accumulates */ + sum += (q31_t) * pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 34.30 to 1.15 format and store saturated value in destination buffer */ + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) __SSAT((sum >> 15), 16); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pSrcA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c new file mode 100644 index 0000000..161e723 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q31.c + * Description: Q31 matrix multiplication + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + @remark + Refer to \ref arm_mat_mult_fast_q31() for a faster but less precise implementation of this function. + */ + +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + q63_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 2.62 to 1.31 format and store in destination buffer */ + *px++ = (q31_t) (sum >> 31); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c new file mode 100644 index 0000000..a0097b1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_f32.c + * Description: Multiplies a floating-point matrix by a scalar + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixScale Matrix Scale + + Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the + matrix by the scalar. For example: + \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix" + + The function checks to make sure that the input and output matrices are of the same size. + + In the fixed-point Q15 and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The overall scale factor applied to the fixed-point data is + 
+      scale = scaleFract * 2^shift.
+
+ */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Floating-point matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scale scale factor to be applied + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix scaling */ + + + float32_t in1, in2, in3, in4; /* temporary variables */ + float32_t out1, out2, out3, out4; /* temporary variables */ + + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32x4_t vec1; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + + blkCnt = numSamples >> 2; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + /* Scaling and results are stored in the destination buffer. */ + vec1 = vld1q_f32(pIn); + res = vmulq_f32(vec1, vdupq_n_f32(scale)); + vst1q_f32(pOut, res); + + /* update pointers to process next sampels */ + pIn += 4U; + pOut += 4U; + + /* Decrement the numSamples loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + /* The results are stored in the destination buffer. */ + *pOut++ = (*pIn++) * scale; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* Input data matrix pointer */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counters */ + arm_status status; /* Status of matrix scaling */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of MatrixScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c new file mode 100644 index 0000000..9b75d4e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_q15.c + * Description: Multiplies a Q15 matrix by a scalar + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Q15 matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.15 format. + These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ + +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pIn = pSrc->pData; /* Input data matrix pointer */ + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counter */ + arm_status status; /* Status of matrix scaling */ + int32_t kShift = 15 - shift; /* Total shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t out1, out2, out3, out4; /* Temporary output variables */ + q15_t in1, in2, in3, in4; /* Temporary input variables */ +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from source */ + inA1 = read_q15x2_ia ((q15_t **) &pIn); + inA2 = read_q15x2_ia ((q15_t **) &pIn); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pOut, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pOut, __PKHBT(in4, in3, 16)); + +#else + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c new file mode 100644 index 0000000..929b17f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c @@ -0,0 +1,164 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_q31.c + * Description: Multiplies a Q31 matrix by a scalar + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Q31 matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.31 format. + These are multiplied to yield a 2.62 intermediate result which is shifted with saturation to 1.31 format. + */ + +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* Input data matrix pointer */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counter */ + arm_status status; /* Status of matrix scaling */ + int32_t kShift = shift + 1; /* Shift to apply after scaling */ + q31_t in, out; /* Temporary variabels */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + in = *pIn++; /* read four inputs from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in << kShift; /* apply shifting */ + if (in != (out >> kShift)) /* saturate the results. */ + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; /* Store result destination */ + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c new file mode 100644 index 0000000..cb57647 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c @@ -0,0 +1,226 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_f32.c + * Description: Floating-point matrix subtraction + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixSub Matrix Subtraction + + Subtract two matrices. + \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_NEON) +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + + float32_t inA1, inA2, inB1, inB2, out1, out2; /* temporary variables */ + + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + blkCnt = numSamples >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + /* Subtract and then store the results in the destination buffer. */ + /* Read values from source A */ + vec1 = vld1q_f32(pIn1); + vec2 = vld1q_f32(pIn2); + res = vsubq_f32(vec1, vec2); + vst1q_f32(pOut, res); + + /* Update pointers to process next samples */ + pIn1 += 4U; + pIn2 += 4U; + pOut += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + /* Subtract and then store the results in the destination buffer. */ + *pOut++ = (*pIn1++) - (*pIn2++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +/** + @} end of MatrixSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c new file mode 100644 index 0000000..5d5e5d0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_q15.c + * Description: Q15 Matrix subtraction + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Q15 matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, Saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + write_q15x2_ia (&pOut, __QSUB16(read_q15x2_ia ((q15_t **) &pInA), read_q15x2_ia ((q15_t **) &pInB))); + write_q15x2_ia (&pOut, __QSUB16(read_q15x2_ia ((q15_t **) &pInA), read_q15x2_ia ((q15_t **) &pInB))); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c new file mode 100644 index 0000000..40d1bef --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_q31.c + * Description: Q31 matrix subtraction + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Q31 matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, saturate and then store the results in the destination buffer. */ + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, saturate and store result in destination buffer. */ + *pOut++ = __QSUB(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c new file mode 100644 index 0000000..71748bf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c @@ -0,0 +1,284 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_f32.c + * Description: Floating-point matrix transpose + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixTrans Matrix Transpose + + Tranposes a matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix" + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_NEON) + +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + + uint16_t blkCnt, rowCnt, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* Row loop */ + rowCnt = row >> 2; + while (rowCnt > 0U) + { + float32x4_t row0V,row1V,row2V,row3V; + float32x4x2_t ra0,ra1,rb0,rb1; + + blkCnt = nColumns >> 2; + + /* The pointer px is set to starting address of the column being processed */ + px = pOut + i; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) /* Column loop */ + { + row0V = vld1q_f32(pIn); + row1V = vld1q_f32(pIn + 1 * nColumns); + row2V = vld1q_f32(pIn + 2 * nColumns); + row3V = vld1q_f32(pIn + 3 * nColumns); + pIn += 4; + + ra0 = vzipq_f32(row0V,row2V); + ra1 = vzipq_f32(row1V,row3V); + + rb0 = vzipq_f32(ra0.val[0],ra1.val[0]); + rb1 = vzipq_f32(ra0.val[1],ra1.val[1]); + + vst1q_f32(px,rb0.val[0]); + px += nRows; + + vst1q_f32(px,rb0.val[1]); + px += nRows; + + vst1q_f32(px,rb1.val[0]); + px += nRows; + + vst1q_f32(px,rb1.val[1]); + px += nRows; + + /* Decrement the column loop counter */ + blkCnt--; + } + + /* Perform matrix transpose for last 3 samples here. */ + blkCnt = nColumns % 0x4U; + + while (blkCnt > 0U) + { + /* Read and store the input element in the destination */ + *px++ = *pIn; + *px++ = *(pIn + 1 * nColumns); + *px++ = *(pIn + 2 * nColumns); + *px++ = *(pIn + 3 * nColumns); + + px += (nRows - 4); + pIn++; + + /* Decrement the column loop counter */ + blkCnt--; + } + + i += 4; + pIn += 3 * nColumns; + + /* Decrement the row loop counter */ + rowCnt--; + + } /* Row loop end */ + + rowCnt = row & 3; + while (rowCnt > 0U) + { + blkCnt = nColumns ; + /* The pointer px is set to starting address of the column being processed */ + px = pOut + i; + + while (blkCnt > 0U) + { + /* Read and store the input element in the destination */ + *px = *pIn++; + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += nRows; + + /* Decrement the column loop counter */ + blkCnt--; + } + i++; + rowCnt -- ; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + * @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c new file mode 100644 index 0000000..707e0d6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q15.c + * Description: Q15 matrix transpose + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q15 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pIn = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; /* variable to hold temporary output */ +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer pOut is set to starting address of column being processed */ + pOut = pDst->pData + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read two elements from row */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) in; +#else + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *pOut = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Read two elements from row */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) in; +#else + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *pOut = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *pOut = *pIn++; + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c new file mode 100644 index 0000000..5d0b5e2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q31.c + * Description: Q31 matrix transpose + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q31 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt new file mode 100644 index 0000000..3f23355 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt @@ -0,0 +1,16 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSPStatistics) + + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPStatistics STATIC ${SRC}) + +configdsp(CMSISDSPStatistics ..) + +### Includes +target_include_directories(CMSISDSPStatistics PUBLIC "${DSP}/../../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c new file mode 100644 index 0000000..4f86aa4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: StatisticsFunctions.c + * Description: Combination of all statistics function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_max_f32.c" +#include "arm_max_q15.c" +#include "arm_max_q31.c" +#include "arm_max_q7.c" +#include "arm_mean_f32.c" +#include "arm_mean_q15.c" +#include "arm_mean_q31.c" +#include "arm_mean_q7.c" +#include "arm_min_f32.c" +#include "arm_min_q15.c" +#include "arm_min_q31.c" +#include "arm_min_q7.c" +#include "arm_power_f32.c" +#include "arm_power_q15.c" +#include "arm_power_q31.c" +#include "arm_power_q7.c" +#include "arm_rms_f32.c" +#include "arm_rms_q15.c" +#include "arm_rms_q31.c" +#include "arm_std_f32.c" +#include "arm_std_q15.c" +#include "arm_std_q31.c" +#include "arm_var_f32.c" +#include "arm_var_q15.c" +#include "arm_var_q31.c" diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c new file mode 100644 index 0000000..cd54e2a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c @@ -0,0 +1,271 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_f32.c + * Description: Maximum value of a floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#if defined(ARM_MATH_NEON) +#include +#endif + +/** + @ingroup groupStats + */ + +/** + @defgroup Max Maximum + + Computes the maximum value of an array of data. + The function returns both the maximum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_NEON) +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex, count; /* loop counter */ + + float32x4_t outV, srcV; + float32x2_t outV2; + + uint32x4_t idxV; + uint32x4_t maxIdx={ULONG_MAX,ULONG_MAX,ULONG_MAX,ULONG_MAX}; + uint32x4_t index={4,5,6,7}; + uint32x4_t delta={4,4,4,4}; + uint32x4_t countV={0,1,2,3}; + uint32x2_t countV2; + + /* Initialise the count value. */ + count = 0U; + + /* Initialise the index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparison */ + if (blockSize <= 3) + { + out = *pSrc++; + + blkCnt = blockSize - 1; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + outV = vld1q_f32(pSrc); + pSrc += 4; + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize - 4 ) >> 2U; + + while (blkCnt > 0U) + { + srcV = vld1q_f32(pSrc); + pSrc += 4; + + idxV = vcgtq_f32(srcV, outV); + outV = vbslq_f32(idxV, srcV, outV ); + countV = vbslq_u32(idxV, index,countV ); + + index = vaddq_u32(index,delta); + + /* Decrement the loop counter */ + blkCnt--; + } + + outV2 = vpmax_f32(vget_low_f32(outV),vget_high_f32(outV)); + outV2 = vpmax_f32(outV2,outV2); + out = outV2[0]; + + idxV = vceqq_f32(outV, vdupq_n_f32(out)); + countV = vbslq_u32(idxV, countV,maxIdx); + + countV2 = vpmin_u32(vget_low_u32(countV),vget_high_u32(countV)); + countV2 = vpmin_u32(countV2,countV2); + outIndex = countV2[0]; + + /* if (blockSize - 1U) is not multiple of 4 */ + blkCnt = (blockSize - 4 ) % 4U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt ; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#else +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* #if defined(ARM_MATH_NEON) */ +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c new file mode 100644 index 0000000..329b0c8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q15.c + * Description: Maximum value of a Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c new file mode 100644 index 0000000..99de13e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q31.c + * Description: Maximum value of a Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c new file mode 100644 index 0000000..9c8b6d3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q7.c + * Description: Maximum value of a Q7 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c new file mode 100644 index 0000000..63d9652 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c @@ -0,0 +1,166 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_f32.c + * Description: Mean value of a floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup mean Mean + + Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector. + The underlying algorithm is used: + + 
+      Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
+
+ + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* Temporary result storage */ + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + + uint32_t blkCnt; /* Loop counter */ + + float32_t in1, in2, in3, in4; + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + inV = vld1q_f32(pSrc); + sumV = vaddq_f32(sumV, inV); + + pSrc += 4; + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = sumV2[0] + sumV2[1]; + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store the result to the destination */ + *pResult = sum / (float32_t) blockSize; +} +#else +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (sum / blockSize); +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of mean group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c new file mode 100644 index 0000000..463aa84 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q15.c + * Description: Mean value of a Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.15 format and is accumulated in a 32-bit + accumulator in 17.15 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.15 format. + */ + +void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in = read_q15x2_ia ((q15_t **) &pSrc); + sum += ((in << 16U) >> 16U); + sum += (in >> 16U); + + in = read_q15x2_ia ((q15_t **) &pSrc); + sum += ((in << 16U) >> 16U); + sum += (in >> 16U); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q15_t) (sum / (int32_t) blockSize); +} + +/** + @} end of mean group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c new file mode 100644 index 0000000..4b0ed6e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q31.c + * Description: Mean value of a Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.31 format and is accumulated in a 64-bit + accumulator in 33.31 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.31 format. + */ + +void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q31_t) (sum / blockSize); +} + +/** + @} end of mean group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c new file mode 100644 index 0000000..8f52211 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c @@ -0,0 +1,112 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q7.c + * Description: Mean value of a Q7 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.7 format and is accumulated in a 32-bit + accumulator in 25.7 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.7 format. + */ + +void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in = read_q7x4_ia ((q7_t **) &pSrc); + sum += ((in << 24U) >> 24U); + sum += ((in << 16U) >> 24U); + sum += ((in << 8U) >> 24U); + sum += (in >> 24U); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q7_t) (sum / (int32_t) blockSize); +} + +/** + @} end of mean group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c new file mode 100644 index 0000000..6e9ff4b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c @@ -0,0 +1,268 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_f32.c + * Description: Minimum value of a floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup Min Minimum + + Computes the minimum value of an array of data. + The function returns both the minimum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_NEON) +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex, count; /* loop counter */ + + float32x4_t outV, srcV; + float32x2_t outV2; + + uint32x4_t idxV; + uint32x4_t maxIdx={ULONG_MAX,ULONG_MAX,ULONG_MAX,ULONG_MAX}; + uint32x4_t index={4,5,6,7}; + uint32x4_t delta={4,4,4,4}; + uint32x4_t countV={0,1,2,3}; + uint32x2_t countV2; + + /* Initialise the count value. */ + count = 0U; + + /* Initialise the index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparison */ + if (blockSize <= 3) + { + out = *pSrc++; + + blkCnt = blockSize - 1; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out > maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + outV = vld1q_f32(pSrc); + pSrc += 4; + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize - 4 ) >> 2U; + + while (blkCnt > 0U) + { + srcV = vld1q_f32(pSrc); + pSrc += 4; + + idxV = vcltq_f32(srcV, outV); + outV = vbslq_f32(idxV, srcV, outV ); + countV = vbslq_u32(idxV, index,countV ); + + index = vaddq_u32(index,delta); + + /* Decrement the loop counter */ + blkCnt--; + } + + outV2 = vpmin_f32(vget_low_f32(outV),vget_high_f32(outV)); + outV2 = vpmin_f32(outV2,outV2); + out = outV2[0]; + + idxV = vceqq_f32(outV, vdupq_n_f32(out)); + countV = vbslq_u32(idxV, countV,maxIdx); + + countV2 = vpmin_u32(vget_low_u32(countV),vget_high_u32(countV)); + countV2 = vpmin_u32(countV2,countV2); + outIndex = countV2[0]; + + /* if (blockSize - 1U) is not multiple of 4 */ + blkCnt = (blockSize - 4 ) % 4U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out > maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt ; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#else +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c new file mode 100644 index 0000000..9450383 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q15.c + * Description: Minimum value of a Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c new file mode 100644 index 0000000..e25eb47 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q31.c + * Description: Minimum value of a Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c new file mode 100644 index 0000000..2b171f0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q7.c + * Description: Minimum value of a Q7 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c new file mode 100644 index 0000000..a4825a5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c @@ -0,0 +1,175 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_f32.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup power Power + + Calculates the sum of the squares of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +#if defined(ARM_MATH_NEON) +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = sumV2[0] + sumV2[1]; + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the result to the destination */ + *pResult = sum; +} +#else +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of power group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c new file mode 100644 index 0000000..12f524d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q15.c + * Description: Sum of the squares of the elements of a Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 34.30 format. + */ + +void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store packed input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sum = __SMLALD(in32, in32, sum); + + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sum = __SMLALD(in32, in32, sum); +#else + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in 34.30 format */ + *pResult = sum; +} + +/** + @} end of power group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c new file mode 100644 index 0000000..1e193b3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q31.c + * Description: Sum of the squares of the elements of a Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.31 format. + Intermediate multiplication yields a 2.62 format, and this + result is truncated to 2.48 format by discarding the lower 14 bits. + The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + With 15 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 16.48 format. + */ + +void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q31_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and store result in a temporary variable sum, providing 15 guard bits. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store results in 16.48 format */ + *pResult = sum; +} + +/** + @} end of power group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c new file mode 100644 index 0000000..47405cd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q7.c + * Description: Sum of the squares of the elements of a Q7 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.7 format. + Intermediate multiplication yields a 2.14 format, and this + result is added without saturation to an accumulator in 18.14 format. + With 17 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 18.14 format. + */ + +void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + q7_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store packed input value */ + q31_t in1, in2; /* Temporary variables to store input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q7x4_ia ((q7_t **) &pSrc); + + in1 = __SXTB16(__ROR(in32, 8)); + in2 = __SXTB16(in32); + + /* calculate power and accumulate to accumulator */ + sum = __SMLAD(in1, in1, sum); + sum = __SMLAD(in2, in2, sum); +#else + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q15_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in 18.14 format */ + *pResult = sum; +} + +/** + @} end of power group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c new file mode 100644 index 0000000..4546510 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c @@ -0,0 +1,176 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_f32.c + * Description: Root mean square value of the elements of a floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup RMS Root mean square (RMS) + + Calculates the Root Mean Square of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + */ +#if defined(ARM_MATH_NEON) +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = sumV2[0] + sumV2[1]; + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Compute Rms and store the result in the destination */ + arm_sqrt_f32(sum / (float32_t) blockSize, pResult); +} +#else +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ( in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Rms and store result in destination */ + arm_sqrt_f32(sum / (float32_t) blockSize, pResult); +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of RMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c new file mode 100644 index 0000000..9fcd964 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_q15.c + * Description: Root Mean Square of the elements of a Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ + +void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sum = __SMLALD(in32, in32, sum); + + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sum = __SMLALD(in32, in32, sum); +#else + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Truncating and saturating the accumulator to 1.15 format */ + /* Store result in destination */ + arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult); +} + +/** + @} end of RMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c new file mode 100644 index 0000000..5a3e8f3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_q31.c + * Description: Root Mean Square of the elements of a Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, and intermediate multiplication + yields a 2.62 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a single guard bit. + There is no saturation on intermediate additions. + If the accumulator overflows, it wraps around and distorts the result. + In order to avoid overflows completely, the input signal must be scaled down by + log2(blockSize) bits, as a total of blockSize additions are performed internally. + Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. + */ + +void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + uint64_t sum = 0; /* Temporary result storage (can get never negative. changed type from q63 to uint64 */ + q31_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ((q63_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */ + /* Compute Rms and store result in destination vector */ + arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult); +} + +/** + @} end of RMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c new file mode 100644 index 0000000..e1e6577 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_f32.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup STD Standard deviation + + Calculates the standard deviation of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
+
+      sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+      sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t var; + arm_var_f32(pSrc,blockSize,&var); + arm_sqrt_f32(var, pResult); +} +#else +void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t sumOfSquares = 0.0f; /* Sum of squares */ + float32_t in; /* Temporary variable to store input value */ + +#ifndef ARM_MATH_CM0_FAMILY + float32_t meanOfSquares, mean, squareOfMean; /* Temporary variables */ +#else + float32_t squareOfSum; /* Square of Sum */ + float32_t var; /* Temporary varaince storage */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += in * in; + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++; + sumOfSquares += in * in; + sum += in; + + in = *pSrc++; + sumOfSquares += in * in; + sum += in; + + in = *pSrc++; + sumOfSquares += in * in; + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ( in * in); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + +#ifndef ARM_MATH_CM0_FAMILY + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f); + + /* Compute mean of all input values */ + mean = sum / (float32_t) blockSize; + + /* Compute square of mean */ + squareOfMean = (mean * mean) * (((float32_t) blockSize) / + ((float32_t) blockSize - 1.0f)); + + /* Compute standard deviation and store result to destination */ + arm_sqrt_f32((meanOfSquares - squareOfMean), pResult); + +#else + /* Run the below code for Cortex-M0 */ + + /* Compute square of sum */ + squareOfSum = ((sum * sum) / (float32_t) blockSize); + + /* Compute variance */ + var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f)); + + /* Compute standard deviation and store result in destination */ + arm_sqrt_f32(var, pResult); + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of STD group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c new file mode 100644 index 0000000..8e5c042 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_q15.c + * Description: Standard deviation of an array of Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ + +void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + /* Compute sum and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); + + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); +#else + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += (in * in); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + /* Compute standard deviation and store result in destination */ + arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15U, 16U), pResult); +} + +/** + @} end of STD group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c new file mode 100644 index 0000000..cfb6cb8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_q31.c + * Description: Standard deviation of the elements of a Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a Q31 vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult standard deviation value returned here. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, which is then downshifted by 8 bits + which yields 1.23, and intermediate multiplication yields a 2.46 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a 16 guard bits. + There is no saturation on intermediate additions. + If the accumulator overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by + log2(blockSize)-8 bits, as a total of blockSize additions are performed internally. + After division, internal variables should be Q18.46 + Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. + */ + +void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Accumulator */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q31_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute standard deviation and store result in destination */ + arm_sqrt_q31((meanOfSquares - squareOfMean) >> 15U, pResult); +} + +/** + @} end of STD group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c new file mode 100644 index 0000000..3c325b1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_f32.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup variance Variance + + Calculates the variance of the elements in the input vector. + The underlying algorithm used is the direct method sometimes referred to as the two-pass method: + + 
+      Result = sum(element - meanOfElements)^2) / numElement - 1
+
+      meanOfElements = ( pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] ) / blockSize
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t mean; + + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + float32x4_t avg; + + arm_mean_f32(pSrc,blockSize,&mean); + avg = vdupq_n_f32(mean); + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + inV = vsubq_f32(inV, avg); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = sumV2[0] + sumV2[1]; + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + in = in - mean; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = sum / (float32_t)(blockSize - 1.0f); + +} + +#else +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t fSum = 0.0f; + float32_t fMean, fValue; + const float32_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = sum / (float32_t) blockSize; + + pInput = pSrc; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = fSum / (float32_t)(blockSize - 1.0f); +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of variance group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c new file mode 100644 index 0000000..259e76b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c @@ -0,0 +1,164 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_q15.c + * Description: Variance of an array of Q15 type + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ + +void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + /* Compute sum and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); + + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); +#else + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ +#if defined (ARM_MATH_DSP) + sumOfSquares = __SMLALD(in, in, sumOfSquares); +#else + sumOfSquares += (in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +} + +/** + @} end of variance group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c new file mode 100644 index 0000000..558332f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_q31.c + * Description: Variance of an array of Q31 type + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, which is then downshifted by 8 bits + which yields 1.23, and intermediate multiplication yields a 2.46 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a 16 guard bits. + There is no saturation on intermediate additions. + If the accumulator overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by + log2(blockSize)-8 bits, as a total of blockSize additions are performed internally. + After division, internal variables should be Q18.46 + Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. + */ + +void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q31_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute variance and store result in destination */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +} + +/** + @} end of variance group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt new file mode 100644 index 0000000..33c4f87 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt @@ -0,0 +1,16 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSPSupport) + + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPSupport STATIC ${SRC}) + +configdsp(CMSISDSPSupport ..) + +### Includes +target_include_directories(CMSISDSPSupport PUBLIC "${DSP}/../../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c new file mode 100644 index 0000000..4deb19b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: SupportFunctions.c + * Description: Combination of all support function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_copy_f32.c" +#include "arm_copy_q15.c" +#include "arm_copy_q31.c" +#include "arm_copy_q7.c" +#include "arm_fill_f32.c" +#include "arm_fill_q15.c" +#include "arm_fill_q31.c" +#include "arm_fill_q7.c" +#include "arm_float_to_q15.c" +#include "arm_float_to_q31.c" +#include "arm_float_to_q7.c" +#include "arm_q15_to_float.c" +#include "arm_q15_to_q31.c" +#include "arm_q15_to_q7.c" +#include "arm_q31_to_float.c" +#include "arm_q31_to_q15.c" +#include "arm_q31_to_q7.c" +#include "arm_q7_to_float.c" +#include "arm_q7_to_q15.c" +#include "arm_q7_to_q31.c" diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c new file mode 100644 index 0000000..707adc4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_f32.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @defgroup copy Vector Copy + + Copies sample by sample from source vector to destination vector. + + 
+      pDst[n] = pSrc[n];   0 <= n < blockSize.
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a floating-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A */ + /* Copy and then store the results in the destination buffer */ + inV = vld1q_f32(pSrc); + vst1q_f32(pDst, inV); + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = A */ + /* Copy and then store the results in the destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* #if defined(ARM_MATH_NEON) */ +/** + @} end of BasicCopy group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c new file mode 100644 index 0000000..d8da113 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q15.c + * Description: Copies the elements of a Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q15 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* read 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, read_q15x2_ia ((q15_t **) &pSrc)); + write_q15x2_ia (&pDst, read_q15x2_ia ((q15_t **) &pSrc)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of BasicCopy group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c new file mode 100644 index 0000000..e342a32 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q31.c + * Description: Copies the elements of a Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q31 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of BasicCopy group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c new file mode 100644 index 0000000..77da8ca --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c @@ -0,0 +1,95 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q7.c + * Description: Copies the elements of a Q7 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q7 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* read 4 samples at a time */ + write_q7x4_ia (&pDst, read_q7x4_ia ((q7_t **) &pSrc)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of BasicCopy group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c new file mode 100644 index 0000000..29f6286 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_f32.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @defgroup Fill Vector Fill + + Fills the destination vector with a constant value. + + 
+      pDst[n] = value;   0 <= n < blockSize.
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a floating-point vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + + float32x4_t inV = vdupq_n_f32(value); + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = value */ + /* Fill the value in the destination buffer */ + vst1q_f32(pDst, inV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = value */ + /* Fill the value in the destination buffer */ + *pDst++ = value; + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* #if defined(ARM_MATH_NEON) */ +/** + @} end of Fill group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c new file mode 100644 index 0000000..d8c0f8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q15.c + * Description: Fills a constant value into a Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q15 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t packedValue; /* value packed to 32 bits */ + + /* Packing two 16 bit values to 32 bit value in order to use SIMD */ + packedValue = __PKHBT(value, value, 16U); + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* fill 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, packedValue); + write_q15x2_ia (&pDst, packedValue); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of Fill group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c new file mode 100644 index 0000000..e174889 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q31.c + * Description: Fills a constant value into a Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q31 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of Fill group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c new file mode 100644 index 0000000..bca3267 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c @@ -0,0 +1,99 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q7.c + * Description: Fills a constant value into a Q7 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q7 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t packedValue; /* value packed to 32 bits */ + + /* Packing four 8 bit values to 32 bit value in order to use SIMD */ + packedValue = __PACKq7(value, value, value, value); + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* fill 4 samples at a time */ + write_q7x4_ia (&pDst, packedValue); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of Fill group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c new file mode 100644 index 0000000..68c1ad0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c @@ -0,0 +1,244 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to Q15 vector. + @param[in] pSrc points to the floating-point input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + + @note + In order to apply rounding, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32_t in; + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 32768.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 32768.0f); + float32x4_t r; + uint32x4_t cmp; + #endif + + int32x4_t cvt; + int16x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + + pIn += 4; + + cvt = vcvtq_n_s32_f32(inV,15); + outV = vqmovn_s32(cvt); + + vst1_s16(pDst, outV); + pDst += 4; + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + + cvt = vcvtq_n_s32_f32(inV,15); + outV = vqmovn_s32(cvt); + + vst1_s16(pDst, outV); + pDst += 4; + pIn += 4; + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of float_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c new file mode 100644 index 0000000..479f8c5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c @@ -0,0 +1,252 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q31.c + * Description: Converts the elements of the floating-point vector to Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup float_to_x Convert 32-bit floating point value + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to Q31 vector. + @param[in] pSrc points to the floating-point input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + + @note + In order to apply rounding, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_NEON) +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32_t in; + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 2147483648.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 2147483648.0f); + float32x4_t r; + uint32x4_t cmp; + #endif + + int32x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* C = A * 32768 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + + pIn += 4; + + outV = vcvtq_n_s32_f32(inV,31); + + vst1q_s32(pDst, outV); + pDst += 4; + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + + outV = vcvtq_n_s32_f32(inV,31); + + vst1q_s32(pDst, outV); + pDst += 4; + pIn += 4; + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + +} +#else +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of float_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c new file mode 100644 index 0000000..5f2a7eb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c @@ -0,0 +1,253 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q7.c + * Description: Converts the elements of the floating-point vector to Q7 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + *\par Description: + * \par + * The equation used for the conversion process is: + * 
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.
+ *
+ * \par Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + * \note + * In order to apply rounding, the library should be rebuilt with the ROUNDING macro + * defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_NEON) +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32_t in; + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 128.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 128.0f); + float32x4_t r; + uint32x4_t cmp; + #endif + + int32x4_t cvt; + int16x4_t cvt1,cvt2; + int8x8_t outV; + + blkCnt = blockSize >> 3U; + + /* Compute 8 outputs at a time. + ** a second loop below computes the remaining 1 to 7 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + outV = vqmovn_s16(vcombine_s16(cvt1,cvt2)); + vst1_s8(pDst, outV); + pDst += 8; + +#else + + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + inV = vld1q_f32(pIn); + cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + outV = vqmovn_s16(vcombine_s16(cvt1,cvt2)); + + vst1_s8(pDst, outV); + pDst += 8; +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + +} +#else +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of float_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c new file mode 100644 index 0000000..f49d9b7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c @@ -0,0 +1,166 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_float.c + * Description: Converts the elements of the Q15 vector to floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q15_to_x Convert 16-bit Integer value + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to floating-point vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.
+
+ */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int16x8_t inV; + int32x4_t inV0, inV1; + float32x4_t outV; + + blkCnt = blockSize >> 3U; + + /* Compute 8 outputs at a time. + ** a second loop below computes the remaining 1 to 7 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + inV = vld1q_s16(pIn); + pIn += 8; + + inV0 = vmovl_s16(vget_low_s16(inV)); + inV1 = vmovl_s16(vget_high_s16(inV)); + + outV = vcvtq_n_f32_s32(inV0,15); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inV1,15); + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 8, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 7; + + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of q15_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c new file mode 100644 index 0000000..1afd489 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_q31.c + * Description: Converts the elements of the Q15 vector to Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to Q31 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.
+
+ */ + +void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in1, in2; + q31_t out1, out2, out3, out4; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q31_t)A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + in1 = read_q15x2_ia ((q15_t **) &pIn); + in2 = read_q15x2_ia ((q15_t **) &pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + /* extract lower 16 bits to 32 bit result */ + out1 = in1 << 16U; + /* extract upper 16 bits to 32 bit result */ + out2 = in1 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out3 = in2 << 16U; + /* extract upper 16 bits to 32 bit result */ + out4 = in2 & 0xFFFF0000; + +#else + + /* extract upper 16 bits to 32 bit result */ + out1 = in1 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out2 = in1 << 16U; + /* extract upper 16 bits to 32 bit result */ + out3 = in2 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out4 = in2 << 16U; + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + *pDst++ = out1; + *pDst++ = out2; + *pDst++ = out3; + *pDst++ = out4; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pIn++ << 16; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of q15_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c new file mode 100644 index 0000000..d118b76 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_q7.c + * Description: Converts the elements of the Q15 vector to Q7 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to Q7 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the Q7 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.
+
+ */ + +void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in1, in2; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in1 = read_q15x2_ia ((q15_t **) &pIn); + in2 = read_q15x2_ia ((q15_t **) &pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + out1 = __PKHTB(in2, in1, 16); + out2 = __PKHBT(in2, in1, 16); + +#else + + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in1, in2, 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* rotate packed value by 24 */ + out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24); + + /* anding with 0xff00ff00 to get two 8 bit values */ + out1 = out1 & 0xFF00FF00; + /* anding with 0x00ff00ff to get two 8 bit values */ + out2 = out2 & 0x00FF00FF; + + /* oring two values(contains two 8 bit values) to get four packed 8 bit values */ + out1 = out1 | out2; + + /* store 4 samples at a time to destiantion buffer */ + write_q7x4_ia (&pDst, out1); + +#else + + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pIn++ >> 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of q15_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c new file mode 100644 index 0000000..03e7ec6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_float.c + * Description: Converts the elements of the Q31 vector to floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q31_to_x Convert 32-bit Integer value + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to floating-point vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.
+
+ */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int32x4_t inV; + float32x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* Convert from q31 to float and then store the results in the destination buffer */ + inV = vld1q_s32(pIn); + pIn += 4; + + outV = vcvtq_n_f32_s32(inV,31); + + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* Convert from q31 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 2147483648.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of q31_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c new file mode 100644 index 0000000..8d82c28 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_q15.c + * Description: Converts the elements of the Q31 vector to Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to Q15 vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.
+
+ */ + +void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in1, in2, in3, in4; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in1 = *pIn++; + in2 = *pIn++; + in3 = *pIn++; + in4 = *pIn++; + + /* pack two higher 16-bit values from two 32-bit values */ +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __PKHTB(in2, in1, 16); + out2 = __PKHTB(in4, in3, 16); +#else + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHTB(in3, in4, 16); +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pDst, out1); + write_q15x2_ia (&pDst, out2); + +#else + + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) (*pIn++ >> 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of q31_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c new file mode 100644 index 0000000..c7d1b4c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_q7.c + * Description: Converts the elements of the Q31 vector to Q7 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to Q7 vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the Q7 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.
+
+ */ + +void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q7_t out1, out2, out3, out4; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + + out1 = (q7_t) (*pIn++ >> 24); + out2 = (q7_t) (*pIn++ >> 24); + out3 = (q7_t) (*pIn++ >> 24); + out4 = (q7_t) (*pIn++ >> 24); + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pIn++ >> 24); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of q31_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c new file mode 100644 index 0000000..6bd86bf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c @@ -0,0 +1,179 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_float.c + * Description: Converts the elements of the Q7 vector to floating-point vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q7_to_x Convert 8-bit Integer value + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to floating-point vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.
+
+ */ + +#if defined(ARM_MATH_NEON) +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int8x16_t inV; + int16x8_t inVLO, inVHI; + int32x4_t inVLL, inVLH, inVHL, inVHH; + float32x4_t outV; + + blkCnt = blockSize >> 4U; + + /* Compute 16 outputs at a time. + ** a second loop below computes the remaining 1 to 15 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + /* Convert from q7 to float and then store the results in the destination buffer */ + inV = vld1q_s8(pIn); + pIn += 16; + + inVLO = vmovl_s8(vget_low_s8(inV)); + inVHI = vmovl_s8(vget_high_s8(inV)); + + inVLL = vmovl_s16(vget_low_s16(inVLO)); + inVLH = vmovl_s16(vget_high_s16(inVLO)); + inVHL = vmovl_s16(vget_low_s16(inVHI)); + inVHH = vmovl_s16(vget_high_s16(inVHI)); + + outV = vcvtq_n_f32_s32(inVLL,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVLH,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVHL,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVHH,7); + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 16, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 0xF; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + /* Convert from q7 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of q7_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c new file mode 100644 index 0000000..89afd10 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_q15.c + * Description: Converts the elements of the Q7 vector to Q15 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to Q15 vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.
+
+ */ + +void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in; + q31_t in1, in2; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in = read_q7x4_ia ((q7_t **) &pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + + in1 = in1 << 8U; + in2 = in2 << 8U; + + in1 = in1 & 0xFF00FF00; + in2 = in2 & 0xFF00FF00; + +#ifndef ARM_MATH_BIG_ENDIAN + out2 = __PKHTB(in1, in2, 16); + out1 = __PKHBT(in2, in1, 16); +#else + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in2, in1, 16); +#endif + + write_q15x2_ia (&pDst, out1); + write_q15x2_ia (&pDst, out2); + +#else + + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) * pIn++ << 8; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of q7_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c new file mode 100644 index 0000000..641c02d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_q31.c + * Description: Converts the elements of the Q7 vector to Q31 vector + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to Q31 vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.
+
+ */ + +void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q31_t in; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + in = read_q7x4_ia ((q7_t **) &pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + *pDst++ = (__ROR(in, 8)) & 0xFF000000; + *pDst++ = (__ROR(in, 16)) & 0xFF000000; + *pDst++ = (__ROR(in, 24)) & 0xFF000000; + *pDst++ = (in & 0xFF000000); + +#else + + *pDst++ = (in & 0xFF000000); + *pDst++ = (__ROR(in, 24)) & 0xFF000000; + *pDst++ = (__ROR(in, 16)) & 0xFF000000; + *pDst++ = (__ROR(in, 8)) & 0xFF000000; + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) * pIn++ << 24; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of q7_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt new file mode 100644 index 0000000..4e5b4f2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt @@ -0,0 +1,116 @@ +cmake_minimum_required (VERSION 3.6) + +project(CMSISDSPTransform) + + + +add_library(CMSISDSPTransform STATIC) + +include(fft) +fft(CMSISDSPTransform) + +if (CONFIGTABLE AND ALLFFT) +target_compile_definitions(CMSISDSPTransform PUBLIC ARM_ALL_FFT_TABLES) +endif() + +target_sources(CMSISDSPTransform PRIVATE arm_bitreversal.c) +target_sources(CMSISDSPTransform PRIVATE arm_bitreversal2.c) + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_F32_16 OR CFFT_F32_32 OR CFFT_F32_64 OR CFFT_F32_128 OR CFFT_F32_256 OR CFFT_F32_512 + OR CFFT_F32_1024 OR CFFT_F32_2048 OR CFFT_F32_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix8_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_Q15_16 OR CFFT_Q15_32 OR CFFT_Q15_64 OR CFFT_Q15_128 OR CFFT_Q15_256 OR CFFT_Q15_512 + OR CFFT_Q15_1024 OR CFFT_Q15_2048 OR CFFT_Q15_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_Q31_16 OR CFFT_Q31_32 OR CFFT_Q31_64 OR CFFT_Q31_128 OR CFFT_Q31_256 OR CFFT_Q31_512 + OR CFFT_Q31_1024 OR CFFT_Q31_2048 OR CFFT_Q31_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_init_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR DCT4_F32_128 OR DCT4_F32_512 OR DCT4_F32_2048 OR DCT4_F32_8192) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_init_f32.c) + +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR DCT4_Q31_128 OR DCT4_Q31_512 OR DCT4_Q31_2048 OR DCT4_Q31_8192) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_init_q31.c) + +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR ALLFFT OR DCT4_Q15_128 OR DCT4_Q15_512 OR DCT4_Q15_2048 OR DCT4_Q15_8192) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_q15.c) + +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_FAST_F32_32 OR RFFT_FAST_F32_64 OR RFFT_FAST_F32_128 + OR RFFT_FAST_F32_256 OR RFFT_FAST_F32_512 OR RFFT_FAST_F32_1024 OR RFFT_FAST_F32_2048 + OR RFFT_FAST_F32_4096 ) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix8_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_F32_128 OR RFFT_F32_512 OR RFFT_F32_2048 OR RFFT_F32_8192) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_Q15_32 OR RFFT_Q15_64 OR RFFT_Q15_128 OR RFFT_Q15_256 + OR RFFT_Q15_512 OR RFFT_Q15_1024 OR RFFT_Q15_2048 OR RFFT_Q15_4096 OR RFFT_Q15_8192) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_Q31_32 OR RFFT_Q31_64 OR RFFT_Q31_128 OR RFFT_Q31_256 + OR RFFT_Q31_512 OR RFFT_Q31_1024 OR RFFT_Q31_2048 OR RFFT_Q31_4096 OR RFFT_Q31_8192) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q31.c) +endif() + +configdsp(CMSISDSPTransform ..) + +### Includes +target_include_directories(CMSISDSPTransform PUBLIC "${DSP}/../../Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c new file mode 100644 index 0000000..d0f7ce4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: TransformFunctions.c + * Description: Combination of all transform function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_bitreversal.c" +#include "arm_bitreversal2.c" +#include "arm_cfft_f32.c" +#include "arm_cfft_q15.c" +#include "arm_cfft_q31.c" +#include "arm_cfft_radix2_f32.c" +#include "arm_cfft_radix2_init_f32.c" +#include "arm_cfft_radix2_init_q15.c" +#include "arm_cfft_radix2_init_q31.c" +#include "arm_cfft_radix2_q15.c" +#include "arm_cfft_radix2_q31.c" +#include "arm_cfft_radix4_f32.c" +#include "arm_cfft_radix4_init_f32.c" +#include "arm_cfft_radix4_init_q15.c" +#include "arm_cfft_radix4_init_q31.c" +#include "arm_cfft_radix4_q15.c" +#include "arm_cfft_radix4_q31.c" +#include "arm_cfft_radix8_f32.c" +#include "arm_dct4_f32.c" +#include "arm_dct4_init_f32.c" +#include "arm_dct4_init_q15.c" +#include "arm_dct4_init_q31.c" +#include "arm_dct4_q15.c" +#include "arm_dct4_q31.c" +#include "arm_rfft_f32.c" +#include "arm_rfft_fast_f32.c" +#include "arm_rfft_fast_init_f32.c" +#include "arm_rfft_init_f32.c" +#include "arm_rfft_init_q15.c" +#include "arm_rfft_init_q31.c" +#include "arm_rfft_q15.c" +#include "arm_rfft_q31.c" diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c new file mode 100644 index 0000000..c608129 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c @@ -0,0 +1,229 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal.c + * Description: Bitreversal functions + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @brief In-place floating-point bit reversal function. + @param[in,out] pSrc points to in-place floating-point data buffer + @param[in] fftSize length of FFT + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none + */ + +void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + uint16_t fftLenBy2, fftLenBy2p1; + uint16_t i, j; + float32_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftSize >> 1U; + fftLenBy2p1 = (fftSize >> 1U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + + +/** + @brief In-place Q31 bit reversal function. + @param[in,out] pSrc points to in-place Q31 data buffer. + @param[in] fftLen length of FFT. + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + uint32_t fftLenBy2, fftLenBy2p1, i, j; + q31_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftLen / 2U; + fftLenBy2p1 = (fftLen / 2U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + + + +/** + @brief In-place Q15 bit reversal function. + @param[in,out] pSrc16 points to in-place Q15 data buffer + @param[in] fftLen length of FFT + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_q15( + q15_t * pSrc16, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + q31_t *pSrc = (q31_t *) pSrc16; + q31_t in; + uint32_t fftLenBy2, fftLenBy2p1; + uint32_t i, j; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftLen / 2U; + fftLenBy2p1 = (fftLen / 2U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[i]; + pSrc[i] = pSrc[j]; + pSrc[j] = in; + + /* pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1]; */ + /* pSrc[i + fftLenBy2p1+1U] <-> pSrc[j + fftLenBy2p1+1U] */ + in = pSrc[i + fftLenBy2p1]; + pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1]; + pSrc[j + fftLenBy2p1] = in; + } + + /* pSrc[i+1U] <-> pSrc[j+fftLenBy2]; */ + /* pSrc[i+2] <-> pSrc[j+fftLenBy2+1U] */ + in = pSrc[i + 1U]; + pSrc[i + 1U] = pSrc[j + fftLenBy2]; + pSrc[j + fftLenBy2] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S new file mode 100644 index 0000000..c16091b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S @@ -0,0 +1,216 @@ +;/* ---------------------------------------------------------------------- +; * Project: CMSIS DSP Library +; * Title: arm_bitreversal2.S +; * Description: arm_bitreversal_32 function done in assembly for maximum speed. +; * Called after doing an fft to reorder the output. +; * The function is loop unrolled by 2. arm_bitreversal_16 as well. +; * +; * $Date: 18. March 2019 +; * $Revision: V1.5.2 +; * +; * Target Processor: Cortex-M cores +; * -------------------------------------------------------------------- */ +;/* +; * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +#if defined ( __CC_ARM ) /* Keil */ + #define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2 + #define LABEL +#elif defined ( __IASMARM__ ) /* IAR */ + #define CODESECT SECTION `.text`:CODE + #define PROC + #define LABEL + #define ENDP + #define EXPORT PUBLIC +#elif defined ( __CSMC__ ) /* Cosmic */ + #define CODESECT switch .text + #define THUMB + #define EXPORT xdef + #define PROC : + #define LABEL : + #define ENDP + #define arm_bitreversal_32 _arm_bitreversal_32 +#elif defined ( __TI_ARM__ ) /* TI ARM */ + #define THUMB .thumb + #define CODESECT .text + #define EXPORT .global + #define PROC : .asmfunc + #define LABEL : + #define ENDP .endasmfunc + #define END +#elif defined ( __GNUC__ ) /* GCC */ + #define THUMB .thumb + #define CODESECT .section .text + #define EXPORT .global + #define PROC : + #define LABEL : + #define ENDP + #define END + + .syntax unified +#endif + + CODESECT + THUMB + +;/** +; @brief In-place bit reversal function. +; @param[in,out] pSrc points to the in-place buffer of unknown 32-bit data type +; @param[in] bitRevLen bit reversal table length +; @param[in] pBitRevTab points to bit reversal table +; @return none +; */ + EXPORT arm_bitreversal_32 + EXPORT arm_bitreversal_16 + +#if defined ( __CC_ARM ) /* Keil */ +#elif defined ( __IASMARM__ ) /* IAR */ +#elif defined ( __CSMC__ ) /* Cosmic */ +#elif defined ( __TI_ARM__ ) /* TI ARM */ +#elif defined ( __GNUC__ ) /* GCC */ + .type arm_bitreversal_16, %function + .type arm_bitreversal_32, %function +#endif + +#if defined (ARM_MATH_CM0_FAMILY) + +arm_bitreversal_32 PROC + ADDS r3,r1,#1 + PUSH {r4-r6} + ADDS r1,r2,#0 + LSRS r3,r3,#1 +arm_bitreversal_32_0 LABEL + LDRH r2,[r1,#2] + LDRH r6,[r1,#0] + ADD r2,r0,r2 + ADD r6,r0,r6 + LDR r5,[r2,#0] + LDR r4,[r6,#0] + STR r5,[r6,#0] + STR r4,[r2,#0] + LDR r5,[r2,#4] + LDR r4,[r6,#4] + STR r5,[r6,#4] + STR r4,[r2,#4] + ADDS r1,r1,#4 + SUBS r3,r3,#1 + BNE arm_bitreversal_32_0 + POP {r4-r6} + BX lr + ENDP + +arm_bitreversal_16 PROC + ADDS r3,r1,#1 + PUSH {r4-r6} + ADDS r1,r2,#0 + LSRS r3,r3,#1 +arm_bitreversal_16_0 LABEL + LDRH r2,[r1,#2] + LDRH r6,[r1,#0] + LSRS r2,r2,#1 + LSRS r6,r6,#1 + ADD r2,r0,r2 + ADD r6,r0,r6 + LDR r5,[r2,#0] + LDR r4,[r6,#0] + STR r5,[r6,#0] + STR r4,[r2,#0] + ADDS r1,r1,#4 + SUBS r3,r3,#1 + BNE arm_bitreversal_16_0 + POP {r4-r6} + BX lr + ENDP + +#else + +arm_bitreversal_32 PROC + ADDS r3,r1,#1 + CMP r3,#1 + IT LS + BXLS lr + PUSH {r4-r9} + ADDS r1,r2,#2 + LSRS r3,r3,#2 +arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */ + LDRH r8,[r1,#4] + LDRH r9,[r1,#2] + LDRH r2,[r1,#0] + LDRH r12,[r1,#-2] + ADD r8,r0,r8 + ADD r9,r0,r9 + ADD r2,r0,r2 + ADD r12,r0,r12 + LDR r7,[r9,#0] + LDR r6,[r8,#0] + LDR r5,[r2,#0] + LDR r4,[r12,#0] + STR r6,[r9,#0] + STR r7,[r8,#0] + STR r5,[r12,#0] + STR r4,[r2,#0] + LDR r7,[r9,#4] + LDR r6,[r8,#4] + LDR r5,[r2,#4] + LDR r4,[r12,#4] + STR r6,[r9,#4] + STR r7,[r8,#4] + STR r5,[r12,#4] + STR r4,[r2,#4] + ADDS r1,r1,#8 + SUBS r3,r3,#1 + BNE arm_bitreversal_32_0 + POP {r4-r9} + BX lr + ENDP + +arm_bitreversal_16 PROC + ADDS r3,r1,#1 + CMP r3,#1 + IT LS + BXLS lr + PUSH {r4-r9} + ADDS r1,r2,#2 + LSRS r3,r3,#2 +arm_bitreversal_16_0 LABEL ;/* loop unrolled by 2 */ + LDRH r8,[r1,#4] + LDRH r9,[r1,#2] + LDRH r2,[r1,#0] + LDRH r12,[r1,#-2] + ADD r8,r0,r8,LSR #1 + ADD r9,r0,r9,LSR #1 + ADD r2,r0,r2,LSR #1 + ADD r12,r0,r12,LSR #1 + LDR r7,[r9,#0] + LDR r6,[r8,#0] + LDR r5,[r2,#0] + LDR r4,[r12,#0] + STR r6,[r9,#0] + STR r7,[r8,#0] + STR r5,[r12,#0] + STR r4,[r2,#0] + ADDS r1,r1,#8 + SUBS r3,r3,#1 + BNE arm_bitreversal_16_0 + POP {r4-r9} + BX lr + ENDP + +#endif + + END diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c new file mode 100644 index 0000000..c5fe60f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c @@ -0,0 +1,99 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal2.c + * Description: Bitreversal functions + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @brief In-place 32 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 32-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_32( + uint32_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint32_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} + + +/** + @brief In-place 16 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 16-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_16( + uint16_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint16_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c new file mode 100644 index 0000000..2fff61c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c @@ -0,0 +1,629 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_f32.c + * Description: Combined Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +extern void arm_radix8_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_bitreversal_32( + uint32_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +/** + @ingroup groupTransforms + */ + +/** + @defgroup ComplexFFT Complex FFT Functions + + @par + The Fast Fourier Transform (FFT) is an efficient algorithm for computing the + Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster + than the DFT, especially for long lengths. + The algorithms described in this section + operate on complex data. A separate set of functions is devoted to handling + of real sequences. + @par + There are separate algorithms for handling floating-point, Q15, and Q31 data + types. The algorithms available for each data type are described next. + @par + The FFT functions operate in-place. That is, the array holding the input data + will also be used to hold the corresponding result. The input data is complex + and contains 2*fftLen interleaved values as shown below. + 
{real[0], imag[0], real[1], imag[1], ...}
+ The FFT result will be contained in the same array and the frequency domain + values will have the same interleaving. + + @par Floating-point + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8 + stages are performed along with a single radix-2 or radix-4 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + Pre-initialized data structures containing twiddle factors and bit reversal + tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_f32. For example: + @par + arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_f32 function follows: + @code + const static arm_cfft_instance_f32 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_f32_len16; + break; + case 32: + S = &arm_cfft_sR_f32_len32; + break; + case 64: + S = &arm_cfft_sR_f32_len64; + break; + case 128: + S = &arm_cfft_sR_f32_len128; + break; + case 256: + S = &arm_cfft_sR_f32_len256; + break; + case 512: + S = &arm_cfft_sR_f32_len512; + break; + case 1024: + S = &arm_cfft_sR_f32_len1024; + break; + case 2048: + S = &arm_cfft_sR_f32_len2048; + break; + case 4096: + S = &arm_cfft_sR_f32_len4096; + break; + } + @endcode + @par Q15 and Q31 + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4 + stages are performed along with a single radix-2 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + Pre-initialized data structures containing twiddle factors and bit reversal + tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_q31. For example: + @par + arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_q31 function follows: + @code + const static arm_cfft_instance_q31 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_q31_len16; + break; + case 32: + S = &arm_cfft_sR_q31_len32; + break; + case 64: + S = &arm_cfft_sR_q31_len64; + break; + case 128: + S = &arm_cfft_sR_q31_len128; + break; + case 256: + S = &arm_cfft_sR_q31_len256; + break; + case 512: + S = &arm_cfft_sR_q31_len512; + break; + case 1024: + S = &arm_cfft_sR_q31_len1024; + break; + case 2048: + S = &arm_cfft_sR_q31_len2048; + break; + case 4096: + S = &arm_cfft_sR_q31_len4096; + break; + } + @endcode + + */ + +void arm_cfft_radix8by2_f32 (arm_cfft_instance_f32 * S, float32_t * p1) +{ + uint32_t L = S->fftLen; + float32_t * pCol1, * pCol2, * pMid1, * pMid2; + float32_t * p2 = p1 + L; + const float32_t * tw = (float32_t *) S->pTwiddle; + float32_t t1[4], t2[4], t3[4], t4[4], twR, twI; + float32_t m0, m1, m2, m3; + uint32_t l; + + pCol1 = p1; + pCol2 = p2; + + /* Define new length */ + L >>= 1; + + /* Initialize mid pointers */ + pMid1 = p1 + L; + pMid2 = p2 + L; + + /* do two dot Fourier transform */ + for (l = L >> 2; l > 0; l-- ) + { + t1[0] = p1[0]; + t1[1] = p1[1]; + t1[2] = p1[2]; + t1[3] = p1[3]; + + t2[0] = p2[0]; + t2[1] = p2[1]; + t2[2] = p2[2]; + t2[3] = p2[3]; + + t3[0] = pMid1[0]; + t3[1] = pMid1[1]; + t3[2] = pMid1[2]; + t3[3] = pMid1[3]; + + t4[0] = pMid2[0]; + t4[1] = pMid2[1]; + t4[2] = pMid2[2]; + t4[3] = pMid2[3]; + + *p1++ = t1[0] + t2[0]; + *p1++ = t1[1] + t2[1]; + *p1++ = t1[2] + t2[2]; + *p1++ = t1[3] + t2[3]; /* col 1 */ + + t2[0] = t1[0] - t2[0]; + t2[1] = t1[1] - t2[1]; + t2[2] = t1[2] - t2[2]; + t2[3] = t1[3] - t2[3]; /* for col 2 */ + + *pMid1++ = t3[0] + t4[0]; + *pMid1++ = t3[1] + t4[1]; + *pMid1++ = t3[2] + t4[2]; + *pMid1++ = t3[3] + t4[3]; /* col 1 */ + + t4[0] = t4[0] - t3[0]; + t4[1] = t4[1] - t3[1]; + t4[2] = t4[2] - t3[2]; + t4[3] = t4[3] - t3[3]; /* for col 2 */ + + twR = *tw++; + twI = *tw++; + + /* multiply by twiddle factors */ + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + /* R = R * Tr - I * Ti */ + *p2++ = m0 + m1; + /* I = I * Tr + R * Ti */ + *p2++ = m2 - m3; + + /* use vertical symmetry */ + /* 0.9988 - 0.0491i <==> -0.0491 - 0.9988i */ + m0 = t4[0] * twI; + m1 = t4[1] * twR; + m2 = t4[1] * twI; + m3 = t4[0] * twR; + + *pMid2++ = m0 - m1; + *pMid2++ = m2 + m3; + + twR = *tw++; + twI = *tw++; + + m0 = t2[2] * twR; + m1 = t2[3] * twI; + m2 = t2[3] * twR; + m3 = t2[2] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + + m0 = t4[2] * twI; + m1 = t4[3] * twR; + m2 = t4[3] * twI; + m3 = t4[2] * twR; + + *pMid2++ = m0 - m1; + *pMid2++ = m2 + m3; + } + + /* first col */ + arm_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 2U); + + /* second col */ + arm_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 2U); +} + +void arm_cfft_radix8by4_f32 (arm_cfft_instance_f32 * S, float32_t * p1) +{ + uint32_t L = S->fftLen >> 1; + float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4; + const float32_t *tw2, *tw3, *tw4; + float32_t * p2 = p1 + L; + float32_t * p3 = p2 + L; + float32_t * p4 = p3 + L; + float32_t t2[4], t3[4], t4[4], twR, twI; + float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1; + float32_t m0, m1, m2, m3; + uint32_t l, twMod2, twMod3, twMod4; + + pCol1 = p1; /* points to real values by default */ + pCol2 = p2; + pCol3 = p3; + pCol4 = p4; + pEnd1 = p2 - 1; /* points to imaginary values by default */ + pEnd2 = p3 - 1; + pEnd3 = p4 - 1; + pEnd4 = pEnd3 + L; + + tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle; + + L >>= 1; + + /* do four dot Fourier transform */ + + twMod2 = 2; + twMod3 = 4; + twMod4 = 6; + + /* TOP */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* Twiddle factors are ones */ + *p2++ = t2[0]; + *p2++ = t2[1]; + *p3++ = t3[0]; + *p3++ = t3[1]; + *p4++ = t4[0]; + *p4++ = t4[1]; + + tw2 += twMod2; + tw3 += twMod3; + tw4 += twMod4; + + for (l = (L - 2) >> 1; l > 0; l-- ) + { + /* TOP */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 - top */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* BOTTOM */ + p1ap3_1 = pEnd1[-1] + pEnd3[-1]; + p1sp3_1 = pEnd1[-1] - pEnd3[-1]; + p1ap3_0 = pEnd1[ 0] + pEnd3[0]; + p1sp3_0 = pEnd1[ 0] - pEnd3[0]; + /* col 2 */ + t2[2] = pEnd2[0] - pEnd4[0] + p1sp3_1; + t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1]; + /* col 3 */ + t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1]; + t3[3] = p1ap3_0 - pEnd2[ 0] - pEnd4[ 0]; + /* col 4 */ + t4[2] = pEnd2[ 0] - pEnd4[ 0] - p1sp3_1; + t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0; + /* col 1 - Bottom */ + *pEnd1-- = p1ap3_0 + pEnd2[ 0] + pEnd4[ 0]; + *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1]; + + /* COL 2 */ + /* read twiddle factors */ + twR = *tw2++; + twI = *tw2++; + /* multiply by twiddle factors */ + /* let Z1 = a + i(b), Z2 = c + i(d) */ + /* => Z1 * Z2 = (a*c - b*d) + i(b*c + a*d) */ + + /* Top */ + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + /* use vertical symmetry col 2 */ + /* 0.9997 - 0.0245i <==> 0.0245 - 0.9997i */ + /* Bottom */ + m0 = t2[3] * twI; + m1 = t2[2] * twR; + m2 = t2[2] * twI; + m3 = t2[3] * twR; + + *pEnd2-- = m0 - m1; + *pEnd2-- = m2 + m3; + + /* COL 3 */ + twR = tw3[0]; + twI = tw3[1]; + tw3 += twMod3; + /* Top */ + m0 = t3[0] * twR; + m1 = t3[1] * twI; + m2 = t3[1] * twR; + m3 = t3[0] * twI; + + *p3++ = m0 + m1; + *p3++ = m2 - m3; + /* use vertical symmetry col 3 */ + /* 0.9988 - 0.0491i <==> -0.9988 - 0.0491i */ + /* Bottom */ + m0 = -t3[3] * twR; + m1 = t3[2] * twI; + m2 = t3[2] * twR; + m3 = t3[3] * twI; + + *pEnd3-- = m0 - m1; + *pEnd3-- = m3 - m2; + + /* COL 4 */ + twR = tw4[0]; + twI = tw4[1]; + tw4 += twMod4; + /* Top */ + m0 = t4[0] * twR; + m1 = t4[1] * twI; + m2 = t4[1] * twR; + m3 = t4[0] * twI; + + *p4++ = m0 + m1; + *p4++ = m2 - m3; + /* use vertical symmetry col 4 */ + /* 0.9973 - 0.0736i <==> -0.0736 + 0.9973i */ + /* Bottom */ + m0 = t4[3] * twI; + m1 = t4[2] * twR; + m2 = t4[2] * twI; + m3 = t4[3] * twR; + + *pEnd4-- = m0 - m1; + *pEnd4-- = m2 + m3; + } + + /* MIDDLE */ + /* Twiddle factors are */ + /* 1.0000 0.7071-0.7071i -1.0000i -0.7071-0.7071i */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 - Top */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* COL 2 */ + twR = tw2[0]; + twI = tw2[1]; + + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + /* COL 3 */ + twR = tw3[0]; + twI = tw3[1]; + + m0 = t3[0] * twR; + m1 = t3[1] * twI; + m2 = t3[1] * twR; + m3 = t3[0] * twI; + + *p3++ = m0 + m1; + *p3++ = m2 - m3; + /* COL 4 */ + twR = tw4[0]; + twI = tw4[1]; + + m0 = t4[0] * twR; + m1 = t4[1] * twI; + m2 = t4[1] * twR; + m3 = t4[0] * twI; + + *p4++ = m0 + m1; + *p4++ = m2 - m3; + + /* first col */ + arm_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 4U); + + /* second col */ + arm_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 4U); + + /* third col */ + arm_radix8_butterfly_f32 (pCol3, L, (float32_t *) S->pTwiddle, 4U); + + /* fourth col */ + arm_radix8_butterfly_f32 (pCol4, L, (float32_t *) S->pTwiddle, 4U); +} + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float32_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for (l = 0; l < L; l++) + { + *pSrc = -*pSrc; + pSrc += 2; + } + } + + switch (L) + { + case 16: + case 128: + case 1024: + arm_cfft_radix8by2_f32 ( (arm_cfft_instance_f32 *) S, p1); + break; + case 32: + case 256: + case 2048: + arm_cfft_radix8by4_f32 ( (arm_cfft_instance_f32 *) S, p1); + break; + case 64: + case 512: + case 4096: + arm_radix8_butterfly_f32 ( p1, L, (float32_t *) S->pTwiddle, 1); + break; + } + + if ( bitReverseFlag ) + arm_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0f / (float32_t)L; + + /* Conjugate and scale output data */ + pSrc = p1; + for (l= 0; l < L; l++) + { + *pSrc++ *= invL ; + *pSrc = -(*pSrc) * invL; + pSrc++; + } + } +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c new file mode 100644 index 0000000..28ad1e1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c @@ -0,0 +1,332 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_q15.c + * Description: Combined Radix Decimation in Q15 Frequency CFFT processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +extern void arm_radix4_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_bitreversal_16( + uint16_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +void arm_cfft_radix4by2_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef); + +void arm_cfft_radix4by2_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for Q15 complex FFT. + @param[in] S points to an instance of Q15 CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen; + + if (ifftFlag == 1U) + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_inverse_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q15 ( p1, L, S->pTwiddle ); + break; + } + } + else + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q15 ( p1, L, S->pTwiddle ); + break; + } + } + + if ( bitReverseFlag ) + arm_bitreversal_16 ((uint16_t*) p1, S->bitRevLength, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_cfft_radix4by2_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef) +{ + uint32_t i; + uint32_t n2; + q15_t p0, p1, p2, p3; +#if defined (ARM_MATH_DSP) + q31_t T, S, R; + q31_t coeff, out1, out2; + const q15_t *pC = pCoef; + q15_t *pSi = pSrc; + q15_t *pSl = pSrc + fftLen; +#else + uint32_t l; + q15_t xt, yt, cosVal, sinVal; +#endif + + n2 = fftLen >> 1U; + +#if defined (ARM_MATH_DSP) + + for (i = n2; i > 0; i--) + { + coeff = read_q15x2_ia ((q15_t **) &pC); + + T = read_q15x2 (pSi); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __SHADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __QSUB16(T, S); + + write_q15x2_ia (&pSi, __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16U; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pSl, (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + } + +#else /* #if defined (ARM_MATH_DSP) */ + + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16U)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16U)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16U)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16U)) ); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* first col */ + arm_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + p2 = pSrc[4 * i + 2]; + p3 = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + p2 <<= 1U; + p3 <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = p2; + pSrc[4 * i + 3] = p3; + } + +} + +void arm_cfft_radix4by2_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef) +{ + uint32_t i; + uint32_t n2; + q15_t p0, p1, p2, p3; +#if defined (ARM_MATH_DSP) + q31_t T, S, R; + q31_t coeff, out1, out2; + const q15_t *pC = pCoef; + q15_t *pSi = pSrc; + q15_t *pSl = pSrc + fftLen; +#else + uint32_t l; + q15_t xt, yt, cosVal, sinVal; +#endif + + n2 = fftLen >> 1U; + +#if defined (ARM_MATH_DSP) + + for (i = n2; i > 0; i--) + { + coeff = read_q15x2_ia ((q15_t **) &pC); + + T = read_q15x2 (pSi); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __SHADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __QSUB16(T, S); + + write_q15x2_ia (&pSi, __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16U; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pSl, (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + } + +#else /* #if defined (ARM_MATH_DSP) */ + + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16U)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16U)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16U)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16U)) ); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* first col */ + arm_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + p2 = pSrc[4 * i + 2]; + p3 = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + p2 <<= 1U; + p3 <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = p2; + pSrc[4 * i + 3] = p3; + } +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c new file mode 100644 index 0000000..701ac95 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c @@ -0,0 +1,254 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_q31.c + * Description: Combined Radix Decimation in Frequency CFFT fixed point processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +extern void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_bitreversal_32( + uint32_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +void arm_cfft_radix4by2_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef); + +void arm_cfft_radix4by2_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 complex FFT. + @param[in] S points to an instance of the fixed-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen; + + if (ifftFlag == 1U) + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_inverse_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q31 ( p1, L, S->pTwiddle ); + break; + } + } + else + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q31 ( p1, L, S->pTwiddle ); + break; + } + } + + if ( bitReverseFlag ) + arm_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_cfft_radix4by2_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef) +{ + uint32_t i, l; + uint32_t n2; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 2U) - (pSrc[2 * l] >> 2U); + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + + yt = (pSrc[2 * i + 1] >> 2U) - (pSrc[2 * l + 1] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2 * l] = p0 << 1; + pSrc[2 * l + 1] = p1 << 1; + } + + /* first col */ + arm_radix4_butterfly_q31 (pSrc, n2, (q31_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_q31 (pSrc + fftLen, n2, (q31_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + xt = pSrc[4 * i + 2]; + yt = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + xt <<= 1U; + yt <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = xt; + pSrc[4 * i + 3] = yt; + } + +} + +void arm_cfft_radix4by2_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef) +{ + uint32_t i, l; + uint32_t n2; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 2U) - (pSrc[2 * l] >> 2U); + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + + yt = (pSrc[2 * i + 1] >> 2U) - (pSrc[2 * l + 1] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2 * l] = p0 << 1U; + pSrc[2 * l + 1] = p1 << 1U; + } + + /* first col */ + arm_radix4_butterfly_inverse_q31( pSrc, n2, (q31_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_inverse_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + xt = pSrc[4 * i + 2]; + yt = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + xt <<= 1U; + yt <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = xt; + pSrc[4 * i + 3] = yt; + } +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c new file mode 100644 index 0000000..f75e329 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c @@ -0,0 +1,470 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_f32.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Radix-2 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future + @param[in] S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_f32( +const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-2 */ + arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-2 */ + arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + + +/** + @} end of ComplexFFT group + */ + + + +/* ---------------------------------------------------------------------- + ** Internal helper function used by the FFTs + ** ------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + return none + */ + +void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float32_t xt, yt, cosVal, sinVal; + float32_t p0, p1, p2, p3; + float32_t a0, a1; + +#if defined (ARM_MATH_DSP) + + /* Initializations for the first stage */ + n2 = fftLen >> 1; + ia = 0; + i = 0; + + // loop for groups + for (k = n2; k > 0; k--) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + /* Twiddle coefficients index modifier */ + ia += twidCoefModifier; + + /* index calculation for the input as, */ + /* pSrc[i + 0], pSrc[i + fftLen/1] */ + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i++; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = n2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2); // groups loop end + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + pSrc[2 * i + 2] = xt; + pSrc[2 * i + 3] = yt; + } // groups loop end + +#else /* #if defined (ARM_MATH_DSP) */ + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 1; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while (i < fftLen); + j++; + } while (j < n2); + twidCoefModifier <<= 1U; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float32_t xt, yt, cosVal, sinVal; + float32_t p0, p1, p2, p3; + float32_t a0, a1; + +#if defined (ARM_MATH_DSP) + + n2 = fftLen >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while (j < n2); // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * i + 1] = p1; + pSrc[2 * i + 2] = p2; + pSrc[2 * i + 3] = p3; + } // butterfly loop end + +#else /* #if defined (ARM_MATH_DSP) */ + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2 ); // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * l] = p2; + + pSrc[2 * i + 1] = p1; + pSrc[2 * l + 1] = p3; + } // butterfly loop end + +#endif /* #if defined (ARM_MATH_DSP) */ + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c new file mode 100644 index 0000000..417ad91 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c @@ -0,0 +1,197 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_f32.c + * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *) twiddleCoef; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.00048828125; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.001953125; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + S->onebyfftLen = 0.0078125; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 32U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + S->onebyfftLen = 0.03125; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c new file mode 100644 index 0000000..3d865d0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_q15.c + * Description: Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed + @param[in,out] S points to an instance of the Q15 CFFT/CIFFT structure. + @param[in] fftLen length of the FFT. + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q15_t *) twiddleCoef_4096_q15; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + S->twidCoefModifier = 4U; + S->bitRevFactor = 4U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + S->twidCoefModifier = 8U; + S->bitRevFactor = 8U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + + break; + + case 32U: + /* Initializations of structure parameters for 32 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c new file mode 100644 index 0000000..f4a20d6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c @@ -0,0 +1,179 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_q31.c + * Description: Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in,out] S points to an instance of the Q31 CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q31_t *) twiddleCoef_4096_q31; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) + { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + break; + + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + break; + + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + break; + + case 32U: + /* Initializations of structure parameters for 32 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c new file mode 100644 index 0000000..2a03b57 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c @@ -0,0 +1,689 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_q15.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier); + +void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the fixed-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in] S points to an instance of the fixed-point CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + arm_radix2_butterfly_inverse_q15 (pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + arm_radix2_butterfly_q15 (pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier) +{ +#if defined (ARM_MATH_DSP) + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t in; + q31_t T, S, R; + q31_t coeff, out1, out2; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + i++; + l++; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + i += n1; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + i += n1; + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + } /* groups loop end */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t xt, yt, cosVal, sinVal; + + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + + (pSrc[2 * i + 1] >> 1U) ) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2U * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2U * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2 * l] = xt; + + pSrc[2 * l + 1] = yt; + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier) +{ +#if defined (ARM_MATH_DSP) + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t in; + q31_t T, S, R; + q31_t coeff, out1, out2; + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (i = 0; i < n2; i++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + i++; + l++; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + i += n1; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + +#else /* #if defined (ARM_MATH_DSP) */ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t xt, yt, cosVal, sinVal; + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + + (pSrc[2 * i + 1] >> 1U) ) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16)) ); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2 * l] = xt; + + pSrc[2 * l + 1] = yt; + + } /* groups loop end */ + + +#endif /* #if defined (ARM_MATH_DSP) */ + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c new file mode 100644 index 0000000..6c79a65 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c @@ -0,0 +1,337 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_q31.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier); + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the fixed-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in] S points to an instance of the fixed-point CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen, + S->pTwiddle, S->twidCoefModifier); + } + else + { + arm_radix2_butterfly_q31(pSrc, S->fftLen, + S->pTwiddle, S->twidCoefModifier); + } + + arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier) +{ + + unsigned i, j, k, l, m; + unsigned n1, n2, ia; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = + ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + m = fftLen / n1; + do + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + i += n1; + m--; + } while ( m > 0); // butterfly loop end + + } // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + i += n1; + l = i + n2; + + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + } // butterfly loop end + +} + + +void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier) +{ + + unsigned i, j, k, l; + unsigned n1, n2, ia; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = + ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + } // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + } // butterfly loop end + + } // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + i += n1; + l = i + n2; + + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + } // butterfly loop end + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c new file mode 100644 index 0000000..9629145 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c @@ -0,0 +1,1200 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_f32.c + * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point Radix-4 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future. + @param[in] S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to the twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + return none + */ + +void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + float32_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_LOOPUNROLL) + + float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float32_t *ptr1; + float32_t p0,p1,p2,p3,p4,p5; + float32_t a0,a1,a2,a3,a4,a5,a6,a7; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + /* Updating input index */ + i0++; + + } + while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + a0 = (Xaplusc + Xbplusd); + /* ya' = ya + yb + yc + yd */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa+yb-xc-yd) */ + a4 = (Xaminusc + Ybminusd); + /* yb' = (ya-xb-yc+xd) */ + a5 = (Yaminusc - Xbminusd); + /* xd' = (xa-yb-xc+yd)) */ + a6 = (Xaminusc - Ybminusd); + /* yd' = (ya+xb-yc-xd) */ + a7 = (Xbminusd + Yaminusc); + + ptr1[0] = a0; + ptr1[1] = a1; + ptr1[2] = a2; + ptr1[3] = a3; + ptr1[4] = a4; + ptr1[5] = a5; + ptr1[6] = a6; + ptr1[7] = a7; + + /* increment pointer by 8 */ + ptr1 += 8U; + } while (--j); + +#else + + float32_t t1, t2, r1, r2, s1, s2; + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) + (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2); + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) + (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) + (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + brief Core function for the floating-point CIFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + param[in] onebyfftLen value of 1/fftLen + return none + */ + +void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen) +{ + float32_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_LOOPUNROLL) + + float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float32_t *ptr1; + float32_t p0,p1,p2,p3,p4,p5,p6,p7; + float32_t a0,a1,a2,a3,a4,a5,a6,a7; + + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* Butterfly implementation */ + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + a0 = (Xaplusc + Xbplusd); + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + a4 = (Xaminusc - Ybminusd); + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + a5 = (Yaminusc + Xbminusd); + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + a6 = (Xaminusc + Ybminusd); + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + a7 = (Yaminusc - Xbminusd); + + p0 = a0 * onebyfftLen; + p1 = a1 * onebyfftLen; + p2 = a2 * onebyfftLen; + p3 = a3 * onebyfftLen; + p4 = a4 * onebyfftLen; + p5 = a5 * onebyfftLen; + p6 = a6 * onebyfftLen; + p7 = a7 * onebyfftLen; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + ptr1[0] = p0; + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + ptr1[1] = p1; + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + ptr1[2] = p2; + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + ptr1[3] = p3; + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[4] = p4; + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + ptr1[5] = p5; + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[6] = p6; + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + ptr1[7] = p7; + + /* increment source pointer by 8 for next calculations */ + ptr1 = ptr1 + 8U; + + } while (--j); + +#else + + float32_t t1, t2, r1, r2, s1, s2; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* Calculation of first stage */ + for (k = fftLen; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) - (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) + (r1 * si2); + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) - (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) + (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) - (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) + (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + n1 = n2; + n2 >>= 2U; + + /* Calculations of last stage */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xc + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) * onebyfftLen; + + /* (xa + xb) - (xc + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) * onebyfftLen; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb-yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb-xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = r1 * onebyfftLen; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = s1 * onebyfftLen; + + /* (xa - xc) - (yb-yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb-yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb-xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb-xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = r1 * onebyfftLen; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = s1 * onebyfftLen; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = r2 * onebyfftLen; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = s2 * onebyfftLen; + } + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +} + + diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c new file mode 100644 index 0000000..930c2c1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c @@ -0,0 +1,156 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_f32.c + * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *) twiddleCoef; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c new file mode 100644 index 0000000..0090688 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_q15.c + * Description: Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Initialization function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in,out] S points to an instance of the Q15 CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + /* Initialise the FFT length */ + S->fftLen = fftLen; + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q15_t *) twiddleCoef_4096_q15; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + S->twidCoefModifier = 4U; + S->bitRevFactor = 4U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c new file mode 100644 index 0000000..17d16b7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_q31.c + * Description: Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + + @brief Initialization function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in,out] S points to an instance of the Q31 CFFT/CIFFT structure. + @param[in] fftLen length of the FFT. + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + /* Initialise the FFT length */ + S->fftLen = fftLen; + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q31_t *) twiddleCoef_4096_q31; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) + { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c new file mode 100644 index 0000000..b4cabb1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c @@ -0,0 +1,1809 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_q15.c + * Description: This file has function definition of Radix-4 FFT & IFFT function and + * In-place bit reversal using bit reversal table + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + + +void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier); + +void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Processing function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in] S points to an instance of the Q15 CFFT/CIFFT structure. + @param[in,out] pSrc points to the complex data buffer. Processing occurs in-place. + @return none + + @par Input and output formats: + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different FFT sizes. + The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: + @par + \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT" + \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT" + */ + +void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* + * Radix-4 FFT algorithm used is : + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 FFT: + * Wn = co1 + j * (- si1) + * W2n = co2 + j * (- si2) + * W3n = co3 + j * (- si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) + * yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) + * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) + * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) + * + */ + +/** + @brief Core function for the Q15 CFFT butterfly process. + @param[in,out] pSrc16 points to the in-place buffer of Q15 data type + @param[in] fftLen length of the FFT + @param[in] pCoef16 points to twiddle coefficient buffer + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier) +{ + +#if defined (ARM_MATH_DSP) + + q31_t R, S, T, U; + q31_t C1, C2, C3, out1, out2; + uint32_t n1, n2, ic, i0, j, k; + + q15_t *ptr1; + q15_t *pSi0; + q15_t *pSi1; + q15_t *pSi2; + q15_t *pSi3; + + q31_t xaya, xbyb, xcyc, xdyd; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + j = n2; + + pSi0 = pSrc16; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + T = __SHADD16(T, 0); /* it turns out doing this twice is 2 cycles, the alternative takes 3 cycles */ +/* + in = ((int16_t) (T & 0xFFFF)) >> 2; // alternative code that takes 3 cycles + T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF); +*/ + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + S = __SHADD16(S, 0); + S = __SHADD16(S, 0); + + /* R = packed((ya + yc), (xa + xc) ) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc) ) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed((yb + yd), (xb + xd) ) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&pSi0, __SHADD16(R, T)); + + /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */ + R = __QSUB16(R, T); + + /* co2 & si2 are read from SIMD Coefficient pointer */ + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = __SMUAD(C2, R) >> 16U; + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUSDX(C2, R); +#else + /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUSDX(R, C2) >> 16U; + /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out2 = __SMUAD(C2, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+fftLen/4 */ + /* T = packed(yb, xb) */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + write_q15x2_ia (&pSi1, (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + /* Butterfly calculations */ + /* U = packed(yd, xd) */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QASX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QSAX(S, T); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QSAX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QASX(S, T); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* co1 & si1 are read from SIMD Coefficient pointer */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + /* Butterfly process for the i0+fftLen/2 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = __SMUAD(C1, S) >> 16U; + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = __SMUSDX(C1, S); +#else + /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out1 = __SMUSDX(S, C1) >> 16U; + /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out2 = __SMUAD(C1, S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xb', yb') in little endian format */ + write_q15x2_ia (&pSi2, ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF)); + + /* co3 & si3 are read from SIMD Coefficient pointer */ + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out1 = __SMUAD(C3, R) >> 16U; + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out2 = __SMUSDX(C3, R); +#else + /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out1 = __SMUSDX(R, C3) >> 16U; + /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out2 = __SMUAD(C3, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xd', yd') in little endian format */ + write_q15x2_ia (&pSi3, ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + pSi0 = pSrc16 + 2 * j; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + + /* R = packed( (ya + yc), (xa + xc)) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed( (yb + yd), (xb + xd)) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = __SHADD16(R, T); + out1 = __SHADD16(out1, 0); + write_q15x2 (pSi0, out1); + pSi0 += 2 * n1; + + /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */ + R = __SHSUB16(R, T); + +#ifndef ARM_MATH_BIG_ENDIAN + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = __SMUAD(C2, R) >> 16U; + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUSDX(C2, R); +#else + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUSDX(R, C2) >> 16U; + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out2 = __SMUAD(C2, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + write_q15x2 (pSi1, ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + pSi1 += 2 * n1; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHASX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHSAX(S, T); + + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUAD(C1, S) >> 16U; + out2 = __SMUSDX(C1, S); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHSAX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHASX(S, T); + + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUSDX(S, C1) >> 16U; + out2 = __SMUAD(C1, S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + write_q15x2 (pSi2, ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + pSi2 += 2 * n1; + + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(C3, R) >> 16U; + out2 = __SMUSDX(C3, R); +#else + out1 = __SMUSDX(R, C3) >> 16U; + out2 = __SMUAD(C3, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + write_q15x2 (pSi3, ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + pSi3 += 2 * n1; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + j = fftLen >> 2; + + ptr1 = &pSrc16[0]; + + /* start of last stage process */ + + /* Butterfly implementation */ + do + { + /* Read xa (real), ya(imag) input */ + xaya = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xb (real), yb(imag) input */ + xbyb = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xc (real), yc(imag) input */ + xcyc = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xd (real), yd(imag) input */ + xdyd = read_q15x2_ia ((q15_t **) &ptr1); + + /* R = packed((ya + yc), (xa + xc)) */ + R = __QADD16(xaya, xcyc); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&ptr1, __SHADD16(R, T)); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + write_q15x2_ia (&ptr1, __SHSUB16(R, T)); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(xaya, xcyc); + + /* Read yd (real), xd(imag) input */ + /* T = packed( (yb - yd), (xb - xd)) */ + U = __QSUB16(xbyb, xdyd); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); +#else + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + } while (--j); + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + q15_t R0, R1, S0, S1, T0, T1, U0, U1; + q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2; + uint32_t n1, n2, ic, i0, i1, i2, i3, j, k; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + i0 = 0U; + j = n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + + /* input is down scale by 4 to avoid overflow */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U] >> 2U; + T1 = pSrc16[(i0 * 2U) + 1U] >> 2U; + + /* input is down scale by 4 to avoid overflow */ + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U] >> 2U; + S1 = pSrc16[(i2 * 2U) + 1U] >> 2U; + + /* R0 = (ya + yc) */ + R0 = __SSAT(T0 + S0, 16U); + /* R1 = (xa + xc) */ + R1 = __SSAT(T1 + S1, 16U); + + /* S0 = (ya - yc) */ + S0 = __SSAT(T0 - S0, 16); + /* S1 = (xa - xc) */ + S1 = __SSAT(T1 - S1, 16); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + + /* input is down scale by 4 to avoid overflow */ + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1] >> 2U; + + /* T0 = (yb + yd) */ + T0 = __SSAT(T0 + U0, 16U); + /* T1 = (xb + xd) */ + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* ya' = ya + yb + yc + yd */ + /* xa' = xa + xb + xc + xd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd) */ + /* R1 = (xa + xc) - (xb + xd) */ + R0 = __SSAT(R0 - T0, 16U); + R1 = __SSAT(R1 - T1, 16U); + + /* co2 & si2 are read from Coefficient pointer */ + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[(2U * ic * 2U) + 1]; + + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U); + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+fftLen/4 */ + /* input is down scale by 4 to avoid overflow */ + /* T0 = yb, T1 = xb */ + T0 = pSrc16[i1 * 2U] >> 2; + T1 = pSrc16[(i1 * 2U) + 1] >> 2; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1] = out2; + + /* Butterfly calculations */ + /* input is down scale by 4 to avoid overflow */ + /* U0 = yd, U1 = xd */ + U0 = pSrc16[i3 * 2U] >> 2; + U1 = pSrc16[(i3 * 2U) + 1] >> 2; + /* T0 = yb-yd */ + T0 = __SSAT(T0 - U0, 16); + /* T1 = xb-xd */ + T1 = __SSAT(T1 - U1, 16); + + /* R1 = (ya-yc) + (xb- xd), R0 = (xa-xc) - (yb-yd)) */ + R0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16); + R1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16); + + /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */ + S0 = (q15_t) __SSAT(((q31_t) S0 + T1), 16U); + S1 = (q15_t) __SSAT(((q31_t) S1 - T0), 16U); + + /* co1 & si1 are read from Coefficient pointer */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1]; + /* Butterfly process for the i0+fftLen/2 sample */ + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = (q15_t) ((Si1 * S1 + Co1 * S0) >> 16); + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16); + + /* writing output(xb', yb') in little endian format */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1] = out2; + + /* Co3 & si3 are read from Coefficient pointer */ + Co3 = pCoef16[3U * (ic * 2U)]; + Si3 = pCoef16[(3U * (ic * 2U)) + 1]; + /* Butterfly process for the i0+3fftLen/4 sample */ + /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */ + out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U); + /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */ + out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U); + /* writing output(xd', yd') in little endian format */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1] = out2; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + Co2 = pCoef16[2U * (ic * 2U)]; + Si2 = pCoef16[(2U * (ic * 2U)) + 1U]; + Co3 = pCoef16[3U * (ic * 2U)]; + Si3 = pCoef16[(3U * (ic * 2U)) + 1U]; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16); + R1 = __SSAT(T1 + S1, 16); + + /* S0 = (ya - yc), S1 =(xa - xc) */ + S0 = __SSAT(T0 - S0, 16); + S1 = __SSAT(T1 - S1, 16); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16); + T1 = __SSAT(T1 + U1, 16); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = ((R0 >> 1U) + (T0 >> 1U)) >> 1U; + out2 = ((R1 >> 1U) + (T1 >> 1U)) >> 1U; + + pSrc16[i0 * 2U] = out1; + pSrc16[(2U * i0) + 1U] = out2; + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U); + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = yb-yd, T1 = xb-xd */ + T0 = __SSAT(T0 - U0, 16); + T1 = __SSAT(T1 - U1, 16); + + /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */ + R0 = (S0 >> 1U) - (T1 >> 1U); + R1 = (S1 >> 1U) + (T0 >> 1U); + + /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */ + S0 = (S0 >> 1U) + (T1 >> 1U); + S1 = (S1 >> 1U) - (T0 >> 1U); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = (q15_t) ((Co1 * S0 + Si1 * S1) >> 16U); + + out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16U); + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Butterfly process for the i0+3fftLen/4 sample */ + out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U); + + out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U); + /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + n1 = n2; + n2 >>= 2U; + + /* start of last stage process */ + + /* Butterfly implementation */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd)) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + pSrc16[i1 * 2U] = R0; + pSrc16[(i1 * 2U) + 1U] = R1; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + /* T0 = (yb - yd), T1 = (xb - xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* writing the butterfly processed i0 + fftLen/2 sample */ + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + pSrc16[i2 * 2U] = (S0 >> 1U) + (T1 >> 1U); + pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U); + + /* writing the butterfly processed i0 + 3fftLen/4 sample */ + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + pSrc16[i3 * 2U] = (S0 >> 1U) - (T1 >> 1U); + pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U); + + } + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +/** + @brief Core function for the Q15 CIFFT butterfly process. + @param[in,out] pSrc16 points to the in-place buffer of Q15 data type + @param[in] fftLen length of the FFT + @param[in] pCoef16 points to twiddle coefficient buffer + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +/* + * Radix-4 IFFT algorithm used is : + * + * CIFFT uses same twiddle coefficients as CFFT function + * x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4] + * + * + * IFFT is implemented with following changes in equations from FFT + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 IFFT: + * Wn = co1 + j * (si1) + * W2n = co2 + j * (si2) + * W3n = co3 + j * (si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) + * yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) + * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) + * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) + * + */ + +void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier) +{ + +#if defined (ARM_MATH_DSP) + + q31_t R, S, T, U; + q31_t C1, C2, C3, out1, out2; + uint32_t n1, n2, ic, i0, j, k; + + q15_t *ptr1; + q15_t *pSi0; + q15_t *pSi1; + q15_t *pSi2; + q15_t *pSi3; + + q31_t xaya, xbyb, xcyc, xdyd; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + j = n2; + + pSi0 = pSrc16; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + S = __SHADD16(S, 0); + S = __SHADD16(S, 0); + + /* R = packed((ya + yc), (xa + xc) ) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc) ) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed((yb + yd), (xb + xd) ) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&pSi0, __SHADD16(R, T)); + + /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */ + R = __QSUB16(R, T); + + /* co2 & si2 are read from SIMD Coefficient pointer */ + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = __SMUSD(C2, R) >> 16U; + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUADX(C2, R); +#else + /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUADX(C2, R) >> 16U; + /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out2 = __SMUSD(__QSUB16(0, C2), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+fftLen/4 */ + /* T = packed(yb, xb) */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + write_q15x2_ia (&pSi1, (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + /* Butterfly calculations */ + /* U = packed(yd, xd) */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QSAX(S, T); + /* S = packed((ya-yc) + (xb- xd), (xa-xc) - (yb-yd)) */ + S = __QASX(S, T); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QASX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QSAX(S, T); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* co1 & si1 are read from SIMD Coefficient pointer */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + /* Butterfly process for the i0+fftLen/2 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = __SMUSD(C1, S) >> 16U; + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = __SMUADX(C1, S); +#else + /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out1 = __SMUADX(C1, S) >> 16U; + /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out2 = __SMUSD(__QSUB16(0, C1), S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xb', yb') in little endian format */ + write_q15x2_ia (&pSi2, ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF)); + + /* co3 & si3 are read from SIMD Coefficient pointer */ + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out1 = __SMUSD(C3, R) >> 16U; + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out2 = __SMUADX(C3, R); +#else + /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out1 = __SMUADX(C3, R) >> 16U; + /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out2 = __SMUSD(__QSUB16(0, C3), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xd', yd') in little endian format */ + write_q15x2_ia (&pSi3, ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + pSi0 = pSrc16 + 2 * j; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + + /* R = packed( (ya + yc), (xa + xc)) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed( (yb + yd), (xb + xd)) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = __SHADD16(R, T); + out1 = __SHADD16(out1, 0); + write_q15x2 (pSi0, out1); + pSi0 += 2 * n1; + + /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */ + R = __SHSUB16(R, T); + +#ifndef ARM_MATH_BIG_ENDIAN + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = __SMUSD(C2, R) >> 16U; + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUADX(C2, R); +#else + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUADX(R, C2) >> 16U; + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out2 = __SMUSD(__QSUB16(0, C2), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + write_q15x2 (pSi1, ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + pSi1 += 2 * n1; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHSAX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHASX(S, T); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUSD(C1, S) >> 16U; + out2 = __SMUADX(C1, S); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHASX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHSAX(S, T); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUADX(S, C1) >> 16U; + out2 = __SMUSD(__QSUB16(0, C1), S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + write_q15x2 (pSi2, ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + pSi2 += 2 * n1; + + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(C3, R) >> 16U; + out2 = __SMUADX(C3, R); +#else + out1 = __SMUADX(C3, R) >> 16U; + out2 = __SMUSD(__QSUB16(0, C3), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + write_q15x2 (pSi3, ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + pSi3 += 2 * n1; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + j = fftLen >> 2; + + ptr1 = &pSrc16[0]; + + /* start of last stage process */ + + /* Butterfly implementation */ + do + { + /* Read xa (real), ya(imag) input */ + xaya = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xb (real), yb(imag) input */ + xbyb = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xc (real), yc(imag) input */ + xcyc = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xd (real), yd(imag) input */ + xdyd = read_q15x2_ia ((q15_t **) &ptr1); + + /* R = packed((ya + yc), (xa + xc)) */ + R = __QADD16(xaya, xcyc); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&ptr1, __SHADD16(R, T)); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + write_q15x2_ia (&ptr1, __SHSUB16(R, T)); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(xaya, xcyc); + + /* Read yd (real), xd(imag) input */ + /* T = packed( (yb - yd), (xb - xd)) */ + U = __QSUB16(xbyb, xdyd); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); +#else + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + } while (--j); + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + + +#else /* arm_radix4_butterfly_inverse_q15 */ + + q15_t R0, R1, S0, S1, T0, T1, U0, U1; + q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2; + uint32_t n1, n2, ic, i0, i1, i2, i3, j, k; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + i0 = 0U; + + j = n2; + + /* Input is in 1.15(q15) format */ + + /* Start of first stage process */ + do + { + /* Butterfly implementation */ + + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U] >> 2U; + T1 = pSrc16[(i0 * 2U) + 1U] >> 2U; + /* input is down scale by 4 to avoid overflow */ + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U] >> 2U; + S1 = pSrc16[(i2 * 2U) + 1U] >> 2U; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + /* Read yd (real), xd(imag) input */ + /* input is down scale by 4 to avoid overflow */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1U] >> 2U; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */ + R0 = __SSAT(R0 - T0, 16U); + R1 = __SSAT(R1 - T1, 16U); + /* co2 & si2 are read from Coefficient pointer */ + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[(2U * ic * 2U) + 1U]; + /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */ + out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16U); + /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+fftLen/4 */ + /* input is down scale by 4 to avoid overflow */ + /* T0 = yb, T1 = xb */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + /* input is down scale by 4 to avoid overflow */ + /* U0 = yd, U1 = xd) */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1U] >> 2U; + + /* T0 = yb-yd, T1 = xb-xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */ + R0 = (q15_t) __SSAT((q31_t) (S0 + T1), 16); + R1 = (q15_t) __SSAT((q31_t) (S1 - T0), 16); + /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */ + S0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16); + S1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16); + + /* co1 & si1 are read from Coefficient pointer */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + /* Butterfly process for the i0+fftLen/2 sample */ + /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */ + out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U); + /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */ + out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U); + /* writing output(xb', yb') in little endian format */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Co3 & si3 are read from Coefficient pointer */ + Co3 = pCoef16[3U * ic * 2U]; + Si3 = pCoef16[(3U * ic * 2U) + 1U]; + /* Butterfly process for the i0+3fftLen/4 sample */ + /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */ + out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U); + /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */ + out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U); + /* writing output(xd', yd') in little endian format */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* End of first stage process */ + + /* data is in 4.11(q11) format */ + + + /* Start of Middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[2U * ic * 2U + 1U]; + Co3 = pCoef16[3U * ic * 2U]; + Si3 = pCoef16[(3U * ic * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = ((R0 >> 1U) + (T0 >> 1U)) >> 1U; + pSrc16[(i0 * 2U) + 1U] = ((R1 >> 1U) + (T1 >> 1U)) >> 1U; + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */ + out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16); + /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = yb-yd, T1 = xb-xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */ + R0 = (S0 >> 1U) + (T1 >> 1U); + R1 = (S1 >> 1U) - (T0 >> 1U); + + /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */ + S0 = (S0 >> 1U) - (T1 >> 1U); + S1 = (S1 >> 1U) + (T0 >> 1U); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U); + out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U); + /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */ + /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Butterfly process for the i0+3fftLen/4 sample */ + out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U); + + out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U); + /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */ + /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + + + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* End of Middle stages process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* start of last stage process */ + + + /* Initializations for the last stage */ + n1 = n2; + n2 >>= 2U; + + /* Butterfly implementation */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + pSrc16[i1 * 2U] = R0; + pSrc16[(i1 * 2U) + 1U] = R1; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + /* T0 = (yb - yd), T1 = (xb - xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* writing the butterfly processed i0 + fftLen/2 sample */ + /* xb' = (xa-yb-xc+yd) */ + /* yb' = (ya+xb-yc-xd) */ + pSrc16[i2 * 2U] = (S0 >> 1U) - (T1 >> 1U); + pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U); + + + /* writing the butterfly processed i0 + 3fftLen/4 sample */ + /* xd' = (xa+yb-xc-yd) */ + /* yd' = (ya-xb-yc+xd) */ + pSrc16[i3 * 2U] = (S0 >> 1U) + (T1 >> 1U); + pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U); + } + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + +#endif /* #if defined (ARM_MATH_DSP) */ + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c new file mode 100644 index 0000000..a9a59dd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c @@ -0,0 +1,827 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_q31.c + * Description: This file has function definition of Radix-4 FFT & IFFT function and + * In-place bit reversal using bit reversal table + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in] S points to an instance of the Q31 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + + @par Input and output formats: + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different FFT sizes. + The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: + @par + \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT" + \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT" + */ + +void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* + * Radix-4 FFT algorithm used is : + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 FFT: + * Wn = co1 + j * (- si1) + * W2n = co2 + j * (- si2) + * W3n = co3 + j * (- si3) + * + * Butterfly implementation: + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) + * yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) + * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) + * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) + * + */ + +/** + @brief Core function for the Q31 CFFT butterfly process. + @param[in,out] pSrc points to the in-place buffer of Q31 data type. + @param[in] fftLen length of the FFT. + @param[in] pCoef points to twiddle coefficient buffer. + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier) +{ + uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k; + q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3; + + q31_t xa, xb, xc, xd; + q31_t ya, yb, yc, yd; + q31_t xa_out, xb_out, xc_out, xd_out; + q31_t ya_out, yb_out, yc_out, yd_out; + + q31_t *ptr1; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + + /* start of first stage process */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* input is in 1.31(q31) format and provide 4 guard bits for the input */ + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (pSrc[(2U * i0)] >> 4U) + (pSrc[(2U * i2)] >> 4U); + /* xa - xc */ + r2 = (pSrc[(2U * i0)] >> 4U) - (pSrc[(2U * i2)] >> 4U); + + /* xb + xd */ + t1 = (pSrc[(2U * i1)] >> 4U) + (pSrc[(2U * i3)] >> 4U); + + /* ya + yc */ + s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U); + /* ya - yc */ + s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U); + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1); + /* (xa + xc) - (xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U); + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2); + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* yb - yd */ + t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U); + /* xb - xd */ + t2 = (pSrc[(2U * i1)] >> 4U) - (pSrc[(2U * i3)] >> 4U); + + /* index calculation for the coefficients */ + ia2 = 2U * ia1; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) + + ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) - + ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U; + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) + + ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) - + ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U; + + /* index calculation for the coefficients */ + ia3 = 3U * ia1; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) + + ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) - + ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* end of first stage process */ + + /* data is in 5.27(q27) format */ + + + /* start of Middle stages process */ + + + /* each stage in middle stages provides two down scaling of the input */ + + twidCoefModifier <<= 2U; + + + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) >> 2U; + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) + + ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1U; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) - + ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1U; + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) + + ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) - + ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) + + ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) - + ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U; + } + } + twidCoefModifier <<= 2U; + } + + /* End of Middle stages process */ + + /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */ + /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */ + /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */ + /* data is in 5.27(q27) format for the 16 point as there are no middle stages */ + + + /* start of Last stage process */ + /* Initializations for the last stage */ + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + /* Read xa (real), ya(imag) input */ + xa = *ptr1++; + ya = *ptr1++; + + /* Read xb (real), yb(imag) input */ + xb = *ptr1++; + yb = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xc = *ptr1++; + yc = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xd = *ptr1++; + yd = *ptr1++; + + /* xa' = xa + xb + xc + xd */ + xa_out = xa + xb + xc + xd; + + /* ya' = ya + yb + yc + yd */ + ya_out = ya + yb + yc + yd; + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + /* writing xa' and ya' */ + *ptr1++ = xa_out; + *ptr1++ = ya_out; + + xc_out = (xa - xb + xc - xd); + yc_out = (ya - yb + yc - yd); + + /* writing xc' and yc' */ + *ptr1++ = xc_out; + *ptr1++ = yc_out; + + xb_out = (xa + yb - xc - yd); + yb_out = (ya - xb - yc + xd); + + /* writing xb' and yb' */ + *ptr1++ = xb_out; + *ptr1++ = yb_out; + + xd_out = (xa - yb - xc + yd); + yd_out = (ya + xb - yc - xd); + + /* writing xd' and yd' */ + *ptr1++ = xd_out; + *ptr1++ = yd_out; + + + } while (--j); + + /* output is in 11.21(q21) format for the 1024 point */ + /* output is in 9.23(q23) format for the 256 point */ + /* output is in 7.25(q25) format for the 64 point */ + /* output is in 5.27(q27) format for the 16 point */ + + /* End of last stage process */ + +} + + +/** + @brief Core function for the Q31 CIFFT butterfly process. + @param[in,out] pSrc points to the in-place buffer of Q31 data type. + @param[in] fftLen length of the FFT. + @param[in] pCoef points to twiddle coefficient buffer. + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +/* + * Radix-4 IFFT algorithm used is : + * + * CIFFT uses same twiddle coefficients as CFFT Function + * x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4] + * + * + * IFFT is implemented with following changes in equations from FFT + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 IFFT: + * Wn = co1 + j * (si1) + * W2n = co2 + j * (si2) + * W3n = co3 + j * (si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) + * yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) + * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) + * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) + * + */ + +void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier) +{ + uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k; + q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3; + q31_t xa, xb, xc, xd; + q31_t ya, yb, yc, yd; + q31_t xa_out, xb_out, xc_out, xd_out; + q31_t ya_out, yb_out, yc_out, yd_out; + + q31_t *ptr1; + + /* input is be 1.31(q31) format for all FFT sizes */ + /* Total process is divided into three stages */ + /* process first stage, middle stages, & last stage */ + + /* Start of first stage process */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + do + { + /* input is in 1.31(q31) format and provide 4 guard bits for the input */ + + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (pSrc[2U * i0] >> 4U) + (pSrc[2U * i2] >> 4U); + /* xa - xc */ + r2 = (pSrc[2U * i0] >> 4U) - (pSrc[2U * i2] >> 4U); + + /* xb + xd */ + t1 = (pSrc[2U * i1] >> 4U) + (pSrc[2U * i3] >> 4U); + + /* ya + yc */ + s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U); + /* ya - yc */ + s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U); + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1); + /* (xa + xc) - (xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U); + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2); + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* yb - yd */ + t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U); + /* xb - xd */ + t2 = (pSrc[2U * i1] >> 4U) - (pSrc[2U * i3] >> 4U); + + /* index calculation for the coefficients */ + ia2 = 2U * ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) - + ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[2U * i1 + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) + + ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U; + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) - + ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) + + ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U; + + /* index calculation for the coefficients */ + ia3 = 3U * ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) - + ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) + + ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* data is in 5.27(q27) format */ + /* each stage provides two down scaling of the input */ + + + /* Start of Middle stages process */ + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + for (j = 0; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) >> 2U; + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32U)) - + ((int32_t) (((q63_t) s1 * si2) >> 32U))) >> 1U; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32U)) + + ((int32_t) (((q63_t) r1 * si2) >> 32U))) >> 1U; + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) - + ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) + + ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[(2U * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) - + ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) + + ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U; + } + } + twidCoefModifier <<= 2U; + } + + /* End of Middle stages process */ + + /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */ + /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */ + /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */ + /* data is in 5.27(q27) format for the 16 point as there are no middle stages */ + + + /* Start of last stage process */ + + + /* Initializations for the last stage */ + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + /* Read xa (real), ya(imag) input */ + xa = *ptr1++; + ya = *ptr1++; + + /* Read xb (real), yb(imag) input */ + xb = *ptr1++; + yb = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xc = *ptr1++; + yc = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xd = *ptr1++; + yd = *ptr1++; + + /* xa' = xa + xb + xc + xd */ + xa_out = xa + xb + xc + xd; + + /* ya' = ya + yb + yc + yd */ + ya_out = ya + yb + yc + yd; + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + /* writing xa' and ya' */ + *ptr1++ = xa_out; + *ptr1++ = ya_out; + + xc_out = (xa - xb + xc - xd); + yc_out = (ya - yb + yc - yd); + + /* writing xc' and yc' */ + *ptr1++ = xc_out; + *ptr1++ = yc_out; + + xb_out = (xa - yb - xc + yd); + yb_out = (ya + xb - yc - xd); + + /* writing xb' and yb' */ + *ptr1++ = xb_out; + *ptr1++ = yb_out; + + xd_out = (xa + yb - xc - yd); + yd_out = (ya - xb - yc + xd); + + /* writing xd' and yd' */ + *ptr1++ = xd_out; + *ptr1++ = yd_out; + + } while (--j); + + /* output is in 11.21(q21) format for the 1024 point */ + /* output is in 9.23(q23) format for the 256 point */ + /* output is in 7.25(q25) format for the 64 point */ + /* output is in 5.27(q27) format for the 16 point */ + + /* End of last stage process */ +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c new file mode 100644 index 0000000..50048f6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c @@ -0,0 +1,285 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix8_f32.c + * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * -------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type. + param[in] fftLen length of the FFT. + param[in] pCoef points to the twiddle coefficient buffer. + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + return none +*/ + +void arm_radix8_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7; + uint32_t i1, i2, i3, i4, i5, i6, i7, i8; + uint32_t id; + uint32_t n1, n2, j; + + float32_t r1, r2, r3, r4, r5, r6, r7, r8; + float32_t t1, t2; + float32_t s1, s2, s3, s4, s5, s6, s7, s8; + float32_t p1, p2, p3, p4; + float32_t co2, co3, co4, co5, co6, co7, co8; + float32_t si2, si3, si4, si5, si6, si7, si8; + const float32_t C81 = 0.70710678118f; + + n2 = fftLen; + + do + { + n1 = n2; + n2 = n2 >> 3; + i1 = 0; + + do + { + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + pSrc[2 * i5] = r1 - r2; + r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = r1 - s3; + r1 = r1 + s3; + s3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1 + 1] = r1 + r2; + pSrc[2 * i5 + 1] = r1 - r2; + pSrc[2 * i3] = t1 + s3; + pSrc[2 * i7] = t1 - s3; + pSrc[2 * i3 + 1] = t2 - r3; + pSrc[2 * i7 + 1] = t2 + r3; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + r2 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - r2; + s5 = s5 + r2; + s8 = s7 - s6; + s7 = s7 + s6; + pSrc[2 * i2] = r5 + s7; + pSrc[2 * i8] = r5 - s7; + pSrc[2 * i6] = t1 + s8; + pSrc[2 * i4] = t1 - s8; + pSrc[2 * i2 + 1] = s5 - r7; + pSrc[2 * i8 + 1] = s5 + r7; + pSrc[2 * i6 + 1] = t2 - r8; + pSrc[2 * i4 + 1] = t2 + r8; + + i1 += n1; + } while (i1 < fftLen); + + if (n2 < 8) + break; + + ia1 = 0; + j = 1; + + do + { + /* index calculation for the coefficients */ + id = ia1 + twidCoefModifier; + ia1 = id; + ia2 = ia1 + id; + ia3 = ia2 + id; + ia4 = ia3 + id; + ia5 = ia4 + id; + ia6 = ia5 + id; + ia7 = ia6 + id; + + co2 = pCoef[2 * ia1]; + co3 = pCoef[2 * ia2]; + co4 = pCoef[2 * ia3]; + co5 = pCoef[2 * ia4]; + co6 = pCoef[2 * ia5]; + co7 = pCoef[2 * ia6]; + co8 = pCoef[2 * ia7]; + si2 = pCoef[2 * ia1 + 1]; + si3 = pCoef[2 * ia2 + 1]; + si4 = pCoef[2 * ia3 + 1]; + si5 = pCoef[2 * ia4 + 1]; + si6 = pCoef[2 * ia5 + 1]; + si7 = pCoef[2 * ia6 + 1]; + si8 = pCoef[2 * ia7 + 1]; + + i1 = j; + + do + { + /* index calculation for the input */ + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + r2 = r1 - r2; + s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = s1 - s3; + s1 = s1 + s3; + s3 = s2 - s4; + s2 = s2 + s4; + r1 = t1 + s3; + t1 = t1 - s3; + pSrc[2 * i1 + 1] = s1 + s2; + s2 = s1 - s2; + s1 = t2 - r3; + t2 = t2 + r3; + p1 = co5 * r2; + p2 = si5 * s2; + p3 = co5 * s2; + p4 = si5 * r2; + pSrc[2 * i5] = p1 + p2; + pSrc[2 * i5 + 1] = p3 - p4; + p1 = co3 * r1; + p2 = si3 * s1; + p3 = co3 * s1; + p4 = si3 * r1; + pSrc[2 * i3] = p1 + p2; + pSrc[2 * i3 + 1] = p3 - p4; + p1 = co7 * t1; + p2 = si7 * t2; + p3 = co7 * t2; + p4 = si7 * t1; + pSrc[2 * i7] = p1 + p2; + pSrc[2 * i7 + 1] = p3 - p4; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + s1 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - s1; + s5 = s5 + s1; + s8 = s7 - s6; + s7 = s7 + s6; + r1 = r5 + s7; + r5 = r5 - s7; + r6 = t1 + s8; + t1 = t1 - s8; + s1 = s5 - r7; + s5 = s5 + r7; + s6 = t2 - r8; + t2 = t2 + r8; + p1 = co2 * r1; + p2 = si2 * s1; + p3 = co2 * s1; + p4 = si2 * r1; + pSrc[2 * i2] = p1 + p2; + pSrc[2 * i2 + 1] = p3 - p4; + p1 = co8 * r5; + p2 = si8 * s5; + p3 = co8 * s5; + p4 = si8 * r5; + pSrc[2 * i8] = p1 + p2; + pSrc[2 * i8 + 1] = p3 - p4; + p1 = co6 * r6; + p2 = si6 * s6; + p3 = co6 * s6; + p4 = si6 * r6; + pSrc[2 * i6] = p1 + p2; + pSrc[2 * i6 + 1] = p3 - p4; + p1 = co4 * t1; + p2 = si4 * t2; + p3 = co4 * t2; + p4 = si4 * t1; + pSrc[2 * i4] = p1 + p2; + pSrc[2 * i4 + 1] = p3 - p4; + + i1 += n1; + } while (i1 < fftLen); + + j++; + } while (j < n2); + + twidCoefModifier <<= 3; + } while (n2 > 7); +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c new file mode 100644 index 0000000..87455dc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c @@ -0,0 +1,448 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_f32.c + * Description: Processing function of DCT4 & IDCT4 F32 + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @ingroup groupTransforms + */ + +/** + @defgroup DCT4_IDCT4 DCT Type IV Functions + + Representation of signals by minimum number of values is important for storage and transmission. + The possibility of large discontinuity between the beginning and end of a period of a signal + in DFT can be avoided by extending the signal so that it is even-symmetric. + Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the + spectrum and is very widely used in signal and image coding applications. + The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions. + DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular. + + DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal. + Reordering of the input data makes the computation of DCT just a problem of + computing the DFT of a real signal with a few additional operations. + This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations. + + DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used. + DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing. + DCT2 implementation can be described in the following steps: + - Re-ordering input + - Calculating Real FFT + - Multiplication of weights and Real FFT output and getting real part from the product. + + This process is explained by the block diagram below: + \image html DCT4.gif "Discrete Cosine Transform - type-IV" + + @par Algorithm + The N-point type-IV DCT is defined as a real, linear transformation by the formula: + \image html DCT4Equation.gif + where k = 0, 1, 2, ..., N-1 + @par + Its inverse is defined as follows: + \image html IDCT4Equation.gif + where n = 0, 1, 2, ..., N-1 + @par + The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N). + The symmetry of the transform matrix indicates that the fast algorithms for the forward + and inverse transform computation are identical. + Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both. + + @par Lengths supported by the transform: + As DCT4 internally uses Real FFT, it supports all the lengths 128, 512, 2048 and 8192. + The library provides separate functions for Q15, Q31, and floating-point data types. + + @par Instance Structure + The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure. + A separate instance structure must be defined for each transform. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes Real FFT as its process function is used internally in DCT4, by calling \ref arm_rfft_init_f32(). + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Manually initialize the instance structure as follows: + 
+      arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+      arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+      arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+
+ where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4; + \c normalize is normalizing factor used and is equal to sqrt(2/N); + \c pTwiddle points to the twiddle factor table; + \c pCosFactor points to the cosFactor table; + \c pRfft points to the real FFT instance; + \c pCfft points to the complex FFT instance; + The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32() + and arm_rfft_f32() respectively for details regarding static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the DCT4 transform functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the floating-point DCT4/IDCT4. + @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure + @param[in] pState points to state buffer + @param[in,out] pInlineBuffer points to the in-place input and output buffer + @return none + */ + +void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer) +{ + const float32_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const float32_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + float32_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + float32_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N); + arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_f32 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ * (float32_t) 0.5; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement the loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_f32 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ * (float32_t) 0.5; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = in * S->normalize; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c new file mode 100644 index 0000000..3fd70e9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_f32.c + * Description: Initialization function of DCT-4 & IDCT4 F32 + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup DCT4_IDCT4 + */ + + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the floating-point DCT4/IDCT4. + @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure + @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure + @param[in] N length of the DCT4 + @param[in] Nby2 half of the length of the DCT4 + @param[in] normalize normalizing factor. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Floating-point normalizing factors are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingF32Table.gif + */ + +arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize) +{ + /* Initialize the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = Weights_8192; + S->pCosFactor = cos_factors_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + case 2048U: + S->pTwiddle = Weights_2048; + S->pCosFactor = cos_factors_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + case 512U: + S->pTwiddle = Weights_512; + S->pCosFactor = cos_factors_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + case 128U: + S->pTwiddle = Weights_128; + S->pCosFactor = cos_factors_128; + break; + #endif + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c new file mode 100644 index 0000000..3c55192 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_q15.c + * Description: Initialization function of DCT-4 & IDCT4 Q15 + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup DCT4_IDCT4 + */ + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the Q15 DCT4/IDCT4. + @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure + @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure + @param[in] N length of the DCT4 + @param[in] Nby2 half of the length of the DCT4 + @param[in] normalize normalizing factor + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingQ15Table.gif + */ + +arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = WeightsQ15_8192; + S->pCosFactor = cos_factorsQ15_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + case 2048U: + S->pTwiddle = WeightsQ15_2048; + S->pCosFactor = cos_factorsQ15_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + case 512U: + S->pTwiddle = WeightsQ15_512; + S->pCosFactor = cos_factorsQ15_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + case 128U: + S->pTwiddle = WeightsQ15_128; + S->pCosFactor = cos_factorsQ15_128; + break; + #endif + + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT */ + arm_rfft_init_q15(S->pRfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c new file mode 100644 index 0000000..f5cc78b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_q31.c + * Description: Initialization function of DCT-4 & IDCT4 Q31 + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup DCT4_IDCT4 + */ + + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the Q31 DCT4/IDCT4. + @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + @param[in] N length of the DCT4. + @param[in] Nby2 half of the length of the DCT4. + @param[in] normalize normalizing factor. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor: + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingQ31Table.gif + */ + +arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize) +{ + /* Initialize the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = WeightsQ31_8192; + S->pCosFactor = cos_factorsQ31_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + case 2048U: + S->pTwiddle = WeightsQ31_2048; + S->pCosFactor = cos_factorsQ31_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + case 512U: + S->pTwiddle = WeightsQ31_512; + S->pCosFactor = cos_factorsQ31_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + case 128U: + S->pTwiddle = WeightsQ31_128; + S->pCosFactor = cos_factorsQ31_128; + break; + #endif + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + arm_rfft_init_q31(S->pRfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c new file mode 100644 index 0000000..f926a1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c @@ -0,0 +1,381 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_q15.c + * Description: Processing function of DCT4 & IDCT4 Q15 + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the Q15 DCT4/IDCT4. + @param[in] S points to an instance of the Q15 DCT4 structure. + @param[in] pState points to state buffer. + @param[in,out] pInlineBuffer points to the in-place input and output buffer. + @return none + + @par Input an output formats + Internally inputs are downscaled in the RFFT process function to avoid overflows. + Number of bits downscaled, depends on the size of the transform. The input and output + formats for different DCT sizes and number of bits to upscale are mentioned in the table below: + + \image html dct4FormatsQ15Table.gif + */ + +void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer) +{ + const q15_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const q15_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + q15_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q15_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_mult_q15 (pInlineBuffer, cosFact, pInlineBuffer, S->N); + arm_shift_q15 (pInlineBuffer, 1, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q15 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q15 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.13 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */ + arm_shift_q15 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q15 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q15 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.13 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */ + arm_shift_q15 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + /* Decrement loop counter */ + i--; + + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c new file mode 100644 index 0000000..369a5c3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c @@ -0,0 +1,383 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_q31.c + * Description: Processing function of DCT4 & IDCT4 Q31 + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the Q31 DCT4/IDCT4. + @param[in] S points to an instance of the Q31 DCT4 structure. + @param[in] pState points to state buffer. + @param[in,out] pInlineBuffer points to the in-place input and output buffer. + @return none + + @par Input an output formats + Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process, + as the conversion from DCT2 to DCT4 involves one subtraction. + Internally inputs are downscaled in the RFFT process function to avoid overflows. + Number of bits downscaled, depends on the size of the transform. + The input and output formats for different DCT sizes and number of bits to upscale are + mentioned in the table below: + + \image html dct4FormatsQ31Table.gif + */ + +void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer) +{ + const q31_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const q31_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + q31_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q31_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_mult_q31 (pInlineBuffer, cosFact, pInlineBuffer, S->N); + arm_shift_q31 (pInlineBuffer, 1, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q31 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q31 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.29 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */ + arm_shift_q31 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q31 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q31 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.29 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */ + arm_shift_q31(pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c new file mode 100644 index 0000000..b5d0a66 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c @@ -0,0 +1,309 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_f32.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +extern void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_split_rfft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier); + +void arm_split_rifft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the floating-point RFFT/RIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_f32 and will be removed in the future. + @param[in] S points to an instance of the floating-point RFFT/RIFFT structure + @param[in] pSrc points to the input buffer + @param[out] pDst points to the output buffer + @return none + */ + +void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst) +{ + const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft; + + /* Calculation of Real IFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + + /* Complex radix-4 IFFT process */ + arm_radix4_butterfly_inverse_f32 (pDst, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier, S_CFFT->onebyfftLen); + + /* Bit reversal process */ + if (S->bitReverseFlagR == 1U) + { + arm_bitreversal_f32 (pDst, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable); + } + } + else + { + /* Calculation of RFFT of input */ + + /* Complex radix-4 FFT process */ + arm_radix4_butterfly_f32 (pSrc, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier); + + /* Bit reversal process */ + if (S->bitReverseFlagR == 1U) + { + arm_bitreversal_f32 (pSrc, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable); + } + + /* Real FFT core process */ + arm_split_rfft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_split_rfft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + float32_t outR, outI; /* Temporary variables for output */ + const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4U * fftLen) - 1U]; /* temp pointers for output buffer */ + float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2U * fftLen) - 1U]; /* temp pointers for input buffer */ + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + i = fftLen - 1U; + + while (i > 0U) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + /* read pATable[2 * i] */ + CoefA1 = *pCoefA++; + /* pATable[2 * i + 1] */ + CoefA2 = *pCoefA; + + /* pSrc[2 * i] * pATable[2 * i] */ + outR = *pSrc1 * CoefA1; + /* pSrc[2 * i] * CoefA2 */ + outI = *pSrc1++ * CoefA2; + + /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */ + outR -= (*pSrc1 + *pSrc2) * CoefA2; + /* pSrc[2 * i + 1] * CoefA1 */ + outI += *pSrc1++ * CoefA1; + + CoefB1 = *pCoefB; + + /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */ + outI -= *pSrc2-- * CoefB1; + /* pSrc[2 * fftLen - 2 * i] * CoefA2 */ + outI -= *pSrc2 * CoefA2; + + /* pSrc[2 * fftLen - 2 * i] * CoefB1 */ + outR += *pSrc2-- * CoefB1; + + /* write output */ + *pDst1++ = outR; + *pDst1++ = outI; + + /* write complex conjugate output */ + *pDst2-- = -outI; + *pDst2-- = outR; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2U); + pCoefA = pCoefA + ((modifier * 2U) - 1U); + + i--; + + } + + pDst[2U * fftLen] = pSrc[0] - pSrc[1]; + pDst[(2U * fftLen) + 1U] = 0.0f; + + pDst[0] = pSrc[0] + pSrc[1]; + pDst[1] = 0.0f; + +} + + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_split_rifft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier) +{ + float32_t outR, outI; /* Temporary variables for output */ + const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2U * fftLen) + 1U]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + while (fftLen > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pSrc[2 * i] * CoefA1 */ + outR = *pSrc1 * CoefA1; + + /* - pSrc[2 * i] * CoefA2 */ + outI = -(*pSrc1++) * CoefA2; + + /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */ + outR += (*pSrc1 + *pSrc2) * CoefA2; + + /* pSrc[2 * i + 1] * CoefA1 */ + outI += (*pSrc1++) * CoefA1; + + CoefB1 = *pCoefB; + + /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */ + outI -= *pSrc2-- * CoefB1; + + /* pSrc[2 * fftLen - 2 * i] * CoefB1 */ + outR += *pSrc2 * CoefB1; + + /* pSrc[2 * fftLen - 2 * i] * CoefA2 */ + outI += *pSrc2-- * CoefA2; + + /* write output */ + *pDst++ = outR; + *pDst++ = outI; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2); + pCoefA = pCoefA + (modifier * 2 - 1); + + /* Decrement loop count */ + fftLen--; + } + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c new file mode 100644 index 0000000..7a1af14 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c @@ -0,0 +1,320 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_f32.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +void stage_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + uint32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b; /* temporary variables */ + float32_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f * ( t1a + t1b ); + *pOut++ = 0.5f * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI + + pA += 2; + pB -= 2; + k--; + } while (k > 0U); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + uint32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f * ( xAR + xAI ); + *pOut++ = 0.5f * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0U) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +/** + @ingroup groupTransforms +*/ + +/** + @defgroup RealFFT Real FFT Functions + + @par + The CMSIS DSP library includes specialized algorithms for computing the + FFT of real data sequences. The FFT is defined over complex data but + in many applications the input is real. Real FFT algorithms take advantage + of the symmetry properties of the FFT and have a speed advantage over complex + algorithms of the same length. + @par + The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage. + @par + The real length N forward FFT of a sequence is computed using the steps shown below. + @par + \image html RFFT.gif "Real Fast Fourier Transform" + @par + The real sequence is initially treated as if it were complex to perform a CFFT. + Later, a processing stage reshapes the data to obtain half of the frequency spectrum + in complex format. Except the first complex number that contains the two real numbers + X[0] and X[N/2] all the data is complex. In other words, the first complex sample + contains two real values packed. + @par + The input for the inverse RFFT should keep the same format as the output of the + forward RFFT. A first processing stage pre-process the data to later perform an + inverse CFFT. + @par + \image html RIFFT.gif "Real Inverse Fast Fourier Transform" + @par + The algorithms for floating-point, Q15, and Q31 data are slightly different + and we describe each algorithm in turn. + @par Floating-point + The main functions are \ref arm_rfft_fast_f32() and \ref arm_rfft_fast_init_f32(). + The older functions \ref arm_rfft_f32() and \ref arm_rfft_init_f32() have been deprecated + but are still documented. + @par + The FFT of a real N-point sequence has even symmetry in the frequency domain. + The second half of the data equals the conjugate of the first half flipped in frequency. + Looking at the data, we see that we can uniquely represent the FFT using only N/2 complex numbers. + These are packed into the output array in alternating real and imaginary components: + @par + X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ... + real[(N/2)-1], imag[(N/2)-1 } + @par + It happens that the first complex number (real[0], imag[0]) is actually + all real. real[0] represents the DC offset, and imag[0] should be 0. + (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is + the first harmonic and so on. + @par + The real FFT functions pack the frequency domain data in this fashion. + The forward transform outputs the data in this form and the inverse + transform expects input data in this form. The function always performs + the needed bitreversal so that the input and output data is always in + normal order. The functions support lengths of [32, 64, 128, ..., 4096] + samples. + @par Q15 and Q31 + The real algorithms are defined in a similar manner and utilize N/2 complex + transforms behind the scenes. + @par + The complex transforms used internally include scaling to prevent fixed-point + overflows. The overall scaling equals 1/(fftLen/2). + @par + A separate instance structure must be defined for each transform used but + twiddle factor and bit reversal tables can be reused. + @par + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes twiddle factor table and bit reversal table pointers. + - Initializes the internal complex FFT data structure. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure + cannot be placed into a const data section. To place an instance structure + into a const data section, the instance structure should be manually + initialized as follows: + 
+      arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+      arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+
+ where fftLenReal is the length of the real transform; + fftLenBy2 length of the internal complex transform. + ifftFlagR Selects forward (=0) or inverse (=1) transform. + bitReverseFlagR Selects bit reversed output (=0) or normal order + output (=1). + twidCoefRModifier stride modifier for the twiddle factor table. + The value is based on the FFT length; + pTwiddleARealpoints to the A array of twiddle coefficients; + pTwiddleBRealpoints to the B array of twiddle coefficients; + pCfft points to the CFFT Instance structure. The CFFT structure + must also be initialized. Refer to arm_cfft_radix4_f32() for details regarding + static initialization of the complex FFT instance structure. + */ + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the floating-point real FFT. + @param[in] S points to an arm_rfft_fast_instance_f32 structure + @param[in] p points to input buffer + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut, + uint8_t ifftFlag) +{ + arm_cfft_instance_f32 * Sint = &(S->Sint); + Sint->fftLen = S->fftLenRFFT / 2; + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f32(S, p, pOut); + + /* Complex radix-4 IFFT process */ + arm_cfft_f32( Sint, pOut, ifftFlag, 1); + } + else + { + /* Calculation of RFFT of input */ + arm_cfft_f32( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f32(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c new file mode 100644 index 0000000..58fbfdb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c @@ -0,0 +1,344 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_f32.c + * Description: Split Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) + +/** + @brief Initialization function for the 32pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_32_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_cfft_instance_f32 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 16U; + S->fftLenRFFT = 32U; + + Sint->bitRevLength = ARMBITREVINDEXTABLE_16_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable16; + Sint->pTwiddle = (float32_t *) twiddleCoef_16; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_32; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) + +/** + @brief Initialization function for the 64pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_64_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_cfft_instance_f32 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 32U; + S->fftLenRFFT = 64U; + + Sint->bitRevLength = ARMBITREVINDEXTABLE_32_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable32; + Sint->pTwiddle = (float32_t *) twiddleCoef_32; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_64; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) + +/** + @brief Initialization function for the 128pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_128_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_cfft_instance_f32 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 64U; + S->fftLenRFFT = 128U; + + Sint->bitRevLength = ARMBITREVINDEXTABLE_64_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable64; + Sint->pTwiddle = (float32_t *) twiddleCoef_64; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_128; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) + +/** + @brief Initialization function for the 256pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected +*/ + +arm_status arm_rfft_256_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_cfft_instance_f32 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 128U; + S->fftLenRFFT = 256U; + + Sint->bitRevLength = ARMBITREVINDEXTABLE_128_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable128; + Sint->pTwiddle = (float32_t *) twiddleCoef_128; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_256; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) + +/** + @brief Initialization function for the 512pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_512_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_cfft_instance_f32 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 256U; + S->fftLenRFFT = 512U; + + Sint->bitRevLength = ARMBITREVINDEXTABLE_256_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable256; + Sint->pTwiddle = (float32_t *) twiddleCoef_256; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_512; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) +/** + @brief Initialization function for the 1024pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_1024_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_cfft_instance_f32 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 512U; + S->fftLenRFFT = 1024U; + + Sint->bitRevLength = ARMBITREVINDEXTABLE_512_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable512; + Sint->pTwiddle = (float32_t *) twiddleCoef_512; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_1024; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) +/** + @brief Initialization function for the 2048pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ +arm_status arm_rfft_2048_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_cfft_instance_f32 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 1024U; + S->fftLenRFFT = 2048U; + + Sint->bitRevLength = ARMBITREVINDEXTABLE_1024_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable1024; + Sint->pTwiddle = (float32_t *) twiddleCoef_1024; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_2048; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) +/** +* @brief Initialization function for the 4096pt floating-point real FFT. +* @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_4096_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_cfft_instance_f32 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 2048U; + S->fftLenRFFT = 4096U; + + Sint->bitRevLength = ARMBITREVINDEXTABLE_2048_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable2048; + Sint->pTwiddle = (float32_t *) twiddleCoef_2048; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_4096; + + return ARM_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_rfft_fast_init_f32( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen) +{ + typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f32 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) + case 4096U: + fptr = arm_rfft_4096_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) + case 2048U: + fptr = arm_rfft_2048_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) + case 1024U: + fptr = arm_rfft_1024_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) + case 512U: + fptr = arm_rfft_512_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) + case 256U: + fptr = arm_rfft_256_fast_init_f32; + break; +#endif +#if (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) + case 128U: + fptr = arm_rfft_128_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) + case 64U: + fptr = arm_rfft_64_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) + case 32U: + fptr = arm_rfft_32_fast_init_f32; + break; +#endif + default: + return ARM_MATH_ARGUMENT_ERROR; + } + + if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c new file mode 100644 index 0000000..141f8b6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_f32.c + * Description: RFFT & RIFFT Floating point initialisation function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the floating-point RFFT/RIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point RFFT/RIFFT structure + @param[in,out] S_CFFT points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLenReal length of the FFT. + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Description + The parameter fftLenRealspecifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 128, 512, 2048. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. + */ + +arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Complex FFT length */ + S->fftLenBy2 = (uint16_t) fftLenReal / 2U; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (float32_t *) realCoefA; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (float32_t *) realCoefB; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLenReal) + { + /* Init table modifier value */ + case 8192U: + S->twidCoefRModifier = 1U; + break; + case 2048U: + S->twidCoefRModifier = 4U; + break; + case 512U: + S->twidCoefRModifier = 16U; + break; + case 128U: + S->twidCoefRModifier = 64U; + break; + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + /* Init Complex FFT Instance */ + S->pCfft = S_CFFT; + + if (S->ifftFlagR) + { + /* Initializes the CIFFT Module for fftLenreal/2 length */ + arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1U, 0U); + } + else + { + /* Initializes the CFFT Module for fftLenreal/2 length */ + arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0U, 0U); + } + + /* return the status of RFFT Init function */ + return (status); + +} + +/** + @} end of RealFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c new file mode 100644 index 0000000..6f90771 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_q15.c + * Description: RFFT & RIFFT Q15 initialisation function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the Q15 RFFT/RIFFT. + @param[in,out] S points to an instance of the Q15 RFFT/RIFFT structure + @param[in] fftLenReal length of the FFT + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Details + The parameter fftLenReal specifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. + */ + +arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (q15_t *) realCoefAQ15; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (q15_t *) realCoefBQ15; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initialization of coef modifier depending on the FFT length */ + switch (S->fftLenReal) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + case 8192U: + S->twidCoefRModifier = 1U; + S->pCfft = &arm_cfft_sR_q15_len4096; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + case 4096U: + S->twidCoefRModifier = 2U; + S->pCfft = &arm_cfft_sR_q15_len2048; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + case 2048U: + S->twidCoefRModifier = 4U; + S->pCfft = &arm_cfft_sR_q15_len1024; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + case 1024U: + S->twidCoefRModifier = 8U; + S->pCfft = &arm_cfft_sR_q15_len512; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 512U: + S->twidCoefRModifier = 16U; + S->pCfft = &arm_cfft_sR_q15_len256; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 256U: + S->twidCoefRModifier = 32U; + S->pCfft = &arm_cfft_sR_q15_len128; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 128U: + S->twidCoefRModifier = 64U; + S->pCfft = &arm_cfft_sR_q15_len64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 64U: + S->twidCoefRModifier = 128U; + S->pCfft = &arm_cfft_sR_q15_len32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 32U: + S->twidCoefRModifier = 256U; + S->pCfft = &arm_cfft_sR_q15_len16; + break; +#endif + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + /* return the status of RFFT Init function */ + return (status); +} + +/** + @} end of RealFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c new file mode 100644 index 0000000..a791c92 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c @@ -0,0 +1,160 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_q31.c + * Description: RFFT & RIFFT Q31 initialisation function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + + + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the Q31 RFFT/RIFFT. + @param[in,out] S points to an instance of the Q31 RFFT/RIFFT structure + @param[in] fftLenReal length of the FFT + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Details + The parameter fftLenReal specifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. +*/ + +arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (q31_t *) realCoefAQ31; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (q31_t *) realCoefBQ31; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initialization of coef modifier depending on the FFT length */ + switch (S->fftLenReal) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + case 8192U: + S->twidCoefRModifier = 1U; + S->pCfft = &arm_cfft_sR_q31_len4096; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + case 4096U: + S->twidCoefRModifier = 2U; + S->pCfft = &arm_cfft_sR_q31_len2048; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + case 2048U: + S->twidCoefRModifier = 4U; + S->pCfft = &arm_cfft_sR_q31_len1024; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + case 1024U: + S->twidCoefRModifier = 8U; + S->pCfft = &arm_cfft_sR_q31_len512; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 512U: + S->twidCoefRModifier = 16U; + S->pCfft = &arm_cfft_sR_q31_len256; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 256U: + S->twidCoefRModifier = 32U; + S->pCfft = &arm_cfft_sR_q31_len128; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 128U: + S->twidCoefRModifier = 64U; + S->pCfft = &arm_cfft_sR_q31_len64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 64U: + S->twidCoefRModifier = 128U; + S->pCfft = &arm_cfft_sR_q31_len32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 32U: + S->twidCoefRModifier = 256U; + S->pCfft = &arm_cfft_sR_q31_len16; + break; +#endif + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + /* return the status of RFFT Init function */ + return (status); +} + +/** + @} end of RealFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c new file mode 100644 index 0000000..fdc9bab --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c @@ -0,0 +1,380 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_q15.c + * Description: RFFT & RIFFT Q15 process function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier); + +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier); + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the Q15 RFFT/RIFFT. + @param[in] S points to an instance of the Q15 RFFT/RIFFT structure + @param[in] pSrc points to input buffer + @param[out] pDst points to output buffer + @return none + + @par Input an output formats + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different RFFT sizes. + The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: + @par + \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT" + @par + \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT" + */ + +void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst) +{ + const arm_cfft_instance_q15 *S_CFFT = S->pCfft; + uint32_t L2 = S->fftLenReal >> 1U; + uint32_t i; + + /* Calculation of RIFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_q15 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + /* Complex IFFT process */ + arm_cfft_q15 (S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR); + + for(i = 0; i < S->fftLenReal; i++) + { + pDst[i] = pDst[i] << 1U; + } + } + else + { + /* Calculation of RFFT of input */ + + /* Complex FFT process */ + arm_cfft_q15 (S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR); + + /* Real FFT core process */ + arm_split_rfft_q15 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + + @par + The function implements a Real FFT + */ + +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pSrc1, *pSrc2; +#if defined (ARM_MATH_DSP) + q15_t *pD1, *pD2; +#endif + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + pSrc1 = &pSrc[2]; + pSrc2 = &pSrc[(2U * fftLen) - 2U]; + +#if defined (ARM_MATH_DSP) + + i = 1U; + pD1 = pDst + 2; + pD2 = pDst + (4U * fftLen) - 2; + + for (i = fftLen - 1; i > 0; i--) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]) + */ + + +#ifndef ARM_MATH_BIG_ENDIAN + /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */ + outR = __SMUSD(read_q15x2 (pSrc1), read_q15x2((q15_t *) pCoefA)); +#else + /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */ + outR = -(__SMUSD(read_q15x2 (pSrc1), read_q15x2((q15_t *) pCoefA))); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* pSrc[2 * n - 2 * i] * pBTable[2 * i] + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */ + outR = __SMLAD(read_q15x2 (pSrc2), read_q15x2((q15_t *) pCoefB), outR) >> 16U; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] - pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ +#ifndef ARM_MATH_BIG_ENDIAN + outI = __SMUSDX(read_q15x2_da (&pSrc2), read_q15x2((q15_t *) pCoefB)); +#else + outI = __SMUSDX(read_q15x2 ((q15_t *) pCoefB), read_q15x2_da (&pSrc2)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */ + outI = __SMLADX(read_q15x2_ia (&pSrc1), read_q15x2 ((q15_t *) pCoefA), outI); + + /* write output */ + *pD1++ = (q15_t) outR; + *pD1++ = outI >> 16U; + + /* write complex conjugate output */ + pD2[0] = (q15_t) outR; + pD2[1] = -(outI >> 16U); + pD2 -= 2; + + /* update coefficient pointer */ + pCoefB = pCoefB + (2U * modifier); + pCoefA = pCoefA + (2U * modifier); + } + + pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2U * fftLen + 1U] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; + +#else + + i = 1U; + + while (i < fftLen) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + */ + + outR = *pSrc1 * *pCoefA; + outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1)); + outR = outR + (*pSrc2 * *pCoefB); + outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 16; + + /* + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + outI = *pSrc2 * *(pCoefB + 1); + outI = outI - (*(pSrc2 + 1) * *pCoefB); + outI = outI + (*(pSrc1 + 1) * *pCoefA); + outI = outI + (*pSrc1 * *(pCoefA + 1)); + + /* update input pointers */ + pSrc1 += 2U; + pSrc2 -= 2U; + + /* write output */ + pDst[2U * i] = (q15_t) outR; + pDst[2U * i + 1U] = outI >> 16U; + + /* write complex conjugate output */ + pDst[(4U * fftLen) - (2U * i)] = (q15_t) outR; + pDst[((4U * fftLen) - (2U * i)) + 1U] = -(outI >> 16U); + + /* update coefficient pointer */ + pCoefB = pCoefB + (2U * modifier); + pCoefA = pCoefA + (2U * modifier); + + i++; + } + + pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1; + pDst[2U * fftLen + 1U] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1; + pDst[1] = 0; + +#endif /* #if defined (ARM_MATH_DSP) */ +} + + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + + @par + The function implements a Real IFFT + */ + +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pSrc1, *pSrc2; + q15_t *pDst1 = &pDst[0]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + pSrc1 = &pSrc[0]; + pSrc2 = &pSrc[2 * fftLen]; + + i = fftLen; + while (i > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + +#if defined (ARM_MATH_DSP) + +#ifndef ARM_MATH_BIG_ENDIAN + /* pIn[2 * n - 2 * i] * pBTable[2 * i] - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */ + outR = __SMUSD(read_q15x2(pSrc2), read_q15x2((q15_t *) pCoefB)); +#else + /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] + pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */ + outR = -(__SMUSD(read_q15x2(pSrc2), read_q15x2((q15_t *) pCoefB))); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] + pIn[2 * n - 2 * i] * pBTable[2 * i] */ + outR = __SMLAD(read_q15x2(pSrc1), read_q15x2 ((q15_t *) pCoefA), outR) >> 16U; + + /* -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + outI = __SMUADX(read_q15x2_da (&pSrc2), read_q15x2((q15_t *) pCoefB)); + + /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */ +#ifndef ARM_MATH_BIG_ENDIAN + outI = __SMLSDX(read_q15x2 ((q15_t *) pCoefA), read_q15x2_ia (&pSrc1), -outI); +#else + outI = __SMLSDX(read_q15x2_ia (&pSrc1), read_q15x2 ((q15_t *) pCoefA), -outI); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* write output */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst1, __PKHBT(outR, (outI >> 16U), 16)); +#else + write_q15x2_ia (&pDst1, __PKHBT((outI >> 16U), outR, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + outR = *pSrc2 * *pCoefB; + outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1)); + outR = outR + (*pSrc1 * *pCoefA); + outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 16; + + outI = *(pSrc1 + 1) * *pCoefA; + outI = outI - (*pSrc1 * *(pCoefA + 1)); + outI = outI - (*pSrc2 * *(pCoefB + 1)); + outI = outI - (*(pSrc2 + 1) * *(pCoefB)); + + /* update input pointers */ + pSrc1 += 2U; + pSrc2 -= 2U; + + /* write output */ + *pDst1++ = (q15_t) outR; + *pDst1++ = (q15_t) (outI >> 16); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* update coefficient pointer */ + pCoefB = pCoefB + (2 * modifier); + pCoefA = pCoefA + (2 * modifier); + + i--; + } + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c new file mode 100644 index 0000000..d16600d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c @@ -0,0 +1,292 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_q31.c + * Description: FFT & RIFFT Q31 process function + * + * $Date: 18. March 2019 + * $Revision: V1.6.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +void arm_split_rfft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier); + +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier); + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the Q31 RFFT/RIFFT. + @param[in] S points to an instance of the Q31 RFFT/RIFFT structure + @param[in] pSrc points to input buffer + @param[out] pDst points to output buffer + @return none + + @par Input an output formats + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different RFFT sizes. + The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: + @par + \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT" + @par + \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT" + */ + +void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst) +{ + const arm_cfft_instance_q31 *S_CFFT = S->pCfft; + uint32_t L2 = S->fftLenReal >> 1U; + uint32_t i; + + /* Calculation of RIFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_q31 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + /* Complex IFFT process */ + arm_cfft_q31 (S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR); + + for(i = 0; i < S->fftLenReal; i++) + { + pDst[i] = pDst[i] << 1U; + } + } + else + { + /* Calculation of RFFT of input */ + + /* Complex FFT process */ + arm_cfft_q31 (S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR); + + /* Real FFT core process */ + arm_split_rfft_q31 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_split_rfft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[4 * fftLen - 1]; + q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[2 * fftLen - 1]; + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + i = fftLen - 1U; + + while (i > 0U) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pSrc[2 * i] * pATable[2 * i] */ + mult_32x32_keep32_R (outR, *pIn1, CoefA1); + + /* outI = pIn[2 * i] * pATable[2 * i + 1] */ + mult_32x32_keep32_R (outI, *pIn1++, CoefA2); + + /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */ + multSub_32x32_keep32_R (outR, *pIn1, CoefA2); + + /* (pIn[2 * i + 1] * pATable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn1++, CoefA1); + + /* pSrc[2 * n - 2 * i] * pBTable[2 * i] */ + multSub_32x32_keep32_R (outR, *pIn2, CoefA2); + CoefB1 = *pCoefB; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefB1); + + /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefA2); + + /* write output */ + *pOut1++ = outR; + *pOut1++ = outI; + + /* write complex conjugate output */ + *pOut2-- = -outI; + *pOut2-- = outR; + + /* update coefficient pointer */ + pCoefB = pCoefB + (2 * modifier); + pCoefA = pCoefA + (2 * modifier - 1); + + /* Decrement loop count */ + i--; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} + + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + q31_t outR, outI; /* Temporary variables for output */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[2 * fftLen + 1]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + while (fftLen > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pIn[2 * i] * pATable[2 * i] */ + mult_32x32_keep32_R (outR, *pIn1, CoefA1); + + /* - pIn[2 * i] * pATable[2 * i + 1] */ + mult_32x32_keep32_R (outI, *pIn1++, -CoefA2); + + /* pIn[2 * i + 1] * pATable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn1, CoefA2); + + /* pIn[2 * i + 1] * pATable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn1++, CoefA1); + + /* pIn[2 * n - 2 * i] * pBTable[2 * i] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefA2); + CoefB1 = *pCoefB; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn2--, CoefA2); + + /* write output */ + *pDst++ = outR; + *pDst++ = outI; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2); + pCoefA = pCoefA + (modifier * 2 - 1); + + /* Decrement loop count */ + fftLen--; + } + +} diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h b/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h new file mode 100644 index 0000000..de1ce94 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h @@ -0,0 +1,24445 @@ +/** + ****************************************************************************** + * @file stm32h723xx.h + * @author MCD Application Team + * @brief CMSIS STM32H723xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h723xx + * @{ + */ + +#ifndef STM32H723xx_H +#define STM32H723xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + __IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2_DIFSEL; /*!< ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0 */ + __IO uint32_t HTR2_CALFACT; /*!< ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 */ + __IO uint32_t LTR3_RES10; /*!< ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset: 0xB8 */ + __IO uint32_t HTR3_RES11; /*!< ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset: 0xBC */ + __IO uint32_t DIFSEL_RES12; /*!< ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0 */ + __IO uint32_t CALFACT_RES13; /*!< ADC Calibration Factors specific ADC1/2, Address offset: 0xC4 */ + __IO uint32_t CALFACT2_RES14; /*!< ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief COordincate Rotation DIgital Computer + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t RESERVED9[990]; /*!< Reserved, Address offset: 0x58-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t RESERVED10[3];/*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ + __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED[3]; /*!< Reserved, 0x64 to 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< Flash Option Status Current Register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< Flash Option Status to Program Register 2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief Filter and Mathematical ACcelerator + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t ADC2ALT; /*!< ADC2 internal input alternate connection register, Address offset: 0x30 */ + uint32_t RESERVED4[60]; /*!< Reserved, 0x34-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED5[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x320-0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + __IO uint32_t UR18; /*!< SYSCFG user register 18, Address offset: 0x348 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} +DTS_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */ + __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */ +} OCTOSPI_TypeDef; + +/** + * @} + */ +/** + * @brief OCTO Serial Peripheral Interface IO Manager + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ +} OCTOSPIM_TypeDef; + +/** + * @} + */ + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */ + __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */ + uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */ + __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */ + uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */ + __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */ + uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 128KB) system data RAM1 accessible over over AXI */ +#define D1_AXISRAM2_BASE (0x24020000UL) /*!< Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity) */ +#define D1_AXISRAM_BASE D1_AXISRAM1_BASE /*!< Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI */ + +#define D2_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM2_BASE (0x30004000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_END (0x080FFFFFUL) /*!< FLASH end address */ + + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) +#define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL) +#define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL) +#define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) +#define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL) +#define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) +#define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL) +#define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL) +#define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL) +#define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + +#define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL) + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) +#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define USART10 ((USART_TypeDef *) USART10_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UART9 ((USART_TypeDef *) UART9_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define I2C5 ((I2C_TypeDef *) I2C5_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define TIM23 ((TIM_TypeDef *) TIM23_BASE) +#define TIM24 ((TIM_TypeDef *) TIM24_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) +#define RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + +#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE) +#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE) +#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE) +#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE) +#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE) + +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_V90 +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +#define ADC3_CFGR_DMAEN_Pos (0U) +#define ADC3_CFGR_DMAEN_Msk (0x1UL << ADC3_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC3_CFGR_DMAEN ADC3_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC3_CFGR_DMACFG_Pos (1U) +#define ADC3_CFGR_DMACFG_Msk (0x1UL << ADC3_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC3_CFGR_DMACFG ADC3_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC3_CFGR_RES_Pos (3U) +#define ADC3_CFGR_RES_Msk (0x3UL << ADC3_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC3_CFGR_RES ADC3_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC3_CFGR_RES_0 (0x1UL << ADC3_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR_RES_1 (0x2UL << ADC3_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR_ALIGN_Pos (15U) +#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */ +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +#define ADC3_CFGR2_OVSR_Pos (2U) +#define ADC3_CFGR2_OVSR_Msk (0x7UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC3_CFGR2_OVSR ADC3_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC3_CFGR2_OVSR_0 (0x1UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC3_CFGR2_OVSR_1 (0x2UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR2_OVSR_2 (0x4UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR2_SWTRIG_Pos (25U) +#define ADC3_CFGR2_SWTRIG_Msk (0x1UL << ADC3_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC3_CFGR2_SWTRIG ADC3_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC3_CFGR2_BULB_Pos (26U) +#define ADC3_CFGR2_BULB_Msk (0x1UL << ADC3_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC3_CFGR2_BULB ADC3_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC3_CFGR2_SMPTRIG_Pos (27U) +#define ADC3_CFGR2_SMPTRIG_Msk (0x1UL << ADC3_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC3_CFGR2_SMPTRIG ADC3_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +/******************** Bit definition for ADC3_TR1 register *******************/ +#define ADC3_TR1_LT1_Pos (0U) +#define ADC3_TR1_LT1_Msk (0xFFFUL << ADC3_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC3_TR1_LT1 ADC3_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC3_TR1_AWDFILT_Pos (12U) +#define ADC3_TR1_AWDFILT_Msk (0x7UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC3_TR1_AWDFILT ADC3_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC3_TR1_AWDFILT_0 (0x1UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC3_TR1_AWDFILT_1 (0x2UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC3_TR1_AWDFILT_2 (0x4UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC3_TR1_HT1_Pos (16U) +#define ADC3_TR1_HT1_Msk (0xFFFUL << ADC3_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC3_TR1_HT1 ADC3_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC3_TR2 register *******************/ +#define ADC3_TR2_LT2_Pos (0U) +#define ADC3_TR2_LT2_Msk (0xFFUL << ADC3_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC3_TR2_LT2 ADC3_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC3_TR2_HT2_Pos (16U) +#define ADC3_TR2_HT2_Msk (0xFFUL << ADC3_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR2_HT2 ADC3_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC3_TR3 register *******************/ +#define ADC3_TR3_LT3_Pos (0U) +#define ADC3_TR3_LT3_Msk (0xFFUL << ADC3_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC3_TR3_LT3 ADC3_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC3_TR3_HT3_Pos (16U) +#define ADC3_TR3_HT3_Msk (0xFFUL << ADC3_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR3_HT3 ADC3_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR1_OFFSET1_Pos (0U) +#define ADC3_OFR1_OFFSET1_Msk (0xFFFUL << ADC3_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR1_OFFSET1 ADC3_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR1_OFFSETPOS_Pos (24U) +#define ADC3_OFR1_OFFSETPOS_Msk (0x1UL << ADC3_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR1_OFFSETPOS ADC3_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC3_OFR1_SATEN_Pos (25U) +#define ADC3_OFR1_SATEN_Msk (0x1UL << ADC3_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR1_SATEN ADC3_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC3_OFR1_OFFSET1_EN_Pos (31U) +#define ADC3_OFR1_OFFSET1_EN_Msk (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR1_OFFSET1_EN ADC3_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR2_OFFSET2_Pos (0U) +#define ADC3_OFR2_OFFSET2_Msk (0xFFFUL << ADC3_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR2_OFFSET2 ADC3_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR2_OFFSETPOS_Pos (24U) +#define ADC3_OFR2_OFFSETPOS_Msk (0x1UL << ADC3_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR2_OFFSETPOS ADC3_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC3_OFR2_SATEN_Pos (25U) +#define ADC3_OFR2_SATEN_Msk (0x1UL << ADC3_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR2_SATEN ADC3_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC3_OFR2_OFFSET2_EN_Pos (31U) +#define ADC3_OFR2_OFFSET2_EN_Msk (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR2_OFFSET2_EN ADC3_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR3_OFFSET3_Pos (0U) +#define ADC3_OFR3_OFFSET3_Msk (0xFFFUL << ADC3_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR3_OFFSET3 ADC3_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR3_OFFSETPOS_Pos (24U) +#define ADC3_OFR3_OFFSETPOS_Msk (0x1UL << ADC3_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR3_OFFSETPOS ADC3_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC3_OFR3_SATEN_Pos (25U) +#define ADC3_OFR3_SATEN_Msk (0x1UL << ADC3_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR3_SATEN ADC3_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC3_OFR3_OFFSET3_EN_Pos (31U) +#define ADC3_OFR3_OFFSET3_EN_Msk (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR3_OFFSET3_EN ADC3_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR4_OFFSET4_Pos (0U) +#define ADC3_OFR4_OFFSET4_Msk (0xFFFUL << ADC3_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR4_OFFSET4 ADC3_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR4_OFFSETPOS_Pos (24U) +#define ADC3_OFR4_OFFSETPOS_Msk (0x1UL << ADC3_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR4_OFFSETPOS ADC3_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC3_OFR4_SATEN_Pos (25U) +#define ADC3_OFR4_SATEN_Msk (0x1UL << ADC3_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR4_SATEN ADC3_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC3_OFR4_OFFSET4_EN_Pos (31U) +#define ADC3_OFR4_OFFSET4_EN_Msk (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR4_OFFSET4_EN ADC3_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +#define ADC3_AWD2CR_AWD2CH_Pos (0U) +#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +#define ADC3_AWD3CR_AWD3CH_Pos (0U) +#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..e917f35 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/Drivers/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..feec324 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..3ddcc58 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..12d68fd --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..f2e2746 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Include/core_armv81mml.h b/Drivers/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000..8441e57 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..344dca5 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..5ddb8ae --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..cafae5a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..d104965 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..b79c6af --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..8157ca7 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..7fed59a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm35p.h b/Drivers/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000..5579c82 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..12c023b --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..c4515d8 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..cf92577 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..40f3af8 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..66ef59b --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..0041d4d --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/CMSIS/LICENSE.txt b/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 0000000..8dada3e --- /dev/null +++ b/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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All rights reserved. + *------------------------------------------------------------------------------ + * Name: EventRecorderConf.h + * Purpose: Event Recorder Configuration + * Rev.: V1.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288 +// <1048576=>1048576 +// Configure size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=1048576) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 1 + +// SysTick Configuration +// Configure values when Time Stamp Source is set to SysTick + +// SysTick Input Clock Frequency [Hz] <1-1000000000> +// Defines SysTick input clock (typical identical with processor clock) +#define SYSTICK_CLOCK 100000000U + +// SysTick Interrupt Period [us] <1-1000000000> +// Defines time period of the SysTick timer interrupt +#define SYSTICK_PERIOD_US 1000U + +// + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..9fc447d --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,242 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66829ad --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..16e56b0 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f08df7a --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..dae6439 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..070fa1e --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..26edb9f --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,295 @@ +/**************************************************************************//** + * @file startup_ARMCM7.s + * @brief CMSIS Core Device Startup File for + * ARMCM7 Device Series + * @version V5.00 + * @date 26. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __etext; +extern uint32_t __data_start__; +extern uint32_t __data_end__; +extern uint32_t __copy_table_start__; +extern uint32_t __copy_table_end__; +extern uint32_t __zero_table_start__; +extern uint32_t __zero_table_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __StackTop; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +#ifndef __START +extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ +#else +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +#endif + +#ifndef __NO_SYSTEM_INIT +extern void SystemInit (void); /* CMSIS System Initialization */ +#endif + + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void); /* Default empty handler */ +void Reset_Handler(void); /* Reset Handler */ + + +/*---------------------------------------------------------------------------- + User Initial Stack & Heap + *----------------------------------------------------------------------------*/ +#ifndef __STACK_SIZE + #define __STACK_SIZE 0x00000400 +#endif +static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); + +#ifndef __HEAP_SIZE + #define __HEAP_SIZE 0x00000C00 +#endif +#if __HEAP_SIZE > 0 +static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Cortex-M7 Processor Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* ARMCM7 Specific Interrupts */ +void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = { + /* Cortex-M7 Exceptions Handler */ + (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + /* External interrupts */ + WDT_IRQHandler, /* 0: Watchdog Timer */ + RTC_IRQHandler, /* 1: Real Time Clock */ + TIM0_IRQHandler, /* 2: Timer0 / Timer1 */ + TIM2_IRQHandler, /* 3: Timer2 / Timer3 */ + MCIA_IRQHandler, /* 4: MCIa */ + MCIB_IRQHandler, /* 5: MCIb */ + UART0_IRQHandler, /* 6: UART0 - DUT FPGA */ + UART1_IRQHandler, /* 7: UART1 - DUT FPGA */ + UART2_IRQHandler, /* 8: UART2 - DUT FPGA */ + UART4_IRQHandler, /* 9: UART4 - not connected */ + AACI_IRQHandler, /* 10: AACI / AC97 */ + CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */ + ENET_IRQHandler, /* 12: Ethernet */ + USBDC_IRQHandler, /* 13: USB Device */ + USBHC_IRQHandler, /* 14: USB Host Controller */ + CHLCD_IRQHandler, /* 15: Character LCD */ + FLEXRAY_IRQHandler, /* 16: Flexray */ + CAN_IRQHandler, /* 17: CAN */ + LIN_IRQHandler, /* 18: LIN */ + I2C_IRQHandler, /* 19: I2C ADC/DAC */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + 0, /* 27: Reserved */ + CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */ + 0, /* 29: Reserved - CPU FPGA */ + UART3_IRQHandler, /* 30: UART3 - CPU FPGA */ + SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ +}; + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) { + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + pTable = &__copy_table_start__; + + for (; pTable < &__copy_table_end__; pTable = pTable + 3) { + pSrc = (uint32_t*)*(pTable + 0); + pDest = (uint32_t*)*(pTable + 1); + for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { + *pDest++ = *pSrc++; + } + } +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + pSrc = &__etext; + pDest = &__data_start__; + + for ( ; pDest < &__data_end__ ; ) { + *pDest++ = *pSrc++; + } +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + pTable = &__zero_table_start__; + + for (; pTable < &__zero_table_end__; pTable = pTable + 2) { + pDest = (uint32_t*)*(pTable + 0); + for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { + *pDest++ = 0; + } + } +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for ( ; pDest < &__bss_end__ ; ) { + *pDest++ = 0UL; + } +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + SystemInit(); +#endif + +#ifndef __START +#define __START _start +#endif + __START(); + +} + + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + + while(1); +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..b69f038 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..65bfaca --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h new file mode 100644 index 0000000..0c062ad --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + +#define RTE_Compiler_EventRecorder + #define RTE_Compiler_EventRecorder_DAP +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h new file mode 100644 index 0000000..62755a7 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM3.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h new file mode 100644 index 0000000..835cb37 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h new file mode 100644 index 0000000..d275f41 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM7_SP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp new file mode 100644 index 0000000..471899c --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_cifar10.cpp +* +* Description: Convolutional Neural Network Example +* +* Target Processor: Cortex-M4/Cortex-M7 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of Arm LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup CNNExample Convolutional Neural Network Example + * + * \par Description: + * \par + * Demonstrates a convolutional neural network (CNN) example with the use of convolution, + * ReLU activation, pooling and fully-connected functions. + * + * \par Model definition: + * \par + * The CNN used in this example is based on CIFAR-10 example from Caffe [1]. + * The neural network consists + * of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a + * fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will + * be classified into one of the 10 output classes. + * This example model implementation needs 32.3 KB to store weights, 40 KB for activations and + * 3.1 KB for storing the \c im2col data. + * + * \image html CIFAR10_CNN.gif "Neural Network model definition" + * + * \par Variables Description: + * \par + * \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices + * \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays + * \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases + * \li \c input_data points to the input image data + * \li \c output_data points to the classification output + * \li \c col_buffer is a buffer to store the \c im2col output + * \li \c scratch_buffer is used to store the activation data (intermediate layer outputs) + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_convolve_HWC_q7_RGB() + * - arm_convolve_HWC_q7_fast() + * - arm_relu_q7() + * - arm_maxpool_q7_HWC() + * - arm_avepool_q7_HWC() + * - arm_fully_connected_q7_opt() + * - arm_fully_connected_q7() + * + * Refer + * \link arm_nnexamples_cifar10.cpp \endlink + * + * \par [1] https://github.com/BVLC/caffe + */ + +#include +#include +#include "arm_math.h" +#include "arm_nnexamples_cifar10_parameter.h" +#include "arm_nnexamples_cifar10_weights.h" + +#include "arm_nnfunctions.h" +#include "arm_nnexamples_cifar10_inputs.h" + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif +#endif + +// include the input and weights + +static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT; +static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS; + +static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT; +static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS; + +static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT; +static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS; + +static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT; +static q7_t ip1_bias[IP1_OUT] = IP1_BIAS; + +/* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */ +uint8_t image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA; +q7_t output_data[IP1_OUT]; + +//vector buffer: max(im2col buffer,average pool buffer, fully connected buffer) +q7_t col_buffer[2 * 5 * 5 * 32 * 2]; + +q7_t scratch_buffer[32 * 32 * 10 * 4]; + +int main() +{ + #ifdef RTE_Compiler_EventRecorder + EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder + #endif + + printf("start execution\n"); + /* start the execution */ + + q7_t *img_buffer1 = scratch_buffer; + q7_t *img_buffer2 = img_buffer1 + 32 * 32 * 32; + + /* input pre-processing */ + int mean_data[3] = INPUT_MEAN_SHIFT; + unsigned int scale_data[3] = INPUT_RIGHT_SHIFT; + for (int i=0;i<32*32*3; i+=3) { + img_buffer2[i] = (q7_t)__SSAT( ((((int)image_data[i] - mean_data[0])<<7) + (0x1<<(scale_data[0]-1))) + >> scale_data[0], 8); + img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1))) + >> scale_data[1], 8); + img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1))) + >> scale_data[2], 8); + } + + // conv1 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING, + CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM, + (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH); + + // pool1 img_buffer1 -> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM, + POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2); + + // conv2 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM, + CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1, + CONV2_OUT_DIM, (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH); + + // pool2 img_buffer1 -> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM, + POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2); + +// conv3 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM, + CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1, + CONV3_OUT_DIM, (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH); + + // pool3 img_buffer-> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM, + POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2); + + arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias, + output_data, (q15_t *) img_buffer1); + + arm_softmax_q7(output_data, 10, output_data); + + for (int i = 0; i < 10; i++) + { + printf("%d: %d\n", i, output_data[i]); + } + + return 0; +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h new file mode 100644 index 0000000..c600c5a --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h @@ -0,0 +1,6 @@ +/* Here are two different test images */ + +//#define IMG_DATA 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3,71,107,133,49,89,114,31,77,105,27,71,105,38,82,117,49,93,128,56,100,135,58,102,137,53,92,128,56,94,131,60,99,137,57,99,139,53,97,138,50,95,137,45,94,136,39,88,131,33,83,125,42,91,133,62,112,154,79,132,179,73,131,181,56,116,168,38,97,146,13,64,108,40,85,127,61,116,168,49,102,148,35,85,132,43,91,143,39,90,139,42,92,134,44,88,125,40,81,112,42,85,115,27,72,104,23,67,102,30,74,109,27,71,106,29,73,108,36,80,115,47,86,120,56,95,128,62,101,135,66,109,144,75,119,156,69,113,152,49,95,134,43,88,127,43,88,127,60,105,144,85,130,170,109,156,197,93,145,190,60,115,164,26,82,130,29,82,126,20,64,107,54,107,160,56,105,149,45,89,132,43,86,134,40,89,134,40,92,132,40,87,123,38,81,115,36,79,114,26,69,105,22,66,101,29,73,108,25,69,104,29,73,108,19,63,98,18,58,89,32,70,100,47,87,118,61,104,137,74,119,152,66,111,145,53,96,131,52,95,130,45,87,123,67,109,145,89,131,167,105,146,182,89,135,175,48,99,145,24,77,124,34,84,129,21,67,110} + + +#define IMG_DATA {235,235,235,231,231,231,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,232,233,233,231,233,232,231,233,231,233,233,230,233,232,232,232,234,232,231,234,232,232,232,233,233,230,232,233,231,233,233,233,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,232,232,232,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,237,234,233,236,234,233,236,236,234,234,236,234,234,235,237,234,234,238,235,236,237,236,236,235,236,236,234,236,236,236,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,235,235,235,237,237,237,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,234,234,236,233,231,236,234,231,235,235,234,234,235,236,227,230,233,231,235,238,231,233,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,234,233,233,230,232,232,231,228,230,232,223,226,231,186,192,197,209,216,219,207,210,213,228,228,230,236,235,235,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,237,237,237,234,234,234,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,236,238,236,233,237,237,219,225,230,203,210,219,163,172,179,195,205,208,214,218,221,230,229,232,237,235,237,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,239,239,238,236,235,235,236,235,235,236,235,235,236,235,235,236,235,235,235,236,235,235,235,235,234,234,234,235,235,235,237,236,236,237,236,236,234,235,236,232,233,234,235,237,237,229,231,232,208,216,218,194,205,210,185,198,207,174,188,200,165,179,189,184,196,202,207,215,220,226,228,232,236,235,237,236,236,235,236,236,235,236,236,235,236,236,236,237,237,237,237,237,237,237,237,237,228,229,229,228,227,228,232,230,231,231,228,230,234,232,233,237,236,236,237,237,235,236,237,235,237,235,236,237,235,236,239,236,237,239,237,238,225,229,230,224,228,229,233,237,238,221,226,228,183,197,204,161,180,190,159,180,191,154,176,190,144,163,177,143,159,171,156,169,177,198,206,211,233,238,239,236,237,234,235,236,233,235,235,235,235,236,236,236,238,237,237,237,237,239,237,238,212,220,222,224,230,233,230,234,238,227,232,234,229,234,234,234,237,236,237,238,235,238,237,236,239,237,238,239,237,238,239,236,237,240,238,239,201,204,203,219,222,221,233,236,235,214,218,218,193,204,210,185,201,210,184,201,211,173,191,203,165,182,196,159,174,187,162,176,185,186,199,204,229,239,240,234,239,238,233,238,237,233,238,238,234,239,238,236,239,238,237,239,238,238,238,238,216,234,241,221,236,243,225,238,246,225,239,243,227,240,240,231,238,237,236,237,235,238,236,235,238,236,237,238,236,237,237,237,237,239,239,239,197,198,196,220,221,218,233,234,231,230,231,229,209,213,217,209,216,222,219,228,235,208,218,227,209,221,234,210,224,235,217,233,240,218,235,241,225,240,243,228,238,240,228,239,240,230,240,240,230,240,239,235,240,239,237,240,239,238,238,238,118,140,149,119,138,148,124,142,153,136,155,161,172,188,191,225,234,233,235,236,233,237,234,232,236,233,234,235,235,235,235,237,236,233,237,235,214,216,214,226,228,226,232,234,232,236,237,236,228,230,232,227,230,235,231,236,241,225,232,239,225,237,247,217,233,243,201,219,226,185,204,211,172,189,195,167,179,186,167,180,185,186,199,201,223,235,235,235,241,239,236,240,239,238,240,239,109,130,141,103,121,133,108,125,137,111,127,137,146,159,165,222,229,231,227,228,225,229,226,224,236,232,233,234,234,234,231,236,234,230,237,235,229,234,235,231,235,236,232,237,238,230,235,236,231,236,238,231,237,240,229,237,241,223,232,238,191,206,213,164,184,191,146,165,172,137,156,163,134,149,159,128,140,153,121,133,143,149,162,166,216,228,229,234,241,239,235,240,238,237,240,239,195,212,224,188,202,215,199,211,224,200,211,223,209,217,227,223,227,231,213,213,211,211,209,206,216,213,214,220,222,222,219,226,225,210,221,219,209,219,223,211,221,225,216,225,230,220,229,233,225,234,237,226,236,239,225,237,241,218,231,237,183,204,208,175,198,203,181,200,207,178,194,202,186,197,211,170,178,196,142,151,164,185,195,202,219,230,233,231,240,238,234,241,239,236,240,239,193,207,222,191,202,217,202,211,224,214,217,234,223,225,241,214,219,227,203,208,208,171,174,174,177,180,183,207,213,214,174,184,188,98,112,121,93,114,126,101,121,132,111,129,139,122,138,147,137,152,161,153,167,174,202,216,220,223,236,237,218,232,235,220,233,238,223,234,240,217,226,233,221,228,237,212,219,229,196,203,212,222,230,237,219,227,234,221,230,233,232,239,242,235,241,242,113,130,152,111,125,147,113,125,141,125,131,151,138,145,165,170,182,193,191,201,205,190,199,204,208,219,226,216,230,234,158,172,183,54,71,92,45,70,91,49,73,91,53,73,90,66,84,98,102,114,129,159,168,179,221,227,233,234,239,241,233,237,241,227,231,237,223,228,233,207,211,217,202,208,212,211,218,220,212,219,223,199,206,214,179,186,196,188,197,205,211,221,227,221,231,234,61,81,108,69,86,114,63,79,100,68,85,102,123,141,155,139,155,164,151,157,164,195,200,207,214,228,234,206,223,228,163,180,190,103,121,138,95,112,131,101,117,135,138,151,168,181,192,207,207,212,223,221,222,232,219,219,227,205,203,212,183,186,195,158,166,174,147,154,163,131,138,147,125,133,140,130,139,144,136,146,152,133,142,151,128,137,147,138,153,160,182,197,203,197,212,216,40,53,77,58,70,94,85,98,116,127,144,153,132,151,156,96,107,110,119,115,118,163,158,161,173,180,182,184,194,197,182,194,198,181,193,200,183,194,202,198,209,217,218,228,236,200,210,217,174,181,186,159,165,172,145,150,159,132,136,149,116,125,138,98,111,123,94,106,118,99,111,123,105,118,128,107,121,130,122,135,145,138,151,161,150,164,174,157,174,184,188,206,213,185,203,208,13,15,35,26,29,47,134,140,151,206,216,220,138,150,150,118,123,123,141,133,134,172,162,162,181,181,180,207,209,211,220,224,225,228,234,233,224,234,232,230,241,240,226,238,238,176,189,190,144,159,163,138,154,162,142,158,170,145,163,177,154,171,187,149,165,182,149,165,182,154,171,187,157,174,189,160,177,191,173,190,204,187,204,217,190,207,218,178,196,208,165,183,193,157,175,183,5,5,24,58,62,79,200,207,217,225,232,239,197,205,212,199,207,211,212,212,218,226,224,229,229,230,237,233,236,246,232,238,245,230,238,239,209,221,220,223,238,239,221,238,241,210,228,234,198,217,228,180,200,214,193,216,230,188,213,229,189,212,231,194,214,234,192,212,232,184,204,224,172,193,212,171,191,209,161,181,197,144,165,179,136,156,169,131,146,161,128,143,158,138,154,165,39,45,71,145,155,179,190,204,222,186,196,216,184,197,217,192,211,229,194,211,230,194,208,227,194,206,227,191,203,228,192,207,228,190,207,221,177,193,207,180,198,215,154,176,193,147,169,188,145,161,184,156,171,195,146,163,186,113,133,156,114,137,161,132,157,180,126,150,173,111,135,158,92,115,138,91,112,135,93,114,133,94,116,131,105,125,140,121,133,151,129,141,158,129,142,156,122,135,161,162,179,207,143,160,194,137,154,189,131,152,187,128,152,190,127,150,192,130,150,193,131,150,192,128,147,190,127,147,189,129,149,189,129,149,188,124,145,186,104,126,163,100,122,154,102,120,154,118,134,170,112,128,163,94,109,145,94,112,148,94,117,153,87,112,144,83,103,136,80,97,130,83,103,134,93,111,139,101,117,141,108,121,144,115,125,146,121,133,148,130,144,156,73,87,109,76,90,113,77,90,122,80,93,127,84,98,134,87,102,142,87,102,147,90,105,150,94,111,152,102,119,160,107,124,165,113,131,172,115,137,181,118,136,186,118,132,180,120,133,175,115,136,172,110,133,168,106,127,163,100,119,155,95,109,148,85,101,139,79,97,132,80,92,127,80,94,129,77,100,133,80,100,129,82,98,122,92,104,126,113,119,138,125,135,146,136,149,156,13,25,41,3,11,25,9,16,35,18,26,48,18,26,52,21,25,56,20,25,58,22,30,61,26,36,62,34,43,70,42,51,77,48,59,87,52,69,106,60,75,121,66,77,126,70,79,126,71,87,127,72,88,126,67,81,120,60,72,112,55,67,106,53,68,104,53,69,103,57,69,102,57,71,105,57,78,110,72,89,115,87,100,119,104,113,128,120,124,136,130,136,141,137,146,149,36,46,55,11,16,20,8,13,19,32,44,53,36,45,58,22,25,41,8,11,30,3,8,24,1,4,17,0,2,15,0,2,15,0,4,20,6,13,42,5,18,56,1,19,60,3,23,62,13,29,71,24,38,81,21,33,77,21,31,76,21,38,78,22,44,79,30,50,83,39,58,90,57,70,101,85,90,118,113,115,138,123,123,138,116,115,125,122,123,128,134,139,137,153,160,158,35,41,45,26,27,26,13,19,18,27,41,41,71,81,84,70,70,76,49,50,57,27,31,37,15,15,21,5,5,11,2,2,7,0,0,7,17,17,35,57,64,91,31,50,78,10,36,62,4,30,60,4,30,62,7,30,63,14,35,69,25,43,74,41,55,83,62,71,99,86,97,123,122,124,146,144,131,149,132,120,135,114,105,114,117,111,116,132,134,133,146,152,146,172,179,175,16,15,17,13,10,9,4,10,8,3,12,11,45,44,46,65,52,57,54,43,47,36,33,35,18,18,20,4,4,7,2,2,4,0,1,3,7,8,15,118,117,134,161,158,179,131,128,148,112,112,131,105,105,125,105,103,124,109,105,127,118,107,126,138,115,133,154,126,144,151,126,141,127,106,116,105,86,91,106,94,97,120,116,116,129,130,129,142,147,144,164,172,165,184,194,190,40,40,35,12,10,7,0,3,3,0,4,4,12,6,7,30,12,17,32,12,17,21,10,12,7,6,7,2,1,3,2,1,2,3,2,3,0,0,2,68,58,64,182,128,146,205,130,148,196,127,144,194,123,141,195,119,137,187,113,129,172,110,122,150,96,106,123,75,83,103,66,69,95,71,70,104,93,88,122,118,113,129,132,126,132,141,135,152,162,158,171,182,176,185,197,194,69,77,64,26,29,21,1,1,1,1,1,2,4,1,0,12,2,5,18,3,9,12,2,5,4,1,2,2,0,0,2,0,0,4,0,1,1,1,1,32,12,11,153,45,59,203,47,68,195,46,67,191,48,69,179,50,67,155,49,59,119,42,49,91,38,42,81,48,46,94,77,71,117,110,102,125,126,116,125,128,120,129,135,128,144,153,147,162,176,171,173,187,183,184,198,196,83,94,82,47,52,43,1,1,1,2,1,2,2,0,0,5,1,2,7,1,5,4,0,2,1,0,0,1,0,0,1,0,0,3,0,0,1,2,0,27,3,2,142,25,38,205,32,54,198,25,46,169,25,43,121,25,36,85,29,34,74,41,39,85,66,56,102,92,82,121,113,105,128,124,115,122,126,115,121,127,118,132,139,131,147,157,150,165,179,174,176,191,187,186,201,199,92,102,93,54,60,50,6,7,3,3,2,1,2,2,0,1,3,1,1,3,3,1,2,2,1,1,1,1,0,0,1,0,0,1,1,1,0,3,2,15,1,0,102,19,28,157,31,47,117,17,23,74,13,12,56,27,22,74,58,55,99,90,81,115,115,99,122,126,111,124,124,112,123,123,113,125,130,119,128,135,126,136,145,137,148,159,151,162,176,171,177,192,188,188,202,201,87,99,89,43,51,37,19,23,11,11,12,4,8,10,2,5,11,4,2,10,4,2,7,2,3,4,1,3,4,1,3,4,1,2,3,2,0,6,6,4,5,2,42,13,13,71,21,24,53,27,25,57,50,41,80,77,62,113,98,82,132,113,101,134,126,113,123,126,112,116,125,111,120,128,115,131,138,126,139,148,137,143,154,145,156,168,161,169,184,179,182,197,193,188,202,201,82,96,82,46,57,36,36,44,22,31,35,17,27,30,15,22,28,15,17,26,13,16,23,12,18,21,12,19,21,13,20,22,14,19,23,15,19,27,20,23,31,21,37,40,27,64,55,45,87,70,67,104,88,81,116,102,85,128,112,88,139,121,105,131,122,110,117,122,107,115,127,112,123,133,119,131,139,127,139,149,138,148,160,151,159,172,164,174,189,183,185,200,196,187,202,200,85,101,83,62,75,48,58,67,38,55,61,37,51,56,35,47,53,33,46,53,34,48,55,38,49,55,40,51,56,41,53,58,44,55,62,46,59,67,45,68,71,48,81,84,59,104,96,74,116,103,83,127,109,92,133,116,97,127,121,97,127,127,107,118,124,106,114,125,108,122,131,117,129,136,123,136,145,133,141,152,141,149,162,153,158,171,163,168,183,178,180,195,191,186,200,199} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h new file mode 100644 index 0000000..09d0ca3 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h @@ -0,0 +1,43 @@ +#define CONV1_IM_DIM 32 +#define CONV1_IM_CH 3 +#define CONV1_KER_DIM 5 +#define CONV1_PADDING 2 +#define CONV1_STRIDE 1 +#define CONV1_OUT_CH 32 +#define CONV1_OUT_DIM 32 + +#define POOL1_KER_DIM 3 +#define POOL1_STRIDE 2 +#define POOL1_PADDING 0 +#define POOL1_OUT_DIM 16 + +#define CONV2_IM_DIM 16 +#define CONV2_IM_CH 32 +#define CONV2_KER_DIM 5 +#define CONV2_PADDING 2 +#define CONV2_STRIDE 1 +#define CONV2_OUT_CH 16 +#define CONV2_OUT_DIM 16 + +#define POOL2_KER_DIM 3 +#define POOL2_STRIDE 2 +#define POOL2_PADDING 0 +#define POOL2_OUT_DIM 8 + +#define CONV3_IM_DIM 8 +#define CONV3_IM_CH 16 +#define CONV3_KER_DIM 5 +#define CONV3_PADDING 2 +#define CONV3_STRIDE 1 +#define CONV3_OUT_CH 32 +#define CONV3_OUT_DIM 8 + +#define POOL3_KER_DIM 3 +#define POOL3_STRIDE 2 +#define POOL3_PADDING 0 +#define POOL3_OUT_DIM 4 + +#define IP1_DIM 4*4*32 +#define IP1_IM_DIM 4 +#define IP1_IM_CH 32 +#define IP1_OUT 10 diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h new file mode 100644 index 0000000..8d92d21 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h @@ -0,0 +1,26 @@ +#define CONV1_WT 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+ +#define CONV1_BIAS {-49,-18,-7,-20,-12,-15,7,2,-10,-84,-72,-65,-53,-6,-87,-63,-64,-28,-28,-4,-3,-10,-52,-15,-5,-7,-31,-44,-102,-19,-5,-65} + +#define CONV2_WT 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+ +#define CONV2_BIAS {55,50,34,43,-37,35,-21,10,35,-53,-76,7,14,-1,92,20} + +#define CONV3_WT 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+ +#define CONV3_BIAS {18,36,-46,-45,64,8,13,-19,28,1,14,-57,23,20,-2,32,48,-11,85,73,-7,52,125,33,125,13,92,-72,89,-1,11,70} + +#define IP1_WT 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34,-1,-20} + +#define IP1_BIAS {30,-121,-51,77,40,20,46,-35,28,-33} + +#define CONV1_BIAS_LSHIFT 6 +#define CONV1_OUT_RSHIFT 9 +#define CONV2_BIAS_LSHIFT 4 +#define CONV2_OUT_RSHIFT 9 +#define CONV3_BIAS_LSHIFT 1 +#define CONV3_OUT_RSHIFT 7 +#define IP1_BIAS_LSHIFT 1 +#define IP1_OUT_RSHIFT 8 +#define INPUT_MEAN_SHIFT {125,123,114} +#define INPUT_RIGHT_SHIFT {8,8,8} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt new file mode 100644 index 0000000..774fef8 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt @@ -0,0 +1,4 @@ +CMSIS NN Lib example arm_nnexample_cifar10 for + Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h new file mode 100644 index 0000000..ddf354d --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h @@ -0,0 +1,44 @@ +/*------------------------------------------------------------------------------ + * MDK - Component ::Event Recorder + * Copyright (c) 2016 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: EventRecorderConf.h + * Purpose: Event Recorder Configuration + * Rev.: V1.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288 +// <1048576=>1048576 +// Configure size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=1048576) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 1 + +// SysTick Configuration +// Configure values when Time Stamp Source is set to SysTick + +// SysTick Input Clock Frequency [Hz] <1-1000000000> +// Defines SysTick input clock (typical identical with processor clock) +#define SYSTICK_CLOCK 100000000U + +// SysTick Interrupt Period [us] <1-1000000000> +// Defines time period of the SysTick timer interrupt +#define SYSTICK_PERIOD_US 1000U + +// + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..9fc447d --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,242 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66829ad --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..16e56b0 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f08df7a --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..dae6439 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..070fa1e --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..26edb9f --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,295 @@ +/**************************************************************************//** + * @file startup_ARMCM7.s + * @brief CMSIS Core Device Startup File for + * ARMCM7 Device Series + * @version V5.00 + * @date 26. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __etext; +extern uint32_t __data_start__; +extern uint32_t __data_end__; +extern uint32_t __copy_table_start__; +extern uint32_t __copy_table_end__; +extern uint32_t __zero_table_start__; +extern uint32_t __zero_table_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __StackTop; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +#ifndef __START +extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ +#else +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +#endif + +#ifndef __NO_SYSTEM_INIT +extern void SystemInit (void); /* CMSIS System Initialization */ +#endif + + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void); /* Default empty handler */ +void Reset_Handler(void); /* Reset Handler */ + + +/*---------------------------------------------------------------------------- + User Initial Stack & Heap + *----------------------------------------------------------------------------*/ +#ifndef __STACK_SIZE + #define __STACK_SIZE 0x00000400 +#endif +static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); + +#ifndef __HEAP_SIZE + #define __HEAP_SIZE 0x00000C00 +#endif +#if __HEAP_SIZE > 0 +static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Cortex-M7 Processor Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* ARMCM7 Specific Interrupts */ +void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = { + /* Cortex-M7 Exceptions Handler */ + (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + /* External interrupts */ + WDT_IRQHandler, /* 0: Watchdog Timer */ + RTC_IRQHandler, /* 1: Real Time Clock */ + TIM0_IRQHandler, /* 2: Timer0 / Timer1 */ + TIM2_IRQHandler, /* 3: Timer2 / Timer3 */ + MCIA_IRQHandler, /* 4: MCIa */ + MCIB_IRQHandler, /* 5: MCIb */ + UART0_IRQHandler, /* 6: UART0 - DUT FPGA */ + UART1_IRQHandler, /* 7: UART1 - DUT FPGA */ + UART2_IRQHandler, /* 8: UART2 - DUT FPGA */ + UART4_IRQHandler, /* 9: UART4 - not connected */ + AACI_IRQHandler, /* 10: AACI / AC97 */ + CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */ + ENET_IRQHandler, /* 12: Ethernet */ + USBDC_IRQHandler, /* 13: USB Device */ + USBHC_IRQHandler, /* 14: USB Host Controller */ + CHLCD_IRQHandler, /* 15: Character LCD */ + FLEXRAY_IRQHandler, /* 16: Flexray */ + CAN_IRQHandler, /* 17: CAN */ + LIN_IRQHandler, /* 18: LIN */ + I2C_IRQHandler, /* 19: I2C ADC/DAC */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + 0, /* 27: Reserved */ + CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */ + 0, /* 29: Reserved - CPU FPGA */ + UART3_IRQHandler, /* 30: UART3 - CPU FPGA */ + SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ +}; + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) { + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + pTable = &__copy_table_start__; + + for (; pTable < &__copy_table_end__; pTable = pTable + 3) { + pSrc = (uint32_t*)*(pTable + 0); + pDest = (uint32_t*)*(pTable + 1); + for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { + *pDest++ = *pSrc++; + } + } +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + pSrc = &__etext; + pDest = &__data_start__; + + for ( ; pDest < &__data_end__ ; ) { + *pDest++ = *pSrc++; + } +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + pTable = &__zero_table_start__; + + for (; pTable < &__zero_table_end__; pTable = pTable + 2) { + pDest = (uint32_t*)*(pTable + 0); + for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { + *pDest++ = 0; + } + } +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for ( ; pDest < &__bss_end__ ; ) { + *pDest++ = 0UL; + } +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + SystemInit(); +#endif + +#ifndef __START +#define __START _start +#endif + __START(); + +} + + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + + while(1); +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..b69f038 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..65bfaca --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h new file mode 100644 index 0000000..b3b3076 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + +#define RTE_Compiler_EventRecorder + #define RTE_Compiler_EventRecorder_DAP +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h new file mode 100644 index 0000000..2df6879 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM3.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h new file mode 100644 index 0000000..f29db07 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h new file mode 100644 index 0000000..6cd8e76 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM7_SP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp new file mode 100644 index 0000000..340dc33 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_gru.cpp +* +* Description: Gated Recurrent Unit Example +* +* Target Processor: Cortex-M4/Cortex-M7 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of Arm LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GRUExample Gated Recurrent Unit Example + * + * \par Description: + * \par + * Demonstrates a gated recurrent unit (GRU) example with the use of fully-connected, + * Tanh/Sigmoid activation functions. + * + * \par Model definition: + * \par + * GRU is a type of recurrent neural network (RNN). It contains two sigmoid gates and one hidden + * state. + * \par + * The computation can be summarized as: + * 
z[t] = sigmoid( W_z ⋅ {h[t-1],x[t]} )
+ * r[t] = sigmoid( W_r ⋅ {h[t-1],x[t]} ) 
+ * n[t] = tanh( W_n ⋅ [r[t] × {h[t-1], x[t]} ) 
+ * h[t] = (1 - z[t]) × h[t-1] + z[t] × n[t]
+ * \image html GRU.gif "Gate Recurrent Unit Diagram" + * + * \par Variables Description: + * \par + * \li \c update_gate_weights, \c reset_gate_weights, \c hidden_state_weights are weights corresponding to update gate (W_z), reset gate (W_r), and hidden state (W_n). + * \li \c update_gate_bias, \c reset_gate_bias, \c hidden_state_bias are layer bias arrays + * \li \c test_input1, \c test_input2, \c test_history are the inputs and initial history + * + * \par + * The buffer is allocated as: + * \par + * | reset | input | history | update | hidden_state | + * \par + * In this way, the concatination is automatically done since (reset, input) and (input, history) + * are physically concatinated in memory. + * \par + * The ordering of the weight matrix should be adjusted accordingly. + * + * + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fully_connected_mat_q7_vec_q15_opt() + * - arm_nn_activations_direct_q15() + * - arm_mult_q15() + * - arm_offset_q15() + * - arm_sub_q15() + * - arm_copy_q15() + * + * Refer + * \link arm_nnexamples_gru.cpp \endlink + * + */ + +#include +#include +#include +#include "arm_nnexamples_gru_test_data.h" +#include "arm_math.h" +#include "arm_nnfunctions.h" + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif +#endif + +#define DIM_HISTORY 32 +#define DIM_INPUT 32 +#define DIM_VEC 64 + +#define USE_X4 + +#ifndef USE_X4 +static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X2; +static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X2; +static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X2; +#else +static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X4; +static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X4; +static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X4; +#endif + +static q7_t update_gate_bias[DIM_HISTORY] = UPDATE_GATE_BIAS; +static q7_t reset_gate_bias[DIM_HISTORY] = RESET_GATE_BIAS; +static q7_t hidden_state_bias[DIM_HISTORY] = HIDDEN_STATE_BIAS; + +static q15_t test_input1[DIM_INPUT] = INPUT_DATA1; +static q15_t test_input2[DIM_INPUT] = INPUT_DATA2; +static q15_t test_history[DIM_HISTORY] = HISTORY_DATA; + +q15_t scratch_buffer[DIM_HISTORY * 4 + DIM_INPUT]; + +void gru_example(q15_t * scratch_input, uint16_t input_size, uint16_t history_size, + q7_t * weights_update, q7_t * weights_reset, q7_t * weights_hidden_state, + q7_t * bias_update, q7_t * bias_reset, q7_t * bias_hidden_state) +{ + q15_t *reset = scratch_input; + q15_t *input = scratch_input + history_size; + q15_t *history = scratch_input + history_size + input_size; + q15_t *update = scratch_input + 2 * history_size + input_size; + q15_t *hidden_state = scratch_input + 3 * history_size + input_size; + + // reset gate calculation + // the range of the output can be adjusted with bias_shift and output_shift +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(input, weights_reset, input_size + history_size, history_size, 0, 15, bias_reset, + reset, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(input, weights_reset, input_size + history_size, history_size, 0, 15, + bias_reset, reset, NULL); +#endif + // sigmoid function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(reset, history_size, 0, ARM_SIGMOID); + arm_mult_q15(history, reset, reset, history_size); + + // update gate calculation + // the range of the output can be adjusted with bias_shift and output_shift +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(input, weights_update, input_size + history_size, history_size, 0, 15, + bias_update, update, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(input, weights_update, input_size + history_size, history_size, 0, 15, + bias_update, update, NULL); +#endif + + // sigmoid function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(update, history_size, 0, ARM_SIGMOID); + + // hidden state calculation +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15, + bias_hidden_state, hidden_state, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15, + bias_hidden_state, hidden_state, NULL); +#endif + + // tanh function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(hidden_state, history_size, 0, ARM_TANH); + arm_mult_q15(update, hidden_state, hidden_state, history_size); + + // we calculate z - 1 here + // so final addition becomes substraction + arm_offset_q15(update, 0x8000, update, history_size); + // multiply history + arm_mult_q15(history, update, update, history_size); + // calculate history_out + arm_sub_q15(hidden_state, update, history, history_size); + + return; +} + +int main() +{ + #ifdef RTE_Compiler_EventRecorder + EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder + #endif + + printf("Start GRU execution\n"); + int input_size = DIM_INPUT; + int history_size = DIM_HISTORY; + + // copy over the input data + arm_copy_q15(test_input1, scratch_buffer + history_size, input_size); + arm_copy_q15(test_history, scratch_buffer + history_size + input_size, history_size); + + gru_example(scratch_buffer, input_size, history_size, + update_gate_weights, reset_gate_weights, hidden_state_weights, + update_gate_bias, reset_gate_bias, hidden_state_bias); + printf("Complete first iteration on GRU\n"); + + arm_copy_q15(test_input2, scratch_buffer + history_size, input_size); + gru_example(scratch_buffer, input_size, history_size, + update_gate_weights, reset_gate_weights, hidden_state_weights, + update_gate_bias, reset_gate_bias, hidden_state_bias); + printf("Complete second iteration on GRU\n"); + + return 0; +} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h new file mode 100644 index 0000000..4fd2bb0 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h @@ -0,0 +1,23 @@ +#define UPDATE_GATE_WEIGHT_X2 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+ +#define UPDATE_GATE_WEIGHT_X4 {-62,78,83,104,-68,28,-33,-63,-58,104,-89,17,-70,83,-16,-85,-80,-116,1,-40,-42,101,-9,40,-93,-83,31,4,-104,23,107,-39,101,88,95,-110,-81,74,-16,-99,121,-111,-83,-98,42,73,-74,50,71,18,18,-89,-63,-20,-4,123,-98,120,-5,-84,-128,-88,-109,-13,44,66,-100,-69,-105,-126,55,-25,-16,-8,-73,-22,-51,70,-68,-11,25,-91,62,-29,-88,16,19,-28,34,-41,-22,110,-39,121,116,-29,-16,55,42,-124,-7,20,66,-69,9,-67,-125,103,52,104,-29,117,60,-40,-78,-100,63,-40,-94,-1,15,1,-76,-25,71,-97,-2,-12,-76,-68,-63,-62,-127,31,31,32,71,-89,-25,-75,-103,15,120,-32,78,-20,-66,-78,124,77,41,31,38,101,-118,-92,-13,16,-23,40,-71,-51,-120,-97,127,107,59,-52,-80,-54,28,59,-22,-52,54,-89,33,-78,51,41,-2,-17,32,124,82,34,-105,-102,-87,-95,-109,54,26,-9,-47,-53,85,48,-31,-40,38,56,86,103,-5,37,-59,24,-114,-55,44,13,-122,-46,-97,42,90,81,-98,-75,-14,119,-88,5,105,-20,-123,-37,-19,-118,43,-45,24,29,95,36,-30,-10,115,106,-12,110,11,84,42,83,14,57,49,-80,-35,-127,10,-74,121,-10,-56,-8,85,50,-120,37,44,-34,37,15,-25,-44,98,-114,16,-88,83,-87,-31,6,-98,-53,25,88,-54,18,111,8,127,115,88,19,-78,61,-96,66,-111,7,-49,-67,-114,-108,-65,-67,114,93,111,80,-100,-6,28,107,-17,-48,-74,-11,-31,-68,-111,25,40,-61,-18,31,33,25,66,25,35,38,19,29,74,-82,-43,71,31,-59,48,-70,112,62,119,121,-23,0,53,25,-80,-31,-26,-4,102,106,41,-7,74,17,-81,-6,89,-44,-27,53,-123,-60,55,-17,87,62,-54,19,-126,116,32,-67,-121,-64,-113,109,-66,45,110,117,97,70,125,-103,-86,-90,-118,12,125,-114,-108,97,-21,-68,15,20,58,57,-17,112,16,121,26,-65,8,24,70,-66,13,-43,-109,74,-67,-127,-55,29,41,-104,-16,-42,59,29,42,-31,88,-69,81,35,-85,-87,78,-125,-82,4,-55,-17,27,54,16,-98,-89,5,109,95,66,101,67,-39,-52,-82,118,18,54,56,-74,-88,-39,65,57,43,33,-63,-19,-113,-16,-57,86,89,72,-73,77,-91,-68,1,-10,-8,126,80,-122,112,-19,37,110,-51,-7,-27,-109,-75,-50,10,-17,67,58,-42,78,-5,-84,4,103,-50,-88,79,15,60,-3,-18,94,81,2,-55,16,23,-61,-16,66,68,-52,44,-23,-114,51,-103,39,-111,-110,-88,34,92,-91,-23,96,-123,-35,111,31,72,-60,-80,-64,24,61,43,88,58,-1,-17,75,-7,-108,42,-38,-125,55,53,-108,23,31,-11,117,96,73,114,38,-13,-26,126,38,25,75,-105,-113,-88,-57,96,65,-105,-9,120,-92,13,9,-128,0,-70,-92,-25,-3,-40,59,85,124,-82,-30,29,93,-38,14,-17,-39,103,-27,-43,-100,3,-95,23,-91,-37,-55,2,125,-121,107,76,-34,58,52,-110,72,54,85,108,-83,16,110,-43,12,30,-31,-116,-68,-44,84,66,-83,28,-78,22,-86,89,65,60,-79,-81,21,0,-118,6,92,-6,11,-8,56,-108,60,27,87,126,-106,-80,-3,-34,-116,88,35,64,-38,-42,33,-125,53,22,-24,126,-79,75,-94,-45,85,-116,15,-69,-11,-116,77,28,91,-29,-109,-41,-22,81,-94,-70,100,-3,95,94,82,31,-89,-81,97,-80,-1,-116,-2,5,88,42,111,119,-113,-46,116,5,36,105,74,-40,-64,-21,93,-105,-110,-109,7,105,-62,78,-11,-20,-74,64,91,5,101,-34,35,54,-112,72,21,-32,-91,46,51,-124,32,-95,-59,90,-6,120,21,-83,98,60,36,6,29,44,25,-17,10,-29,-41,40,-19,-18,57,65,110,4,-56,51,89,87,-50,112,-12,109,109,-50,34,38,-123,-115,-88,-38,85,25,-32,-27,-18,37,-30,-13,87,-52,20,-84,9,1,18,-106,118,87,-19,103,-81,85,23,76,21,44,-45,-50,-120,36,106,78,40,101,-120,-49,20,-119,115,16,78,-102,2,68,18,20,-72,-20,-103,104,70,119,75,-113,11,23,83,107,100,43,64,-67,44,-88,117,18,126,105,-9,44,-63,-85,98,119,63,4,-82,-48,30,-21,115,-53,114,16,-62,-42,123,-84,-39,-7,106,83,-11,-39,25,-8,15,-114,104,106,-9,31,84,23,52,-54,-13,-34,88,-76,46,74,77,80,-40,-51,101,68,64,77,-104,-40,73,82,108,-111,125,19,-13,-75,52,-116,33,-104,34,-41,125,60,116,-118,-54,109,65,77,6,82,-114,-29,-47,-6,57,-96,-128,-121,85,-91,2,81,-2,-43,115,114,-117,-102,-80,-76,7,-124,-65,-1,100,-82,-20,64,-73,-75,82,32,98,121,-75,27,72,34,-109,-117,-83,-98,-24,-24,99,21,43,64,-125,-88,-91,36,-94,-87,-106,-100,-97,115,95,59,-39,-29,-4,-36,-46,-84,15,-121,-127,-45,58,-46,-94,4,-21,29,123,-111,-128,4,53,45,-27,73,29,-44,-80,-94,-117,-109,100,-78,-84,-18,53,101,-25,-7,-27,84,44,101,28,108,105,60,95,-95,-126,-24,-59,-61,15,15,88,-71,-11,-90,94,-59,25,112,-38,126,58,-48,-64,-114,-88,71,122,36,112,1,82,-14,62,39,-62,-42,127,106,58,52,-28,-85,95,-126,50,109,5,-45,-86,-68,125,105,-6,-100,-102,74,-83,-18,-9,-127,90,-33,-18,-68,-100,48,101,-41,-86,-94,104,-68,-124,57,22,-93,17,-22,108,-99,21,13,-91,-25,-64,31,-22,-86,50,-71,-100,66,73,85,-102,-27,-27,-43,-92,-23,-17,-70,-31,69,115,122,86,4,-11,127,-105,92,85,-70,33,123,-40,125,-49,-95,-112,115,-43,124,84,117,-82,-87,61,-61,114,-32,104,-8,57,-71,62,18,-31,-18,30,18,112,94,-84,49,-7,123,-119,-90,-92,103,5,-101,-26,37,78,-31,-92,-1,-10,-50,-21,-111,35,-50,90,-60,-89,-73,60,124,-45,-2,-13,96,-96,-18,48,54,-75,31,-125,-1,-34,-64,88,93,-19,-98,-83,75,-80,-69,-91,16,-75,104,29,-6,92,112,12,21,15,-38,-33,-24,118,-56,-2,56,127,127,-14,94,-38,127,83,113,29,-48,-80,97,-50,-48,-109,-57,61,-96,41,4,-111,-4,-26,85,67,-108,-14,106,76,-113,-31,-12,-2,-30,-29,-76,-7,80,-41,26,63,94,-5,116,58,-39,-13,-76,95,44,-79,-109,-72,-101,-81,-104,26,-122,-42,38,-116,-6,-24,48,-91,112,-109,-103,-45,38,46,-82,-19,99,107,-119,-20,-52,114,-91,-102,49,62,35,97,-38,-14,112,111,107,-35,108,125,110,11,115,80,47,36,54,22,76,26,69,55,11,-65,-50,27,100,-2,-116,26,-73,76,37,-88,109,-2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+ +#define RESET_GATE_WEIGHT_X2 {65,-28,-36,70,67,55,86,-53,23,25,-19,59,67,43,-92,48,94,-113,60,-58,24,76,-15,-19,15,36,-74,115,-59,3,34,-43,21,-125,-45,127,92,-5,-65,-103,-83,51,42,109,-51,-39,-97,-64,-4,57,79,-42,88,-4,-108,83,-4,20,86,82,-87,95,12,-69,28,30,-97,-13,-33,-48,75,119,18,31,-83,-59,-114,-21,127,34,-27,-26,-47,86,-83,-49,8,29,-48,-31,-94,-59,-49,-36,0,28,-64,113,65,-8,47,-55,-49,112,-40,-39,-100,-42,32,82,27,-78,-105,3,19,88,15,-121,-120,7,-9,-107,-23,104,114,66,113,-102,-90,24,80,-34,106,48,-91,-11,22,-96,-82,75,26,-42,59,-45,23,78,79,-76,6,20,63,-118,-125,-42,111,-80,-79,-59,-121,-79,83,49,-95,-49,81,15,-11,-54,-45,64,-30,-49,81,-57,71,91,113,-46,-63,-4,-96,-95,-27,5,-52,35,67,112,58,-62,48,112,106,80,-19,103,4,-32,-118,-74,12,13,-126,-20,-5,115,-74,-30,123,-74,-66,11,-99,-16,-102,-100,-81,-20,-24,92,-79,-31,44,-24,-85,-123,5,-52,-111,73,29,28,-19,18,23,-112,-32,-52,-38,99,-59,-52,-31,87,124,28,-42,-39,81,-87,-24,16,47,20,36,1,-70,121,124,13,1,30,112,87,-86,11,36,-18,74,-104,-100,-14,0,-24,28,-53,53,66,-63,-109,-10,-50,-15,63,34,82,-59,85,-44,105,-10,-27,99,5,-105,-69,-75,2,-47,-66,71,-30,73,-11,-45,93,47,-37,-34,-8,90,-106,103,112,65,-100,-25,-13,38,74,54,27,-81,-8,19,49,94,118,-121,-116,120,-71,-87,36,-65,-112,8,-59,-106,-40,-16,68,87,-109,53,12,-7,9,6,67,78,8,-42,-123,79,-93,-102,-40,12,-66,-109,47,15,-8,-5,51,-62,111,8,-66,-82,-102,120,68,-67,9,-73,-69,-79,56,-36,-10,-69,-99,-2,-11,-66,76,37,4,92,1,-89,74,85,-124,-25,40,106,-102,42,-19,-30,0,-70,82,84,106,-84,48,16,37,33,-114,38,-29,-117,51,101,26,56,127,-81,-76,38,-124,103,-25,54,-21,-112,40,102,3,63,36,-54,16,-18,114,39,5,105,83,117,-92,-5,-14,-102,-87,-48,-77,-19,-82,-55,119,-95,-43,97,126,-48,-50,-97,-25,-102,-53,47,111,66,-82,-16,-38,76,-15,23,20,88,-19,125,-90,107,-31,102,107,30,-111,71,38,26,43,-85,82,29,-99,126,-109,21,-42,-107,-115,-123,30,-46,39,4,-19,-44,-69,86,41,4,33,57,-110,95,-22,123,71,1,119,77,90,105,81,-68,74,-38,-109,6,-82,-20,-115,-104,38,27,-44,82,-107,99,-41,-28,-55,100,10,-42,7,91,56,-91,113,-91,70,-66,-48,-18,109,-27,42,-89,-20,-63,-41,77,-13,73,10,-74,-51,88,28,50,-5,7,92,18,-98,-41,-14,8,-16,99,30,-109,7,52,110,-120,-17,33,53,1,106,-99,-14,-93,-46,-60,7,-54,100,91,93,89,-84,118,58,-84,38,57,-24,-25,22,-52,119,-85,-75,-79,60,-97,1,-13,54,-43,98,-92,65,37,-110,64,21,-18,-111,-9,86,90,42,-71,-29,86,-10,-15,-20,106,-45,-22,44,105,55,-61,-89,-119,31,93,-97,-35,9,-113,86,-113,22,-68,-29,-36,-123,98,79,34,-29,71,44,49,56,93,4,63,-3,45,12,54,-96,27,-55,-72,84,69,27,-28,-111,-57,-41,92,-106,-90,55,105,-60,94,34,94,-1,112,-86,-55,-58,68,-65,37,110,-107,-62,66,61,-69,-52,27,-61,70,-56,-116,-101,-103,127,-98,-79,25,-117,40,33,111,10,-3,-65,1,84,-41,5,-93,-85,-96,78,54,43,70,77,-53,-71,-38,48,103,-88,115,94,20,-5,-125,-7,-61,30,-25,-57,-42,-100,63,-114,40,-53,123,50,-7,121,75,67,75,3,-38,-101,-44,-46,54,38,-22,4,18,102,-126,44,86,-10,-1,118,98,102,-125,74,32,18,74,73,72,64,47,105,-72,5,73,98,9,39,18,10,-68,81,-128,-89,27,-51,51,16,119,-71,-53,51,-84,107,-116,7,73,106,20,52,-85,-74,-103,-18,29,-13,73,106,-92,107,-115,5,65,83,-79,-7,98,-42,-33,82,-64,75,-32,100,-67,-122,84,43,-111,114,-99,46,12,99,43,50,-24,-88,-60,111,68,64,54,-105,-120,119,68,5,51,63,89,-57,-75,-25,-35,-28,42,-64,101,-103,-35,-99,-96,-18,-64,-94,-46,89,-65,-38,-1,-97,127,-67,84,-18,86,115,60,-78,-109,-61,-93,-67,-87,-80,124,26,-9,111,115,-88,-71,-86,-71,-65,-15,108,-25,111,9,86,-115,-55,-23,57,27,103,108,-28,65,86,68,114,62,126,-4,33,-34,-123,87,-76,-104,-126,26,-13,44,108,105,12,-35,-58,3,-5,-32,91,49,89,88,37,38,119,-125,-48,37,53,85,-73,67,116,-116,-127,103,127,-115,92,-35,-83,-45,25,-96,-13,-90,41,-27,105,119,85,27,-3,-64,93,17,-53,104,-70,-43,65,45,-90,61,-31,-49,-99,84,46,93,-37,84,-79,13,-59,-76,62,19,-11,-96,-104,-3,-8,-78,92,98,50,-7,-39,-82,37,-126,127,-113,67,94,115,-9,-33,-57,26,-67,9,28,-8,81,-98,-10,84,34,111,-95,127,75,38,-7,-2,-71,-62,-72,99,-74,25,123,114,51,-28,103,-110,43,113,7,58,75,-95,-52,19,-112,101,26,65,-115,-91,85,-5,-45,110,-103,-34,-69,50,-15,-19,-110,-44,-7,-112,-93,29,50,-84,-55,-41,11,19,-31,-47,-62,-12,-105,-47,68,-124,-47,-113,-55,30,25,55,-14,85,-66,-5,-105,62,-27,-89,-124,-84,112,34,52,25,104,32,-30,84,-46,-38,60,-2,-107,-95,-86,-25,117,60,-121,32,84,8,-88,-1,91,-46,-76,81,44,79,105,-105,82,20,59,-115,96,21,-113,19,92,122,76,36,-112,78,16,38,73,69,54,97,41,-49,78,-71,-69,95,-85,117,10,-98,25,72,126,47,-17,4,-44,-32,-16,-12,105,76,4,-82,-91,-21,-117,30,-67,46,-8,-125,84,-51,94,0,-60,127,99,43,60,16,55,-16,-121,-61,-115,38,25,17,35,23,68,9,-107,-44,118,119,43,99,-95,40,42,-70,54,19,92,-36,82,-35,122,-96,54,-29,-50,100,-79,-71,-99,-60,-2,-100,41,97,-93,-58,-123,126,-102,81,-5,83,110,-50,58,-86,41,-126,43,-49,98,-59,94,-91,115,16,-3,-58,-30,-109,110,-114,124,22,-88,-79,-29,-100,54,-33,23,-1,-77,52,-126,114,70,-50,90,82,-13,-25,-125,16,48,101,-93,19,-103,67,-1,-32,28,-72,-26,73,45,-22,83,-68,-61,89,57,-37,90,16,-38,-124,47,-5,-113,81,71,-30,-46,-18,-52,-104,-40,49,-101,106,38,6,125,-70,25,-88,-50,-77,-12,53,110,-84,23,-109,-53,112,2,88,101,-55,-10,-72,123,-35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+ +#define RESET_GATE_WEIGHT_X4 {65,28,-28,30,-90,106,24,80,-36,-97,70,-13,80,-19,-34,103,67,-33,55,-48,106,4,48,-32,86,75,-53,119,-91,-118,-11,-74,23,18,25,31,22,12,-96,13,-19,-83,59,-59,-82,-126,75,-20,67,-114,43,-21,26,-5,-42,115,-92,127,48,34,59,-74,-45,-30,94,-27,-113,-26,23,123,78,-74,60,-47,-58,86,79,-66,-76,11,24,-83,76,-49,6,-99,20,-16,-15,8,-19,29,63,-102,-118,-100,15,-48,36,-31,-125,-81,-42,-20,-74,-94,115,-59,111,-24,-80,92,-59,-49,3,-36,-79,-79,-59,-31,34,0,-43,28,-121,44,-79,-24,21,-64,-125,113,83,-85,49,-123,-45,65,127,-8,-95,5,-49,-52,92,47,-5,-55,81,-111,15,73,-65,-49,-103,112,-11,29,-54,28,-83,-40,51,-39,-45,-19,64,18,42,-100,109,-42,-30,23,-49,-112,-51,32,-39,82,81,-32,-57,-52,-97,27,-64,-78,71,-38,91,99,-4,-105,57,3,113,-59,-46,-52,79,19,-42,88,-63,-31,-4,87,88,15,-4,-121,-96,124,-95,28,-108,-120,83,7,-27,-42,5,-39,-4,-9,20,-107,-52,81,35,-87,86,-23,82,104,67,-24,112,16,-87,114,95,66,58,47,-62,20,12,113,-69,-102,48,36,112,1,-70,54,121,27,-2,-102,-11,-87,124,-81,13,-8,-66,-48,76,-77,1,19,30,49,37,-19,4,-82,112,94,87,118,92,-55,1,119,-86,-121,11,-116,-89,-95,74,-43,36,120,-18,-71,85,97,-124,126,74,-87,-104,36,-25,-48,40,-50,-100,-65,-14,-112,106,-97,-102,-25,0,8,-24,-59,42,-102,-19,-53,28,-106,-53,-40,-30,47,0,111,53,-16,66,68,-70,66,82,-82,-63,87,-109,-109,84,-16,106,-38,-10,53,-50,12,-84,76,48,-15,-15,-7,63,9,16,23,37,20,34,6,82,67,33,88,-114,-19,-59,78,85,8,38,125,-29,-90,-44,-42,105,-123,-117,107,51,-31,-10,79,-27,-93,101,102,26,107,99,-102,5,-40,56,30,127,-111,-105,12,-69,-66,-81,71,-76,38,-75,-109,2,47,38,26,-124,43,-47,15,-66,-8,103,-85,-25,82,71,-5,-30,51,54,29,-21,-99,73,-62,-11,111,-112,126,40,-109,-45,8,93,-66,102,21,3,-42,47,-82,-37,-102,63,-107,36,-115,-34,120,-8,68,-54,-123,16,30,90,-67,-106,9,-18,-46,114,39,103,-73,112,-69,39,4,5,-19,65,-79,-100,56,105,-44,83,-69,-25,-36,-13,-10,117,86,-92,41,38,-69,74,-99,-5,4,-14,33,57,-41,-110,-14,-15,68,-20,-65,95,8,-22,-16,106,37,-45,110,123,99,71,30,-22,-107,44,-62,1,-109,119,7,105,66,55,61,77,52,90,110,-61,-69,-89,-52,105,-120,81,-17,-119,27,31,-61,-68,33,74,53,93,70,-97,-56,-38,1,-109,106,-35,-116,9,-101,6,-99,-82,-14,-113,-103,86,127,-20,-93,-115,-46,-113,-98,22,-79,-104,-60,38,7,-68,25,-29,-117,27,-54,-44,100,-36,40,-123,33,82,91,-107,93,98,111,79,10,99,89,-41,-84,34,-3,-29,-65,-28,118,-55,58,71,1,44,84,100,-84,10,38,49,-41,56,5,-42,57,7,-24,93,-93,4,-85,91,-25,56,22,63,-96,-3,78,-91,-52,113,119,45,54,12,43,-91,-85,70,-75,54,70,-96,77,-66,-79,-48,60,27,-53,-55,-71,-18,-97,109,1,-72,-38,84,48,-27,-13,42,54,69,103,27,-88,-89,-43,-20,98,-28,115,-111,94,-63,-92,-41,65,-57,20,-41,-5,77,37,-13,-110,92,-125,-106,-7,73,64,10,21,-90,-61,55,30,-74,-18,-51,-111,105,-25,-60,-57,88,-9,28,86,94,-42,34,-100,50,90,-5,42,94,63,-1,-114,7,-71,92,-29,112,40,-86,-53,18,86,-98,-10,-55,123,-58,50,-7,-103,121,-18,-46,-35,89,-58,75,29,67,-13,-65,3,-38,-5,75,73,3,106,-1,-32,-97,91,-38,-92,-101,107,127,49,-67,89,-44,-115,-46,5,84,88,-18,37,54,65,38,83,86,38,115,119,-22,-79,4,-7,60,-125,-78,-48,18,98,102,-42,-109,37,-61,53,-126,-33,44,82,-93,85,-67,-73,86,-64,-10,75,-87,67,-80,116,-1,-32,118,100,124,-116,26,-127,98,-67,102,-122,-9,103,111,127,-125,84,74,43,115,-115,-88,92,32,-111,18,114,-71,-35,-86,-83,74,-99,73,46,-71,-45,-65,25,72,12,64,99,-15,-96,108,-13,47,43,105,50,-25,-90,111,41,-72,-24,5,-88,9,-27,86,105,73,-60,98,111,-115,119,-55,85,9,68,39,64,-23,27,57,-3,18,54,10,-105,27,-64,103,93,-68,-120,81,119,108,17,-28,-53,-128,68,-89,5,65,104,86,-70,27,51,-51,63,68,-43,114,65,51,89,16,-57,62,45,126,-90,119,-75,-71,-25,-4,61,33,-31,-53,-35,51,-28,-34,-49,-123,-99,-84,42,107,-64,87,84,-76,46,-116,101,7,-103,-104,93,-126,-37,73,-35,106,-99,26,84,-13,-79,20,-96,52,-18,44,13,108,-59,-85,-64,-74,-94,105,-76,12,62,19,-115,-11,-91,117,-67,60,46,-96,85,-104,-5,-121,-8,32,-125,-3,-45,-8,110,84,84,8,-51,-78,-103,92,-34,-88,94,-1,0,98,-69,50,50,91,-60,-46,127,-7,-15,-39,-19,-76,99,81,43,-82,-110,37,-44,44,60,79,16,-126,-7,127,-112,105,55,-105,-16,-113,-93,67,29,82,-121,20,-61,94,50,115,-84,59,-115,-115,38,-9,-55,-33,-41,96,25,21,17,-57,11,26,19,-113,35,19,23,-67,-31,9,-47,92,68,122,9,28,-62,-8,-12,76,-107,36,-44,81,-105,-98,-47,-112,118,78,119,-10,68,84,-124,16,43,38,99,34,-47,111,-113,73,-95,69,40,-95,-55,127,30,54,42,97,-70,75,25,38,55,41,54,-49,19,-7,-14,-2,85,78,92,-71,-36,-71,-66,-62,-5,-69,82,95,-35,-72,-105,99,62,-85,122,117,-96,-74,-27,25,-89,10,54,-98,-29,123,-124,114,-84,25,-50,72,100,51,112,-28,34,126,-79,47,-71,103,52,-110,25,-17,-99,4,-60,43,104,113,32,-44,-2,-32,-100,7,-30,58,84,-16,41,-12,97,75,-46,-95,-38,105,-93,76,-58,-52,60,19,-2,4,-123,-82,126,-112,-107,101,-95,-91,-102,-21,81,26,-86,65,-25,-117,-5,30,83,110,-38,-50,-124,57,-31,-16,13,58,47,-86,-5,114,71,-98,63,41,-113,-126,81,101,-126,81,107,43,71,-49,-30,34,115,-83,-100,98,-46,-59,-18,-8,27,3,39,94,-52,-91,-104,-27,10,5,75,115,-40,16,49,110,-128,-24,58,-3,-101,-58,106,-80,103,9,-104,-30,38,-109,6,85,126,-108,-59,110,125,-114,-70,96,31,-93,89,124,25,22,-88,-34,-67,76,97,-88,-50,-79,-77,-107,-96,71,-69,-29,-12,-100,53,84,87,-98,19,5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+ +#define HIDDEN_STATE_WEIGHT_X2 {-3,-33,59,21,117,70,0,44,108,108,-47,-80,-118,34,88,-91,-123,-108,8,51,26,82,-80,107,-100,-69,97,-90,17,19,63,111,-40,-125,110,24,58,-69,26,-31,-65,-37,-47,-41,-109,106,-100,108,-99,108,116,104,86,-50,-45,10,-53,112,34,96,-10,-39,-32,-25,69,102,-2,-4,-25,121,-1,-28,-48,-100,0,-128,60,-73,42,-32,118,-88,-113,-112,-113,70,-98,118,95,77,-52,123,-99,72,26,-102,-32,120,113,22,6,-68,84,-33,103,66,111,60,-76,33,10,25,-43,93,41,-79,110,13,67,107,-113,90,58,64,-125,79,-85,-18,76,80,-59,11,-18,-74,15,-102,99,-19,117,99,65,-50,-108,-121,-9,-104,33,94,-95,110,-48,-97,76,36,1,-58,86,-115,45,-88,38,51,123,-23,-20,-43,-37,15,91,-85,-88,6,-96,58,78,13,23,1,-43,62,-70,-108,44,30,74,90,79,-80,-20,71,-21,0,60,19,-59,-52,44,-14,77,92,-69,121,-123,-27,119,-84,79,87,24,85,118,1,-51,-96,60,102,-6,15,96,120,-109,6,35,11,-119,-109,-18,16,-112,91,-126,71,-29,121,-21,-120,37,57,-117,-39,93,56,-73,-104,77,-107,-52,111,-61,-4,44,-119,67,72,-66,36,-127,-113,-124,123,21,98,84,86,76,23,78,7,-127,-4,1,-46,-107,59,-21,53,-65,-99,-15,-98,53,-31,7,64,7,105,51,-75,50,-52,48,101,-126,-120,5,34,3,81,-39,70,41,112,25,30,79,-6,107,-11,-97,92,-84,67,49,107,60,101,-37,27,-91,-61,-96,120,-113,87,-46,68,64,102,-86,-60,13,-71,56,-105,90,-9,-35,27,103,120,39,23,-39,-1,-85,-95,-6,119,-41,-2,-69,102,102,-119,-3,-11,-125,-111,40,-115,-41,-117,-44,-7,83,123,-21,23,99,-107,43,100,-99,-3,89,3,-113,103,47,-94,-69,-38,-28,-37,49,-117,-49,-126,17,-98,37,92,55,-116,-70,-50,77,120,47,124,78,114,67,-48,6,-42,-115,85,116,-114,-46,-50,-13,70,-101,110,-55,20,-51,125,-19,-9,-15,46,30,-27,-123,114,-50,-30,-72,76,-83,71,47,-45,74,102,44,108,-26,108,-113,-43,110,-91,37,-69,76,-33,106,-76,-96,20,-117,63,-33,-5,11,-121,-51,63,-56,59,-16,-33,114,74,124,73,99,-50,51,-71,118,106,30,-92,26,-40,119,-121,2,-45,9,0,-5,-2,-89,88,-11,-85,-60,19,81,-96,75,82,-40,124,89,-36,-117,-100,-2,-34,112,101,39,-101,-106,60,59,-126,-32,96,68,-53,87,20,54,-24,46,-95,65,-112,22,60,122,-22,-106,-124,97,-37,-86,95,-110,-8,44,58,-12,-120,-45,-86,-32,-86,-94,-14,15,29,-8,-114,71,70,-93,-69,100,-123,-18,-47,-12,127,104,-102,93,-11,-73,121,87,-79,-92,46,92,-108,-107,79,121,-71,-89,16,-11,-52,72,-114,-32,-60,-9,-57,-4,10,-81,-22,68,74,76,-68,-127,96,-84,69,-3,-26,-106,-3,-87,-65,105,109,122,-103,31,-108,-86,-5,-39,85,88,67,-82,0,-25,93,61,-62,5,-54,-114,-51,-9,-114,20,49,-26,38,19,39,-103,33,-120,37,-97,32,-89,119,111,-124,-99,78,-49,-128,76,-18,-12,-109,96,90,-73,-104,59,-59,-92,123,55,54,-120,-80,-48,-16,-95,96,36,118,-119,-58,93,45,-43,-75,64,38,-2,-72,-111,22,-89,-75,-120,-42,45,108,59,-105,40,27,32,-66,121,-22,-71,-9,118,124,60,-96,47,4,14,-27,64,70,47,-91,-70,1,-44,94,-46,53,4,23,-124,-92,-95,83,-49,-81,40,-80,48,0,39,1,-113,32,40,-21,-1,-110,102,1,-74,-51,40,108,-35,-36,89,84,123,-48,-115,-115,83,-61,114,-127,-61,114,100,-82,-45,60,87,60,19,86,97,-68,40,-66,75,86,-32,-128,88,-57,-27,77,3,-27,43,-39,-62,66,5,-82,45,-104,-78,34,57,96,89,-90,66,-10,37,-110,-30,82,-58,13,94,12,115,35,117,0,80,61,-7,107,-104,-21,21,-70,-93,-94,-51,-61,39,-62,64,-82,-109,76,84,58,-47,-100,52,46,-51,88,91,8,-47,108,-80,25,-58,111,-59,-83,-75,92,98,110,54,106,65,-47,-120,-5,90,-123,101,-61,-85,-93,109,88,0,8,59,86,56,126,17,-26,58,-101,-25,35,0,-123,-3,-56,112,-128,8,17,-52,88,31,-3,105,-56,68,-1,-94,96,-19,10,-22,-88,-10,119,-44,19,42,75,-86,18,-107,89,-82,-120,76,40,84,-122,29,33,-47,17,-50,-13,23,-66,-46,85,-29,-110,42,-68,8,99,-93,-29,101,16,52,-13,127,0,86,-117,-92,-70,-32,-27,127,-123,1,34,-13,92,114,-11,29,-103,-121,-54,20,73,16,74,108,16,-61,89,50,-30,-14,116,44,-31,16,96,24,-51,7,39,-87,-69,-61,-98,61,-46,113,85,-95,103,67,99,-66,-45,-42,-70,96,104,5,-111,69,-25,99,-118,23,109,11,4,-41,-94,73,100,96,6,90,-75,-25,79,-13,-43,-6,-12,51,12,40,124,-56,81,-8,59,-60,-26,-54,33,122,85,53,-99,125,19,-26,94,41,-5,46,-48,-70,-10,41,102,-1,-98,-9,15,29,46,-66,-118,-53,45,119,-127,94,53,-58,90,124,5,-110,-98,-80,-77,77,29,19,105,-121,92,9,-124,50,-119,59,40,67,104,-12,13,103,101,47,-51,34,-66,-101,-117,112,-5,118,-48,-60,-114,38,-71,2,51,114,80,115,-5,116,20,16,-47,-19,30,24,-68,7,-30,-3,-64,-7,-34,-12,44,34,-91,-97,116,112,-99,108,-75,17,26,-14,-61,80,22,-7,34,47,-93,45,106,121,78,43,-97,39,-99,-68,-72,-7,64,-49,-82,-127,78,-64,48,18,15,126,-125,-111,-69,-111,10,-46,111,-75,123,-44,-67,-31,-96,-67,-53,-53,-106,67,-101,23,62,30,9,-114,-12,-57,-38,-78,95,-10,-3,110,88,123,-26,78,-125,114,53,10,-57,26,38,-51,73,92,-124,79,15,75,-62,109,-113,-67,1,35,52,-36,55,7,111,-43,109,101,88,122,-21,-32,-87,59,16,-122,-109,-118,17,-22,-39,53,-105,77,90,-24,-65,43,-27,113,30,-117,-30,106,37,55,59,54,-70,99,99,-73,120,97,-39,-88,-54,101,51,-76,70,-121,-68,23,-73,-31,75,-8,-63,-123,-93,96,-81,99,-95,28,-36,55,-104,32,-64,41,-97,95,-89,126,-26,-25,126,2,-26,-54,110,-86,110,74,-3,-110,56,-60,-49,117,-82,-55,-103,-112,70,-85,85,-63,82,7,75,-61,90,32,35,-115,72,73,-121,63,-84,-52,-29,-59,-4,29,64,119,127,58,-117,48,126,120,-115,-15,-10,27,27,-81,117,-5,121,-72,113,31,-13,10,27,-106,-51,81,-96,-22,19,-78,6,71,-34,123,118,75,-23,-72,-97,111,-121,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+ +#define HIDDEN_STATE_WEIGHT_X4 {-3,69,-33,102,76,60,80,19,59,-2,21,-4,-59,-59,11,-52,117,-25,70,121,-18,44,-74,-14,0,-1,44,-28,15,77,-102,92,108,-48,108,-100,99,-69,-19,121,-47,0,-80,-128,117,-123,99,-27,-118,60,34,-73,65,119,-50,-84,88,42,-91,-32,-108,79,-121,87,-123,118,-108,-88,-9,24,-104,85,8,-113,51,-112,33,118,94,1,26,-113,82,70,-95,-51,110,-96,-80,-98,107,118,-48,60,-97,102,-100,95,-69,77,76,-6,36,15,97,-52,-90,123,1,96,-58,120,17,-99,19,72,86,-109,-115,6,63,26,111,-102,45,35,-88,11,-40,-32,-125,120,38,-119,51,-109,110,113,24,22,123,-18,-23,16,58,6,-69,-68,-20,-112,-43,91,26,84,-31,-33,-37,-126,15,71,-65,103,-37,66,91,-29,-85,121,-47,111,-41,60,-88,-21,6,-120,-109,-76,106,33,-96,37,58,57,-100,10,108,25,78,-117,13,-39,-99,-43,108,93,23,93,1,56,116,41,104,-79,-43,-73,62,-104,86,110,-50,13,-70,77,-108,-107,-45,67,10,107,44,-52,30,111,-53,-113,112,90,74,-61,90,-4,34,58,96,64,79,44,-80,-119,-10,-125,-39,79,-20,67,71,72,-32,-85,-25,-18,-21,-66,0,36,-127,-96,-113,120,49,76,-117,-33,-124,-113,123,87,-49,106,-126,-76,21,-46,98,68,17,-96,-98,20,84,64,86,102,37,-117,92,63,76,-86,23,-60,55,-33,-116,-5,78,13,7,-71,-70,11,-50,-121,-127,56,-4,-105,77,-51,120,63,1,90,-46,-9,47,-56,124,59,-107,-35,59,27,78,-16,114,-33,-21,103,53,120,67,114,-48,74,-65,39,-99,23,6,124,-42,73,-15,-39,-98,-1,-115,99,85,-50,53,-85,-31,-95,116,51,-114,-71,7,-6,64,119,-46,118,-50,106,7,-41,105,-2,-13,30,70,-92,51,-69,-75,102,-101,26,110,-40,50,102,-52,-119,-55,119,20,-121,48,-3,101,-11,-51,2,125,-45,-126,-125,-120,-111,-19,9,-9,0,5,40,34,-115,-15,-5,46,-2,3,-41,81,-117,30,-89,-27,88,-39,-44,70,-7,-123,-11,114,-85,41,83,112,123,-50,-60,-30,19,25,-21,30,23,-72,81,76,-96,79,99,-6,-107,-83,75,71,82,107,43,-11,100,47,-40,-45,124,-97,-99,92,-3,74,89,102,-36,-84,89,67,3,44,-117,108,-100,49,-113,107,103,-26,-2,108,-34,60,47,101,-94,-113,112,-43,101,-37,-69,27,-38,110,39,-91,-101,-91,-28,-61,-37,37,-106,-69,60,59,121,-126,-71,-97,47,32,4,-32,-89,96,16,-89,14,119,-27,68,-11,-53,-52,111,64,-124,70,87,72,20,-114,-99,47,78,-91,54,-32,-24,-60,-49,-70,-128,1,46,-9,-95,-57,76,-44,-18,94,65,-4,-112,10,-12,-46,-109,53,22,-81,60,-22,96,4,90,23,122,68,-22,74,-73,-124,-104,-92,-106,76,-124,-68,59,-95,-59,83,97,-127,-37,96,-92,-49,123,-81,-86,-84,95,69,55,40,54,-80,-110,-3,-8,-26,-120,48,-80,0,44,-106,58,-3,-48,39,-16,1,-12,-87,-120,-65,-95,-113,96,32,-45,105,-86,109,36,40,118,-21,-32,122,-86,-103,-119,-1,-58,-110,-94,31,-14,-108,93,102,45,1,15,-86,29,-5,-43,-74,-75,-51,-8,-39,-114,85,64,40,38,108,71,88,70,67,-2,-35,-72,-36,-93,-82,-69,0,-111,89,22,84,100,-25,-123,93,-89,123,-75,-48,-18,61,-47,-62,-120,-115,-42,-115,-12,5,127,-54,45,83,108,-61,104,-114,-102,-51,59,114,-105,-127,93,-9,-11,-114,40,-61,27,114,-73,20,121,49,32,100,-66,-82,87,-26,-79,38,121,-45,-22,60,-92,19,46,39,-71,87,-9,60,92,-103,-108,33,118,19,124,86,-107,-120,79,37,60,97,-96,-68,40,-51,-66,88,-10,-61,119,89,75,91,86,8,-44,50,19,-30,-32,-47,-128,108,42,-14,75,116,88,-80,-57,25,-86,44,18,-31,-27,-58,77,111,-107,16,89,96,3,-59,-27,-83,-82,24,-120,-51,43,-75,-39,92,76,7,40,39,-62,98,66,110,84,-87,-122,-69,5,54,-82,106,29,-61,33,-98,45,65,-104,-47,-47,61,17,-46,-78,-120,34,-5,-50,113,-13,85,57,90,96,-123,23,-95,-66,103,89,101,-90,-61,-46,67,85,99,66,-85,-10,-93,-29,-66,-110,-45,37,109,-110,88,42,-42,-68,-70,-30,0,82,8,8,96,99,104,-58,59,13,86,-93,5,-29,-111,94,56,12,126,101,69,16,-25,115,17,35,-26,52,99,-13,-118,117,58,0,-101,127,23,0,109,80,-25,61,35,86,11,-117,4,-7,0,107,-123,-92,-41,-70,-94,-104,-3,-21,-56,-32,73,-27,100,21,112,-70,-128,127,96,-123,6,-93,8,-94,17,1,90,34,-75,-51,-52,-61,88,-13,-25,92,79,39,31,-62,-3,114,-13,-11,-43,64,105,-82,-56,29,-6,-103,-12,-109,68,76,-1,-121,51,-54,12,84,-94,58,96,20,40,73,124,-47,-19,-100,10,16,-56,74,81,52,-22,46,-88,108,-8,16,59,-60,-101,-26,-117,-127,-36,78,55,-54,112,33,-5,-64,7,48,111,122,118,85,-48,18,-43,15,109,53,-60,-99,-114,126,101,-125,88,125,38,19,-71,-111,122,-69,-21,-26,2,94,51,-111,-32,10,-87,41,114,-5,80,-46,59,111,16,46,115,-48,-5,-75,-122,123,-109,-70,116,-10,20,-44,-118,-67,17,41,16,102,-47,-31,-22,-96,-39,-1,-19,-98,30,-67,53,-53,-105,-9,24,15,-68,-53,77,-106,90,29,7,46,-30,67,-24,-101,-65,-66,-3,-118,-64,23,43,62,-27,-53,-7,45,-34,30,113,9,30,119,-12,-127,44,-114,-117,-12,-30,94,34,53,-91,-57,106,-38,37,-58,-97,90,116,-78,55,95,59,124,112,5,-99,-10,54,-3,-70,-110,108,-98,-75,110,99,88,99,-80,17,-77,26,123,-73,-26,120,77,-14,29,-61,78,97,-125,-39,19,80,105,22,114,-88,53,-54,-121,-7,92,34,10,101,-57,51,9,47,-124,-93,26,-76,38,70,50,45,-119,106,-51,-121,73,-68,59,121,40,78,92,23,-124,-73,67,43,104,-97,79,-31,15,75,-12,39,13,-99,75,-8,-62,-63,103,-68,101,-72,109,-123,-113,-93,47,-7,-51,64,-67,96,1,-81,34,-49,-66,-82,35,99,52,-95,28,27,-36,27,-93,-15,52,-68,55,-81,-104,117,67,-3,53,102,32,-5,-64,121,-31,-10,19,-123,41,-72,-97,113,45,-10,-111,-71,95,31,-89,-13,36,-111,39,86,126,10,-26,27,-91,48,-77,-45,-25,-106,126,-51,104,101,71,81,2,81,-26,-96,7,-114,-44,-94,-54,-22,110,19,-76,77,3,-127,-86,-78,110,6,-62,-96,121,-100,74,71,-3,-34,43,86,37,109,-110,123,56,118,-7,-33,-96,15,-60,75,-49,-23,-6,-34,57,60,117,-72,-82,-97,-104,88,30,-86,-55,111,-103,-121,-126,-63,-94,-103,-112,0,70,80,118,-46,-44,101,-85,28,85,52,91,-127,29,-88,-63,95,82,59,124,90,-86,-37,7,-116,75,72,-13,82,55,-125,-61,80,90,-75,41,-28,-41,-6,32,-62,35,88,91,61,-112,-104,-115,23,72,-102,-25,77,103,0,73,13,-121,6,81,-52,-70,59,63,113,-84,-85,-112,-9,113,-82,-52,98,-29,45,-25,59,-73,-78,-59,-96,-4,-32,-82,79,16,80,29,94,64,-7,67,-77,-5,-125,119,12,127,-9,104,-95,56,16,58,86,-117,18,66,26,-115,-55,48,59,126,-15,-90,-16,-126,15,120,75,-115,13,106,-76,80,-9,-15,-70,-10,50,-78,56,-51,110,85,-29,-102,20,15,-56,-73,-64,-23,-66,-12,-80,-128,-6,-121,-103,-6,-122,-97,40,46,-36,30,-2,-34,-2,32,116,-93,-59,-109,34,-79,126,-95,-120,-15,-40,-86,-64,71,-48,126,124,-2,-39,75,-64,127,57,30,-107,1,-74,-32,-105,-112,104,-115,80,-27,50,-86,-86,75,-13,-8,81,-13,-66,-38,-14,125,118,103,33,48,-71,10,35,-118,88,65,119,-36,-116,-107,-20,-43,-110,107,33,-27,15,-48,-119,46,-35,96,-75,88,-12,-7,90,-41,-6,-87,89,-88,-117,98,-29,-64,-41,-18,99,-83,13,61,-8,126,46,82,127,-81,-75,20,57,10,-36,81,54,-123,67,18,124,45,-55,95,50,-41,-38,-127,66,61,24,9,51,-55,113,-66,-80,28,49,-113,-71,24,113,-107,105,-71,37,47,-117,73,45,30,-74,117,114,26,6,-42,-80,-74,108,-81,110,73,88,124,-24,-43,-3,49,84,-55,-30,-125,36,102,62,-126,-45,-33,-50,98,-8,6,109,62,113,-84,-12,32,-40,24,-101,-87,-57,-56,59,-123,106,32,12,-71,-18,97,49,113,-47,105,-113,49,99,-124,-124,-81,-118,117,-12,-76,46,-9,-48,-41,-3,-54,-86,97,88,119,-82,-113,-52,-126,-93,-23,-121,127,-97,-28,-24,31,-62,-119,52,-93,75,7,33,-101,-67,67,-45,39,74,-83,127,-115,-66,4,-6,-18,-29,29,-23,68,-123,-103,31,24,117,49,8,-70,41,1,20,71,99,-40,-21,-116,-30,93,66,95,27,63,117,-49,20,-113,-92,-7,127,115,-85,97,-39,34,-67,-10,-53,123,-87,119,2,-77,68,-74,-66,22,96,-13,-12,96,-26,86,35,47,-128,-4,83,52,114,-2,-84,-14,67,-94,-53,-45,-74,-71,-94,94,-101,-122,3,-48,-14,124,-43,56,-3,58,-22,-97,-106,1,-32,57,-16,-127,51,23,-67,-59,-27,-60,125,-46,-125,-117,28,-74,29,29,-76,94,25,58,-32,-31,-101,-105,42,49,101,-115,-60,114,-55,-72,101,94,35,-14,-6,-115,-101,20,-36,-8,103,77,-42,82,61,104,85,35,-71,100,111,67,107,-90,-24,19,6,117,-87,-16,-67,-26,26,24,105,-64,102,105,-36,-7,60,109,112,-19,119,59,-81,10,-91,-9,69,124,-54,124,52,80,13,-105,21,-116,-114,-33,5,0,10,126,-93,22,-26,-115,115,94,22,105,-111,30,-7,102,44,63,0,85,-38,91,-30,98,-21,43,4,-63,-34,-124,-67,38,33,-2,45,-32,-86,12,-92,-38,29,39,121,-119,-42,-23,-30,-106,3,-12,-54,-108,7} + +#define UPDATE_GATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103} + +#define RESET_GATE_BIAS {-77,67,-93,-3,98,59,-121,33,49,50,41,91,-115,-33,71,47,-70,45,89,-115,72,106,-22,100,97,-100,-95,108,-33,3,14,30} + +#define HIDDEN_STATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103} + +#define INPUT_DATA1 {-367,-338,0,-89,453,-413,-343,-16,42,418,201,274,-352,477,-290,-92,266,-49,342,453,-398,247,-153,328,217,342,85,69,-38,351,73,128} + +#define INPUT_DATA2 {280,41,-322,61,315,350,504,-227,-221,-483,352,252,455,-236,344,364,-378,229,-187,-498,295,357,-511,58,-349,-458,-420,-66,-400,-379,477,-60} + +#define HISTORY_DATA {-38,53,105,-79,-463,51,-343,-226,-435,-282,218,441,-299,-215,-109,335,340,-471,-109,273,33,-245,-469,170,-26,-59,192,-119,76,-6,236,-145} diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt new file mode 100644 index 0000000..fdfe60f --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt @@ -0,0 +1,4 @@ +CMSIS NN Lib example arm_nnexample_gru0 for + Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10.cpp b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10.cpp new file mode 100644 index 0000000..471899c --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10.cpp @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_cifar10.cpp +* +* Description: Convolutional Neural Network Example +* +* Target Processor: Cortex-M4/Cortex-M7 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of Arm LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup CNNExample Convolutional Neural Network Example + * + * \par Description: + * \par + * Demonstrates a convolutional neural network (CNN) example with the use of convolution, + * ReLU activation, pooling and fully-connected functions. + * + * \par Model definition: + * \par + * The CNN used in this example is based on CIFAR-10 example from Caffe [1]. + * The neural network consists + * of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a + * fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will + * be classified into one of the 10 output classes. + * This example model implementation needs 32.3 KB to store weights, 40 KB for activations and + * 3.1 KB for storing the \c im2col data. + * + * \image html CIFAR10_CNN.gif "Neural Network model definition" + * + * \par Variables Description: + * \par + * \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices + * \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays + * \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases + * \li \c input_data points to the input image data + * \li \c output_data points to the classification output + * \li \c col_buffer is a buffer to store the \c im2col output + * \li \c scratch_buffer is used to store the activation data (intermediate layer outputs) + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_convolve_HWC_q7_RGB() + * - arm_convolve_HWC_q7_fast() + * - arm_relu_q7() + * - arm_maxpool_q7_HWC() + * - arm_avepool_q7_HWC() + * - arm_fully_connected_q7_opt() + * - arm_fully_connected_q7() + * + * Refer + * \link arm_nnexamples_cifar10.cpp \endlink + * + * \par [1] https://github.com/BVLC/caffe + */ + +#include +#include +#include "arm_math.h" +#include "arm_nnexamples_cifar10_parameter.h" +#include "arm_nnexamples_cifar10_weights.h" + +#include "arm_nnfunctions.h" +#include "arm_nnexamples_cifar10_inputs.h" + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif +#endif + +// include the input and weights + +static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT; +static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS; + +static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT; +static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS; + +static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT; +static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS; + +static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT; +static q7_t ip1_bias[IP1_OUT] = IP1_BIAS; + +/* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */ +uint8_t image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA; +q7_t output_data[IP1_OUT]; + +//vector buffer: max(im2col buffer,average pool buffer, fully connected buffer) +q7_t col_buffer[2 * 5 * 5 * 32 * 2]; + +q7_t scratch_buffer[32 * 32 * 10 * 4]; + +int main() +{ + #ifdef RTE_Compiler_EventRecorder + EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder + #endif + + printf("start execution\n"); + /* start the execution */ + + q7_t *img_buffer1 = scratch_buffer; + q7_t *img_buffer2 = img_buffer1 + 32 * 32 * 32; + + /* input pre-processing */ + int mean_data[3] = INPUT_MEAN_SHIFT; + unsigned int scale_data[3] = INPUT_RIGHT_SHIFT; + for (int i=0;i<32*32*3; i+=3) { + img_buffer2[i] = (q7_t)__SSAT( ((((int)image_data[i] - mean_data[0])<<7) + (0x1<<(scale_data[0]-1))) + >> scale_data[0], 8); + img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1))) + >> scale_data[1], 8); + img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1))) + >> scale_data[2], 8); + } + + // conv1 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING, + CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM, + (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH); + + // pool1 img_buffer1 -> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM, + POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2); + + // conv2 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM, + CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1, + CONV2_OUT_DIM, (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH); + + // pool2 img_buffer1 -> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM, + POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2); + +// conv3 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM, + CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1, + CONV3_OUT_DIM, (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH); + + // pool3 img_buffer-> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM, + POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2); + + arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias, + output_data, (q15_t *) img_buffer1); + + arm_softmax_q7(output_data, 10, output_data); + + for (int i = 0; i < 10; i++) + { + printf("%d: %d\n", i, output_data[i]); + } + + return 0; +} diff --git a/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_inputs.h b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_inputs.h new file mode 100644 index 0000000..c600c5a --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_inputs.h @@ -0,0 +1,6 @@ +/* Here are two different test images */ + +//#define IMG_DATA {158,112,49,159,111,47,165,116,51,166,118,53,160,112,46,156,109,41,162,115,47,159,113,45,158,111,44,159,113,41,161,116,41,160,111,52,161,111,49,166,117,41,169,117,45,170,119,44,167,117,40,162,113,38,160,111,39,160,112,43,156,109,44,149,107,45,150,107,45,148,106,43,149,107,44,143,101,39,140,98,43,141,97,41,143,97,38,137,95,36,126,91,36,116,85,33,152,112,51,151,110,40,159,114,45,166,116,56,162,112,49,160,113,43,164,117,47,162,114,45,163,116,46,156,110,38,155,111,41,159,110,54,163,113,52,170,119,41,171,117,40,171,115,33,169,115,30,160,111,33,154,112,41,151,115,50,145,110,53,139,104,55,140,102,52,141,100,48,149,105,50,147,102,46,145,102,45,142,97,38,143,98,34,136,95,31,125,91,32,119,88,34,151,110,47,151,109,33,158,111,36,167,111,48,160,106,42,163,115,44,165,117,45,165,117,45,163,115,43,162,115,43,158,114,48,157,109,57,161,111,51,166,115,38,167,114,37,169,113,35,170,116,39,159,114,47,145,111,54,121,96,49,110,90,52,98,78,50,101,77,47,114,85,50,120,86,48,134,96,55,143,103,51,140,99,39,142,99,35,139,98,34,130,95,34,120,89,33,155,107,40,155,110,32,160,109,31,174,112,44,167,110,43,167,117,46,169,120,48,169,119,48,165,115,44,165,117,45,167,123,57,191,146,95,177,130,75,157,111,41,162,115,47,164,114,54,158,112,58,149,111,67,104,80,47,103,87,65,98,90,76,92,90,84,80,75,66,74,63,50,86,70,52,83,62,39,113,85,45,132,98,46,140,102,43,140,101,39,136,99,39,127,94,36,155,107,41,156,114,48,161,115,49,170,114,47,169,114,43,163,113,40,169,120,47,166,116,44,164,113,41,164,116,42,173,128,59,246,214,164,195,156,107,151,114,56,146,111,60,142,108,71,111,80,50,78,53,31,85,69,56,113,103,98,112,110,111,106,114,118,97,102,105,93,94,93,74,72,67,84,78,70,85,73,47,105,83,45,128,96,48,138,101,46,133,94,36,129,93,36,148,109,54,133,104,64,130,100,57,147,112,53,161,115,44,165,113,39,167,116,41,167,115,41,163,111,37,165,116,39,163,118,42,180,138,85,157,122,78,128,102,58,97,75,43,66,50,31,69,58,43,66,56,45,89,83,76,118,113,110,122,121,120,119,122,122,114,116,116,94,96,96,99,100,97,91,91,86,58,58,47,67,58,37,108,84,49,140,105,58,138,98,44,134,95,40,127,100,57,109,95,80,47,37,17,88,74,28,153,117,48,170,118,43,168,115,40,170,118,43,169,117,42,166,116,37,164,120,39,147,107,52,129,98,59,127,108,75,100,87,70,68,67,57,78,83,72,72,75,64,83,84,74,132,130,121,146,142,132,124,118,108,105,99,90,107,102,94,115,111,103,85,83,77,63,71,69,46,47,39,79,61,36,132,98,58,141,99,48,134,93,39,131,115,90,99,96,92,42,43,38,70,64,41,143,111,56,167,117,42,165,114,36,168,116,39,171,119,49,161,113,51,140,109,51,120,94,49,130,110,77,144,131,107,116,106,93,88,87,79,91,95,88,85,88,82,77,77,69,124,118,107,163,153,140,136,124,112,102,93,81,106,98,88,100,93,84,85,81,74,54,60,58,49,53,49,57,47,32,107,83,50,138,103,51,136,97,39,170,161,144,103,105,105,54,58,59,124,121,113,153,124,82,161,113,43,163,117,41,166,122,50,165,121,66,174,135,95,113,89,59,125,105,78,157,141,121,156,143,128,121,111,101,86,80,74,82,81,77,84,85,82,80,78,73,81,71,61,138,125,112,146,135,123,113,103,93,87,79,70,83,77,69,86,82,76,71,73,67,56,57,53,40,35,27,74,59,35,133,106,59,137,103,45,180,176,163,134,139,143,94,100,105,154,154,149,174,149,112,158,116,51,156,116,47,153,118,60,207,180,146,237,214,198,207,180,166,156,131,119,174,153,145,148,131,125,125,110,107,93,85,79,86,84,79,74,74,71,59,57,53,76,68,58,137,125,112,143,133,122,133,124,114,106,98,89,86,81,74,87,85,78,84,85,78,75,76,71,50,49,43,40,30,15,95,75,44,132,103,57,183,183,175,108,116,122,142,151,158,165,169,168,177,156,122,155,112,50,159,118,51,122,89,47,213,197,179,237,224,226,220,191,188,164,135,131,183,159,155,156,137,132,125,108,104,120,111,104,78,76,69,80,80,77,45,44,40,91,85,77,175,165,154,157,147,137,155,147,138,107,100,92,87,83,77,103,102,96,88,88,79,78,79,73,59,59,59,41,36,33,59,46,31,104,81,46,188,191,189,100,108,116,135,144,153,170,175,178,187,167,136,166,120,59,173,123,55,134,93,44,117,95,80,194,182,188,199,171,164,170,142,133,185,161,151,189,171,159,134,119,106,117,107,95,102,98,89,84,84,79,38,38,34,125,121,113,210,201,192,160,152,142,146,139,130,93,89,82,83,80,75,94,93,88,104,104,94,85,87,81,73,75,78,55,53,55,62,55,48,76,56,26,189,194,194,90,96,105,127,134,144,175,180,185,174,156,133,166,123,68,178,123,53,159,109,47,97,68,44,168,154,152,168,144,126,137,114,94,186,166,148,216,202,183,160,149,129,123,113,98,120,114,105,115,114,109,50,50,47,150,147,140,194,187,178,155,149,140,123,118,111,91,88,83,84,83,79,84,84,80,95,95,85,86,87,81,84,87,89,73,73,73,79,74,64,73,55,24,189,192,193,93,95,103,152,154,163,185,188,192,119,110,98,136,106,66,173,124,58,167,116,50,103,72,39,147,132,120,145,125,103,167,149,127,189,174,155,226,216,200,180,172,157,141,131,117,126,117,107,117,114,109,71,71,68,154,152,147,186,181,174,149,144,136,114,110,104,87,85,80,80,80,76,72,73,70,80,80,72,99,100,94,100,101,99,90,88,81,97,89,69,94,73,34,194,196,196,108,107,112,168,167,172,186,186,188,105,109,109,99,89,67,156,119,62,167,122,55,100,74,34,115,106,88,138,123,103,198,185,169,190,180,169,172,165,159,145,140,140,154,143,134,146,136,125,103,100,95,71,71,70,152,152,149,179,175,170,137,13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3,71,107,133,49,89,114,31,77,105,27,71,105,38,82,117,49,93,128,56,100,135,58,102,137,53,92,128,56,94,131,60,99,137,57,99,139,53,97,138,50,95,137,45,94,136,39,88,131,33,83,125,42,91,133,62,112,154,79,132,179,73,131,181,56,116,168,38,97,146,13,64,108,40,85,127,61,116,168,49,102,148,35,85,132,43,91,143,39,90,139,42,92,134,44,88,125,40,81,112,42,85,115,27,72,104,23,67,102,30,74,109,27,71,106,29,73,108,36,80,115,47,86,120,56,95,128,62,101,135,66,109,144,75,119,156,69,113,152,49,95,134,43,88,127,43,88,127,60,105,144,85,130,170,109,156,197,93,145,190,60,115,164,26,82,130,29,82,126,20,64,107,54,107,160,56,105,149,45,89,132,43,86,134,40,89,134,40,92,132,40,87,123,38,81,115,36,79,114,26,69,105,22,66,101,29,73,108,25,69,104,29,73,108,19,63,98,18,58,89,32,70,100,47,87,118,61,104,137,74,119,152,66,111,145,53,96,131,52,95,130,45,87,123,67,109,145,89,131,167,105,146,182,89,135,175,48,99,145,24,77,124,34,84,129,21,67,110} + + +#define IMG_DATA {235,235,235,231,231,231,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,232,233,233,231,233,232,231,233,231,233,233,230,233,232,232,232,234,232,231,234,232,232,232,233,233,230,232,233,231,233,233,233,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,232,232,232,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,237,234,233,236,234,233,236,236,234,234,236,234,234,235,237,234,234,238,235,236,237,236,236,235,236,236,234,236,236,236,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,235,235,235,237,237,237,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,234,234,236,233,231,236,234,231,235,235,234,234,235,236,227,230,233,231,235,238,231,233,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,234,233,233,230,232,232,231,228,230,232,223,226,231,186,192,197,209,216,219,207,210,213,228,228,230,236,235,235,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,237,237,237,234,234,234,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,236,238,236,233,237,237,219,225,230,203,210,219,163,172,179,195,205,208,214,218,221,230,229,232,237,235,237,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,239,239,238,236,235,235,236,235,235,236,235,235,236,235,235,236,235,235,235,236,235,235,235,235,234,234,234,235,235,235,237,236,236,237,236,236,234,235,236,232,233,234,235,237,237,229,231,232,208,216,218,194,205,210,185,198,207,174,188,200,165,179,189,184,196,202,207,215,220,226,228,232,236,235,237,236,236,235,236,236,235,236,236,235,236,236,236,237,237,237,237,237,237,237,237,237,228,229,229,228,227,228,232,230,231,231,228,230,234,232,233,237,236,236,237,237,235,236,237,235,237,235,236,237,235,236,239,236,237,239,237,238,225,229,230,224,228,229,233,237,238,221,226,228,183,197,204,161,180,190,159,180,191,154,176,190,144,163,177,143,159,171,156,169,177,198,206,211,233,238,239,236,237,234,235,236,233,235,235,235,235,236,236,236,238,237,237,237,237,239,237,238,212,220,222,224,230,233,230,234,238,227,232,234,229,234,234,234,237,236,237,238,235,238,237,236,239,237,238,239,237,238,239,236,237,240,238,239,201,204,203,219,222,221,233,236,235,214,218,218,193,204,210,185,201,210,184,201,211,173,191,203,165,182,196,159,174,187,162,176,185,186,199,204,229,239,240,234,239,238,233,238,237,233,238,238,234,239,238,236,239,238,237,239,238,238,238,238,216,234,241,221,236,243,225,238,246,225,239,243,227,240,240,231,238,237,236,237,235,238,236,235,238,236,237,238,236,237,237,237,237,239,239,239,197,198,196,220,221,218,233,234,231,230,231,229,209,213,217,209,216,222,219,228,235,208,218,227,209,221,234,210,224,235,217,233,240,218,235,241,225,240,243,228,238,240,228,239,240,230,240,240,230,240,239,235,240,239,237,240,239,238,238,238,118,140,149,119,138,148,124,142,153,136,155,161,172,188,191,225,234,233,235,236,233,237,234,232,236,233,234,235,235,235,235,237,236,233,237,235,214,216,214,226,228,226,232,234,232,236,237,236,228,230,232,227,230,235,231,236,241,225,232,239,225,237,247,217,233,243,201,219,226,185,204,211,172,189,195,167,179,186,167,180,185,186,199,201,223,235,235,235,241,239,236,240,239,238,240,239,109,130,141,103,121,133,108,125,137,111,127,137,146,159,165,222,229,231,227,228,225,229,226,224,236,232,233,234,234,234,231,236,234,230,237,235,229,234,235,231,235,236,232,237,238,230,235,236,231,236,238,231,237,240,229,237,241,223,232,238,191,206,213,164,184,191,146,165,172,137,156,163,134,149,159,128,140,153,121,133,143,149,162,166,216,228,229,234,241,239,235,240,238,237,240,239,195,212,224,188,202,215,199,211,224,200,211,223,209,217,227,223,227,231,213,213,211,211,209,206,216,213,214,220,222,222,219,226,225,210,221,219,209,219,223,211,221,225,216,225,230,220,229,233,225,234,237,226,236,239,225,237,241,218,231,237,183,204,208,175,198,203,181,200,207,178,194,202,186,197,211,170,178,196,142,151,164,185,195,202,219,230,233,231,240,238,234,241,239,236,240,239,193,207,222,191,202,217,202,211,224,214,217,234,223,225,241,214,219,227,203,208,208,171,174,174,177,180,183,207,213,214,174,184,188,98,112,121,93,114,126,101,121,132,111,129,139,122,138,147,137,152,161,153,167,174,202,216,220,223,236,237,218,232,235,220,233,238,223,234,240,217,226,233,221,228,237,212,219,229,196,203,212,222,230,237,219,227,234,221,230,233,232,239,242,235,241,242,113,130,152,111,125,147,113,125,141,125,131,151,138,145,165,170,182,193,191,201,205,190,199,204,208,219,226,216,230,234,158,172,183,54,71,92,45,70,91,49,73,91,53,73,90,66,84,98,102,114,129,159,168,179,221,227,233,234,239,241,233,237,241,227,231,237,223,228,233,207,211,217,202,208,212,211,218,220,212,219,223,199,206,214,179,186,196,188,197,205,211,221,227,221,231,234,61,81,108,69,86,114,63,79,100,68,85,102,123,141,155,139,155,164,151,157,164,195,200,207,214,228,234,206,223,228,163,180,190,103,121,138,95,112,131,101,117,135,138,151,168,181,192,207,207,212,223,221,222,232,219,219,227,205,203,212,183,186,195,158,166,174,147,154,163,131,138,147,125,133,140,130,139,144,136,146,152,133,142,151,128,137,147,138,153,160,182,197,203,197,212,216,40,53,77,58,70,94,85,98,116,127,144,153,132,151,156,96,107,110,119,115,118,163,158,161,173,180,182,184,194,197,182,194,198,181,193,200,183,194,202,198,209,217,218,228,236,200,210,217,174,181,186,159,165,172,145,150,159,132,136,149,116,125,138,98,111,123,94,106,118,99,111,123,105,118,128,107,121,130,122,135,145,138,151,161,150,164,174,157,174,184,188,206,213,185,203,208,13,15,35,26,29,47,134,140,151,206,216,220,138,150,150,118,123,123,141,133,134,172,162,162,181,181,180,207,209,211,220,224,225,228,234,233,224,234,232,230,241,240,226,238,238,176,189,190,144,159,163,138,154,162,142,158,170,145,163,177,154,171,187,149,165,182,149,165,182,154,171,187,157,174,189,160,177,191,173,190,204,187,204,217,190,207,218,178,196,208,165,183,193,157,175,183,5,5,24,58,62,79,200,207,217,225,232,239,197,205,212,199,207,211,212,212,218,226,224,229,229,230,237,233,236,246,232,238,245,230,238,239,209,221,220,223,238,239,221,238,241,210,228,234,198,217,228,180,200,214,193,216,230,188,213,229,189,212,231,194,214,234,192,212,232,184,204,224,172,193,212,171,191,209,161,181,197,144,165,179,136,156,169,131,146,161,128,143,158,138,154,165,39,45,71,145,155,179,190,204,222,186,196,216,184,197,217,192,211,229,194,211,230,194,208,227,194,206,227,191,203,228,192,207,228,190,207,221,177,193,207,180,198,215,154,176,193,147,169,188,145,161,184,156,171,195,146,163,186,113,133,156,114,137,161,132,157,180,126,150,173,111,135,158,92,115,138,91,112,135,93,114,133,94,116,131,105,125,140,121,133,151,129,141,158,129,142,156,122,135,161,162,179,207,143,160,194,137,154,189,131,152,187,128,152,190,127,150,192,130,150,193,131,150,192,128,147,190,127,147,189,129,149,189,129,149,188,124,145,186,104,126,163,100,122,154,102,120,154,118,134,170,112,128,163,94,109,145,94,112,148,94,117,153,87,112,144,83,103,136,80,97,130,83,103,134,93,111,139,101,117,141,108,121,144,115,125,146,121,133,148,130,144,156,73,87,109,76,90,113,77,90,122,80,93,127,84,98,134,87,102,142,87,102,147,90,105,150,94,111,152,102,119,160,107,124,165,113,131,172,115,137,181,118,136,186,118,132,180,120,133,175,115,136,172,110,133,168,106,127,163,100,119,155,95,109,148,85,101,139,79,97,132,80,92,127,80,94,129,77,100,133,80,100,129,82,98,122,92,104,126,113,119,138,125,135,146,136,149,156,13,25,41,3,11,25,9,16,35,18,26,48,18,26,52,21,25,56,20,25,58,22,30,61,26,36,62,34,43,70,42,51,77,48,59,87,52,69,106,60,75,121,66,77,126,70,79,126,71,87,127,72,88,126,67,81,120,60,72,112,55,67,106,53,68,104,53,69,103,57,69,102,57,71,105,57,78,110,72,89,115,87,100,119,104,113,128,120,124,136,130,136,141,137,146,149,36,46,55,11,16,20,8,13,19,32,44,53,36,45,58,22,25,41,8,11,30,3,8,24,1,4,17,0,2,15,0,2,15,0,4,20,6,13,42,5,18,56,1,19,60,3,23,62,13,29,71,24,38,81,21,33,77,21,31,76,21,38,78,22,44,79,30,50,83,39,58,90,57,70,101,85,90,118,113,115,138,123,123,138,116,115,125,122,123,128,134,139,137,153,160,158,35,41,45,26,27,26,13,19,18,27,41,41,71,81,84,70,70,76,49,50,57,27,31,37,15,15,21,5,5,11,2,2,7,0,0,7,17,17,35,57,64,91,31,50,78,10,36,62,4,30,60,4,30,62,7,30,63,14,35,69,25,43,74,41,55,83,62,71,99,86,97,123,122,124,146,144,131,149,132,120,135,114,105,114,117,111,116,132,134,133,146,152,146,172,179,175,16,15,17,13,10,9,4,10,8,3,12,11,45,44,46,65,52,57,54,43,47,36,33,35,18,18,20,4,4,7,2,2,4,0,1,3,7,8,15,118,117,134,161,158,179,131,128,148,112,112,131,105,105,125,105,103,124,109,105,127,118,107,126,138,115,133,154,126,144,151,126,141,127,106,116,105,86,91,106,94,97,120,116,116,129,130,129,142,147,144,164,172,165,184,194,190,40,40,35,12,10,7,0,3,3,0,4,4,12,6,7,30,12,17,32,12,17,21,10,12,7,6,7,2,1,3,2,1,2,3,2,3,0,0,2,68,58,64,182,128,146,205,130,148,196,127,144,194,123,141,195,119,137,187,113,129,172,110,122,150,96,106,123,75,83,103,66,69,95,71,70,104,93,88,122,118,113,129,132,126,132,141,135,152,162,158,171,182,176,185,197,194,69,77,64,26,29,21,1,1,1,1,1,2,4,1,0,12,2,5,18,3,9,12,2,5,4,1,2,2,0,0,2,0,0,4,0,1,1,1,1,32,12,11,153,45,59,203,47,68,195,46,67,191,48,69,179,50,67,155,49,59,119,42,49,91,38,42,81,48,46,94,77,71,117,110,102,125,126,116,125,128,120,129,135,128,144,153,147,162,176,171,173,187,183,184,198,196,83,94,82,47,52,43,1,1,1,2,1,2,2,0,0,5,1,2,7,1,5,4,0,2,1,0,0,1,0,0,1,0,0,3,0,0,1,2,0,27,3,2,142,25,38,205,32,54,198,25,46,169,25,43,121,25,36,85,29,34,74,41,39,85,66,56,102,92,82,121,113,105,128,124,115,122,126,115,121,127,118,132,139,131,147,157,150,165,179,174,176,191,187,186,201,199,92,102,93,54,60,50,6,7,3,3,2,1,2,2,0,1,3,1,1,3,3,1,2,2,1,1,1,1,0,0,1,0,0,1,1,1,0,3,2,15,1,0,102,19,28,157,31,47,117,17,23,74,13,12,56,27,22,74,58,55,99,90,81,115,115,99,122,126,111,124,124,112,123,123,113,125,130,119,128,135,126,136,145,137,148,159,151,162,176,171,177,192,188,188,202,201,87,99,89,43,51,37,19,23,11,11,12,4,8,10,2,5,11,4,2,10,4,2,7,2,3,4,1,3,4,1,3,4,1,2,3,2,0,6,6,4,5,2,42,13,13,71,21,24,53,27,25,57,50,41,80,77,62,113,98,82,132,113,101,134,126,113,123,126,112,116,125,111,120,128,115,131,138,126,139,148,137,143,154,145,156,168,161,169,184,179,182,197,193,188,202,201,82,96,82,46,57,36,36,44,22,31,35,17,27,30,15,22,28,15,17,26,13,16,23,12,18,21,12,19,21,13,20,22,14,19,23,15,19,27,20,23,31,21,37,40,27,64,55,45,87,70,67,104,88,81,116,102,85,128,112,88,139,121,105,131,122,110,117,122,107,115,127,112,123,133,119,131,139,127,139,149,138,148,160,151,159,172,164,174,189,183,185,200,196,187,202,200,85,101,83,62,75,48,58,67,38,55,61,37,51,56,35,47,53,33,46,53,34,48,55,38,49,55,40,51,56,41,53,58,44,55,62,46,59,67,45,68,71,48,81,84,59,104,96,74,116,103,83,127,109,92,133,116,97,127,121,97,127,127,107,118,124,106,114,125,108,122,131,117,129,136,123,136,145,133,141,152,141,149,162,153,158,171,163,168,183,178,180,195,191,186,200,199} diff --git a/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_parameter.h b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_parameter.h new file mode 100644 index 0000000..09d0ca3 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_parameter.h @@ -0,0 +1,43 @@ +#define CONV1_IM_DIM 32 +#define CONV1_IM_CH 3 +#define CONV1_KER_DIM 5 +#define CONV1_PADDING 2 +#define CONV1_STRIDE 1 +#define CONV1_OUT_CH 32 +#define CONV1_OUT_DIM 32 + +#define POOL1_KER_DIM 3 +#define POOL1_STRIDE 2 +#define POOL1_PADDING 0 +#define POOL1_OUT_DIM 16 + +#define CONV2_IM_DIM 16 +#define CONV2_IM_CH 32 +#define CONV2_KER_DIM 5 +#define CONV2_PADDING 2 +#define CONV2_STRIDE 1 +#define CONV2_OUT_CH 16 +#define CONV2_OUT_DIM 16 + +#define POOL2_KER_DIM 3 +#define POOL2_STRIDE 2 +#define POOL2_PADDING 0 +#define POOL2_OUT_DIM 8 + +#define CONV3_IM_DIM 8 +#define CONV3_IM_CH 16 +#define CONV3_KER_DIM 5 +#define CONV3_PADDING 2 +#define CONV3_STRIDE 1 +#define CONV3_OUT_CH 32 +#define CONV3_OUT_DIM 8 + +#define POOL3_KER_DIM 3 +#define POOL3_STRIDE 2 +#define POOL3_PADDING 0 +#define POOL3_OUT_DIM 4 + +#define IP1_DIM 4*4*32 +#define IP1_IM_DIM 4 +#define IP1_IM_CH 32 +#define IP1_OUT 10 diff --git a/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_weights.h b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_weights.h new file mode 100644 index 0000000..8d92d21 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_weights.h @@ -0,0 +1,26 @@ +#define CONV1_WT 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+ +#define CONV1_BIAS {-49,-18,-7,-20,-12,-15,7,2,-10,-84,-72,-65,-53,-6,-87,-63,-64,-28,-28,-4,-3,-10,-52,-15,-5,-7,-31,-44,-102,-19,-5,-65} + +#define CONV2_WT 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+ +#define CONV2_BIAS {55,50,34,43,-37,35,-21,10,35,-53,-76,7,14,-1,92,20} + +#define CONV3_WT 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+ +#define CONV3_BIAS {18,36,-46,-45,64,8,13,-19,28,1,14,-57,23,20,-2,32,48,-11,85,73,-7,52,125,33,125,13,92,-72,89,-1,11,70} + +#define IP1_WT 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34,-1,-20} + +#define IP1_BIAS {30,-121,-51,77,40,20,46,-35,28,-33} + +#define CONV1_BIAS_LSHIFT 6 +#define CONV1_OUT_RSHIFT 9 +#define CONV2_BIAS_LSHIFT 4 +#define CONV2_OUT_RSHIFT 9 +#define CONV3_BIAS_LSHIFT 1 +#define CONV3_OUT_RSHIFT 7 +#define IP1_BIAS_LSHIFT 1 +#define IP1_OUT_RSHIFT 8 +#define INPUT_MEAN_SHIFT {125,123,114} +#define INPUT_RIGHT_SHIFT {8,8,8} diff --git a/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/readme_iar.txt b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/readme_iar.txt new file mode 100644 index 0000000..8ca1d5c --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/readme_iar.txt @@ -0,0 +1,7 @@ +CMSIS NN Lib example arm_nnexample_cifar10 for + Cortex-M0, Cortex-M3, Cortex-M4 and Cortex-M7. + +The example is configured for IAR Embedded Workbench for ARM Simulator. + +When changing target, remember to change the ARM_MATH_CMx and __FPU_PRESENT +Preprocessor defines for C/C++ Compiler diff --git a/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru.cpp b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru.cpp new file mode 100644 index 0000000..340dc33 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru.cpp @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_gru.cpp +* +* Description: Gated Recurrent Unit Example +* +* Target Processor: Cortex-M4/Cortex-M7 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of Arm LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GRUExample Gated Recurrent Unit Example + * + * \par Description: + * \par + * Demonstrates a gated recurrent unit (GRU) example with the use of fully-connected, + * Tanh/Sigmoid activation functions. + * + * \par Model definition: + * \par + * GRU is a type of recurrent neural network (RNN). It contains two sigmoid gates and one hidden + * state. + * \par + * The computation can be summarized as: + * 
z[t] = sigmoid( W_z ⋅ {h[t-1],x[t]} )
+ * r[t] = sigmoid( W_r ⋅ {h[t-1],x[t]} ) 
+ * n[t] = tanh( W_n ⋅ [r[t] × {h[t-1], x[t]} ) 
+ * h[t] = (1 - z[t]) × h[t-1] + z[t] × n[t]
+ * \image html GRU.gif "Gate Recurrent Unit Diagram" + * + * \par Variables Description: + * \par + * \li \c update_gate_weights, \c reset_gate_weights, \c hidden_state_weights are weights corresponding to update gate (W_z), reset gate (W_r), and hidden state (W_n). + * \li \c update_gate_bias, \c reset_gate_bias, \c hidden_state_bias are layer bias arrays + * \li \c test_input1, \c test_input2, \c test_history are the inputs and initial history + * + * \par + * The buffer is allocated as: + * \par + * | reset | input | history | update | hidden_state | + * \par + * In this way, the concatination is automatically done since (reset, input) and (input, history) + * are physically concatinated in memory. + * \par + * The ordering of the weight matrix should be adjusted accordingly. + * + * + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fully_connected_mat_q7_vec_q15_opt() + * - arm_nn_activations_direct_q15() + * - arm_mult_q15() + * - arm_offset_q15() + * - arm_sub_q15() + * - arm_copy_q15() + * + * Refer + * \link arm_nnexamples_gru.cpp \endlink + * + */ + +#include +#include +#include +#include "arm_nnexamples_gru_test_data.h" +#include "arm_math.h" +#include "arm_nnfunctions.h" + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif +#endif + +#define DIM_HISTORY 32 +#define DIM_INPUT 32 +#define DIM_VEC 64 + +#define USE_X4 + +#ifndef USE_X4 +static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X2; +static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X2; +static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X2; +#else +static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X4; +static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X4; +static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X4; +#endif + +static q7_t update_gate_bias[DIM_HISTORY] = UPDATE_GATE_BIAS; +static q7_t reset_gate_bias[DIM_HISTORY] = RESET_GATE_BIAS; +static q7_t hidden_state_bias[DIM_HISTORY] = HIDDEN_STATE_BIAS; + +static q15_t test_input1[DIM_INPUT] = INPUT_DATA1; +static q15_t test_input2[DIM_INPUT] = INPUT_DATA2; +static q15_t test_history[DIM_HISTORY] = HISTORY_DATA; + +q15_t scratch_buffer[DIM_HISTORY * 4 + DIM_INPUT]; + +void gru_example(q15_t * scratch_input, uint16_t input_size, uint16_t history_size, + q7_t * weights_update, q7_t * weights_reset, q7_t * weights_hidden_state, + q7_t * bias_update, q7_t * bias_reset, q7_t * bias_hidden_state) +{ + q15_t *reset = scratch_input; + q15_t *input = scratch_input + history_size; + q15_t *history = scratch_input + history_size + input_size; + q15_t *update = scratch_input + 2 * history_size + input_size; + q15_t *hidden_state = scratch_input + 3 * history_size + input_size; + + // reset gate calculation + // the range of the output can be adjusted with bias_shift and output_shift +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(input, weights_reset, input_size + history_size, history_size, 0, 15, bias_reset, + reset, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(input, weights_reset, input_size + history_size, history_size, 0, 15, + bias_reset, reset, NULL); +#endif + // sigmoid function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(reset, history_size, 0, ARM_SIGMOID); + arm_mult_q15(history, reset, reset, history_size); + + // update gate calculation + // the range of the output can be adjusted with bias_shift and output_shift +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(input, weights_update, input_size + history_size, history_size, 0, 15, + bias_update, update, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(input, weights_update, input_size + history_size, history_size, 0, 15, + bias_update, update, NULL); +#endif + + // sigmoid function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(update, history_size, 0, ARM_SIGMOID); + + // hidden state calculation +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15, + bias_hidden_state, hidden_state, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15, + bias_hidden_state, hidden_state, NULL); +#endif + + // tanh function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(hidden_state, history_size, 0, ARM_TANH); + arm_mult_q15(update, hidden_state, hidden_state, history_size); + + // we calculate z - 1 here + // so final addition becomes substraction + arm_offset_q15(update, 0x8000, update, history_size); + // multiply history + arm_mult_q15(history, update, update, history_size); + // calculate history_out + arm_sub_q15(hidden_state, update, history, history_size); + + return; +} + +int main() +{ + #ifdef RTE_Compiler_EventRecorder + EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder + #endif + + printf("Start GRU execution\n"); + int input_size = DIM_INPUT; + int history_size = DIM_HISTORY; + + // copy over the input data + arm_copy_q15(test_input1, scratch_buffer + history_size, input_size); + arm_copy_q15(test_history, scratch_buffer + history_size + input_size, history_size); + + gru_example(scratch_buffer, input_size, history_size, + update_gate_weights, reset_gate_weights, hidden_state_weights, + update_gate_bias, reset_gate_bias, hidden_state_bias); + printf("Complete first iteration on GRU\n"); + + arm_copy_q15(test_input2, scratch_buffer + history_size, input_size); + gru_example(scratch_buffer, input_size, history_size, + update_gate_weights, reset_gate_weights, hidden_state_weights, + update_gate_bias, reset_gate_bias, hidden_state_bias); + printf("Complete second iteration on GRU\n"); + + return 0; +} diff --git a/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru_test_data.h b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru_test_data.h new file mode 100644 index 0000000..4fd2bb0 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru_test_data.h @@ -0,0 +1,23 @@ +#define UPDATE_GATE_WEIGHT_X2 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+ +#define UPDATE_GATE_WEIGHT_X4 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+ +#define RESET_GATE_WEIGHT_X2 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+ +#define RESET_GATE_WEIGHT_X4 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+ +#define HIDDEN_STATE_WEIGHT_X2 {-3,-33,59,21,117,70,0,44,108,108,-47,-80,-118,34,88,-91,-123,-108,8,51,26,82,-80,107,-100,-69,97,-90,17,19,63,111,-40,-125,110,24,58,-69,26,-31,-65,-37,-47,-41,-109,106,-100,108,-99,108,116,104,86,-50,-45,10,-53,112,34,96,-10,-39,-32,-25,69,102,-2,-4,-25,121,-1,-28,-48,-100,0,-128,60,-73,42,-32,118,-88,-113,-112,-113,70,-98,118,95,77,-52,123,-99,72,26,-102,-32,120,113,22,6,-68,84,-33,103,66,111,60,-76,33,10,25,-43,93,41,-79,110,13,67,107,-113,90,58,64,-125,79,-85,-18,76,80,-59,11,-18,-74,15,-102,99,-19,117,99,65,-50,-108,-121,-9,-104,33,94,-95,110,-48,-97,76,36,1,-58,86,-115,45,-88,38,51,123,-23,-20,-43,-37,15,91,-85,-88,6,-96,58,78,13,23,1,-43,62,-70,-108,44,30,74,90,79,-80,-20,71,-21,0,60,19,-59,-52,44,-14,77,92,-69,121,-123,-27,119,-84,79,87,24,85,118,1,-51,-96,60,102,-6,15,96,120,-109,6,35,11,-119,-109,-18,16,-112,91,-126,71,-29,121,-21,-120,37,57,-117,-39,93,56,-73,-104,77,-107,-52,111,-61,-4,44,-119,67,72,-66,36,-127,-113,-124,123,21,98,84,86,76,23,78,7,-127,-4,1,-46,-107,59,-21,53,-65,-99,-15,-98,53,-31,7,64,7,105,51,-75,50,-52,48,101,-126,-120,5,34,3,81,-39,70,41,112,25,30,79,-6,107,-11,-97,92,-84,67,49,107,60,101,-37,27,-91,-61,-96,120,-113,87,-46,68,64,102,-86,-60,13,-71,56,-105,90,-9,-35,27,103,120,39,23,-39,-1,-85,-95,-6,119,-41,-2,-69,102,102,-119,-3,-11,-125,-111,40,-115,-41,-117,-44,-7,83,123,-21,23,99,-107,43,100,-99,-3,89,3,-113,103,47,-94,-69,-38,-28,-37,49,-117,-49,-126,17,-98,37,92,55,-116,-70,-50,77,120,47,124,78,114,67,-48,6,-42,-115,85,116,-114,-46,-50,-13,70,-101,110,-55,20,-51,125,-19,-9,-15,46,30,-27,-123,114,-50,-30,-72,76,-83,71,47,-45,74,102,44,108,-26,108,-113,-43,110,-91,37,-69,76,-33,106,-76,-96,20,-117,63,-33,-5,11,-121,-51,63,-56,59,-16,-33,114,74,124,73,99,-50,51,-71,118,106,30,-92,26,-40,119,-121,2,-45,9,0,-5,-2,-89,88,-11,-85,-60,19,81,-96,75,82,-40,124,89,-36,-117,-100,-2,-34,112,101,39,-101,-106,60,59,-126,-32,96,68,-53,87,20,54,-24,46,-95,65,-112,22,60,122,-22,-106,-124,97,-37,-86,95,-110,-8,44,58,-12,-120,-45,-86,-32,-86,-94,-14,15,29,-8,-114,71,70,-93,-69,100,-123,-18,-47,-12,127,104,-102,93,-11,-73,121,87,-79,-92,46,92,-108,-107,79,121,-71,-89,16,-11,-52,72,-114,-32,-60,-9,-57,-4,10,-81,-22,68,74,76,-68,-127,96,-84,69,-3,-26,-106,-3,-87,-65,105,109,122,-103,31,-108,-86,-5,-39,85,88,67,-82,0,-25,93,61,-62,5,-54,-114,-51,-9,-114,20,49,-26,38,19,39,-103,33,-120,37,-97,32,-89,119,111,-124,-99,78,-49,-128,76,-18,-12,-109,96,90,-73,-104,59,-59,-92,123,55,54,-120,-80,-48,-16,-95,96,36,118,-119,-58,93,45,-43,-75,64,38,-2,-72,-111,22,-89,-75,-120,-42,45,108,59,-105,40,27,32,-66,121,-22,-71,-9,118,124,60,-96,47,4,14,-27,64,70,47,-91,-70,1,-44,94,-46,53,4,23,-124,-92,-95,83,-49,-81,40,-80,48,0,39,1,-113,32,40,-21,-1,-110,102,1,-74,-51,40,108,-35,-36,89,84,123,-48,-115,-115,83,-61,114,-127,-61,114,100,-82,-45,60,87,60,19,86,97,-68,40,-66,75,86,-32,-128,88,-57,-27,77,3,-27,43,-39,-62,66,5,-82,45,-104,-78,34,57,96,89,-90,66,-10,37,-110,-30,82,-58,13,94,12,115,35,117,0,80,61,-7,107,-104,-21,21,-70,-93,-94,-51,-61,39,-62,64,-82,-109,76,84,58,-47,-100,52,46,-51,88,91,8,-47,108,-80,25,-58,111,-59,-83,-75,92,98,110,54,106,65,-47,-120,-5,90,-123,101,-61,-85,-93,109,88,0,8,59,86,56,126,17,-26,58,-101,-25,35,0,-123,-3,-56,112,-128,8,17,-52,88,31,-3,105,-56,68,-1,-94,96,-19,10,-22,-88,-10,119,-44,19,42,75,-86,18,-107,89,-82,-120,76,40,84,-122,29,33,-47,17,-50,-13,23,-66,-46,85,-29,-110,42,-68,8,99,-93,-29,101,16,52,-13,127,0,86,-117,-92,-70,-32,-27,127,-123,1,34,-13,92,114,-11,29,-103,-121,-54,20,73,16,74,108,16,-61,89,50,-30,-14,116,44,-31,16,96,24,-51,7,39,-87,-69,-61,-98,61,-46,113,85,-95,103,67,99,-66,-45,-42,-70,96,104,5,-111,69,-25,99,-118,23,109,11,4,-41,-94,73,100,96,6,90,-75,-25,79,-13,-43,-6,-12,51,12,40,124,-56,81,-8,59,-60,-26,-54,33,122,85,53,-99,125,19,-26,94,41,-5,46,-48,-70,-10,41,102,-1,-98,-9,15,29,46,-66,-118,-53,45,119,-127,94,53,-58,90,124,5,-110,-98,-80,-77,77,29,19,105,-121,92,9,-124,50,-119,59,40,67,104,-12,13,103,101,47,-51,34,-66,-101,-117,112,-5,118,-48,-60,-114,38,-71,2,51,114,80,115,-5,116,20,16,-47,-19,30,24,-68,7,-30,-3,-64,-7,-34,-12,44,34,-91,-97,116,112,-99,108,-75,17,26,-14,-61,80,22,-7,34,47,-93,45,106,121,78,43,-97,39,-99,-68,-72,-7,64,-49,-82,-127,78,-64,48,18,15,126,-125,-111,-69,-111,10,-46,111,-75,123,-44,-67,-31,-96,-67,-53,-53,-106,67,-101,23,62,30,9,-114,-12,-57,-38,-78,95,-10,-3,110,88,123,-26,78,-125,114,53,10,-57,26,38,-51,73,92,-124,79,15,75,-62,109,-113,-67,1,35,52,-36,55,7,111,-43,109,101,88,122,-21,-32,-87,59,16,-122,-109,-118,17,-22,-39,53,-105,77,90,-24,-65,43,-27,113,30,-117,-30,106,37,55,59,54,-70,99,99,-73,120,97,-39,-88,-54,101,51,-76,70,-121,-68,23,-73,-31,75,-8,-63,-123,-93,96,-81,99,-95,28,-36,55,-104,32,-64,41,-97,95,-89,126,-26,-25,126,2,-26,-54,110,-86,110,74,-3,-110,56,-60,-49,117,-82,-55,-103,-112,70,-85,85,-63,82,7,75,-61,90,32,35,-115,72,73,-121,63,-84,-52,-29,-59,-4,29,64,119,127,58,-117,48,126,120,-115,-15,-10,27,27,-81,117,-5,121,-72,113,31,-13,10,27,-106,-51,81,-96,-22,19,-78,6,71,-34,123,118,75,-23,-72,-97,111,-121,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+ +#define HIDDEN_STATE_WEIGHT_X4 {-3,69,-33,102,76,60,80,19,59,-2,21,-4,-59,-59,11,-52,117,-25,70,121,-18,44,-74,-14,0,-1,44,-28,15,77,-102,92,108,-48,108,-100,99,-69,-19,121,-47,0,-80,-128,117,-123,99,-27,-118,60,34,-73,65,119,-50,-84,88,42,-91,-32,-108,79,-121,87,-123,118,-108,-88,-9,24,-104,85,8,-113,51,-112,33,118,94,1,26,-113,82,70,-95,-51,110,-96,-80,-98,107,118,-48,60,-97,102,-100,95,-69,77,76,-6,36,15,97,-52,-90,123,1,96,-58,120,17,-99,19,72,86,-109,-115,6,63,26,111,-102,45,35,-88,11,-40,-32,-125,120,38,-119,51,-109,110,113,24,22,123,-18,-23,16,58,6,-69,-68,-20,-112,-43,91,26,84,-31,-33,-37,-126,15,71,-65,103,-37,66,91,-29,-85,121,-47,111,-41,60,-88,-21,6,-120,-109,-76,106,33,-96,37,58,57,-100,10,108,25,78,-117,13,-39,-99,-43,108,93,23,93,1,56,116,41,104,-79,-43,-73,62,-104,86,110,-50,13,-70,77,-108,-107,-45,67,10,107,44,-52,30,111,-53,-113,112,90,74,-61,90,-4,34,58,96,64,79,44,-80,-119,-10,-125,-39,79,-20,67,71,72,-32,-85,-25,-18,-21,-66,0,36,-127,-96,-113,120,49,76,-117,-33,-124,-113,123,87,-49,106,-126,-76,21,-46,98,68,17,-96,-98,20,84,64,86,102,37,-117,92,63,76,-86,23,-60,55,-33,-116,-5,78,13,7,-71,-70,11,-50,-121,-127,56,-4,-105,77,-51,120,63,1,90,-46,-9,47,-56,124,59,-107,-35,59,27,78,-16,114,-33,-21,103,53,120,67,114,-48,74,-65,39,-99,23,6,124,-42,73,-15,-39,-98,-1,-115,99,85,-50,53,-85,-31,-95,116,51,-114,-71,7,-6,64,119,-46,118,-50,106,7,-41,105,-2,-13,30,70,-92,51,-69,-75,102,-101,26,110,-40,50,102,-52,-119,-55,119,20,-121,48,-3,101,-11,-51,2,125,-45,-126,-125,-120,-111,-19,9,-9,0,5,40,34,-115,-15,-5,46,-2,3,-41,81,-117,30,-89,-27,88,-39,-44,70,-7,-123,-11,114,-85,41,83,112,123,-50,-60,-30,19,25,-21,30,23,-72,81,76,-96,79,99,-6,-107,-83,75,71,82,107,43,-11,100,47,-40,-45,124,-97,-99,92,-3,74,89,102,-36,-84,89,67,3,44,-117,108,-100,49,-113,107,103,-26,-2,108,-34,60,47,101,-94,-113,112,-43,101,-37,-69,27,-38,110,39,-91,-101,-91,-28,-61,-37,37,-106,-69,60,59,121,-126,-71,-97,47,32,4,-32,-89,96,16,-89,14,119,-27,68,-11,-53,-52,111,64,-124,70,87,72,20,-114,-99,47,78,-91,54,-32,-24,-60,-49,-70,-128,1,46,-9,-95,-57,76,-44,-18,94,65,-4,-112,10,-12,-46,-109,53,22,-81,60,-22,96,4,90,23,122,68,-22,74,-73,-124,-104,-92,-106,76,-124,-68,59,-95,-59,83,97,-127,-37,96,-92,-49,123,-81,-86,-84,95,69,55,40,54,-80,-110,-3,-8,-26,-120,48,-80,0,44,-106,58,-3,-48,39,-16,1,-12,-87,-120,-65,-95,-113,96,32,-45,105,-86,109,36,40,118,-21,-32,122,-86,-103,-119,-1,-58,-110,-94,31,-14,-108,93,102,45,1,15,-86,29,-5,-43,-74,-75,-51,-8,-39,-114,85,64,40,38,108,71,88,70,67,-2,-35,-72,-36,-93,-82,-69,0,-111,89,22,84,100,-25,-123,93,-89,123,-75,-48,-18,61,-47,-62,-120,-115,-42,-115,-12,5,127,-54,45,83,108,-61,104,-114,-102,-51,59,114,-105,-127,93,-9,-11,-114,40,-61,27,114,-73,20,121,49,32,100,-66,-82,87,-26,-79,38,121,-45,-22,60,-92,19,46,39,-71,87,-9,60,92,-103,-108,33,118,19,124,86,-107,-120,79,37,60,97,-96,-68,40,-51,-66,88,-10,-61,119,89,75,91,86,8,-44,50,19,-30,-32,-47,-128,108,42,-14,75,116,88,-80,-57,25,-86,44,18,-31,-27,-58,77,111,-107,16,89,96,3,-59,-27,-83,-82,24,-120,-51,43,-75,-39,92,76,7,40,39,-62,98,66,110,84,-87,-122,-69,5,54,-82,106,29,-61,33,-98,45,65,-104,-47,-47,61,17,-46,-78,-120,34,-5,-50,113,-13,85,57,90,96,-123,23,-95,-66,103,89,101,-90,-61,-46,67,85,99,66,-85,-10,-93,-29,-66,-110,-45,37,109,-110,88,42,-42,-68,-70,-30,0,82,8,8,96,99,104,-58,59,13,86,-93,5,-29,-111,94,56,12,126,101,69,16,-25,115,17,35,-26,52,99,-13,-118,117,58,0,-101,127,23,0,109,80,-25,61,35,86,11,-117,4,-7,0,107,-123,-92,-41,-70,-94,-104,-3,-21,-56,-32,73,-27,100,21,112,-70,-128,127,96,-123,6,-93,8,-94,17,1,90,34,-75,-51,-52,-61,88,-13,-25,92,79,39,31,-62,-3,114,-13,-11,-43,64,105,-82,-56,29,-6,-103,-12,-109,68,76,-1,-121,51,-54,12,84,-94,58,96,20,40,73,124,-47,-19,-100,10,16,-56,74,81,52,-22,46,-88,108,-8,16,59,-60,-101,-26,-117,-127,-36,78,55,-54,112,33,-5,-64,7,48,111,122,118,85,-48,18,-43,15,109,53,-60,-99,-114,126,101,-125,88,125,38,19,-71,-111,122,-69,-21,-26,2,94,51,-111,-32,10,-87,41,114,-5,80,-46,59,111,16,46,115,-48,-5,-75,-122,123,-109,-70,116,-10,20,-44,-118,-67,17,41,16,102,-47,-31,-22,-96,-39,-1,-19,-98,30,-67,53,-53,-105,-9,24,15,-68,-53,77,-106,90,29,7,46,-30,67,-24,-101,-65,-66,-3,-118,-64,23,43,62,-27,-53,-7,45,-34,30,113,9,30,119,-12,-127,44,-114,-117,-12,-30,94,34,53,-91,-57,106,-38,37,-58,-97,90,116,-78,55,95,59,124,112,5,-99,-10,54,-3,-70,-110,108,-98,-75,110,99,88,99,-80,17,-77,26,123,-73,-26,120,77,-14,29,-61,78,97,-125,-39,19,80,105,22,114,-88,53,-54,-121,-7,92,34,10,101,-57,51,9,47,-124,-93,26,-76,38,70,50,45,-119,106,-51,-121,73,-68,59,121,40,78,92,23,-124,-73,67,43,104,-97,79,-31,15,75,-12,39,13,-99,75,-8,-62,-63,103,-68,101,-72,109,-123,-113,-93,47,-7,-51,64,-67,96,1,-81,34,-49,-66,-82,35,99,52,-95,28,27,-36,27,-93,-15,52,-68,55,-81,-104,117,67,-3,53,102,32,-5,-64,121,-31,-10,19,-123,41,-72,-97,113,45,-10,-111,-71,95,31,-89,-13,36,-111,39,86,126,10,-26,27,-91,48,-77,-45,-25,-106,126,-51,104,101,71,81,2,81,-26,-96,7,-114,-44,-94,-54,-22,110,19,-76,77,3,-127,-86,-78,110,6,-62,-96,121,-100,74,71,-3,-34,43,86,37,109,-110,123,56,118,-7,-33,-96,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+ +#define UPDATE_GATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103} + +#define RESET_GATE_BIAS {-77,67,-93,-3,98,59,-121,33,49,50,41,91,-115,-33,71,47,-70,45,89,-115,72,106,-22,100,97,-100,-95,108,-33,3,14,30} + +#define HIDDEN_STATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103} + +#define INPUT_DATA1 {-367,-338,0,-89,453,-413,-343,-16,42,418,201,274,-352,477,-290,-92,266,-49,342,453,-398,247,-153,328,217,342,85,69,-38,351,73,128} + +#define INPUT_DATA2 {280,41,-322,61,315,350,504,-227,-221,-483,352,252,455,-236,344,364,-378,229,-187,-498,295,357,-511,58,-349,-458,-420,-66,-400,-379,477,-60} + +#define HISTORY_DATA {-38,53,105,-79,-463,51,-343,-226,-435,-282,218,441,-299,-215,-109,335,340,-471,-109,273,33,-245,-469,170,-26,-59,192,-119,76,-6,236,-145} diff --git a/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/readme_iar.txt b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/readme_iar.txt new file mode 100644 index 0000000..a73e193 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/readme_iar.txt @@ -0,0 +1,7 @@ +CMSIS NN Lib example arm_nnexample_gru0 for + Cortex-M0, Cortex-M3, Cortex-M4 and Cortex-M7. + +The example is configured for IAR Embedded Workbench for ARM Simulator. + +When changing target, remember to change the ARM_MATH_CMx and __FPU_PRESENT +Preprocessor defines for C/C++ Compiler \ No newline at end of file diff --git a/Drivers/CMSIS/NN/Include/arm_nn_tables.h b/Drivers/CMSIS/NN/Include/arm_nn_tables.h new file mode 100644 index 0000000..36be5a8 --- /dev/null +++ b/Drivers/CMSIS/NN/Include/arm_nn_tables.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_tables.h + * Description: Extern declaration for NN tables + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_NN_TABLES_H +#define _ARM_NN_TABLES_H + +#include "arm_math.h" + +/** +* @brief tables for various activation functions +* +*/ + +extern const q15_t sigmoidTable_q15[256]; +extern const q7_t sigmoidTable_q7[256]; + +extern const q7_t tanhTable_q7[256]; +extern const q15_t tanhTable_q15[256]; + + /** + * @brief 2-way tables for various activation functions + * + * 2-way table, H table for value larger than 1/4 + * L table for value smaller than 1/4, H table for remaining + * We have this only for the q15_t version. It does not make + * sense to have it for q7_t type + */ +extern const q15_t sigmoidHTable_q15[192]; +extern const q15_t sigmoidLTable_q15[128]; + +#endif /* ARM_NN_TABLES_H */ diff --git a/Drivers/CMSIS/NN/Include/arm_nnfunctions.h b/Drivers/CMSIS/NN/Include/arm_nnfunctions.h new file mode 100644 index 0000000..331255b --- /dev/null +++ b/Drivers/CMSIS/NN/Include/arm_nnfunctions.h @@ -0,0 +1,1075 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnfunctions.h + * Description: Public header file for CMSIS NN Library + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS NN Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS NN software library, + * a collection of efficient neural network kernels developed to maximize the + * performance and minimize the memory footprint of neural networks on Cortex-M processor cores. + * + * The library is divided into a number of functions each covering a specific category: + * - Neural Network Convolution Functions + * - Neural Network Activation Functions + * - Fully-connected Layer Functions + * - Neural Network Pooling Functions + * - Softmax Functions + * - Neural Network Support Functions + * + * The library has separate functions for operating on different weight and activation data + * types including 8-bit integers (q7_t) and 16-bit integers (q15_t). The descrition of the + * kernels are included in the function description. The implementation details are also + * described in this paper [1]. + * + * Block Diagram + * -------- + * \image html CMSIS-NN-OVERVIEW.PNG + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - ARM_MATH_DSP: + * + * Define macro ARM_MATH_DSP, If the silicon supports DSP instructions. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_NN_TRUNCATE: + * + * Define macro ARM_NN_TRUNCATE to use floor instead of round-to-the-nearest-int for the computation. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2018 Arm Limited. All rights reserved. + * + * [1] CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs https://arxiv.org/abs/1801.06601 + */ + +/** + * @defgroup groupNN Neural Network Functions + * These functions perform basic operations for neural network layers. + */ + +#ifndef _ARM_NNFUNCTIONS_H +#define _ARM_NNFUNCTIONS_H + +#include "arm_nnsupportfunctions.h" +#include "arm_nn_tables.h" + +#define USE_INTRINSIC + +//#define ARM_NN_TRUNCATE /* This config the rounding model to floor or round to the nearest int */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup NNConv Neural Network Convolution Functions + * + * Perform convolution layer + * + * The convolution is implemented in 2 steps: im2col and GEMM + * + * im2col is a process of converting each patch of image data into + * a column. After im2col, the convolution is computed as matrix-matrix + * multiplication. + * + * To reduce the memory footprint, the im2col is performed partially. + * Each iteration, only a few column (i.e., patches) are generated and + * computed with GEMM kernels similar to CMSIS-DSP arm_mat_mult functions. + * + */ + + /** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_convolve_HWC_q7_basic(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Basic Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + */ + + arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_convolve_HWC_q15_basic(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + + arm_status arm_convolve_HWC_q7_fast(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + + arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function implement convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for + * second half of MobileNets after depthwise separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Q7 version of convolution for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + + arm_status arm_convolve_HWC_q7_RGB(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + + arm_status arm_convolve_HWC_q15_fast(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + + arm_status + arm_convolve_HWC_q15_fast_nonsquare(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + + arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + +/** + * @defgroup FC Fully-connected Layer Functions + * + * Perform fully-connected layer + * + * Fully-connected layer is basically a matrix-vector multiplication + * with bias. The matrix is the weights and the input/output vectors + * are the activation values. Supported {weight, activation} precisions + * include {8-bit, 8-bit}, {16-bit, 16-bit}, and {8-bit, 16-bit}. + * + * Here we have two types of kernel functions. The basic function + * implements the function using regular GEMV approach. The opt functions + * operates with weights in interleaved formats. + * + */ + + /** + * @brief Q7 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_q7(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_q7_opt(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Q15 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_q15(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_q15_opt(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_mat_q7_vec_q15(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + +/** + * @brief Matrix-Multiplication Kernels for Convolution + * + * These functions are used within convolution layer functions for + * matrix multiplication. + * + * The implementation is similar to CMSIS-DSP arm_mat_mult functions + * with one Q7 and one Q15 operands. The Q15 operand is the im2col + * output which is always with 2 columns. + * + */ + + /** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + + q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut); + + /** + * @brief Matrix-multiplication function for convolution with reordered columns + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + + q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut); + +#ifdef __cplusplus +} +#endif + +/* + * Other functions + * These layers are typically not timing critical + * Basic implementation is supported here + */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup Acti Neural Network Activation Functions + * + * Perform activation layers, including ReLU (Rectified Linear Unit), + * sigmoid and tanh + * + */ + + /** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + + void arm_relu_q7(q7_t * data, uint16_t size); + + /** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + + void arm_relu_q15(q15_t * data, uint16_t size); + + /** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + */ + + void arm_nn_activations_direct_q7(q7_t * data, uint16_t size, uint16_t int_width, + arm_nn_activation_type type); + + /** + * @brief Q15 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + */ + + void arm_nn_activations_direct_q15(q15_t * data, uint16_t size, uint16_t int_width, + arm_nn_activation_type type); + +/** + * @defgroup Pooling Neural Network Pooling Functions + * + * Perform pooling functions, including max pooling and average pooling + * + */ + + /** + * @brief Q7 max pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + + void arm_maxpool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t * bufferA, + q7_t * Im_out); + + /** + * @brief Q7 average pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + + void arm_avepool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t * bufferA, + q7_t * Im_out); + +/** + * @defgroup Softmax Softmax Functions + * + * EXP(2) based softmax function + * + */ + + /** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + */ + + void arm_softmax_q7(const q7_t * vec_in, const uint16_t dim_vec, q7_t * p_out); + + /** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + */ + + void arm_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out); + + /** + * @brief uint8 depthwise convolution function with asymmetric quantization for even number of channel multiplier + * and input channels. Unless specified otherwise, arguments are mandatory. + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x Convolution stride along the width + * @param[in] stride_y Convolution stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * availble, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] out_shift Amount of right-shift for output + * @param[in] out_mult Output multiplier for requantization + * @return The function returns one of the following + * ARM_MATH_SIZE_MISMATCH - Not supported dimension of tensors + * ARM_MATH_SUCCESS - Successful operation + * ARM_MATH_ARGUMENT_ERROR - Implementation not available + * + * Input constraints + * ch_mult is multiple of 2 + * kernel_x is multiple of 2 + * + */ + arm_status arm_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t out_shift, + const int32_t out_mult); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h b/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h new file mode 100644 index 0000000..af426e1 --- /dev/null +++ b/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnsupportfunctions.h + * Description: Public header file of support functions for CMSIS NN Library + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#ifndef _ARM_NNSUPPORTFUNCTIONS_H_ +#define _ARM_NNSUPPORTFUNCTIONS_H_ + +#include "arm_math.h" +#include "arm_common_tables.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define LEFT_SHIFT(_shift) (_shift > 0 ? _shift : 0) +#define RIGHT_SHIFT(_shift) (_shift > 0 ? 0 : -_shift) +#define Q31_MIN (0x80000000L) +#define Q31_MAX (0x7FFFFFFFL) + +/** + * @brief Union for SIMD access of Q31/Q15/Q7 types + */ +union arm_nnword +{ + q31_t word; + /**< Q31 type */ + q15_t half_words[2]; + /**< Q15 type */ + q7_t bytes[4]; + /**< Q7 type */ +}; + +/** + * @brief Struct for specifying activation function types + * + */ +typedef enum +{ + ARM_SIGMOID = 0, + /**< Sigmoid activation function */ + ARM_TANH = 1, + /**< Tanh activation function */ +} arm_nn_activation_type; + +/** + * @defgroup nndata_convert Neural Network Data Conversion Functions + * + * Perform data type conversion in-between neural network operations + * + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + */ + +void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + */ + +void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize); + +#if defined (ARM_MATH_DSP) + +/** + * @brief read and expand one Q7 word into two Q15 words + */ + +__STATIC_FORCEINLINE void *read_and_pad(void *source, q31_t * out1, q31_t * out2) +{ + q31_t inA = *__SIMD32(source)++; + q31_t inAbuf1 = __SXTB16(__ROR(inA, 8)); + q31_t inAbuf2 = __SXTB16(inA); + +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __PKHTB(inAbuf1, inAbuf2, 16); + *out1 = __PKHBT(inAbuf2, inAbuf1, 16); +#else + *out1 = __PKHTB(inAbuf1, inAbuf2, 16); + *out2 = __PKHBT(inAbuf2, inAbuf1, 16); +#endif + + return source; +} + +/** + * @brief read and expand one Q7 word into two Q15 words with reordering + */ + +__STATIC_FORCEINLINE void *read_and_pad_reordered(void *source, q31_t * out1, q31_t * out2) +{ + q31_t inA = *__SIMD32(source)++; +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __SXTB16(__ROR(inA, 8)); + *out1 = __SXTB16(inA); +#else + *out1 = __SXTB16(__ROR(inA, 8)); + *out2 = __SXTB16(inA); +#endif + + return source; +} +#endif + +/** + * @defgroup NNBasicMath Basic Math Functions for Neural Network Computation + * + * Basic Math Functions for Neural Network Computation + * + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + const uint16_t out_shift, + uint32_t blockSize); + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + const uint16_t out_shift, + uint32_t blockSize); + +/** + * @brief macro for adding rounding offset + */ +#ifndef ARM_NN_TRUNCATE + #define NN_ROUND(out_shift) ( (0x1u << out_shift) >> 1 ) +#else + #define NN_ROUND(out_shift) 0 +#endif + +/** + * @brief Saturating doubling high multiply. Result matches + * NEON instruction VQRDMULH. + * @param[in] m1 Multiplicand + * @param[in] m2 Multiplier + * @return Result of multiplication. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_sat_doubling_high_mult(const q31_t m1, const q31_t m2) +{ + q31_t result = 0; + // Rounding offset to add for a right shift of 31 + q63_t mult = 1 << 30; + + if ((m1 < 0) ^ (m2 < 0)) + { + mult = 1 - mult; + } + // Gets resolved as a SMLAL instruction + mult = mult + (q63_t)m1 * m2; + + // Utilize all of the upper 32 bits. This is the doubling step + // as well. + result = mult / (1UL << 31); + + if ((m1 == m2) && (m1 == Q31_MIN)) + { + result = Q31_MAX; + } + return result; +} + +/** + * @brief Rounding divide by power of two. + * @param[in] dividend - Dividend + * @param[in] exponent - Divisor = power(2, exponent) + * Range: [0, 31] + * @return Rounded result of division. Midpoint is rounded away from zero. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_divide_by_power_of_two(const q31_t dividend, const q31_t exponent) +{ + q31_t result = 0; + const q31_t remainder_mask = (1l << exponent) - 1; + int32_t remainder = remainder_mask & dividend; + + // Basic division + result = dividend >> exponent; + + // Adjust 'result' for rounding (mid point away from zero) + q31_t threshold = remainder_mask >> 1; + if (result < 0) + { + threshold++; + } + if (remainder > threshold) + { + result++; + } + + return result; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..9fc447d --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,242 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66829ad --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..e3ea17f --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00080000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f08df7a --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.s b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.s new file mode 100644 index 0000000..dae6439 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.c new file mode 100644 index 0000000..af23005 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */ + (3U << 11U*2U) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..116c5cb --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00100000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..070fa1e --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..26edb9f --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,295 @@ +/**************************************************************************//** + * @file startup_ARMCM7.s + * @brief CMSIS Core Device Startup File for + * ARMCM7 Device Series + * @version V5.00 + * @date 26. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __etext; +extern uint32_t __data_start__; +extern uint32_t __data_end__; +extern uint32_t __copy_table_start__; +extern uint32_t __copy_table_end__; +extern uint32_t __zero_table_start__; +extern uint32_t __zero_table_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __StackTop; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +#ifndef __START +extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ +#else +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +#endif + +#ifndef __NO_SYSTEM_INIT +extern void SystemInit (void); /* CMSIS System Initialization */ +#endif + + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void); /* Default empty handler */ +void Reset_Handler(void); /* Reset Handler */ + + +/*---------------------------------------------------------------------------- + User Initial Stack & Heap + *----------------------------------------------------------------------------*/ +#ifndef __STACK_SIZE + #define __STACK_SIZE 0x00000400 +#endif +static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); + +#ifndef __HEAP_SIZE + #define __HEAP_SIZE 0x00000C00 +#endif +#if __HEAP_SIZE > 0 +static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Cortex-M7 Processor Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* ARMCM7 Specific Interrupts */ +void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = { + /* Cortex-M7 Exceptions Handler */ + (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + /* External interrupts */ + WDT_IRQHandler, /* 0: Watchdog Timer */ + RTC_IRQHandler, /* 1: Real Time Clock */ + TIM0_IRQHandler, /* 2: Timer0 / Timer1 */ + TIM2_IRQHandler, /* 3: Timer2 / Timer3 */ + MCIA_IRQHandler, /* 4: MCIa */ + MCIB_IRQHandler, /* 5: MCIb */ + UART0_IRQHandler, /* 6: UART0 - DUT FPGA */ + UART1_IRQHandler, /* 7: UART1 - DUT FPGA */ + UART2_IRQHandler, /* 8: UART2 - DUT FPGA */ + UART4_IRQHandler, /* 9: UART4 - not connected */ + AACI_IRQHandler, /* 10: AACI / AC97 */ + CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */ + ENET_IRQHandler, /* 12: Ethernet */ + USBDC_IRQHandler, /* 13: USB Device */ + USBHC_IRQHandler, /* 14: USB Host Controller */ + CHLCD_IRQHandler, /* 15: Character LCD */ + FLEXRAY_IRQHandler, /* 16: Flexray */ + CAN_IRQHandler, /* 17: CAN */ + LIN_IRQHandler, /* 18: LIN */ + I2C_IRQHandler, /* 19: I2C ADC/DAC */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + 0, /* 27: Reserved */ + CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */ + 0, /* 29: Reserved - CPU FPGA */ + UART3_IRQHandler, /* 30: UART3 - CPU FPGA */ + SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ +}; + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) { + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + pTable = &__copy_table_start__; + + for (; pTable < &__copy_table_end__; pTable = pTable + 3) { + pSrc = (uint32_t*)*(pTable + 0); + pDest = (uint32_t*)*(pTable + 1); + for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { + *pDest++ = *pSrc++; + } + } +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + pSrc = &__etext; + pDest = &__data_start__; + + for ( ; pDest < &__data_end__ ; ) { + *pDest++ = *pSrc++; + } +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + pTable = &__zero_table_start__; + + for (; pTable < &__zero_table_end__; pTable = pTable + 2) { + pDest = (uint32_t*)*(pTable + 0); + for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { + *pDest++ = 0; + } + } +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for ( ; pDest < &__bss_end__ ; ) { + *pDest++ = 0UL; + } +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + SystemInit(); +#endif + +#ifndef __START +#define __START _start +#endif + __START(); + +} + + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + + while(1); +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..0170ef4 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00080000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..65bfaca --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.s b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.s new file mode 100644 index 0000000..9b70614 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.s @@ -0,0 +1,395 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.6.0 +;* Date : 04-November-2016 +;* Description : STM32F411xExx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.c new file mode 100644 index 0000000..bca0633 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.c @@ -0,0 +1,763 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.6.0 + * @date 04-November-2016 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h new file mode 100644 index 0000000..4459a74 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h new file mode 100644 index 0000000..f12e4f3 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_nn_test' + * Target: 'ARMCM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM3.h" + +#define RTE_Compiler_IO_STDERR /* Compiler I/O: STDERR */ + #define RTE_Compiler_IO_STDERR_ITM /* Compiler I/O: STDERR ITM */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +#define RTE_Compiler_IO_TTY /* Compiler I/O: TTY */ + #define RTE_Compiler_IO_TTY_ITM /* Compiler I/O: TTY ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h new file mode 100644 index 0000000..d4542f5 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_nn_test' + * Target: 'ARMCM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +#define RTE_Compiler_IO_STDERR /* Compiler I/O: STDERR */ + #define RTE_Compiler_IO_STDERR_ITM /* Compiler I/O: STDERR ITM */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +#define RTE_Compiler_IO_TTY /* Compiler I/O: TTY */ + #define RTE_Compiler_IO_TTY_ITM /* Compiler I/O: TTY ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h new file mode 100644 index 0000000..97ef09a --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_nn_test' + * Target: 'ARMCM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM7_SP.h" + +#define RTE_Compiler_IO_STDERR /* Compiler I/O: STDERR */ + #define RTE_Compiler_IO_STDERR_ITM /* Compiler I/O: STDERR ITM */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +#define RTE_Compiler_IO_TTY /* Compiler I/O: TTY */ + #define RTE_Compiler_IO_TTY_ITM /* Compiler I/O: TTY ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c new file mode 100644 index 0000000..0089709 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_convolve_HWC_q15_ref(const q15_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q15_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q15_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q15_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c new file mode 100644 index 0000000..e355ebf --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void +arm_convolve_HWC_q15_nonsquare_ref(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) + +{ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } +} + + diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c new file mode 100644 index 0000000..560cd23 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_convolve_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = ((q31_t) (bias[i]) << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c new file mode 100644 index 0000000..1e2d19e --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_convolve_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = ((q31_t) (bias[i]) << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c new file mode 100644 index 0000000..1672a4e --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_depthwise_separable_conv_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output +#ifndef ARM_NN_TRUNCATE + int conv_out = (bias[i_ch_out] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int conv_out = bias[i_ch_out] << bias_shift; +#endif + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c new file mode 100644 index 0000000..6ebd1f0 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output +#ifndef ARM_NN_TRUNCATE + int conv_out = (bias[i_ch_out] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int conv_out = bias[i_ch_out] << bias_shift; +#endif + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c new file mode 100644 index 0000000..09dd653 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_mat_q7_vec_q15_opt_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 1; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c new file mode 100644 index 0000000..8fc74d4 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_mat_q7_vec_q15_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef ARM_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c new file mode 100644 index 0000000..2118f99 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q15_opt_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 1; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c new file mode 100644 index 0000000..99ab4d9 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q15_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef ARM_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c new file mode 100644 index 0000000..567f964 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q7_opt_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 2; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t) __SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c new file mode 100644 index 0000000..f59f3db --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q7_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef ARM_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t) __SSAT((ip_out >> out_shift), 8); + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c new file mode 100644 index 0000000..2cc6b72 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +void arm_nn_mult_q7_ref(q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) { + uint16_t i; + +for (i = 0; i < blockSize; i++) + { + q31_t product = pSrcA[i] * pSrcB[i]; +#ifndef ARM_NN_TRUNCATE + pDst[i] = (q7_t)__SSAT((product + (0x1 << (out_shift - 1)))>>out_shift, 8); +#else + pDst[i] = (q7_t)__SSAT(product >> out_shift, 8); +#endif + } +} + +void arm_nn_mult_q15_ref(q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) { + uint16_t i; + +for (i = 0; i < blockSize; i++) + { + q31_t product = pSrcA[i] * pSrcB[i]; +#ifndef ARM_NN_TRUNCATE + pDst[i] = (q15_t)__SSAT((product + (0x1 << (out_shift - 1)))>>out_shift, 16); +#else + pDst[i] = (q15_t)__SSAT(product >> out_shift, 16); +#endif + + + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c new file mode 100644 index 0000000..9a4adb2 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_avepool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } +} + +void arm_maxpool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c new file mode 100644 index 0000000..323fc11 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +void arm_relu_q7_ref(q7_t * data, uint16_t size) +{ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } +} + +void arm_relu_q15_ref(q15_t * data, uint16_t size) +{ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h new file mode 100644 index 0000000..74b79f8 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h @@ -0,0 +1,7 @@ +#define IP2_WEIGHT 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+ +#define IP4_WEIGHT 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+ +#define IP4_q7_q15_WEIGHT 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+ +#define IP4_WEIGHT_Q15 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diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h new file mode 100644 index 0000000..4a0647a --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _REF_FUNCTIONS_H_ +#define _REF_FUNCTIONS_H_ + +#include "arm_math.h" +#include "arm_nnfunctions.h" +//#include "arm_nnsupportfunctions.h" +#include "fully_connected_testing_weights.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* + * + * Convolution reference implemenation + * + */ + + void arm_convolve_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + + void arm_convolve_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + + void arm_convolve_HWC_q15_ref(const q15_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q15_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q15_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q15_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + void arm_convolve_HWC_q15_nonsquare_ref(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + void arm_depthwise_separable_conv_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + void arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + +/* + * + * Fully-connected reference implemenation + * + */ + + void arm_fully_connected_q7_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_q15_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_mat_q7_vec_q15_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_q7_opt_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_q15_opt_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_mat_q7_vec_q15_opt_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + +/* + * + * Pooling reference implemenation + * + */ + + void arm_avepool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out); + + void arm_maxpool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out); + +/* + * + * Other reference implemenation + * + */ + + void arm_relu_q7_ref(q7_t * data, uint16_t size); + + void arm_relu_q15_ref(q15_t * data, uint16_t size); + + void arm_nn_mult_q7_ref(q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, const uint16_t out_shift, uint32_t blockSize); + + void arm_nn_mult_q15_ref(q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, const uint16_t out_shift, uint32_t blockSize); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp new file mode 100644 index 0000000..5cf72a2 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp @@ -0,0 +1,801 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_nn_test.cpp +* +* Description: Example code for NN kernel testing. +* +* Target Processor: Cortex-M cores +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#include "arm_nnexamples_nn_test.h" + +//#define TEST_SIGMOID +//#define TEST_TANH +#define TEST_POOL +#define TEST_RELU +#define TEST_IP +#define TEST_CONV +#define TEST_NONSQUARE +#define TEST_NNMULT + +int test_index = 0; +q7_t test_flags[50]; +bool test_pass; + +int main() +{ + printf("start tests\n"); + + srand(1); + + // common pointers for testing data + q7_t *test1; + q15_t *test2; + q7_t *test3; + q15_t *test4; + + for (test_index = 0; test_index<50; test_index++) { + test_flags[test_index] = -1; + } + test_index = 0; + +#ifdef TEST_NNMULT +#define NNMULT_DIM 128 + test1 = new q7_t[NNMULT_DIM*2]; + test2 = new q15_t[NNMULT_DIM*2]; + test3 = new q7_t[NNMULT_DIM*2]; + test4 = new q15_t[NNMULT_DIM*2]; + + q7_t * mult_out_q7 = test3; + q7_t * mult_ref_q7 = test3 + NNMULT_DIM; + q15_t * mult_out_q15 = test4; + q15_t * mult_ref_q15 = test4 + NNMULT_DIM; + + for (int i=0;i= 2 || pool_out_opt[i] - pool_out_ref[i] >= 2) + { + printf("Output mismatch at %d, expected %d, actual %d\n", i, pool_out_ref[i], pool_out_opt[i]); + if_ave_pool_match = false; + } + } + if (if_ave_pool_match == true) + { + printf("Outputs match.\n"); + } + + delete[]test1; + delete[]test2; + delete[]test3; + +#endif + +#ifdef TEST_RELU + +#define RELU_DIM 127 + + test1 = new q7_t[RELU_DIM]; + test2 = new q15_t[RELU_DIM]; + test3 = new q7_t[RELU_DIM]; + test4 = new q15_t[RELU_DIM]; + + for (int i = 0; i < RELU_DIM; i++) + { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + test3[i] = test1[i]; + test4[i] = test2[i]; + } + + q7_t *relu_ref_data_q7 = test1; + q7_t *relu_opt_data_q7 = test3; + q15_t *relu_ref_data_q15 = test2; + q15_t *relu_opt_data_q15 = test4; + + printf("Start ref relu q7 implementation\n"); + + arm_relu_q7_ref(relu_ref_data_q7, RELU_DIM); + + printf("Start opt relu q7 implementation\n"); + + arm_relu_q7(relu_opt_data_q7, RELU_DIM); + + verify_results_q7(relu_ref_data_q7, relu_opt_data_q7, RELU_DIM); + + printf("Start ref relu q15 implementation\n"); + + arm_relu_q15_ref(relu_ref_data_q15, RELU_DIM); + + printf("Start opt relu q15 implementation\n"); + + arm_relu_q15(relu_opt_data_q15, RELU_DIM); + + verify_results_q15(relu_ref_data_q15, relu_opt_data_q15, RELU_DIM); + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + +#ifdef TEST_IP + +#define IP_ROW_DIM 127 +#define IP_COL_DIM 127 + + q7_t ip_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT; + q7_t ip_q7_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT; + q7_t ip_q7_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_q7_q15_WEIGHT; + q15_t ip_q15_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT; + q15_t ip_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT_Q15; + + test1 = new q7_t[IP_COL_DIM + IP_ROW_DIM]; + test2 = new q15_t[IP_COL_DIM]; + test3 = new q7_t[IP_ROW_DIM * 3]; + test4 = new q15_t[IP_COL_DIM + IP_ROW_DIM * 2]; + + for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++) + { + test1[i] = rand() % 256 - 100; + } + for (int i = 0; i < IP_ROW_DIM * 3; i++) + { + test3[i] = 0; + } + + q7_t *ip_bias_q7 = test1 + IP_COL_DIM; + + q7_t *ip_out_q7_ref = test3; + q7_t *ip_out_q7_opt = test3 + IP_ROW_DIM; + q7_t *ip_out_q7_opt_fast = test3 + 2 * IP_ROW_DIM; + q15_t *ip_out_q15_ref = test4 + IP_COL_DIM; + q15_t *ip_out_q15_opt = test4 + IP_COL_DIM + IP_ROW_DIM; + + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM); + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + printf("Start ref q7 implementation\n"); + + arm_fully_connected_q7_ref(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_ref, test2); + + printf("Start q7 implementation\n"); + + arm_fully_connected_q7(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt, test2); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM); + + printf("Start q7 ref opt implementation\n"); + + arm_fully_connected_q7_opt_ref(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q7_opt_fast, test2); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + printf("Start q7 opt implementation\n"); + + arm_fully_connected_q7_opt(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt_fast, + test2); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++) + { + test4[i] = (rand() % 65536 - 32768); + } + + initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref q15 implementation\n"); + + arm_fully_connected_q15_ref(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_ref, NULL); + + printf("Start q15 implementation\n"); + + arm_fully_connected_q15(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref opt q15 implementation\n"); + + arm_fully_connected_q15_opt_ref(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, + NULL); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start opt q15 implementation\n"); + + arm_fully_connected_q15_opt(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15_ref(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_ref, + test2); + + printf("Start q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_opt, + test2); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref opt q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15_opt_ref(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q15_opt, test2); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start opt q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15_opt(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q15_opt, test2); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + +#ifdef TEST_NONSQUARE + +/* Use RCONV to differential with square CONV */ + +#define RCONV_IM_DIM_X 10 +#define RCONV_IM_DIM_Y 8 +#define RCONV_IM_CH 4 +#define RCONV_KER_DIM_X 5 +#define RCONV_KER_DIM_Y 3 +#define RCONV_STRIDE_X 1 +#define RCONV_STRIDE_Y 1 +#define RCONV_PADDING_X 2 +#define RCONV_PADDING_Y 1 +#define RCONV_OUT_CH 4 +#define RCONV_OUT_DIM_X 10 +#define RCONV_OUT_DIM_Y 8 + + test1 = new q7_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; + test2 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH]; + test3 = + new q7_t[RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; + + for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++) + { + test1[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; i++) + { + test3[i] = rand() % 256 - 100; + } + + q7_t *rconv_weight_q7 = test1; + q7_t *rconv_bias_q7 = test1 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH; + + q15_t *rconv_buf = test2; + + q7_t *rconv_im_in_q7 = test3; + q7_t *rconv_im_out_ref_q7 = test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH; + q7_t *rconv_im_out_opt_q7 = + test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q7 nonsquare ref implementation\n"); + arm_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start conv q7 nonsquare opt implementation\n"); + arm_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q7 nonsquare ref implementation\n"); + arm_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start conv q7 nonsquare basic implementation\n"); + arm_convolve_HWC_q7_basic_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start 1x1 conv q7 nonsquare fast implementation\n"); + arm_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X, + RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start 1x1 conv q7 nonsquare dedicated function implementation\n"); + arm_convolve_1x1_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X, + RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start depthwise separable conv q7 nonsquare ref implementation\n"); + arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, + rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, + RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y, + rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start depthwise separable conv q7 nonsquare opt implementation\n"); + arm_depthwise_separable_conv_HWC_q7_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, + rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, + RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y, + rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + delete[]test1; + delete[]test2; + delete[]test3; + + test2 = new q15_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; // weights + bias + test4 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH //buffer + + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; // i/o + + for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++) + { + test2[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH + + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + i++) + { + test4[i] = rand() % 256 - 100; + } + + q15_t *rconv_weight_q15 = test2; + q15_t *rconv_bias_q15 = test2 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH; + + rconv_buf = test4; + + q15_t *rconv_im_in_q15 = test4 + 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH; + q15_t *rconv_im_out_ref_q15 = rconv_im_in_q15 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH; + q15_t *rconv_im_out_opt_q15 = rconv_im_out_ref_q15 + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + + initialize_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q15 nonsquare ref implementation\n"); + arm_convolve_HWC_q15_nonsquare_ref(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_ref_q15, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start conv q5 nonsquare opt implementation\n"); + arm_convolve_HWC_q15_fast_nonsquare(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_opt_q15, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + delete [] test2; + delete [] test4; +#endif + +#ifdef TEST_CONV + +#define CONV_IM_DIM 16 +#define CONV_IM_CH 16 +#define CONV_KER_DIM 5 +#define CONV_OUT_CH 16 +#define CONV_OUT_DIM 16 + + test1 = new q7_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH]; + test2 = + new q15_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH]; + test3 = new q7_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH]; + test4 = new q15_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH]; + + for (int i = 0; i < CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; i++) + { + test1[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; i++) + { + test2[i] = (rand() % 65536 - 32768); + } + + for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++) + { + test3[i] = rand() % 256 - 100; + } + + for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++) + { + test4[i] = (rand() % 65536 - 32768); + } + + q7_t *conv_weight_q7 = test1; + q7_t *conv_bias_q7 = test1 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + + q15_t *conv_weight_q15 = test2; + q15_t *conv_buf = test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + q15_t *conv_bias_q15 = + test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + + q7_t *conv_im_in_q7 = test3; + q7_t *conv_im_out_ref_q7 = test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH; + q7_t *conv_im_out_opt_q7 = + test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; + + q15_t *conv_im_in_q15 = test4; + q15_t *conv_im_out_ref_q15 = test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH; + q15_t *conv_im_out_opt_q15 = + test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; + + initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 ref implementation\n"); + + arm_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q7 basic implementation\n"); + + arm_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 fast implementation\n"); + + arm_convolve_HWC_q7_fast(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // testing with RGB + printf("start q7 ref implementation for RGB\n"); + + arm_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q7 basic implementation for RGB\n"); + + arm_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 RGB implementation for RGB\n"); + + arm_convolve_HWC_q7_RGB(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // testing q15 + initialize_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q15 ref implementation\n"); + + arm_convolve_HWC_q15_ref(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_ref_q15, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q15 basic implementation\n"); + + arm_convolve_HWC_q15_basic(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_opt_q15, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q15 fast implementation\n"); + + arm_convolve_HWC_q15_fast(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_opt_q15, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // depthwise separable conv + initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 depthwise_separable_conv ref implementation\n"); + + arm_depthwise_separable_conv_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q7 depthwise_separable_conv implementation\n"); + + arm_depthwise_separable_conv_HWC_q7(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + + test_pass = true; + test_index = 0; + while (test_flags[test_index] != -1) { + if (test_flags[test_index]) { + test_pass = false; + } + test_index ++; + } + if (test_pass) { + printf("All tests passed\n"); + } else { + printf("Test failed passed\n"); + } + + return 0; +} diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h new file mode 100644 index 0000000..264b755 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h @@ -0,0 +1,78 @@ +#ifndef _MAIN_H_ +#define _MAIN_H_ + +#include +#include +#include + +#include "arm_math.h" + +#include "arm_nnfunctions.h" +#include "ref_functions.h" + +extern int test_index; +extern q7_t test_flags[50]; + +void initialize_results_q7(q7_t * ref, q7_t * opt, int length) +{ + arm_fill_q7(0, ref, length); + arm_fill_q7(37, opt, length); +} + +void initialize_results_q15(q15_t * ref, q15_t * opt, int length) +{ + arm_fill_q15(0, ref, length); + arm_fill_q15(0x5F5, opt, length); +} + +void verify_results_q7(q7_t * ref, q7_t * opt, int length) +{ + + bool if_match = true; + + for (int i = 0; i < length; i++) + { + if (ref[i] != opt[i]) + { + printf("Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]); + + if_match = false; + } + } + + if (if_match == true) + { + printf("Outputs match.\r\n\r\n"); + test_flags[test_index++] = 0; + } else { + test_flags[test_index++] = 1; + } + +} + +void verify_results_q15(q15_t * ref, q15_t * opt, int length) +{ + + bool if_match = true; + + for (int i = 0; i < length; i++) + { + if (ref[i] != opt[i]) + { + printf("Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]); + + if_match = false; + } + } + + if (if_match == true) + { + printf("Outputs match.\r\n\r\n"); + test_flags[test_index++] = 0; + } else { + test_flags[test_index++] = 1; + } + +} + +#endif diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt new file mode 100644 index 0000000..2e9e171 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_nnexample_nn_test for + Cortex-M3, Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c new file mode 100644 index 0000000..9c64e2a --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q15.c + * Description: Q15 neural network activation function using direct table look-up + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q15 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q15(q15_t * data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q15_t *pIn = data; + q15_t *pOut = data; + uint16_t shift_size = 8 + 3 - int_width; + uint32_t bit_mask = 0x7FF >> int_width; + uint32_t full_frac = bit_mask + 1; + const q15_t *lookup_table; + + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q15; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q15; + break; + } + + while (i) + { + q15_t out; + q15_t in = *pIn++; + q15_t frac = (uint32_t) in & bit_mask; + q15_t value = lookup_table[__USAT(in >> shift_size, 8)]; + q15_t value2 = lookup_table[__USAT(1 + (in >> shift_size), 8)]; + + /* doing the interpolation here for better accuracy */ + out = ((q31_t) (full_frac - frac) * value + (q31_t) value2 * frac) >> shift_size; + + *pOut++ = out; + i--; + } + +} + +/** + * @} end of Acti group + */ diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c new file mode 100644 index 0000000..1ca429f --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q7.c + * Description: Q7 neural network activation function using direct table look-up + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q7(q7_t * data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q7_t *pIn = data; + q7_t *pOut = data; + q7_t in; + q7_t out; + uint16_t shift_size = 3 - int_width; + const q7_t *lookup_table; + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q7; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q7; + break; + } + while (i) + { + in = *pIn++; + out = lookup_table[(uint8_t) (in >> shift_size)]; + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c new file mode 100644 index 0000000..571d51c --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q15.c + * Description: Q15 version of ReLU + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void arm_relu_q15(q15_t * data, uint16_t size) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + uint16_t i = size >> 1; + q15_t *pIn = data; + q15_t *pOut = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = *__SIMD32(pIn)++; + + /* extract the first bit */ + buf = __ROR(in & 0x80008000, 15); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB16(0x00000000, buf); + + *__SIMD32(pOut)++ = in & (~mask); + i--; + } + + if (size & 0x1) + { + if (*pIn < 0) + { + *pIn = 0; + } + pIn++; + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif /* ARM_MATH_DSP */ + +} + +/** + * @} end of Acti group + */ diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c new file mode 100644 index 0000000..013325c --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q7.c + * Description: Q7 version of ReLU + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void arm_relu_q7(q7_t * data, uint16_t size) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + uint16_t i = size >> 2; + q7_t *pIn = data; + q7_t *pOut = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = *__SIMD32(pIn)++; + + /* extract the first bit */ + buf = __ROR(in & 0x80808080, 7); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB8(0x00000000, buf); + + *__SIMD32(pOut)++ = in & (~mask); + i--; + } + + i = size & 0x3; + while (i) + { + if (*pIn < 0) + { + *pIn = 0; + } + pIn++; + i--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif /* ARM_MATH_DSP */ + +} + +/** + * @} end of Acti group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c new file mode 100644 index 0000000..2f4133c --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1x1_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of 1x1 convolution (non-square shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is optimized for convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for the second half of MobileNets [1] after depthwise + * separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + * + * [1] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications + * https://arxiv.org/abs/1704.04861 + */ + +arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x; + int16_t i_ch_out; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 + || padding_x != 0 || padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_out_y * dim_im_in_x + i_out_x) * ch_im_in, pBuffer, + ch_im_in); + pBuffer += ch_im_in; + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + q31_t sum = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t) __SSAT((sum >> out_shift), 8); + pOut++; + + } + + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 + || padding_x != 0 || padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_y + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c new file mode 100644 index 0000000..00b5aa5 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_basic.c + * Description: Q15 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +arm_status +arm_convolve_HWC_q15_basic(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + uint16_t im2col_out_pixel_index = 0; + q15_t *pBuffer = bufferA; + q15_t *pOut = Im_out; + q15_t *im_buffer = bufferA; + const q15_t *pA; + int i; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); + } + pBuffer += ch_im_in; + } + } + + pA = wt; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = im_buffer; + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + while (colCnt) + { + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA2 = *__SIMD32(pA)++; + q31_t inB2 = *__SIMD32(pB)++; + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q15_t) __SSAT((sum >> out_shift), 16); + pOut++; + } + + /* counter reset */ + pBuffer = im_buffer; + im2col_out_pixel_index++; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c new file mode 100644 index 0000000..c9873c1 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +arm_status +arm_convolve_HWC_q15_fast(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel * dim_kernel; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel * dim_kernel; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA2 = *__SIMD32(pA2)++; + q31_t inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel * dim_kernel; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c new file mode 100644 index 0000000..0274202 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: 24. May 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +arm_status +arm_convolve_HWC_q15_fast_nonsquare(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA2 = *__SIMD32(pA2)++; + q31_t inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel_y * dim_kernel_x; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c new file mode 100644 index 0000000..42bfb1f --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_RGB.c + * Description: Q7 version of convolution for RGB image + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Q7 convolution function for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals 3 + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +arm_status +arm_convolve_HWC_q7_RGB(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, const uint16_t dim_im_out, q15_t * bufferA, q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_MATH_SIZE_MISMATCH; + } + // This part implements the im2col function + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Equivalent to arm_fill_q15(0, pBuffer, ch_im_in) with assumption: ch_im_in = 3 */ + *__SIMD32(pBuffer) = 0x0; + *(pBuffer + 2) = 0; + pBuffer += 3; + } else + { + /* + * Equivalent to: + * arm_q7_to_q15_no_shift( (q7_t*)Im_in+(i_ker_y*dim_im_in+i_ker_x)*3, pBuffer, 3); + */ + + const q7_t *pPixel = Im_in + (i_ker_y * dim_im_in + i_ker_x) * 3; + q31_t buf = *__SIMD32(pPixel); + + union arm_nnword top; + union arm_nnword bottom; + + top.word = __SXTB16(buf); + bottom.word = __SXTB16(__ROR(buf, 8)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * little-endian, | omit | 3rd | 2nd | 1st | + * MSB LSB + * top | 3rd | 1st |; bottom | omit | 2nd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = top.word; + * *(pBuffer+2) = bottom.half_words[0]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = top.half_words[0]; + *__SIMD32(pBuffer) = __PKHBT(bottom.word, top.word, 0); +#else + /* + * big-endian, | 1st | 2nd | 3rd | omit | + * MSB LSB + * top | 2nd | omit |; bottom | 1st | 3rd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = bottom.word; + * *(pBuffer+2) = top.half_words[1]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = bottom.half_words[0]; + *__SIMD32(pBuffer) = __PKHTB(top.word, bottom.word, 0); +#endif + pBuffer += 2; + } + } + } + + if (pBuffer == bufferA + 2 * 3 * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15(wt, bufferA, + ch_im_out, + 3 * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = 3 * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = 3 * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + /* if-for implementation */ + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c new file mode 100644 index 0000000..a926086 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +arm_status +arm_convolve_HWC_q7_basic(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift((q7_t *) + Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15(wt, bufferA, + ch_im_out, + ch_im_in * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c new file mode 100644 index 0000000..b426b92 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + */ + +arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift((q7_t *) + Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_y * dim_kernel_x) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15(wt, bufferA, + ch_im_out, + ch_im_in * + dim_kernel_y * dim_kernel_x, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c new file mode 100644 index 0000000..7b59d79 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast.c + * Description: Fast Q7 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 4 ( because of the SIMD32 read and swap ) + * + * ch_im_out is multipe of 2 ( bacause 2x2 mat_mult kernel ) + * + * The im2col converts the Q7 tensor input into Q15 column, which is stored in + * bufferA. There is reordering happenning during this im2col process with + * arm_q7_to_q15_reordered_no_shift. For every four elements, the second and + * third elements are swapped. + * + * The computation kernel arm_nn_mat_mult_kernel_q7_q15_reordered does the + * GEMM computation with the reordered columns. + * + * To speed-up the determination of the padding condition, we split the + * computation into 3x3 parts, i.e., {top, mid, bottom} X {left, mid, right}. + * This reduces the total number of boundary condition checks and improves + * the data copying performance. + */ + +arm_status +arm_convolve_HWC_q7_fast(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out - padding; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out - padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + + + (i_ker_y * + dim_im_in + + i_out_x * + stride - padding) * ch_im_in, pBuffer, ch_im_in * dim_kernel); + pBuffer += ch_im_in * dim_kernel; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad_reordered((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t) __SSAT((sum >> out_shift), 8); + pOut++; + + } + + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c new file mode 100644 index 0000000..f2aa4a2 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c @@ -0,0 +1,379 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of convolution (non-sqaure shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out_y - padding_y; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out_x - padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + + (i_ker_y * dim_im_in_x + i_out_x * stride_x - padding_x) * ch_im_in, + pBuffer, ch_im_in * dim_kernel_x); + pBuffer += ch_im_in * dim_kernel_x; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = (ch_im_in * dim_kernel_y * dim_kernel_x) & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t) __SSAT((sum >> out_shift), 8); + pOut++; + + } + + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + /* if-for implementation */ + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c new file mode 100644 index 0000000..b6cd573 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_u8_basic_ver1.c + * Description: u8 depthwise convolution function + * + * $Date: June, 2019 + * $Revision: V.0.8.0 + * + * Target : Cortex-M cores with DSP extension + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" +#include +#include + +#define DILATION_X (1) +#define DILATION_Y (1) + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization for even number of channel multiplier + * and input channels. Unless specified otherwise, arguments are mandatory. Both square and non-square inputs + * are accepted. + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x Convolution stride along the width + * @param[in] stride_y Convolution stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * availble, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] out_shift Amount of right-shift for output + * @param[in] out_mult Output multiplier for requantization + * @return The function returns one of the following + * ARM_MATH_SIZE_MISMATCH - Not supported dimension of tensors + * ARM_MATH_SUCCESS - Successful operation + * ARM_MATH_ARGUMENT_ERROR - Implementation not available + * + * Input constraints + * ch_mult is multiple of 2 + * kernel_x is multiple of 2 + * + */ + +arm_status arm_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t out_shift, + const int32_t out_mult) +{ + arm_status status = ARM_MATH_SUCCESS; + #if defined (ARM_MATH_DSP) + int i_out = 0; + (void)dilation_x; + (void)dilation_y; + + const int32_t input_offset_pkd = (input_offset & 0xFFFF) | (input_offset & 0xFFFF) << 16; + const int32_t kernel_offset_pkd = (filter_offset & 0xFFFF) | (filter_offset & 0xFFFF) << 16; + + if (0 != ch_mult % 2 || 0 != kernel_x % 2) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult += 2) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + + int32_t acc_0 = 0; + int32_t acc_1 = 0; + if (NULL != bias) + { + acc_0 = bias[idx_out_ch]; + acc_1 = bias[idx_out_ch + 1]; + } + + for (int i_ker_y = 0; i_ker_y < kernel_y; i_ker_y++) + { + const int32_t idx_y = base_idx_y + DILATION_Y * i_ker_y; + const int32_t y_in_range = (idx_y >= 0) && (idx_y < input_y); + + for (int i_ker_x = 0; i_ker_x < kernel_x; i_ker_x += 2) + { + if (1 == y_in_range) + { + const int32_t idx_x = base_idx_x + DILATION_X * i_ker_x; + const int32_t idx_x1 = base_idx_x + DILATION_X * (i_ker_x + 1); + /* Range check for first input */ + if (idx_x >= 0 && idx_x < input_x) + { + const int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + + const int32_t ker_idx_0 = + (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + const int32_t ker_idx_1 = ker_idx_0 + input_ch * ch_mult; + + int32_t input_pkd = input[idx_0] | (input[idx_0 + input_ch] << 16); + int32_t kernel_pkd = kernel[ker_idx_0] | (kernel[ker_idx_1] << 16); + + input_pkd = __SADD16(input_pkd, input_offset_pkd); + kernel_pkd = __SADD16(kernel_pkd, kernel_offset_pkd); + /* Range check for second input */ + if (idx_x1 >= input_x) + { + input_pkd &= 0xFFFF; + } + acc_0 = __SMLAD(input_pkd, kernel_pkd, acc_0); + + kernel_pkd = kernel[ker_idx_0 + 1] | (kernel[ker_idx_1 + 1] << 16); + kernel_pkd = __SADD16(kernel_pkd, kernel_offset_pkd); + acc_1 = __SMLAD(input_pkd, kernel_pkd, acc_1); + } + } + } + } + + /* Requantize and clamp output to provided range */ + acc_0 = arm_nn_divide_by_power_of_two(arm_nn_sat_doubling_high_mult( + acc_0 * (1 << LEFT_SHIFT(out_shift)), out_mult), + RIGHT_SHIFT(out_shift)); + + acc_0 += output_offset; + + if (output_activation_min > acc_0) + { + acc_0 = output_activation_min; + } + + if (acc_0 > output_activation_max) + { + acc_0 = output_activation_max; + } + output[i_out++] = acc_0; + + /* Requantize and clamp output to provided range */ + acc_1 = arm_nn_divide_by_power_of_two(arm_nn_sat_doubling_high_mult( + acc_1 * (1 << LEFT_SHIFT(out_shift)), out_mult), + RIGHT_SHIFT(out_shift)); + acc_1 += output_offset; + + if (output_activation_min > acc_1) + { + acc_1 = output_activation_min; + } + + if (acc_1 > output_activation_max) + { + acc_1 = output_activation_max; + } + output[i_out++] = acc_1; + } + } + } + } +#else + /* No available implementation. */ + status = ARM_MATH_ARGUMENT_ERROR; +#endif + return status; +} + +/** + * @} end of NNConv group + */ + + diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c new file mode 100644 index 0000000..68ebeb8 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c @@ -0,0 +1,418 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7.c + * Description: Q7 depthwise separable convolution function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals ch_im_out + * + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + */ + +arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *) bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel * dim_kernel) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] + "+r"(sum),[sum2] "+r"(sum2), + [sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB), + [pA] "+r"(pA):[colCnt] + "r"(colCnt),[ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); +#else + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] + "+r"(sum),[sum2] "+r"(sum2), + [sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB), + [pA] "+r"(pA):[colCnt] + "r"(colCnt),[ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel * dim_kernel) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = *__SIMD32(pA); + pA += ch_im_in; + inB.word = *__SIMD32(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel * dim_kernel); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + rowCnt--; + } + + /* clear counter and pointers */ + pBuffer = colBuffer; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out, i_ker_x, i_ker_y; + int conv_out; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += + Im_in[(in_row * + dim_im_in + + in_col) * + ch_im_in + + i_ch_out] * wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + + i_out_x) * ch_im_out + i_ch_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; + +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c new file mode 100644 index 0000000..397f233 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c @@ -0,0 +1,411 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7_nonsquare.c + * Description: Q7 depthwise separable convolution function (non-square shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + +arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + +/* + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + * + */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *) bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel_x * dim_kernel_y) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile ("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n":[sum] "+r"(sum),[sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt), + [ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); +#else + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile ("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n":[sum] "+r"(sum),[sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt), + [ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); +#endif /*ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel_x * dim_kernel_y) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = *__SIMD32(pA); + pA += ch_im_in; + inB.word = *__SIMD32(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel_x * dim_kernel_y); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + rowCnt--; + } + + // clear counter and pointers + pBuffer = colBuffer; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + int conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + + /* Return to application */ + return ARM_MATH_SUCCESS; + +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c new file mode 100644 index 0000000..a4adc5d --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + + /** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + * + * @details + * + * This function does the matrix multiplication with weight matrix + * and 2 columns from im2col. + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ +#if defined (ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + const q7_t *pBias = bias; + + uint16_t rowCnt = ch_im_out >> 1; + /* this loop over rows in A */ + while (rowCnt) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + pA = (q7_t *) read_and_pad((void *)pA, &inA11, &inA12); + pA2 = (q7_t *) read_and_pad((void *)pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = *__SIMD32(pB)++; + inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + rowCnt--; + } /* for over ch_im_out */ + + /* compute left-over row if any */ + if (ch_im_out & 0x1) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* load the bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + while (colCnt) + { + q31_t inA11, inA12; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + pA = (q7_t *) read_and_pad((void *)pA, &inA11, &inA12); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + + inB1 = *__SIMD32(pB)++; + inB2 = *__SIMD32(pB2)++; + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + + colCnt--; + } + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + colCnt--; + } + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + } + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ + +} diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c new file mode 100644 index 0000000..deef7c6 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_math.h" + + /** + * @brief Matrix-multiplication function for convolution with reordered columns + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + * + * @details + * + * This function assumes that data in pInBuffer are reordered + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ + +#if defined (ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + int i; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + pA = (q7_t *) read_and_pad_reordered((void *)pA, &inA11, &inA12); + pA2 = (q7_t *) read_and_pad_reordered((void *)pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = *__SIMD32(pB)++; + inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + } /* for over ch_im_out */ + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ +} diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c new file mode 100644 index 0000000..2746967 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c @@ -0,0 +1,199 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15.c + * Description: Mixed Q15-Q7 fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + */ + +arm_status +arm_fully_connected_mat_q7_vec_q15(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12); + pB2 = (q7_t *) read_and_pad((void *)pB2, &inM21, &inM22); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16)); + + /*adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c new file mode 100644 index 0000000..7be156f --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c @@ -0,0 +1,403 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15_opt.c + * Description: Mixed Q15-Q7 opt fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + * Limitation: x4 version requires weight reordering to work + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a12 | a22 | a31 | a41 | a32 | a42 | + * + * | a13 | a23 | a14 | a24 | a33 | a43 | a34 | a44 | + * + * | a15 | a25 | a16 | a26 | a35 | a45 | a36 | a46 | + * + * The column left over will be in-order. + * which is: + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a12 | a22 | a31 | a41 | + * + * | a32 | a42 | a13 | a23 | a14 | a24 | + * + * | a33 | a43 | a34 | a44 | a15 | a25 | + * + * | a16 | a26 | a35 | a45 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + */ + +arm_status +arm_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, const q7_t * bias, q15_t * pOut, q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } + +#else + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#else + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c new file mode 100644 index 0000000..c3e7cf2 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15.c + * Description: Q15 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + */ + +arm_status +arm_fully_connected_q15(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + const q15_t *pB2 = pB + dim_vec; + q15_t *pO = pOut; + const q15_t *pA; + const q15_t *pBias = bias; + uint16_t rowCnt = num_of_rows >> 1; + + /* this loop loops over different output */ + while (rowCnt) { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV1, inM1, inM2; + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + inM2 = *__SIMD32(pB2)++; + sum2 = __SMLAD(inV1, inM2, sum2); + + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + inM2 = *__SIMD32(pB2)++; + sum2 = __SMLAD(inV1, inM2, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2>> out_shift), 16)); + + /* adjust the pointers and counters */ + pB = pB + dim_vec; + rowCnt --; + } + + rowCnt = num_of_rows & 0x1; + + while (rowCnt) { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) { + q31_t inV1, inM1; + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while(colCnt) { + q15_t inV = *pA++; + q15_t inM = *pB++; + + sum += inV * inM; + + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt --; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c new file mode 100644 index 0000000..f7a3915 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c @@ -0,0 +1,332 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15_opt.c + * Description: Q15 opt fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original matrix looks like this: + * + * | a11 | a12 | a13 | + * + * | a21 | a22 | a23 | + * + * | a31 | a32 | a33 | + * + * | a41 | a42 | a43 | + * + * | a51 | a52 | a53 | + * + * | a61 | a62 | a63 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | + * + * Remaining rows are kept the same original order. + * + * So the stored weight matrix looks like this: + * + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | a51 | a52 | a53 | a61 | + * + * | a62 | a63 | + */ + +arm_status +arm_fully_connected_q15_opt(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + q15_t *pO = pOut; + const q15_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + sum = __SMLAD(inV, inM11, sum); + inM12 = *__SIMD32(pB)++; + sum2 = __SMLAD(inV, inM12, sum2); + inM13 = *__SIMD32(pB)++; + sum3 = __SMLAD(inV, inM13, sum3); + inM14 = *__SIMD32(pB)++; + sum4 = __SMLAD(inV, inM14, sum4); + colCnt--; + } + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r0, [%[pB]], #16\n" + "smlad %[sum], r4, r0, %[sum]\n" + "ldr.w r1, [%[pB] , #-12]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r2, [%[pB] , #-8]\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "ldr.w r3, [%[pB] , #-4]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB++; + q15_t inM3 = *pB++; + q15_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM1, inM2; + + inM1 = *__SIMD32(pB)++; + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM1, sum); + + inM2 = *__SIMD32(pB)++; + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM2, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c new file mode 100644 index 0000000..d8efc04 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q7 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This basic function is designed to work with regular weight + * matrix without interleaving. + * + */ + +arm_status +arm_fully_connected_q7(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, const q7_t * bias, q7_t * pOut, q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q7_t *pO = pOut; + const q7_t *pBias = bias; + q15_t *pA; + uint16_t rowCnt = num_of_rows >> 1; + + /* expand the vector into the buffer */ + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12); + pB2 = (q7_t *) read_and_pad_reordered((void *)pB2, &inM21, &inM22); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum2 >> out_shift), 8)); + + /* adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + uint16_t colCnt = dim_vec >> 2; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + int i, j; + + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t) __SSAT((ip_out >> out_shift), 8); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c new file mode 100644 index 0000000..e3d0874 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c @@ -0,0 +1,484 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7_opt.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This opt function is designed to work with interleaved weight + * matrix. The vector input is assumed in q7_t format, we call + * arm_q7_to_q15_no_shift_shuffle function to expand into + * q15_t format with certain weight re-ordering, refer to the function + * comments for more details. + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a13 | a23 | a31 | a41 | a33 | a43 | + * + * | a12 | a22 | a14 | a24 | a32 | a42 | a34 | a44 | + * + * | a15 | a25 | a35 | a45 | a16 | a26 | a36 | a46 | + * + * So within the kernel, we first read the re-ordered vector in as: + * + * | b1 | b3 | and | b2 | b4 | + * + * the four q31_t weights will look like + * + * | a11 | a13 |, | a21 | a23 |, | a31 | a33 |, | a41 | a43 | + * + * | a12 | a14 |, | a22 | a24 |, | a32 | a34 |, | a42 | a44 | + * + * The column left over will be in-order. + * which is: + * + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a13 | a23 | a31 | a41 | + * + * | a33 | a43 | a12 | a22 | a14 | a24 | + * + * | a32 | a42 | a34 | a44 | a15 | a25 | + * + * | a35 | a45 | a16 | a26 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + */ + +arm_status +arm_fully_connected_q7_opt(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q7_t *pO = pOut; + const q7_t *pBias = bias; + q15_t *pA; + uint16_t rowCnt = num_of_rows >> 2; + + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } +#else + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#else + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum2 >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum3 >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum4 >> out_shift), 8)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t) __SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c new file mode 100644 index 0000000..5a60459 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q15.c + * Description: Q15 vector multiplication with variable output shifts + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inB1, inB2; /* temporary input variables */ + q15_t out1, out2, out3, out4; /* temporary output variables */ + q31_t mul1, mul2, mul3, mul4; /* temporary variables */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* read two samples at a time from sourceA */ + inA1 = *__SIMD32(pSrcA)++; + /* read two samples at a time from sourceB */ + inB1 = *__SIMD32(pSrcB)++; + /* read two samples at a time from sourceA */ + inA2 = *__SIMD32(pSrcA)++; + /* read two samples at a time from sourceB */ + inB2 = *__SIMD32(pSrcB)++; + + /* multiply mul = sourceA * sourceB */ + mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2); + + /* saturate result to 16 bit */ + out1 = (q15_t) __SSAT((mul1 + NN_ROUND(out_shift)) >> out_shift, 16); + out2 = (q15_t) __SSAT((mul2 + NN_ROUND(out_shift)) >> out_shift, 16); + out3 = (q15_t) __SSAT((mul3 + NN_ROUND(out_shift)) >> out_shift, 16); + out4 = (q15_t) __SSAT((mul4 + NN_ROUND(out_shift)) >> out_shift, 16); + + /* store the result */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); + *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); + *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ + diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c new file mode 100644 index 0000000..3735c04 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q7.c + * Description: Q7 vector multiplication with variable output shifts + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the results in temporary variables */ + out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Store the results of 4 inputs in the destination buffer in single cycle by packing */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c new file mode 100644 index 0000000..c28f1a6 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nntables.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @brief tables for various activation functions + * + * This file include the declaration of common tables. + * Most of them are used for activation functions + * + * Assumption: + * Unified table: input is 3.x format, i.e, range of [-8, 8) + * sigmoid(8) = 0.9996646498695336 + * tanh(8) = 0.9999997749296758 + * The accuracy here should be good enough + * + * 2-stage HL table: + * + * The entire input range is divided into two parts: + * + * Low range table: 0x000x xxxx or 0x111x xxxx + * table entry will be the binary number excluding the first + * two digits, i.e., 0x0x xxxx or 0x1x xxxx + * + * + * + * High range table 0x0010 0000 -- 0x0111 1111 + * 0x1000 0000 -- 0x1101 1111 + * + * For positive numbers, table entry will be + * 0x0010 0000 -- 0x0111 1111 minus 0x0010 0000 + * i.e., 0x0000 0000 - 0x0101 11111 + * + * same thing for the negative numbers, table entry will be + * 0x1000 0000 -- 0x1101 1111 minux 0x0010 0000 + * i.e., 0x0110 0000 - 0x1011 1111 + */ + +const q7_t sigmoidTable_q7[256] = { + 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, + 0x50, 0x52, 0x53, 0x55, 0x57, 0x59, 0x5a, 0x5c, + 0x5e, 0x5f, 0x61, 0x62, 0x63, 0x65, 0x66, 0x67, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x71, 0x72, 0x72, 0x73, 0x74, 0x74, 0x75, 0x76, + 0x76, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7a, + 0x7a, 0x7a, 0x7b, 0x7b, 0x7b, 0x7c, 0x7c, 0x7c, + 0x7c, 0x7c, 0x7d, 0x7d, 0x7d, 0x7d, 0x7d, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06, + 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0c, 0x0c, 0x0d, 0x0e, 0x0e, + 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, + 0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21, + 0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, 0x2e, + 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, +}; + +const q15_t sigmoidTable_q15[256] = { + 0x4000, 0x4200, 0x43ff, 0x45fc, 0x47f5, 0x49eb, 0x4bdc, 0x4dc8, + 0x4fad, 0x518a, 0x5360, 0x552c, 0x56ef, 0x58a8, 0x5a57, 0x5bfb, + 0x5d93, 0x5f20, 0x60a1, 0x6216, 0x637f, 0x64db, 0x662b, 0x676f, + 0x68a6, 0x69d2, 0x6af1, 0x6c05, 0x6d0d, 0x6e09, 0x6efb, 0x6fe2, + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, + 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, + 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, + 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, + 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, + 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, + 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, + 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, + 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, + 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, + 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, + 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, + 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, + 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, + 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, + 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, + 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, + 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, + 0x0f42, 0x101e, 0x1105, 0x11f7, 0x12f3, 0x13fb, 0x150f, 0x162e, + 0x175a, 0x1891, 0x19d5, 0x1b25, 0x1c81, 0x1dea, 0x1f5f, 0x20e0, + 0x226d, 0x2405, 0x25a9, 0x2758, 0x2911, 0x2ad4, 0x2ca0, 0x2e76, + 0x3053, 0x3238, 0x3424, 0x3615, 0x380b, 0x3a04, 0x3c01, 0x3e00, +}; + +const q15_t sigmoidLTable_q15[128] = { + 0x4000, 0x4100, 0x4200, 0x42ff, 0x43ff, 0x44fd, 0x45fc, 0x46f9, + 0x47f5, 0x48f1, 0x49eb, 0x4ae5, 0x4bdc, 0x4cd3, 0x4dc8, 0x4ebb, + 0x4fad, 0x509c, 0x518a, 0x5276, 0x5360, 0x5447, 0x552c, 0x560f, + 0x56ef, 0x57cd, 0x58a8, 0x5981, 0x5a57, 0x5b2a, 0x5bfb, 0x5cc9, + 0x5d93, 0x5e5b, 0x5f20, 0x5fe2, 0x60a1, 0x615d, 0x6216, 0x62cc, + 0x637f, 0x642e, 0x64db, 0x6584, 0x662b, 0x66ce, 0x676f, 0x680c, + 0x68a6, 0x693d, 0x69d2, 0x6a63, 0x6af1, 0x6b7c, 0x6c05, 0x6c8a, + 0x6d0d, 0x6d8d, 0x6e09, 0x6e84, 0x6efb, 0x6f70, 0x6fe2, 0x7051, + 0x0f42, 0x0faf, 0x101e, 0x1090, 0x1105, 0x117c, 0x11f7, 0x1273, + 0x12f3, 0x1376, 0x13fb, 0x1484, 0x150f, 0x159d, 0x162e, 0x16c3, + 0x175a, 0x17f4, 0x1891, 0x1932, 0x19d5, 0x1a7c, 0x1b25, 0x1bd2, + 0x1c81, 0x1d34, 0x1dea, 0x1ea3, 0x1f5f, 0x201e, 0x20e0, 0x21a5, + 0x226d, 0x2337, 0x2405, 0x24d6, 0x25a9, 0x267f, 0x2758, 0x2833, + 0x2911, 0x29f1, 0x2ad4, 0x2bb9, 0x2ca0, 0x2d8a, 0x2e76, 0x2f64, + 0x3053, 0x3145, 0x3238, 0x332d, 0x3424, 0x351b, 0x3615, 0x370f, + 0x380b, 0x3907, 0x3a04, 0x3b03, 0x3c01, 0x3d01, 0x3e00, 0x3f00, +}; + +const q15_t sigmoidHTable_q15[192] = { + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, + 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, + 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, + 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, + 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, + 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, + 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, + 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, + 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, + 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, + 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, + 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, + 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, + 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, + 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, + 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, + 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, + 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, +}; + +const q7_t tanhTable_q7[256] = { + 0x00, 0x08, 0x10, 0x18, 0x1f, 0x27, 0x2e, 0x35, + 0x3b, 0x41, 0x47, 0x4c, 0x51, 0x56, 0x5a, 0x5e, + 0x61, 0x65, 0x68, 0x6a, 0x6d, 0x6f, 0x71, 0x72, + 0x74, 0x75, 0x76, 0x78, 0x78, 0x79, 0x7a, 0x7b, + 0x7b, 0x7c, 0x7c, 0x7d, 0x7d, 0x7e, 0x7e, 0x7e, + 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, + 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x82, + 0x82, 0x82, 0x82, 0x82, 0x83, 0x83, 0x84, 0x84, + 0x85, 0x85, 0x86, 0x87, 0x88, 0x88, 0x8a, 0x8b, + 0x8c, 0x8e, 0x8f, 0x91, 0x93, 0x96, 0x98, 0x9b, + 0x9f, 0xa2, 0xa6, 0xaa, 0xaf, 0xb4, 0xb9, 0xbf, + 0xc5, 0xcb, 0xd2, 0xd9, 0xe1, 0xe8, 0xf0, 0xf8, +}; + +const q15_t tanhTable_q15[256] = { + 0x0000, 0x07fd, 0x0feb, 0x17b9, 0x1f59, 0x26bf, 0x2ddf, 0x34ae, + 0x3b27, 0x4142, 0x46fd, 0x4c56, 0x514d, 0x55e2, 0x5a1a, 0x5df6, + 0x617c, 0x64b0, 0x6797, 0x6a37, 0x6c95, 0x6eb5, 0x709e, 0x7254, + 0x73dc, 0x753a, 0x7672, 0x7788, 0x787f, 0x795b, 0x7a1e, 0x7acb, + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, + 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, + 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, + 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, + 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, + 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, + 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, + 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, + 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, + 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, + 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, + 0x849b, 0x8535, 0x85e2, 0x86a5, 0x8781, 0x8878, 0x898e, 0x8ac6, + 0x8c24, 0x8dac, 0x8f62, 0x914b, 0x936b, 0x95c9, 0x9869, 0x9b50, + 0x9e84, 0xa20a, 0xa5e6, 0xaa1e, 0xaeb3, 0xb3aa, 0xb903, 0xbebe, + 0xc4d9, 0xcb52, 0xd221, 0xd941, 0xe0a7, 0xe847, 0xf015, 0xf803, +}; + +const q15_t tanhLTable_q15[128] = { + 0x0000, 0x0400, 0x07fd, 0x0bf7, 0x0feb, 0x13d7, 0x17b9, 0x1b90, + 0x1f59, 0x2314, 0x26bf, 0x2a58, 0x2ddf, 0x3151, 0x34ae, 0x37f6, + 0x3b27, 0x3e40, 0x4142, 0x442c, 0x46fd, 0x49b6, 0x4c56, 0x4edd, + 0x514d, 0x53a3, 0x55e2, 0x580a, 0x5a1a, 0x5c13, 0x5df6, 0x5fc4, + 0x617c, 0x6320, 0x64b0, 0x662d, 0x6797, 0x68f0, 0x6a37, 0x6b6e, + 0x6c95, 0x6dac, 0x6eb5, 0x6fb0, 0x709e, 0x717f, 0x7254, 0x731e, + 0x73dc, 0x7490, 0x753a, 0x75da, 0x7672, 0x7701, 0x7788, 0x7807, + 0x787f, 0x78f0, 0x795b, 0x79bf, 0x7a1e, 0x7a77, 0x7acb, 0x7b1b, + 0x849b, 0x84e5, 0x8535, 0x8589, 0x85e2, 0x8641, 0x86a5, 0x8710, + 0x8781, 0x87f9, 0x8878, 0x88ff, 0x898e, 0x8a26, 0x8ac6, 0x8b70, + 0x8c24, 0x8ce2, 0x8dac, 0x8e81, 0x8f62, 0x9050, 0x914b, 0x9254, + 0x936b, 0x9492, 0x95c9, 0x9710, 0x9869, 0x99d3, 0x9b50, 0x9ce0, + 0x9e84, 0xa03c, 0xa20a, 0xa3ed, 0xa5e6, 0xa7f6, 0xaa1e, 0xac5d, + 0xaeb3, 0xb123, 0xb3aa, 0xb64a, 0xb903, 0xbbd4, 0xbebe, 0xc1c0, + 0xc4d9, 0xc80a, 0xcb52, 0xceaf, 0xd221, 0xd5a8, 0xd941, 0xdcec, + 0xe0a7, 0xe470, 0xe847, 0xec29, 0xf015, 0xf409, 0xf803, 0xfc00, +}; + +const q15_t tanhHTable_q15[192] = { + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, + 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, + 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, + 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, + 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, + 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, + 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, + 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, + 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, + 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, + 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, +}; diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c new file mode 100644 index 0000000..264e760 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_no_shift.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
    
+ * 	pDst[n] = (q15_t) pSrc[n];   0 <= n < blockSize.    
+ *
+ * + */ + +void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0_FAMILY + q31_t in; + q31_t in1, in2; + q31_t out1, out2; + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = *__SIMD32(pIn)++; + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + + out2 = __PKHTB(in1, in2, 16); + out1 = __PKHBT(in2, in1, 16); + +#else + + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in2, in1, 16); + +#endif + + *__SIMD32(pDst)++ = out1; + *__SIMD32(pDst)++ = out2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) * pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of nndata_convert group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c new file mode 100644 index 0000000..7d29aa4 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_reordered_no_shift.c + * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + * @details + * + * This function does the q7 to q15 expansion with re-ordering + * + * 
+ *                          |   A1   |   A2   |   A3   |   A4   |
+ *
+ *                           0      7 8     15 16    23 24    31
+ *
+ * + * is converted into: + * + * 
+ *  |       A1       |       A3       |   and  |       A2       |       A4       |
+ *
+ *   0             15 16            31          0             15 16            31
+ *
+ * + * + * This looks strange but is natural considering how sign-extension is done at + * assembly level. + * + * The expansion of other other oprand will follow the same rule so that the end + * results are the same. + * + * The tail (i.e., last (N % 4) elements) will still be in original order. + * + */ + +void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0_FAMILY + q31_t in; + q31_t in1, in2; + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = *__SIMD32(pIn)++; + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + *__SIMD32(pDst)++ = in2; + *__SIMD32(pDst)++ = in1; +#else + *__SIMD32(pDst)++ = in1; + *__SIMD32(pDst)++ = in2; +#endif + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) * pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of q7_to_x group + */ diff --git a/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c new file mode 100644 index 0000000..2956774 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c @@ -0,0 +1,460 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_pool_q7_HWC.c + * Description: Pooling function implementations + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +#if defined (ARM_MATH_DSP) + +/** + * @brief A few utility functions used by pooling functions + * + * + */ + +static void buffer_scale_back_q15_to_q7(q15_t * buffer, q7_t * target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t) (buffer[i] / scale); + } +} + +static void compare_and_replace_if_larger_q7(q7_t * base, // base data + const q7_t * target, // compare target + const uint16_t length // data length + ) +{ + q7_t *pIn = base; + const q7_t *pCom = target; + union arm_nnword in; + union arm_nnword com; + uint16_t cnt = length >> 2; + + while (cnt > 0u) + { + in.word = *__SIMD32(pIn); + com.word = *__SIMD32(pCom)++; + + // if version + if (com.bytes[0] > in.bytes[0]) + in.bytes[0] = com.bytes[0]; + if (com.bytes[1] > in.bytes[1]) + in.bytes[1] = com.bytes[1]; + if (com.bytes[2] > in.bytes[2]) + in.bytes[2] = com.bytes[2]; + if (com.bytes[3] > in.bytes[3]) + in.bytes[3] = com.bytes[3]; + + *__SIMD32(pIn)++ = in.word; + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0u) + { + if (*pCom > *pIn) + { + *pIn = *pCom; + } + pIn++; + pCom++; + cnt--; + } +} + +static void accumulate_q7_to_q15(q15_t * base, q7_t * target, const uint16_t length) +{ + q15_t *pCnt = base; + q7_t *pV = target; + q31_t v1, v2, vo1, vo2; + uint16_t cnt = length >> 2; + q31_t in; + + while (cnt > 0u) + { + q31_t value = *__SIMD32(pV)++; + v1 = __SXTB16(__ROR(value, 8)); + v2 = __SXTB16(value); +#ifndef ARM_MATH_BIG_ENDIAN + + vo2 = __PKHTB(v1, v2, 16); + vo1 = __PKHBT(v2, v1, 16); + +#else + + vo1 = __PKHTB(v1, v2, 16); + vo2 = __PKHBT(v2, v1, 16); + +#endif + + in = *__SIMD32(pCnt); + *__SIMD32(pCnt)++ = __QADD16(vo1, in); + + in = *__SIMD32(pCnt); + *__SIMD32(pCnt)++ = __QADD16(vo2, in); + + cnt--; + } + cnt = length & 0x3; + while (cnt > 0u) + { + *pCnt++ += *pV++; + cnt--; + } +} + +#endif // ARM_MATH_DSP + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + + /** + * @brief Q7 max pooling function + * @param[in, out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + * @details + * + * Buffer size: + * + * bufferA size: 0 + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void +arm_maxpool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, const uint16_t dim_im_out, q7_t * bufferA, q7_t * Im_out) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_x, i_y; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + /* arm_copy_q7(win_start, target, ch_im_in); */ + memmove(target, win_start, ch_im_in); + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + compare_and_replace_if_larger_q7(target, win_start, ch_im_in); + } + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + /* arm_copy_q7(row_start, target, dim_im_out * ch_im_in); */ + memmove(target, row_start, dim_im_out * ch_im_in); + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + compare_and_replace_if_larger_q7(target, row_start, dim_im_out * ch_im_in); + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } + +#endif /* ARM_MATH_DSP */ + +} + + /** + * @brief Q7 average pooling function + * @param[in,out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*dim_im_out*ch_im_in + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void +arm_avepool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, const uint16_t dim_im_out, q7_t * bufferA, q7_t * Im_out) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + q15_t *buffer = (q15_t *) bufferA; + int16_t i_x, i_y; + int16_t count = 0; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + arm_q7_to_q15_no_shift(win_start, buffer, ch_im_in); + count = 1; + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + accumulate_q7_to_q15(buffer, win_start, ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, ch_im_in, count); + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + arm_q7_to_q15_no_shift(row_start, buffer, dim_im_out * ch_im_in); + count = 1; + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + accumulate_q7_to_q15(buffer, row_start, dim_im_out * ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, dim_im_out * ch_im_in, count); + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } + +#endif /* ARM_MATH_DSP */ + +} + +/** + * @} end of Pooling group + */ diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c new file mode 100644 index 0000000..abc2737 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q15.c + * Description: Q15 softmax function + * + * $Date: 20. February 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + + /** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + * @details + * + * Here, instead of typical e based softmax, we use + * 2-based softmax, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q31_t base; + base = -1 * 0x100000; + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* we ignore really small values + * anyway, they will be 0 after shrinking + * to q15_t + */ + base = base - 16; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 32) / sum */ + int64_t div_base = 0x100000000LL; + int output_base = (int32_t)(div_base / sum); + + /* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) ) + * so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16 + * and vec_in[i]-base = 16 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 17+base-vec[i] will be 1 */ + shift = (uint8_t)__USAT(17+base-vec_in[i], 5); + p_out[i] = (q15_t) __SSAT((output_base >> shift), 16); + } else + { + p_out[i] = 0; + } + } + +} + +/** + * @} end of Softmax group + */ diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c new file mode 100644 index 0000000..a4e2548 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q7.c + * Description: Q7 softmax function + * + * $Date: 20. February 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + + /** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q7(const q7_t * vec_in, const uint16_t dim_vec, q7_t * p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q15_t base; + base = -257; + + /* We first search for the maximum */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* + * So the base is set to max-8, meaning + * that we ignore really small values. + * anyway, they will be 0 after shrinking to q7_t. + */ + base = base - 8; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 20) / sum */ + int output_base = 0x100000 / sum; + + /* + * Final confidence will be output_base >> ( 13 - (vec_in[i] - base) ) + * so 128 (0x1<<7) -> 100% confidence when sum = 0x1 << 8, output_base = 0x1 << 12 + * and vec_in[i]-base = 8 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 13+base-vec_in[i] will be 5 */ + shift = (uint8_t)__USAT(13+base-vec_in[i], 5); + p_out[i] = (q7_t) __SSAT((output_base >> shift), 8); + } else { + p_out[i] = 0; + } + } +} + +/** + * @} end of Softmax group + */ diff --git a/Drivers/CMSIS/RTOS/Template/cmsis_os.h b/Drivers/CMSIS/RTOS/Template/cmsis_os.h new file mode 100644 index 0000000..30068d3 --- /dev/null +++ b/Drivers/CMSIS/RTOS/Template/cmsis_os.h @@ -0,0 +1,698 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + *---------------------------------------------------------------------------- + * + * Copyright (c) 2013-2017 ARM LIMITED + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_cb *osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_cb *osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_cb *osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_cb *osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_cb *osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value. +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter +/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +/// \return RTOS kernel system timer as 32-bit value +uint32_t osKernelSysTick (void); + +/// The RTOS kernel system timer frequency in Hz +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#define osKernelSysTickFrequency 100000000 + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) + +#endif // System Timer available + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h b/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h new file mode 100644 index 0000000..e0b602c --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h @@ -0,0 +1,756 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 18. June 2018 + * $Revision: V2.1.3 + * + * Project: CMSIS-RTOS2 API + * Title: cmsis_os2.h header file + * + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.0.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS2_H_ +#define CMSIS_OS2_H_ + +#ifndef __NO_RETURN +#if defined(__CC_ARM) +#define __NO_RETURN __declspec(noreturn) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__GNUC__) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__ICCARM__) +#define __NO_RETURN __noreturn +#else +#define __NO_RETURN +#endif +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Version information. +typedef struct { + uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec). + uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec). +} osVersion_t; + +/// Kernel state. +typedef enum { + osKernelInactive = 0, ///< Inactive. + osKernelReady = 1, ///< Ready. + osKernelRunning = 2, ///< Running. + osKernelLocked = 3, ///< Locked. + osKernelSuspended = 4, ///< Suspended. + osKernelError = -1, ///< Error. + osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization. +} osKernelState_t; + +/// Thread state. +typedef enum { + osThreadInactive = 0, ///< Inactive. + osThreadReady = 1, ///< Ready. + osThreadRunning = 2, ///< Running. + osThreadBlocked = 3, ///< Blocked. + osThreadTerminated = 4, ///< Terminated. + osThreadError = -1, ///< Error. + osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osThreadState_t; + +/// Priority values. +typedef enum { + osPriorityNone = 0, ///< No priority (not initialized). + osPriorityIdle = 1, ///< Reserved for Idle thread. + osPriorityLow = 8, ///< Priority: low + osPriorityLow1 = 8+1, ///< Priority: low + 1 + osPriorityLow2 = 8+2, ///< Priority: low + 2 + osPriorityLow3 = 8+3, ///< Priority: low + 3 + osPriorityLow4 = 8+4, ///< Priority: low + 4 + osPriorityLow5 = 8+5, ///< Priority: low + 5 + osPriorityLow6 = 8+6, ///< Priority: low + 6 + osPriorityLow7 = 8+7, ///< Priority: low + 7 + osPriorityBelowNormal = 16, ///< Priority: below normal + osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1 + osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2 + osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3 + osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4 + osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5 + osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6 + osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7 + osPriorityNormal = 24, ///< Priority: normal + osPriorityNormal1 = 24+1, ///< Priority: normal + 1 + osPriorityNormal2 = 24+2, ///< Priority: normal + 2 + osPriorityNormal3 = 24+3, ///< Priority: normal + 3 + osPriorityNormal4 = 24+4, ///< Priority: normal + 4 + osPriorityNormal5 = 24+5, ///< Priority: normal + 5 + osPriorityNormal6 = 24+6, ///< Priority: normal + 6 + osPriorityNormal7 = 24+7, ///< Priority: normal + 7 + osPriorityAboveNormal = 32, ///< Priority: above normal + osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1 + osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2 + osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3 + osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4 + osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5 + osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6 + osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7 + osPriorityHigh = 40, ///< Priority: high + osPriorityHigh1 = 40+1, ///< Priority: high + 1 + osPriorityHigh2 = 40+2, ///< Priority: high + 2 + osPriorityHigh3 = 40+3, ///< Priority: high + 3 + osPriorityHigh4 = 40+4, ///< Priority: high + 4 + osPriorityHigh5 = 40+5, ///< Priority: high + 5 + osPriorityHigh6 = 40+6, ///< Priority: high + 6 + osPriorityHigh7 = 40+7, ///< Priority: high + 7 + osPriorityRealtime = 48, ///< Priority: realtime + osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1 + osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2 + osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3 + osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4 + osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5 + osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6 + osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7 + osPriorityISR = 56, ///< Reserved for ISR deferred thread. + osPriorityError = -1, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority_t; + +/// Entry point of a thread. +typedef void (*osThreadFunc_t) (void *argument); + +/// Timer callback function. +typedef void (*osTimerFunc_t) (void *argument); + +/// Timer type. +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} osTimerType_t; + +// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). +#define osFlagsWaitAll 0x00000001U ///< Wait for all flags. +#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. + +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +#define osFlagsError 0x80000000U ///< Error indicator. +#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). +#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). +#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3). +#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). +#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). + +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode + +// Mutex attributes (attr_bits in \ref osMutexAttr_t). +#define osMutexRecursive 0x00000001U ///< Recursive mutex. +#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. +#define osMutexRobust 0x00000008U ///< Robust mutex. + +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + + +/// \details Thread ID identifies the thread. +typedef void *osThreadId_t; + +/// \details Timer ID identifies the timer. +typedef void *osTimerId_t; + +/// \details Event Flags ID identifies the event flags. +typedef void *osEventFlagsId_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +/// \details Semaphore ID identifies the semaphore. +typedef void *osSemaphoreId_t; + +/// \details Memory Pool ID identifies the memory pool. +typedef void *osMemoryPoolId_t; + +/// \details Message Queue ID identifies the message queue. +typedef void *osMessageQueueId_t; + + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + + +/// Attributes structure for thread. +typedef struct { + const char *name; ///< name of the thread + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *stack_mem; ///< memory for stack + uint32_t stack_size; ///< size of stack + osPriority_t priority; ///< initial thread priority (default: osPriorityNormal) + TZ_ModuleId_t tz_module; ///< TrustZone module identifier + uint32_t reserved; ///< reserved (must be 0) +} osThreadAttr_t; + +/// Attributes structure for timer. +typedef struct { + const char *name; ///< name of the timer + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osTimerAttr_t; + +/// Attributes structure for event flags. +typedef struct { + const char *name; ///< name of the event flags + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osEventFlagsAttr_t; + +/// Attributes structure for mutex. +typedef struct { + const char *name; ///< name of the mutex + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osMutexAttr_t; + +/// Attributes structure for semaphore. +typedef struct { + const char *name; ///< name of the semaphore + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osSemaphoreAttr_t; + +/// Attributes structure for memory pool. +typedef struct { + const char *name; ///< name of the memory pool + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mp_mem; ///< memory for data storage + uint32_t mp_size; ///< size of provided memory for data storage +} osMemoryPoolAttr_t; + +/// Attributes structure for message queue. +typedef struct { + const char *name; ///< name of the message queue + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mq_mem; ///< memory for data storage + uint32_t mq_size; ///< size of provided memory for data storage +} osMessageQueueAttr_t; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelInitialize (void); + +/// Get RTOS Kernel Information. +/// \param[out] version pointer to buffer for retrieving version information. +/// \param[out] id_buf pointer to buffer for retrieving kernel identification string. +/// \param[in] id_size size of buffer for kernel identification string. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); + +/// Get the current RTOS Kernel state. +/// \return current RTOS Kernel state. +osKernelState_t osKernelGetState (void); + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelStart (void); + +/// Lock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelLock (void); + +/// Unlock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelUnlock (void); + +/// Restore the RTOS Kernel scheduler lock state. +/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +/// \return new lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelRestoreLock (int32_t lock); + +/// Suspend the RTOS Kernel scheduler. +/// \return time in ticks, for how long the system can sleep or power-down. +uint32_t osKernelSuspend (void); + +/// Resume the RTOS Kernel scheduler. +/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode. +void osKernelResume (uint32_t sleep_ticks); + +/// Get the RTOS kernel tick count. +/// \return RTOS kernel current tick count. +uint32_t osKernelGetTickCount (void); + +/// Get the RTOS kernel tick frequency. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. +uint32_t osKernelGetTickFreq (void); + +/// Get the RTOS kernel system timer count. +/// \return RTOS kernel current system timer count as 32-bit value. +uint32_t osKernelGetSysTimerCount (void); + +/// Get the RTOS kernel system timer frequency. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. +uint32_t osKernelGetSysTimerFreq (void); + + +// ==== Thread Management Functions ==== + +/// Create a thread and add it to Active Threads. +/// \param[in] func thread function. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \param[in] attr thread attributes; NULL: default values. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); + +/// Get name of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return name as null-terminated string. +const char *osThreadGetName (osThreadId_t thread_id); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadGetId (void); + +/// Get current thread state of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current thread state of the specified thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id); + +/// Get stack size of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return stack size in bytes. +uint32_t osThreadGetStackSize (osThreadId_t thread_id); + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return remaining stack space in bytes. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id); + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current priority value of the specified thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadYield (void); + +/// Suspend execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSuspend (osThreadId_t thread_id); + +/// Resume execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadResume (osThreadId_t thread_id); + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadDetach (osThreadId_t thread_id); + +/// Wait for specified thread to terminate. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadJoin (osThreadId_t thread_id); + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void); + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadTerminate (osThreadId_t thread_id); + +/// Get number of active threads. +/// \return number of active threads. +uint32_t osThreadGetCount (void); + +/// Enumerate active threads. +/// \param[out] thread_array pointer to array for retrieving thread IDs. +/// \param[in] array_items maximum number of items in array for retrieving thread IDs. +/// \return number of enumerated threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); + + +// ==== Thread Flags Functions ==== + +/// Set the specified Thread Flags of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] flags specifies the flags of the thread that shall be set. +/// \return thread flags after setting or error code if highest bit set. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); + +/// Clear the specified Thread Flags of current running thread. +/// \param[in] flags specifies the flags of the thread that shall be cleared. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsClear (uint32_t flags); + +/// Get the current Thread Flags of current running thread. +/// \return current thread flags. +uint32_t osThreadFlagsGet (void); + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value +/// \return status code that indicates the execution status of the function. +osStatus_t osDelay (uint32_t ticks); + +/// Wait until specified time. +/// \param[in] ticks absolute time in ticks +/// \return status code that indicates the execution status of the function. +osStatus_t osDelayUntil (uint32_t ticks); + + +// ==== Timer Management Functions ==== + +/// Create and Initialize a timer. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. +/// \param[in] attr timer attributes; NULL: default values. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); + +/// Get name of a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return name as null-terminated string. +const char *osTimerGetName (osTimerId_t timer_id); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks); + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStop (osTimerId_t timer_id); + +/// Check if a timer is running. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return 0 not running, 1 running. +uint32_t osTimerIsRunning (osTimerId_t timer_id); + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerDelete (osTimerId_t timer_id); + + +// ==== Event Flags Management Functions ==== + +/// Create and Initialize an Event Flags object. +/// \param[in] attr event flags attributes; NULL: default values. +/// \return event flags ID for reference by other functions or NULL in case of error. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); + +/// Get name of an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return name as null-terminated string. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id); + +/// Set the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be set. +/// \return event flags after setting or error code if highest bit set. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); + +/// Clear the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be cleared. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); + +/// Get the current Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return current event flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id); + +/// Wait for one or more Event Flags to become signaled. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); + +/// Delete an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id); + + +// ==== Mutex Management Functions ==== + +/// Create and Initialize a Mutex object. +/// \param[in] attr mutex attributes; NULL: default values. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId_t osMutexNew (const osMutexAttr_t *attr); + +/// Get name of a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return name as null-terminated string. +const char *osMutexGetName (osMutexId_t mutex_id); + +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease (osMutexId_t mutex_id); + +/// Get Thread which owns a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return thread ID of owner thread or NULL when mutex was not acquired. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id); + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexDelete (osMutexId_t mutex_id); + + +// ==== Semaphore Management Functions ==== + +/// Create and Initialize a Semaphore object. +/// \param[in] max_count maximum number of available tokens. +/// \param[in] initial_count initial number of available tokens. +/// \param[in] attr semaphore attributes; NULL: default values. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); + +/// Get name of a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return name as null-terminated string. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); + +/// Release a Semaphore token up to the initial maximum count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); + +/// Get current Semaphore token count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return number of tokens available. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id); + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id); + + +// ==== Memory Pool Management Functions ==== + +/// Create and Initialize a Memory Pool object. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size memory block size in bytes. +/// \param[in] attr memory pool attributes; NULL: default values. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); + +/// Get name of a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return name as null-terminated string. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); + +/// Get maximum number of memory blocks in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return maximum number of memory blocks. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); + +/// Get memory block size in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return memory block size in bytes. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks used in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks used. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks available in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks available. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id); + +/// Delete a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id); + + +// ==== Message Queue Management Functions ==== + +/// Create and Initialize a Message Queue object. +/// \param[in] msg_count maximum number of messages in queue. +/// \param[in] msg_size maximum message size in bytes. +/// \param[in] attr message queue attributes; NULL: default values. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); + +/// Get name of a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return name as null-terminated string. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id); + +/// Put a Message into a Queue or timeout if Queue is full. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[in] msg_ptr pointer to buffer with message to put into a queue. +/// \param[in] msg_prio message priority. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[out] msg_ptr pointer to buffer for message to get from a queue. +/// \param[out] msg_prio pointer to buffer for message priority or NULL. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); + +/// Get maximum number of messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum number of messages. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id); + +/// Get maximum message size in a Memory Pool. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum message size in bytes. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id); + +/// Get number of queued messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of queued messages. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id); + +/// Get number of available slots for messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of available slots for messages. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id); + +/// Reset a Message Queue to initial empty state. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id); + +/// Delete a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS2_H_ diff --git a/Drivers/CMSIS/RTOS2/Include/os_tick.h b/Drivers/CMSIS/RTOS2/Include/os_tick.h new file mode 100644 index 0000000..8f7cdf6 --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Include/os_tick.h @@ -0,0 +1,71 @@ +/**************************************************************************//** + * @file os_tick.h + * @brief CMSIS OS Tick header file + * @version V1.0.1 + * @date 24. November 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef OS_TICK_H +#define OS_TICK_H + +#include + +/// IRQ Handler. +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +typedef void (*IRQHandler_t) (void); +#endif + +/// Setup OS Tick timer to generate periodic RTOS Kernel Ticks +/// \param[in] freq tick frequency in Hz +/// \param[in] handler tick IRQ handler +/// \return 0 on success, -1 on error. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler); + +/// Enable OS Tick timer interrupt +void OS_Tick_Enable (void); + +/// Disable OS Tick timer interrupt +void OS_Tick_Disable (void); + +/// Acknowledge execution of OS Tick timer interrupt +void OS_Tick_AcknowledgeIRQ (void); + +/// Get OS Tick timer IRQ number +/// \return OS Tick IRQ number +int32_t OS_Tick_GetIRQn (void); + +/// Get OS Tick timer clock frequency +/// \return OS Tick timer clock frequency in Hz +uint32_t OS_Tick_GetClock (void); + +/// Get OS Tick timer interval reload value +/// \return OS Tick timer interval reload value +uint32_t OS_Tick_GetInterval (void); + +/// Get OS Tick timer counter value +/// \return OS Tick timer counter value +uint32_t OS_Tick_GetCount (void); + +/// Get OS Tick timer overflow status +/// \return OS Tick overflow status (1 - overflow, 0 - no overflow). +uint32_t OS_Tick_GetOverflow (void); + +#endif /* OS_TICK_H */ diff --git a/Drivers/CMSIS/RTOS2/Source/os_systick.c b/Drivers/CMSIS/RTOS2/Source/os_systick.c new file mode 100644 index 0000000..985a9d9 --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Source/os_systick.c @@ -0,0 +1,132 @@ +/**************************************************************************//** + * @file os_systick.c + * @brief CMSIS OS Tick SysTick implementation + * @version V1.0.1 + * @date 24. November 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" + +//lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer" +#include "RTE_Components.h" +#include CMSIS_device_header + +#ifdef SysTick + +#ifndef SYSTICK_IRQ_PRIORITY +#define SYSTICK_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PendST; + +// Setup OS Tick. +__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + (void)handler; + + if (freq == 0U) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + load = (SystemCoreClock / freq) - 1U; + if (load > 0x00FFFFFFU) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + // Set SysTick Interrupt Priority +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__CORTEX_M) && (__CORTEX_M == 7U))) + SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0))) + SCB->SHP[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) + SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#else +#error "Unknown ARM Core!" +#endif + + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk; + SysTick->LOAD = load; + SysTick->VAL = 0U; + + PendST = 0U; + + return (0); +} + +/// Enable OS Tick. +__WEAK void OS_Tick_Enable (void) { + + if (PendST != 0U) { + PendST = 0U; + SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; + } + + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +/// Disable OS Tick. +__WEAK void OS_Tick_Disable (void) { + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) { + SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + PendST = 1U; + } +} + +// Acknowledge OS Tick IRQ. +__WEAK void OS_Tick_AcknowledgeIRQ (void) { + (void)SysTick->CTRL; +} + +// Get OS Tick IRQ number. +__WEAK int32_t OS_Tick_GetIRQn (void) { + return ((int32_t)SysTick_IRQn); +} + +// Get OS Tick clock. +__WEAK uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +__WEAK uint32_t OS_Tick_GetInterval (void) { + return (SysTick->LOAD + 1U); +} + +// Get OS Tick count value. +__WEAK uint32_t OS_Tick_GetCount (void) { + uint32_t load = SysTick->LOAD; + return (load - SysTick->VAL); +} + +// Get OS Tick overflow status. +__WEAK uint32_t OS_Tick_GetOverflow (void) { + return ((SysTick->CTRL >> 16) & 1U); +} + +#endif // SysTick diff --git a/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c b/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c new file mode 100644 index 0000000..22cfa93 --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c @@ -0,0 +1,187 @@ +/**************************************************************************//** + * @file os_tick_gtim.c + * @brief CMSIS OS Tick implementation for Generic Timer + * @version V1.0.1 + * @date 24. November 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" +#include "irq_ctrl.h" + +#include "RTE_Components.h" +#include CMSIS_device_header + +#ifndef GTIM_IRQ_PRIORITY +#define GTIM_IRQ_PRIORITY 0xFFU +#endif + +#ifndef GTIM_IRQ_NUM +#define GTIM_IRQ_NUM SecurePhyTimer_IRQn +#endif + +// Timer interrupt pending flag +static uint8_t GTIM_PendIRQ; + +// Timer tick frequency +static uint32_t GTIM_Clock; + +// Timer load value +static uint32_t GTIM_Load; + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t prio, bits; + + if (freq == 0U) { + return (-1); + } + + GTIM_PendIRQ = 0U; + + // Get timer clock +#ifdef SCTR_BASE + GTIM_Clock = *(uint32_t*)(SCTR_BASE+0x20); +#else + // FVP REFCLK CNTControl 100MHz + GTIM_Clock = 100000000UL; +#endif + + PL1_SetCounterFrequency(GTIM_Clock); + + // Calculate load value + GTIM_Load = (GTIM_Clock / freq) - 1U; + + // Disable Generic Timer and set load value + PL1_SetControl(0U); + PL1_SetLoadValue(GTIM_Load); + + // Disable corresponding IRQ + IRQ_Disable(GTIM_IRQ_NUM); + IRQ_ClearPending(GTIM_IRQ_NUM); + + // Determine number of implemented priority bits + IRQ_SetPriority(GTIM_IRQ_NUM, 0xFFU); + + prio = IRQ_GetPriority(GTIM_IRQ_NUM); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (GTIM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set Private Timer interrupt priority + IRQ_SetPriority(GTIM_IRQ_NUM, prio-1U); + + // Set edge-triggered IRQ + IRQ_SetMode(GTIM_IRQ_NUM, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(GTIM_IRQ_NUM, handler); + + // Enable corresponding interrupt + IRQ_Enable(GTIM_IRQ_NUM); + + // Enable system counter and timer control +#ifdef SCTR_BASE + *(uint32_t*)SCTR_BASE |= 3U; +#endif + + // Enable timer control + PL1_SetControl(1U); + + return (0); +} + +/// Enable OS Tick. +void OS_Tick_Enable (void) { + uint32_t ctrl; + + // Set pending interrupt if flag set + if (GTIM_PendIRQ != 0U) { + GTIM_PendIRQ = 0U; + IRQ_SetPending (GTIM_IRQ_NUM); + } + + // Start the Private Timer + ctrl = PL1_GetControl(); + // Set bit: Timer enable + ctrl |= 1U; + PL1_SetControl(ctrl); +} + +/// Disable OS Tick. +void OS_Tick_Disable (void) { + uint32_t ctrl; + + // Stop the Private Timer + ctrl = PL1_GetControl(); + // Clear bit: Timer enable + ctrl &= ~1U; + PL1_SetControl(ctrl); + + // Remember pending interrupt flag + if (IRQ_GetPending(GTIM_IRQ_NUM) != 0) { + IRQ_ClearPending(GTIM_IRQ_NUM); + GTIM_PendIRQ = 1U; + } +} + +// Acknowledge OS Tick IRQ. +void OS_Tick_AcknowledgeIRQ (void) { + IRQ_ClearPending (GTIM_IRQ_NUM); + PL1_SetLoadValue(GTIM_Load); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (GTIM_IRQ_NUM); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (GTIM_Clock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (GTIM_Load + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + return (GTIM_Load - PL1_GetCurrentValue()); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + CNTP_CTL_Type cntp_ctl; + cntp_ctl.w = PL1_GetControl(); + return (cntp_ctl.b.ISTATUS); +} diff --git a/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c b/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c new file mode 100644 index 0000000..e75ac3a --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c @@ -0,0 +1,165 @@ +/**************************************************************************//** + * @file os_tick_ptim.c + * @brief CMSIS OS Tick implementation for Private Timer + * @version V1.0.2 + * @date 02. March 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header + +#if defined(PTIM) + +#include "os_tick.h" +#include "irq_ctrl.h" + +#ifndef PTIM_IRQ_PRIORITY +#define PTIM_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PTIM_PendIRQ; // Timer interrupt pending flag + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + uint32_t prio; + uint32_t bits; + + if (freq == 0U) { + return (-1); + } + + PTIM_PendIRQ = 0U; + + // Private Timer runs with the system frequency + load = (SystemCoreClock / freq) - 1U; + + // Disable Private Timer and set load value + PTIM_SetControl (0U); + PTIM_SetLoadValue (load); + + // Disable corresponding IRQ + IRQ_Disable (PrivTimer_IRQn); + IRQ_ClearPending(PrivTimer_IRQn); + + // Determine number of implemented priority bits + IRQ_SetPriority (PrivTimer_IRQn, 0xFFU); + + prio = IRQ_GetPriority (PrivTimer_IRQn); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (PTIM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set Private Timer interrupt priority + IRQ_SetPriority(PrivTimer_IRQn, prio-1U); + + // Set edge-triggered IRQ + IRQ_SetMode(PrivTimer_IRQn, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(PrivTimer_IRQn, handler); + + // Enable corresponding interrupt + IRQ_Enable (PrivTimer_IRQn); + + // Set bits: IRQ enable and Auto reload + PTIM_SetControl (0x06U); + + return (0); +} + +/// Enable OS Tick. +void OS_Tick_Enable (void) { + uint32_t ctrl; + + // Set pending interrupt if flag set + if (PTIM_PendIRQ != 0U) { + PTIM_PendIRQ = 0U; + IRQ_SetPending (PrivTimer_IRQn); + } + + // Start the Private Timer + ctrl = PTIM_GetControl(); + // Set bit: Timer enable + ctrl |= 1U; + PTIM_SetControl (ctrl); +} + +/// Disable OS Tick. +void OS_Tick_Disable (void) { + uint32_t ctrl; + + // Stop the Private Timer + ctrl = PTIM_GetControl(); + // Clear bit: Timer enable + ctrl &= ~1U; + PTIM_SetControl (ctrl); + + // Remember pending interrupt flag + if (IRQ_GetPending(PrivTimer_IRQn) != 0) { + IRQ_ClearPending (PrivTimer_IRQn); + PTIM_PendIRQ = 1U; + } +} + +// Acknowledge OS Tick IRQ. +void OS_Tick_AcknowledgeIRQ (void) { + PTIM_ClearEventFlag(); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (PrivTimer_IRQn); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (PTIM_GetLoadValue() + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + uint32_t load = PTIM_GetLoadValue(); + return (load - PTIM_GetCurrentValue()); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + return (PTIM->ISR & 1); +} + +#endif // PTIM diff --git a/Drivers/CMSIS/RTOS2/Template/cmsis_os.h b/Drivers/CMSIS/RTOS2/Template/cmsis_os.h new file mode 100644 index 0000000..376dbf7 --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Template/cmsis_os.h @@ -0,0 +1,922 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 18. June 2018 + * $Revision: V2.1.3 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedefs + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * Version 2.0.0 + * OS objects creation without macros (dynamic creation and resource allocation): + * - added: osXxxxNew functions which replace osXxxxCreate + * - added: osXxxxAttr_t structures + * - deprecated: osXxxxCreate functions, osXxxxDef_t structures + * - deprecated: osXxxxDef and osXxxx macros + * osStatus codes simplified and renamed to osStatus_t + * osEvent return structure deprecated + * Kernel: + * - added: osKernelInfo_t and osKernelGetInfo + * - added: osKernelState_t and osKernelGetState (replaces osKernelRunning) + * - added: osKernelLock, osKernelUnlock + * - added: osKernelSuspend, osKernelResume + * - added: osKernelGetTickCount, osKernelGetTickFreq + * - renamed osKernelSysTick to osKernelGetSysTimerCount + * - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq + * - deprecated osKernelSysTickMicroSec + * Thread: + * - extended number of thread priorities + * - renamed osPrioriry to osPrioriry_t + * - replaced osThreadCreate with osThreadNew + * - added: osThreadGetName + * - added: osThreadState_t and osThreadGetState + * - added: osThreadGetStackSize, osThreadGetStackSpace + * - added: osThreadSuspend, osThreadResume + * - added: osThreadJoin, osThreadDetach, osThreadExit + * - added: osThreadGetCount, osThreadEnumerate + * - added: Thread Flags (moved from Signals) + * Signals: + * - renamed osSignals to osThreadFlags (moved to Thread Flags) + * - changed return value of Set/Clear/Wait functions + * - Clear function limited to current running thread + * - extended Wait function (options) + * - added: osThreadFlagsGet + * Event Flags: + * - added new independent object for handling Event Flags + * Delay and Wait functions: + * - added: osDelayUntil + * - deprecated: osWait + * Timer: + * - replaced osTimerCreate with osTimerNew + * - added: osTimerGetName, osTimerIsRunning + * Mutex: + * - extended: attributes (Recursive, Priority Inherit, Robust) + * - replaced osMutexCreate with osMutexNew + * - renamed osMutexWait to osMutexAcquire + * - added: osMutexGetName, osMutexGetOwner + * Semaphore: + * - extended: maximum and initial token count + * - replaced osSemaphoreCreate with osSemaphoreNew + * - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value) + * - added: osSemaphoreGetName, osSemaphoreGetCount + * Memory Pool: + * - using osMemoryPool prefix instead of osPool + * - replaced osPoolCreate with osMemoryPoolNew + * - extended osMemoryPoolAlloc (timeout) + * - added: osMemoryPoolGetName + * - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize + * - added: osMemoryPoolGetCount, osMemoryPoolGetSpace + * - added: osMemoryPoolDelete + * - deprecated: osPoolCAlloc + * Message Queue: + * - extended: fixed size message instead of a single 32-bit value + * - using osMessageQueue prefix instead of osMessage + * - replaced osMessageCreate with osMessageQueueNew + * - updated: osMessageQueuePut, osMessageQueueGet + * - added: osMessageQueueGetName + * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize + * - added: osMessageQueueGetCount, osMessageQueueGetSpace + * - added: osMessageQueueReset, osMessageQueueDelete + * Mail Queue: + * - deprecated (superseded by extended Message Queue functionality) + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS_H_ +#define CMSIS_OS_H_ + +/// \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000U ///< RTOS identification and version (main[31:16].sub[15:0]) + +/// \note CAN BE CHANGED: \b osKernelSystemId identifies the underlying RTOS kernel. +#define osKernelSystemId "KERNEL V1.0" ///< RTOS identification string + +/// \note CAN BE CHANGED: \b osFeature_xxx identifies RTOS features. +#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Signals 16U ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available + +#if (osCMSIS >= 0x20000U) +#include "cmsis_os2.h" +#else +#include +#include +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Priority values. +#if (osCMSIS < 0x20000U) +typedef enum { + osPriorityIdle = -3, ///< Priority: idle (lowest) + osPriorityLow = -2, ///< Priority: low + osPriorityBelowNormal = -1, ///< Priority: below normal + osPriorityNormal = 0, ///< Priority: normal (default) + osPriorityAboveNormal = +1, ///< Priority: above normal + osPriorityHigh = +2, ///< Priority: high + osPriorityRealtime = +3, ///< Priority: realtime (highest) + osPriorityError = 0x84, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority; +#else +#define osPriority osPriority_t +#endif + +/// Entry point of a thread. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +typedef void (*os_ptimer) (void const *argument); + +/// Timer type. +#if (osCMSIS < 0x20000U) +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} os_timer_type; +#else +#define os_timer_type osTimerType_t +#endif + +/// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +/// Status code values returned by CMSIS-RTOS functions. +#if (osCMSIS < 0x20000U) +typedef enum { + osOK = 0, ///< Function completed; no error or event occurred. + osEventSignal = 0x08, ///< Function completed; signal event occurred. + osEventMessage = 0x10, ///< Function completed; message event occurred. + osEventMail = 0x20, ///< Function completed; mail event occurred. + osEventTimeout = 0x40, ///< Function completed; timeout occurred. + osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< Resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< Value of a parameter is out of range. + osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus; +#else +typedef int32_t osStatus; +#define osEventSignal (0x08) +#define osEventMessage (0x10) +#define osEventMail (0x20) +#define osEventTimeout (0x40) +#define osErrorOS osError +#define osErrorTimeoutResource osErrorTimeout +#define osErrorISRRecursive (-126) +#define osErrorValue (-127) +#define osErrorPriority (-128) +#endif + + +// >>> the following data type definitions may be adapted towards a specific RTOS + +/// Thread ID identifies the thread. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osThreadId; +#else +#define osThreadId osThreadId_t +#endif + +/// Timer ID identifies the timer. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osTimerId; +#else +#define osTimerId osTimerId_t +#endif + +/// Mutex ID identifies the mutex. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osMutexId; +#else +#define osMutexId osMutexId_t +#endif + +/// Semaphore ID identifies the semaphore. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osSemaphoreId; +#else +#define osSemaphoreId osSemaphoreId_t +#endif + +/// Pool ID identifies the memory pool. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osPoolId; + +/// Message ID identifies the message queue. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osMessageQId; + +/// Mail ID identifies the mail queue. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; +#else +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osThreadAttr_t attr; ///< thread attributes +} osThreadDef_t; +#endif + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; +#else +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function + osTimerAttr_t attr; ///< timer attributes +} osTimerDef_t; +#endif + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value +} osMutexDef_t; +#else +#define osMutexDef_t osMutexAttr_t +#endif + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value +} osSemaphoreDef_t; +#else +#define osSemaphoreDef_t osSemaphoreAttr_t +#endif + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; +#else +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + osMemoryPoolAttr_t attr; ///< memory pool attributes +} osPoolDef_t; +#endif + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + void *pool; ///< memory array for messages +} osMessageQDef_t; +#else +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + osMessageQueueAttr_t attr; ///< message queue attributes +} osMessageQDef_t; +#endif + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; +#else +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *mail; ///< pointer to mail + osMemoryPoolAttr_t mp_attr; ///< memory pool attributes + osMessageQueueAttr_t mq_attr; ///< message queue attributes +} osMailQDef_t; +#endif + + +/// Event structure contains detailed information about an event. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelInitialize (void); +#endif + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelStart (void); +#endif + +/// Check if the RTOS kernel is already started. +/// \return 0 RTOS is not started, 1 RTOS is started. +#if (osCMSIS < 0x20000U) +int32_t osKernelRunning(void); +#endif + +#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter. +/// \return RTOS kernel system timer as 32-bit value +#if (osCMSIS < 0x20000U) +uint32_t osKernelSysTick (void); +#else +#define osKernelSysTick osKernelGetSysTimerCount +#endif + +/// The RTOS kernel system timer frequency in Hz. +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#if (osCMSIS < 0x20000U) +#define osKernelSysTickFrequency 100000000 +#endif + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#if (osCMSIS < 0x20000U) +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) +#else +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000) +#endif + +#endif // System Timer available + + +// ==== Thread Management Functions ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#else +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), \ + { NULL, osThreadDetached, NULL, 0U, NULL, 8*((stacksz+7)/8), (priority), 0U, 0U } } +#endif +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +#if (osCMSIS < 0x20000U) +osThreadId osThreadGetId (void); +#endif + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); +#endif + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the specified thread. +#if (osCMSIS < 0x20000U) +osPriority osThreadGetPriority (osThreadId thread_id); +#endif + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadYield (void); +#endif + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadTerminate (osThreadId thread_id); +#endif + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osDelay (uint32_t millisec); +#endif + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== + +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = { (function) } +#else +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), { NULL, 0U, NULL, 0U } } +#endif +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create and Initialize a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); +#endif + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStop (osTimerId timer_id); +#endif + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerDelete (osTimerId timer_id); +#endif + + +// ==== Mutex Management Functions ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } +#else +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = \ +{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, NULL, 0U } +#endif +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); +#else +#define osMutexWait osMutexAcquire +#endif + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexRelease (osMutexId mutex_id); +#endif + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexDelete (osMutexId mutex_id); +#endif + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#else +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = \ +{ NULL, 0U, NULL, 0U } +#endif +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count maximum and initial number of available tokens. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); +#endif + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); +#endif + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#else +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a Memory Pool object. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a Memory Pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool available + + +// ==== Message Queue Management Functions ==== + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), NULL } +#else +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue object. +/// \param[in] queue_def message queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queue available + + +// ==== Mail Queue Management Functions ==== + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of mails in the queue. +/// \param type data type of a single mail element. +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), NULL } +#else +#define osMailQDef(name, queue_sz, type) \ +static void *os_mail_p_##name[2]; \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), (&os_mail_p_##name), \ + { NULL, 0U, NULL, 0U, NULL, 0U }, \ + { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize a Mail Queue object. +/// \param[in] queue_def mail queue definition referenced with \ref osMailQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block for mail from a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block for mail from a mail memory pool and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a Mail into a Queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory with mail to put into a queue. +/// \return status code that indicates the execution status of the function. +osStatus osMailPut (osMailQId queue_id, const void *mail); + +/// Get a Mail from a Queue or timeout if Queue is empty. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block by returning it to a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queue available + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS_H_ diff --git a/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c b/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c new file mode 100644 index 0000000..de1650c --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 10. January 2017 + * $Revision: V1.2 + * + * Project: CMSIS-RTOS API V1 + * Title: cmsis_os_v1.c V1 module file + *---------------------------------------------------------------------------*/ + +#include +#include "cmsis_os.h" + +#if (osCMSIS >= 0x20000U) + + +// Thread +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) { + + if (thread_def == NULL) { + return (osThreadId)NULL; + } + return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr); +} + + +// Signals + +#define SignalMask ((1U< 0U) && (flags < 0x80000000U)) { + event.status = osEventSignal; + event.value.signals = (int32_t)flags; + } else { + switch ((int32_t)flags) { + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + case osErrorParameter: + event.status = osErrorValue; + break; + default: + event.status = (osStatus)flags; + break; + } + } + return event; +} + + +// Timer +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) { + + if (timer_def == NULL) { + return (osTimerId)NULL; + } + return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr); +} + + +// Mutex +osMutexId osMutexCreate (const osMutexDef_t *mutex_def) { + + if (mutex_def == NULL) { + return (osMutexId)NULL; + } + return osMutexNew(mutex_def); +} + + +// Semaphore + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) + +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) { + + if (semaphore_def == NULL) { + return (osSemaphoreId)NULL; + } + return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def); +} + +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { + osStatus_t status; + uint32_t count; + + status = osSemaphoreAcquire(semaphore_id, millisec); + switch (status) { + case osOK: + count = osSemaphoreGetCount(semaphore_id); + return ((int32_t)count + 1); + case osErrorResource: + case osErrorTimeout: + return 0; + default: + break; + } + return -1; +} + +#endif // Semaphore + + +// Memory Pool + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) + +osPoolId osPoolCreate (const osPoolDef_t *pool_def) { + + if (pool_def == NULL) { + return (osPoolId)NULL; + } + return ((osPoolId)(osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr))); +} + +void *osPoolAlloc (osPoolId pool_id) { + return osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U); +} + +void *osPoolCAlloc (osPoolId pool_id) { + void *block; + uint32_t block_size; + + block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id); + if (block_size == 0U) { + return NULL; + } + block = osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U); + if (block != NULL) { + memset(block, 0, block_size); + } + return block; +} + +osStatus osPoolFree (osPoolId pool_id, void *block) { + return osMemoryPoolFree((osMemoryPoolId_t)pool_id, block); +} + +#endif // Memory Pool + + +// Message Queue + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) + +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { + (void)thread_id; + + if (queue_def == NULL) { + return (osMessageQId)NULL; + } + return ((osMessageQId)(osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr))); +} + +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { + return osMessageQueuePut((osMessageQueueId_t)queue_id, &info, 0U, millisec); +} + +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) { + osStatus_t status; + osEvent event; + uint32_t message; + + status = osMessageQueueGet((osMessageQueueId_t)queue_id, &message, NULL, millisec); + switch (status) { + case osOK: + event.status = osEventMessage; + event.value.v = message; + break; + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + default: + event.status = status; + break; + } + return event; +} + +#endif // Message Queue + + +// Mail Queue + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) + +typedef struct os_mail_queue_s { + osMemoryPoolId_t mp_id; + osMessageQueueId_t mq_id; +} os_mail_queue_t; + +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) { + os_mail_queue_t *ptr; + (void)thread_id; + + if (queue_def == NULL) { + return (osMailQId)NULL; + } + + ptr = queue_def->mail; + if (ptr == NULL) { + return (osMailQId)NULL; + } + + ptr->mp_id = osMemoryPoolNew (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr); + ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr); + if ((ptr->mp_id == (osMemoryPoolId_t)NULL) || (ptr->mq_id == (osMessageQueueId_t)NULL)) { + if (ptr->mp_id != (osMemoryPoolId_t)NULL) { + osMemoryPoolDelete(ptr->mp_id); + } + if (ptr->mq_id != (osMessageQueueId_t)NULL) { + osMessageQueueDelete(ptr->mq_id); + } + return (osMailQId)NULL; + } + + return (osMailQId)ptr; +} + +void *osMailAlloc (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return NULL; + } + return osMemoryPoolAlloc(ptr->mp_id, millisec); +} + +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + void *block; + uint32_t block_size; + + if (ptr == NULL) { + return NULL; + } + block_size = osMemoryPoolGetBlockSize(ptr->mp_id); + if (block_size == 0U) { + return NULL; + } + block = osMemoryPoolAlloc(ptr->mp_id, millisec); + if (block != NULL) { + memset(block, 0, block_size); + } + + return block; + +} + +osStatus osMailPut (osMailQId queue_id, const void *mail) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return osErrorParameter; + } + if (mail == NULL) { + return osErrorValue; + } + return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U); +} + +osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + osStatus_t status; + osEvent event; + void *mail; + + if (ptr == NULL) { + event.status = osErrorParameter; + return event; + } + + status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec); + switch (status) { + case osOK: + event.status = osEventMail; + event.value.p = mail; + break; + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + default: + event.status = status; + break; + } + return event; +} + +osStatus osMailFree (osMailQId queue_id, void *mail) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return osErrorParameter; + } + if (mail == NULL) { + return osErrorValue; + } + return osMemoryPoolFree(ptr->mp_id, mail); +} + +#endif // Mail Queue + + +#endif // osCMSIS diff --git a/Drivers/CMSIS/docs/General/html/LICENSE.txt b/Drivers/CMSIS/docs/General/html/LICENSE.txt new file mode 100644 index 0000000..8dada3e --- /dev/null +++ b/Drivers/CMSIS/docs/General/html/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 0000000..996abd9 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4417 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +#define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) +#endif /* STM32F3 */ + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h new file mode 100644 index 0000000..2e05881 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h @@ -0,0 +1,1191 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_H +#define STM32H7xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_conf.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ +/** @defgroup REV_ID device revision ID + * @{ + */ +#define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */ +#define REV_ID_Z ((uint32_t)0x1001) /*!< STM32H7 rev.Z */ +#define REV_ID_A ((uint32_t)0x1000) /*!< STM32H7 rev.A */ +#define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */ +#if (STM32H7_DEV_ID == 0x450UL) +#define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */ +#else +#define REV_ID_X ((uint32_t)0x1007) /*!< STM32H7 rev.X */ +#endif /* STM32H7_DEV_ID */ +#define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */ + + +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) + + +/** + * @} + */ + +/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ + +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) + +/** + * @} + */ + +#if !defined(SYSCFG_PMCR_BOOSTEN) +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ + +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) + +/** + * @} + */ +#endif /* ! SYSCFG_PMCR_BOOSTEN */ + + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) || defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +/** @defgroup SYSCFG_Adc2_Alternate_Connection SYSCFG ADC2 Alternate Connection + * @{ + */ + +/** @brief Adc2 Alternate Connection on Vinp[16] and Vinp[17] + */ +#define SYSCFG_ADC2_ROUT0_DAC1_1 ((uint32_t)0x00000000) /*!< DAC1_out1 connected to ADC2 VINP[16] */ +#define SYSCFG_ADC2_ROUT0_VBAT4 SYSCFG_ADC2ALT_ADC2_ROUT0 /*!< VBAT/4 connected to ADC2 VINP[16] */ +#define SYSCFG_ADC2_ROUT1_DAC1_2 ((uint32_t)0x00000000) /*!< DAC1_out2 connected to ADC2 VINP[17] */ +#define SYSCFG_ADC2_ROUT1_VREFINT SYSCFG_ADC2ALT_ADC2_ROUT1 /*!< VREFINT connected to ADC2 VINP[17] */ + +#define IS_SYSCFG_ADC2ALT_ROUT0(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT0_DAC1_1) || \ + ((__VALUE__) == SYSCFG_ADC2_ROUT0_VBAT4)) +#define IS_SYSCFG_ADC2ALT_ROUT1(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT1_DAC1_2) || \ + ((__VALUE__) == SYSCFG_ADC2_ROUT1_VREFINT)) + +/** + * @} + */ +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0 || SYSCFG_ADC2ALT_ADC2_ROUT1*/ + + +/** @defgroup SYSCFG_Ethernet_Config Ethernet Config + * @{ + */ +#define SYSCFG_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface */ +#define SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< Select the Reduced Media Independent Interface */ + +#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \ + ((CONFIG) == SYSCFG_ETH_RMII)) + +/** + * @} + */ + + +/** @defgroup SYSCFG_Analog_Switch_Config Analog Switch Config + * @{ + */ +#define SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< Select PA0 analog switch */ +#define SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< Select PA1 analog switch */ +#define SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< Select PC2 analog switch */ +#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< Select PC3 analog switch */ + + + + +#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO /*!< PA0 analog switch opened */ +#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */ +#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO /*!< PA1 analog switch opened */ +#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/ +#define SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO /*!< PC2 analog switch opened */ +#define SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000) /*!< PC2 analog switch closed */ +#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO /*!< PC3 analog switch opened */ +#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) /*!< PC3 analog switch closed */ + +/** + * @} + */ + +#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \ + (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \ + (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \ + (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3)) + + +#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \ + (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE) || \ + (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || \ + (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE)) + + +/** @defgroup SYSCFG_Boot_Config Boot Config + * @{ + */ +#define SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000) /*!< Select Boot address0 */ +#define SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001) /*!< Select Boot address1 */ + +#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \ + ((REGISTER) == SYSCFG_BOOT_ADDR1)) + +#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE) + +/** + * @} + */ + + +/** @defgroup SYSCFG_IOCompenstionCell_Config IOCompenstionCell Config + * @{ + */ +#define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ +#define SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS /*!< Code from the SYSCFG compensation cell code register */ + +#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \ + ((SELECT) == SYSCFG_REGISTER_CODE)) + +#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL)) + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup EXTI_Event_Input_Config Event Input Config + * @{ + */ + +#define EXTI_MODE_IT ((uint32_t)0x00010000) +#define EXTI_MODE_EVT ((uint32_t)0x00020000) +#define EXTI_RISING_EDGE ((uint32_t)0x00100000) +#define EXTI_FALLING_EDGE ((uint32_t)0x00200000) + +#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE)) +#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT)) + +#define EXTI_LINE0 ((uint32_t)0x00) /*!< External interrupt LINE 0 */ +#define EXTI_LINE1 ((uint32_t)0x01) /*!< External interrupt LINE 1 */ +#define EXTI_LINE2 ((uint32_t)0x02) /*!< External interrupt LINE 2 */ +#define EXTI_LINE3 ((uint32_t)0x03) /*!< External interrupt LINE 3 */ +#define EXTI_LINE4 ((uint32_t)0x04) /*!< External interrupt LINE 4 */ +#define EXTI_LINE5 ((uint32_t)0x05) /*!< External interrupt LINE 5 */ +#define EXTI_LINE6 ((uint32_t)0x06) /*!< External interrupt LINE 6 */ +#define EXTI_LINE7 ((uint32_t)0x07) /*!< External interrupt LINE 7 */ +#define EXTI_LINE8 ((uint32_t)0x08) /*!< External interrupt LINE 8 */ +#define EXTI_LINE9 ((uint32_t)0x09) /*!< External interrupt LINE 9 */ +#define EXTI_LINE10 ((uint32_t)0x0A) /*!< External interrupt LINE 10 */ +#define EXTI_LINE11 ((uint32_t)0x0B) /*!< External interrupt LINE 11 */ +#define EXTI_LINE12 ((uint32_t)0x0C) /*!< External interrupt LINE 12 */ +#define EXTI_LINE13 ((uint32_t)0x0D) /*!< External interrupt LINE 13 */ +#define EXTI_LINE14 ((uint32_t)0x0E) /*!< External interrupt LINE 14 */ +#define EXTI_LINE15 ((uint32_t)0x0F) /*!< External interrupt LINE 15 */ +#define EXTI_LINE16 ((uint32_t)0x10) +#define EXTI_LINE17 ((uint32_t)0x11) +#define EXTI_LINE18 ((uint32_t)0x12) +#define EXTI_LINE19 ((uint32_t)0x13) +#define EXTI_LINE20 ((uint32_t)0x14) +#define EXTI_LINE21 ((uint32_t)0x15) +#define EXTI_LINE22 ((uint32_t)0x16) +#define EXTI_LINE23 ((uint32_t)0x17) +#define EXTI_LINE24 ((uint32_t)0x18) +#define EXTI_LINE25 ((uint32_t)0x19) +#define EXTI_LINE26 ((uint32_t)0x1A) +#define EXTI_LINE27 ((uint32_t)0x1B) +#define EXTI_LINE28 ((uint32_t)0x1C) +#define EXTI_LINE29 ((uint32_t)0x1D) +#define EXTI_LINE30 ((uint32_t)0x1E) +#define EXTI_LINE31 ((uint32_t)0x1F) +#define EXTI_LINE32 ((uint32_t)0x20) +#define EXTI_LINE33 ((uint32_t)0x21) +#define EXTI_LINE34 ((uint32_t)0x22) +#define EXTI_LINE35 ((uint32_t)0x23) +#define EXTI_LINE36 ((uint32_t)0x24) +#define EXTI_LINE37 ((uint32_t)0x25) +#define EXTI_LINE38 ((uint32_t)0x26) +#define EXTI_LINE39 ((uint32_t)0x27) + +#define EXTI_LINE40 ((uint32_t)0x28) +#define EXTI_LINE41 ((uint32_t)0x29) +#define EXTI_LINE42 ((uint32_t)0x2A) +#define EXTI_LINE43 ((uint32_t)0x2B) +#define EXTI_LINE44 ((uint32_t)0x2C) /* Not available in all family lines */ +/* EXTI_LINE45 Reserved */ +#if defined(DUAL_CORE) +#define EXTI_LINE46 ((uint32_t)0x2E) +#else +/* EXTI_LINE46 Reserved */ +#endif /* DUAL_CORE */ +#define EXTI_LINE47 ((uint32_t)0x2F) +#define EXTI_LINE48 ((uint32_t)0x30) +#define EXTI_LINE49 ((uint32_t)0x31) +#define EXTI_LINE50 ((uint32_t)0x32) +#define EXTI_LINE51 ((uint32_t)0x33) +#define EXTI_LINE52 ((uint32_t)0x34) +#define EXTI_LINE53 ((uint32_t)0x35) +#define EXTI_LINE54 ((uint32_t)0x36) +#define EXTI_LINE55 ((uint32_t)0x37) +#define EXTI_LINE56 ((uint32_t)0x38) +#define EXTI_LINE57 ((uint32_t)0x39) +#define EXTI_LINE58 ((uint32_t)0x3A) +#define EXTI_LINE59 ((uint32_t)0x3B) +#define EXTI_LINE60 ((uint32_t)0x3C) +#define EXTI_LINE61 ((uint32_t)0x3D) +#define EXTI_LINE62 ((uint32_t)0x3E) +#define EXTI_LINE63 ((uint32_t)0x3F) +#define EXTI_LINE64 ((uint32_t)0x40) +#define EXTI_LINE65 ((uint32_t)0x41) +#define EXTI_LINE66 ((uint32_t)0x42) +#define EXTI_LINE67 ((uint32_t)0x43) +#define EXTI_LINE68 ((uint32_t)0x44) +#define EXTI_LINE69 ((uint32_t)0x45) +#define EXTI_LINE70 ((uint32_t)0x46) +#define EXTI_LINE71 ((uint32_t)0x47) +#define EXTI_LINE72 ((uint32_t)0x48) +#define EXTI_LINE73 ((uint32_t)0x49) +#define EXTI_LINE74 ((uint32_t)0x4A) +#define EXTI_LINE75 ((uint32_t)0x4B) /* Not available in all family lines */ +#define EXTI_LINE76 ((uint32_t)0x4C) /* Not available in all family lines */ +#if defined(DUAL_CORE) +#define EXTI_LINE77 ((uint32_t)0x4D) +#define EXTI_LINE78 ((uint32_t)0x4E) +#define EXTI_LINE79 ((uint32_t)0x4F) +#define EXTI_LINE80 ((uint32_t)0x50) +#else +/* EXTI_LINE77 Reserved */ +/* EXTI_LINE78 Reserved */ +/* EXTI_LINE79 Reserved */ +/* EXTI_LINE80 Reserved */ +#endif /* DUAL_CORE */ +/* EXTI_LINE81 Reserved */ +#if defined(DUAL_CORE) +#define EXTI_LINE82 ((uint32_t)0x52) +#else +/* EXTI_LINE82 Reserved */ +#endif /* DUAL_CORE */ +/* EXTI_LINE83 Reserved */ +#if defined(DUAL_CORE) +#define EXTI_LINE84 ((uint32_t)0x54) +#else +/* EXTI_LINE84 Reserved */ +#endif /* DUAL_CORE */ +#define EXTI_LINE85 ((uint32_t)0x55) +#define EXTI_LINE86 ((uint32_t)0x56) /* Not available in all family lines */ +#define EXTI_LINE87 ((uint32_t)0x57) +#define EXTI_LINE88 ((uint32_t)0x58) /* Not available in all family lines */ +#define EXTI_LINE89 ((uint32_t)0x59) /* Not available in all family lines */ +#define EXTI_LINE90 ((uint32_t)0x5A) /* Not available in all family lines */ +#define EXTI_LINE91 ((uint32_t)0x5B) /* Not available in all family lines */ + +#if defined(DUAL_CORE) +#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \ + ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84) || \ + ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86)) +#else +#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \ + ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86)) +#endif /* DUAL_CORE */ + +#if defined(DUAL_CORE) +#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \ + ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ + ((LINE) == EXTI_LINE78) || \ + ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82)) +#else +#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ + ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \ + ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \ + ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87)) +#else +#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ + ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \ + ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \ + ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ + ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53)) +#elif (POWER_DOMAINS_NUMBER == 3U) +#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ + ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE88)) +#else +#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ + ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88)) +#endif /*DUAL_CORE*/ + + +#define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/ +#define BDMA_CH7_CLEAR ((uint32_t)0x00000001) /*!< BDMA ch7 event selected as D3 domain pendclear source*/ +#if defined (LPTIM4) +#define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM4 out selected as D3 domain pendclear source*/ +#else +#define LPTIM2_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM2 out selected as D3 domain pendclear source*/ +#endif /* LPTIM4 */ +#if defined (LPTIM5) +#define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM5 out selected as D3 domain pendclear source*/ +#else +#define LPTIM3_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM3 out selected as D3 domain pendclear source*/ +#endif /* LPTIM5 */ +#if defined (LPTIM4) && defined (LPTIM5) +#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \ + ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR)) +#else +#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \ + ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR)) +#endif /* LPTIM4 LPTIM5 */ +/** + * @} + */ + + +/** @defgroup FMC_SwapBankMapping_Config SwapBankMapping Config + * @{ + */ +#define FMC_SWAPBMAP_DISABLE (0x00000000U) +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0 +#define FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1 + +#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE) || \ + ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \ + ((__MODE__) == FMC_SWAPBMAP_SDRAMB2)) +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ +#if defined(DUAL_CORE) +/** @defgroup ART_Exported_Macros ART Exported Macros + * @{ + */ + +/** @brief ART Enable Macro. + * Enable the Cortex-M4 ART cache. + */ +#define __HAL_ART_ENABLE() SET_BIT(ART->CTR, ART_CTR_EN) + +/** @brief ART Disable Macro. + * Disable the Cortex-M4 ART cache. + */ +#define __HAL_ART_DISABLE() CLEAR_BIT(ART->CTR, ART_CTR_EN) + +/** @brief ART Cache BaseAddress Config. + * Configure the Cortex-M4 ART cache Base Address. + */ +#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__) MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL)) + +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** @brief SYSCFG Break AXIRAM double ECC lock. + * Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML) + +/** @brief SYSCFG Break ITCM double ECC lock. + * Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML) + +/** @brief SYSCFG Break DTCM double ECC lock. + * Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML) + +/** @brief SYSCFG Break SRAM1 double ECC lock. + * Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L) + +/** @brief SYSCFG Break SRAM2 double ECC lock. + * Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L) + +/** @brief SYSCFG Break SRAM3 double ECC lock. + * Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L) + +/** @brief SYSCFG Break SRAM4 double ECC lock. + * Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L) + +/** @brief SYSCFG Break Backup SRAM double ECC lock. + * Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML) + +/** @brief SYSCFG Break Cortex-M7 Lockup lock. + * Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L) + +/** @brief SYSCFG Break FLASH double ECC lock. + * Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL) + +#if defined(DUAL_CORE) +/** @brief SYSCFG Break Cortex-M4 Lockup lock. + * Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L) +#endif /* DUAL_CORE */ + +#if !defined(SYSCFG_PMCR_BOOSTEN) +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of : + * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 + * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 + * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 + * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\ + }while(0) + +#endif /* !SYSCFG_PMCR_BOOSTEN */ +/** + * @} + */ + +/** @defgroup DBG_Exported_Macros DBG Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#define __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1)) + +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2)) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3)) +#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4)) +#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5)) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6)) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7)) +#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12)) +#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13)) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14)) +#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1)) +#define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1)) +#define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2)) +#define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3)) +#if defined(I2C5) +#define __HAL_DBGMCU_FREEZE_I2C5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C5)) +#endif /*I2C5*/ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) +#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN)) +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ + +#if defined(TIM23) +#define __HAL_DBGMCU_FREEZE_TIM23() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM23)) +#endif /*TIM23*/ +#if defined(TIM24) +#define __HAL_DBGMCU_FREEZE_TIM24() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM24)) +#endif /*TIM24*/ + +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1)) +#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8)) +#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15)) +#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16)) +#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17)) +#define __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM)) + +#define __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4)) +#define __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2)) +#define __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3)) +#define __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4)) +#define __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5)) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC)) +#define __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1)) + + +#define __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1)) + +#define __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2)) +#define __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3)) +#define __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4)) +#define __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5)) +#define __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6)) +#define __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7)) +#define __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12)) +#define __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13)) +#define __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14)) +#define __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1)) +#define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1)) +#define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2)) +#define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3)) +#if defined(I2C5) +#define __HAL_DBGMCU_UnFreeze_I2C5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C5)) +#endif /*I2C5*/ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) +#define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN)) +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ + +#if defined(TIM23) +#define __HAL_DBGMCU_UnFreeze_TIM23() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM23)) +#endif /*TIM23*/ +#if defined(TIM24) +#define __HAL_DBGMCU_UnFreeze_TIM24() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM24)) +#endif /*TIM24*/ + +#define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1)) +#define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8)) +#define __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15)) +#define __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16)) +#define __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17)) +#define __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM)) + +#define __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4)) +#define __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2)) +#define __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3)) +#define __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4)) +#define __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5)) +#define __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC)) +#define __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1)) + + +#if defined(DUAL_CORE) +#define __HAL_DBGMCU_FREEZE2_IWDG2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG2)) +#define __HAL_DBGMCU_FREEZE2_WWDG2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2)) + +#define __HAL_DBGMCU_UnFreeze2_IWDG2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2)) +#define __HAL_DBGMCU_UnFreeze2_WWDG2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2)) + + +#define __HAL_DBGMCU_FREEZE2_WWDG1() (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1)) + +#define __HAL_DBGMCU_FREEZE2_TIM2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2)) +#define __HAL_DBGMCU_FREEZE2_TIM3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3)) +#define __HAL_DBGMCU_FREEZE2_TIM4() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4)) +#define __HAL_DBGMCU_FREEZE2_TIM5() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5)) +#define __HAL_DBGMCU_FREEZE2_TIM6() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6)) +#define __HAL_DBGMCU_FREEZE2_TIM7() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7)) +#define __HAL_DBGMCU_FREEZE2_TIM12() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12)) +#define __HAL_DBGMCU_FREEZE2_TIM13() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13)) +#define __HAL_DBGMCU_FREEZE2_TIM14() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14)) +#define __HAL_DBGMCU_FREEZE2_LPTIM1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1)) +#define __HAL_DBGMCU_FREEZE2_I2C1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1)) +#define __HAL_DBGMCU_FREEZE2_I2C2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2)) +#define __HAL_DBGMCU_FREEZE2_I2C3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3)) +#define __HAL_DBGMCU_FREEZE2_FDCAN() (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN)) + + +#define __HAL_DBGMCU_FREEZE2_TIM1() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1)) +#define __HAL_DBGMCU_FREEZE2_TIM8() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8)) +#define __HAL_DBGMCU_FREEZE2_TIM15() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15)) +#define __HAL_DBGMCU_FREEZE2_TIM16() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16)) +#define __HAL_DBGMCU_FREEZE2_TIM17() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17)) +#define __HAL_DBGMCU_FREEZE2_HRTIM() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM)) + +#define __HAL_DBGMCU_FREEZE2_I2C4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4)) +#define __HAL_DBGMCU_FREEZE2_LPTIM2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2)) +#define __HAL_DBGMCU_FREEZE2_LPTIM3() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3)) +#define __HAL_DBGMCU_FREEZE2_LPTIM4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4)) +#define __HAL_DBGMCU_FREEZE2_LPTIM5() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5)) +#define __HAL_DBGMCU_FREEZE2_RTC() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC)) +#define __HAL_DBGMCU_FREEZE2_IWDG1() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1)) + +#define __HAL_DBGMCU_UnFreeze2_WWDG1() (DBGMCU->APB3FZ2 &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1)) + +#define __HAL_DBGMCU_UnFreeze2_TIM2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2)) +#define __HAL_DBGMCU_UnFreeze2_TIM3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3)) +#define __HAL_DBGMCU_UnFreeze2_TIM4() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4)) +#define __HAL_DBGMCU_UnFreeze2_TIM5() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5)) +#define __HAL_DBGMCU_UnFreeze2_TIM6() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6)) +#define __HAL_DBGMCU_UnFreeze2_TIM7() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7)) +#define __HAL_DBGMCU_UnFreeze2_TIM12() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12)) +#define __HAL_DBGMCU_UnFreeze2_TIM13() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13)) +#define __HAL_DBGMCU_UnFreeze2_TIM14() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1)) +#define __HAL_DBGMCU_UnFreeze2_I2C1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1)) +#define __HAL_DBGMCU_UnFreeze2_I2C2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2)) +#define __HAL_DBGMCU_UnFreeze2_I2C3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3)) +#define __HAL_DBGMCU_UnFreeze2_FDCAN() (DBGMCU->APB1HFZ2 &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN)) + + +#define __HAL_DBGMCU_UnFreeze2_TIM1() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM1)) +#define __HAL_DBGMCU_UnFreeze2_TIM8() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM8)) +#define __HAL_DBGMCU_UnFreeze2_TIM15() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM15)) +#define __HAL_DBGMCU_UnFreeze2_TIM16() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM16)) +#define __HAL_DBGMCU_UnFreeze2_TIM17() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM17)) +#define __HAL_DBGMCU_UnFreeze2_HRTIM() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM)) + +#define __HAL_DBGMCU_UnFreeze2_I2C4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_I2C4)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM3() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM5() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5)) +#define __HAL_DBGMCU_UnFreeze2_RTC() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_RTC)) +#define __HAL_DBGMCU_UnFreeze2_IWDG1() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1)) + +#endif /*DUAL_CORE*/ +/** + * @} + */ +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +/** @defgroup HAL_Group1 Initialization and de-initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); + +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @defgroup HAL_Group2 HAL Control functions + * + */ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +#if defined(SYSCFG_PMCR_EPIS_SEL) +void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface); +#endif /* SYSCFG_PMCR_EPIS_SEL */ +void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ); +#if defined(SYSCFG_PMCR_BOOSTEN) +void HAL_SYSCFG_EnableBOOST(void); +void HAL_SYSCFG_DisableBOOST(void); +#endif /* SYSCFG_PMCR_BOOSTEN */ + +#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0) +void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress); +#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/ + +#if defined(DUAL_CORE) +void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress); +void HAL_SYSCFG_EnableCM7BOOT(void); +void HAL_SYSCFG_DisableCM7BOOT(void); +void HAL_SYSCFG_EnableCM4BOOT(void); +void HAL_SYSCFG_DisableCM4BOOT(void); +#endif /*DUAL_CORE*/ +void HAL_EnableCompensationCell(void); +void HAL_DisableCompensationCell(void); +void HAL_SYSCFG_EnableIOSpeedOptimize(void); +void HAL_SYSCFG_DisableIOSpeedOptimize(void); +void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode); +void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); +#if defined(SYSCFG_CCCR_NCC_MMC) +void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); +#endif /* SYSCFG_CCCR_NCC_MMC */ +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +#if defined(DUAL_CORE) +void HAL_EnableDomain2DBGSleepMode(void); +void HAL_DisableDomain2DBGSleepMode(void); +void HAL_EnableDomain2DBGStopMode(void); +void HAL_DisableDomain2DBGStopMode(void); +void HAL_EnableDomain2DBGStandbyMode(void); +void HAL_DisableDomain2DBGStandbyMode(void); +#endif /*DUAL_CORE*/ +#if defined(DBGMCU_CR_DBG_STOPD3) +void HAL_EnableDomain3DBGStopMode(void); +void HAL_DisableDomain3DBGStopMode(void); +#endif /*DBGMCU_CR_DBG_STOPD3*/ +#if defined(DBGMCU_CR_DBG_STANDBYD3) +void HAL_EnableDomain3DBGStandbyMode(void); +void HAL_DisableDomain3DBGStandbyMode(void); +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ +void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge ); +void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +#if defined(DUAL_CORE) +void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line); +#endif /*DUAL_CORE*/ +void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line); +void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd); +#if defined(DUAL_CORE) +void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd); +#endif /*DUAL_CORE*/ +void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc); +void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig); +uint32_t HAL_GetFMCMemorySwappingConfig(void); +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); +void HAL_SYSCFG_DisableVREFBUF(void); +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) +void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0); +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1); +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_H */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h new file mode 100644 index 0000000..cc4c24c --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h @@ -0,0 +1,461 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_CORTEX_H +#define STM32H7xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +#if !defined(CORE_CM4) +#define MPU_REGION_NUMBER8 ((uint8_t)0x08) +#define MPU_REGION_NUMBER9 ((uint8_t)0x09) +#define MPU_REGION_NUMBER10 ((uint8_t)0x0A) +#define MPU_REGION_NUMBER11 ((uint8_t)0x0B) +#define MPU_REGION_NUMBER12 ((uint8_t)0x0C) +#define MPU_REGION_NUMBER13 ((uint8_t)0x0D) +#define MPU_REGION_NUMBER14 ((uint8_t)0x0E) +#define MPU_REGION_NUMBER15 ((uint8_t)0x0F) +#endif /* !defined(CORE_CM4) */ + +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** + * @} + */ + + + +/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier + * @{ + */ +#define CM7_CPUID ((uint32_t)0x00000003) + +#if defined(DUAL_CORE) +#define CM4_CPUID ((uint32_t)0x00000001) +#endif /*DUAL_CORE*/ +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +#if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +uint32_t HAL_GetCurrentCPUID(void); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) + +#define IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#if !defined(CORE_CM4) +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7) || \ + ((NUMBER) == MPU_REGION_NUMBER8) || \ + ((NUMBER) == MPU_REGION_NUMBER9) || \ + ((NUMBER) == MPU_REGION_NUMBER10) || \ + ((NUMBER) == MPU_REGION_NUMBER11) || \ + ((NUMBER) == MPU_REGION_NUMBER12) || \ + ((NUMBER) == MPU_REGION_NUMBER13) || \ + ((NUMBER) == MPU_REGION_NUMBER14) || \ + ((NUMBER) == MPU_REGION_NUMBER15)) +#else +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) +#endif /* !defined(CORE_CM4) */ + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_CORTEX_H */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h new file mode 100644 index 0000000..188e31c --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h @@ -0,0 +1,222 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_DEF +#define STM32H7xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +/** @brief Reset the Handle's State field. + * @param __HANDLE__: specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) + #error " USE_RTOS should be 0 in the current HAL release " +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler V5 */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ +#if defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__CC_ARM) /* ARM Compiler */ + #define ALIGN_32BYTES(buf) __align(32) buf +#endif + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_DEF */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h new file mode 100644 index 0000000..59ad97a --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h @@ -0,0 +1,1333 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_DMA_H +#define STM32H7xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the request selected for the specified stream. + This parameter can be a value of @ref DMA_Request_selection */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_Priority_level */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_FIFO_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_FIFO_threshold_level */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Transfer complete level structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callbacks IDs structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + void *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ + + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ + + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */ + + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + + + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */ + + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ + +}DMA_HandleTypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @brief DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */ +#define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */ +#define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */ + +/** + * @} + */ + +/** @defgroup DMA_Request_selection DMA Request selection + * @brief DMA Request selection + * @{ + */ +/* DMAMUX1 requests */ +#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ + +#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ +#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ +#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ +#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ +#define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ +#define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ +#define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ +#define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ + +#define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */ +#define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */ + +#define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ +#define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ +#define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ +#define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ +#define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ +#define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ +#define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ + +#define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ +#define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ +#define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ +#define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ +#define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ + +#define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ +#define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ +#define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ +#define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ +#define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ +#define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ + +#define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ +#define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ +#define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ +#define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ + +#define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ +#define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ +#define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ +#define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ + +#define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ +#define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ +#define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ +#define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ + +#define DMA_REQUEST_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */ +#define DMA_REQUEST_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */ +#define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ +#define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ +#define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ +#define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ + +#define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ +#define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ +#define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ +#define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ +#define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ +#define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ +#define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ + +#define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ +#define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ +#define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ +#define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ +#define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ +#define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ + +#define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ +#define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ + +#define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ +#define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ +#define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ +#define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ + +#define DMA_REQUEST_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */ +#define DMA_REQUEST_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */ + +#define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ +#define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ + +#define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ +#define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ + +#define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ +#define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ + +#if defined (PSSI) +#define DMA_REQUEST_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */ +#define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */ +#else +#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */ +#endif /* PSSI */ + +#define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */ +#define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */ + +#define DMA_REQUEST_HASH_IN 78U /*!< DMAMUX1 HASH IN request */ + +#define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ +#define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ +#define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ +#define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ + +#define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ +#define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ +#define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ +#define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ + +#define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ +#define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ + +#if defined(SAI2) +#define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ +#define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ +#endif /* SAI2 */ + +#define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */ +#define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */ + +#define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ +#define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ + +#if defined(HRTIM1) +#define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ +#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */ +#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */ +#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */ +#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */ +#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6*/ +#endif /* HRTIM1 */ + +#define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ +#define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ +#define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */ +#define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */ + +#define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ +#define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ +#define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ +#define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ + +#define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ +#define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ + +#define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ +#define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ + +#if defined(SAI3) +#define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ +#define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ +#endif /* SAI3 */ + +#if defined(ADC3) +#define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */ +#endif /* ADC3 */ + +#if defined(UART9) +#define DMA_REQUEST_UART9_RX 116U /*!< DMAMUX1 UART9 request */ +#define DMA_REQUEST_UART9_TX 117U /*!< DMAMUX1 UART9 request */ +#endif /* UART9 */ + +#if defined(USART10) +#define DMA_REQUEST_USART10_RX 118U /*!< DMAMUX1 USART10 request */ +#define DMA_REQUEST_USART10_TX 119U /*!< DMAMUX1 USART10 request */ +#endif /* USART10 */ + +#if defined(FMAC) +#define DMA_REQUEST_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */ +#define DMA_REQUEST_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */ +#endif /* FMAC */ + +#if defined(CORDIC) +#define DMA_REQUEST_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */ +#define DMA_REQUEST_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */ +#endif /* CORDIC */ + +#if defined(I2C5) +#define DMA_REQUEST_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */ +#define DMA_REQUEST_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */ +#endif /* I2C5 */ + +#if defined(TIM23) +#define DMA_REQUEST_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */ +#define DMA_REQUEST_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */ +#define DMA_REQUEST_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */ +#define DMA_REQUEST_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */ +#define DMA_REQUEST_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */ +#define DMA_REQUEST_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */ +#endif /* TIM23 */ + +#if defined(TIM24) +#define DMA_REQUEST_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */ +#define DMA_REQUEST_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */ +#define DMA_REQUEST_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */ +#define DMA_REQUEST_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */ +#define DMA_REQUEST_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */ +#define DMA_REQUEST_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */ +#endif /* TIM24 */ + +/* DMAMUX2 requests */ +#define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ +#define BDMA_REQUEST_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */ +#define BDMA_REQUEST_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */ +#define BDMA_REQUEST_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */ +#define BDMA_REQUEST_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */ +#define BDMA_REQUEST_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */ +#define BDMA_REQUEST_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */ +#define BDMA_REQUEST_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */ +#define BDMA_REQUEST_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */ +#define BDMA_REQUEST_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */ +#define BDMA_REQUEST_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */ +#define BDMA_REQUEST_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */ +#define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */ +#define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */ +#define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */ +#if defined(SAI4) +#define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */ +#define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */ +#endif /* SAI4 */ +#if defined(ADC3) +#define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */ +#endif /* ADC3 */ +#if defined(DAC2) +#define BDMA_REQUEST_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */ +#endif /* DAC2 */ +#if defined(DFSDM2_Channel0) +#define BDMA_REQUEST_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 request */ +#endif /* DFSDM1_Channel0 */ + +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @brief DMA data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @brief DMA peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @brief DMA memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @brief DMA mode + * @{ + */ +#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ +#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ +#define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM) /*!< Double buffer mode with first target memory M0 */ +#define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @brief DMA priority levels + * @{ + */ +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode + * @brief DMA FIFO direct mode + * @{ + */ +#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ +#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level + * @brief DMA FIFO level + * @{ + */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ +#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ +#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_Memory_burst DMA Memory burst + * @brief DMA memory burst + * @{ + */ +#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) +#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) +#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) +#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_burst DMA Peripheral burst + * @brief DMA peripheral burst + * @{ + */ +#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) +#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) +#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) +#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @brief DMA interrupts definition + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) +#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) +#define DMA_IT_FE ((uint32_t)0x00000080U) +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @brief DMA flag definitions + * @{ + */ +#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U) +#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U) +#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) +#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) +#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) +#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) +#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) +#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) +#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) +#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) +#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) +#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) +#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) +#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) +#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) +#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) +#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) +#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) +#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) +#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) +/** + * @} + */ + +/** @defgroup BDMA_flag_definitions BDMA flag definitions + * @brief BDMA flag definitions + * @{ + */ +#define BDMA_FLAG_GL0 ((uint32_t)0x00000001) +#define BDMA_FLAG_TC0 ((uint32_t)0x00000002) +#define BDMA_FLAG_HT0 ((uint32_t)0x00000004) +#define BDMA_FLAG_TE0 ((uint32_t)0x00000008) +#define BDMA_FLAG_GL1 ((uint32_t)0x00000010) +#define BDMA_FLAG_TC1 ((uint32_t)0x00000020) +#define BDMA_FLAG_HT1 ((uint32_t)0x00000040) +#define BDMA_FLAG_TE1 ((uint32_t)0x00000080) +#define BDMA_FLAG_GL2 ((uint32_t)0x00000100) +#define BDMA_FLAG_TC2 ((uint32_t)0x00000200) +#define BDMA_FLAG_HT2 ((uint32_t)0x00000400) +#define BDMA_FLAG_TE2 ((uint32_t)0x00000800) +#define BDMA_FLAG_GL3 ((uint32_t)0x00001000) +#define BDMA_FLAG_TC3 ((uint32_t)0x00002000) +#define BDMA_FLAG_HT3 ((uint32_t)0x00004000) +#define BDMA_FLAG_TE3 ((uint32_t)0x00008000) +#define BDMA_FLAG_GL4 ((uint32_t)0x00010000) +#define BDMA_FLAG_TC4 ((uint32_t)0x00020000) +#define BDMA_FLAG_HT4 ((uint32_t)0x00040000) +#define BDMA_FLAG_TE4 ((uint32_t)0x00080000) +#define BDMA_FLAG_GL5 ((uint32_t)0x00100000) +#define BDMA_FLAG_TC5 ((uint32_t)0x00200000) +#define BDMA_FLAG_HT5 ((uint32_t)0x00400000) +#define BDMA_FLAG_TE5 ((uint32_t)0x00800000) +#define BDMA_FLAG_GL6 ((uint32_t)0x01000000) +#define BDMA_FLAG_TC6 ((uint32_t)0x02000000) +#define BDMA_FLAG_HT6 ((uint32_t)0x04000000) +#define BDMA_FLAG_TE6 ((uint32_t)0x08000000) +#define BDMA_FLAG_GL7 ((uint32_t)0x10000000) +#define BDMA_FLAG_TC7 ((uint32_t)0x20000000) +#define BDMA_FLAG_HT7 ((uint32_t)0x40000000) +#define BDMA_FLAG_TE7 ((uint32_t)0x80000000) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__: specifies the DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Return the current DMA Stream FIFO filled level. + * @param __HANDLE__: DMA handle + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0) + +/** + * @brief Enable the specified DMA Stream. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) \ +((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \ +(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN)) + +/** + * @brief Disable the specified DMA Stream. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) \ +((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \ +(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN)) + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Stream transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Return the current DMA Stream half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Return the current DMA Stream transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Return the current DMA Stream FIFO error flag. + * @param __HANDLE__: DMA handle + * @retval The specified FIFO error flag index. + */ +#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\ + (uint32_t)0x00000000) + +/** + * @brief Return the current DMA Stream direct mode error flag. + * @param __HANDLE__: DMA handle + * @retval The specified direct mode error flag index. + */ +#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\ + (uint32_t)0x00000000) + +/** + * @brief Returns the current BDMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(BDMA1) +#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Get the DMA Stream pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval The state of FLAG (SET or RESET). + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7 )? (BDMA1->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7 )? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) +#else +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) +#endif /* BDMA1 */ + +/** + * @brief Clear the DMA Stream pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval None + */ +#if defined(BDMA1) +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA1->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) +#else +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) +#endif /* BDMA1 */ + +#define DMA_TO_BDMA_IT(__DMA_IT__) \ +((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ + (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\ + (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ + (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\ + ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\ + ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\ + ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\ + (uint32_t)0x00000000) + + +#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ +(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__))) + +#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__))) + +/** + * @brief Enable the specified DMA Stream interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\ + (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\ + (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__)))) + + +#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__))) + +#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Stream interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\ + (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\ + (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__)))) + + +#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__)))) + +#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Stream interrupt is enabled or not. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval The state of DMA_IT. + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ + (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\ + (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__)))) + +/** + * @brief Writes the number of data units to be transferred on the DMA Stream. + * @param __HANDLE__: DMA handle + * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\ + (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__))) + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param __HANDLE__: DMA handle + * + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\ + (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR)) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32h7xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Types DMA Private Types + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA private macros + * @{ + */ + +#if defined(TIM24) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG)) +#elif defined(ADC3) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3)) +#else +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX)) +#endif /* TIM24 */ + +#if defined(ADC3) +#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3)) +#else +#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0)) +#endif /* ADC3 */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR) || \ + ((MODE) == DMA_PFCTRL) || \ + ((MODE) == DMA_DOUBLE_BUFFER_M0) || \ + ((MODE) == DMA_DOUBLE_BUFFER_M1)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == DMA_FIFOMODE_ENABLE)) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ + ((BURST) == DMA_MBURST_INC4) || \ + ((BURST) == DMA_MBURST_INC8) || \ + ((BURST) == DMA_MBURST_INC16)) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ + ((BURST) == DMA_PBURST_INC4) || \ + ((BURST) == DMA_PBURST_INC8) || \ + ((BURST) == DMA_PBURST_INC16)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_DMA_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h new file mode 100644 index 0000000..cde5755 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h @@ -0,0 +1,310 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_DMA_EX_H +#define STM32H7xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief HAL DMA Memory definition + */ +typedef enum +{ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U, /*!< Memory 1 */ + +}HAL_DMA_MemoryTypeDef; + +/** + * @brief HAL DMAMUX Synchronization configuration structure definition + */ +typedef struct +{ + uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. + This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */ + + uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. + This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */ + + FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled + This parameter can take the value ENABLE or DISABLE*/ + + + FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. + This parameter can take the value ENABLE or DISABLE */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event. + This parameters can be in the range 1 to 32 */ + +}HAL_DMA_MuxSyncConfigTypeDef; + + +/** + * @brief HAL DMAMUX request generator parameters structure definition + */ +typedef struct +{ + uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator + This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */ + + uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. + This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event. + This parameters can be in the range 1 to 32 */ + +}HAL_DMA_MuxRequestGeneratorConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMAEx_Exported_Constants DMA Exported Constants + * @brief DMAEx Exported constants + * @{ + */ + +/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection + * @brief DMAEx MUX SyncSignalID selection + * @{ + */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */ +#define HAL_DMAMUX1_SYNC_EXTI0 6U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */ + +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */ +#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */ +#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */ +#define HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */ +#define HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */ +#define HAL_DMAMUX2_SYNC_I2C4_WKUP 10U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */ +#define HAL_DMAMUX2_SYNC_SPI6_WKUP 11U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */ +#define HAL_DMAMUX2_SYNC_COMP1_OUT 12U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */ +#define HAL_DMAMUX2_SYNC_RTC_WKUP 13U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */ +#define HAL_DMAMUX2_SYNC_EXTI0 14U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX2_SYNC_EXTI2 15U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */ + +/** + * @} + */ + +/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection + * @brief DMAEx MUX SyncPolarity selection + * @{ + */ +#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< block synchronization events */ +#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */ + +/** + * @} + */ + + +/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection + * @brief DMAEx MUX SignalGeneratorID selection + * @{ + */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */ +#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */ + +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */ +#if defined(LPTIM4) +#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */ +#endif /* LPTIM4 */ +#if defined(LPTIM5) +#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */ +#endif /* LPTIM5 */ +#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */ +#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */ +#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */ +#define HAL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */ +#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */ +#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */ +#if defined(ADC3) +#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */ +#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */ +#endif /* ADC3 */ +#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */ +#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */ + + +/** + * @} + */ + +/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection + * @brief DMAEx MUX RequestGeneneratorPolarity selection + * @{ + */ +#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */ +#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma); + +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMA Private Macros + * @brief DMAEx private macros + * @{ + */ + +#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO) +#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2) + +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) + +#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) + +#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ + ((EVENT) == ENABLE)) + +#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO) +#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT) + +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_DMA_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h new file mode 100644 index 0000000..a7ba0c6 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h @@ -0,0 +1,537 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_EXTI_H +#define STM32H7xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ + + uint32_t PendClearSource; /*!< Specifies the event pending clear source for D3/SRD + domain. This parameter can be a value of @ref + EXTI_PendClear_Source */ + +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x00U) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x01U) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x02U) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x03U) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x04U) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x05U) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x06U) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x07U) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x08U) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x09U) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0AU) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0BU) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0CU) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0DU) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0EU) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0FU) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U) +#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x13U) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x14U) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x15U) +#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x19U) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x02U) +#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x03U) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U) +#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U) +#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U) +#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x09U) +#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU) +#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU) +#if !defined(USB2_OTG_FS) +#define EXTI_LINE_44 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0CU) +#else +#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) +#endif /* USB2_OTG_FS */ +#define EXTI_LINE_45 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0DU) +#if defined(DSI) +#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU) +#else +#define EXTI_LINE_46 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0EU) +#endif /* DSI */ +#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU) +#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x10U) +#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U) +#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U) +#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U) +#if defined(LPTIM4) +#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x14U) +#else +#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x15U) +#else +#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U) +#endif /*LPTIM5*/ +#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) +#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) +#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U) +#if defined(EXTI_IMR2_IM57) +#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U) +#else +#define EXTI_LINE_57 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x19U) +#endif /*EXTI_IMR2_IM57*/ +#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#if defined(EXTI_IMR2_IM59) +#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#else +#define EXTI_LINE_59 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x1BU) +#endif /*EXTI_IMR2_IM59*/ +#define EXTI_LINE_60 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU) +#define EXTI_LINE_61 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU) +#define EXTI_LINE_62 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU) +#define EXTI_LINE_63 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU) +#define EXTI_LINE_64 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U) +#define EXTI_LINE_65 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U) +#define EXTI_LINE_66 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U) +#define EXTI_LINE_67 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U) +#define EXTI_LINE_68 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U) +#define EXTI_LINE_69 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U) +#define EXTI_LINE_70 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U) +#define EXTI_LINE_71 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U) +#define EXTI_LINE_72 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U) +#define EXTI_LINE_73 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U) +#define EXTI_LINE_74 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU) +#if defined(ADC3) +#define EXTI_LINE_75 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU) +#else +#define EXTI_LINE_75 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0BU) +#endif /* ADC3 */ +#if defined(SAI4) +#define EXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) +#else +#define EXTI_LINE_76 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0CU) +#endif /* SAI4 */ +#if defined (DUAL_CORE) +#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU) +#define EXTI_LINE_78 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU) +#define EXTI_LINE_79 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU) +#define EXTI_LINE_80 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U) +#else +#define EXTI_LINE_77 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU) +#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU) +#define EXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU) +#define EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U) +#endif /* DUAL_CORE */ +#define EXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U) +#if defined (DUAL_CORE) +#define EXTI_LINE_82 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U) +#else +#define EXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U) +#endif /* DUAL_CORE */ +#define EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U) +#if defined (DUAL_CORE) +#define EXTI_LINE_84 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U) +#else +#define EXTI_LINE_84 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U) +#endif /* DUAL_CORE */ +#define EXTI_LINE_85 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U) +#if defined(ETH) +#define EXTI_LINE_86 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) +#else +#define EXTI_LINE_86 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U) +#endif /* ETH */ +#define EXTI_LINE_87 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) +#if defined(DTS) +#define EXTI_LINE_88 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U) +#endif /* DTS */ +#if defined(EXTI_IMR3_IM89) +#define EXTI_LINE_89 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x19U) +#endif /*EXTI_IMR3_IM89*/ +#if defined(EXTI_IMR3_IM90) +#define EXTI_LINE_90 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#endif /*EXTI_IMR3_IM90*/ +#if defined(I2C5) +#define EXTI_LINE_91 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#endif /*I2C5*/ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000U +#define EXTI_MODE_INTERRUPT 0x00000001U +#define EXTI_MODE_EVENT 0x00000002U +#if defined(DUAL_CORE) +#define EXTI_MODE_CORE1_INTERRUPT EXTI_MODE_INTERRUPT +#define EXTI_MODE_CORE1_EVENT EXTI_MODE_EVENT +#define EXTI_MODE_CORE2_INTERRUPT 0x00000010U +#define EXTI_MODE_CORE2_EVENT 0x00000020U +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000U +#define EXTI_TRIGGER_RISING 0x00000001U +#define EXTI_TRIGGER_FALLING 0x00000002U +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000U +#define EXTI_GPIOB 0x00000001U +#define EXTI_GPIOC 0x00000002U +#define EXTI_GPIOD 0x00000003U +#define EXTI_GPIOE 0x00000004U +#define EXTI_GPIOF 0x00000005U +#define EXTI_GPIOG 0x00000006U +#define EXTI_GPIOH 0x00000007U +#if defined(GPIOI) +#define EXTI_GPIOI 0x00000008U +#endif /*GPIOI*/ +#define EXTI_GPIOJ 0x00000009U +#define EXTI_GPIOK 0x0000000AU + +/** + * @} + */ + +/** @defgroup EXTI_PendClear_Source EXTI PendClear Source + * @brief + * @{ + */ +#define EXTI_D3_PENDCLR_SRC_NONE 0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero */ +#define EXTI_D3_PENDCLR_SRC_DMACH6 0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#define EXTI_D3_PENDCLR_SRC_DMACH7 0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/ +#if defined (LPTIM4) +#define EXTI_D3_PENDCLR_SRC_LPTIM4 0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#else +#define EXTI_D3_PENDCLR_SRC_LPTIM2 0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#endif +#if defined (LPTIM5) +#define EXTI_D3_PENDCLR_SRC_LPTIM5 0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#else +#define EXTI_D3_PENDCLR_SRC_LPTIM3 0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24U +#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Event presence definition + */ +#define EXTI_EVENT_PRESENCE_SHIFT 28U +#define EXTI_EVENT (0x01UL << EXTI_EVENT_PRESENCE_SHIFT) +#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16U +#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) +#define EXTI_REG3 (0x02UL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3) +#define EXTI_PIN_MASK 0x0000001FUL + +/** + * @brief EXTI Target and bit usage + */ +#define EXTI_TARGET_SHIFT 20U +#define EXTI_TARGET_MSK_NONE (0x00UL << EXTI_TARGET_SHIFT) +#define EXTI_TARGET_MSK_D3SRD (0x01UL << EXTI_TARGET_SHIFT) +#define EXTI_TARGET_MSK_CPU1 (0x02UL << EXTI_TARGET_SHIFT) +#if defined (DUAL_CORE) +#define EXTI_TARGET_MSK_CPU2 (0x04UL << EXTI_TARGET_SHIFT) +#define EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2) +#define EXTI_TARGET_MSK_ALL_CPU (EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2) +#else +#define EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1) +#define EXTI_TARGET_MSK_ALL_CPU EXTI_TARGET_MSK_CPU1 +#endif /* DUAL_CORE */ +#define EXTI_TARGET_MSK_ALL EXTI_TARGET_MASK + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#if defined (DUAL_CORE) +#define EXTI_MODE_MASK (EXTI_MODE_CORE1_EVENT | EXTI_MODE_CORE1_INTERRUPT | EXTI_MODE_CORE2_INTERRUPT | EXTI_MODE_CORE2_EVENT) +#else +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) +#endif /* DUAL_CORE */ + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if (STM32H7_DEV_ID == 0x483UL) +#define EXTI_LINE_NB 92UL +#elif (STM32H7_DEV_ID == 0x480UL) +#define EXTI_LINE_NB 89UL +#else +#define EXTI_LINE_NB 88UL +#endif /* EXTI_LINE_91 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_PROPERTY(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) +#if defined (DUAL_CORE) +#define IS_EXTI_TARGET(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)) +#else +#define IS_EXTI_TARGET(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)) +#endif + +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK |\ + EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \ + IS_EXTI_PROPERTY(__EXTI_LINE__) && IS_EXTI_TARGET(__EXTI_LINE__) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL)))) + +#define IS_EXTI_MODE(__MODE__) (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)|| \ + ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00UL) + +#if defined(GPIOI) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#endif /*GPIOI*/ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16UL) +#if defined (LPTIM4) && defined (LPTIM5) +#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5)) +#else +#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3)) +#endif /* LPTIM4 && LPTIM5 */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_EXTI_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h new file mode 100644 index 0000000..a4a137e --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h @@ -0,0 +1,2464 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_fdcan.h + * @author MCD Application Team + * @brief Header file of FDCAN HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_FDCAN_H +#define STM32H7xx_HAL_FDCAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +#if defined(FDCAN1) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FDCAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Types FDCAN Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ + HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ + HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ + HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ +} HAL_FDCAN_StateTypeDef; + +/** + * @brief FDCAN Init structure definition + */ +typedef struct +{ + uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. + This parameter can be a value of @ref FDCAN_frame_format */ + + uint32_t Mode; /*!< Specifies the FDCAN mode. + This parameter can be a value of @ref FDCAN_operating_mode */ + + FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the nominal bit time quanta. + This parameter must be a number between 1 and 512 */ + + uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a bit to perform + resynchronization. + This parameter must be a number between 1 and 128 */ + + uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter must be a number between 2 and 256 */ + + uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter must be a number between 2 and 128 */ + + uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the data bit time quanta. + This parameter must be a number between 1 and 32 */ + + uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a data bit to + perform resynchronization. + This parameter must be a number between 1 and 16 */ + + uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. + This parameter must be a number between 1 and 32 */ + + uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. + This parameter must be a number between 1 and 16 */ + + uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address. + This parameter must be a number between 0 and 2560 */ + + uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. + This parameter must be a number between 0 and 128 */ + + uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. + This parameter must be a number between 0 and 64 */ + + uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements. + This parameter must be a number between 0 and 64 */ + + uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0 element. + This parameter can be a value of @ref FDCAN_data_field_size */ + + uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements. + This parameter must be a number between 0 and 64 */ + + uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1 element. + This parameter can be a value of @ref FDCAN_data_field_size */ + + uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer elements. + This parameter must be a number between 0 and 64 */ + + uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer element. + This parameter can be a value of @ref FDCAN_data_field_size */ + + uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements. + This parameter must be a number between 0 and 32 */ + + uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers. + This parameter must be a number between 0 and 32 */ + + uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue. + This parameter must be a number between 0 and 32 */ + + uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. + This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ + + uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element. + This parameter can be a value of @ref FDCAN_data_field_size */ + +} FDCAN_InitTypeDef; + +/** + * @brief FDCAN clock calibration unit structure definition + */ +typedef struct +{ + uint32_t ClockCalibration; /*!< Enable or disable the clock calibration. + This parameter can be a value of @ref FDCAN_clock_calibration. */ + + uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider when the clock calibration + is bypassed. + This parameter can be a value of @ref FDCAN_clock_divider */ + + uint32_t MinOscClkPeriods; /*!< Configures the minimum number of periods in two CAN bit times. The + actual configured number of periods is MinOscClkPeriods x 32. + This parameter must be a number between 0x00 and 0xFF */ + + uint32_t CalFieldLength; /*!< Specifies the calibration field length. + This parameter can be a value of @ref FDCAN_calibration_field_length */ + + uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time. + This parameter must be a number between 4 and 25 */ + + uint32_t WatchdogStartValue; /*!< Start value of the Calibration Watchdog Counter. + If set to zero the counter is disabled. + This parameter must be a number between 0x0000 and 0xFFFF */ + +} FDCAN_ClkCalUnitTypeDef; + +/** + * @brief FDCAN filter structure definition + */ +typedef struct +{ + uint32_t IdType; /*!< Specifies the identifier type. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. + This parameter must be a number between: + - 0 and 127, if IdType is FDCAN_STANDARD_ID + - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t FilterType; /*!< Specifies the filter type. + This parameter can be a value of @ref FDCAN_filter_type. + The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted + only when IdType is FDCAN_EXTENDED_ID. + This parameter is ignored if FilterConfig is set to + FDCAN_FILTER_TO_RXBUFFER */ + + uint32_t FilterConfig; /*!< Specifies the filter configuration. + This parameter can be a value of @ref FDCAN_filter_config */ + + uint32_t FilterID1; /*!< Specifies the filter identification 1. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t FilterID2; /*!< Specifies the filter identification 2. + This parameter is ignored if FilterConfig is set to + FDCAN_FILTER_TO_RXBUFFER. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t RxBufferIndex; /*!< Contains the index of the Rx buffer in which the + matching message will be stored. + This parameter must be a number between 0 and 63. + This parameter is ignored if FilterConfig is different + from FDCAN_FILTER_TO_RXBUFFER */ + + uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for + calibration messages. + This parameter is ignored if FilterConfig is different + from FDCAN_FILTER_TO_RXBUFFER. + This parameter can be: + - 0 : ordinary message + - 1 : calibration message */ + +} FDCAN_FilterTypeDef; + +/** + * @brief FDCAN Tx header structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type for the message that will be + transmitted. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without + bit rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or + FD format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. + This parameter can be a value of @ref FDCAN_EFC */ + + uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO + element for identification of Tx message status. + This parameter must be a number between 0 and 0xFF */ + +} FDCAN_TxHeaderTypeDef; + +/** + * @brief FDCAN Rx header structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type of the received message. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t RxFrameType; /*!< Specifies the the received message frame type. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the received frame length. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit + rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD + format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame + reception. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. + This parameter must be a number between: + - 0 and 127, if IdType is FDCAN_STANDARD_ID + - 0 and 63, if IdType is FDCAN_EXTENDED_ID + When the frame is a Non-Filter matching frame, this parameter + is unused. */ + + uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. + Acceptance of non-matching frames may be enabled via + HAL_FDCAN_ConfigGlobalFilter(). + This parameter takes 0 if the frame matched an Rx filter or + 1 if it did not match any Rx filter */ + +} FDCAN_RxHeaderTypeDef; + +/** + * @brief FDCAN Tx event FIFO structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the length of the transmitted frame. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit + rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD + format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame + transmission. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element + for identification of Tx message status. + This parameter must be a number between 0 and 0xFF */ + + uint32_t EventType; /*!< Specifies the event type. + This parameter can be a value of @ref FDCAN_event_type */ + +} FDCAN_TxEventFifoTypeDef; + +/** + * @brief FDCAN High Priority Message Status structure definition + */ +typedef struct +{ + uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. + This parameter can be: + - 0 : Standard Filter List + - 1 : Extended Filter List */ + + uint32_t FilterIndex; /*!< Specifies the index of matching filter element. + This parameter can be a number between: + - 0 and 127, if FilterList is 0 (Standard) + - 0 and 63, if FilterList is 1 (Extended) */ + + uint32_t MessageStorage; /*!< Specifies the HP Message Storage. + This parameter can be a value of @ref FDCAN_hp_msg_storage */ + + uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the + message was stored. + This parameter is valid only when MessageStorage is: + FDCAN_HP_STORAGE_RXFIFO0 + or + FDCAN_HP_STORAGE_RXFIFO1 */ + +} FDCAN_HpMsgStatusTypeDef; + +/** + * @brief FDCAN Protocol Status structure definition + */ +typedef struct +{ + uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. + This parameter can be a value of @ref FDCAN_protocol_error_code */ + + uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase + of a CAN FD format frame with its BRS flag set. + This parameter can be a value of @ref FDCAN_protocol_error_code */ + + uint32_t Activity; /*!< Specifies the FDCAN module communication state. + This parameter can be a value of @ref FDCAN_communication_state */ + + uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. + This parameter can be: + - 0 : The FDCAN is in Error_Active state + - 1 : The FDCAN is in Error_Passive state */ + + uint32_t Warning; /*!< Specifies the FDCAN module warning status. + This parameter can be: + - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the + Error_Warning limit of 96 + - 1 : at least one of error counters has reached the Error_Warning + limit of 96 */ + + uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. + This parameter can be: + - 0 : The FDCAN is not in Bus_Off state + - 1 : The FDCAN is in Bus_Off state */ + + uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. + This parameter can be: + - 0 : Last received CAN FD message did not have its ESI flag set + - 1 : Last received CAN FD message had its ESI flag set */ + + uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. + This parameter can be: + - 0 : Last received CAN FD message did not have its BRS flag set + - 1 : Last received CAN FD message had its BRS flag set */ + + uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received + since last protocol status. + This parameter can be: + - 0 : No CAN FD message received + - 1 : CAN FD message received */ + + uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. + This parameter can be: + - 0 : No protocol exception event occurred since last read access + - 1 : Protocol exception event occurred */ + + uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. + This parameter can be a number between 0 and 127 */ + +} FDCAN_ProtocolStatusTypeDef; + +/** + * @brief FDCAN Error Counters structure definition + */ +typedef struct +{ + uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. + This parameter can be a number between 0 and 255 */ + + uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. + This parameter can be a number between 0 and 127 */ + + uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. + This parameter can be: + - 0 : The Receive Error Counter (RxErrorCnt) is below the error + passive level of 128 + - 1 : The Receive Error Counter (RxErrorCnt) has reached the error + passive level of 128 */ + + uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. + This parameter can be a number between 0 and 255. + This counter is incremented each time when a FDCAN protocol error causes + the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; + the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag + FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ + +} FDCAN_ErrorCountersTypeDef; + +/** + * @brief FDCAN TT Init structure definition + */ +typedef struct +{ + uint32_t OperationMode; /*!< Specifies the FDCAN Operation Mode. + This parameter can be a value of @ref FDCAN_operation_mode */ + + uint32_t GapEnable; /*!< Specifies the FDCAN TT Operation. + This parameter can be a value of @ref FDCAN_TT_operation. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL0 */ + + uint32_t TimeMaster; /*!< Specifies whether the instance is a slave or a potential master. + This parameter can be a value of @ref FDCAN_TT_time_master */ + + uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR + numerator : TUR = (Numerator +/- SDL) / Denominator. + With : SDL = 2^(SyncDevLimit+5). + This parameter must be a number between 0 and 7 */ + + uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset. + This parameter must be a number between 0 and 127 */ + + uint32_t ExternalClkSync; /*!< Enable or disable External Clock Synchronization. + This parameter can be a value of @ref FDCAN_TT_external_clk_sync. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL1 */ + + uint32_t AppWdgLimit; /*!< Specifies the Application Watchdog Limit : maximum time after + which the application has to serve the application watchdog. + The application watchdog is incremented once each 256 NTUs. + The application watchdog can be disabled by setting AppWdgLimit to 0. + This parameter must be a number between 0 and 255. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL0 */ + + uint32_t GlobalTimeFilter; /*!< Enable or disable Global Time Filtering. + This parameter can be a value of @ref FDCAN_TT_global_time_filtering. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL1 */ + + uint32_t ClockCalibration; /*!< Enable or disable Automatic Clock Calibration. + This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL1 */ + + uint32_t EvtTrigPolarity; /*!< Specifies the Event Trigger Polarity. + This parameter can be a value of @ref FDCAN_TT_event_trig_polarity. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL0 */ + + uint32_t BasicCyclesNbr; /*!< Specifies the number of basic cycles in the system matrix. + This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */ + + uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc. + This parameter can be a value of @ref FDCAN_TT_cycle_start_sync */ + + uint32_t TxEnableWindow; /*!< Specifies the length of Tx enable window in NTUs. + This parameter must be a number between 1 and 16 */ + + uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix. + This is the sum of Tx_Triggers for exclusive, single arbitrating and + merged arbitrating windows. + This parameter must be a number between 0 and 4095 */ + + uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator. + It is advised to set this parameter to the largest applicable value. + This parameter must be a number between 0x10000 and 0x1FFFF */ + + uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator. + This parameter must be a number between 0x0001 and 0x3FFF */ + + uint32_t TriggerMemoryNbr; /*!< Specifies the number of trigger memory elements. + This parameter must be a number between 0 and 64 */ + + uint32_t StopWatchTrigSel; /*!< Specifies the input to be used as stop watch trigger. + This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */ + + uint32_t EventTrigSel; /*!< Specifies the input to be used as event trigger. + This parameter can be a value of @ref FDCAN_TT_event_trig_selection */ + +} FDCAN_TT_ConfigTypeDef; + +/** + * @brief FDCAN Trigger structure definition + */ +typedef struct +{ + uint32_t TriggerIndex; /*!< Specifies the trigger which will be configured. + This parameter must be a number between 0 and 63 */ + + uint32_t TimeMark; /*!< Specifies the cycle time for which the trigger becomes active. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t RepeatFactor; /*!< Specifies the trigger repeat factor. + This parameter can be a value of @ref FDCAN_TT_Repeat_Factor */ + + uint32_t StartCycle; /*!< Specifies the index of the first cycle in which the trigger becomes active. + This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. + This parameter must be a number between 0 and RepeatFactor */ + + uint32_t TmEventInt; /*!< Enable or disable the internal time mark event. + If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element + becomes active. + This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal */ + + uint32_t TmEventExt; /*!< Enable or disable the external time mark event. + If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when + trigger memory element becomes active. + This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External */ + + uint32_t TriggerType; /*!< Specifies the trigger type. + This parameter can be a value of @ref FDCAN_TT_Trigger_Type */ + + uint32_t FilterType; /*!< Specifies the filter identifier type. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid. + This parameter can be a value of @ref FDCAN_Tx_location. + This parameter is taken in consideration only if the trigger is configured for + transmission. */ + + uint32_t FilterIndex; /*!< Specifies the filter for which the trigger is valid. + This parameter is taken in consideration only if the trigger is configured for + reception. + This parameter must be a number between: + - 0 and 127, if FilterType is FDCAN_STANDARD_ID + - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */ + +} FDCAN_TriggerTypeDef; + +/** + * @brief FDCAN TT Operation Status structure definition + */ +typedef struct +{ + uint32_t ErrorLevel; /*!< Specifies the type of the TT operation error level. + This parameter can be a value of @ref FDCAN_TT_error_level */ + + uint32_t MasterState; /*!< Specifies the type of the TT master state. + This parameter can be a value of @ref FDCAN_TT_master_state */ + + uint32_t SyncState; /*!< Specifies the type of the TT synchronization state. + This parameter can be a value of @ref FDCAN_TT_sync_state */ + + uint32_t GTimeQuality; /*!< Specifies the Quality of Global Time Phase. + This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0. + This parameter can be: + - 0 : Global time not valid + - 1 : Global time in phase with Time Master */ + + uint32_t ClockQuality; /*!< Specifies the Quality of Clock Speed. + This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1. + This parameter can be: + - 0 : Local clock speed not synchronized to Time Master clock speed + - 1 : Synchronization Deviation = SDL */ + + uint32_t RefTrigOffset; /*!< Specifies the Actual Reference Trigger Offset Value. + This parameter can be a number between 0 and 0xFF */ + + uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State. + This parameter can be: + - 0 : No global time preset pending + - 1 : Node waits for the global time preset to take effect */ + + uint32_t GapFinished; /*!< Specifies whether a Gap is finished. + This parameter can be: + - 0 : Reset at the end of each reference message + - 1 : Gap finished */ + + uint32_t MasterPriority; /*!< Specifies the Priority of actual Time Master. + This parameter can be a number between 0 and 0x7 */ + + uint32_t GapStarted; /*!< Specifies whether a Gap is started. + This parameter can be: + - 0 : No Gap in schedule + - 1 : Gap time after Basic Cycle has started */ + + uint32_t WaitForEvt; /*!< Specifies whether a Gap is announced. + This parameter can be: + - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0 + - 1 : Reference message with Next_is_Gap = 1 received */ + + uint32_t AppWdgEvt; /*!< Specifies the Application Watchdog State. + This parameter can be: + - 0 : Application Watchdog served in time + - 1 : Failed to serve Application Watchdog in time */ + + uint32_t ECSPending; /*!< Specifies the External Clock Synchronization State. + This parameter can be: + - 0 : No external clock synchronization pending + - 1 : Node waits for external clock synchronization to take effect */ + + uint32_t PhaseLock; /*!< Specifies the Phase Lock State. + This parameter can be: + - 0 : Phase outside range + - 1 : Phase inside range */ + +} FDCAN_TTOperationStatusTypeDef; + +/** + * @brief FDCAN Message RAM blocks + */ +typedef struct +{ + uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. + This parameter must be a 32-bit word address */ + + uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. + This parameter must be a 32-bit word address */ + + uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. + This parameter must be a 32-bit word address */ + + uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. + This parameter must be a 32-bit word address */ + + uint32_t RxBufferSA; /*!< Specifies the Rx Buffer Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TxBufferSA; /*!< Specifies the Tx Buffers Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TTMemorySA; /*!< Specifies the Trigger Memory Start Address. + This parameter must be a 32-bit word address */ + + uint32_t EndAddress; /*!< Specifies the End Address of the allocated RAM. + This parameter must be a 32-bit word address */ + +} FDCAN_MsgRamAddressTypeDef; + +/** + * @brief FDCAN handle structure definition + */ +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +typedef struct __FDCAN_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +{ + FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ + + TTCAN_TypeDef *ttcan; /*!< TT register base address */ + + FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ + + FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ + + uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index + of latest Tx FIFO/Queue request */ + + __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ + + HAL_LockTypeDef Lock; /*!< FDCAN locking object */ + + __IO uint32_t ErrorCode; /*!< FDCAN Error code */ + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< FDCAN Clock Calibration callback */ + void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */ + void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */ + void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */ + void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */ + void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */ + void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */ + void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Rx Buffer New Message callback */ + void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */ + void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */ + void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */ + void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */ + void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */ + void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< FDCAN T Schedule Synchronization callback */ + void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< FDCAN TT Time Mark callback */ + void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback */ + void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< FDCAN TT Global Time callback */ + + void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */ + void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +} FDCAN_HandleTypeDef; + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL FDCAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */ + HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */ + HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */ + HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */ + HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */ + HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */ + + HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */ + HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */ + +} HAL_FDCAN_CallbackIDTypeDef; + +/** + * @brief HAL FDCAN Callback pointer definition + */ +typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */ +typedef void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< pointer to Clock Calibration FDCAN callback function */ +typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */ +typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */ +typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */ +typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */ +typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */ +typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */ +typedef void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< pointer to TT Schedule Synchronization FDCAN callback function */ +typedef void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< pointer to TT Time Mark FDCAN callback function */ +typedef void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function */ +typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< pointer to TT Global Time FDCAN callback function */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants + * @{ + */ + +/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code + * @{ + */ +#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ +#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ +#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ +#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ +#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ +#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ +#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */ +#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ +#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ +#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ +#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ +#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ +#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE /*!< Global Time Error : Synchronization deviation exceeded limit */ +#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */ +#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */ +#define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1 /*!< Scheduling error 1 */ +#define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2 /*!< Scheduling error 2 */ +#define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT /*!< No system startup due to missing reference message */ +#define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT /*!< Missing reference message */ +#define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW /*!< Application watchdog not served in time */ +#define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER /*!< Error found in trigger list */ + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_format FDCAN Frame Format + * @{ + */ +#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ +#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ +#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ +/** + * @} + */ + +/** @defgroup FDCAN_operating_mode FDCAN Operating Mode + * @{ + */ +#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ +#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ +#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ +#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ +#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ +/** + * @} + */ + +/** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration + * @{ + */ +#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */ +#define FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U) /*!< Enable Clock Calibration */ +/** + * @} + */ + +/** @defgroup FDCAN_clock_divider FDCAN Clock Divider + * @{ + */ +#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ +#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */ +#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */ +#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */ +#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */ +#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */ +#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */ +#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */ +#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */ +#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */ +#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */ +#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */ +#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */ +#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */ +#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */ +#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */ +/** + * @} + */ + +/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length + * @{ + */ +#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U) /*!< Calibration field length is 32 bits */ +#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */ +/** + * @} + */ + +/** @defgroup FDCAN_calibration_state FDCAN Calibration State + * @{ + */ +#define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U) /*!< Clock not calibrated */ +#define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U) /*!< Clock basic calibrated */ +#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */ +/** + * @} + */ + +/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter + * @{ + */ +#define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U) /*!< Time Quanta Counter */ +#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */ +#define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter */ +/** + * @} + */ + +/** @defgroup FDCAN_data_field_size FDCAN Data Field Size + * @{ + */ +#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */ +#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */ +#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */ +#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */ +#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */ +#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */ +#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ +#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */ +/** + * @} + */ + +/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode + * @{ + */ +#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ +#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ +/** + * @} + */ + +/** @defgroup FDCAN_id_type FDCAN ID Type + * @{ + */ +#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ +#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_type FDCAN Frame Type + * @{ + */ +#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ +#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup FDCAN_data_length_code FDCAN Data Length Code + * @{ + */ +#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ +#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */ +#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */ +#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */ +#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */ +#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */ +#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */ +#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */ +#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */ +#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */ +#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */ +#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */ +#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */ +#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */ +#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ +#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */ +/** + * @} + */ + +/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator + * @{ + */ +#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ +#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ +/** + * @} + */ + +/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching + * @{ + */ +#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ +#define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ +/** + * @} + */ + +/** @defgroup FDCAN_format FDCAN format + * @{ + */ +#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ +#define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ +/** + * @} + */ + +/** @defgroup FDCAN_EFC FDCAN Event FIFO control + * @{ + */ +#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ +#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ +/** + * @} + */ + +/** @defgroup FDCAN_filter_type FDCAN Filter Type + * @{ + */ +#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ +#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ +#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ +#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ +/** + * @} + */ + +/** @defgroup FDCAN_filter_config FDCAN Filter Configuration + * @{ + */ +#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ +#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ +#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ +#define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ +#define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */ +/** + * @} + */ + +/** @defgroup FDCAN_Tx_location FDCAN Tx Location + * @{ + */ +#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ +#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ +#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ +#define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3 */ +#define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4 */ +#define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5 */ +#define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6 */ +#define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7 */ +#define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8 */ +#define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9 */ +#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */ +#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */ +#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */ +#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */ +#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */ +#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */ +#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */ +#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */ +#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */ +#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */ +#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */ +#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */ +#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */ +#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */ +#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */ +#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */ +#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */ +#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */ +#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */ +#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */ +#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */ +#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_location FDCAN Rx Location + * @{ + */ +#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ +#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ +#define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0 */ +#define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1 */ +#define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2 */ +#define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3 */ +#define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4 */ +#define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5 */ +#define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6 */ +#define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7 */ +#define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8 */ +#define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9 */ +#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */ +#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */ +#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */ +#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */ +#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */ +#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */ +#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */ +#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */ +#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */ +#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */ +#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */ +#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */ +#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */ +#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */ +#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */ +#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */ +#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */ +#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */ +#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */ +#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */ +#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */ +#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */ +#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */ +#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */ +#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */ +#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */ +#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */ +#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */ +#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */ +#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */ +#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */ +#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */ +#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */ +#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */ +#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */ +#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */ +#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */ +#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */ +#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */ +#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */ +#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */ +#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */ +#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */ +#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */ +#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */ +#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */ +#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */ +#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */ +#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */ +#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */ +#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */ +#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */ +#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */ +#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */ +/** + * @} + */ + +/** @defgroup FDCAN_event_type FDCAN Event Type + * @{ + */ +#define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ +#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ +/** + * @} + */ + +/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage + * @{ + */ +#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ +#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ +#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ +#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code + * @{ + */ +#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ +#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ +#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ +#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ +#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ +#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ +#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ +#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ +/** + * @} + */ + +/** @defgroup FDCAN_communication_state FDCAN communication state + * @{ + */ +#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ +#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ +#define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ +#define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ +/** + * @} + */ + +/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark + * @{ + */ +#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */ +#define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U) /*!< Rx FIFO0 */ +#define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U) /*!< Rx FIFO1 */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode + * @{ + */ +#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ +#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */ +/** + * @} + */ + +/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames + * @{ + */ +#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ +#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ +#define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ +/** + * @} + */ + +/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames + * @{ + */ +#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ +#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ +/** + * @} + */ + +/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line + * @{ + */ +#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ +#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_Timestamp FDCAN timestamp + * @{ + */ +#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ +#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ +/** + * @} + */ + +/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler + * @{ + */ +#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ +#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ +#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ +#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ +#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ +#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ +#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ +#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ +#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ +#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ +#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ +#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ +#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ +#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ +#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ +#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ +/** + * @} + */ + +/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation + * @{ + */ +#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ +#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ +#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ +#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload + * @{ + */ +#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U) /*!< Reference message has no additional payload */ +#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor + * @{ + */ +#define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles */ +#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle */ +#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle */ +#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle */ +#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */ +#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */ +#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type + * @{ + */ +#define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation */ +#define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation */ +#define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window */ +#define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window */ +#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window */ +#define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U) /*!< Start a merged arbitration window */ +#define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation */ +#define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation */ +#define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows */ +#define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration */ +#define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal + * @{ + */ +#define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ +#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external + * @{ + */ +#define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ +#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */ +/** + * @} + */ + +/** @defgroup FDCAN_operation_mode FDCAN Operation Mode + * @{ + */ +#define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */ +#define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */ +#define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_operation FDCAN TT Operation + * @{ + */ +#define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U) /*!< Strictly time-triggered operation */ +#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master + * @{ + */ +#define FDCAN_TT_SLAVE ((uint32_t)0x00000000U) /*!< Time slave */ +#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization + * @{ + */ +#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U) /*!< External clock synchronization in Level 0,2 disabled */ +#define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering + * @{ + */ +#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U) /*!< Global time filtering in Level 0,2 disabled */ +#define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration + * @{ + */ +#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U) /*!< Automatic clock calibration in Level 0,2 disabled */ +#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity + * @{ + */ +#define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U) /*!< Rising edge trigger */ +#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number + * @{ + */ +#define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync + * @{ + */ +#define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U) /*!< No sync pulse */ +#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */ +#define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection + * @{ + */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection + * @{ + */ +#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger */ +#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger */ +#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger */ +#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source + * @{ + */ +#define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U) /*!< Stop Watch disabled */ +#define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV) */ +#define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV) */ +#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity + * @{ + */ +#define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt */ +#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source + * @{ + */ +#define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated */ +#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time */ +#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time */ +#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level + * @{ + */ +#define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U) /*!< Severity 0 - No Error */ +#define FDCAN_TT_WARNING ((uint32_t)0x00000001U) /*!< Severity 1 - Warning */ +#define FDCAN_TT_ERROR ((uint32_t)0x00000002U) /*!< Severity 2 - Error */ +#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_master_state FDCAN TT Master State + * @{ + */ +#define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */ +#define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U) /*!< Operating as Time Slave */ +#define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master */ +#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State + * @{ + */ +#define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U) /*!< Out of Synchronization */ +#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */ +#define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap */ +#define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U) /*!< Synchronized to schedule */ +/** + * @} + */ + +/** @defgroup Interrupt_Masks Interrupt masks + * @{ + */ +#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */ +#define CCU_IR_MASK ((uint32_t)0xC0000000U) /*!< CCU interrupts mask */ +/** + * @} + */ + +/** @defgroup FDCAN_flags FDCAN Flags + * @{ + */ +#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ +#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ +#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ +#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ +#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX /*!< At least one received message stored into a Rx Buffer */ +#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ +#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ +#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW /*!< Tx Event FIFO fill level reached watermark */ +#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ +#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ +#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ +#define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W /*!< Rx FIFO 0 fill level reached watermark */ +#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ +#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ +#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ +#define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W /*!< Rx FIFO 1 fill level reached watermark */ +#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ +#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ +#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ +#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ +#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ +#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ +#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ +#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ +#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ +#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ +#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ +#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ +#define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed */ +#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred */ +/** + * @} + */ + +/** @defgroup FDCAN_Interrupts FDCAN Interrupts + * @{ + */ + +/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts + * @{ + */ +#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ +#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ +#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts + * @{ + */ +#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ +#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE /*!< At least one received message stored into a Rx Buffer */ +/** + * @} + */ + +/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts + * @{ + */ +#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ +#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ +/** + * @} + */ + +/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts + * @{ + */ +#define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed */ +#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */ +/** + * @} + */ + +/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts + * @{ + */ +#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ +#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ +#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */ +#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts + * @{ + */ +#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ +#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ +#define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */ +#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts + * @{ + */ +#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ +#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ +#define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */ +#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts + * @{ + */ +#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ +#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ +#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ +#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ +#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ +#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ +/** + * @} + */ + +/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts + * @{ + */ +#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ +#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ +#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FDCAN_TTflags FDCAN TT Flags + * @{ + */ +#define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC /*!< Start of Basic Cycle */ +#define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC /*!< Start of Matrix Cycle */ +#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM /*!< Change of Synchronization Mode */ +#define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG /*!< Start of Gap */ +#define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt */ +#define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */ +#define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE /*!< Stop Watch Event */ +#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW /*!< Global Time Wrap */ +#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD /*!< Global Time Discontinuity */ +#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE /*!< Global Time Error */ +#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow */ +#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow */ +#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1 /*!< Scheduling Error 1 */ +#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2 /*!< Scheduling Error 2 */ +#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC /*!< Error Level Changed */ +#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT /*!< Initialization Watch Trigger */ +#define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT /*!< Watch Trigger */ +#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW /*!< Application Watchdog */ +#define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER /*!< Configuration Error */ +/** + * @} + */ + +/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts + * @{ + */ + +/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts + * @{ + */ +#define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE /*!< Start of Basic Cycle */ +#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle */ +#define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */ +#define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE /*!< Start of Gap */ +/** + * @} + */ + +/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts + * @{ + */ +#define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt */ +#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */ +/** + * @} + */ + +/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt + * @{ + */ +#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */ +/** + * @} + */ + +/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts + * @{ + */ +#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE /*!< Global Time Wrap */ +#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE /*!< Global Time Discontinuity */ +/** + * @} + */ + +/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts + * @{ + */ +#define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE /*!< Global Time Error */ +#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow */ +#define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE /*!< Tx Count Overflow */ +#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1 */ +#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2 */ +#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */ +/** + * @} + */ + +/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts + * @{ + */ +#define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */ +#define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE /*!< Watch Trigger */ +#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE /*!< Application Watchdog */ +#define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE /*!< Configuration Error */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros + * @{ + */ + +/** @brief Reset FDCAN handle state. + * @param __HANDLE__ FDCAN handle. + * @retval None + */ +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @brief Enable the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \ + FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ + }while(0) + + +/** + * @brief Disable the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \ + FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ + }while(0) + +/** + * @brief Check whether the specified FDCAN interrupt is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be one of @arg FDCAN_Interrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \ + ((__HANDLE__)->Instance->IR &\ + (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__))) + +/** + * @brief Clear the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the interrupts to clear. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ + do { \ + ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \ + FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ + } while(0); + +/** + * @brief Check whether the specified FDCAN flag is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ FDCAN flag. + * This parameter can be one of @arg FDCAN_flags + * @retval FlagStatus + */ +#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? \ + ((__HANDLE__)->Instance->IR &\ + (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__))) + +/** + * @brief Clear the specified FDCAN flags. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ specifies the flags to clear. + * This parameter can be any combination of @arg FDCAN_flags + * @retval None + */ +#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + do { \ + ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \ + FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \ + } while(0); + +/** @brief Check if the specified FDCAN interrupt source is enabled or disabled. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. + * This parameter can be a value of @arg FDCAN_Interrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \ + ((__HANDLE__)->Instance->IE &\ + (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & \ + (__INTERRUPT__))) + +/** + * @brief Enable the specified FDCAN TT interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN TT interrupt. + * This parameter can be any combination of @arg FDCAN_TTInterrupts + * @retval None + */ +#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FDCAN TT interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN TT interrupt. + * This parameter can be any combination of @arg FDCAN_TTInterrupts + * @retval None + */ +#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified FDCAN TT interrupt is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN TT interrupt. + * This parameter can be one of @arg FDCAN_TTInterrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__)) + +/** + * @brief Clear the specified FDCAN TT interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the TT interrupts to clear. + * This parameter can be any combination of @arg FDCAN_TTInterrupts + * @retval None + */ +#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__)) + +/** + * @brief Check whether the specified FDCAN TT flag is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ FDCAN TT flag. + * This parameter can be one of @arg FDCAN_TTflags + * @retval FlagStatus + */ +#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__)) + +/** + * @brief Clear the specified FDCAN TT flags. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ specifies the TT flags to clear. + * This parameter can be any combination of @arg FDCAN_TTflags + * @retval None + */ +#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__)) + +/** @brief Check if the specified FDCAN TT interrupt source is enabled or disabled. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the FDCAN TT interrupt source to check. + * This parameter can be a value of @arg FDCAN_TTInterrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FDCAN_Exported_Functions + * @{ + */ + +/** @addtogroup FDCAN_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, + pFDCAN_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_ClockCalibrationCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxEventFifoCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo0CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo1CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferAbortCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_ErrorStatusCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TT_TimeMarkCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TT_StopWatchCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group2 + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, + const FDCAN_ClkCalUnitTypeDef *sCcuConfig); +uint32_t HAL_FDCAN_GetClockCalibrationState(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_GetClockCalibrationCounter(const FDCAN_HandleTypeDef *hfdcan, uint32_t Counter); +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, + uint32_t NonMatchingExt, uint32_t RejectRemoteStd, + uint32_t RejectRemoteExt); +HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); +HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); +HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark); +HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); +HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); +HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); +HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, + uint32_t TimeoutPeriod); +HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, + uint32_t TdcFilter); +HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group3 + * @{ + */ +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex); +HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, + FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); +HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_HpMsgStatusTypeDef *HpMsgStatus); +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus); +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters); +uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex); +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group4 + * @{ + */ +/* TT Configuration and control functions**************************************/ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TT_ConfigTypeDef *pTTParams); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, + uint32_t Payload); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TriggerTypeDef *sTriggerConfig); +HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset); +HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, + uint32_t TimeMarkValue, uint32_t RepeatFactor, + uint32_t StartCycle); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_TTOperationStatusTypeDef *TTOpStatus); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group5 + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, + uint32_t InterruptLine); +HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, + uint32_t BufferIndexes); +HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); +HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs); +HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs); +void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group6 + * @{ + */ +/* Callback functions *********************************************************/ +void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); +void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); +void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); +void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); +void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); +void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); +void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); +void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); +void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); +void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); +void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group7 + * @{ + */ +/* Peripheral State functions *************************************************/ +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan); +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Types FDCAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Variables FDCAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Constants FDCAN Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Macros FDCAN Private Macros + * @{ + */ +#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ + ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ + ((FORMAT) == FDCAN_FRAME_FD_BRS )) +#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ + ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ + ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ + ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ + ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) + +#define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \ + ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE )) + +#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV10) || \ + ((CKDIV) == FDCAN_CLOCK_DIV12) || \ + ((CKDIV) == FDCAN_CLOCK_DIV14) || \ + ((CKDIV) == FDCAN_CLOCK_DIV16) || \ + ((CKDIV) == FDCAN_CLOCK_DIV18) || \ + ((CKDIV) == FDCAN_CLOCK_DIV20) || \ + ((CKDIV) == FDCAN_CLOCK_DIV22) || \ + ((CKDIV) == FDCAN_CLOCK_DIV24) || \ + ((CKDIV) == FDCAN_CLOCK_DIV26) || \ + ((CKDIV) == FDCAN_CLOCK_DIV28) || \ + ((CKDIV) == FDCAN_CLOCK_DIV30)) +#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) +#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) +#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) +#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) +#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) +#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) +#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) +#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) +#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_)) +#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_)) +#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \ + ((SIZE) == FDCAN_DATA_BYTES_12) || \ + ((SIZE) == FDCAN_DATA_BYTES_16) || \ + ((SIZE) == FDCAN_DATA_BYTES_20) || \ + ((SIZE) == FDCAN_DATA_BYTES_24) || \ + ((SIZE) == FDCAN_DATA_BYTES_32) || \ + ((SIZE) == FDCAN_DATA_BYTES_48) || \ + ((SIZE) == FDCAN_DATA_BYTES_64)) +#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ + ((MODE) == FDCAN_TX_QUEUE_OPERATION)) +#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ + ((ID_TYPE) == FDCAN_EXTENDED_ID)) +#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ + ((CONFIG) == FDCAN_FILTER_REJECT ) || \ + ((CONFIG) == FDCAN_FILTER_HP ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER )) +#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \ + ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \ + ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \ + ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \ + ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \ + ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \ + ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \ + ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \ + ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \ + ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \ + ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31)) +#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ + ((FIFO) == FDCAN_RX_FIFO1)) +#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ + ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) +#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ + ((TYPE) == FDCAN_FILTER_DUAL ) || \ + ((TYPE) == FDCAN_FILTER_MASK )) +#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ + ((TYPE) == FDCAN_FILTER_DUAL ) || \ + ((TYPE) == FDCAN_FILTER_MASK ) || \ + ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) +#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ + ((TYPE) == FDCAN_REMOTE_FRAME)) +#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ + ((DLC) == FDCAN_DLC_BYTES_1 ) || \ + ((DLC) == FDCAN_DLC_BYTES_2 ) || \ + ((DLC) == FDCAN_DLC_BYTES_3 ) || \ + ((DLC) == FDCAN_DLC_BYTES_4 ) || \ + ((DLC) == FDCAN_DLC_BYTES_5 ) || \ + ((DLC) == FDCAN_DLC_BYTES_6 ) || \ + ((DLC) == FDCAN_DLC_BYTES_7 ) || \ + ((DLC) == FDCAN_DLC_BYTES_8 ) || \ + ((DLC) == FDCAN_DLC_BYTES_12) || \ + ((DLC) == FDCAN_DLC_BYTES_16) || \ + ((DLC) == FDCAN_DLC_BYTES_20) || \ + ((DLC) == FDCAN_DLC_BYTES_24) || \ + ((DLC) == FDCAN_DLC_BYTES_32) || \ + ((DLC) == FDCAN_DLC_BYTES_48) || \ + ((DLC) == FDCAN_DLC_BYTES_64)) +#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ + ((ESI) == FDCAN_ESI_PASSIVE)) +#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ + ((BRS) == FDCAN_BRS_ON )) +#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ + ((FDF) == FDCAN_FD_CAN )) +#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ + ((EFC) == FDCAN_STORE_TX_EVENTS)) +#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U) +#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U) +#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \ + ((FIFO) == FDCAN_CFG_RX_FIFO0 ) || \ + ((FIFO) == FDCAN_CFG_RX_FIFO1 )) +#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ + ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ + ((DESTINATION) == FDCAN_REJECT )) +#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ + ((DESTINATION) == FDCAN_REJECT_REMOTE)) +#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ + ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) +#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ + ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) +#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) +#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ + ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ + ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ + ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) +#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \ + ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64)) +#define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \ + ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \ + ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER )) +#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \ + ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD)) +#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE ) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE)) +#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \ + ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP ) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE ) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED ) || \ + ((TYPE) == FDCAN_TT_WATCH_TRIGGER ) || \ + ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP ) || \ + ((TYPE) == FDCAN_TT_RX_TRIGGER ) || \ + ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER ) || \ + ((TYPE) == FDCAN_TT_END_OF_LIST )) +#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \ + ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT)) +#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \ + ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT)) +#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \ + ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \ + ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 )) +#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION ) || \ + ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION)) +#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE ) || \ + ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER)) +#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \ + ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE )) +#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \ + ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE )) +#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \ + ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE )) +#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \ + ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING)) +#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64)) +#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE ) || \ + ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \ + ((SYNC) == FDCAN_TT_SYNC_MATRIX_START )) +#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U)) +#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU)) +#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU)) +#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC))) +#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC))) +#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \ + ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \ + ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \ + ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3)) +#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \ + ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \ + ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \ + ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3)) +#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U)) +#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED ) || \ + ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \ + ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \ + ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME)) +#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \ + ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING)) +#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \ + ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \ + ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \ + ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME)) + +#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Functions FDCAN Private Functions + * @{ + */ + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ +#endif /* FDCAN1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_FDCAN_H */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h new file mode 100644 index 0000000..a4773b5 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h @@ -0,0 +1,861 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_FLASH_H +#define STM32H7xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_SECTERASE_BANK1, + FLASH_PROC_MASSERASE_BANK1, + FLASH_PROC_PROGRAM_BANK1, + FLASH_PROC_SECTERASE_BANK2, + FLASH_PROC_MASSERASE_BANK2, + FLASH_PROC_PROGRAM_BANK2, + FLASH_PROC_ALLBANK_MASSERASE +} FLASH_ProcedureTypeDef; + + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t NbSectorsToErase; /*!< Internal variable to save the remaining sectors to erase in IT context */ + + __IO uint32_t VoltageForErase; /*!< Internal variable to provide voltage range selected by user in IT context */ + + __IO uint32_t Sector; /*!< Internal variable to define the current sector which is erasing */ + + __IO uint32_t Address; /*!< Internal variable to save address selected for program */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code */ + +}FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Code FLASH Error Code + * @brief FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ + +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */ +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */ +#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */ +#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */ +#if defined (FLASH_SR_OPERR) +#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */ +#endif /* FLASH_SR_OPERR */ +#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */ +#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */ +#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */ +#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */ +#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */ + +#define HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1 /*!< Write Protection Error on Bank 1 */ +#define HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1 /*!< Program Sequence Error on Bank 1 */ +#define HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1 /*!< Strobe Error on Bank 1 */ +#define HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1 /*!< Inconsistency Error on Bank 1 */ +#if defined (FLASH_SR_OPERR) +#define HAL_FLASH_ERROR_OPE_BANK1 FLASH_FLAG_OPERR_BANK1 /*!< Operation Error on Bank 1 */ +#endif /* FLASH_SR_OPERR */ +#define HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1 /*!< Read Protection Error on Bank 1 */ +#define HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1 /*!< Read Secured Error on Bank 1 */ +#define HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */ +#define HAL_FLASH_ERROR_DBECC_BANK1 FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1 */ +#define HAL_FLASH_ERROR_CRCRD_BANK1 FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1 */ + +#define HAL_FLASH_ERROR_WRP_BANK2 FLASH_FLAG_WRPERR_BANK2 /*!< Write Protection Error on Bank 2 */ +#define HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2 /*!< Program Sequence Error on Bank 2 */ +#define HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2 /*!< Strobe Error on Bank 2 */ +#define HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2 /*!< Inconsistency Error on Bank 2 */ +#if defined (FLASH_SR_OPERR) +#define HAL_FLASH_ERROR_OPE_BANK2 FLASH_FLAG_OPERR_BANK2 /*!< Operation Error on Bank 2 */ +#endif /* FLASH_SR_OPERR */ +#define HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2 /*!< Read Protection Error on Bank 2 */ +#define HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2 /*!< Read Secured Error on Bank 2 */ +#define HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2 /*!< ECC Single Correction Error on Bank 2 */ +#define HAL_FLASH_ERROR_DBECC_BANK2 FLASH_FLAG_DBECCERR_BANK2 /*!< ECC Double Detection Error on Bank 2 */ +#define HAL_FLASH_ERROR_CRCRD_BANK2 FLASH_FLAG_CRCRDERR_BANK2 /*!< CRC Read Error on Bank2 */ + +#define HAL_FLASH_ERROR_OB_CHANGE FLASH_OPTSR_OPTCHANGEERR /*!< Option Byte Change Error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word at a specified address */ +#if defined (FLASH_OPTCR_PG_OTP) +#define FLASH_TYPEPROGRAM_OTPWORD 0x02U /*!< Program an OTP word at a specified address */ +#endif /* FLASH_OPTCR_PG_OTP */ +/** + * @} + */ + +/** @defgroup FLASH_Flag_definition FLASH Flag definition + * @brief Flag definition + * @{ + */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_WBNE FLASH_SR_WBNE /*!< Write Buffer Not Empty flag */ +#define FLASH_FLAG_QW FLASH_SR_QW /*!< Wait Queue on flag */ +#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC Busy flag */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< End Of Program on flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write Protection Error on flag */ +#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Program Sequence Error on flag */ +#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< Strobe Error flag */ +#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency Error on flag */ +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< Operation Error on flag */ +#endif /* FLASH_SR_OPERR */ +#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR /*!< Read Protection Error on flag */ +#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR /*!< Read Secured Error on flag */ +#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on flag */ +#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on flag */ +#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC End of Calculation flag */ +#define FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR /*!< CRC Read Error on bank flag */ + +#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank 1 Busy flag */ +#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Write Buffer Not Empty on Bank 1 flag */ +#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Wait Queue on Bank 1 flag */ +#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC Busy on Bank 1 flag */ +#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< End Of Program on Bank 1 flag */ +#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR /*!< Write Protection Error on Bank 1 flag */ +#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR /*!< Program Sequence Error on Bank 1 flag */ +#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< Strobe Error on Bank 1 flag */ +#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR /*!< Inconsistency Error on Bank 1 flag */ +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR /*!< Operation Error on Bank 1 flag */ +#endif /* FLASH_SR_OPERR */ +#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR /*!< Read Protection Error on Bank 1 flag */ +#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR /*!< Read Secured Error on Bank 1 flag */ +#define FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR /*!< Single ECC Error Correction on Bank 1 flag */ +#define FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR /*!< Double Detection ECC Error on Bank 1 flag */ +#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC End of Calculation on Bank 1 flag */ +#define FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR /*!< CRC Read error on Bank 1 flag */ + +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \ + FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \ + FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | \ + FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCERR_BANK1 | \ + FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */ +#else +#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \ + FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \ + FLASH_FLAG_RDPERR_BANK1 | FLASH_FLAG_RDSERR_BANK1 | \ + FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \ + FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */ +#endif /* FLASH_SR_OPERR */ + +#define FLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | \ + FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | \ + FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | \ + FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */ + +#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) /*!< FLASH Bank 2 Busy flag */ +#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Write Buffer Not Empty on Bank 2 flag */ +#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Wait Queue on Bank 2 flag */ +#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC Busy on Bank 2 flag */ +#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) /*!< End Of Program on Bank 2 flag */ +#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) /*!< Write Protection Error on Bank 2 flag */ +#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) /*!< Program Sequence Error on Bank 2 flag */ +#define FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U) /*!< Strobe Error on Bank 2 flag */ +#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) /*!< Inconsistency Error on Bank 2 flag */ +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) /*!< Operation Error on Bank 2 flag */ +#endif /* FLASH_SR_OPERR */ +#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) /*!< Read Protection Error on Bank 2 flag */ +#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) /*!< Read Secured Error on Bank 2 flag */ +#define FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 flag */ +#define FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 flag */ +#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC End of Calculation on Bank 2 flag */ +#define FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U) /*!< CRC Read error on Bank 2 flag */ + +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \ + FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \ + FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | \ + FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCERR_BANK2 | \ + FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */ +#else +#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \ + FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \ + FLASH_FLAG_RDPERR_BANK2 | FLASH_FLAG_RDSERR_BANK2 | \ + FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \ + FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */ +#endif /* FLASH_SR_OPERR */ + +#define FLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | \ + FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | \ + FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | \ + FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Bank 1 Operation Interrupt source */ +#define FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE /*!< Write Protection Error on Bank 1 Interrupt source */ +#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE /*!< Program Sequence Error on Bank 1 Interrupt source */ +#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE /*!< Strobe Error on Bank 1 Interrupt source */ +#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE /*!< Inconsistency Error on Bank 1 Interrupt source */ +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE /*!< Operation Error on Bank 1 Interrupt source */ +#endif /* FLASH_CR_OPERRIE */ +#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE /*!< Read protection Error on Bank 1 Interrupt source */ +#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE /*!< Read Secured Error on Bank 1 Interrupt source */ +#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE /*!< Single ECC Error Correction on Bank 1 Interrupt source */ +#define FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE /*!< Double Detection ECC Error on Bank 1 Interrupt source */ +#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE /*!< CRC End on Bank 1 Interrupt source */ +#define FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE /*!< CRC Read error on Bank 1 Interrupt source */ + +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \ + FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \ + FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | \ + FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | \ + FLASH_IT_SNECCERR_BANK1 | FLASH_IT_DBECCERR_BANK1 | \ + FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */ +#else +#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \ + FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \ + FLASH_IT_INCERR_BANK1 | FLASH_IT_RDPERR_BANK1 | \ + FLASH_IT_RDSERR_BANK1 | FLASH_IT_SNECCERR_BANK1 | \ + FLASH_IT_DBECCERR_BANK1 | FLASH_IT_CRCEND_BANK1 | \ + FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */ +#endif /* FLASH_CR_OPERRIE */ + +#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) /*!< End of FLASH Bank 2 Operation Interrupt source */ +#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) /*!< Write Protection Error on Bank 2 Interrupt source */ +#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) /*!< Program Sequence Error on Bank 2 Interrupt source */ +#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) /*!< Strobe Error on Bank 2 Interrupt source */ +#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) /*!< Inconsistency Error on Bank 2 Interrupt source */ +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) /*!< Operation Error on Bank 2 Interrupt source */ +#endif /* FLASH_CR_OPERRIE */ +#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) /*!< Read protection Error on Bank 2 Interrupt source */ +#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) /*!< Read Secured Error on Bank 2 Interrupt source */ +#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 Interrupt source */ +#define FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 Interrupt source */ +#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) /*!< CRC End on Bank 2 Interrupt source */ +#define FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U) /*!< CRC Read Error on Bank 2 Interrupt source */ + +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \ + FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \ + FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2 | \ + FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK2 | \ + FLASH_IT_SNECCERR_BANK2 | FLASH_IT_DBECCERR_BANK2 | \ + FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */ +#else +#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \ + FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \ + FLASH_IT_INCERR_BANK2 | FLASH_IT_RDPERR_BANK2 | \ + FLASH_IT_RDSERR_BANK2 | FLASH_IT_SNECCERR_BANK2 | \ + FLASH_IT_DBECCERR_BANK2 | FLASH_IT_CRCEND_BANK2 | \ + FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */ +#endif /* FLASH_CR_OPERRIE */ +/** + * @} + */ + +#if defined (FLASH_CR_PSIZE) +/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE 0x00000000U /*!< Flash program/erase by 8 bits */ +#define FLASH_PSIZE_HALF_WORD FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */ +#define FLASH_PSIZE_WORD FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */ +#define FLASH_PSIZE_DOUBLE_WORD FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */ +/** + * @} + */ +#endif /* FLASH_CR_PSIZE */ + + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 0x45670123U +#define FLASH_KEY2 0xCDEF89ABU +#define FLASH_OPT_KEY1 0x08192A3BU +#define FLASH_OPT_KEY2 0x4C5D6E7FU +/** + * @} + */ + +/** @defgroup FLASH_Sectors FLASH Sectors + * @{ + */ +#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */ +#if (FLASH_SECTOR_TOTAL == 128) +#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 16U /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 17U /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 18U /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 19U /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 20U /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 21U /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 22U /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 23U /*!< Sector Number 23 */ +#define FLASH_SECTOR_24 24U /*!< Sector Number 24 */ +#define FLASH_SECTOR_25 25U /*!< Sector Number 25 */ +#define FLASH_SECTOR_26 26U /*!< Sector Number 26 */ +#define FLASH_SECTOR_27 27U /*!< Sector Number 27 */ +#define FLASH_SECTOR_28 28U /*!< Sector Number 28 */ +#define FLASH_SECTOR_29 29U /*!< Sector Number 29 */ +#define FLASH_SECTOR_30 30U /*!< Sector Number 30 */ +#define FLASH_SECTOR_31 31U /*!< Sector Number 31 */ +#define FLASH_SECTOR_32 32U /*!< Sector Number 32 */ +#define FLASH_SECTOR_33 33U /*!< Sector Number 33 */ +#define FLASH_SECTOR_34 34U /*!< Sector Number 34 */ +#define FLASH_SECTOR_35 35U /*!< Sector Number 35 */ +#define FLASH_SECTOR_36 36U /*!< Sector Number 36 */ +#define FLASH_SECTOR_37 37U /*!< Sector Number 37 */ +#define FLASH_SECTOR_38 38U /*!< Sector Number 38 */ +#define FLASH_SECTOR_39 39U /*!< Sector Number 39 */ +#define FLASH_SECTOR_40 40U /*!< Sector Number 40 */ +#define FLASH_SECTOR_41 41U /*!< Sector Number 41 */ +#define FLASH_SECTOR_42 42U /*!< Sector Number 42 */ +#define FLASH_SECTOR_43 43U /*!< Sector Number 43 */ +#define FLASH_SECTOR_44 44U /*!< Sector Number 44 */ +#define FLASH_SECTOR_45 45U /*!< Sector Number 45 */ +#define FLASH_SECTOR_46 46U /*!< Sector Number 46 */ +#define FLASH_SECTOR_47 47U /*!< Sector Number 47 */ +#define FLASH_SECTOR_48 48U /*!< Sector Number 48 */ +#define FLASH_SECTOR_49 49U /*!< Sector Number 49 */ +#define FLASH_SECTOR_50 50U /*!< Sector Number 50 */ +#define FLASH_SECTOR_51 51U /*!< Sector Number 51 */ +#define FLASH_SECTOR_52 52U /*!< Sector Number 52 */ +#define FLASH_SECTOR_53 53U /*!< Sector Number 53 */ +#define FLASH_SECTOR_54 54U /*!< Sector Number 54 */ +#define FLASH_SECTOR_55 55U /*!< Sector Number 55 */ +#define FLASH_SECTOR_56 56U /*!< Sector Number 56 */ +#define FLASH_SECTOR_57 57U /*!< Sector Number 57 */ +#define FLASH_SECTOR_58 58U /*!< Sector Number 58 */ +#define FLASH_SECTOR_59 59U /*!< Sector Number 59 */ +#define FLASH_SECTOR_60 60U /*!< Sector Number 60 */ +#define FLASH_SECTOR_61 61U /*!< Sector Number 61 */ +#define FLASH_SECTOR_62 62U /*!< Sector Number 62 */ +#define FLASH_SECTOR_63 63U /*!< Sector Number 63 */ +#define FLASH_SECTOR_64 64U /*!< Sector Number 64 */ +#define FLASH_SECTOR_65 65U /*!< Sector Number 65 */ +#define FLASH_SECTOR_66 66U /*!< Sector Number 66 */ +#define FLASH_SECTOR_67 67U /*!< Sector Number 67 */ +#define FLASH_SECTOR_68 68U /*!< Sector Number 68 */ +#define FLASH_SECTOR_69 69U /*!< Sector Number 69 */ +#define FLASH_SECTOR_70 70U /*!< Sector Number 70 */ +#define FLASH_SECTOR_71 71U /*!< Sector Number 71 */ +#define FLASH_SECTOR_72 72U /*!< Sector Number 72 */ +#define FLASH_SECTOR_73 73U /*!< Sector Number 73 */ +#define FLASH_SECTOR_74 74U /*!< Sector Number 74 */ +#define FLASH_SECTOR_75 75U /*!< Sector Number 75 */ +#define FLASH_SECTOR_76 76U /*!< Sector Number 76 */ +#define FLASH_SECTOR_77 77U /*!< Sector Number 77 */ +#define FLASH_SECTOR_78 78U /*!< Sector Number 78 */ +#define FLASH_SECTOR_79 79U /*!< Sector Number 79 */ +#define FLASH_SECTOR_80 80U /*!< Sector Number 80 */ +#define FLASH_SECTOR_81 81U /*!< Sector Number 81 */ +#define FLASH_SECTOR_82 82U /*!< Sector Number 82 */ +#define FLASH_SECTOR_83 83U /*!< Sector Number 83 */ +#define FLASH_SECTOR_84 84U /*!< Sector Number 84 */ +#define FLASH_SECTOR_85 85U /*!< Sector Number 85 */ +#define FLASH_SECTOR_86 86U /*!< Sector Number 86 */ +#define FLASH_SECTOR_87 87U /*!< Sector Number 87 */ +#define FLASH_SECTOR_88 88U /*!< Sector Number 88 */ +#define FLASH_SECTOR_89 89U /*!< Sector Number 89 */ +#define FLASH_SECTOR_90 90U /*!< Sector Number 90 */ +#define FLASH_SECTOR_91 91U /*!< Sector Number 91 */ +#define FLASH_SECTOR_92 92U /*!< Sector Number 92 */ +#define FLASH_SECTOR_93 93U /*!< Sector Number 93 */ +#define FLASH_SECTOR_94 94U /*!< Sector Number 94 */ +#define FLASH_SECTOR_95 95U /*!< Sector Number 95 */ +#define FLASH_SECTOR_96 96U /*!< Sector Number 96 */ +#define FLASH_SECTOR_97 97U /*!< Sector Number 97 */ +#define FLASH_SECTOR_98 98U /*!< Sector Number 98 */ +#define FLASH_SECTOR_99 99U /*!< Sector Number 99 */ +#define FLASH_SECTOR_100 100U /*!< Sector Number 100 */ +#define FLASH_SECTOR_101 101U /*!< Sector Number 101 */ +#define FLASH_SECTOR_102 102U /*!< Sector Number 102 */ +#define FLASH_SECTOR_103 103U /*!< Sector Number 103 */ +#define FLASH_SECTOR_104 104U /*!< Sector Number 104 */ +#define FLASH_SECTOR_105 105U /*!< Sector Number 105 */ +#define FLASH_SECTOR_106 106U /*!< Sector Number 106 */ +#define FLASH_SECTOR_107 107U /*!< Sector Number 107 */ +#define FLASH_SECTOR_108 108U /*!< Sector Number 108 */ +#define FLASH_SECTOR_109 109U /*!< Sector Number 109 */ +#define FLASH_SECTOR_110 110U /*!< Sector Number 110 */ +#define FLASH_SECTOR_111 111U /*!< Sector Number 111 */ +#define FLASH_SECTOR_112 112U /*!< Sector Number 112 */ +#define FLASH_SECTOR_113 113U /*!< Sector Number 113 */ +#define FLASH_SECTOR_114 114U /*!< Sector Number 114 */ +#define FLASH_SECTOR_115 115U /*!< Sector Number 115 */ +#define FLASH_SECTOR_116 116U /*!< Sector Number 116 */ +#define FLASH_SECTOR_117 117U /*!< Sector Number 117 */ +#define FLASH_SECTOR_118 118U /*!< Sector Number 118 */ +#define FLASH_SECTOR_119 119U /*!< Sector Number 119 */ +#define FLASH_SECTOR_120 120U /*!< Sector Number 120 */ +#define FLASH_SECTOR_121 121U /*!< Sector Number 121 */ +#define FLASH_SECTOR_122 122U /*!< Sector Number 122 */ +#define FLASH_SECTOR_123 123U /*!< Sector Number 123 */ +#define FLASH_SECTOR_124 124U /*!< Sector Number 124 */ +#define FLASH_SECTOR_125 125U /*!< Sector Number 125 */ +#define FLASH_SECTOR_126 126U /*!< Sector Number 126 */ +#define FLASH_SECTOR_127 127U /*!< Sector Number 127 */ +#endif /* FLASH_SECTOR_TOTAL == 128 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__: FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * In case of Bank 1 This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source + * @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source + * @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source + * @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source + * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source + * @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources + * + * In case of Bank 2, this parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source + * @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source + * @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source + * @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source + * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source + * @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources + * @retval none + */ + +#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__)) + +#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU)) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \ + __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \ + __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)) +#else +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) +#endif /* DUAL_BANK */ + + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * In case of Bank 1 This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source + * @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source + * @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source + * @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source + * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source + * @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources + * + * In case of Bank 2, this parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source + * @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source + * @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source + * @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source + * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source + * @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources + * @retval none + */ + +#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__)) + +#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU)) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \ + __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \ + __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)) +#else +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) +#endif /* DUAL_BANK */ + + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param __FLAG__: specifies the FLASH flag to check. + * In case of Bank 1 This parameter can be one of the following values : + * @arg FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag + * @arg FLASH_FLAG_WBNE_BANK1 : Write Buffer Not Empty on Bank 1 flag + * @arg FLASH_FLAG_QW_BANK1 : Wait Queue on Bank 1 flag + * @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag + * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag + * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag + * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag + * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag + * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag + * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag + * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag + * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag + * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag + * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag + * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag + * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag + * + * In case of Bank 2 This parameter can be one of the following values : + * @arg FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag + * @arg FLASH_FLAG_WBNE_BANK2 : Write Buffer Not Empty on Bank 2 flag + * @arg FLASH_FLAG_QW_BANK2 : Wait Queue on Bank 2 flag + * @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag + * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag + * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag + * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag + * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag + * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag + * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag + * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag + * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag + * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag + * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag + * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag + * @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__)) + +#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU))) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \ + __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)) +#else +#define __HAL_FLASH_GET_FLAG(__FLAG__) __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) +#endif /* DUAL_BANK */ + + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__: specifies the FLASH flags to clear. + * In case of Bank 1, this parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag + * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag + * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag + * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag + * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag + * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag + * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag + * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag + * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag + * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag + * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag + * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag + * @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags + * @arg FLASH_FLAG_ALL_BANK1 : All Bank 1 flags + * + * In case of Bank 2, this parameter can be any combination of the following values : + * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag + * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag + * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag + * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag + * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag + * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag + * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag + * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag + * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag + * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag + * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag + * @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag + * @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags + * @arg FLASH_FLAG_ALL_BANK2 : All Bank 2 flags + * @retval none + */ + +#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__)) + +#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU)) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \ + __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)) +#else +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) +#endif /* DUAL_BANK */ + +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32h7xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* Program operation functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD)) +#else +#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) +#endif /* FLASH_OPTCR_PG_OTP */ + +#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT)) +#if defined (DUAL_BANK) +#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT)) +#endif /* DUAL_BANK */ + +#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG)) +#if defined (DUAL_BANK) +#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG)) +#endif /* DUAL_BANK */ + +#if defined (DUAL_BANK) +#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE)) +#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END)) +#else +#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) <= FLASH_END)) +#endif /* DUAL_BANK */ + +#if defined (DUAL_BANK) +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)) +#else +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS)) +#endif /* FLASH_OPTCR_PG_OTP */ +#else +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)) +#else +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS)) +#endif /* FLASH_OPTCR_PG_OTP */ +#endif /* DUAL_BANK */ + +#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U)) + +#if defined (DUAL_BANK) +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2)) +#else +#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) +#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) +#endif /* DUAL_BANK */ + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank); +HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout); +HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_FLASH_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h new file mode 100644 index 0000000..1ca4e72 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h @@ -0,0 +1,1071 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_FLASH_EX_H +#define STM32H7xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter must be a value of @ref FLASH_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism + This parameter must be a value of @ref FLASHEx_Voltage_Range */ + +} FLASH_EraseInitTypeDef; + + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + + uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASHEx_OB_USER_Type */ + + uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY / + IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */ + + uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config . + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not + when RDP level decreased from Level 1 to Level 0 or during a mass erase. + This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */ + + uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). + This parameter must be a value between begin and end of a bank */ + + uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). + This parameter must be a value between PCROP Start address and end of a bank */ + + uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 + or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ + + uint32_t BootAddr0; /*!< Boot Address 0. + This parameter must be a value between begin and end of a bank */ + + uint32_t BootAddr1; /*!< Boot Address 1. + This parameter must be a value between begin and end of a bank */ +#if defined(DUAL_CORE) + uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1 + or both. + This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ + + uint32_t CM4BootAddr0; /*!< CM4 Boot Address 0. + This parameter must be a value between begin and end of a bank */ + + uint32_t CM4BootAddr1; /*!< CM4 Boot Address 1. + This parameter must be a value between begin and end of a bank */ +#endif /*DUAL_CORE*/ + + uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not + when RDP level decreased from Level 1 to Level 0 or during a mass erase. + This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */ + + uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address. + This parameter must be a value between begin address and end address of bank1 */ + + uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address. + This parameter must be a value between Secure Area Start address and end address of a bank1 */ + +#if defined (FLASH_OTPBL_LOCKBL) + uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked. + This parameter must be a value of @ref FLASHEx_OTP_Blocks */ +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + uint32_t SharedRamConfig; /*!< Specifies the configuration of TCM / AXI shared RAM. + This parameter must be a value of @ref FLASHEx_OB_TCM_AXI_SHARED */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + uint32_t FreqBoostState; /*!< Specifies the state of CPU Frequency Boost. + This parameter must be a value of @ref FLASHEx_OB_CPUFREQ_BOOST */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeCRC; /*!< CRC Selection Type. + This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */ + + uint32_t BurstSize; /*!< CRC Burst Size. + This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */ + + uint32_t Bank; /*!< Select bank where CRC computation is enabled. + This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */ + + uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation + This parameter must be a value of @ref FLASH_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be computed. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t CRCStartAddr; /*!< CRC Start address. + This parameter must be a value between begin address and end address of a bank */ + + uint32_t CRCEndAddr; /*!< CRC End address. + This parameter must be a value between CRC Start address and end address of a bank */ + +} FLASH_CRCInitTypeDef; + +#if (USE_FLASH_ECC == 1U) +/** + * @brief ECC Info Structure definition + */ +typedef struct +{ + uint32_t Area; /*!< Area from which an ECC was detected. + This parameter can be a value of @ref FLASHEx_ECC_Area */ + + uint32_t Address; /*!< ECC error address */ + +} FLASH_EccInfoTypeDef; +#endif /* USE_FLASH_ECC */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE 0x01U /*!< Flash Mass erase activation */ +/** + * @} + */ + +#if defined (FLASH_CR_PSIZE) +/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range + * @{ + */ +#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */ +#define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */ +#define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */ +#define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */ +/** + * @} + */ +#endif /* FLASH_CR_PSIZE */ + +/** @defgroup FLASHEx_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ +/** + * @} + */ + +#if (USE_FLASH_ECC == 1U) +/** @defgroup FLASH_ECC_Area FLASH ECC Area + * @brief FLASH ECC Area + * @{ + */ +#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */ +#define FLASH_ECC_AREA_USER_BANK2 0x00000001U /*!< FLASH bank 2 area */ +/** + * @} + */ +#endif /* USE_FLASH_ECC */ + +/** @defgroup FLASHEx_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */ +#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */ +#define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */ +#define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */ +#if defined (DUAL_CORE) +#define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */ +#define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */ +#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */ +#else /* Single core */ +#define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */ +#endif /*DUAL_CORE*/ +#if defined (FLASH_OTPBL_LOCKBL) +#define OPTIONBYTE_OTP_LOCK 0x80U /*!< OTP Lock option byte configuration */ +#endif /* FLASH_OTPBL_LOCKBL */ +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OPTIONBYTE_SHARED_RAM 0x100U /*!< TCM / AXI Shared RAM option byte configuration */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +#define OPTIONBYTE_FREQ_BOOST 0x200U /*!< CPU Frequency Boost option byte configuration */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#if defined (DUAL_CORE) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD) /*!< All option byte configuration */ +#elif defined (FLASH_OTPBL_LOCKBL) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK) /*!< All option byte configuration */ +#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST) /*!< All option byte configuration */ +#else +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD) /*!< All option byte configuration */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 0xAA00U +#define OB_RDP_LEVEL_1 0x5500U +#define OB_RDP_LEVEL_2 0xCC00U /*!< Warning: When enabling read protection level 2 + it s no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog + * @{ + */ +#define OB_IWDG_SW OB_IWDG1_SW /*!< Software IWDG selected */ +#define OB_IWDG_HW OB_IWDG1_HW /*!< Hardware IWDG selected */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST 0x00U /*!< Reset generated when entering in STOP */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST 0x00U /*!< Reset generated when entering in STANDBY */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP + * @{ + */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */ +#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY + * @{ + */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */ +#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */ +#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */ +#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */ +/** + * @} + */ + + + +/** @defgroup FLASHEx_Boot_Address FLASH Boot Address + * @{ + */ +#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */ +#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */ +#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */ +#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */ +#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */ +#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */ +#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ +#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ +#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ +#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ +#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ +#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ +#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ + +/* Unused FLASH Latency defines */ +#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */ +#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */ +#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ +#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ +#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ +#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ +#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ +#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ +/** + * @} + */ + +/** @defgroup FLASHEx_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 0x01U /*!< Bank 1 */ +#if defined (DUAL_BANK) +#define FLASH_BANK_2 0x02U /*!< Bank 2 */ +#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ +#endif /* DUAL_BANK */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP + * @{ + */ +#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level + is decreased from Level 1 to Level 0 or during a mass erase */ +#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is + decreased from Level 1 to Level 0 (full mass erase) */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#if (FLASH_SECTOR_TOTAL == 128) +#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ +#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ +#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ +#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ +#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ +#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ +#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ +#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ +#define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */ +#define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */ +#define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */ +#define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */ +#define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */ +#define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */ +#define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */ +#define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */ +#define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */ +#define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */ +#define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */ +#define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */ +#define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */ +#define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */ +#define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */ +#define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */ +#define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */ +#define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */ +#define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */ +#define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */ +#define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */ +#define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */ +#define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ +#define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ +#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ +#else +#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ +#endif /* FLASH_SECTOR_TOTAL == 128 */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY + * @{ + */ +#define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */ +#define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY /*!< security disabled */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE + * @{ + */ +#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7 + * @{ + */ +#define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */ +#define OB_BCM7_ENABLE FLASH_OPTSR_BCM7 /*!< CM7 Boot enabled */ + +/** + * @} + */ + +/** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4 + * @{ + */ +#define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */ +#define OB_BCM4_ENABLE FLASH_OPTSR_BCM4 /*!< CM4 Boot enabled */ +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW + * @{ + */ +#define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */ +#define OB_IWDG1_HW 0x00000000U /*!< Software independent watchdog 1 */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW + * @{ + */ +#define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/ +#define OB_IWDG2_HW 0x00000000U /*!< Software independent watchdog 2*/ +/** + * @} + */ +#endif + +/** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1 + * @{ + */ +#define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */ +#define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1 + * @{ + */ +#define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */ +#define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */ +/** + * @} + */ + +#if defined (FLASH_OPTSR_NRST_STOP_D2) +/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2 + * @{ + */ +#define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */ +#define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2 + * @{ + */ +#define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */ +#define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */ +/** + * @} + */ +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_BANK) +/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK + * @{ + */ +#define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ +#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */ +/** + * @} + */ +#endif /* DUAL_BANK */ + +/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV + * @{ + */ +#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */ +#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */ +/** + * @} + */ + +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV + * @{ + */ +#define OB_VDDMMC_HSLV_DISABLE 0x00000000U /*!< VDDMMC HSLV disabled */ +#define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */ +/** + * @} + */ +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +/** @defgroup FLASHEx_OB_CPUFREQ_BOOST FLASHEx OB CPUFREQ BOOST + * @{ + */ +#define OB_CPUFREQ_BOOST_DISABLE 0x00000000U /*!< CPUFREQ BOOST disabled */ +#define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST /*!< CPUFREQ BOOST enabled */ +/** + * @} + */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +/** @defgroup FLASHEx_OB_TCM_AXI_SHARED FLASHEx OB TCM AXI SHARED + * @{ + */ +#define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U /*!< 64KB ITCM / 320KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0 /*!< 128KB ITCM / 256KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1 /*!< 192KB ITCM / 192KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED /*!< 256KB ITCM / 128KB system AXI */ +/** + * @} + */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + + /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type + * @{ + */ +#define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */ +#define OB_USER_NRST_STOP_D1 0x0002U /*!< Reset when entering Stop mode selection*/ +#define OB_USER_NRST_STDBY_D1 0x0004U /*!< Reset when entering standby mode selection*/ +#define OB_USER_IWDG_STOP 0x0008U /*!< Independent watchdog counter freeze in stop mode */ +#define OB_USER_IWDG_STDBY 0x0010U /*!< Independent watchdog counter freeze in standby mode */ +#define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */ +#define OB_USER_SECURITY 0x0040U /*!< security selection */ +#define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */ +#if defined (DUAL_BANK) +#define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */ +#endif /* DUAL_BANK */ +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +#define OB_USER_VDDMMC_HSLV 0x0200U /*!< VDDMMC HSLV selection */ +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ +#if defined (DUAL_CORE) +#define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */ +#define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */ +#define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */ +#endif /*DUAL_CORE*/ +#if defined (FLASH_OPTSR_NRST_STOP_D2) +#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection */ +#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection */ +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_CORE) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ + OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\ + OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) +#elif defined (FLASH_OPTSR_VDDMMC_HSLV) +#if defined (DUAL_BANK) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ + OB_USER_VDDMMC_HSLV) +#else +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV |\ + OB_USER_VDDMMC_HSLV) +#endif /* DUAL_BANK */ +#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV |\ + OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) +#else /* Single core */ +#if defined (DUAL_BANK) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK ) +#else +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV ) +#endif /* DUAL_BANK */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION + * @{ + */ +#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */ +#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */ +#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP + * @{ + */ +#define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level + is decreased from Level 1 to Level 0 or during a mass erase */ +#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is + decreased from Level 1 to Level 0 (full mass erase) */ +/** + * @} + */ + +/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type + * @{ + */ +#define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */ +#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */ +#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */ +/** + * @} + */ + +/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size + * @{ + */ +#define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */ +#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256-bit) */ +#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (256-bit) */ +#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (256-bit) */ +/** + * @} + */ + +/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay + * @{ + */ +#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */ +#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz */ +#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */ +#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */ +/** + * @} + */ + +#if defined (FLASH_OTPBL_LOCKBL) +/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks + * @{ + */ +#define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */ +#define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */ +#define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */ +#define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */ +#define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */ +#define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */ +#define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */ +#define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */ +#define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */ +#define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */ +#define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */ +#define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */ +#define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */ +#define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */ +#define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */ +#define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */ +#define FLASH_OTP_BLOCK_ALL 0x0000FFFFU /*!< OTP All Blocks */ +/** + * @} + */ +#endif /* FLASH_OTPBL_LOCKBL */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1) + * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. + * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) + * @retval The FLASH Boot Base Address + */ +#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U) + +#if defined (FLASH_CR_PSIZE) +/** + * @brief Set the FLASH Program/Erase parallelism. + * @param __PSIZE__ FLASH Program/Erase parallelism + * This parameter can be a value of @ref FLASH_Program_Parallelism + * @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2) + * @retval none + */ +#if defined (DUAL_BANK) +#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \ + MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \ + MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__))) +#else +#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) +#endif /* DUAL_BANK */ + +/** + * @brief Get the FLASH Program/Erase parallelism. + * @param __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2) + * @retval FLASH Program/Erase parallelism + * This return value can be a value of @ref FLASH_Program_Parallelism + */ +#if defined (DUAL_BANK) +#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \ + READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \ + READ_BIT((FLASH->CR2), FLASH_CR_PSIZE)) +#else +#define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) +#endif /* DUAL_BANK */ + +#endif /* FLASH_CR_PSIZE */ + +/** + * @brief Set the FLASH Programming Delay. + * @param __DELAY__ FLASH Programming Delay + * This parameter can be a value of @ref FLASHEx_Programming_Delay + * @retval none + */ +#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) + +/** + * @brief Get the FLASH Programming Delay. + * @retval FLASH Programming Delay + * This return value can be a value of @ref FLASHEx_Programming_Delay + */ +#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) + /** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +/* Extension Program operation functions *************************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void); +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void); +#if defined (DUAL_BANK) +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void); +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void); +#endif /* DUAL_BANK */ + +HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result); + +/** + * @} + */ + +#if (USE_FLASH_ECC == 1U) +/** @addtogroup FLASHEx_Exported_Functions_Group3 + * @{ + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void); +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void); +void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void); +void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void); +#if defined (DUAL_BANK) +void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void); +void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void); +#endif /* DUAL_BANK */ + +void HAL_FLASHEx_EnableEccDetectionInterrupt(void); +void HAL_FLASHEx_DisableEccDetectionInterrupt(void); +void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void); +void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void); +#if defined (DUAL_BANK) +void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void); +void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void); +#endif /* DUAL_BANK */ + +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData); +void HAL_FLASHEx_BusFault_IRQHandler(void); + +__weak void HAL_FLASHEx_EccDetectionCallback(void); +__weak void HAL_FLASHEx_EccCorrectionCallback(void); +/** + * @} + */ +#endif /* USE_FLASH_ECC */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ + +/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters + * @{ + */ + +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#if defined (FLASH_CR_PSIZE) +#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_4)) +#endif /* FLASH_CR_PSIZE */ + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \ + (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) + +#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1) ||\ + ((LEVEL) == OB_RDP_LEVEL_2)) + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \ + ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3)) + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ + ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || \ + ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || \ + ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || \ + ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || \ + ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || \ + ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || \ + ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || \ + ((LATENCY) == FLASH_LATENCY_15)) + +#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL) + +#if (FLASH_SECTOR_TOTAL == 8U) +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#else +#define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U) +#endif /* FLASH_SECTOR_TOTAL == 8U */ + +#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \ + ((CONFIG) == OB_PCROP_RDP_ERASE)) + +#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \ + ((CONFIG) == OB_SECURE_RDP_ERASE)) + +#if defined (DUAL_BANK) +#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) +#endif /* DUAL_BANK */ + +#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE)) + +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +#define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE)) +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + +#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW)) +#if defined (DUAL_CORE) +#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW)) +#endif /* DUAL_CORE */ +#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1)) + +#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1)) + +#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \ + ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB)) + +#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) + +#if defined (DUAL_CORE) +#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE)) + +#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE)) +#endif /* DUAL_CORE */ + +#if defined (FLASH_OPTSR_NRST_STOP_D2) +#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2)) + +#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2)) +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \ + ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB)) +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +#define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE)) +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ + (((TYPE) & ~OB_USER_ALL) == 0U)) + +#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \ + ((VALUE) == OB_BOOT_ADD1) || \ + ((VALUE) == OB_BOOT_ADD_BOTH)) + +#define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \ + ((VALUE) == FLASH_CRC_SECTORS) || \ + ((VALUE) == FLASH_CRC_BANK)) + +#if defined (FLASH_OTPBL_LOCKBL) +#define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U)) +#endif /* FLASH_OTPBL_LOCKBL */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_FLASH_EX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h new file mode 100644 index 0000000..e0b75b7 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h @@ -0,0 +1,359 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_GPIO_H +#define STM32H7xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< Fast speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< High speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +#if defined(DUAL_CORE) +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__)) +#endif + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32h7xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) +#define TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_GPIO_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h new file mode 100644 index 0000000..9d6cb56 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h @@ -0,0 +1,492 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_GPIO_EX_H +#define STM32H7xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#if defined(PWR_CPUCR_RETDS_CD) /* CPU domain power down Deepsleep */ +#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */ +#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */ +#define GPIO_AF0_NDSTOP2 ((uint8_t)0x00) /* NDSTOP2 Alternate Function mapping */ +#endif /* PWR_CPUCR_RETDS_CD */ +#if defined(PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */ +#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_D2PWREN ((uint8_t)0x00) /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */ +#if defined(DUAL_CORE) +#define GPIO_AF0_C2DSLEEP ((uint8_t)0x00) /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_C2SLEEP ((uint8_t)0x00) /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#endif /* DUAL_CORE */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#if defined(HRTIM1) +#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#if defined(SAI4) +#define GPIO_AF1_SAI4 ((uint8_t)0x01) /* SAI4 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /* SAI4 */ +#define GPIO_AF1_FMC ((uint8_t)0x01) /* FMC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ + + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */ +#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */ +#if defined(HRTIM1) +#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#if defined(FDCAN3) +#define GPIO_AF2_FDCAN3 ((uint8_t)0x02) /* FDCAN3 Alternate Function mapping */ +#endif /*FDCAN3*/ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */ +#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */ +#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */ +#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */ +#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */ +#if defined(OCTOSPIM) +#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF3_OCTOSPIM_P2 ((uint8_t)0x03) /* OCTOSPI Manager Port 2 Alternate Function mapping */ +#endif /* OCTOSPIM */ +#if defined(HRTIM1) +#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#define GPIO_AF3_LTDC ((uint8_t)0x03) /* LTDC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */ +#endif /* I2C5*/ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ +#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#if defined(USART10) +#define GPIO_AF4_USART10 ((uint8_t)0x04) /* USART10 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /*USART10*/ +#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#if defined(PSSI) +#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ +#endif /* PSSI */ +#if defined(OCTOSPIM) +#define GPIO_AF4_OCTOSPIM_P1 ((uint8_t)0x04) /* OCTOSPI Manager Port 1 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */ +#if defined(FDCAN3) +#define GPIO_AF5_FDCAN3 ((uint8_t)0x05) /* FDCAN3 Alternate Function mapping */ +#endif /*FDCAN3*/ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ +#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF6_I2C5 ((uint8_t)0x06) /* I2C5 Alternate Function mapping */ +#endif /* I2C5*/ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */ +#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#if defined(SAI3) +#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */ +#endif /* SAI3 */ +#if defined(OCTOSPIM) +#define GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */ +#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */ +#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */ +#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */ +#if defined(SAI2) +#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ +#endif /*SAI2*/ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */ +#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */ +#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#if defined(SAI4) +#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ +#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ +#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */ +#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */ +#if defined(QUADSPI) +#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */ +#endif /* QUADSPI */ +#if defined(SAI4) +#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ +#if defined(OCTOSPIM) +#define GPIO_AF9_OCTOSPIM_P1 ((uint8_t)0x09) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF9_OCTOSPIM_P2 ((uint8_t)0x09) /* OCTOSPI Manager Port 2 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 10 selection + */ +#if defined(SAI2) +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ +#endif /*SAI2*/ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */ +#if defined(USB2_OTG_FS) +#define GPIO_AF10_OTG2_FS ((uint8_t)0x0A) /* OTG2_FS Alternate Function mapping */ +#endif /*USB2_OTG_FS*/ +#define GPIO_AF10_COMP1 ((uint8_t)0x0A) /* COMP1 Alternate Function mapping */ +#define GPIO_AF10_COMP2 ((uint8_t)0x0A) /* COMP2 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#define GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */ +#if defined(QUADSPI) +#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ +#endif /* QUADSPI */ +#if defined(SAI4) +#define GPIO_AF10_SAI4 ((uint8_t)0x0A) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ +#if !defined(USB2_OTG_FS) +#define GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#endif /* !USB2_OTG_FS */ +#define GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */ +#if defined(OCTOSPIM) +#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ +#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */ +#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */ +#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */ +#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */ +#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */ +#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF11_DFSDM2 ((uint8_t)0x0B) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#if defined(USART10) +#define GPIO_AF11_USART10 ((uint8_t)0x0B) /* USART10 Alternate Function mapping */ +#endif /* USART10 */ +#if defined(UART9) +#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ +#endif /* UART9 */ +#if defined(ETH) +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */ +#endif /* ETH */ +#if defined(LTDC) +#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#endif /*LTDC*/ +#if defined(OCTOSPIM) +#define GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_MDIOS ((uint8_t)0x0C) /* MDIOS Alternate Function mapping */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_TIM8 ((uint8_t)0x0C) /* TIM8 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#if defined(USB2_OTG_FS) +#define GPIO_AF12_OTG1_FS ((uint8_t)0x0C) /* OTG1_FS Alternate Function mapping */ +#endif /* USB2_OTG_FS */ +#if defined(OCTOSPIM) +#define GPIO_AF12_OCTOSPIM_P1 ((uint8_t)0x0C) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */ +#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#if defined(DSI) +#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ +#endif /* DSI */ +#if defined(PSSI) +#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */ +#endif /* PSSI */ +#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */ +#if defined(TIM23) +#define GPIO_AF13_TIM23 ((uint8_t)0x0D) /* TIM23 Alternate Function mapping */ +#endif /*TIM23*/ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */ +#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */ +#if defined(TIM24) +#define GPIO_AF14_TIM24 ((uint8_t)0x0E) /* TIM24 Alternate Function mapping */ +#endif /*TIM24*/ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions + * @{ + */ +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @brief GPIO pin available on the platform + */ +/* Defines the available pins per GPIOs */ +#define GPIOA_PIN_AVAILABLE GPIO_PIN_All +#define GPIOB_PIN_AVAILABLE GPIO_PIN_All +#define GPIOC_PIN_AVAILABLE GPIO_PIN_All +#define GPIOD_PIN_AVAILABLE GPIO_PIN_All +#define GPIOE_PIN_AVAILABLE GPIO_PIN_All +#define GPIOF_PIN_AVAILABLE GPIO_PIN_All +#define GPIOG_PIN_AVAILABLE GPIO_PIN_All +#if defined(GPIOI) +#define GPIOI_PIN_AVAILABLE GPIO_PIN_All +#endif /*GPIOI*/ +#if defined(GPIOI) +#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All +#else +#define GPIOJ_PIN_AVAILABLE (GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 ) +#endif /* GPIOI */ +#define GPIOH_PIN_AVAILABLE GPIO_PIN_All +#if defined(GPIOI) +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \ + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) +#else +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 ) +#endif /* GPIOI */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Macros GPIO Private Macros + * @{ + */ +/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index + * @{ + */ +#if defined(GPIOI) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOE))? 4UL :\ + ((__GPIOx__) == (GPIOF))? 5UL :\ + ((__GPIOx__) == (GPIOG))? 6UL :\ + ((__GPIOx__) == (GPIOH))? 7UL :\ + ((__GPIOx__) == (GPIOI))? 8UL :\ + ((__GPIOx__) == (GPIOJ))? 9UL : 10UL) +#else +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOE))? 4UL :\ + ((__GPIOx__) == (GPIOF))? 5UL :\ + ((__GPIOx__) == (GPIOG))? 6UL :\ + ((__GPIOx__) == (GPIOH))? 7UL :\ + ((__GPIOx__) == (GPIOJ))? 9UL : 10UL) +#endif /* GPIOI */ + +/** + * @} + */ + +/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_GPIO_EX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h new file mode 100644 index 0000000..45cf33d --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h @@ -0,0 +1,211 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_hsem.h + * @author MCD Application Team + * @brief Header file of HSEM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_HSEM_H +#define STM32H7xx_HAL_HSEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup HSEM + * @{ + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HSEM_Exported_Macros HSEM Exported Macros + * @{ + */ + +/** + * @brief SemID to mask helper Macro. + * @param __SEMID__: semaphore ID from 0 to 31 + * @retval Semaphore Mask. + */ +#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__)) + +/** + * @brief Enables the specified HSEM interrupts. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (HSEM->C1IER |= (__SEM_MASK__)) : \ + (HSEM->C2IER |= (__SEM_MASK__))) +#else +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->C1IER |= (__SEM_MASK__)) +#endif /* DUAL_CORE */ +/** + * @brief Disables the specified HSEM interrupts. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (HSEM->C1IER &= ~(__SEM_MASK__)) : \ + (HSEM->C2IER &= ~(__SEM_MASK__))) +#else +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->C1IER &= ~(__SEM_MASK__)) +#endif /* DUAL_CORE */ + +/** + * @brief Checks whether interrupt has occurred or not for semaphores specified by a mask. + * @param __SEM_MASK__: semaphores Mask + * @retval semaphores Mask : Semaphores where an interrupt occurred. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + ((__SEM_MASK__) & HSEM->C1MISR) : \ + ((__SEM_MASK__) & HSEM->C2MISR)) +#else +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1MISR) +#endif /* DUAL_CORE */ + +/** + * @brief Get the semaphores release status flags. + * @param __SEM_MASK__: semaphores Mask + * @retval semaphores Mask : Semaphores where Release flags rise. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (__SEM_MASK__) & HSEM->C1ISR : \ + (__SEM_MASK__) & HSEM->C2ISR) +#else +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1ISR) +#endif /* DUAL_CORE */ + +/** + * @brief Clears the HSEM Interrupt flags. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (HSEM->C1ICR |= (__SEM_MASK__)) : \ + (HSEM->C2ICR |= (__SEM_MASK__))) +#else +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->C1ICR |= (__SEM_MASK__)) +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HSEM_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions + * @brief HSEM Take and Release functions + * @{ + */ + +/* HSEM semaphore take (lock) using 2-Step method ****************************/ +HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID); +/* HSEM semaphore fast take (lock) using 1-Step method ***********************/ +HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID); +/* HSEM Release **************************************************************/ +void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID); +/* HSEM Release All************************************************************/ +void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID); +/* HSEM Check semaphore state Taken or not **********************************/ +uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID); + +/** + * @} + */ + +/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions + * @brief HSEM Set and Get Key functions. + * @{ + */ +/* HSEM Set Clear Key *********************************************************/ +void HAL_HSEM_SetClearKey(uint32_t Key); +/* HSEM Get Clear Key *********************************************************/ +uint32_t HAL_HSEM_GetClearKey(void); +/** + * @} + */ + +/** @addtogroup HSEM_Exported_Functions_Group3 + * @brief HSEM Notification functions + * @{ + */ +/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/ +void HAL_HSEM_ActivateNotification(uint32_t SemMask); +/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/ +void HAL_HSEM_DeactivateNotification(uint32_t SemMask); +/* HSEM Free Callback (When a semaphore is released) *******************************/ +void HAL_HSEM_FreeCallback(uint32_t SemMask); +/* HSEM IRQ Handler **********************************************************/ +void HAL_HSEM_IRQHandler(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HSEM_Private_Macros HSEM Private Macros + * @{ + */ + +#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX ) + +#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX ) + +#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX ) + +#if defined(DUAL_CORE) +#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \ + ((__COREID__) == HSEM_CPU2_COREID)) +#else +#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID) +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_HSEM_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h new file mode 100644 index 0000000..c524cbc --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h @@ -0,0 +1,838 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_I2C_H +#define STM32H7xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section + in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32h7xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32h7xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7xx_HAL_I2C_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h new file mode 100644 index 0000000..e701b8b --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_I2C_EX_H +#define STM32H7xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#if defined(SYSCFG_PMCR_I2C5_FMP) +#define I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */ +#else +#define I2C_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */ +#endif /* SYSCFG_PMCR_I2C5_FMP */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_I2C_EX_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h new file mode 100644 index 0000000..fb61178 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h @@ -0,0 +1,868 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_mdma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_MDMA_H +#define STM32H7xx_HAL_MDMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup MDMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup MDMA_Exported_Types MDMA Exported Types + * @brief MDMA Exported Types + * @{ + */ + +/** + * @brief MDMA Configuration Structure definition + */ +typedef struct +{ + + uint32_t Request; /*!< Specifies the MDMA request. + This parameter can be a value of @ref MDMA_Request_selection*/ + + uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a : + a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer + This parameter can be a value of @ref MDMA_Transfer_TriggerMode */ + + uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx. + This parameter can be a value of @ref MDMA_Priority_level */ + + uint32_t Endianness; /*!< Specifies if the MDMA transactions preserve the Little endianness. + This parameter can be a value of @ref MDMA_Endianness */ + + uint32_t SourceInc; /*!< Specifies if the Source increment mode . + This parameter can be a value of @ref MDMA_Source_increment_mode */ + + uint32_t DestinationInc; /*!< Specifies if the Destination increment mode . + This parameter can be a value of @ref MDMA_Destination_increment_mode */ + + uint32_t SourceDataSize; /*!< Specifies the source data size. + This parameter can be a value of @ref MDMA_Source_data_size */ + + uint32_t DestDataSize; /*!< Specifies the destination data size. + This parameter can be a value of @ref MDMA_Destination_data_size */ + + + uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode. + This parameter can be a value of @ref MDMA_data_Alignment */ + + uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes), + this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/ + + uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref MDMA_Source_burst + @note : the burst may be FIXED/INCR based on SourceInc value , + the BURST must be programmed as to ensure that the burst size will be lower than than + BufferTransferLength */ + + uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref MDMA_Destination_burst + @note : the burst may be FIXED/INCR based on DestinationInc value , + the BURST must be programmed as to ensure that the burst size will be lower than than + BufferTransferLength */ + + int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset + signed value : if > 0 then increment the next block source Address by offset from where the last block ends + if < 0 then decrement the next block source Address by offset from where the last block ends + if == 0, the next block source address starts from where the last block ends + */ + + + int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset + signed value : if > 0 then increment the next block destination Address by offset from where the last block ends + if < 0 then decrement the next block destination Address by offset from where the last block ends + if == 0, the next block destination address starts from where the last block ends + */ + +}MDMA_InitTypeDef; + +/** + * @brief HAL MDMA linked list node structure definition + * @note The Linked list node allows to define a new MDMA configuration + * (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers). + * When CLAR register is configured to a non NULL value , each time a transfer ends, + * a new configuration (linked list node) is automatically loaded from the address given in CLAR register. + */ +typedef struct +{ + __IO uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */ + __IO uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */ + __IO uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */ + __IO uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */ + __IO uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */ + __IO uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */ + __IO uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */ + __IO uint32_t Reserved; /*!< Reserved register */ + __IO uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */ + __IO uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */ + +}MDMA_LinkNodeTypeDef; + +/** + * @brief HAL MDMA linked list node configuration structure definition + * @note used with HAL_MDMA_LinkedList_CreateNode function + */ +typedef struct +{ + MDMA_InitTypeDef Init; /*!< configuration of the specified MDMA Linked List Node */ + uint32_t SrcAddress; /*!< The source memory address for the Linked list Node */ + uint32_t DstAddress; /*!< The destination memory address for the Linked list Node */ + uint32_t BlockDataLength; /*!< The data length of a block in bytes */ + uint32_t BlockCount; /*!< The number of blocks to be transferred */ + + uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served. + PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ + + uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served. + PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ + + +}MDMA_LinkNodeConfTypeDef; + + +/** + * @brief HAL MDMA State structure definition + */ +typedef enum +{ + HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */ + HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */ + HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */ + HAL_MDMA_STATE_ERROR = 0x03U, /*!< MDMA error state */ + HAL_MDMA_STATE_ABORT = 0x04U, /*!< MDMA Abort state */ + +}HAL_MDMA_StateTypeDef; + +/** + * @brief HAL MDMA Level Complete structure definition + */ +typedef enum +{ + HAL_MDMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */ + HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */ + HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */ + +}HAL_MDMA_LevelCompleteTypeDef; + +/** + * @brief HAL MDMA Callbacks IDs structure definition + */ +typedef enum +{ + HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, /*!< Buffer Transfer */ + HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, /*!< Block Transfer */ + HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U, /*!< Repeated Block Transfer */ + HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_MDMA_XFER_ALL_CB_ID = 0x06U /*!< All */ + +}HAL_MDMA_CallbackIDTypeDef; + + +/** + * @brief MDMA handle Structure definition + */ +typedef struct __MDMA_HandleTypeDef +{ + MDMA_Channel_TypeDef *Instance; /*!< Register base address */ + + MDMA_InitTypeDef Init; /*!< MDMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< MDMA locking object */ + + __IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */ + + void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */ + + void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */ + + void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */ + + void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */ + + void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */ + + + MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list + (after the initial node defined by the Init struct) + this parameter is used internally by the MDMA driver + to construct the linked list node + */ + + MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list + this parameter is used internally by the MDMA driver + to construct the linked list node + */ + uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */ + + __IO uint32_t ErrorCode; /*!< MDMA Error code */ + +} MDMA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MDMA_Exported_Constants MDMA Exported Constants + * @brief MDMA Exported constants + * @{ + */ + +/** @defgroup MDMA_Error_Codes MDMA Error Codes + * @brief MDMA Error Codes + * @{ + */ +#define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */ +#define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */ +#define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U) /*!< Error Mask Data error */ +#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U) /*!< Linked list Data error */ +#define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */ +#define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */ +#define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ +#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */ +#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */ + +/** + * @} + */ + +/** @defgroup MDMA_Request_selection MDMA Request selection + * @brief MDMA_Request_selection + * @{ + */ + +#define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U) /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U) /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U) /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U) /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U) /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U) /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U) /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U) /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U) /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U) /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU) /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU) /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU) /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */ +#if defined (LTDC) +#define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U) /*!< MDMA HW request is LTDC Line interrupt Flag */ +#endif /* LTDC */ +#if defined (JPEG) +#define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U) /*!< MDMA HW request is JPEG Input FIFO threshold Flag */ +#define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U) /*!< MDMA HW request is JPEG Input FIFO not full Flag */ +#define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U) /*!< MDMA HW request is JPEG Output FIFO threshold Flag */ +#define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U) /*!< MDMA HW request is JPEG Output FIFO not empty Flag */ +#define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U) /*!< MDMA HW request is JPEG End of conversion Flag */ +#endif /* JPEG */ +#if defined (OCTOSPI1) +#define MDMA_REQUEST_OCTOSPI1_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag */ +#define MDMA_REQUEST_OCTOSPI1_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag */ +#endif /* OCTOSPI1 */ +#if defined (QUADSPI) +#define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */ +#define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */ +#endif /* QUADSPI */ +#define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U) /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U) /*!< MDMA HW request is DMA2D Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU) /*!< MDMA HW request is DMA2D Transfer Watermark Flag */ + +#if defined (DSI) +#define MDMA_REQUEST_DSI_TEARING_EFFECT ((uint32_t)0x0000001BU) /*!< MDMA HW request is DSI Tearing Effect Flag */ +#define MDMA_REQUEST_DSI_END_REFRESH ((uint32_t)0x0000001CU) /*!< MDMA HW request is DSI End of refresh Flag */ +#endif /* DSI */ + +#define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU) /*!< MDMA HW request is SDMMC1 End of Data Flag */ + +#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU) /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag */ +#define MDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU) /*!< MDMA HW request is SDMMC1 Command End Flag */ + +#if defined (OCTOSPI2) +#define MDMA_REQUEST_OCTOSPI2_FIFO_TH ((uint32_t)0x00000020U) /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag */ +#define MDMA_REQUEST_OCTOSPI2_TC ((uint32_t)0x00000021U) /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag */ +#endif /* OCTOSPI2 */ + +#define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */ + +/** + * @} + */ + +/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger Mode + * @brief MDMA Transfer Trigger Mode + * @{ + */ +#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */ +#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */ +#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */ +#define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */ + +/** + * @} + */ + +/** @defgroup MDMA_Priority_level MDMA Priority level + * @brief MDMA Priority level + * @{ + */ +#define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ +#define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0) /*!< Priority level: Medium */ +#define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1) /*!< Priority level: High */ +#define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL) /*!< Priority level: Very High */ + +/** + * @} + */ + + +/** @defgroup MDMA_Endianness MDMA Endianness + * @brief MDMA Endianness + * @{ + */ +#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */ +#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */ +#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */ +#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */ + +/** + * @} + */ + +/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode + * @brief MDMA Source increment mode + * @{ + */ +#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ +#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ +#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ +#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ +#define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ +#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ +#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ +#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ +#define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ + +/** + * @} + */ + +/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode + * @brief MDMA Destination increment mode + * @{ + */ +#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ +#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ +#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ +#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ +#define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ +#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ +#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ +#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ +#define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ + +/** + * @} + */ + +/** @defgroup MDMA_Source_data_size MDMA Source data size + * @brief MDMA Source data size + * @{ + */ +#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */ +#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */ +#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */ +#define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */ + +/** + * @} + */ + +/** @defgroup MDMA_Destination_data_size MDMA Destination data size + * @brief MDMA Destination data size + * @{ + */ +#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */ +#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */ +#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */ +#define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */ + +/** + * @} + */ + +/** @defgroup MDMA_data_Alignment MDMA data alignment + * @brief MDMA data alignment + * @{ + */ +#define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size + All data are right aligned, in Little Endien mode. */ +#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */ +#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended , + Note : this mode is allowed only if the Source data size is smaller than Destination data size */ +#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */ + +/** + * @} + */ + +/** @defgroup MDMA_Source_burst MDMA Source burst + * @brief MDMA Source burst + * @{ + */ +#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ +#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */ +#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */ +#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */ +#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */ +#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */ +#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */ +#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */ + +/** + * @} + */ + +/** @defgroup MDMA_Destination_burst MDMA Destination burst + * @brief MDMA Destination burst + * @{ + */ +#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ +#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */ +#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */ +#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */ +#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */ +#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */ +#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */ +#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */ + +/** + * @} + */ + +/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions + * @brief MDMA interrupt enable definitions + * @{ + */ +#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */ +#define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */ +#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */ +#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */ +#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */ + +/** + * @} + */ + +/** @defgroup MDMA_flag_definitions MDMA flag definitions + * @brief MDMA flag definitions + * @{ + */ +#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */ +#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */ +#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */ +#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */ +#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */ +#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel request Active flag */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup MDMA_Exported_Macros MDMA Exported Macros + * @{ + */ + +/** + * @brief Enable the specified MDMA Channel. + * @param __HANDLE__: MDMA handle + * @retval None + */ +#define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN) + +/** + * @brief Disable the specified MDMA Channel. + * @param __HANDLE__: MDMA handle + * @retval None + */ +#define __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN) + +/** + * @brief Get the MDMA Channel pending flags. + * @param __HANDLE__: MDMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg MDMA_FLAG_TE : Transfer Error flag. + * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. + * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. + * @arg MDMA_FLAG_BT : Block Transfer complete flag. + * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. + * @arg MDMA_FLAG_CRQA : Channel request Active flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__)) + +/** + * @brief Clear the MDMA Stream pending flags. + * @param __HANDLE__: MDMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg MDMA_FLAG_TE : Transfer Error flag. + * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. + * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. + * @arg MDMA_FLAG_BT : Block Transfer complete flag. + * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. + * @retval None + */ +#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__)) + +/** + * @brief Enables the specified MDMA Channel interrupts. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg MDMA_IT_TE : Transfer Error interrupt mask + * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask + * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask + * @arg MDMA_IT_BT : Block Transfer interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @retval None + */ +#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified MDMA Channel interrupts. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg MDMA_IT_TE : Transfer Error interrupt mask + * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask + * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask + * @arg MDMA_IT_BT : Block Transfer interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @retval None + */ +#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified MDMA Channel interrupt is enabled or not. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the MDMA interrupt source to check. + * @arg MDMA_IT_TE : Transfer Error interrupt mask + * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask + * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask + * @arg MDMA_IT_BT : Block Transfer interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @retval The state of MDMA_IT (SET or RESET). + */ +#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Writes the number of data in bytes to be transferred on the MDMA Channelx. + * @param __HANDLE__ : MDMA handle + * @param __COUNTER__: Number of data in bytes to be transferred. + * @retval None + */ +#define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT)) + +/** + * @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer. + * @param __HANDLE__ : MDMA handle + * @retval The number of remaining data in bytes in the current MDMA Channelx transfer. + */ +#define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MDMA_Exported_Functions MDMA Exported Functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData); + +HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma)); +HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/* Linked list operation functions ********************************************/ +/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions + * @brief Linked list operation functions + * @{ + */ + +HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); + + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); +HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); +HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma); +void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma); +uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MDMA_Private_Types MDMA Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup MDMA_Private_Defines MDMA Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MDMA_Private_Variables MDMA Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MDMA_Private_Constants MDMA Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MDMA_Private_Macros MDMA Private Macros + * @{ + */ + +#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \ + ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \ + ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \ + ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER )) + + +#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \ + ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \ + ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \ + ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH)) + +#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE)) + + +#if defined (OCTOSPI2) +#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC)) +#else +#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END)) +#endif /* OCTOSPI2 */ + +#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \ + ((__INC__) == MDMA_SRC_INC_BYTE ) || \ + ((__INC__) == MDMA_SRC_INC_HALFWORD ) || \ + ((__INC__) == MDMA_SRC_INC_WORD ) || \ + ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \ + ((__INC__) == MDMA_SRC_DEC_BYTE) || \ + ((__INC__) == MDMA_SRC_DEC_HALFWORD) || \ + ((__INC__) == MDMA_SRC_DEC_WORD) || \ + ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD)) + +#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE ) || \ + ((__INC__) == MDMA_DEST_INC_BYTE ) || \ + ((__INC__) == MDMA_DEST_INC_HALFWORD ) || \ + ((__INC__) == MDMA_DEST_INC_WORD ) || \ + ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \ + ((__INC__) == MDMA_DEST_DEC_BYTE) || \ + ((__INC__) == MDMA_DEST_DEC_HALFWORD) || \ + ((__INC__) == MDMA_DEST_DEC_WORD) || \ + ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD)) + +#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE ) || \ + ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \ + ((__SIZE__) == MDMA_SRC_DATASIZE_WORD ) || \ + ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD)) + +#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE ) || \ + ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \ + ((__SIZE__) == MDMA_DEST_DATASIZE_WORD ) || \ + ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD)) + +#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT)) + + +#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \ + ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \ + ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \ + ((__BURST__) == MDMA_SOURCE_BURST_8BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_128BEATS)) + + +#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \ + ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \ + ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \ + ((__BURST__) == MDMA_DEST_BURST_8BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_128BEATS)) + + #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \ + ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \ + ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \ + ((__MODE__) == MDMA_FULL_TRANSFER)) + +#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU)) + +#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U)) + +#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U)) + +#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536)) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MDMA_Private_Functions MDMA Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_MDMA_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h new file mode 100644 index 0000000..c1d7222 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h @@ -0,0 +1,809 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_PWR_H +#define STM32H7xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This + parameter can be a value of @ref + PWR_PVD_detection_level. + */ + + uint32_t Mode; /*!< Mode: Specifies the EXTI operating mode for the PVD + event. This parameter can be a value of @ref + PWR_PVD_Mode. + */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector + level 0 selection : 1V95 */ +#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector + level 1 selection : 2V1 */ +#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector + level 2 selection : 2V25 */ +#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector + level 3 selection : 2V4 */ +#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector + level 4 selection : 2V55 */ +#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector + level 5 selection : 2V7 */ +#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector + level 6 selection : 2V85 */ +#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage + (Compare internally to VREF) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0U) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI (0x01U) +#define PWR_SLEEPENTRY_WFE (0x02U) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI (0x01U) +#define PWR_STOPENTRY_WFE (0x02U) +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale + * @{ + */ +#if defined(PWR_SRDCR_VOS) +#define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1) +#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE3 (0U) +#else +#define PWR_REGULATOR_VOLTAGE_SCALE0 (0U) +#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1) +#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0) +#endif /* PWR_SRDCR_VOS */ +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +/* PWR CPU flag */ +#define PWR_FLAG_STOP (0x01U) +#if defined (PWR_CPUCR_SBF_D2) +#define PWR_FLAG_SB_D1 (0x02U) +#define PWR_FLAG_SB_D2 (0x03U) +#endif /* defined (PWR_CPUCR_SBF_D2) */ +#define PWR_FLAG_SB (0x04U) +#if defined (DUAL_CORE) +#define PWR_FLAG_CPU_HOLD (0x05U) +#define PWR_FLAG_CPU2_HOLD (0x06U) +#define PWR_FLAG2_STOP (0x07U) +#define PWR_FLAG2_SB_D1 (0x08U) +#define PWR_FLAG2_SB_D2 (0x09U) +#define PWR_FLAG2_SB (0x0AU) +#endif /* defined (DUAL_CORE) */ +#define PWR_FLAG_PVDO (0x0BU) +#define PWR_FLAG_AVDO (0x0CU) +#define PWR_FLAG_ACTVOSRDY (0x0DU) +#define PWR_FLAG_ACTVOS (0x0EU) +#define PWR_FLAG_BRR (0x0FU) +#define PWR_FLAG_VOSRDY (0x10U) +#if defined (SMPS) +#define PWR_FLAG_SMPSEXTRDY (0x11U) +#else +#define PWR_FLAG_SCUEN (0x11U) +#endif /* defined (SMPS) */ +#if defined (PWR_CSR1_MMCVDO) +#define PWR_FLAG_MMCVDO (0x12U) +#endif /* defined (PWR_CSR1_MMCVDO) */ +#define PWR_FLAG_USB33RDY (0x13U) +#define PWR_FLAG_TEMPH (0x14U) +#define PWR_FLAG_TEMPL (0x15U) +#define PWR_FLAG_VBATH (0x16U) +#define PWR_FLAG_VBATL (0x17U) + +/* PWR Wake up flag */ +#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1 +#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2 +#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3 +#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4 +#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5 +#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6 +/** + * @} + */ + +/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask + * @{ + */ +#define PWR_EWUP_MASK (0x0FFF3F3FU) +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Configure the main internal regulator output voltage. + * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a + * trade-off between performance and power consumption + * when the device does not operate at the maximum + * frequency (refer to the datasheet for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output + * Scale 0 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output + * Scale 1 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output + * Scale 2 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output + * Scale 3 mode. + * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is + * only possible when Vcore is supplied from LDO (Low DropOut). The + * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() + * macro before configuring Voltage Scale 0 using + * __HAL_PWR_VOLTAGESCALING_CONFIG(). + * Transition to Voltage Scale 0 is only possible when the system is + * already in Voltage Scale 1. + * Transition from Voltage Scale 0 is only possible to Voltage Scale 1 + * then once in Voltage Scale 1 it is possible to switch to another + * voltage scale. + * After each regulator voltage setting, wait on VOSRDY flag to be set + * using macro __HAL_PWR_GET_FLAG(). + * To enter low power mode , and if current regulator voltage is + * Voltage Scale 0 then first switch to Voltage Scale 1 before entering + * low power mode. + * @retval None. + */ +#if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Configure the Voltage Scaling */ \ + MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \ + UNUSED(tmpreg); \ +} while(0) +#else /* 3 power domains devices */ +#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Check the voltage scaling to be configured */ \ + if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \ + { \ + /* Configure the Voltage Scaling 1 */ \ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + /* Enable the PWR overdrive */ \ + SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Delay after setting the syscfg boost setting */ \ + tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + } \ + else \ + { \ + /* Disable the PWR overdrive */ \ + CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Delay after setting the syscfg boost setting */ \ + tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Configure the Voltage Scaling x */ \ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + } \ + UNUSED(tmpreg); \ +} while(0) +#else /* STM32H72xxx and STM32H73xxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Configure the Voltage Scaling */ \ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + UNUSED(tmpreg); \ +} while(0) +#endif /* defined(SYSCFG_PWRCR_ODEN) */ +#endif /* defined (PWR_SRDCR_VOS) */ + +/** @brief Check PWR flags are set or not. + * @param __FLAG__ : Specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD + * is enabled by the HAL_PWR_EnablePVD() + * function. + * The PVD is stopped by STANDBY mode. For this + * reason, this bit is equal to 0 after STANDBY + * or reset until the PVDE bit is set. + * @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD + * is enabled by the HAL_PWREx_EnableAVD() + * function. The AVD is stopped by STANDBY mode. + * For this reason, this bit is equal to 0 + * after STANDBY or reset until the AVDE bit + * is set. + * @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator + * voltage scaling output selection is + * ready. + * @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not + * reset when the device wakes up from STANDBY + * mode or by a system reset or power-on reset. + * @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator + * voltage scaling output selection is ready. + * mode or by a system reset or power-on reset. + * @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply + * from regulator is ready. + * @arg PWR_FLAG_TEMPH : This flag indicates that the temperature + * equal or above high threshold level. + * @arg PWR_FLAG_TEMPL : This flag indicates that the temperature + * equal or below low threshold level. + * @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal + * or above high threshold level. + * @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal + * or below low threshold level. + * @arg PWR_FLAG_STOP : This flag indicates that the system entered + * in STOP mode. + * @arg PWR_FLAG_SB : This flag indicates that the system entered in + * STANDBY mode. + * @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain + * entered in STANDBY mode. + * @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain + * entered in STANDBY mode. + * @arg PWR_FLAG2_STOP : This flag indicates that the system entered + * in STOP mode. + * @arg PWR_FLAG2_SB : This flag indicates that the system entered + * in STANDBY mode. + * @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain + * entered in STANDBY mode. + * @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain + * entered in STANDBY mode. + * @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes + * up with hold. + * @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes + * up with hold. + * @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS + * External supply is sready. + * @arg PWR_FLAG_SCUEN : This flag indicates that the supply + * configuration update is enabled. + * @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is + * above or equal to 1.2 V. + * @note The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR, + * PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL, + * PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags + * are used for all H7 family lines. + * The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2, + * PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7 + * dual core lines. + * The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7 + * family except STM32H7Axxx and STM32H7Bxxx lines. + * The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and + * STM32H7Bxxx lines. + * The PWR_FLAG_SCUEN flag is used for devices that support only LDO + * regulator. + * The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO + * and SMPS regulators. + * @retval The (__FLAG__) state (TRUE or FALSE). + */ +#if defined (DUAL_CORE) /* Dual core lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\ + ((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* Single core lines */ +#if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */ +#if defined (SMPS) /* STM32H725 and STM32H735 lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#endif /* defined (SMPS) */ +#else /* STM32H7Axxx and STM32H7Bxxx lines */ +#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* STM32H7Axx and STM32H7Bxx lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#endif /* SMPS */ +#endif /* PWR_CPUCR_SBF_D2 */ +#endif /* DUAL_CORE */ + +/** @brief Check PWR wake up flags are set or not. + * @param __FLAG__: specifies the wake up flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. + * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. + * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. + * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices + * that support GPIOI port. + * @retval The (__FLAG__) state (TRUE or FALSE). + */ +#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1) + +#if defined (DUAL_CORE) +/** @brief Clear CPU PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with other families. + * @note This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2. + * This parameter can be one of the following values : + * @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 + * CPU flags. + * @retval None. + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ +do { \ + SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \ +} while(0) +#else +/** @brief Clear CPU PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with other families. + * @note This macro clear all CPU flags. + * For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU + * flags are STOPF, SBF, SBF_D1 and SBF_D2. + * For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF. + * @retval None. + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF) +#endif /* defined (DUAL_CORE) */ + +/** @brief Clear PWR wake up flags. + * @param __FLAG__ : Specifies the wake up flag to be cleared. + * This parameter can be one of the following values : + * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. + * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. + * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. + * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices + * that support GPIOI port. + * @retval None. + */ +#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) + +/** + * @brief Enable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable the PVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable the PVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable event on PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable event on PVD EXTI D2 Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable event on PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable event on PVD EXTI D2 Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable the PVD Rising Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Rising Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Rising & Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Disable the PVD Rising & Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) + +#if defined (DUAL_CORE) +/** + * @brief Checks whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI D2 PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Clear the PVD EXTI D2 flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32h7xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit (void); +void HAL_PWR_EnableBkUpAccess (void); +void HAL_PWR_DisableBkUpAccess (void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD (void); +void HAL_PWR_DisablePVD (void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode (void); + +/* Power PVD IRQ Handler */ +void HAL_PWR_PVD_IRQHandler (void); +void HAL_PWR_PVDCallback (void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit (void); +void HAL_PWR_DisableSleepOnExit (void); +void HAL_PWR_EnableSEVOnPend (void); +void HAL_PWR_DisableSEVOnPend (void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< External interrupt line 16 + Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +/* Check PVD level parameter */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\ + ((LEVEL) == PWR_PVDLEVEL_1) ||\ + ((LEVEL) == PWR_PVDLEVEL_2) ||\ + ((LEVEL) == PWR_PVDLEVEL_3) ||\ + ((LEVEL) == PWR_PVDLEVEL_4) ||\ + ((LEVEL) == PWR_PVDLEVEL_5) ||\ + ((LEVEL) == PWR_PVDLEVEL_6) ||\ + ((LEVEL) == PWR_PVDLEVEL_7)) + +/* Check PVD mode parameter */ +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_NORMAL)) + +/* Check low power regulator parameter */ +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) ||\ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +/* Check low power mode entry parameter */ +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +/* Check low power mode entry parameter */ +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE)) + +/* Check voltage scale level parameter */ +#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H7xx_HAL_PWR_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h new file mode 100644 index 0000000..e8455d8 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h @@ -0,0 +1,789 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_PWR_EX_H +#define STM32H7xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Types PWREx Exported Types + * @{ + */ +/** + * @brief PWREx AVD configuration structure definition + */ +typedef struct +{ + uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This + parameter can be a value of @ref + PWREx_AVD_detection_level + */ + + uint32_t Mode; /*!< Mode : Specifies the EXTI operating mode for the AVD + event. This parameter can be a value of @ref + PWREx_AVD_Mode. + */ +}PWREx_AVDTypeDef; + +/** + * @brief PWREx Wakeup pin configuration structure definition + */ +typedef struct +{ + uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled. + This parameter can be a value of @ref + PWREx_WakeUp_Pins + */ + + uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity. + This parameter can be a value of @ref + PWREx_PIN_Polarity + */ + + uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. This + parameter can be a value of @ref + PWREx_PIN_Pull + */ +}PWREx_WakeupPinTypeDef; + +#if defined (PWR_CSR1_MMCVDO) +/** + * @brief PWR VDDMMC voltage level enum definition + */ +typedef enum +{ + PWR_MMC_VOLTAGE_BELOW_1V2, /*!< VDDMMC is below 1V2 */ + PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */ +} PWREx_MMC_VoltageLevel; +#endif /* defined (PWR_CSR1_MMCVDO) */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ +/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins + * @{ + */ +/* High level and No pull (default configuration) */ +#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 +#if defined (PWR_WKUPEPR_WKUPEN5) +#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 +#if defined (PWR_WKUPEPR_WKUPEN3) +#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 +#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 + +/* High level and No pull */ +#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6 +#if defined (PWR_WKUPEPR_WKUPEN5) +#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5 +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 +#if defined (PWR_WKUPEPR_WKUPEN3) +#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 +#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 + +/* Low level and No pull */ +#define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6) +#if defined (PWR_WKUPEPR_WKUPP5) +#define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5) +#endif /* defined (PWR_WKUPEPR_WKUPP5) */ +#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) +#if defined (PWR_WKUPEPR_WKUPP3) +#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) +#endif /* defined (PWR_WKUPEPR_WKUPP3) */ +#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) +#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) +/** + * @} + */ + +/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration + * @{ + */ +#define PWR_PIN_POLARITY_HIGH (0x00000000U) +#define PWR_PIN_POLARITY_LOW (0x00000001U) +/** + * @} + */ + +/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration + * @{ + */ +#define PWR_PIN_NO_PULL (0x00000000U) +#define PWR_PIN_PULL_UP (0x00000001U) +#define PWR_PIN_PULL_DOWN (0x00000002U) +/** + * @} + */ + +/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags. + * @{ + */ +#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ +#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ +#endif /* defined (PWR_WKUPFR_WKUPF3) */ +#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ +#if defined (PWR_WKUPFR_WKUPF5) +#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ +#endif /* defined (PWR_WKUPFR_WKUPF5) */ +#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ + PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\ + PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6) +#else +#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ + PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6) +#endif /* defined (PWR_WKUPFR_WKUPF3) */ +/** + * @} + */ + +#if defined (DUAL_CORE) +/** @defgroup PWREx_Core_Select PWREx Core definition + * @{ + */ +#define PWR_CORE_CPU1 (0x00000000U) +#define PWR_CORE_CPU2 (0x00000001U) +/** + * @} + */ +#endif /* defined (DUAL_CORE) */ + +/** @defgroup PWREx_Domains PWREx Domains definition + * @{ + */ +#define PWR_D1_DOMAIN (0x00000000U) +#if defined (PWR_CPUCR_PDDS_D2) +#define PWR_D2_DOMAIN (0x00000001U) +#endif /* defined (PWR_CPUCR_PDDS_D2) */ +#define PWR_D3_DOMAIN (0x00000002U) +/** + * @} + */ + +/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition + * @{ + */ +#if defined (DUAL_CORE) +#define PWR_D1_DOMAIN_FLAGS (0x00000000U) +#define PWR_D2_DOMAIN_FLAGS (0x00000001U) +#define PWR_ALL_DOMAIN_FLAGS (0x00000002U) +#else +#define PWR_CPU_FLAGS (0x00000000U) +#endif /* defined (DUAL_CORE) */ +/** + * @} + */ + +/** @defgroup PWREx_D3_State PWREx D3 Domain State + * @{ + */ +#define PWR_D3_DOMAIN_STOP (0x00000000U) +#define PWR_D3_DOMAIN_RUN (0x00000800U) + +/** + * @} + */ + +/** @defgroup PWREx_Supply_configuration PWREx Supply configuration + * @{ + */ +#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ +#if defined (SMPS) +#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS only */ +#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ +#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ +#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ +#endif /* defined (SMPS) */ +#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */ + +#if defined (SMPS) +#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \ + PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) +#else +#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) +#endif /* defined (SMPS) */ +/** + * @} + */ + + +/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level + * @{ + */ +#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0 + selection : 1V7 */ +#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1 + selection : 2V1 */ +#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2 + selection : 2V5 */ +#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3 + selection : 2V8 */ +/** + * @} + */ + +/** @defgroup PWREx_AVD_Mode PWREx AVD Mode + * @{ + */ +#define PWR_AVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_AVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0) +#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1) +#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection + * @{ + */ +#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ +#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds + * @{ + */ +#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) +#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL +#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH +/** + * @} + */ + +/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds + * @{ + */ +#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) +#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL +#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH +/** + * @} + */ +/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16 + * @{ + */ +#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 + Connected to the AVD EXTI Line */ +/** + * @} + */ + +#if defined (PWR_CR1_SRDRAMSO) +/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection + * @{ + */ +#define PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode */ +#define PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */ +#define PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode */ +#define PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode */ +#define PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO /*!< AHB RAM1 shut-off in DStop/DStop2 mode */ +#define PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO /*!< AHB RAM2 shut-off in DStop/DStop2 mode */ +#define PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO /*!< AXI RAM1 shut-off in DStop/DStop2 mode */ +#define PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO /*!< AXI RAM2 shut-off in DStop/DStop2 mode */ +#define PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO /*!< AXI RAM3 shut-off in DStop/DStop2 mode */ +#define PWR_MEMORY_BLOCK_KEEP_ON 0U /*!< Memory content is kept in DStop or DStop2 mode */ +#define PWR_MEMORY_BLOCK_SHUT_OFF 1U /*!< Memory content is lost in DStop or DStop2 mode */ +/** + * @} + */ +#endif /* defined (PWR_CR1_SRDRAMSO) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Macro PWREx Exported Macro + * @{ + */ + +/** + * @brief Enable the AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable the AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable the AVD EXTI Line 16 + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable the AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable event on AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable event on AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable event on AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable event on AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable the AVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Check whether the specified AVD EXTI interrupt flag is set or not. + * @retval EXTI AVD Line Status. + */ +#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) + +#if defined (DUAL_CORE) +/** + * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not. + * @retval EXTI D2 AVD Line Status. + */ +#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Clear the AVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Clear the AVD EXTI D2 flag. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Generates a Software interrupt on AVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @{ + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource); +uint32_t HAL_PWREx_GetSupplyConfig (void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetVoltageRange (void); +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetStopModeVoltageRange (void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @{ + */ +/* System low power control functions */ +#if defined (PWR_CPUCR_RETDS_CD) +void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry); +#endif /* defined (PWR_CPUCR_RETDS_CD) */ +void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain); +void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain); +void HAL_PWREx_ConfigD3Domain (uint32_t D3State); +/* Clear Cortex-Mx pending flag */ +void HAL_PWREx_ClearPendingEvent (void); +#if defined (DUAL_CORE) +/* Clear domain flags */ +void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags); +/* Core Hold/Release functions */ +HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU); +void HAL_PWREx_ReleaseCore (uint32_t CPU); +#endif /* defined (DUAL_CORE) */ +/* Flash low power control functions */ +void HAL_PWREx_EnableFlashPowerDown (void); +void HAL_PWREx_DisableFlashPowerDown (void); +#if defined (PWR_CR1_SRDRAMSO) +/* Memory shut-off functions */ +void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); +void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); +#endif /* defined(PWR_CR1_SRDRAMSO) */ +/* Wakeup Pins control functions */ +void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams); +void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); +uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); +HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); +/* Power Wakeup PIN IRQ Handler */ +void HAL_PWREx_WAKEUP_PIN_IRQHandler (void); +void HAL_PWREx_WKUP1_Callback (void); +void HAL_PWREx_WKUP2_Callback (void); +#if defined (PWR_WKUPEPR_WKUPEN3) +void HAL_PWREx_WKUP3_Callback (void); +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +void HAL_PWREx_WKUP4_Callback (void); +#if defined (PWR_WKUPEPR_WKUPEN5) +void HAL_PWREx_WKUP5_Callback (void); +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +void HAL_PWREx_WKUP6_Callback (void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions + * @{ + */ +/* Backup regulator control functions */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void); +/* USB regulator control functions */ +HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void); +HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void); +void HAL_PWREx_EnableUSBVoltageDetector (void); +void HAL_PWREx_DisableUSBVoltageDetector (void); +/* Battery control functions */ +void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue); +void HAL_PWREx_DisableBatteryCharging (void); +#if defined (PWR_CR1_BOOSTE) +/* Analog Booster functions */ +void HAL_PWREx_EnableAnalogBooster (void); +void HAL_PWREx_DisableAnalogBooster (void); +#endif /* PWR_CR1_BOOSTE */ +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions + * @{ + */ +/* Power VBAT/Temperature monitoring functions */ +void HAL_PWREx_EnableMonitoring (void); +void HAL_PWREx_DisableMonitoring (void); +uint32_t HAL_PWREx_GetTemperatureLevel (void); +uint32_t HAL_PWREx_GetVBATLevel (void); +#if defined (PWR_CSR1_MMCVDO) +PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); +#endif /* PWR_CSR1_MMCVDO */ +/* Power AVD configuration functions */ +void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD); +void HAL_PWREx_EnableAVD (void); +void HAL_PWREx_DisableAVD (void); +/* Power PVD/AVD IRQ Handler */ +void HAL_PWREx_PVD_AVD_IRQHandler (void); +void HAL_PWREx_AVDCallback (void); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ + +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +/* Check PWR regulator configuration parameter */ +#if defined (SMPS) +#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) ||\ + ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) + +#else +#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) +#endif /* defined (SMPS) */ + +/* Check PWR regulator configuration in STOP mode parameter */ +#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\ + ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\ + ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) + +/* Check PWR domain parameter */ +#if defined (PWR_CPUCR_PDDS_D2) +#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ + ((DOMAIN) == PWR_D2_DOMAIN) ||\ + ((DOMAIN) == PWR_D3_DOMAIN)) +#else +#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ + ((DOMAIN) == PWR_D3_DOMAIN)) +#endif /* defined (PWR_CPUCR_PDDS_D2) */ + +/* Check D3/SRD domain state parameter */ +#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\ + ((STATE) == PWR_D3_DOMAIN_RUN)) + +/* Check wake up pin parameter */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN3) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN5) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW)) +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ + +/* Check wake up pin polarity parameter */ +#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\ + ((POLARITY) == PWR_PIN_POLARITY_LOW)) + +/* Check wake up pin pull configuration parameter */ +#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\ + ((PULL) == PWR_PIN_PULL_UP) ||\ + ((PULL) == PWR_PIN_PULL_DOWN)) + +/* Check wake up flag parameter */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ + ((FLAG) == PWR_WAKEUP_FLAG2) ||\ + ((FLAG) == PWR_WAKEUP_FLAG3) ||\ + ((FLAG) == PWR_WAKEUP_FLAG4) ||\ + ((FLAG) == PWR_WAKEUP_FLAG5) ||\ + ((FLAG) == PWR_WAKEUP_FLAG6) ||\ + ((FLAG) == PWR_WAKEUP_FLAG_ALL)) +#else +#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ + ((FLAG) == PWR_WAKEUP_FLAG2) ||\ + ((FLAG) == PWR_WAKEUP_FLAG4) ||\ + ((FLAG) == PWR_WAKEUP_FLAG6) ||\ + ((FLAG) == PWR_WAKEUP_FLAG_ALL)) +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ + +/* Check wake up flag parameter */ +#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\ + ((LEVEL) == PWR_AVDLEVEL_1) ||\ + ((LEVEL) == PWR_AVDLEVEL_2) ||\ + ((LEVEL) == PWR_AVDLEVEL_3)) + +/* Check AVD mode parameter */ +#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_NORMAL) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING)) + +/* Check resistor battery parameter */ +#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) +/* Check D1/CD CPU ID parameter */ +#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID) + +#if defined (DUAL_CORE) +/* Check CPU parameter */ +#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) + +/* Check D2 CPU ID parameter */ +#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID) + +/* Check PWR domain flag parameter */ +#define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \ + ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \ + ((FLAG) == PWR_ALL_DOMAIN_FLAGS)) +#endif /* defined (DUAL_CORE) */ + +#if defined (PWR_CR1_SRDRAMSO) +/* Check memory block parameter */ +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK)) +#endif /* defined (PWR_CR1_SRDRAMSO) */ +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32H7xx_HAL_PWR_EX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h new file mode 100644 index 0000000..564a8a0 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h @@ -0,0 +1,8266 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_RCC_H +#define STM32H7xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + or between Min_Data = 8 and Max_Data = 420(*) + (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ + + uint32_t PLLP; /*!< PLLP: Division factor for system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + uint32_t PLLRGE; /*!AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* JPEG */ + +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI2 */ +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXMMU */ +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) +#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) +#endif /* JPEG */ +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN)) +#endif /* OCTOSPII */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN)) +#endif /* OCTOSPI2 */ +#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN)) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN)) +#endif /* OTOFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN)) +#endif /* OTOFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN)) +#endif /* GFXMMU */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U) +#endif /* JPEG */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U) +#if defined (QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U) +#endif /* OCTOSPII */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U) +#endif /* OCTOSPI2 */ +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U) +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U) +#endif /* OTOFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U) +#endif /* OTOFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U) +#endif /* GFXMMU */ + +#define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U) +#endif /* JPEG */ +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U) +#if defined (QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U) +#endif /* QUADSPI */ +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U) +#endif +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U) +#endif +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U) +#endif +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U) +#endif +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U) +#endif +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U) +#endif +/** @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DUAL_CORE*/ + +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) +#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) +#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) +#endif +#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) +#endif /* USB2_OTG_FS */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U) +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) != 0U) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U) +#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U) +#endif +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U) +#endif /* USB2_OTG_FS */ + +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U) +#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) == 0U) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U) +#define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U) +#endif +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U) +#endif /* USB2_OTG_FS */ + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* DCMI && PSSI */ + +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRYP */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* FMAC */ + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CORDIC */ + +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) +#else +#define __HAL_RCC_AHBSRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ + +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#else +#define __HAL_RCC_AHBSRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ + +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_HSEMEN */ + +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* BDMA1 */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN)) +#define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_FMACEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CORDICEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN)) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN)) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN)) +#endif + +/** @brief Get the enable or disable status of the AHB2 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) != 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) != 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U) +#endif + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) == 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) == 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U) +#endif + +/** @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOI */ + +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_BDMA_CLK_ENABLE() __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) +#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN) +#define __HAL_RCC_BDMA_CLK_DISABLE() __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN) +#endif +#define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) + + +/** @brief Get the enable or disable status of the AHB4 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U) +#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U) +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U) +#define __HAL_RCC_BDMA_IS_CLK_ENABLED() __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U) +#endif +#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U) + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U) +#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U) + +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U) +#define __HAL_RCC_BDMA_IS_CLK_DISABLED() __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U) +#endif +#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U) + + +/** @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DSI*/ + +#define __HAL_RCC_WWDG1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) + +/** @brief Get the enable or disable status of the APB3 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) != 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U) +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) == 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U) + + +/** @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C5 */ + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DAC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDIOS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM23 */ + +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM24 */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C5EN) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) +#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) +#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) +#define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) +#define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) +#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) +#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM23EN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM24EN) +#endif /* TIM24 */ + + +/** @brief Get the enable or disable status of the APB1 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) != 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) != 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U) +#define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U) +#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U) +#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U) +#define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U) +#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) != 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) != 0U) +#endif /* TIM24 */ + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) == 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) == 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U) +#define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U) +#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U) +#define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U) +#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) == 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) == 0U) +#endif /* TIM24 */ + + +/** @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*UART9*/ + +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*USART10*/ + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*SAI2*/ + +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*SAI3*/ + +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) +#endif /*SAI2*/ +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) +#endif /*HRTIM*/ + +/** @brief Get the enable or disable status of the APB2 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U) +#endif /*SAI2*/ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U) +#endif /* SAI3 */ +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U) +#endif /*SAI2*/ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U) +#endif /*HRTIM1*/ + +/** @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM5 */ + +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* DAC2 */ + +#define __HAL_RCC_COMP12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAI4 */ + +#define __HAL_RCC_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DTS*/ + +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) +#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) +#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) +#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) +#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) +#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) +#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN) +#endif /*DFSDM2*/ + +/** @brief Get the enable or disable status of the APB4 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U) +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U) +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U) +#define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U) +#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U) +#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U) +#define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U) +#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U) +#endif /*DFSDM2*/ + +#if defined(DUAL_CORE) + +/* Exported macros for RCC_C1 -------------------------------------------------*/ + +/** @brief Enable or disable the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_MDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + + + + +#define __HAL_RCC_C1_MDMA_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) +#define __HAL_RCC_C1_DMA2D_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) +#define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) +#define __HAL_RCC_C1_FMC_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_C1_QSPI_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) +#define __HAL_RCC_C1_SDMMC1_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) + + + + +/** @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ART_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ETH1TX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ETH1RX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DMA1_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_C1_DMA2_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_C1_ADC12_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) +#define __HAL_RCC_C1_ART_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) +#define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) +#define __HAL_RCC_C1_ETH1TX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) +#define __HAL_RCC_C1_ETH1RX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRYP */ + +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ +#define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) +#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) +#define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) +#define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) + +/** @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_BDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_GPIOA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) +#define __HAL_RCC_C1_GPIOB_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) +#define __HAL_RCC_C1_GPIOC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) +#define __HAL_RCC_C1_GPIOD_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) +#define __HAL_RCC_C1_GPIOE_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) +#define __HAL_RCC_C1_GPIOF_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) +#define __HAL_RCC_C1_GPIOG_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) +#define __HAL_RCC_C1_GPIOH_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) +#define __HAL_RCC_C1_GPIOI_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) +#define __HAL_RCC_C1_GPIOJ_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) +#define __HAL_RCC_C1_GPIOK_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) +#define __HAL_RCC_C1_CRC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_C1_BDMA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) +#define __HAL_RCC_C1_ADC3_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) +#define __HAL_RCC_C1_HSEM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_C1_BKPRAM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) + + +/** @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_WWDG1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LTDC_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) +#define __HAL_RCC_C1_DSI_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) +#define __HAL_RCC_C1_WWDG1_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) + +/** @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_WWDG2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DAC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SWPMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_MDIOS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_TIM2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) +#define __HAL_RCC_C1_TIM3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) +#define __HAL_RCC_C1_TIM4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) +#define __HAL_RCC_C1_TIM5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) +#define __HAL_RCC_C1_TIM6_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) +#define __HAL_RCC_C1_TIM7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) +#define __HAL_RCC_C1_TIM12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) +#define __HAL_RCC_C1_TIM13_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) +#define __HAL_RCC_C1_TIM14_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) +#define __HAL_RCC_C1_LPTIM1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) +#define __HAL_RCC_C1_WWDG2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) +#define __HAL_RCC_C1_SPI2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) +#define __HAL_RCC_C1_SPI3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) +#define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) +#define __HAL_RCC_C1_USART2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) +#define __HAL_RCC_C1_USART3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) +#define __HAL_RCC_C1_UART4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) +#define __HAL_RCC_C1_UART5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) +#define __HAL_RCC_C1_I2C1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) +#define __HAL_RCC_C1_I2C2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) +#define __HAL_RCC_C1_I2C3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) +#define __HAL_RCC_C1_CEC_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) +#define __HAL_RCC_C1_DAC12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) +#define __HAL_RCC_C1_UART7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) +#define __HAL_RCC_C1_UART8_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) +#define __HAL_RCC_C1_CRS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) +#define __HAL_RCC_C1_SWPMI_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) +#define __HAL_RCC_C1_OPAMP_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) +#define __HAL_RCC_C1_MDIOS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) +#define __HAL_RCC_C1_FDCAN_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) + +/** @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) +#define __HAL_RCC_C1_TIM8_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) +#define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) +#define __HAL_RCC_C1_USART6_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) +#define __HAL_RCC_C1_SPI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) +#define __HAL_RCC_C1_SPI4_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) +#define __HAL_RCC_C1_TIM15_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) +#define __HAL_RCC_C1_TIM16_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) +#define __HAL_RCC_C1_TIM17_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) +#define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) +#define __HAL_RCC_C1_SAI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) +#define __HAL_RCC_C1_SAI2_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) +#define __HAL_RCC_C1_SAI3_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) +#define __HAL_RCC_C1_DFSDM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) +#define __HAL_RCC_C1_HRTIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) + +/** @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_COMP12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_SYSCFG_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) +#define __HAL_RCC_C1_LPUART1_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) +#define __HAL_RCC_C1_SPI6_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) +#define __HAL_RCC_C1_I2C4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) +#define __HAL_RCC_C1_LPTIM2_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) +#define __HAL_RCC_C1_LPTIM3_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) +#define __HAL_RCC_C1_LPTIM4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) +#define __HAL_RCC_C1_LPTIM5_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) +#define __HAL_RCC_C1_COMP12_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) +#define __HAL_RCC_C1_VREF_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) +#define __HAL_RCC_C1_RTC_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) +#define __HAL_RCC_C1_SAI4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) + +/* Exported macros for RCC_C2 -------------------------------------------------*/ + +/** @brief Enable or disable the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + + +#define __HAL_RCC_C2_MDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FLASH_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DTCM1_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DTCM2_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ITCM_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_D1SRAM1_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + + + + +#define __HAL_RCC_C2_MDMA_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) +#define __HAL_RCC_C2_DMA2D_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) +#define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) +#define __HAL_RCC_C2_FMC_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_C2_QSPI_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) +#define __HAL_RCC_C2_SDMMC1_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) +#define __HAL_RCC_FLASH_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN)) +#define __HAL_RCC_DTCM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN)) +#define __HAL_RCC_DTCM2_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN)) +#define __HAL_RCC_ITCM_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN)) +#define __HAL_RCC_D1SRAM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN)) + +/** @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ART_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ETH1TX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ETH1RX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C2_DMA1_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_C2_DMA2_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_C2_ADC12_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) +#define __HAL_RCC_C2_ART_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) +#define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) +#define __HAL_RCC_C2_ETH1TX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) +#define __HAL_RCC_C2_ETH1RX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRYP */ + +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ +#define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) +#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) +#define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) +#define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) + +/** @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_BDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C2_GPIOA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) +#define __HAL_RCC_C2_GPIOB_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) +#define __HAL_RCC_C2_GPIOC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) +#define __HAL_RCC_C2_GPIOD_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) +#define __HAL_RCC_C2_GPIOE_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) +#define __HAL_RCC_C2_GPIOF_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) +#define __HAL_RCC_C2_GPIOG_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) +#define __HAL_RCC_C2_GPIOH_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) +#define __HAL_RCC_C2_GPIOI_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) +#define __HAL_RCC_C2_GPIOJ_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) +#define __HAL_RCC_C2_GPIOK_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) +#define __HAL_RCC_C2_CRC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_C2_BDMA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) +#define __HAL_RCC_C2_ADC3_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) +#define __HAL_RCC_C2_HSEM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_C2_BKPRAM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) + + +/** @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_WWDG1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LTDC_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) +#define __HAL_RCC_C2_DSI_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) +#define __HAL_RCC_C2_WWDG1_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) + +/** @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_WWDG2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DAC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SWPMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_MDIOS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C2_TIM2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) +#define __HAL_RCC_C2_TIM3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) +#define __HAL_RCC_C2_TIM4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) +#define __HAL_RCC_C2_TIM5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) +#define __HAL_RCC_C2_TIM6_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) +#define __HAL_RCC_C2_TIM7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) +#define __HAL_RCC_C2_TIM12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) +#define __HAL_RCC_C2_TIM13_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) +#define __HAL_RCC_C2_TIM14_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) +#define __HAL_RCC_C2_LPTIM1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) +#define __HAL_RCC_C2_WWDG2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) +#define __HAL_RCC_C2_SPI2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) +#define __HAL_RCC_C2_SPI3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) +#define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) +#define __HAL_RCC_C2_USART2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) +#define __HAL_RCC_C2_USART3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) +#define __HAL_RCC_C2_UART4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) +#define __HAL_RCC_C2_UART5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) +#define __HAL_RCC_C2_I2C1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) +#define __HAL_RCC_C2_I2C2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) +#define __HAL_RCC_C2_I2C3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) +#define __HAL_RCC_C2_CEC_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) +#define __HAL_RCC_C2_DAC12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) +#define __HAL_RCC_C2_UART7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) +#define __HAL_RCC_C2_UART8_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) +#define __HAL_RCC_C2_CRS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) +#define __HAL_RCC_C2_SWPMI_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) +#define __HAL_RCC_C2_OPAMP_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) +#define __HAL_RCC_C2_MDIOS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) +#define __HAL_RCC_C2_FDCAN_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) + +/** @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) +#define __HAL_RCC_C2_TIM8_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) +#define __HAL_RCC_C2_USART1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) +#define __HAL_RCC_C2_USART6_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) +#define __HAL_RCC_C2_SPI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) +#define __HAL_RCC_C2_SPI4_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) +#define __HAL_RCC_C2_TIM15_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) +#define __HAL_RCC_C2_TIM16_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) +#define __HAL_RCC_C2_TIM17_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) +#define __HAL_RCC_C2_SPI5_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) +#define __HAL_RCC_C2_SAI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) +#define __HAL_RCC_C2_SAI2_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) +#define __HAL_RCC_C2_SAI3_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) +#define __HAL_RCC_C2_DFSDM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) +#define __HAL_RCC_C2_HRTIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) + +/** @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_COMP12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\ + UNUSED(tmpreg); \ + } while(0) + + + +#define __HAL_RCC_C2_SYSCFG_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) +#define __HAL_RCC_C2_LPUART1_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) +#define __HAL_RCC_C2_SPI6_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) +#define __HAL_RCC_C2_I2C4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) +#define __HAL_RCC_C2_LPTIM2_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) +#define __HAL_RCC_C2_LPTIM3_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) +#define __HAL_RCC_C2_LPTIM4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) +#define __HAL_RCC_C2_LPTIM5_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) +#define __HAL_RCC_C2_COMP12_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) +#define __HAL_RCC_C2_VREF_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) +#define __HAL_RCC_C2_RTC_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) +#define __HAL_RCC_C2_SAI4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) + +#endif /*DUAL_CORE*/ + +/** @brief Enable or disable the AHB3 peripheral reset. + */ + +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00015031U) /* Resets MDMA, DMA2D, JPEG, FMC, QSPI and SDMMC1 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x01E95031U) /* Resets MDMA, DMA2D, JPEG, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 and GFXMMU */ +#else +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST)) +#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST)) +#if defined(JPEG) +#define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST)) +#endif /* JPEG */ +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) +#endif /*QUADSPI*/ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST)) +#endif /*OCTOSPI1*/ +#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST)) +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST)) +#endif /*GFXMMU*/ + +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) +#define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST)) +#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST)) +#if defined(JPEG) +#define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST)) +#endif /* JPEG */ +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST)) +#endif /*QUADSPI*/ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST)) +#endif /*OCTOSPI1*/ +#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST)) +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST)) +#endif /*GFXMMU*/ + + + +/** @brief Force or release the AHB1 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0A00C023U) /* Resets DMA1, DMA2, ADC12, ART, ETHMAC, USB1OTG and USB2OTG */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02000223U) /* Resets DMA1, DMA2, ADC12, CRC and USB1OTG */ +#else +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST)) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST)) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1RSTR_CRCRST) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST)) +#endif /*USB2_OTG_FS*/ + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST)) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST)) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1RSTR_CRCRST) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST)) +#endif /*USB2_OTG_FS*/ + +/** @brief Force or release the AHB2 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000271U) /* Resets DCMI, CRYPT, HASH, RNG and SDMMC2 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000A75U) /* Resets DCMI_PSSI, HSEM, CRYPT, HASH, RNG, SDMMC2 and BDMA1 */ +#else +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) +#endif /* HASH */ +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_FMACRST)) +#endif /*FMAC*/ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CORDICRST)) +#endif /*CORDIC*/ +#if defined(RCC_AHB2RSTR_HSEMRST) +#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST)) +#endif /*BDMA1*/ + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST)) +#endif /* HASH */ +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_FMACRST)) +#endif /*FMAC*/ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CORDICRST)) +#endif /*CORDIC*/ +#if defined(RCC_AHB2RSTR_HSEMRST) +#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST)) +#endif /*BDMA1*/ + + +/** @brief Force or release the AHB4 peripheral reset. + */ + +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032807FFU) /* Resets GPIOA..GPIOK, CRC, BDMA, ADC3 and HSEM */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x002007FFU) /* Resets GPIOA..GPIOK and BDMA2 */ +#else +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST) +#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST) +#if defined(RCC_AHB4RSTR_CRCRST) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST) +#define __HAL_RCC_BDMA_FORCE_RESET() __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST) +#endif /*ADC3*/ +#if defined(RCC_AHB4RSTR_HSEMRST) +#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST) +#endif + +#define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST) +#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST) +#if defined(RCC_AHB4RSTR_CRCRST) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST) +#define __HAL_RCC_BDMA_RELEASE_RESET() __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST) +#endif /*ADC3*/ +#if defined(RCC_AHB4RSTR_HSEMRST) +#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST) +#endif + +/** @brief Force or release the APB3 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000018U) /* Rests LTDC and DSI */ +#else +#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST) +#endif /*DSI*/ + +#define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U) +#if defined(LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST) +#endif /*DSI*/ + +/** @brief Force or release the APB1 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xE8FFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, CEC, DAC1(2), UART7 and UART8 */ +#else +#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x00000136U) /* Resets CRS, SWP, OPAMP, MDIOS and FDCAN */ +#else +#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C5RST) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST) +#define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST) +#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST) +#define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST) +#define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST) +#define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST) +#define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST) +#if defined(TIM23) +#define __HAL_RCC_TIM23_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM23RST) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM24RST) +#endif /* TIM24 */ + +#define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U) +#define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST) +#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C5RST) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST) +#define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST) +#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST) +#define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST) +#define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST) +#define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST) +#define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST) +#if defined(TIM23) +#define __HAL_RCC_TIM23_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM23RST) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM24RST) +#endif /* TIM24 */ + +/** @brief Force or release the APB2 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x31D73033U) /* Resets TIM1, TIM8, USART1, USART6, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1..SAI3, DFSDM1 and HRTIM */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x40D730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1, SAI2 and DFSDM1 */ +#else +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST) +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST) +#if defined(UART9) +#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST) +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) +#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST) +#endif /*HRTIM1*/ + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST) +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST) +#if defined(UART9) +#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST) +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) +#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST) +#endif /*HRTIM1*/ + +/** @brief Force or release the APB4 peripheral reset. + */ + +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0020DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF and SAI4 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0C00E6AAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2, LPTIM3, DAC2, COMP12, VREF, DTS and DFSDM2 */ +#else +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST) +#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST) +#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST) +#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST) +#define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST) +#define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST) +#define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST) +#if defined(SAI4) +#define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST) +#endif /*DFSDM2*/ + +#define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST) +#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST) +#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST) +#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST) +#define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST) +#define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST) +#endif /*LPTIM5*/ +#if defined(RCC_APB4RSTR_DAC2RST) +#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST) +#endif +#define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST) +#define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST) +#if defined(SAI4) +#define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST) +#endif /*DFSDM2*/ + +/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + + +#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN)) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN)) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN)) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN)) +#endif +#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) +#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE +#else +#define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN)) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE /* For backward compatibility */ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ + +#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN)) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN)) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN)) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN)) +#endif +#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) +#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE +#else +#define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN)) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE /* For backward compatibility */ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U) +#endif +#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U) +#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U) +#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U) +#else +#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U) +#endif + +#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U) +#endif +#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U) +#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U) +#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U) +#else +#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U) +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ + +/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) +#endif /*ETH*/ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN)) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) +#endif /* USB2_OTG_FS */ + +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) +#endif /*ETH*/ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN)) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) +#endif /* USB2_OTG_FS */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U) +#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U) +#endif /*ETH*/ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) != 0U) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U) +#endif /* USB2_OTG_FS */ + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U) +#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U) +#endif /* ETH */ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) == 0U) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U) +#endif /* ETH */ +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U) +#endif /* USB2_OTG_FS */ + + +/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN)) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_FMACLPEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CORDICLPEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) +#endif + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN)) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_FMACLPEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CORDICLPEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) +#endif + +/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) != 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) != 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM3LPEN */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U) +#endif +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) == 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) == 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/ + + +/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN) +#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) +#endif /* BDMA2 */ +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) +#endif /* ADC3 */ +#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN)) +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/ +#else +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) +#endif /* RCC_AHB4LPENR_SRDSRAMLPEN */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN) +#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) +#endif /*ADC3*/ +#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN)) +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE +#else +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) +#endif + + +/** @brief Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U) +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U) +#endif /*ADC3*/ +#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U) +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U) +#endif + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U) +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U) +#endif /*ADC3*/ +#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U) +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U) +#endif + + +/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) + + +/** @brief Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) != 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U) + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) == 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U) + + +/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C5LPEN) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM23LPEN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM24LPEN) +#endif /* TIM24 */ + + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C5LPEN) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM23LPEN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM24LPEN) +#endif /* TIM24 */ + + +/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) != 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) != 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U) +#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U) +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U) +#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) != 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) != 0U) +#endif /* TIM24 */ + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) == 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) == 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U) +#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U) +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U) +#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) == 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) == 0U) +#endif /* TIM24 */ + + +/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) +#endif /*HRTIM1*/ + + +/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U) +#if defined(UART9) +#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U) +#endif /*HRTIM1*/ + +/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN) +#endif /*DFSDM2*/ + + +/** @brief Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U) +#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U) +#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U) +#endif /*DFSDM2*/ + + +#if defined(DUAL_CORE) + +/** @brief Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) + + +#define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) + + + +/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +#define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) + +#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) + +/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) + +#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) + +/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) + +#define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) + +/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) + + +#define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) + +/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) + +#define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) + +/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) + + +#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) + +/** @brief Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + + +#define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) + + +#define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) + + + +/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +#define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) + +#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) + +/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) + +#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) + +/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) + +#define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) + +/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) + + +#define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) + +/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) + +#define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) + +/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) + +#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) + +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +/** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN + * @note After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP + */ +#else +/** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN + * @note After reset (default config), peripheral clock is disabled when CPU is in CSTOP + */ +#endif /*DUAL_CORE*/ + +#if defined(RCC_D3AMR_BDMAAMEN) +#define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN) +#endif +#if defined(RCC_D3AMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN) +#endif +#if defined(RCC_D3AMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN) +#endif +#if defined(RCC_D3AMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN) +#endif +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN) +#endif +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN) +#endif +#if defined(RCC_D3AMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN) +#endif +#if defined(RCC_D3AMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN) +#endif +#if defined(RCC_D3AMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN) +#endif +#if defined(RCC_D3AMR_CRCAMEN) +#define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN) +#endif +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN) +#endif +#if defined(RCC_D3AMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_DTSAMEN) +#endif +#if defined(RCC_D3AMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN) +#endif +#if defined(RCC_D3AMR_SRAM4AMEN) +#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN) +#endif + +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN) +#endif +#if defined(RCC_SRDAMR_GPIOAMEN) +#define __HAL_RCC_GPIO_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN) +#endif +#if defined(RCC_SRDAMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN) +#endif +#if defined(RCC_SRDAMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN) +#endif +#if defined(RCC_SRDAMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN) +#endif +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN) +#endif +#if defined(RCC_SRDAMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN) +#endif +#if defined(RCC_SRDAMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN) +#endif +#if defined(RCC_SRDAMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN) +#endif +#if defined(RCC_SRDAMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN) +#endif +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN) +#endif +#if defined(RCC_SRDAMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN) +#endif +#if defined(RCC_SRDAMR_SRDSRAMAMEN) +#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN) +#endif + +#if defined(RCC_D3AMR_BDMAAMEN) +#define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN) +#endif +#if defined(RCC_D3AMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN) +#endif +#if defined(RCC_D3AMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN) +#endif +#if defined(RCC_D3AMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN) +#endif +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN) +#endif +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN) +#endif +#if defined(RCC_D3AMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN) +#endif +#if defined(RCC_D3AMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN) +#endif +#if defined(RCC_D3AMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN) +#endif +#if defined(RCC_D3AMR_CRCAMEN) +#define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN) +#endif +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN) +#endif +#if defined(RCC_D3AMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_DTSAMEN) +#endif +#if defined(RCC_D3AMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN) +#endif +#if defined(RCC_D3AMR_SRAM4AMEN) +#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN) +#endif + +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN) +#endif +#if defined(RCC_SRDAMR_GPIOAMEN) +#define __HAL_RCC_GPIO_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN) +#endif +#if defined(RCC_SRDAMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN) +#endif +#if defined(RCC_SRDAMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN) +#endif +#if defined(RCC_SRDAMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN) +#endif +#if defined(RCC_SRDAMR_DAC2AMEN) +#define __HAL_RCC_DAC2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN) +#endif +#if defined(RCC_SRDAMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN) +#endif +#if defined(RCC_SRDAMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN) +#endif +#if defined(RCC_SRDAMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN) +#endif +#if defined(RCC_SRDAMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN) +#endif +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN) +#endif +#if defined(RCC_SRDAMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN) +#endif +#if defined(RCC_SRDAMR_SRDSRAMAMEN) +#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN) +#endif + + +#if defined(RCC_CKGAENR_AXICKG) +/** @brief Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register). + */ + +#define __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG) +#define __HAL_RCC_AHB_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG) +#define __HAL_RCC_CPU_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG) +#define __HAL_RCC_SDMMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG) +#define __HAL_RCC_MDMA_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG) +#define __HAL_RCC_DMA2D_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG) +#define __HAL_RCC_LTDC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG) +#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG) +#define __HAL_RCC_AHB12_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG) +#define __HAL_RCC_AHB34_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG) +#define __HAL_RCC_FLIFT_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG) +#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG) +#define __HAL_RCC_FMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG) +#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG) +#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG) +#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG) +#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG) +#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG) +#define __HAL_RCC_ECCRAM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG) +#define __HAL_RCC_EXTI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG) +#define __HAL_RCC_JTAG_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG) + + +#define __HAL_RCC_AXI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG) +#define __HAL_RCC_AHB_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG) +#define __HAL_RCC_CPU_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG) +#define __HAL_RCC_SDMMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG) +#define __HAL_RCC_MDMA_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG) +#define __HAL_RCC_DMA2D_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG) +#define __HAL_RCC_LTDC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG) +#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG) +#define __HAL_RCC_AHB12_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG) +#define __HAL_RCC_AHB34_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG) +#define __HAL_RCC_FLIFT_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG) +#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG) +#define __HAL_RCC_FMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG) +#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG) +#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG) +#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG) +#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG) +#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG) +#define __HAL_RCC_ECCRAM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG) +#define __HAL_RCC_EXTI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG) +#define __HAL_RCC_JTAG_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG) + +#endif /* RCC_CKGAENR_AXICKG */ + + + + +/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). + * @note After enabling the HSI, the application software should wait on + * HSIRDY flag to be set indicating that HSI clock is stable and can + * be used to clock the PLL and/or system clock. + * @note HSI can not be stopped if it is used directly or through the PLL + * as system clock. In this case, you have to select another source + * of the system clock then stop the HSI. + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @param __STATE__ specifies the new state of the HSI. + * This parameter can be one of the following values: + * @arg RCC_HSI_OFF turn OFF the HSI oscillator + * @arg RCC_HSI_ON turn ON the HSI oscillator + * @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset) + * @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2 + * @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4 + * @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8 + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_CONFIG(__STATE__) \ + MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__)) + + +/** @brief Macro to get the HSI divider. + * @retval The HSI divider. The returned value can be one + * of the following: + * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset) + * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 + * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 + * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 + */ +#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after start-up + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICalibrationValue__: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x7F (3F for Rev Y device). + */ +#if defined(RCC_VER_X) +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ + do { \ + if(HAL_GetREVID() <= REV_ID_Y) \ + { \ + if((__HSICalibrationValue__) == RCC_HSICALIBRATION_DEFAULT) \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, ((uint32_t)0x20) << HAL_RCC_REV_Y_HSITRIM_Pos); \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos); \ + } \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \ + } \ + } while(0) + +#else +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); +#endif /*RCC_VER_X*/ +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for some peripherals. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI start-up time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + + +/** + * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). + * @note After enabling the HSI48, the application software should wait on + * HSI48RDY flag to be set indicating that HSI48 clock is stable and can + * be used to clock the USB. + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON); + +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); + +/** + * @brief Macros to enable or disable the Internal oscillator (CSI). + * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after + * start-up from Reset, wakeup from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note CSI can not be stopped if it is used as system clock source. + * In this case, you have to select another source of the system + * clock then stop the CSI. + * @note After enabling the CSI, the application software should wait on + * CSIRDY flag to be set indicating that CSI clock is stable and can + * be used as system clock source. + * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator + * clock cycles. + */ +#define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) +#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) + +/** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal CSI RC. + * @param __CSICalibrationValue__: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + */ +#if defined(RCC_VER_X) +#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ + do { \ + if(HAL_GetREVID() <= REV_ID_Y) \ + { \ + if((__CSICalibrationValue__) == RCC_CSICALIBRATION_DEFAULT) \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, ((uint32_t)0x10) << HAL_RCC_REV_Y_CSITRIM_Pos); \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \ + } \ + } \ + else \ + { \ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ + } \ + } while(0) + +#else +#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ + do { \ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ + } while(0) + +#endif /*RCC_VER_X*/ +/** + * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the CSI start-up time. + * @note The enable of this function has not effect on the CSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) +#define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) + + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + +/** + * @brief Macro to configure the External High Speed oscillator (__HSE__). + * @note After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL), + * the application software should wait on HSERDY flag to be set indicating + * that HSE clock is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator. + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. + * @arg RCC_HSE_BYPASS_DIGITAL: HSE oscillator bypassed with digital external clock. (*) + * + * (*): Only available on stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + */ +#if defined(RCC_CR_HSEEXT) +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + } \ + } while(0) +#else +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0) +#endif /* RCC_CR_HSEEXT */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). + A duty cycle close to 50% is recommended. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @note If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*) + * @param __STATE__: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator. + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. + * @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*) + * + * (*) Available on some STM32H7 lines only. + */ +#if defined(RCC_BDCR_LSEEXT) +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + } \ + } while(0) +#else + +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) + +#endif /* RCC_BDCR_LSEEXT */ +/** + * @} + */ + +/** @brief Macros to enable or disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) + +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ + RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ + } while (0) + +#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) + + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) + +/** + * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) + * @note Enabling/disabling those Clocks can be done only when the PLL is disabled. + * This is mainly used to save Power. + * (The ck_pll_p of the System PLL cannot be stopped if used as System Clock). + * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) + +#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) + + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 + * @retval None + */ +#define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) + +#define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) + + +/** + * @brief Macro to configures the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . + * + * @param __PLLM1__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 4 and 512 or between 8 and 420(*). + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLLP1__: specifies the division factor for system clock. + * This parameter must be a number between 2 or 1(**) and 128 (where odd numbers are not allowed) + * + * @param __PLLQ1__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLLR1__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL1P__, __PLL1Q__ or __PLL1R__ parameters. + * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * (**): For stm32h72xxx and stm32h73xxx family lines. + */ + + +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \ + do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \ + WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \ + ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \ + } while(0) + + +/** @brief Macro to configure the PLLs clock source. + * @note This function must be used only when all PLLs are disabled. + * @param __PLLSOURCE__: specifies the PLLs entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__)) + + +/** + * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO + * + * @param __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO + * It should be a value between 0 and 8191 + * @note Warning: The software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0 + * 150 to 420 MHz if PLL1VCOSEL = 1. + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos) + + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__)) + + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) + + + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_CFGR_SWS_CSI: CSI used as system clock. + * - RCC_CFGR_SWS_HSI: HSI used as system clock. + * - RCC_CFGR_SWS_HSE: HSE used as system clock. + * - RCC_CFGR_SWS_PLL: PLL used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) + + +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC)) + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); + +/** + * @} + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note On STM32H7 Rev.B and above devices this can't be updated while LSE is ON. + * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. + * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. + * @retval None + */ +#if defined(RCC_VER_X) +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + do{ \ + if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) \ + { \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk); \ + } \ + else \ + { \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); \ + } \ + } while(0) +#else +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); +#endif /*RCC_VER_X*/ +/** + * @brief Macro to configure the wake up from stop clock. + * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source + * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source + * @retval None + */ +#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__)) + +/** + * @brief Macro to configure the Kernel wake up from stop clock. + * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source + * @retval None + */ +#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: HSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt + * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: HSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear the RCC's interrupt pending bits + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: CSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_HSECSS: HSE Clock Security interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: CSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_HSECSS: HSE Clock Security interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) + +#if defined(DUAL_CORE) +#define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF) + +#define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +/** @brief Check RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSIDIV: HSI divider flag + * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready + * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready + * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready + * @arg RCC_FLAG_PLLRDY: PLL1 clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_C1RST: CPU reset flag + * @arg RCC_FLAG_C2RST: CPU2 reset flag + * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag + * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag + * @arg RCC_FLAG_BORRST: BOR reset flag + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag + * @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag + * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag + * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset + * @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset + * @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset + * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset + * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag + * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +#define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +#define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +#else + +/** @brief Check RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSIDIV: HSI divider flag + * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready + * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready (*) + * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready (*) + * @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*) + * @arg RCC_FLAG_CDCKRDY: CPU Domain clock ready (*) + * @arg RCC_FLAG_PLLRDY: PLL1 clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_CPURST: CPU reset flag + * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag (*) + * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag (*) + * @arg RCC_FLAG_CDRST: CD domain power switch reset flag (*) + * @arg RCC_FLAG_BORRST: BOR reset flag + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: System reset from CPU reset flag + * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag + * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset + * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset + * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag + * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + * + * (*) Available on some STM32H7 lines only. + */ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos) + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32h7xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ + +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms */ +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */ +#define CSI_TIMEOUT_VALUE (2U) /* 2 ms */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms */ +#define PLL_FRAC_TIMEOUT_VALUE (1U) /* PLL Fractional part waiting time before new latch enable : 1 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ +#define RCC_DBP_TIMEOUT_VALUE (100U) +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ + +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) + +#if defined(RCC_CR_HSEEXT) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL)) +#else +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS)) +#endif /* RCC_CR_HSEEXT */ + +#if defined(RCC_BDCR_LSEEXT) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL)) +#else +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS)) +#endif /* RCC_BDCR_LSEEXT */ + +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \ + ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \ + ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8)) + +#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) + +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) + +#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ + ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_NONE) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1VCIRANGE_0) || \ + ((VALUE) == RCC_PLL1VCIRANGE_1) || \ + ((VALUE) == RCC_PLL1VCIRANGE_2) || \ + ((VALUE) == RCC_PLL1VCIRANGE_3)) + +#define IS_RCC_PLLVCO_VALUE(VALUE) (((VALUE) == RCC_PLL1VCOWIDE) || ((VALUE) == RCC_PLL1VCOMEDIUM)) + +#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U) + +#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#if !defined(RCC_VER_2_0) +#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#else +#define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U)) +#endif /* !RCC_VER_2_0 */ +#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ + ((VALUE) == RCC_PLL1_DIVQ) || \ + ((VALUE) == RCC_PLL1_DIVR)) + +#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \ + ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \ + ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \ + ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \ + ((SYSCLK) == RCC_SYSCLK_DIV512)) + + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \ + ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \ + ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \ + ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \ + ((HCLK) == RCC_HCLK_DIV512)) + +#define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \ + ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \ + ((CDPCLK1) == RCC_APB3_DIV16)) + +#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */ + +#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \ + ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \ + ((PCLK1) == RCC_APB1_DIV16)) + +#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \ + ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \ + ((PCLK2) == RCC_APB2_DIV16)) + +#define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \ + ((SRDPCLK1) == RCC_APB4_DIV4) || ((SRDPCLK1) == RCC_APB4_DIV8) || \ + ((SRDPCLK1) == RCC_APB4_DIV16)) + +#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/ + +#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63)) + +#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI48)) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \ + ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK)) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ + ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ + ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ + ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ + ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ + ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ + ((DIV) == RCC_MCODIV_15)) + +#if defined(DUAL_CORE) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ + ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_C1RST) || ((FLAG) == RCC_FLAG_C2RST) || \ + ((FLAG) == RCC_FLAG_SFTR2ST) || ((FLAG) == RCC_FLAG_WWDG2RST)|| \ + ((FLAG) == RCC_FLAG_IWDG2RST) || ((FLAG) == RCC_FLAG_D1RST) || \ + ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTR1ST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ + ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ + ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV)) + +#else + +#if defined(RCC_CR_D2CKRDY) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ + ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \ + ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ + ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ + ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) +#else +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_CPUCKRDY) || ((FLAG) == RCC_FLAG_CDCKRDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ + ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_CDRST) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ + ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ + ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) +#endif /* RCC_CR_D2CKRDY */ + +#endif /*DUAL_CORE*/ + +#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU) +#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU) + +#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \ + ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI)) + +#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ + ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_RCC_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h new file mode 100644 index 0000000..d39df84 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h @@ -0,0 +1,4482 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_RCC_EX_H +#define STM32H7xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief PLL2 Clock structure definition + */ +typedef struct +{ + + uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + or between Min_Data = 8 and Max_Data = 420(*) + (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ + + uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed */ + + uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + uint32_t PLL2RGE; /*!CR, RCC_CR_PLL2ON) +#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) + +/** + * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) + * @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled, + * This is mainly used to save Power. + * @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) + +#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 + * @retval None + */ +#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) + +#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) + +/** + * @brief Macro to configures the PLL2 multiplication and division factors. + * @note This function must be used only when PLL2 is disabled. + * + * @param __PLL2M__ specifies the division factor for PLL2 VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock + * This parameter must be a number between 4 and 512 or between 8 and 420(*). + * @note You have to set the PLL2N parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLL2P__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @param __PLL2R__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL2P__, __PLL2Q__ or __PLL2R__ parameters. + * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + */ + +#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \ + do{ \ + MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \ + WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \ + ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \ + } while(0) + +/** + * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO + * + * @param __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 + * 150 to 420 MHz if PLL2VCOSEL = 1. + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) + + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) + +/** @brief Macros to enable or disable the main PLL3. + * @note After enabling PLL3, the application software should wait on + * PLL3RDY flag to be set indicating that PLL3 clock is stable and can + * be used as kernel clock source. + * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) +#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 + * @retval None + */ +#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) + +#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) + +/** + * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) + * @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled, + * This is mainly used to save Power. + * @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) + +#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) + +/** + * @brief Macro to configures the PLL3 multiplication and division factors. + * @note This function must be used only when PLL3 is disabled. + * + * @param __PLL3M__ specifies the division factor for PLL3 VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLL3N parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLL3P__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 2 and 128 (where odd numbers not allowed) + * + * @param __PLL3Q__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL3R__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL3P__, __PLL3Q__ or __PLL3R__ parameters. + * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + */ + +#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \ + do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \ + WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \ + ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \ + } while(0) + + + +/** + * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO + * + * @param __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 + * 150 to 420 MHz if PLL3VCOSEL = 1. + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) + + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __RCC_PLL3VCORange__ specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) +/** + * @brief Macro to Configure the SAI1 clock source. + * @param __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL + * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 + * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 + * @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC + * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock + * @retval None + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) +#else +#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) +#endif /* RCC_D2CCIP1R_SAI1SEL */ + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL + * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 + * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 + * @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP + * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL))) +#else +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL))) +#endif /* RCC_D2CCIP1R_SAI1SEL */ + +/** + * @brief Macro to Configure the SPDIFRX clock source. + * @param __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived + * from system PLL, PLL2, PLL3, or internal OSC clock + * This parameter can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL + * @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2 + * @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3 + * @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) +#else +#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ + +/** + * @brief Macro to get the SPDIFRX clock source. + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL))) +#else +#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ + +#if defined(SAI3) +/** + * @brief Macro to Configure the SAI2/3 clock source. + * @param __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL + * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 + * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 + * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP + * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__)) + +/** @brief Macro to get the SAI2/3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL + * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 + * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 + * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP + * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock + */ +#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) + +/** + * @brief Macro to Configure the SAI2 clock source. + * @param __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL + * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 + * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 + * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP + * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG + +/** @brief Macro to get the SAI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL + * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 + * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 + * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP + * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock + */ +#define __HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE + +/** + * @brief Macro to Configure the SAI3 clock source. + * @param __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL + * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 + * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 + * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP + * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG + +/** @brief Macro to get the SAI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL + * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 + * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 + * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP + * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock + */ +#define __HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) +/** + * @brief Macro to Configure the SAI2A clock source. + * @param __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL + * @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2 + * @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3 + * @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock = CLKP + * @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock + * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock + * @retval None + */ +#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__)) + +/** @brief Macro to get the SAI2A clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL + * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2 + * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3 + * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock = CLKP + * @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock + * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock + */ +#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL))) +#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) +/** + * @brief Macro to Configure the SAI2B clock source. + * @param __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL + * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 + * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 + * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP + * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock + * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock + * @retval None + */ +#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__)) + +/** @brief Macro to get the SAI2B clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL + * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 + * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 + * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP + * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock + * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock + */ +#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL))) +#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */ + + +#if defined(SAI4_Block_A) +/** + * @brief Macro to Configure the SAI4A clock source. + * @param __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL + * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2 + * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3 + * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP + * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__)) + +/** @brief Macro to get the SAI4A clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL + * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2 + * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3 + * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP + * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock + */ +#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL))) +#endif /* SAI4_Block_A */ + +#if defined(SAI4_Block_B) +/** + * @brief Macro to Configure the SAI4B clock source. + * @param __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL + * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 + * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 + * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP + * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__)) + +/** @brief Macro to get the SAI4B clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL + * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 + * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 + * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP + * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock + */ +#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL))) +#endif /* SAI4_Block_B */ + +/** @brief macro to configure the I2C1/2/3/5* clock (I2C123CLK). + * + * @param __I2C1235CLKSource__ specifies the I2C1/2/3/5* clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock + * + * (**): Available on stm32h72xxx and stm32h73xxx family lines. + */ +#if defined(RCC_D2CCIP2R_I2C123SEL) +#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) +#elif defined(RCC_CDCCIP2R_I2C123SEL) +#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) +#else /* RCC_D2CCIP2R_I2C1235SEL */ +#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) +/* alias */ +#define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG +#endif /* RCC_D2CCIP2R_I2C123SEL */ + +/** @brief macro to get the I2C1/2/3/5* clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock + * + * (**): Available on stm32h72xxx and stm32h73xxx family lines. + */ +#if defined(RCC_D2CCIP2R_I2C123SEL) +#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) +#elif defined(RCC_CDCCIP2R_I2C123SEL) +#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL))) +#else /* RCC_D2CCIP2R_I2C1235SEL */ +#define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) +/* alias */ +#define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#endif /* RCC_D2CCIP2R_I2C123SEL */ + +/** @brief macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1CLKSource__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock + */ +#if defined(I2C5) +#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ + +/** @brief macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock + */ +#if defined(I2C5) +#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ + +/** @brief macro to configure the I2C2 clock (I2C2CLK). + * + * @param __I2C2CLKSource__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock + */ +#if defined(I2C5) +#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ + +/** @brief macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock + */ +#if defined(I2C5) +#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ + +/** @brief macro to configure the I2C3 clock (I2C3CLK). + * + * @param __I2C3CLKSource__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock + */ +#if defined(I2C5) +#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ + +/** @brief macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock + */ +#if defined(I2C5) +#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ + +/** @brief macro to configure the I2C4 clock (I2C4CLK). + * + * @param __I2C4CLKSource__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock + */ +#if defined(RCC_D3CCIPR_I2C4SEL) +#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) +#else +#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) +#endif /* RCC_D3CCIPR_I2C4SEL */ + +/** @brief macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock + */ +#if defined(RCC_D3CCIPR_I2C4SEL) +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) +#else +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL))) +#endif /* RCC_D3CCIPR_I2C4SEL */ + +#if defined(I2C5) +/** @brief macro to configure the I2C5 clock (I2C5CLK). + * + * @param __I2C5CLKSource__ specifies the I2C5 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock + */ +#define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG +#endif /* I2C5 */ + +#if defined(I2C5) +/** @brief macro to get the I2C5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK5 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock + */ +#define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#endif /* I2C5 */ + +/** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK). + * + * @param __USART16910CLKSource__ specifies the USART1/6/9* /10* clock source. + * This parameter can be one of the following values: + * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock + * + * (*) : Available on some STM32H7 lines only. + */ +#if defined(RCC_D2CCIP2R_USART16SEL) +#define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__)) +#elif defined(RCC_CDCCIP2R_USART16910SEL) +#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) +/* alias */ +#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG +#else /* RCC_D2CCIP2R_USART16910SEL */ +#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) +/* alias */ +#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG +#endif /* RCC_D2CCIP2R_USART16SEL */ + +/** @brief macro to get the USART1/6/9* /10* clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock + * + * (*) : Available on some STM32H7 lines only. + */ +#if defined(RCC_D2CCIP2R_USART16SEL) +#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) +#elif defined(RCC_CDCCIP2R_USART16910SEL) +#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL))) +/* alias*/ +#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE +#else /* RCC_D2CCIP2R_USART16910SEL */ +#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) +/* alias */ +#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ + +/** @brief macro to configure the USART234578 clock (USART234578CLK). + * + * @param __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock + */ +#if defined(RCC_D2CCIP2R_USART28SEL) +#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__)) +#else +#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) +#endif /* RCC_D2CCIP2R_USART28SEL */ + +/** @brief macro to get the USART2/3/4/5/7/8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock + */ +#if defined(RCC_D2CCIP2R_USART28SEL) +#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) +#else +#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) +#endif /* RCC_D2CCIP2R_USART28SEL */ + +/** @brief macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1CLKSource__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE + +/** @brief macro to configure the USART2 clock (USART2CLK). + * + * @param __USART2CLKSource__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3CLKSource__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the UART4 clock (UART4CLK). + * + * @param __UART4CLKSource__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the UART5 clock (UART5CLK). + * + * @param __UART5CLKSource__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the USART6 clock (USART6CLK). + * + * @param __USART6CLKSource__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE + +/** @brief macro to configure the UART5 clock (UART7CLK). + * + * @param __UART7CLKSource__ specifies the UART7 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART7 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the UART8 clock (UART8CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +#if defined(UART9) +/** @brief macro to configure the UART9 clock (UART9CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock + */ +#define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the UART9 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock + */ +#define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE +#endif /* UART9 */ + +#if defined(USART10) +/** @brief macro to configure the USART10 clock (USART10CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock + */ +#define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the USART10 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock + */ +#define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE +#endif /* USART10 */ + +/** @brief macro to configure the LPUART1 clock (LPUART1CLK). + * + * @param __LPUART1CLKSource__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock + */ +#if defined (RCC_D3CCIPR_LPUART1SEL) +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) +#else +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) +#endif /* RCC_D3CCIPR_LPUART1SEL */ + +/** @brief macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock + */ +#if defined (RCC_D3CCIPR_LPUART1SEL) +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL))) +#else +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) +#endif /* RCC_D3CCIPR_LPUART1SEL */ + +/** @brief macro to configure the LPTIM1 clock source. + * + * @param __LPTIM1CLKSource__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) +#else +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ + +/** @brief macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL))) +#else +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ + +/** @brief macro to configure the LPTIM2 clock source. + * + * @param __LPTIM2CLKSource__ specifies the LPTIM2 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock + */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) +#else +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ + +/** @brief macro to get the LPTIM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock + */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL))) +#else +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ + +/** @brief macro to configure the LPTIM3/4/5 clock source. + * + * @param __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source. + * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock + */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__)) +#else +#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) +#endif /* RCC_D3CCIPR_LPTIM345SEL */ + +/** @brief macro to get the LPTIM3/4/5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock + */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) +#else +#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) +#endif /* RCC_D3CCIPR_LPTIM345SEL */ + +/** @brief macro to configure the LPTIM3 clock source. + * + * @param __LPTIM3CLKSource__ specifies the LPTIM3 clock source. + * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock + */ +#define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG + +/** @brief macro to get the LPTIM3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock + */ +#define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE + +#if defined(LPTIM4) +/** @brief macro to configure the LPTIM4 clock source. + * + * @param __LPTIM4CLKSource__ specifies the LPTIM4 clock source. + * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock + */ +#define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG + + +/** @brief macro to get the LPTIM4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock + */ +#define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +/** @brief macro to configure the LPTIM5 clock source. + * + * @param __LPTIM5CLKSource__ specifies the LPTIM5 clock source. + * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock + */ +#define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG + + +/** @brief macro to get the LPTIM5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock + */ +#define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE +#endif /* LPTIM5 */ + +#if defined(QUADSPI) +/** @brief macro to configure the QSPI clock source. + * + * @param __QSPICLKSource__ specifies the QSPI clock source. + * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock + */ +#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__)) + + +/** @brief macro to get the QSPI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock + */ +#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL))) +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @brief macro to configure the OSPI clock source. + * + * @param __OSPICLKSource__ specifies the OSPI clock source. + * @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) +#else +#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) +#endif /* RCC_CDCCIPR_OCTOSPISEL */ + +/** @brief macro to get the OSPI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL))) +#else +#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL))) +#endif /* RCC_CDCCIPR_OCTOSPISEL */ +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + + +#if defined(DSI) +/** @brief macro to configure the DSI clock source. + * + * @param __DSICLKSource__ specifies the DSI clock source. + * @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock + * @arg RCC_RCC_DSICLKSOURCE_PLL2 : PLL2_Q Clock clock is selected as DSI byte lane clock + */ +#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__)) + + +/** @brief macro to get the DSI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock + * @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock + */ +#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL))) +#endif /*DSI*/ + +/** @brief macro to configure the FMC clock source. + * + * @param __FMCCLKSource__ specifies the FMC clock source. + * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) +#else +#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) +#endif /* RCC_D1CCIPR_FMCSEL */ + +/** @brief macro to get the FMC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL))) +#else +#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL))) +#endif /* RCC_D1CCIPR_FMCSEL */ + +/** @brief Macro to configure the USB clock (USBCLK). + * @param __USBCLKSource__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock + * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock + * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock + */ +#if defined(RCC_D2CCIP2R_USBSEL) +#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) +#else +#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) +#endif /* RCC_D2CCIP2R_USBSEL */ + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock + * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock + * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock + */ +#if defined(RCC_D2CCIP2R_USBSEL) +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL))) +#else +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL))) +#endif /* RCC_D2CCIP2R_USBSEL */ + +/** @brief Macro to configure the ADC clock + * @param __ADCCLKSource__ specifies the ADC digital interface clock source. + * This parameter can be one of the following values: + * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) +#else +#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) +#endif /* RCC_D3CCIPR_ADCSEL */ + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL))) +#else +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) +#endif /* RCC_D3CCIPR_ADCSEL */ + +/** @brief Macro to configure the SWPMI1 clock + * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock + * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) +#else +#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) +#endif /* RCC_D2CCIP1R_SWPSEL */ + +/** @brief Macro to get the SWPMI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock + * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL))) +#else +#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) +#endif /* RCC_D2CCIP1R_SWPSEL */ + +/** @brief Macro to configure the DFSDM1 clock + * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock + */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) +#else +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock + */ +#if defined (RCC_D2CCIP1R_DFSDM1SEL) +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL))) +#else +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ + +#if defined(DFSDM2_BASE) +/** @brief Macro to configure the DFSDM2 clock + * @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock + * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock + */ +#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__)) + +/** @brief Macro to get the DFSDM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) Clock selected as DFSDM2 clock + * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock + */ +#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL))) +#endif /* DFSDM2 */ + +/** @brief macro to configure the CEC clock (CECCLK). + * + * @param __CECCLKSource__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock + */ +#if defined(RCC_D2CCIP2R_CECSEL) +#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) +#else +#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) +#endif /* RCC_D2CCIP2R_CECSEL */ + +/** @brief macro to get the CEC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock + */ +#if defined(RCC_D2CCIP2R_CECSEL) +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL))) +#else +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL))) +#endif /* RCC_D2CCIP2R_CECSEL */ + +/** @brief Macro to configure the CLKP : Oscillator clock for peripheral + * @param __CLKPSource__ specifies Oscillator clock for peripheral + * This parameter can be one of the following values: + * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) +#else +#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) +#endif /* RCC_D1CCIPR_CKPERSEL */ + +/** @brief Macro to get the Oscillator clock for peripheral source. + * @retval The clock source can be one of the following values: + * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL))) +#else +#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL))) +#endif /* RCC_D1CCIPR_CKPERSEL */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @brief Macro to configure the FDCAN clock + * @param __FDCANCLKSource__ specifies clock source for FDCAN + * This parameter can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) +#else +#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) +#endif /* RCC_D2CCIP1R_FDCANSEL */ + +/** @brief Macro to get the FDCAN clock + * @retval The clock source can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL))) +#else +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL))) +#endif /* RCC_D2CCIP1R_FDCANSEL */ + +#endif /*FDCAN1 || FDCAN2*/ + +/** + * @brief Macro to Configure the SPI1/2/3 clock source. + * @param __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL + * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 + * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 + * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP + * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) +#else +#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) +#endif /* RCC_D2CCIP1R_SPI123SEL */ + +/** @brief Macro to get the SPI1/2/3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL + * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 + * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 + * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP + * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) +#else +#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) +#endif /* RCC_D2CCIP1R_SPI123SEL */ + +/** + * @brief Macro to Configure the SPI1 clock source. + * @param __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL + * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 + * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 + * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP + * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG + +/** @brief Macro to get the SPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL + * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 + * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 + * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP + * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock + */ +#define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE + +/** + * @brief Macro to Configure the SPI2 clock source. + * @param __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL + * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 + * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 + * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP + * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG + +/** @brief Macro to get the SPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL + * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 + * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 + * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP + * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock + */ +#define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE + +/** + * @brief Macro to Configure the SPI3 clock source. + * @param __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL + * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 + * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 + * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP + * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG + +/** @brief Macro to get the SPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL + * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 + * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 + * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP + * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock + */ +#define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE + +/** + * @brief Macro to Configure the SPI4/5 clock source. + * @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 + * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 + * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 + * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI + * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI + * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) +#else +#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) +#endif /* RCC_D2CCIP1R_SPI45SEL */ + +/** @brief Macro to get the SPI4/5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 + * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 + * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 + * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI + * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI + * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE +*/ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) +#else +#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL))) +#endif /* RCC_D2CCIP1R_SPI45SEL */ + +/** + * @brief Macro to Configure the SPI4 clock source. + * @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 + * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 + * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 + * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI + * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI + * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE + * @retval None + */ +#define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG + +/** @brief Macro to get the SPI4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 + * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 + * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 + * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI + * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI + * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE +*/ +#define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE + +/** + * @brief Macro to Configure the SPI5 clock source. + * @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 + * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 + * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 + * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI + * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI + * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE + * @retval None + */ +#define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG + +/** @brief Macro to get the SPI5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 + * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 + * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 + * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI + * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI + * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE +*/ +#define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE + +/** + * @brief Macro to Configure the SPI6 clock source. + * @param __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 + * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 + * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 + * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI + * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI + * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE + * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*) + * + * @retval None + * + * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines. + * + */ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) +#else +#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) +#endif /* RCC_D3CCIPR_SPI6SEL */ + +/** @brief Macro to get the SPI6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 + * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 + * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 + * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI + * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI + * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE + * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN +*/ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL))) +#else +#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL))) +#endif /* RCC_D3CCIPR_SPI6SEL */ + +/** @brief Macro to configure the SDMMC clock + * @param __SDMMCCLKSource__ specifies clock source for SDMMC + * This parameter can be one of the following values: + * @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock + * @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) +#else +#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) +#endif /* RCC_D1CCIPR_SDMMCSEL */ + +/** @brief Macro to get the SDMMC clock + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL))) +#else +#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL))) +#endif /* RCC_D1CCIPR_SDMMCSEL */ + +/** @brief macro to configure the RNG clock (RNGCLK). + * + * @param __RNGCLKSource__ specifies the RNG clock source. + * This parameter can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock + */ +#if defined(RCC_D2CCIP2R_RNGSEL) +#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) +#else +#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) +#endif /* RCC_D2CCIP2R_RNGSEL */ + +/** @brief macro to get the RNG clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock + */ +#if defined(RCC_D2CCIP2R_RNGSEL) +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL))) +#else +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL))) +#endif /* RCC_D2CCIP2R_RNGSEL */ + +#if defined(HRTIM1) +/** @brief Macro to configure the HRTIM1 prescaler clock source. + * @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock + * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock + */ +#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__)) + +/** @brief Macro to get the HRTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock + * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock + */ +#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL))) +#endif /* HRTIM1 */ + +/** @brief Macro to configure the Timers clocks prescalers + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, + * else it is equal to 2 x Frcc_pclkx_d2 (default after reset) + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to 4 x Frcc_pclkx_d2 + */ +#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\ + RCC->CFGR |= (__PRESC__); \ + }while(0) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +#if defined(DUAL_CORE) +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4. + * @retval None + */ +#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4. + * @retval None + */ +#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) +#endif /* DUAL_CORE */ + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) + +#if defined(DUAL_CORE) +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag or not for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) +#endif /* DUAL_CORE */ +/** + * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR + * @retval None + */ + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after pre-scaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + + +/** + * @} + */ + + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); +uint32_t HAL_RCCEx_GetD1PCLK1Freq(void); +uint32_t HAL_RCCEx_GetD3PCLK1Freq(void); +uint32_t HAL_RCCEx_GetD1SysClockFreq(void); +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); +#if defined(DUAL_CORE) +void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); +#endif /*DUAL_CORE*/ +#if defined(RCC_GCR_WW1RSC) +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); +#endif /*RCC_GCR_WW1RSC*/ +/** + * @} + */ + + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ + +#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \ + ((VALUE) == RCC_PLL2_DIVQ) || \ + ((VALUE) == RCC_PLL2_DIVR)) + +#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \ + ((VALUE) == RCC_PLL3_DIVQ) || \ + ((VALUE) == RCC_PLL3_DIVR)) + +#if defined(RCC_D2CCIP2R_USART16SEL) +#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) +#else +#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) +/* alias*/ +#define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ + +#if defined(RCC_D2CCIP2R_USART28SEL) +#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) +#else +#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) +#endif /* RCC_D2CCIP2R_USART28SEL */ + +#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) + +#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) + +#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) + +#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) + +#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) + +#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) + +#define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) + +#define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) + +#if defined(UART9) +#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_UART9CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_HSI)) +#endif + +#if defined(USART10) +#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART10CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_HSI)) +#endif + +#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) + +#if defined(I2C5) +#define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI)) + +#define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE /* For API Backward compatibility */ +#else +#define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C123CLKSOURCE_CSI)) +#endif /*I2C5*/ + +#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C1CLKSOURCE_CSI)) + +#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C2CLKSOURCE_CSI)) + +#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) + +#define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_I2C4CLKSOURCE_CSI)) + +#if defined(I2C5) +#define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C5CLKSOURCE_CSI)) +#endif /*I2C5*/ + +#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \ + ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \ + ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \ + ((SOURCE) == RCC_RNGCLKSOURCE_LSI)) + +#if defined(HRTIM1) +#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \ + ((SOURCE) == RCC_HRTIM1CLK_CPUCLK)) +#endif + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USBCLKSOURCE_HSI48)) + +#define IS_RCC_SAI1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) + +#if defined(SAI3) +#define IS_RCC_SAI23CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN)) + +#define IS_RCC_SAI2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) + + +#define IS_RCC_SAI3CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN)) +#endif + +#if defined(RCC_CDCCIP1R_SAI2ASEL) +#define IS_RCC_SAI2ACLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF)) +#endif + +#if defined(RCC_CDCCIP1R_SAI2BSEL) +#define IS_RCC_SAI2BCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF)) +#endif + +#define IS_RCC_SPI123CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN)) + +#define IS_RCC_SPI1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN)) + +#define IS_RCC_SPI2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN)) + +#define IS_RCC_SPI3CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) + +#define IS_RCC_SPI45CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK2) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) + +#define IS_RCC_SPI4CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK2) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) + +#define IS_RCC_SPI5CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK2)|| \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) + +#if defined(RCC_D3CCIPR_SPI6SEL) +#define IS_RCC_SPI6CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) +#else +#define IS_RCC_SPI6CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN)) +#endif /* RCC_D3CCIPR_SPI6SEL */ + +#if defined(SAI4) +#define IS_RCC_SAI4ACLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN)) + +#define IS_RCC_SAI4BCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN)) +#endif /*SAI4*/ + +#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \ + ((VALUE) == RCC_PLL2VCIRANGE_1) || \ + ((VALUE) == RCC_PLL2VCIRANGE_2) || \ + ((VALUE) == RCC_PLL2VCIRANGE_3)) + +#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \ + ((VALUE) == RCC_PLL3VCIRANGE_1) || \ + ((VALUE) == RCC_PLL3VCIRANGE_2) || \ + ((VALUE) == RCC_PLL3VCIRANGE_3)) + +#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \ + ((VALUE) == RCC_PLL2VCOMEDIUM)) + +#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \ + ((VALUE) == RCC_PLL3VCOMEDIUM)) + +#define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP)) + +#if defined(LPTIM4) +#define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP)) +#endif /* LPTIM4*/ + +#if defined(LPTIM5) +#define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP)) +#endif /*LPTIM5*/ + +#if defined(QUADSPI) +#define IS_RCC_QSPICLK(__SOURCE__) \ + (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP)) +#endif /*QUADSPI*/ + +#if defined(OCTOSPI1) || defined(OCTOSPI1) +#define IS_RCC_OSPICLK(__SOURCE__) \ + (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) +#endif /*OCTOSPI1 || OCTOSPI1*/ + +#if defined(DSI) +#define IS_RCC_DSICLK(__SOURCE__) \ + (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \ + ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2)) +#endif /*DSI*/ + +#define IS_RCC_FMCCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP)) + +#if defined(FDCAN1) || defined(FDCAN2) +#define IS_RCC_FDCANCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2)) +#endif /*FDCAN1 || FDCAN2*/ + +#define IS_RCC_SDMMC(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2)) + +#define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_ADCCLKSOURCE_CLKP)) + +#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI)) + +#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS)) + +#if defined(DFSDM2_BASE) +#define IS_RCC_DFSDM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \ + ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS)) +#endif /*DFSDM2*/ + +#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI)) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_CSI)) + +#define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ + ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ + ((SOURCE) == RCC_CLKPSOURCE_HSE)) +#define IS_RCC_TIMPRES(VALUE) \ + (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ + ((VALUE) == RCC_TIMPRES_ACTIVATED)) + +#if defined(DUAL_CORE) +#define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \ + ((CORE) == RCC_BOOT_C2)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \ + ((WWDG) == RCC_WWDG2)) +#else +#define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1) + +#endif /*DUAL_CORE*/ + +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN)) + +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) + +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) + +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) + +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) + +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) + +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_RCC_EX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h new file mode 100644 index 0000000..8f49df2 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h @@ -0,0 +1,2466 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_TIM_H +#define STM32H7xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +#if defined(TIM_BDTR_BKBID) + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + +#endif /* TIM_BDTR_BKBID */ + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +#if defined(TIM_BDTR_BKBID) + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + +#endif /* TIM_BDTR_BKBID */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#if defined(TIM_BREAK_INPUT_SUPPORT) +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +#endif /* TIM_BREAK_INPUT_SUPPORT */ +#define TIM_DMABASE_TISEL 0x0000001AU +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ +#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ +#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ +#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ +#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ +#if defined(TIM_BDTR_BKBID) + +/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ +#endif /*TIM_BDTR_BKBID */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ +#if defined(TIM_BDTR_BKBID) + +/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ +#endif /* TIM_BDTR_BKBID */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */ +#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ +#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ +#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ +#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ +#define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */ +#define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ +#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ +#define TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) */ +#define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL)) + + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENABLE)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ + ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ + ((__CHANNEL__) != (TIM_CHANNEL_6))) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) +#if defined(TIM_BDTR_BKBID) + +#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) + +#endif /* TIM_BDTR_BKBID */ + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) +#if defined(TIM_BDTR_BKBID) + +#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + +#endif /* TIM_BDTR_BKBID */ + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR12) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR12) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32h7xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_TIM_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h new file mode 100644 index 0000000..0943858 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h @@ -0,0 +1,533 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_TIM_EX_H +#define STM32H7xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity + Not relevant when analog watchdog output of the DFSDM1 used as break input source */ +} TIMEx_BreakInputConfigTypeDef; + +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */ +#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 OUT */ +#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 OUT */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC3 AWD3 */ + +#define TIM_TIM8_ETR_GPIO 0x00000000U /*!< TIM8_ETR is connected to GPIO */ +#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 OUT */ +#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 OUT */ +#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */ +#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */ + +#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */ +#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to COMP1 OUT */ +#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to COMP2 OUT */ +#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to RCC LSE */ +#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */ +#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */ + +#define TIM_TIM3_ETR_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */ +#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 OUT */ + +#define TIM_TIM5_ETR_GPIO 0x00000000U /*!< TIM5_ETR is connected to GPIO */ +#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */ +#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */ +#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI4 FS_A */ +#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI4 FS_B */ + +#define TIM_TIM23_ETR_GPIO 0x00000000U /*!< TIM23_ETR is connected to GPIO */ +#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM23_ETR is connected to COMP1 OUT */ +#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM23_ETR is connected to COMP2 OUT */ + +#define TIM_TIM24_ETR_GPIO 0x00000000U /*!< TIM24_ETR is connected to GPIO */ +#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM24_ETR is connected to SAI4 FS_A */ +#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM24_ETR is connected to SAI4 FS_B */ +#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM24_ETR is connected to SAI1 FS_A */ +#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /*!< TIM24_ETR is connected to SAI1 FS_B */ +/** + * @} + */ +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /*!< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ +/** + * @} + */ +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection + * @{ + */ +#define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1_TI1 is connected to GPIO */ +#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ + +#define TIM_TIM8_TI1_GPIO 0x00000000U /*!< TIM8_TI1 is connected to GPIO */ +#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM8_TI1 is connected to COMP2 OUT */ + +#define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2_TI4 is connected to GPIO */ +#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ +#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */ +#define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */ + +#define TIM_TIM3_TI1_GPIO 0x00000000U /*!< TIM3_TI1 is connected to GPIO */ +#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */ +#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */ +#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */ + +#define TIM_TIM5_TI1_GPIO 0x00000000U /*!< TIM5_TI1 is connected to GPIO */ +#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM5_TI1 is connected to CAN TMP */ +#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to CAN RTP */ + +#define TIM_TIM12_TI1_GPIO 0x00000000U /*!< TIM12 TI1 is connected to GPIO */ +#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 TI1 is connected to SPDIF FS */ + +#define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15_TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 CH1 */ +#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 CH1 */ +#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to TIM4 CH1 */ +#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /*!< TIM15_TI1 is connected to RCC LSE */ +#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to RCC CSI */ +#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to RCC MCO2 */ + +#define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15_TI2 is connected to GPIO */ +#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM2 CH2 */ +#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM3 CH2 */ +#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM4 CH2 */ + +#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 TI1 is connected to RCC LSI */ +#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 TI1 is connected to RCC LSE */ +#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 TI1 is connected to WKUP_IT */ + +#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17 TI1 is connected to GPIO */ +#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17 TI1 is connected to SPDIF FS */ +#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17 TI1 is connected to RCC HSE 1Mhz */ +#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 TI1 is connected to RCC MCO1 */ + +#define TIM_TIM23_TI4_GPIO 0x00000000U /*!< TIM23_TI4 is connected to GPIO */ +#define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM23_TI4 is connected to COMP1 OUT */ +#define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM23_TI4 is connected to COMP2 OUT */ +#define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */ + +#define TIM_TIM24_TI1_GPIO 0x00000000U /*!< TIM24_TI1 is connected to GPIO */ +#define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24_TI1 is connected to CAN TMP */ +#define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24_TI1 is connected to CAN RTP */ +#define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24_TI1 is connected to CAN SOC */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1)) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) + +#define IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM1_TI1_COMP1) ||\ + ((__TISEL__) == TIM_TIM8_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM8_TI1_COMP2) ||\ + ((__TISEL__) == TIM_TIM2_TI4_GPIO) ||\ + ((__TISEL__) == TIM_TIM2_TI4_COMP1) ||\ + ((__TISEL__) == TIM_TIM2_TI4_COMP2) ||\ + ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) ||\ + ((__TISEL__) == TIM_TIM3_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM3_TI1_COMP1) ||\ + ((__TISEL__) == TIM_TIM3_TI1_COMP2) ||\ + ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) ||\ + ((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\ + ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\ + ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS) ||\ + ((__TISEL__) == TIM_TIM12_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\ + ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\ + ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) ||\ + ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) ||\ + ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) ||\ + ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) ||\ + ((__TISEL__) == TIM_TIM15_TI2_GPIO) ||\ + ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) ||\ + ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) ||\ + ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) ||\ + ((__TISEL__) == TIM_TIM16_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) ||\ + ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) ||\ + ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) ||\ + ((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\ + ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\ + ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1) ||\ + ((__TISEL__) == TIM_TIM23_TI4_GPIO) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP1) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP2) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\ + ((__TISEL__) == TIM_TIM24_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC)) + +#define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) ||\ + ((__RREMAP__) == TIM_TIM3_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\ + ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB)) + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +#if defined(TIM_BREAK_INPUT_SUPPORT) +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +#endif /* TIM_BREAK_INPUT_SUPPORT */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); +#if defined(TIM_BDTR_BKBID) + +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); +#endif /* TIM_BDTR_BKBID */ +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7xx_HAL_TIM_EX_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h new file mode 100644 index 0000000..4f15c6e --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h @@ -0,0 +1,6914 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_BUS_H +#define STM32H7xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN +#define LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN + +#if defined(JPEG) +#define LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN +#endif /* JPEG */ + +#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN +#if defined(QUADSPI) +#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) +#define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN +#define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN +#endif /*(OCTOSPI1) || (OCTOSPI2)*/ +#if defined(OCTOSPIM) +#define LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) || defined(OTFDEC2) +#define LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN +#define LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN +#endif /* (OTFDEC1) || (OTFDEC2) */ +#if defined(GFXMMU) +#define LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN +#endif /* GFXMMU */ +#define LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN +#define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN +#define LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN +#define LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN +#define LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN +#else +#define LL_AHB3_GRP1_PERIPH_AXISRAM1 RCC_AHB3LPENR_AXISRAM1LPEN +#define LL_AHB3_GRP1_PERIPH_AXISRAM LL_AHB3_GRP1_PERIPH_AXISRAM1 /* for backward compatibility*/ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ +#if defined(CD_AXISRAM2_BASE) +#define LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN +#endif /* CD_AXISRAM2_BASE */ +#if defined(CD_AXISRAM3_BASE) +#define LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN +#endif /* CD_AXISRAM3_BASE */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN +#if defined(DUAL_CORE) +#define LL_AHB1_GRP1_PERIPH_ART RCC_AHB1ENR_ARTEN +#endif /* DUAL_CORE */ +#if defined(RCC_AHB1ENR_CRCEN) +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#endif /* RCC_AHB1ENR_CRCEN */ +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN +#define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN +#define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN +#endif /* ETH */ +#define LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN +#define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN +#if defined(USB2_OTG_FS) +#define LL_AHB1_GRP1_PERIPH_USB2OTGHS RCC_AHB1ENR_USB2OTGHSEN +#define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI RCC_AHB1ENR_USB2OTGHSULPIEN +#endif /* USB2_OTG_FS */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN +#if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN) +#define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN +#endif /* HSEM && RCC_AHB2ENR_HSEMEN */ +#if defined(CRYP) +#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN +#endif /* CRYP */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#endif /* HASH */ +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN +#if defined(FMAC) +#define LL_AHB2_GRP1_PERIPH_FMAC RCC_AHB2ENR_FMACEN +#endif /* FMAC */ +#if defined(CORDIC) +#define LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN +#endif /* CORDIC */ +#if defined(BDMA1) +#define LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN +#endif /* BDMA1 */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define LL_AHB2_GRP1_PERIPH_D2SRAM1 RCC_AHB2ENR_D2SRAM1EN +#else +#define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN +#define LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/ +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define LL_AHB2_GRP1_PERIPH_D2SRAM2 RCC_AHB2ENR_D2SRAM2EN +#else +#define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN +#define LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/ +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define LL_AHB2_GRP1_PERIPH_D2SRAM3 RCC_AHB2ENR_D2SRAM3EN +#endif /* RCC_AHB2ENR_D2SRAM3EN */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH + * @{ + */ +#define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN +#define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN +#define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN +#define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN +#define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN +#define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN +#define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN +#define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN +#if defined(GPIOI) +#define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN +#endif /* GPIOI */ +#define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN +#define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN +#if defined(RCC_AHB4ENR_CRCEN) +#define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN +#endif /* RCC_AHB4ENR_CRCEN */ +#if defined(BDMA2) +#define LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN +#define LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/ +#else +#define LL_AHB4_GRP1_PERIPH_BDMA RCC_AHB4ENR_BDMAEN +#endif /* BDMA2 */ +#if defined(ADC3) +#define LL_AHB4_GRP1_PERIPH_ADC3 RCC_AHB4ENR_ADC3EN +#endif /* ADC3 */ +#if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN) +#define LL_AHB4_GRP1_PERIPH_HSEM RCC_AHB4ENR_HSEMEN +#endif /* HSEM && RCC_AHB4ENR_HSEMEN*/ +#define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN +#if defined(RCC_AHB4LPENR_SRAM4LPEN) +#define LL_AHB4_GRP1_PERIPH_SRAM4 RCC_AHB4LPENR_SRAM4LPEN +#define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRAM4 +#else +#define LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN +#define LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/ +#define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/ +#endif /* RCC_AHB4ENR_D3SRAM1EN */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH + * @{ + */ +#if defined(LTDC) +#define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB3_GRP1_PERIPH_DSI RCC_APB3ENR_DSIEN +#endif /* DSI */ +#define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN +#if defined(RCC_APB3ENR_WWDGEN) +#define LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/ +#endif /* RCC_APB3ENR_WWDGEN */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN +#if defined(DUAL_CORE) +#define LL_APB1_GRP1_PERIPH_WWDG2 RCC_APB1LENR_WWDG2EN +#endif /*DUAL_CORE*/ +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN +#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN +#if defined(I2C5) +#define LL_APB1_GRP1_PERIPH_I2C5 RCC_APB1LENR_I2C5EN +#endif /* I2C5 */ +#if defined(RCC_APB1LENR_CECEN) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN +#else +#define LL_APB1_GRP1_PERIPH_HDMICEC RCC_APB1LENR_HDMICECEN +#define LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_HDMICEC /* for backward compatibility*/ +#endif /* RCC_APB1LENR_CECEN */ +#define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN +#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN +#define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN +#define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN +#define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN +#if defined(TIM23) +#define LL_APB1_GRP2_PERIPH_TIM23 RCC_APB1HENR_TIM23EN +#endif /* TIM23 */ +#if defined(TIM24) +#define LL_APB1_GRP2_PERIPH_TIM24 RCC_APB1HENR_TIM24EN +#endif /* TIM24 */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN +#if defined(UART9) +#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN +#endif /* UART9 */ +#if defined(USART10) +#define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN +#endif /* USART10 */ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#if defined(SAI2) +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#endif /* SAI2 */ +#if defined(SAI3) +#define LL_APB2_GRP1_PERIPH_SAI3 RCC_APB2ENR_SAI3EN +#endif /* SAI3 */ +#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN +#if defined(HRTIM1) +#define LL_APB2_GRP1_PERIPH_HRTIM RCC_APB2ENR_HRTIMEN +#endif /* HRTIM1 */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH + * @{ + */ +#define LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN +#define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN +#define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN +#define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN +#define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN +#define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN +#if defined(LPTIM4) +#define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN +#endif /* LPTIM4 */ +#if defined(LPTIM5) +#define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN +#endif /* LPTIM5 */ +#if defined(DAC2) +#define LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN +#endif /* DAC2 */ +#define LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN +#define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN +#define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN +#if defined(SAI4) +#define LL_APB4_GRP1_PERIPH_SAI4 RCC_APB4ENR_SAI4EN +#endif /* SAI4 */ +#if defined(DTS) +#define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN +#endif /* DFSDM2_BASE */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_CLKAM_PERIPH CLKAM PERIPH + * @{ + */ +#if defined(RCC_D3AMR_BDMAAMEN) +#define LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN +#else +#define LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN +#define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/ +#endif /* RCC_D3AMR_BDMAAMEN */ +#if defined(RCC_SRDAMR_GPIOAMEN) +#define LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN +#endif /* RCC_SRDAMR_GPIOAMEN */ +#if defined(RCC_D3AMR_LPUART1AMEN) +#define LL_CLKAM_PERIPH_LPUART1 RCC_D3AMR_LPUART1AMEN +#else +#define LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN +#endif /* RCC_D3AMR_LPUART1AMEN */ +#if defined(RCC_D3AMR_SPI6AMEN) +#define LL_CLKAM_PERIPH_SPI6 RCC_D3AMR_SPI6AMEN +#else +#define LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN +#endif /* RCC_D3AMR_SPI6AMEN */ +#if defined(RCC_D3AMR_I2C4AMEN) +#define LL_CLKAM_PERIPH_I2C4 RCC_D3AMR_I2C4AMEN +#else +#define LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN +#endif /* RCC_D3AMR_I2C4AMEN */ +#if defined(RCC_D3AMR_LPTIM2AMEN) +#define LL_CLKAM_PERIPH_LPTIM2 RCC_D3AMR_LPTIM2AMEN +#else +#define LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN +#endif /* RCC_D3AMR_LPTIM2AMEN */ +#if defined(RCC_D3AMR_LPTIM3AMEN) +#define LL_CLKAM_PERIPH_LPTIM3 RCC_D3AMR_LPTIM3AMEN +#else +#define LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN +#endif /* RCC_D3AMR_LPTIM3AMEN */ +#if defined(RCC_D3AMR_LPTIM4AMEN) +#define LL_CLKAM_PERIPH_LPTIM4 RCC_D3AMR_LPTIM4AMEN +#endif /* RCC_D3AMR_LPTIM4AMEN */ +#if defined(RCC_D3AMR_LPTIM5AMEN) +#define LL_CLKAM_PERIPH_LPTIM5 RCC_D3AMR_LPTIM5AMEN +#endif /* RCC_D3AMR_LPTIM5AMEN */ +#if defined(DAC2) +#define LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN +#endif /* DAC2 */ +#if defined(RCC_D3AMR_COMP12AMEN) +#define LL_CLKAM_PERIPH_COMP12 RCC_D3AMR_COMP12AMEN +#else +#define LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN +#endif /* RCC_D3AMR_COMP12AMEN */ +#if defined(RCC_D3AMR_VREFAMEN) +#define LL_CLKAM_PERIPH_VREF RCC_D3AMR_VREFAMEN +#else +#define LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN +#endif /* RCC_D3AMR_VREFAMEN */ +#if defined(RCC_D3AMR_RTCAMEN) +#define LL_CLKAM_PERIPH_RTC RCC_D3AMR_RTCAMEN +#else +#define LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN +#endif /* RCC_D3AMR_RTCAMEN */ +#if defined(RCC_D3AMR_CRCAMEN) +#define LL_CLKAM_PERIPH_CRC RCC_D3AMR_CRCAMEN +#endif /* RCC_D3AMR_CRCAMEN */ +#if defined(SAI4) +#define LL_CLKAM_PERIPH_SAI4 RCC_D3AMR_SAI4AMEN +#endif /* SAI4 */ +#if defined(ADC3) +#define LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN +#endif /* ADC3 */ +#if defined(RCC_SRDAMR_DTSAMEN) +#define LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN +#endif /* RCC_SRDAMR_DTSAMEN */ +#if defined(RCC_D3AMR_DTSAMEN) +#define LL_CLKAM_PERIPH_DTS RCC_D3AMR_DTSAMEN +#endif /* RCC_D3AMR_DTSAMEN */ +#if defined(DFSDM2_BASE) +#define LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN +#endif /* DFSDM2_BASE */ +#if defined(RCC_D3AMR_BKPRAMAMEN) +#define LL_CLKAM_PERIPH_BKPRAM RCC_D3AMR_BKPRAMAMEN +#else +#define LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN +#endif /* RCC_D3AMR_BKPRAMAMEN */ +#if defined(RCC_D3AMR_SRAM4AMEN) +#define LL_CLKAM_PERIPH_SRAM4 RCC_D3AMR_SRAM4AMEN +#else +#define LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN +#define LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM +#endif /* RCC_D3AMR_SRAM4AMEN */ +/** + * @} + */ + +#if defined(RCC_CKGAENR_AXICKG) +/** @defgroup BUS_LL_EC_CKGA_PERIPH CKGA (AXI Clocks Gating) PERIPH + * @{ + */ +#define LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG +#define LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG +#define LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG +#define LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG +#define LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG +#define LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG +#define LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG +#define LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG +#define LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG +#define LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG +#define LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG +#define LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG +#define LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG +#define LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG +#define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG +#define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG +#define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG +#define LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG +#define LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG +#define LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG +#define LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG +/** + * @} + */ +#endif /* RCC_CKGAENR_AXICKG */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR DMA2DEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR JPGDECEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR IOMNGREN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR DTCM2EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR ITCMEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR AXISRAMEN LL_AHB3_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DMA2DEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR JPGDECEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR IOMNGREN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR DTCM2EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR ITCMEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR AXISRAMEN LL_AHB3_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR DMA2DEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR JPGDECEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR IOMNGREN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR DTCM2EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR ITCMEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR AXISRAMEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ARTEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ARTRST LL_AHB1_GRP1_ForceReset\n (*) + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n (*) + * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ForceReset\n (*) + * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ARTRST LL_AHB1_GRP1_ReleaseReset\n (*) + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n (*) + * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ReleaseReset\n (*) + * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ARTLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ARTLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR FMACEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR FMACEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR FMACEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR FMACRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR FMACRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR FMACLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BDMAEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR ADC3EN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR HSEMEN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR SRAM4EN LL_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BDMAEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR ADC3EN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR HSEMEN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SRAM4EN LL_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BDMAEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR ADC3EN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR HSEMEN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR SRAM4EN LL_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4ENR, Periphs); +} + +/** + * @brief Force AHB4 peripherals reset. + * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n (*) + * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n (*) + * AHB4RSTR BDMARST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR ADC3RST LL_AHB4_GRP1_ForceReset\n (*) + * AHB4RSTR HSEMRST LL_AHB4_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Release AHB4 peripherals reset. + * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n (*) + * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset\n (*) + * AHB4RSTR BDMARST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR ADC3RST LL_AHB4_GRP1_ReleaseReset\n (*) + * AHB4RSTR HSEMRST LL_AHB4_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_EnableClock\n (*) + * APB3ENR DSIEN LL_APB3_GRP1_EnableClock\n (*) + * APB3ENR WWDG1EN LL_APB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR DSIEN LL_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR WWDG1EN LL_APB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_DisableClock\n + * APB3ENR DSIEN LL_APB3_GRP1_DisableClock\n + * APB3ENR WWDG1EN LL_APB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3ENR, Periphs); +} + +/** + * @brief Force APB3 peripherals reset. + * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ForceReset\n (*) + * APB3RSTR DSIRST LL_APB3_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Release APB3 peripherals reset. + * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR DSIRST LL_APB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Enable APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR DSILPEN LL_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_APB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR DSILPEN LL_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_APB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock\n + * APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock\n (*) + * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C5EN LL_APB1_GRP1_EnableClock\n (*) + * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1LENR DAC12EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART8EN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C5EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock\n + * APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock\n (*) + * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C5EN LL_APB1_GRP1_DisableClock\n (*) + * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1LENR DAC12EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART8EN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C5RST LL_APB1_GRP5_ForceReset\n (*) + * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1LRSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C5RST LL_APB1_GRP1_ReleaseReset\n (*) + * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LRSTR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C5LPEN LL_APB1_GRP1_EnableClockSleep\n (*) + * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C5LPEN LL_APB1_GRP1_DisableClockSleep\n (*) + * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LLPENR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_EnableClock\n + * APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock\n + * APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock\n + * APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1HENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1HENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_DisableClock\n + * APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock\n + * APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock\n + * APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1HRSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HRSTR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1HLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HLPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n (*) + * APB2ENR USART10EN LL_APB2_GRP1_EnableClock\n (*) + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI3EN LL_APB2_GRP1_EnableClock\n (*) + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR HRTIMEN LL_APB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI3EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR HRTIMEN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n (*) + * APB2ENR USART10EN LL_APB2_GRP1_DisableClock\n (*) + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI3EN LL_APB2_GRP1_DisableClock\n (*) + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR HRTIMEN LL_APB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n + * APB2ENR UART9RST LL_APB2_GRP1_ForceReset\n (*) + * APB2ENR USART10RST LL_APB2_GRP1_ForceReset\n (*) + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI3RST LL_APB2_GRP1_ForceReset\n (*) + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR HRTIMRST LL_APB2_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n + * APB2ENR UART9RST LL_APB2_GRP1_ReleaseReset\n (*) + * APB2ENR USART10RST LL_APB2_GRP1_ReleaseReset\n (*) + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI3RST LL_APB2_GRP1_ReleaseReset\n (*) + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR HRTIMRST LL_APB2_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2ENR UART9LPEN LL_APB2_GRP1_EnableClockSleep\n (*) + * APB2ENR USART10LPEN LL_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI3LPEN LL_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR HRTIMLPEN LL_APB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2ENR UART9LPEN LL_APB2_GRP1_DisableClockSleep\n (*) + * APB2ENR USART10LPEN LL_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI3LPEN LL_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR HRTIMLPEN LL_APB2_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n + * APB4ENR I2C4EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR DAC2EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR COMP12EN LL_APB4_GRP1_EnableClock\n + * APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n + * APB4ENR SAI4EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR DTSEN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR DFSDM2EN LL_APB4_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR I2C4EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DAC2EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR COMP12EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR SAI4EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DFSDM2EN LL_APB4_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n + * APB4ENR I2C4EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR DAC2EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR COMP12EN LL_APB4_GRP1_DisableClock\n + * APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n + * APB4ENR SAI4EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR DTSEN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR DFSDM2EN LL_APB4_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4ENR, Periphs); +} + +/** + * @brief Force APB4 peripherals reset. + * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR I2C4RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR DAC2EN LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR COMP12RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n + * APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR DTSRST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB4RSTR, Periphs); +} + +/** + * @brief Release APB4 peripherals reset. + * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR I2C4RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR DAC2RST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR COMP12RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR SAI4RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR DFSDM2RST LL_APB4_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4RSTR, Periphs); +} + +/** + * @brief Enable APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR I2C4LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR DAC2LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR COMP12LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SAI4LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR I2C4LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR DAC2LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR COMP12LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SAI4LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_CLKAM CLKAM + * @{ + */ + +/** + * @brief Enable peripherals clock for CLKAM Mode. + * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPUART1 LL_CLKAM_Enable\n + * D3AMR / SRDAMR SPI6 LL_CLKAM_Enable\n + * D3AMR / SRDAMR I2C4 LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR DAC2 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR COMP12 LL_CLKAM_Enable\n + * D3AMR / SRDAMR VREF LL_CLKAM_Enable\n + * D3AMR / SRDAMR RTC LL_CLKAM_Enable\n + * D3AMR / SRDAMR CRC LL_CLKAM_Enable\n + * D3AMR / SRDAMR SAI4 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR ADC3 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR DTS LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR BKPRAM LL_CLKAM_Enable\n + * D3AMR / SRDAMR SRAM4 LL_CLKAM_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CLKAM_PERIPH_BDMA + * @arg @ref LL_CLKAM_PERIPH_GPIO (*) + * @arg @ref LL_CLKAM_PERIPH_LPUART1 + * @arg @ref LL_CLKAM_PERIPH_SPI6 + * @arg @ref LL_CLKAM_PERIPH_I2C4 + * @arg @ref LL_CLKAM_PERIPH_LPTIM2 + * @arg @ref LL_CLKAM_PERIPH_LPTIM3 + * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*) + * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*) + * @arg @ref LL_CLKAM_PERIPH_DAC2 (*) + * @arg @ref LL_CLKAM_PERIPH_COMP12 + * @arg @ref LL_CLKAM_PERIPH_VREF + * @arg @ref LL_CLKAM_PERIPH_RTC + * @arg @ref LL_CLKAM_PERIPH_CRC (*) + * @arg @ref LL_CLKAM_PERIPH_SAI4 (*) + * @arg @ref LL_CLKAM_PERIPH_ADC3 (*) + * @arg @ref LL_CLKAM_PERIPH_DTS (*) + * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*) + * @arg @ref LL_CLKAM_PERIPH_BKPRAM + * @arg @ref LL_CLKAM_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + +#if defined(RCC_D3AMR_BDMAAMEN) + SET_BIT(RCC->D3AMR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->D3AMR, Periphs); +#else + SET_BIT(RCC->SRDAMR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->SRDAMR, Periphs); +#endif /* RCC_D3AMR_BDMAAMEN */ + (void)tmpreg; +} + +/** + * @brief Disable peripherals clock for CLKAM Mode. + * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPUART1 LL_CLKAM_Disable\n + * D3AMR / SRDAMR SPI6 LL_CLKAM_Disable\n + * D3AMR / SRDAMR I2C4 LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR DAC2 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR COMP12 LL_CLKAM_Disable\n + * D3AMR / SRDAMR VREF LL_CLKAM_Disable\n + * D3AMR / SRDAMR RTC LL_CLKAM_Disable\n + * D3AMR / SRDAMR CRC LL_CLKAM_Disable\n + * D3AMR / SRDAMR SAI4 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR ADC3 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR DTS LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR BKPRAM LL_CLKAM_Disable\n + * D3AMR / SRDAMR SRAM4 LL_CLKAM_Disable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CLKAM_PERIPH_BDMA + * @arg @ref LL_CLKAM_PERIPH_GPIO (*) + * @arg @ref LL_CLKAM_PERIPH_LPUART1 + * @arg @ref LL_CLKAM_PERIPH_SPI6 + * @arg @ref LL_CLKAM_PERIPH_I2C4 + * @arg @ref LL_CLKAM_PERIPH_LPTIM2 + * @arg @ref LL_CLKAM_PERIPH_LPTIM3 + * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*) + * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*) + * @arg @ref LL_CLKAM_PERIPH_DAC2 (*) + * @arg @ref LL_CLKAM_PERIPH_COMP12 + * @arg @ref LL_CLKAM_PERIPH_VREF + * @arg @ref LL_CLKAM_PERIPH_RTC + * @arg @ref LL_CLKAM_PERIPH_CRC (*) + * @arg @ref LL_CLKAM_PERIPH_SAI4 (*) + * @arg @ref LL_CLKAM_PERIPH_ADC3 (*) + * @arg @ref LL_CLKAM_PERIPH_DTS (*) + * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*) + * @arg @ref LL_CLKAM_PERIPH_BKPRAM + * @arg @ref LL_CLKAM_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs) +{ +#if defined(RCC_D3AMR_BDMAAMEN) + CLEAR_BIT(RCC->D3AMR, Periphs); +#else + CLEAR_BIT(RCC->SRDAMR, Periphs); +#endif /* RCC_D3AMR_BDMAAMEN */ +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_CKGA CKGA + * @{ + */ + +#if defined(RCC_CKGAENR_AXICKG) + + +/** + * @brief Enable clock gating for AXI bus peripherals. + * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n + * CKGAENR AHBCKG LL_CKGA_Enable\n + * CKGAENR CPUCKG LL_CKGA_Enable\n + * CKGAENR SDMMCCKG LL_CKGA_Enable\n + * CKGAENR MDMACKG LL_CKGA_Enable\n + * CKGAENR DMA2DCKG LL_CKGA_Enable\n + * CKGAENR LTDCCKG LL_CKGA_Enable\n + * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n + * CKGAENR AHB12CKG LL_CKGA_Enable\n + * CKGAENR AHB34CKG LL_CKGA_Enable\n + * CKGAENR FLIFTCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n + * CKGAENR FMCCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n + * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n + * CKGAENR ECCRAMCKG LL_CKGA_Enable\n + * CKGAENR EXTICKG LL_CKGA_Enable\n + * CKGAENR JTAGCKG LL_CKGA_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHB + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_SDMMC + * @arg @ref LL_CKGA_PERIPH_MDMA + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_LTDC + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_AHB12 + * @arg @ref LL_CKGA_PERIPH_AHB34 + * @arg @ref LL_CKGA_PERIPH_FLIFT + * @arg @ref LL_CKGA_PERIPH_OCTOSPI2 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_OCTOSPI1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_ECCRAM + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG + * @retval None +*/ +__STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->CKGAENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->CKGAENR, Periphs); + (void)tmpreg; +} + +#endif /* RCC_CKGAENR_AXICKG */ + +#if defined(RCC_CKGAENR_AXICKG) + +/** + * @brief Disable clock gating for AXI bus peripherals. + * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n + * CKGAENR AHBCKG LL_CKGA_Enable\n + * CKGAENR CPUCKG LL_CKGA_Enable\n + * CKGAENR SDMMCCKG LL_CKGA_Enable\n + * CKGAENR MDMACKG LL_CKGA_Enable\n + * CKGAENR DMA2DCKG LL_CKGA_Enable\n + * CKGAENR LTDCCKG LL_CKGA_Enable\n + * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n + * CKGAENR AHB12CKG LL_CKGA_Enable\n + * CKGAENR AHB34CKG LL_CKGA_Enable\n + * CKGAENR FLIFTCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n + * CKGAENR FMCCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n + * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n + * CKGAENR ECCRAMCKG LL_CKGA_Enable\n + * CKGAENR EXTICKG LL_CKGA_Enable\n + * CKGAENR JTAGCKG LL_CKGA_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHB + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_SDMMC + * @arg @ref LL_CKGA_PERIPH_MDMA + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_LTDC + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_AHB12 + * @arg @ref LL_CKGA_PERIPH_AHB34 + * @arg @ref LL_CKGA_PERIPH_FLIFT + * @arg @ref LL_CKGA_PERIPH_OCTOSPI2 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_OCTOSPI1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_ECCRAM + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG + * @retval None +*/ +__STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs) +{ + CLEAR_BIT(RCC->CKGAENR, Periphs); +} + +#endif /* RCC_CKGAENR_AXICKG */ + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @addtogroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable C1 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR FMCEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FMCEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR FMCEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB3ENR, Periphs); +} + +/** + * @brief Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable C1 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ARTEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ARTEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ARTEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB1ENR, Periphs); +} + +/** + * @brief Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable C1 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR HASHEN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR RNGEN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR HASHEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR RNGEN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR HASHEN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR RNGEN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB2ENR, Periphs); +} + +/** + * @brief Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable C1 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR CRCEN LL_C1_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR CRCEN LL_C1_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB4ENR, Periphs); +} + +/** + * @brief Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable C1 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_EnableClock\n (*) + * APB3ENR DSIEN LL_C1_APB3_GRP1_EnableClock\n (*) + * APB3ENR WWDG1EN LL_C1_APB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR DSIEN LL_C1_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR WWDG1EN LL_C1_APB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_DisableClock\n (*) + * APB3ENR DSIEN LL_C1_APB3_GRP1_DisableClock\n (*) + * APB3ENR WWDG1EN LL_C1_APB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB3ENR, Periphs); +} + +/** + * @brief Enable C1 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR DSILPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR DSILPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable C1 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM4EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM5EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM6EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM7EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM12EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM13EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM14EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR WWDG2EN LL_C1_APB1_GRP1_EnableClock\n (*) + * APB1LENR SPI2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR SPI3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR USART2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR USART3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART4EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART5EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR I2C1EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR I2C2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR I2C3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR CECEN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR DAC12EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART7EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART8EN LL_C1_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1LENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB1 peripheral clock is enabled or not + * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM4EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM5EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM6EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM7EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM12EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM13EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM14EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR WWDG2EN LL_C1_APB1_GRP1_IsEnabledClock\n (*) + * APB1LENR SPI2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART4EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART5EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C1EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR CECEN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR DAC12EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART7EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART8EN LL_C1_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM4EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM5EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM6EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM7EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM12EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM13EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM14EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR WWDG2EN LL_C1_APB1_GRP1_DisableClock\n (*) + * APB1LENR SPI2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR SPI3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR USART2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR USART3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART4EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART5EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR I2C1EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR I2C2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR I2C3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR CECEN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR DAC12EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART7EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART8EN LL_C1_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1LENR, Periphs); +} + +/** + * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1LLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs); +} + +/** + * @brief Enable C1 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR SWPMIEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR OPAMPEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR MDIOSEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_C1_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1HENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB1 peripheral clock is enabled or not + * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR SWPMIEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR OPAMPEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR MDIOSEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR FDCANEN LL_C1_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR SWPMIEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR OPAMPEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR MDIOSEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR FDCANEN LL_C1_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1HENR, Periphs); +} + +/** + * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1HLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable C1 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClock\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClock\n (*) + * APB2ENR SPI1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SAI3EN LL_C1_APB2_GRP1_EnableClock\n (*) + * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR HRTIMEN LL_C1_APB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR SPI1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI3EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR HRTIMEN LL_C1_APB2_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_DisableClock\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_DisableClock\n (*) + * APB2ENR SPI1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SAI3EN LL_C1_APB2_GRP1_DisableClock\n (*) + * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR HRTIMEN LL_C1_APB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB2ENR, Periphs); +} + +/** + * @brief Enable C1 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClockSleep\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR UART9LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR USART10LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable C1 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPUART1EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR SPI6EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR I2C4EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR DAC2EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR COMP12EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR VREFEN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR SAI4EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR DTSEN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPUART1EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR SPI6EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR I2C4EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR COMP12EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR VREFEN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR SAI4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DTSEN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPUART1EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR SPI6EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR I2C4EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR COMP12EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR VREFEN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR SAI4EN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR DTSEN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB4ENR, Periphs); +} + +/** + * @brief Enable C1 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4ENR DTSLPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*) + * APB4ENR DTSLPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*) + * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable C2 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR FMCEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FMCEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR FMCEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB3ENR, Periphs); +} + +/** + * @brief Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable C2 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ARTEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ARTEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ARTEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB1ENR, Periphs); +} + +/** + * @brief Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable C2 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB2ENR, Periphs); +} + +/** + * @brief Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable C2 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR CRCEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR CRCEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB4ENR, Periphs); +} + +/** + * @brief Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable C2 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_EnableClock\n + * APB3ENR DSIEN LL_C2_APB3_GRP1_EnableClock\n + * APB3ENR WWDG1EN LL_C2_APB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_IsEnabledClock\n + * APB3ENR DSIEN LL_C2_APB3_GRP1_IsEnabledClock\n + * APB3ENR WWDG1EN LL_C2_APB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_DisableClock\n + * APB3ENR DSIEN LL_C2_APB3_GRP1_DisableClock\n + * APB3ENR WWDG1EN LL_C2_APB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB3ENR, Periphs); +} + +/** + * @brief Enable C2 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_EnableClockSleep\n + * APB3LPENR DSILPEN LL_C2_APB3_GRP1_EnableClockSleep\n + * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_DisableClockSleep\n + * APB3LPENR DSILPEN LL_C2_APB3_GRP1_DisableClockSleep\n + * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable C2 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM4EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM5EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM6EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM7EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM12EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM13EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM14EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR WWDG2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR SPI2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR SPI3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR USART2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR USART3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART4EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART5EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR I2C1EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR I2C2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR I2C3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR CECEN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR DAC12EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART7EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART8EN LL_C2_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1LENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB1 peripheral clock is enabled or not + * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM4EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM5EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM6EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM7EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM12EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM13EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM14EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR WWDG2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART4EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART5EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR CECEN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR DAC12EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART7EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART8EN LL_C2_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM4EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM5EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM6EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM7EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM12EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM13EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM14EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR WWDG2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR SPI2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR SPI3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR USART2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR USART3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART4EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART5EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR I2C1EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR I2C2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR I2C3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR CECEN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR DAC12EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART7EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART8EN LL_C2_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1LENR, Periphs); +} + +/** + * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1LLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs); +} + +/** + * @brief Enable C2 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR SWPMIEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR OPAMPEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR MDIOSEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_C2_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1HENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB1 peripheral clock is enabled or not + * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR SWPMIEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR OPAMPEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR MDIOSEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR FDCANEN LL_C2_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR SWPMIEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR OPAMPEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR MDIOSEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR FDCANEN LL_C2_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1HENR, Periphs); +} + +/** + * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1HLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable C2 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SAI3EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR HRTIMEN LL_C2_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI3EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR HRTIMEN LL_C2_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SAI3EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR HRTIMEN LL_C2_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB2ENR, Periphs); +} + +/** + * @brief Enable C2 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable C2 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPUART1EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR SPI6EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR I2C4EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR COMP12EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR VREFEN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR SAI4EN LL_C2_APB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPUART1EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR SPI6EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR I2C4EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR COMP12EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR VREFEN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR SAI4EN LL_C2_APB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPUART1EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR SPI6EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR I2C4EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR COMP12EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR VREFEN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR SAI4EN LL_C2_APB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB4ENR, Periphs); +} + +/** + * @brief Enable C2 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB4LPENR, Periphs); +} + +/** + * @} + */ + +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_BUS_H */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h new file mode 100644 index 0000000..2b63e8f --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h @@ -0,0 +1,669 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_CORTEX_H +#define STM32H7xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00UL /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01UL /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02UL /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03UL /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04UL /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05UL /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06UL /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07UL /*!< REGION Number 7 */ +#if !defined(CORE_CM4) +#define LL_MPU_REGION_NUMBER8 0x08UL /*!< REGION Number 8 */ +#define LL_MPU_REGION_NUMBER9 0x09UL /*!< REGION Number 9 */ +#define LL_MPU_REGION_NUMBER10 0x0AUL /*!< REGION Number 10 */ +#define LL_MPU_REGION_NUMBER11 0x0BUL /*!< REGION Number 11 */ +#define LL_MPU_REGION_NUMBER12 0x0CUL /*!< REGION Number 12 */ +#define LL_MPU_REGION_NUMBER13 0x0DUL /*!< REGION Number 13 */ +#define LL_MPU_REGION_NUMBER14 0x0EUL /*!< REGION Number 14 */ +#define LL_MPU_REGION_NUMBER15 0x0FUL /*!< REGION Number 15 */ +#endif /* !defined(CORE_CM4) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ + +/* Legacy Define */ +#define LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source); +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK)); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_CORTEX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h new file mode 100644 index 0000000..86ce847 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h @@ -0,0 +1,780 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_CRS_H +#define STM32H7xx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 64, which corresponds to the middle of the trimming interval. + * The trimming step is specified in the product datasheet. + * A higher TRIM value corresponds to a higher output frequency. + */ +#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 127 + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 127 + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 + * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_CRS_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h new file mode 100644 index 0000000..5195c3b --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h @@ -0,0 +1,3322 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_DMA_H +#define STM32H7xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include "stm32h7xx_ll_dmamux.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ +static const uint8_t LL_DMA_STR_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) +}; + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Macros DMA LL Private Macros + * @{ + */ +/** + * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel + * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. + * @param __DMA_INSTANCE__ DMAx + * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0). + */ +#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ +(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL) +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Stream + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_LL_FIFOMODE + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream + + This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_MBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_PBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ + + uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode. + This parameter can be a value of @ref DMA_LL_EC_DOUBLEBUFFER_MODE + + This feature can be modified afterwards using unitary function @ref LL_DMA_EnableDoubleBufferMode() & LL_DMA_DisableDoubleBufferMode(). */ + + uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode. + This parameter can be a value of @ref DMA_LL_EC_CURRENTTARGETMEM + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetCurrentTargetMem(). */ +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_STREAM STREAM + * @{ + */ +#define LL_DMA_STREAM_0 0x00000000U +#define LL_DMA_STREAM_1 0x00000001U +#define LL_DMA_STREAM_2 0x00000002U +#define LL_DMA_STREAM_3 0x00000003U +#define LL_DMA_STREAM_4 0x00000004U +#define LL_DMA_STREAM_5 0x00000005U +#define LL_DMA_STREAM_6 0x00000006U +#define LL_DMA_STREAM_7 0x00000007U +#define LL_DMA_STREAM_ALL 0xFFFF0000U +/** + * @} + */ + + +/** @defgroup DMA_LL_EC_DIRECTION DIRECTION + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE MODE + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ +#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE + * @{ + */ +#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ +#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + * @{ + */ +#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ +#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH PERIPH + * @{ + */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY MEMORY + * @{ + */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE + * @{ + */ +#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ +#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY PRIORITY + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_LL_EC_MBURST MBURST + * @{ + */ +#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ +#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ +#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ +#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PBURST PBURST + * @{ + */ +#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ +#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ +#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ +#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE + * @{ + */ +#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ +#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 + * @{ + */ +#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ +#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ +#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ +#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ +#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ +#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD + * @{ + */ +#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy + * @{ + */ +/** + * @brief Convert DMAx_Streamy into DMAx + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) + +/** + * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval LL_DMA_STREAM_y + */ +#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ + LL_DMA_STREAM_7) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy + * @param __DMA_INSTANCE__ DMAx + * @param __STREAM__ LL_DMA_STREAM_y + * @retval DMAx_Streamy + */ +#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ + DMA2_Stream7) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA stream. + * @rmtoll CR EN LL_DMA_EnableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableStream(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); +} + +/** + * @brief Disable DMA stream. + * @rmtoll CR EN LL_DMA_DisableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableStream(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); +} + +/** + * @brief Check if DMA stream is enabled or disabled. + * @rmtoll CR EN LL_DMA_IsEnabledStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure all parameters linked to DMA transfer. + * @rmtoll CR DIR LL_DMA_ConfigTransfer\n + * CR CIRC LL_DMA_ConfigTransfer\n + * CR PINC LL_DMA_ConfigTransfer\n + * CR MINC LL_DMA_ConfigTransfer\n + * CR PSIZE LL_DMA_ConfigTransfer\n + * CR MSIZE LL_DMA_ConfigTransfer\n + * CR PL LL_DMA_ConfigTransfer\n + * CR PFCTRL LL_DMA_ConfigTransfer\n + * CR DBM LL_DMA_ConfigTransfer\n + * CR CT LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @arg @ref LL_DMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_DMA_DOUBLEBUFFER_MODE_ENABLE + * @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1 + *@retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, + DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | \ + DMA_SxCR_PFCTRL | DMA_SxCR_DBM | DMA_SxCR_CT, Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR)); +} + +/** + * @brief Set DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_SetMode\n + * CR PFCTRL LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); +} + +/** + * @brief Get DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_GetMode\n + * CR PFCTRL LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size); +} + +/** + * @brief Get Memory size. + * @rmtoll CR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE)); +} + +/** + * @brief Set Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param OffsetSize This parameter can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize); +} + +/** + * @brief Get Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + */ +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS)); +} + +/** + * @brief Set Stream priority level. + * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority); +} + +/** + * @brief Get Stream priority level. + * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL)); +} + +/** + * @brief Enable DMA stream bufferable transfer. + * @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); +} + +/** + * @brief Disable DMA stream bufferable transfer. + * @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); +} + +/** + * @brief Set Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_SetDataLength + * @note This action has no effect if + * stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param NbData Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_GetDataLength + * @note Once the stream is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT)); +} +/** + * @brief Set DMA request for DMA Streams on DMAMUX Channel x. + * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * + * @note (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mburst This parameter can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst); +} + +/** + * @brief Get Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST)); +} + +/** + * @brief Set Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Pburst This parameter can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst); +} + +/** + * @brief Get Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST)); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_SetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param CurrentMemory This parameter can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_GetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT)); +} + +/** + * @brief Enable the double buffer mode. + * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Disable the double buffer mode. + * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Check if double buffer mode is enabled or not. + * @rmtoll CR DBM LL_DMA_IsEnabledDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL); +} + +/** + * @brief Get FIFO status. + * @rmtoll FCR FS LL_DMA_GetFIFOStatus + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOSTATUS_0_25 + * @arg @ref LL_DMA_FIFOSTATUS_25_50 + * @arg @ref LL_DMA_FIFOSTATUS_50_75 + * @arg @ref LL_DMA_FIFOSTATUS_75_100 + * @arg @ref LL_DMA_FIFOSTATUS_EMPTY + * @arg @ref LL_DMA_FIFOSTATUS_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS)); +} + +/** + * @brief Disable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Enable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Select FIFO threshold. + * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold); +} + +/** + * @brief Get FIFO threshold. + * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH)); +} + +/** + * @brief Configure the FIFO . + * @rmtoll FCR FTH LL_DMA_ConfigFifo\n + * FCR DMDIS LL_DMA_ConfigFifo + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param FifoMode This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOMODE_ENABLE + * @arg @ref LL_DMA_FIFOMODE_DISABLE + * @param FifoThreshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigFifo(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA stream is enabled. + * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n + * PAR PA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DstAddress Between 0 to 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @rmtoll PAR PA LL_DMA_SetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param PeriphAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress); +} + +/** + * @brief Get the Memory address. + * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); +} + +/** + * @brief Get the Peripheral address. + * @rmtoll PAR PA LL_DMA_GetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); +} + +/** + * @brief Set Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_SetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Address Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address); +} + +/** + * @brief Get Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_GetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Stream 0 half transfer flag. + * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 half transfer flag. + * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 half transfer flag. + * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 half transfer flag. + * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 half transfer flag. + * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 half transfer flag. + * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 half transfer flag. + * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 half transfer flag. + * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 transfer complete flag. + * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 transfer complete flag. + * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 transfer complete flag. + * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 transfer complete flag. + * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 transfer complete flag. + * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 transfer complete flag. + * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 transfer complete flag. + * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 transfer complete flag. + * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 transfer error flag. + * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 transfer error flag. + * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 transfer error flag. + * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 transfer error flag. + * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 transfer error flag. + * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 transfer error flag. + * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 transfer error flag. + * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 transfer error flag. + * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 direct mode error flag. + * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 direct mode error flag. + * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 direct mode error flag. + * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 direct mode error flag. + * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 direct mode error flag. + * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 direct mode error flag. + * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 direct mode error flag. + * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 direct mode error flag. + * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 FIFO error flag. + * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 FIFO error flag. + * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 FIFO error flag. + * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 FIFO error flag. + * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 FIFO error flag. + * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 FIFO error flag. + * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 FIFO error flag. + * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 FIFO error flag. + * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Clear Stream 0 half transfer flag. + * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0); +} + +/** + * @brief Clear Stream 1 half transfer flag. + * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1); +} + +/** + * @brief Clear Stream 2 half transfer flag. + * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2); +} + +/** + * @brief Clear Stream 3 half transfer flag. + * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3); +} + +/** + * @brief Clear Stream 4 half transfer flag. + * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4); +} + +/** + * @brief Clear Stream 5 half transfer flag. + * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5); +} + +/** + * @brief Clear Stream 6 half transfer flag. + * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6); +} + +/** + * @brief Clear Stream 7 half transfer flag. + * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7); +} + +/** + * @brief Clear Stream 0 transfer complete flag. + * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0); +} + +/** + * @brief Clear Stream 1 transfer complete flag. + * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1); +} + +/** + * @brief Clear Stream 2 transfer complete flag. + * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2); +} + +/** + * @brief Clear Stream 3 transfer complete flag. + * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3); +} + +/** + * @brief Clear Stream 4 transfer complete flag. + * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4); +} + +/** + * @brief Clear Stream 5 transfer complete flag. + * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5); +} + +/** + * @brief Clear Stream 6 transfer complete flag. + * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6); +} + +/** + * @brief Clear Stream 7 transfer complete flag. + * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7); +} + +/** + * @brief Clear Stream 0 transfer error flag. + * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0); +} + +/** + * @brief Clear Stream 1 transfer error flag. + * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1); +} + +/** + * @brief Clear Stream 2 transfer error flag. + * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2); +} + +/** + * @brief Clear Stream 3 transfer error flag. + * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3); +} + +/** + * @brief Clear Stream 4 transfer error flag. + * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4); +} + +/** + * @brief Clear Stream 5 transfer error flag. + * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5); +} + +/** + * @brief Clear Stream 6 transfer error flag. + * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6); +} + +/** + * @brief Clear Stream 7 transfer error flag. + * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7); +} + +/** + * @brief Clear Stream 0 direct mode error flag. + * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0); +} + +/** + * @brief Clear Stream 1 direct mode error flag. + * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1); +} + +/** + * @brief Clear Stream 2 direct mode error flag. + * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2); +} + +/** + * @brief Clear Stream 3 direct mode error flag. + * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3); +} + +/** + * @brief Clear Stream 4 direct mode error flag. + * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4); +} + +/** + * @brief Clear Stream 5 direct mode error flag. + * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5); +} + +/** + * @brief Clear Stream 6 direct mode error flag. + * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6); +} + +/** + * @brief Clear Stream 7 direct mode error flag. + * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7); +} + +/** + * @brief Clear Stream 0 FIFO error flag. + * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0); +} + +/** + * @brief Clear Stream 1 FIFO error flag. + * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1); +} + +/** + * @brief Clear Stream 2 FIFO error flag. + * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2); +} + +/** + * @brief Clear Stream 3 FIFO error flag. + * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3); +} + +/** + * @brief Clear Stream 4 FIFO error flag. + * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4); +} + +/** + * @brief Clear Stream 5 FIFO error flag. + * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5); +} + +/** + * @brief Clear Stream 6 FIFO error flag. + * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6); +} + +/** + * @brief Clear Stream 7 FIFO error flag. + * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Enable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_EnableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Enable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_EnableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Disable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_DisableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Disable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_DisableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Check if Half transfer interrupt is enabled. + * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer error nterrup is enabled. + * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer complete interrupt is enabled. + * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Direct mode error interrupt is enabled. + * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if FIFO error interrupt is enabled. + * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_DMA_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h new file mode 100644 index 0000000..be9b2fc --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h @@ -0,0 +1,2436 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_dmamux.h + * @author MCD Application Team + * @brief Header file of DMAMUX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_DMAMUX_H +#define STM32H7xx_LL_DMAMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (DMAMUX1) || defined (DMAMUX2) + +/** @defgroup DMAMUX_LL DMAMUX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants + * @{ + */ +/* Define used to get DMAMUX CCR register size */ +#define DMAMUX_CCR_SIZE 0x00000004U + +/* Define used to get DMAMUX RGCR register size */ +#define DMAMUX_RGCR_SIZE 0x00000004U + +/* Define used to get DMAMUX RequestGenerator offset */ +#define DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE) +/* Define used to get DMAMUX Channel Status offset */ +#define DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE) +/* Define used to get DMAMUX RequestGenerator status offset */ +#define DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants + * @{ + */ +/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function + * @{ + */ +#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */ +#define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */ +#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4 /*!< Request Generator 4 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5 /*!< Request Generator 5 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6 /*!< Request Generator 6 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7 /*!< Request Generator 7 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function + * @{ + */ +#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */ +#define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */ +#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4 /*!< Request Generator 4 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5 /*!< Request Generator 5 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6 /*!< Request Generator 6 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7 /*!< Request Generator 7 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions + * @{ + */ +#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ +#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX1_Request_selection DMAMUX1 Request selection + * @brief DMAMUX1 Request selection + * @{ + */ +/* DMAMUX1 requests */ +#define LL_DMAMUX1_REQ_MEM2MEM 0U /*!< memory to memory transfer */ +#define LL_DMAMUX1_REQ_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ +#define LL_DMAMUX1_REQ_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ +#define LL_DMAMUX1_REQ_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ +#define LL_DMAMUX1_REQ_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ +#define LL_DMAMUX1_REQ_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ +#define LL_DMAMUX1_REQ_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ +#define LL_DMAMUX1_REQ_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ +#define LL_DMAMUX1_REQ_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ +#define LL_DMAMUX1_REQ_ADC1 9U /*!< DMAMUX1 ADC1 request */ +#define LL_DMAMUX1_REQ_ADC2 10U /*!< DMAMUX1 ADC2 request */ +#define LL_DMAMUX1_REQ_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ +#define LL_DMAMUX1_REQ_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ +#define LL_DMAMUX1_REQ_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ +#define LL_DMAMUX1_REQ_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ +#define LL_DMAMUX1_REQ_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ +#define LL_DMAMUX1_REQ_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ +#define LL_DMAMUX1_REQ_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ +#define LL_DMAMUX1_REQ_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ +#define LL_DMAMUX1_REQ_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ +#define LL_DMAMUX1_REQ_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ +#define LL_DMAMUX1_REQ_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ +#define LL_DMAMUX1_REQ_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ +#define LL_DMAMUX1_REQ_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ +#define LL_DMAMUX1_REQ_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ +#define LL_DMAMUX1_REQ_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ +#define LL_DMAMUX1_REQ_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ +#define LL_DMAMUX1_REQ_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ +#define LL_DMAMUX1_REQ_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ +#define LL_DMAMUX1_REQ_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ +#define LL_DMAMUX1_REQ_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ +#define LL_DMAMUX1_REQ_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ +#define LL_DMAMUX1_REQ_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ +#define LL_DMAMUX1_REQ_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ +#define LL_DMAMUX1_REQ_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ +#define LL_DMAMUX1_REQ_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ +#define LL_DMAMUX1_REQ_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ +#define LL_DMAMUX1_REQ_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ +#define LL_DMAMUX1_REQ_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ +#define LL_DMAMUX1_REQ_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ +#define LL_DMAMUX1_REQ_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ +#define LL_DMAMUX1_REQ_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */ +#define LL_DMAMUX1_REQ_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */ +#define LL_DMAMUX1_REQ_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ +#define LL_DMAMUX1_REQ_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ +#define LL_DMAMUX1_REQ_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ +#define LL_DMAMUX1_REQ_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ +#define LL_DMAMUX1_REQ_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ +#define LL_DMAMUX1_REQ_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ +#define LL_DMAMUX1_REQ_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ +#define LL_DMAMUX1_REQ_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ +#define LL_DMAMUX1_REQ_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ +#define LL_DMAMUX1_REQ_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ +#define LL_DMAMUX1_REQ_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ +#define LL_DMAMUX1_REQ_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ +#define LL_DMAMUX1_REQ_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ +#define LL_DMAMUX1_REQ_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ +#define LL_DMAMUX1_REQ_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ +#define LL_DMAMUX1_REQ_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ +#define LL_DMAMUX1_REQ_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ +#define LL_DMAMUX1_REQ_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ +#define LL_DMAMUX1_REQ_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ +#define LL_DMAMUX1_REQ_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ +#define LL_DMAMUX1_REQ_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ +#define LL_DMAMUX1_REQ_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ +#define LL_DMAMUX1_REQ_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ +#define LL_DMAMUX1_REQ_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */ +#define LL_DMAMUX1_REQ_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */ +#define LL_DMAMUX1_REQ_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ +#define LL_DMAMUX1_REQ_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ +#define LL_DMAMUX1_REQ_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ +#define LL_DMAMUX1_REQ_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ +#define LL_DMAMUX1_REQ_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ +#define LL_DMAMUX1_REQ_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ +#if defined (PSSI) +#define LL_DMAMUX1_REQ_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */ +#define LL_DMAMUX1_REQ_DCMI LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */ +#else +#define LL_DMAMUX1_REQ_DCMI 75U /*!< DMAMUX1 DCMI request */ +#endif /* PSSI */ +#define LL_DMAMUX1_REQ_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */ +#define LL_DMAMUX1_REQ_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */ +#define LL_DMAMUX1_REQ_HASH_IN 78U /*!< DMAMUX1 HASH IN request */ +#define LL_DMAMUX1_REQ_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ +#define LL_DMAMUX1_REQ_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ +#define LL_DMAMUX1_REQ_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ +#define LL_DMAMUX1_REQ_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ +#define LL_DMAMUX1_REQ_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ +#define LL_DMAMUX1_REQ_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ +#define LL_DMAMUX1_REQ_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ +#define LL_DMAMUX1_REQ_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ +#define LL_DMAMUX1_REQ_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ +#define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ +#if defined(SAI2) +#define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ +#define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ +#endif /* SAI2 */ +#define LL_DMAMUX1_REQ_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */ +#define LL_DMAMUX1_REQ_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */ +#define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request */ +#define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request */ +#if defined (HRTIM1) +#define LL_DMAMUX1_REQ_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6 */ +#endif /* HRTIM1 */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM1 Filter0 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM1 Filter1 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM1 Filter2 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM1 Filter3 request */ +#define LL_DMAMUX1_REQ_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ +#define LL_DMAMUX1_REQ_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ +#define LL_DMAMUX1_REQ_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ +#define LL_DMAMUX1_REQ_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ +#define LL_DMAMUX1_REQ_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ +#define LL_DMAMUX1_REQ_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ +#define LL_DMAMUX1_REQ_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ +#define LL_DMAMUX1_REQ_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ +#if defined (SAI3) +#define LL_DMAMUX1_REQ_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ +#define LL_DMAMUX1_REQ_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ +#endif /* SAI3 */ +#if defined (ADC3) +#define LL_DMAMUX1_REQ_ADC3 115U /*!< DMAMUX1 ADC3 request */ +#endif /* ADC3 */ +#if defined (UART9) +#define LL_DMAMUX1_REQ_UART9_RX 116U /*!< DMAMUX1 UART9 RX request */ +#define LL_DMAMUX1_REQ_UART9_TX 117U /*!< DMAMUX1 UART9 TX request */ +#endif /* UART9 */ +#if defined (USART10) +#define LL_DMAMUX1_REQ_USART10_RX 118U /*!< DMAMUX1 USART10 RX request */ +#define LL_DMAMUX1_REQ_USART10_TX 119U /*!< DMAMUX1 USART10 TX request */ +#endif /* USART10 */ +#if defined(FMAC) +#define LL_DMAMUX1_REQ_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */ +#define LL_DMAMUX1_REQ_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */ +#endif /* FMAC */ +#if defined(CORDIC) +#define LL_DMAMUX1_REQ_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */ +#define LL_DMAMUX1_REQ_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */ +#endif /* CORDIC */ +#if defined(I2C5) +#define LL_DMAMUX1_REQ_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */ +#define LL_DMAMUX1_REQ_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */ +#endif /* I2C5 */ +#if defined(TIM23) +#define LL_DMAMUX1_REQ_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */ +#define LL_DMAMUX1_REQ_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */ +#define LL_DMAMUX1_REQ_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */ +#define LL_DMAMUX1_REQ_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */ +#define LL_DMAMUX1_REQ_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */ +#define LL_DMAMUX1_REQ_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */ +#endif /* TIM23 */ +#if defined(TIM24) +#define LL_DMAMUX1_REQ_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */ +#define LL_DMAMUX1_REQ_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */ +#define LL_DMAMUX1_REQ_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */ +#define LL_DMAMUX1_REQ_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */ +#define LL_DMAMUX1_REQ_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */ +#define LL_DMAMUX1_REQ_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */ +#endif /* TIM24 */ +/** + * @} + */ + +/** @defgroup DMAMUX2_Request_selection DMAMUX2 Request selection + * @brief DMAMUX2 Request selection + * @{ + */ +/* DMAMUX2 requests */ +#define LL_DMAMUX2_REQ_MEM2MEM 0U /*!< memory to memory transfer */ +#define LL_DMAMUX2_REQ_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */ +#define LL_DMAMUX2_REQ_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */ +#define LL_DMAMUX2_REQ_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */ +#define LL_DMAMUX2_REQ_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */ +#define LL_DMAMUX2_REQ_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */ +#define LL_DMAMUX2_REQ_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */ +#define LL_DMAMUX2_REQ_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */ +#define LL_DMAMUX2_REQ_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */ +#define LL_DMAMUX2_REQ_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */ +#define LL_DMAMUX2_REQ_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */ +#define LL_DMAMUX2_REQ_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */ +#define LL_DMAMUX2_REQ_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */ +#define LL_DMAMUX2_REQ_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */ +#define LL_DMAMUX2_REQ_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */ +#if defined (SAI4) +#define LL_DMAMUX2_REQ_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */ +#define LL_DMAMUX2_REQ_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */ +#endif /* SAI4 */ +#if defined (ADC3) +#define LL_DMAMUX2_REQ_ADC3 17U /*!< DMAMUX2 ADC3 request */ +#endif /* ADC3 */ +#if defined (DAC2) +#define LL_DMAMUX2_REQ_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */ +#endif /* DAC2 */ +#if defined (DFSDM2_Channel0) +#define LL_DMAMUX2_REQ_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 Filter0 request */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ + + +/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel + * @{ + */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX1 Channel 0 connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX1 Channel 1 connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX1 Channel 2 connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */ +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX1 Channel 3 connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */ +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX1 Channel 4 connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */ +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX1 Channel 5 connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */ +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX1 Channel 6 connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */ +#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX1 Channel 7 connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA2 Channel 0 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */ +#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */ +#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */ +#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity + * @{ + */ +#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ +#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */ +#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */ +#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event + * @{ + */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */ +#define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */ +#define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */ +#define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */ +#define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */ +#define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */ + +#define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */ +#define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */ +#define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */ +#define LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */ +#define LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */ +#define LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */ +#define LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */ +#define LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */ +#define LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */ +#define LL_DMAMUX2_SYNC_EXTI0 0x0E000000U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */ +#define LL_DMAMUX2_SYNC_EXTI2 0x0F000000U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */ + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel + * @{ + */ +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U +#define LL_DMAMUX_REQ_GEN_4 0x00000004U +#define LL_DMAMUX_REQ_GEN_5 0x00000005U +#define LL_DMAMUX_REQ_GEN_6 0x00000006U +#define LL_DMAMUX_REQ_GEN_7 0x00000007U +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity + * @{ + */ +#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */ +#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */ +#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */ +#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation + * @{ + */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */ +#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */ +#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */ +#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */ +#define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */ +#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */ + +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */ +#define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */ +#if defined (LPTIM4) +#define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */ +#endif /* LPTIM4 */ +#if defined (LPTIM5) +#define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */ +#endif /* LPTIM5 */ +#define LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */ +#define LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */ +#define LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */ +#define LL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */ +#define LL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */ +#define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */ +#define LL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */ +#if defined (ADC3) +#define LL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */ +#define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */ +#endif /* ADC3 */ +#define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */ +#define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros + * @{ + */ + +/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions + * @{ + */ + +/** @defgroup DMAMUX_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Set DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. + * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. + * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * @arg @ref LL_DMAMUX2_REQ_MEM2MEM + * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX2_REQ_SPI6_RX + * @arg @ref LL_DMAMUX2_REQ_SPI6_TX + * @arg @ref LL_DMAMUX2_REQ_I2C4_RX + * @arg @ref LL_DMAMUX2_REQ_I2C4_TX + * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) + * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) + * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) + * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) + * + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. + * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. + * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * @arg @ref LL_DMAMUX2_REQ_MEM2MEM + * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX2_REQ_SPI6_RX + * @arg @ref LL_DMAMUX2_REQ_SPI6_TX + * @arg @ref LL_DMAMUX2_REQ_I2C4_RX + * @arg @ref LL_DMAMUX2_REQ_I2C4_TX + * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) + * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) + * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) + * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) + * + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL)); +} + +/** + * @brief Enable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Disable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_EnableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Disable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_DisableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Check if the synchronization mode is enabled or disabled. + * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); +} + +/** + * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param SyncID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_SYNC_EXTI0 + * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP + * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP + * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT + * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP + * @arg @ref LL_DMAMUX2_SYNC_EXTI0 + * @arg @ref LL_DMAMUX2_SYNC_EXTI2 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); +} + +/** + * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_SYNC_EXTI0 + * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP + * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP + * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT + * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP + * @arg @ref LL_DMAMUX2_SYNC_EXTI0 + * @arg @ref LL_DMAMUX2_SYNC_EXTI2 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID)); +} + +/** + * @brief Enable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Disable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Check if the Request Generator is enabled or disabled. + * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a generation event. + * @note This field can only be written when Generator is disabled. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a generation event. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); +} + +/** + * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @param RequestSignalID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0 + * @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0 + * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2 + * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); +} + +/** + * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_SYNC_EXTI0 + * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP + * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP + * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT + * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP + * @arg @ref LL_DMAMUX2_SYNC_EXTI0 + * @arg @ref LL_DMAMUX2_SYNC_EXTI2 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID)); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Synchronization Event Overrun Flag Channel 0. + * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 1. + * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 2. + * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 3. + * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 4. + * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 5. + * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 6. + * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 7. + * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 8. + * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 9. + * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 10. + * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 11. + * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 12. + * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 13. + * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 14. + * @rmtoll CSR SOF14 LL_DMAMUX_IsActiveFlag_SO14 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 15. + * @rmtoll CSR SOF15 LL_DMAMUX_IsActiveFlag_SO15 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 4 Trigger Event Overrun Flag. + * @rmtoll RGSR OF4 LL_DMAMUX_IsActiveFlag_RGO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 5 Trigger Event Overrun Flag. + * @rmtoll RGSR OF5 LL_DMAMUX_IsActiveFlag_RGO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 6 Trigger Event Overrun Flag. + * @rmtoll RGSR OF6 LL_DMAMUX_IsActiveFlag_RGO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 7 Trigger Event Overrun Flag. + * @rmtoll RGSR OF7 LL_DMAMUX_IsActiveFlag_RGO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 0. + * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 1. + * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 2. + * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 3. + * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 4. + * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 5. + * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 6. + * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 7. + * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 8. + * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 9. + * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 10. + * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 11. + * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 12. + * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 13. + * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 14. + * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 15. + * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15); +} + +/** + * @brief Clear Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0); +} + +/** + * @brief Clear Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1); +} + +/** + * @brief Clear Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2); +} + +/** + * @brief Clear Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3); +} + +/** + * @brief Clear Request Generator 4 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF4 LL_DMAMUX_ClearFlag_RGO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4); +} + +/** + * @brief Clear Request Generator 5 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF5 LL_DMAMUX_ClearFlag_RGO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5); +} + +/** + * @brief Clear Request Generator 6 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF6 LL_DMAMUX_ClearFlag_RGO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6); +} + +/** + * @brief Clear Request Generator 7 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF7 LL_DMAMUX_ClearFlag_RGO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE)); +} + +/** + * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 || DMAMUX2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_DMAMUX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h new file mode 100644 index 0000000..885f22d --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h @@ -0,0 +1,3285 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_LL_EXTI_H +#define __STM32H7xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_64_95; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ +#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ +#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ +#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ +#define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ +#if defined(USB2_OTG_FS) +#define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ +#endif /* USB2_OTG_FS */ +#if defined(DSI) +#define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ +#endif /* DSI */ +#define LL_EXTI_LINE_47 EXTI_IMR2_IM47 /*!< Extended line 47 */ +#define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ +#define LL_EXTI_LINE_49 EXTI_IMR2_IM49 /*!< Extended line 49 */ +#define LL_EXTI_LINE_50 EXTI_IMR2_IM50 /*!< Extended line 50 */ +#define LL_EXTI_LINE_51 EXTI_IMR2_IM51 /*!< Extended line 51 */ +#define LL_EXTI_LINE_52 EXTI_IMR2_IM52 /*!< Extended line 52 */ +#define LL_EXTI_LINE_53 EXTI_IMR2_IM53 /*!< Extended line 53 */ +#define LL_EXTI_LINE_54 EXTI_IMR2_IM54 /*!< Extended line 54 */ +#define LL_EXTI_LINE_55 EXTI_IMR2_IM55 /*!< Extended line 55 */ +#define LL_EXTI_LINE_56 EXTI_IMR2_IM56 /*!< Extended line 56 */ +#if defined(EXTI_IMR2_IM57) +#define LL_EXTI_LINE_57 EXTI_IMR2_IM57 /*!< Extended line 57 */ +#endif /*EXTI_IMR2_IM57*/ +#define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */ +#if defined(EXTI_IMR2_IM59) +#define LL_EXTI_LINE_59 EXTI_IMR2_IM59 /*!< Extended line 59 */ +#endif /*EXTI_IMR2_IM59*/ +#define LL_EXTI_LINE_60 EXTI_IMR2_IM60 /*!< Extended line 60 */ +#define LL_EXTI_LINE_61 EXTI_IMR2_IM61 /*!< Extended line 61 */ +#define LL_EXTI_LINE_62 EXTI_IMR2_IM62 /*!< Extended line 62 */ +#define LL_EXTI_LINE_63 EXTI_IMR2_IM63 /*!< Extended line 63 */ +#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_64 EXTI_IMR3_IM64 /*!< Extended line 64 */ +#define LL_EXTI_LINE_65 EXTI_IMR3_IM65 /*!< Extended line 65 */ +#define LL_EXTI_LINE_66 EXTI_IMR3_IM66 /*!< Extended line 66 */ +#define LL_EXTI_LINE_67 EXTI_IMR3_IM67 /*!< Extended line 67 */ +#define LL_EXTI_LINE_68 EXTI_IMR3_IM68 /*!< Extended line 68 */ +#define LL_EXTI_LINE_69 EXTI_IMR3_IM69 /*!< Extended line 69 */ +#define LL_EXTI_LINE_70 EXTI_IMR3_IM70 /*!< Extended line 70 */ +#define LL_EXTI_LINE_71 EXTI_IMR3_IM71 /*!< Extended line 71 */ +#define LL_EXTI_LINE_72 EXTI_IMR3_IM72 /*!< Extended line 72 */ +#define LL_EXTI_LINE_73 EXTI_IMR3_IM73 /*!< Extended line 73 */ +#define LL_EXTI_LINE_74 EXTI_IMR3_IM74 /*!< Extended line 74 */ +#if defined(ADC3) +#define LL_EXTI_LINE_75 EXTI_IMR3_IM75 /*!< Extended line 75 */ +#endif /* ADC3 */ +#if defined(SAI4) +#define LL_EXTI_LINE_76 EXTI_IMR3_IM76 /*!< Extended line 76 */ +#endif /* SAI4 */ +#if defined(DUAL_CORE) +#define LL_EXTI_LINE_77 EXTI_IMR3_IM77 /*!< Extended line 77 */ +#define LL_EXTI_LINE_78 EXTI_IMR3_IM78 /*!< Extended line 78 */ +#define LL_EXTI_LINE_79 EXTI_IMR3_IM79 /*!< Extended line 79 */ +#define LL_EXTI_LINE_80 EXTI_IMR3_IM80 /*!< Extended line 80 */ +#define LL_EXTI_LINE_82 EXTI_IMR3_IM82 /*!< Extended line 82 */ +#define LL_EXTI_LINE_84 EXTI_IMR3_IM84 /*!< Extended line 84 */ +#endif /* DUAL_CORE */ +#define LL_EXTI_LINE_85 EXTI_IMR3_IM85 /*!< Extended line 85 */ +#if defined(ETH) +#define LL_EXTI_LINE_86 EXTI_IMR3_IM86 /*!< Extended line 86 */ +#endif /* ETH */ +#define LL_EXTI_LINE_87 EXTI_IMR3_IM87 /*!< Extended line 87 */ +#if defined(DTS) +#define LL_EXTI_LINE_88 EXTI_IMR3_IM88 /*!< Extended line 88 */ +#endif /* DTS */ +#if defined(EXTI_IMR3_IM89) +#define LL_EXTI_LINE_89 EXTI_IMR3_IM89 /*!< Extended line 89 */ +#endif /* EXTI_IMR3_IM89 */ +#if defined(EXTI_IMR3_IM90) +#define LL_EXTI_LINE_90 EXTI_IMR3_IM90 /*!< Extended line 90 */ +#endif /* EXTI_IMR3_IM90 */ +#if defined(I2C5) +#define LL_EXTI_LINE_91 EXTI_IMR3_IM91 /*!< Extended line 91 */ +#endif /* I2C5 */ +#define LL_EXTI_LINE_ALL_64_95 EXTI_IMR3_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x01U) /*!< Cortex-M7 Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x02U) /*!< Cortex-M7 Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x03U) /*!< Cortex-M7 Interrupt & Event Mode */ + +#if defined(DUAL_CORE) +#define LL_EXTI_MODE_C1_IT LL_EXTI_MODE_IT /*!< Cortex-M7 Interrupt Mode */ +#define LL_EXTI_MODE_C1_EVENT LL_EXTI_MODE_EVENT /*!< Cortex-M7 Event Mode */ +#define LL_EXTI_MODE_C1_IT_EVENT LL_EXTI_MODE_IT_EVENT /*!< Cortex-M7 Interrupt & Event Mode */ + +#define LL_EXTI_MODE_C2_IT ((uint8_t)0x10U) /*!< Cortex-M4 Interrupt Mode */ +#define LL_EXTI_MODE_C2_EVENT ((uint8_t)0x20U) /*!< Cortex-M4 Event Mode */ +#define LL_EXTI_MODE_C2_IT_EVENT ((uint8_t)0x30U) /*!< Cortex-M4 Interrupt & Event Mode */ +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_D3_PEND_CLR D3 Pend Clear Source + * @{ + */ +#define LL_EXTI_D3_PEND_CLR_DMACH6 ((uint8_t)0x00U) /*!< DMA ch6 event selected as D3 domain pendclear source */ +#define LL_EXTI_D3_PEND_CLR_DMACH7 ((uint8_t)0x01U) /*!< DMA ch7 event selected as D3 domain pendclear source */ +#if defined (LPTIM4) +#define LL_EXTI_D3_PEND_CLR_LPTIM4 ((uint8_t)0x02U) /*!< LPTIM4 out selected as D3 domain pendclear source */ +#else +#define LL_EXTI_D3_PEND_CLR_LPTIM2 ((uint8_t)0x02U) /*!< LPTIM2 out selected as D3 domain pendclear source */ +#endif /*LPTIM4*/ +#if defined (LPTIM5) +#define LL_EXTI_D3_PEND_CLR_LPTIM5 ((uint8_t)0x03U) /*!< LPTIM5 out selected as D3 domain pendclear source */ +#else +#define LL_EXTI_D3_PEND_CLR_LPTIM3 ((uint8_t)0x02U) /*!< LPTIM3 out selected as D3 domain pendclear source */ +#endif /*LPTIM5*/ +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) + +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_EnableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_DisableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR3, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_IsEnabledIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR1, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR2, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll C2IMR3 IMx LL_C2_EXTI_EnableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR1, ExtiLine); +} + + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR2, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 64 to 95 for cpu2 + * @rmtoll C2IMR3 IMx LL_C2_EXTI_DisableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR3, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine))? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95 + * @rmtoll C2IMR3 IMx LL_C2_EXTI_IsEnabledIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#endif /* DUAL_CORE */ + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_EnableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_DisableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR3, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_IsEnabledEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#if defined(DUAL_CORE) + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR1, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 64 to 95 for cpu2 + * @rmtoll C2EMR3 EMx LL_C2_EXTI_EnableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR1, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR2, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 64 to 95 for cpu2 + * @rmtoll C2EMR3 EMx LL_C2_EXTI_DisableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR3, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 for cpu2 + * @rmtoll C2EMR3 EMx LL_C2_EXTI_IsEnabledEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR3 RTx LL_EXTI_EnableRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR3 RTx LL_EXTI_DisableRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR3, ExtiLine); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 64 to 95 + * @rmtoll RTSR3 RTx LL_EXTI_IsEnabledRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR3 FTx LL_EXTI_EnableFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR3 FTx LL_EXTI_DisableFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR3, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 64 to 95 + * @rmtoll FTSR3 FTx LL_EXTI_IsEnabledFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR1 + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 64 to 95 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR3 + * register (by writing a 1 into the bit) + * @rmtoll SWIER3 SWIx LL_EXTI_GenerateSWI_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER3, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR3 PIFx LL_EXTI_IsActiveFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR3 PIFx LL_EXTI_ReadFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR3, ExtiLine)); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR2, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR3 PIFx LL_EXTI_ClearFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR3, ExtiLine); +} + +#if defined(DUAL_CORE) + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR1 PIFx LL_C2_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR2 PIFx LL_C2_EXTI_IsActiveFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 64 to 95 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR3 PIFx LL_C2_EXTI_IsActiveFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR1 PIFx LL_C2_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->C2PR1, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR2 PIFx LL_C2_EXTI_ReadFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->C2PR2, ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 64 to 95 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR3 PIFx LL_C2_EXTI_ReadFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_64_95(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->C2PR3, ExtiLine)); +} +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR1 PIFx LL_C2_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->C2PR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR2 PIFx LL_C2_EXTI_ClearFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_ClearFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->C2PR2, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 64 to 95 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR3 PIFx LL_C2_EXTI_ClearFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_ClearFlag_64_95(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->C2PR3, ExtiLine); +} + +#endif /* DUAL_CORE */ + +/** + * @brief Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31 + * @rmtoll D3PMR1 MRx LL_D3_EXTI_EnablePendMask_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->D3PMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63 + * @rmtoll D3PMR2 MRx LL_D3_EXTI_EnablePendMask_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->D3PMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31 + * @rmtoll D3PMR1 MRx LL_D3_EXTI_DisablePendMask_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->D3PMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63 + * @rmtoll D3PMR2 MRx LL_D3_EXTI_DisablePendMask_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->D3PMR2, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31 + * @rmtoll D3PMR1 MRx LL_D3_EXTI_IsEnabledPendMask_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->D3PMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63 + * @rmtoll D3PMR2 MRx LL_D3_EXTI_IsEnabledPendMask_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->D3PMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15 + * @rmtoll D3PCR1L PCSx LL_D3_EXTI_SetPendClearSel_0_15 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc)); +} + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31 + * @rmtoll D3PCR1H PCSx LL_D3_EXTI_SetPendClearSel_16_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * ClrSrc)); +} + + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47 + * @rmtoll D3PCR2L PCSx LL_D3_EXTI_SetPendClearSel_32_47 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc)); +} + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63 + * @rmtoll D3PCR2H PCSx LL_D3_EXTI_SetPendClearSel_48_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * ClrSrc)); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15 + * @rmtoll D3PCR1L PCSx LL_D3_EXTI_GetPendClearSel_0_15 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine)); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31 + * @rmtoll D3PCR1H PCSx LL_D3_EXTI_GetPendClearSel_16_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos))); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47 + * @rmtoll D3PCR2L PCSx LL_D3_EXTI_GetPendClearSel_32_47 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine)); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63 + * @rmtoll D3PCR2H PCSx LL_D3_EXTI_GetPendClearSel_48_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos))); +} + + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{, + */ + +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +ErrorStatus LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_EXTI_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h new file mode 100644 index 0000000..b099741 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h @@ -0,0 +1,984 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_GPIO_H +#define STM32H7xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed)); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + ((((Pin * Pin) * Pin) * Pin) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * + (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask << 16U); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /*defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_GPIO_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h new file mode 100644 index 0000000..689b7e5 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h @@ -0,0 +1,902 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_hsem.h + * @author MCD Application Team + * @brief Header file of HSEM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_HSEM_H +#define STM32H7xx_LL_HSEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(HSEM) + +/** @defgroup HSEM_LL HSEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants + * @{ + */ + +/** @defgroup HSEM_LL_EC_COREID COREID Defines + * @{ + */ +#define LL_HSEM_COREID_NONE 0U +#define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1 +#if defined(DUAL_CORE) +#define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2 +#endif /* DUAL_CORE */ +#define LL_HSEM_COREID HSEM_CR_COREID_CURRENT +/** + * @} + */ + + +/** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_HSEM_ReadReg function + * @{ + */ + +#define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0 +#define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1 +#define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2 +#define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3 +#define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4 +#define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5 +#define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6 +#define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7 +#define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8 +#define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9 +#define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10 +#define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11 +#define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12 +#define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13 +#define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14 +#define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15 +#if (HSEM_SEMID_MAX == 15) +#define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU +#else /* HSEM_SEMID_MAX == 31 */ +#define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16 +#define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17 +#define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18 +#define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19 +#define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20 +#define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21 +#define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22 +#define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23 +#define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24 +#define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25 +#define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26 +#define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27 +#define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28 +#define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29 +#define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30 +#define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31 +#define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU +#endif /* HSEM_SEMID_MAX == 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros + * @{ + */ + +/** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in HSEM register + * @param __INSTANCE__ HSEM Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in HSEM register + * @param __INSTANCE__ HSEM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @defgroup HSEM_LL_EF_Data_Management Data_Management + * @{ + */ + + +/** + * @brief Return 1 if the semaphore is locked, else return 0. + * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Get core id. + * @rmtoll R COREID LL_HSEM_GetCoreId + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval Returned value can be one of the following values: + * @arg @ref LL_HSEM_COREID_NONE + * @arg @ref LL_HSEM_COREID_CPU1 + * @arg @ref LL_HSEM_COREID_CPU2 + */ +__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); +} + +/** + * @brief Get process id. + * @rmtoll R PROCID LL_HSEM_GetProcessId + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval Process number. Value between Min_Data=0 and Max_Data=255 + */ +__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); +} + +/** + * @brief Get the lock by writing in R register. + * @note The R register has to be read to determined if the lock is taken. + * @rmtoll R LOCK LL_HSEM_SetLock + * @rmtoll R COREID LL_HSEM_SetLock + * @rmtoll R PROCID LL_HSEM_SetLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process id. Value between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) +{ + WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process)); +} + +/** + * @brief Get the lock with 2-step lock. + * @rmtoll R LOCK LL_HSEM_2StepLock + * @rmtoll R COREID LL_HSEM_2StepLock + * @rmtoll R PROCID LL_HSEM_2StepLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process id. Value between Min_Data=0 and Max_Data=255 + * @retval 1 lock fail, 0 lock successful or already locked by same process and core + */ +__STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) +{ + WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process)); + return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL); +} + +/** + * @brief Get the lock with 1-step lock. + * @rmtoll RLR LOCK LL_HSEM_1StepLock + * @rmtoll RLR COREID LL_HSEM_1StepLock + * @rmtoll RLR PROCID LL_HSEM_1StepLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval 1 lock fail, 0 lock successful or already locked by same core + */ +__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); +} + +/** + * @brief Release the lock of the semaphore. + * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0. + * @rmtoll R LOCK LL_HSEM_ReleaseLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process number. Value between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) +{ + WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process)); +} + +/** + * @brief Get the lock status of the semaphore. + * @rmtoll R LOCK LL_HSEM_GetStatus + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval 0 semaphore is free, 1 semaphore is locked */ +__STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); +} + +/** + * @brief Set the key. + * @rmtoll KEYR KEY LL_HSEM_SetKey + * @param HSEMx HSEM Instance. + * @param key Key value. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) +{ + WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos); +} + +/** + * @brief Get the key. + * @rmtoll KEYR KEY LL_HSEM_GetKey + * @param HSEMx HSEM Instance. + * @retval key to unlock all semaphore from the same core + */ +__STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx) +{ + return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); +} + +/** + * @brief Release all semaphore with the same core id. + * @rmtoll CR KEY LL_HSEM_ResetAllLock + * @rmtoll CR SEC LL_HSEM_ResetAllLock + * @rmtoll CR PRIV LL_HSEM_ResetAllLock + * @param HSEMx HSEM Instance. + * @param key Key value. + * @param core This parameter can be one of the following values: + * @arg @ref LL_HSEM_COREID_CPU1 + * @arg @ref LL_HSEM_COREID_CPU2 + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core) +{ + WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core); +} + +/** + * @} + */ + +/** @defgroup HSEM_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable interrupt. + * @rmtoll C1IER ISEM LL_HSEM_EnableIT_C1IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + SET_BIT(HSEMx->C1IER, SemaphoreMask); +} + +/** + * @brief Disable interrupt. + * @rmtoll C1IER ISEM LL_HSEM_DisableIT_C1IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + CLEAR_BIT(HSEMx->C1IER, SemaphoreMask); +} + +/** + * @brief Check if interrupt is enabled. + * @rmtoll C1IER ISEM LL_HSEM_IsEnabledIT_C1IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable interrupt. + * @rmtoll C2IER ISEM LL_HSEM_EnableIT_C2IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + SET_BIT(HSEMx->C2IER, SemaphoreMask); +} + +/** + * @brief Disable interrupt. + * @rmtoll C2IER ISEM LL_HSEM_DisableIT_C2IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + CLEAR_BIT(HSEMx->C2IER, SemaphoreMask); +} + +/** + * @brief Check if interrupt is enabled. + * @rmtoll C2IER ISEM LL_HSEM_IsEnabledIT_C2IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Clear interrupt status. + * @rmtoll C1ICR ISEM LL_HSEM_ClearFlag_C1ICR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + WRITE_REG(HSEMx->C1ICR, SemaphoreMask); +} + +/** + * @brief Get interrupt status from ISR register. + * @rmtoll C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +/** + * @brief Get interrupt status from MISR register. + * @rmtoll C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Clear interrupt status. + * @rmtoll C2ICR ISEM LL_HSEM_ClearFlag_C2ICR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + WRITE_REG(HSEMx->C2ICR, SemaphoreMask); +} + +/** + * @brief Get interrupt status from ISR register. + * @rmtoll C2ISR ISEM LL_HSEM_IsActiveFlag_C2ISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +/** + * @brief Get interrupt status from MISR register. + * @rmtoll C2MISR ISEM LL_HSEM_IsActiveFlag_C2MISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(HSEM) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_HSEM_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h new file mode 100644 index 0000000..be137a4 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h @@ -0,0 +1,2301 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_PWR_H +#define STM32H7xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_LL_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +/* Wake-Up Pins PWR register offsets */ +#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL +#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU +/** + * @} + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /*!< Clear flags for CPU */ +#if defined (DUAL_CORE) +#define LL_PWR_FLAG_CPU2_CSSF PWR_CPU2CR_CSSF /*!< Clear flags for CPU2 */ +#endif /* DUAL_CORE */ +#define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /*!< Clear PC1 WKUP flag */ +#if defined (PWR_WKUPCR_WKUPC5) +#define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /*!< Clear PI11 WKUP flag */ +#endif /* defined (PWR_WKUPCR_WKUPC5) */ +#define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear PC13 WKUP flag */ +#if defined (PWR_WKUPCR_WKUPC3) +#define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear PI8 WKUP flag */ +#endif /* defined (PWR_WKUPCR_WKUPC3) */ +#define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear PA2 WKUP flag */ +#define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear PA0 WKUP flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /*!< Analog voltage detector output on VDDA flag */ +#define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /*!< Programmable voltage detect output flag */ +#define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS /*!< Current VOS applied for VCORE voltage scaling flag */ +#define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */ +#if defined (PWR_CSR1_MMCVDO) +#define LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO /*!< Voltage detector output on VDDMMC flag */ +#endif /* PWR_CSR1_MMCVDO */ + +#define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /*!< Temperature high threshold flag */ +#define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /*!< Temperature low threshold flag */ +#define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /*!< VBAT high threshold flag */ +#define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /*!< VBAT low threshold flag */ +#define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /*!< Backup Regulator ready flag */ + +#define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /*!< USB supply ready flag */ +#define LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY /*!< SMPS External supply ready flag */ + +#if defined (PWR_CPUCR_SBF_D2) +#define LL_PWR_FLAG_CPU_SBF_D2 PWR_CPUCR_SBF_D2 /*!< D2 domain DSTANDBY Flag */ +#endif /* PWR_CPUCR_SBF_D2 */ +#if defined (PWR_CPUCR_SBF_D1) +#define LL_PWR_FLAG_CPU_SBF_D1 PWR_CPUCR_SBF_D1 /*!< D1 domain DSTANDBY Flag */ +#endif /* PWR_CPUCR_SBF_D1 */ +#define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF /*!< System STANDBY Flag */ +#define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF /*!< STOP Flag */ +#if defined (DUAL_CORE) +#define LL_PWR_FLAG_CPU_HOLD2F PWR_CPUCR_HOLD2F /*!< CPU2 in hold wakeup flag */ +#endif /* DUAL_CORE */ + +#if defined (DUAL_CORE) +#define LL_PWR_FLAG_CPU2_SBF_D2 PWR_CPU2CR_SBF_D2 /*!< D2 domain DSTANDBY Flag */ +#define LL_PWR_FLAG_CPU2_SBF_D1 PWR_CPU2CR_SBF_D1 /*!< D1 domain DSTANDBY Flag */ +#define LL_PWR_FLAG_CPU2_SBF PWR_CPU2CR_SBF /*!< System STANDBY Flag */ +#define LL_PWR_FLAG_CPU2_STOPF PWR_CPU2CR_STOPF /*!< STOP Flag */ +#define LL_PWR_FLAG_CPU2_HOLD1F PWR_CPU2CR_HOLD1F /*!< CPU1 in hold wakeup flag */ +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY /*!< Voltage scaling ready flag */ +#else +#define LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY /*!< Voltage scaling ready flag */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ +#if defined (PWR_WKUPFR_WKUPF5) +#define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ +#endif /* defined (PWR_WKUPFR_WKUPF5) */ +#define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ +#endif /* defined (PWR_WKUPFR_WKUPF3) */ +#define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ +#define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Power mode + * @{ + */ +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_CPU_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep */ +#else +#define LL_PWR_CPU_MODE_CDSTOP 0x00000000U /*!< Enter CD domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_CPU_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_D2STANDBY PWR_CPUCR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_CPU_MODE_D3RUN PWR_CPUCR_RUN_D3 /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep */ +#define LL_PWR_CPU_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_D3STANDBY PWR_CPUCR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep */ +#else +#define LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep */ +#define LL_PWR_CPU_MODE_SRDSTOP 0x00000000U /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +#define LL_PWR_CPU2_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D1STANDBY PWR_CPU2CR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D2STANDBY PWR_CPU2CR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D3RUN PWR_CPU2CR_RUN_D3 /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep */ +#define LL_PWR_CPU2_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D3STANDBY PWR_CPU2CR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling + * @{ + */ +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /*!< Select voltage scale 3 */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /*!< Select voltage scale 2 */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */ +#if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ +#define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */ +#else +#define LL_PWR_REGU_VOLTAGE_SCALE0 0x00000000U /*!< Select voltage scale 0 */ +#endif /* defined (SYSCFG_PWRCR_ODEN) */ +#else +#define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Select voltage scale 3 */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0 /*!< Select voltage scale 2 */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1 /*!< Select voltage scale 1 */ +#define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */ +#endif /* PWR_CPUCR_PDDS_D2 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector + * @{ + */ +#define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 1.95 V */ +#define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */ +#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.25 V */ +#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.4 V */ +#define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.55 V */ +#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.85 V */ +#define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector + * @{ + */ +#define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog Voltage threshold detected by AVD 1.7 V */ +#define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog Voltage threshold detected by AVD 2.1 V */ +#define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog Voltage threshold detected by AVD 2.5 V */ +#define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog Voltage threshold detected by AVD 2.8 V */ + +/** + * @} + */ + +/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor + * @{ + */ +#define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /*!< Charge the Battery through a 5 kO resistor */ +#define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /*!< Charge the Battery through a 1.5 kO resistor */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PI8 */ +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC13 */ +#if defined (PWR_WKUPEPR_WKUPEN5) +#define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /*!< Wake-Up pin 5 : PI11 */ +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /*!< Wake-Up pin 6 : PC1 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration + * @{ + */ +#define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */ +#define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */ +#define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration + * @{ + */ +#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ +#if defined (SMPS) +#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS */ +#define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ +#define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ +#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ +#define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ +#endif /* SMPS */ +#define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + + /** + * @brief Set the voltage Regulator mode during deep sleep mode + * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode); +} + +/** + * @brief Get the voltage Regulator mode during deep sleep mode + * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR1 PVDEN LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR1 PVDEN LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR1 PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR1 PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Flash Power Down in Stop Mode + * @rmtoll CR1 FLPS LL_PWR_EnableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Disable the Flash Power Down in Stop Mode + * @rmtoll CR1 FLPS LL_PWR_DisableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Check if the Flash Power Down in Stop Mode is enabled + * @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashPowerDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL); +} + +#if defined (PWR_CR1_BOOSTE) +/** + * @brief Enable the Analog Voltage Booster (VDDA) + * @rmtoll CR1 BOOSTE LL_PWR_EnableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Disable the Analog Voltage Booster (VDDA) + * @rmtoll CR1 BOOSTE LL_PWR_DisableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Check if the Analog Voltage Booster (VDDA) is enabled + * @rmtoll CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_BOOSTE */ + +#if defined (PWR_CR1_AVD_READY) +/** + * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready + * @rmtoll CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AVD_READY); +} + +/** + * @brief Disable the Analog Voltage Ready (VDDA) + * @rmtoll CR1 AVD_READY LL_PWR_DisableAnalogVoltageReady + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY); +} + +/** + * @brief Check if the Analog Voltage Booster (VDDA) is enabled + * @rmtoll CR1 AVD_READY LL_PWR_IsEnabledAnalogVoltageReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AVD_READY */ + +/** + * @brief Set the internal Regulator output voltage in STOP mode + * @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); +} + +/** + * @brief Get the internal Regulator output voltage in STOP mode + * @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 + */ +__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS)); +} + +/** + * @brief Enable Analog Power Voltage Detector + * @rmtoll CR1 AVDEN LL_PWR_EnableAVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Disable Analog Power Voltage Detector + * @rmtoll CR1 AVDEN LL_PWR_DisableAVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Check if Analog Power Voltage Detector is enabled + * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector + * @rmtoll CR1 ALS LL_PWR_SetAVDLevel + * @param AVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_AVDLEVEL_0 + * @arg @ref LL_PWR_AVDLEVEL_1 + * @arg @ref LL_PWR_AVDLEVEL_2 + * @arg @ref LL_PWR_AVDLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel); +} + +/** + * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector + * @rmtoll CR1 ALS LL_PWR_GetAVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_AVDLEVEL_0 + * @arg @ref LL_PWR_AVDLEVEL_1 + * @arg @ref LL_PWR_AVDLEVEL_2 + * @arg @ref LL_PWR_AVDLEVEL_3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS)); +} + +#if defined (PWR_CR1_AXIRAM1SO) +/** + * @brief Enable the AXI RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM1SO LL_PWR_EnableAXIRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); +} + +/** + * @brief Disable the AXI RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM1SO LL_PWR_DisableAXIRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); +} + +/** + * @brief Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AXIRAM1SO LL_PWR_IsEnabledAXIRAM1ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AXIRAM1SO */ + +#if defined (PWR_CR1_AXIRAM2SO) +/** + * @brief Enable the AXI RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM2SO LL_PWR_EnableAXIRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); +} + +/** + * @brief Disable the AXI RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM2SO LL_PWR_DisableAXIRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); +} + +/** + * @brief Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AXIRAM2SO LL_PWR_IsEnabledAXIRAM2ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AXIRAM2SO */ + +#if defined (PWR_CR1_AXIRAM3SO) +/** + * @brief Enable the AXI RAM3 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM3SO LL_PWR_EnableAXIRAM3ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); +} + +/** + * @brief Disable the AXI RAM3 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM3SO LL_PWR_DisableAXIRAM3ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); +} + +/** + * @brief Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AXIRAM3SO LL_PWR_IsEnabledAXIRAM3ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AXIRAM3SO */ + +#if defined (PWR_CR1_AHBRAM1SO) +/** + * @brief Enable the AHB RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM1SO LL_PWR_EnableAHBRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); +} + +/** + * @brief Disable the AHB RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM1SO LL_PWR_DisableAHBRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); +} + +/** + * @brief Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AHBRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AHBRAM1SO */ + +#if defined (PWR_CR1_AHBRAM2SO) +/** + * @brief Enable the AHB RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM2SO LL_PWR_EnableAHBRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); +} + +/** + * @brief Disable the AHB RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM2SO LL_PWR_DisableAHBRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); +} + +/** + * @brief Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AHBRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AHBRAM2SO */ + +#if defined (PWR_CR1_ITCMSO) +/** + * @brief Enable the ITCM shut-off in DStop/DStop2 mode + * @rmtoll CR1 ITCMSO LL_PWR_EnableITCMSOShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ITCMSO); +} + +/** + * @brief Disable the ITCM shut-off in DStop/DStop2 mode + * @rmtoll CR1 ITCMSO LL_PWR_DisableITCMSOShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO); +} + +/** + * @brief Check if the ITCM shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 ITCMSO LL_PWR_IsEnabledITCMShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_ITCMSO */ + +#if defined (PWR_CR1_HSITFSO) +/** + * @brief Enable the USB and FDCAN shut-off in DStop/DStop2 mode + * @rmtoll CR1 HSITFSO LL_PWR_EnableHSITFShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_HSITFSO); +} + +/** + * @brief Disable the USB and FDCAN shut-off in DStop/DStop2 mode + * @rmtoll CR1 HSITFSO LL_PWR_DisableHSITFShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO); +} + +/** + * @brief Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 HSITFSO LL_PWR_IsEnabledHSITFShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_HSITFSO */ + +#if defined (PWR_CR1_SRDRAMSO) +/** + * @brief Enable the SRD AHB RAM shut-off in DStop/DStop2 mode + * @rmtoll CR1 SRDRAMSO LL_PWR_EnableSRDRAMShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); +} + +/** + * @brief Disable the SRD AHB RAM shut-off in DStop/DStop2 mode + * @rmtoll CR1 SRDRAMSO LL_PWR_DisableSRDRAMShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); +} + +/** + * @brief Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 SRDRAMSO LL_PWR_IsEnabledSRDRAMShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_SRDRAMSO */ + +/** + * @brief Enable Backup Regulator + * @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator + * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and + * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup + * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, + * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that + * the data written into the RAM will be maintained in the Standby and VBAT modes. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_BREN); +} + +/** + * @brief Disable Backup Regulator + * @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_BREN); +} + +/** + * @brief Check if the backup Regulator is enabled + * @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL); +} + +/** + * @brief Enable VBAT and Temperature monitoring + * @rmtoll CR2 MONEN LL_PWR_EnableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMonitoring(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Disable VBAT and Temperature monitoring + * @rmtoll CR2 MONEN LL_PWR_DisableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMonitoring(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Check if the VBAT and Temperature monitoring is enabled + * @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL); +} + +#if defined (SMPS) +/** + * @brief Configure the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply + * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply + * @rmtoll CR3 SMPSEN LL_PWR_ConfigSupply + * @rmtoll CR3 SMPSEXTHP LL_PWR_ConfigSupply + * @rmtoll CR3 SMPSLEVEL LL_PWR_ConfigSupply + * @param SupplySource This parameter can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) +{ + /* Set the power supply configuration */ + MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); +} +#else +/** + * @brief Configure the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply + * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply + * @rmtoll CR3 SCUEN LL_PWR_ConfigSupply + * @param SupplySource This parameter can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) +{ + /* Set the power supply configuration */ + MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); +} +#endif /* defined (SMPS) */ + +#if defined (SMPS) +/** + * @brief Get the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_GetSupply + * @rmtoll CR3 LDOEN LL_PWR_GetSupply + * @rmtoll CR3 SMPSEN LL_PWR_GetSupply + * @rmtoll CR3 SMPSEXTHP LL_PWR_GetSupply + * @rmtoll CR3 SMPSLEVEL LL_PWR_GetSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + */ +__STATIC_INLINE uint32_t LL_PWR_GetSupply(void) +{ + /* Get the power supply configuration */ + return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); +} +#else +/** + * @brief Get the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_GetSupply + * @rmtoll CR3 LDOEN LL_PWR_GetSupply + * @rmtoll CR3 SCUEN LL_PWR_GetSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + */ +__STATIC_INLINE uint32_t LL_PWR_GetSupply(void) +{ + /* Get the power supply configuration */ + return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); +} +#endif /* defined (SMPS) */ + +/** + * @brief Enable battery charging + * @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_VBE); +} + +/** + * @brief Disable battery charging + * @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_VBE); +} + +/** + * @brief Check if battery charging is enabled + * @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL); +} + +/** + * @brief Set the Battery charge resistor impedance + * @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor + * @param Resistor This parameter can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) +{ + MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor); +} + +/** + * @brief Get the Battery charge resistor impedance + * @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K + */ +__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) +{ + return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS)); +} + +/** + * @brief Enable the USB regulator + * @rmtoll CR3 USBREGEN LL_PWR_EnableUSBReg + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBReg(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_USBREGEN); +} + +/** + * @brief Disable the USB regulator + * @rmtoll CR3 USBREGEN LL_PWR_DisableUSBReg + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBReg(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN); +} + +/** + * @brief Check if the USB regulator is enabled + * @rmtoll CR3 USBREGEN LL_PWR_IsEnabledUSBReg + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the USB voltage detector + * @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Disable the USB voltage detector + * @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Check if the USB voltage detector is enabled + * @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL); +} + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Set the D1 domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_SetD1PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D1STOP + * @arg @ref LL_PWR_CPU_MODE_D1STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode); +} +#else +/** + * @brief Set the CPU domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_SetCDPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_CDSTOP + * @arg @ref LL_PWR_CPU_MODE_CDSTOP2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Set the D1 domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_SetD1PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D1STOP + * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Get the D1 Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_GetD1PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D1STOP + * @arg @ref LL_PWR_CPU_MODE_D1STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1)); +} +#else +/** + * @brief Get the CD Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_GetCDPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_CDSTOP + * @arg @ref LL_PWR_CPU_MODE_CDSTOP2 + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD)); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get the D1 Domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_GetD1PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D1STOP + * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1)); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Set the D2 domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_SetD2PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D2STOP + * @arg @ref LL_PWR_CPU_MODE_D2STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Set the D2 domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_SetD2PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D2STOP + * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Get the D2 Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_GetD2PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D2STOP + * @arg @ref LL_PWR_CPU_MODE_D2STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2)); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get the D2 Domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_GetD2PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D2STOP + * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2)); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Set the D3 domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_SetD3PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D3STOP + * @arg @ref LL_PWR_CPU_MODE_D3STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode); +} +#else +/** + * @brief Set the SRD domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_SetSRDPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_SRDSTOP + * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Set the D3 domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_SetD3PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D3STOP + * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D3STOP + * @arg @ref LL_PWR_CPU_MODE_D3STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3)); +} +#else +/** + * @brief Get the SRD Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_GetSRDPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_SRDSTOP + * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD)); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get the D3 Domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_GetD3PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D3STOP + * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3)); +} +#endif /* DUAL_CORE */ + +#if defined (DUAL_CORE) +/** + * @brief Hold the CPU1 and allocated peripherals when exiting from STOP mode + * @rmtoll CPU2CR HOLD1 LL_PWR_HoldCPU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_HoldCPU1(void) +{ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); +} + +/** + * @brief Release the CPU1 and allocated peripherals + * @rmtoll CPU2CR HOLD1 LL_PWR_ReleaseCPU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ReleaseCPU1(void) +{ + CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); +} + +/** + * @brief Ckeck if the CPU1 and allocated peripherals are held + * @rmtoll CPU2CR HOLD1 LL_PWR_IsCPU1Held + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1)) ? 1UL : 0UL); +} + +/** + * @brief Hold the CPU2 and allocated peripherals when exiting from STOP mode + * @rmtoll CPUCR HOLD2 LL_PWR_HoldCPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_HoldCPU2(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); +} + +/** + * @brief Release the CPU2 and allocated peripherals + * @rmtoll CPUCR HOLD2 LL_PWR_ReleaseCPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ReleaseCPU2(void) +{ + CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); +} + +/** + * @brief Ckeck if the CPU2 and allocated peripherals are held + * @rmtoll CPUCR HOLD2 LL_PWR_IsCPU2Held + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief D3 domain remains in Run mode regardless of CPU subsystem modes + * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_EnableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); +} +#else +/** + * @brief SRD domain remains in Run mode regardless of CPU subsystem modes + * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_EnableSRDRunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief D3 domain remains in Run mode regardless of CPU2 subsystem modes + * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_EnableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void) +{ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief D3 domain follows CPU subsystem modes + * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_DisableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void) +{ + CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); +} +#else +/** + * @brief SRD domain follows CPU subsystem modes + * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_DisableSRDRunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void) +{ + CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief D3 domain follows CPU2 subsystem modes + * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_DisableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void) +{ + CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Check if D3 is kept in Run mode when CPU enters low power mode + * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_IsEnabledD3RunInLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL); +} +#else +/** + * @brief Check if SRD is kept in Run mode when CPU enters low power mode + * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Check if D3 is kept in Run mode when CPU2 enters low power mode + * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Set the main internal Regulator output voltage + * @rmtoll D3CR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0 + * is applied when PWR_D3CR_VOS[1:0] = 0b11 and SYSCFG_PWRCR_ODEN = 0b1. + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ +#if defined (PWR_CPUCR_PDDS_D2) + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); +#else + MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); +#endif /* PWR_CPUCR_PDDS_D2 */ +} + +/** + * @brief Get the main internal Regulator output voltage + * @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling + * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking + * VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit. + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ +#if defined (PWR_CPUCR_PDDS_D2) + return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS)); +#else + return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS)); +#endif /* PWR_CPUCR_PDDS_D2 */ +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); +} + +/** + * @brief Get the Wake-Up pin polarity for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin Pull None + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Up + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Down + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Get the Wake-Up pin pull + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL + * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP + * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin) +{ + uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); + + return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the voltage level is ready for current actual used VOS + * @rmtoll CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether VDDA voltage is below the selected AVD threshold + * @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL); +} + +#if defined (PWR_CSR1_MMCVDO) +/** + * @brief Indicate whether VDDMMC voltage is below 1V2 + * @rmtoll CSR1 MMCVDO LL_PWR_IsActiveFlag_MMCVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL); +} +#endif /* PWR_CSR1_MMCVDO */ + +/** + * @brief Get Backup Regulator ready Flag + * @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is above or below low threshold + * @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is above or below high threshold + * @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above or below low threshold + * @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above or below high threshold + * @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL); +} + +#if defined (SMPS) +/** + * @brief Indicate whether the SMPS external supply is ready or not + * @rmtoll CR3 SMPSEXTRDY LL_PWR_IsActiveFlag_SMPSEXT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL); +} +#endif /* SMPS */ + +/** + * @brief Indicate whether the USB supply is ready or not + * @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Get HOLD2 Flag + * @rmtoll CPUCR HOLD2F LL_PWR_IsActiveFlag_HOLD2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL); +} + +/** + * @brief Get HOLD1 Flag + * @rmtoll CPU2CR HOLD1F LL_PWR_IsActiveFlag_HOLD1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Get CPU System Stop Flag + * @rmtoll CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 System Stop Flag + * @rmtoll CPU2CR STOPF LL_PWR_CPU2_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Get CPU System Standby Flag + * @rmtoll CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 System Standby Flag + * @rmtoll CPU2CR SBF LL_PWR_CPU2_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_SBF_D1) +/** + * @brief Get CPU D1 Domain Standby Flag + * @rmtoll CPUCR SBF_D1 LL_PWR_CPU_IsActiveFlag_SB_D1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL); +} +#endif /* PWR_CPUCR_SBF_D1 */ + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 D1 Domain Standby Flag + * @rmtoll CPU2CR SBF_D1 LL_PWR_CPU2_IsActiveFlag_SB_D1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_SBF_D2) +/** + * @brief Get CPU D2 Domain Standby Flag + * @rmtoll CPUCR SBF_D2 LL_PWR_CPU_IsActiveFlag_SB_D2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL); +} +#endif /* PWR_CPUCR_SBF_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 D2 Domain Standby Flag + * @rmtoll CPU2CR SBF_D2 LL_PWR_CPU2_IsActiveFlag_SB_D2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + + +/** + * @brief Indicate whether the Regulator is ready in the selected voltage range + * or if its output voltage is still changing to the required voltage level + * @rmtoll D3CR VOSRDY LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ +#if defined (PWR_CPUCR_PDDS_D2) + return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL); +#else + return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL); +#endif /* PWR_CPUCR_PDDS_D2 */ +} + +/** + * @brief Get Wake-up Flag 6 + * @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL); +} + +#if defined (PWR_WKUPFR_WKUPF5) +/** + * @brief Get Wake-up Flag 5 + * @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL); +} +#endif /* defined (PWR_WKUPFR_WKUPF5) */ + +/** + * @brief Get Wake-up Flag 4 + * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL); +} + +#if defined (PWR_WKUPFR_WKUPF3) +/** + * @brief Get Wake-up Flag 3 + * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL); +} +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + +/** + * @brief Get Wake-up Flag 2 + * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 1 + * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL); +} + +/** + * @brief Clear CPU STANDBY, STOP and HOLD flags + * @rmtoll CPUCR CSSF LL_PWR_ClearFlag_CPU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); +} + +#if defined (DUAL_CORE) +/** + * @brief Clear CPU2 STANDBY, STOP and HOLD flags + * @rmtoll CPU2CR CSSF LL_PWR_ClearFlag_CPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void) +{ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); +} +#endif /* DUAL_CORE */ + +/** + * @brief Clear Wake-up Flag 6 + * @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6); +} + +#if defined (PWR_WKUPCR_WKUPC5) +/** + * @brief Clear Wake-up Flag 5 + * @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5); +} +#endif /* defined (PWR_WKUPCR_WKUPC5) */ + +/** + * @brief Clear Wake-up Flag 4 + * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); +} + +#if defined (PWR_WKUPCR_WKUPC3) +/** + * @brief Clear Wake-up Flag 3 + * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); +} +#endif /* defined (PWR_WKUPCR_WKUPC3) */ + +/** + * @brief Clear Wake-up Flag 2 + * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); +} + +/** + * @brief Clear Wake-up Flag 1 + * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); +} + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* defined (USE_FULL_LL_DRIVER) */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_PWR_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h new file mode 100644 index 0000000..bd700dc --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h @@ -0,0 +1,6404 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_RCC_H +#define STM32H7xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ +extern const uint8_t LL_RCC_PrescTable[16]; + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif + +/* 32 24 16 8 0 + -------------------------------------------------------- + | Mask | ClkSource | Bit | Register | + | | Config | Position | Offset | + --------------------------------------------------------*/ + +#if defined(RCC_VER_2_0) +/* Clock source register offset Vs CDCCIPR register */ +#define CDCCIP 0x0UL +#define CDCCIP1 0x4UL +#define CDCCIP2 0x8UL +#define SRDCCIP 0xCUL +#else +/* Clock source register offset Vs D1CCIPR register */ +#define D1CCIP 0x0UL +#define D2CCIP1 0x4UL +#define D2CCIP2 0x8UL +#define D3CCIP 0xCUL +#endif /* RCC_VER_2_0 */ + +#define LL_RCC_REG_SHIFT 0U +#define LL_RCC_POS_SHIFT 8U +#define LL_RCC_CONFIG_SHIFT 16U +#define LL_RCC_MASK_SHIFT 24U + +#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL) + +#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL) + +#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \ + (( __POS__ ) << LL_RCC_POS_SHIFT) | \ + (( __REG__ ) << LL_RCC_REG_SHIFT) | \ + (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT))) +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t CPUCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK1_Frequency; + uint32_t PCLK2_Frequency; + uint32_t PCLK3_Frequency; + uint32_t PCLK4_Frequency; +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @brief PLL Clocks Frequency Structure + */ +typedef struct +{ + uint32_t PLL_P_Frequency; + uint32_t PLL_Q_Frequency; + uint32_t PLL_R_Frequency; +} LL_PLL_ClocksTypeDef; + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#if defined(RCC_VER_X) || defined(RCC_VER_3_0) +#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ +#else +#define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* RCC_VER_X || RCC_VER_3_0 */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */ +#endif /* CSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider + * @{ + */ +#define LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1 +#define LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2 +#define LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4 +#define LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U) +#define LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0) +#define LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1) +#define LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI +#define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE +#define LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source + * @{ + */ +#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U) +#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup clock source + * @{ + */ +#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U) +#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV System prescaler + * @{ + */ +#if defined(RCC_D1CFGR_D1CPRE_DIV1) +#define LL_RCC_SYSCLK_DIV_1 RCC_D1CFGR_D1CPRE_DIV1 +#define LL_RCC_SYSCLK_DIV_2 RCC_D1CFGR_D1CPRE_DIV2 +#define LL_RCC_SYSCLK_DIV_4 RCC_D1CFGR_D1CPRE_DIV4 +#define LL_RCC_SYSCLK_DIV_8 RCC_D1CFGR_D1CPRE_DIV8 +#define LL_RCC_SYSCLK_DIV_16 RCC_D1CFGR_D1CPRE_DIV16 +#define LL_RCC_SYSCLK_DIV_64 RCC_D1CFGR_D1CPRE_DIV64 +#define LL_RCC_SYSCLK_DIV_128 RCC_D1CFGR_D1CPRE_DIV128 +#define LL_RCC_SYSCLK_DIV_256 RCC_D1CFGR_D1CPRE_DIV256 +#define LL_RCC_SYSCLK_DIV_512 RCC_D1CFGR_D1CPRE_DIV512 +#else +#define LL_RCC_SYSCLK_DIV_1 RCC_CDCFGR1_CDCPRE_DIV1 +#define LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR1_CDCPRE_DIV2 +#define LL_RCC_SYSCLK_DIV_4 RCC_CDCFGR1_CDCPRE_DIV4 +#define LL_RCC_SYSCLK_DIV_8 RCC_CDCFGR1_CDCPRE_DIV8 +#define LL_RCC_SYSCLK_DIV_16 RCC_CDCFGR1_CDCPRE_DIV16 +#define LL_RCC_SYSCLK_DIV_64 RCC_CDCFGR1_CDCPRE_DIV64 +#define LL_RCC_SYSCLK_DIV_128 RCC_CDCFGR1_CDCPRE_DIV128 +#define LL_RCC_SYSCLK_DIV_256 RCC_CDCFGR1_CDCPRE_DIV256 +#define LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR1_CDCPRE_DIV512 +#endif /* RCC_D1CFGR_D1CPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler + * @{ + */ +#if defined(RCC_D1CFGR_HPRE_DIV1) +#define LL_RCC_AHB_DIV_1 RCC_D1CFGR_HPRE_DIV1 +#define LL_RCC_AHB_DIV_2 RCC_D1CFGR_HPRE_DIV2 +#define LL_RCC_AHB_DIV_4 RCC_D1CFGR_HPRE_DIV4 +#define LL_RCC_AHB_DIV_8 RCC_D1CFGR_HPRE_DIV8 +#define LL_RCC_AHB_DIV_16 RCC_D1CFGR_HPRE_DIV16 +#define LL_RCC_AHB_DIV_64 RCC_D1CFGR_HPRE_DIV64 +#define LL_RCC_AHB_DIV_128 RCC_D1CFGR_HPRE_DIV128 +#define LL_RCC_AHB_DIV_256 RCC_D1CFGR_HPRE_DIV256 +#define LL_RCC_AHB_DIV_512 RCC_D1CFGR_HPRE_DIV512 +#else +#define LL_RCC_AHB_DIV_1 RCC_CDCFGR1_HPRE_DIV1 +#define LL_RCC_AHB_DIV_2 RCC_CDCFGR1_HPRE_DIV2 +#define LL_RCC_AHB_DIV_4 RCC_CDCFGR1_HPRE_DIV4 +#define LL_RCC_AHB_DIV_8 RCC_CDCFGR1_HPRE_DIV8 +#define LL_RCC_AHB_DIV_16 RCC_CDCFGR1_HPRE_DIV16 +#define LL_RCC_AHB_DIV_64 RCC_CDCFGR1_HPRE_DIV64 +#define LL_RCC_AHB_DIV_128 RCC_CDCFGR1_HPRE_DIV128 +#define LL_RCC_AHB_DIV_256 RCC_CDCFGR1_HPRE_DIV256 +#define LL_RCC_AHB_DIV_512 RCC_CDCFGR1_HPRE_DIV512 +#endif /* RCC_D1CFGR_HPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#if defined(RCC_D2CFGR_D2PPRE1_DIV1) +#define LL_RCC_APB1_DIV_1 RCC_D2CFGR_D2PPRE1_DIV1 +#define LL_RCC_APB1_DIV_2 RCC_D2CFGR_D2PPRE1_DIV2 +#define LL_RCC_APB1_DIV_4 RCC_D2CFGR_D2PPRE1_DIV4 +#define LL_RCC_APB1_DIV_8 RCC_D2CFGR_D2PPRE1_DIV8 +#define LL_RCC_APB1_DIV_16 RCC_D2CFGR_D2PPRE1_DIV16 +#else +#define LL_RCC_APB1_DIV_1 RCC_CDCFGR2_CDPPRE1_DIV1 +#define LL_RCC_APB1_DIV_2 RCC_CDCFGR2_CDPPRE1_DIV2 +#define LL_RCC_APB1_DIV_4 RCC_CDCFGR2_CDPPRE1_DIV4 +#define LL_RCC_APB1_DIV_8 RCC_CDCFGR2_CDPPRE1_DIV8 +#define LL_RCC_APB1_DIV_16 RCC_CDCFGR2_CDPPRE1_DIV16 +#endif /* RCC_D2CFGR_D2PPRE1_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB low-speed prescaler (APB2) + * @{ + */ +#if defined(RCC_D2CFGR_D2PPRE2_DIV1) +#define LL_RCC_APB2_DIV_1 RCC_D2CFGR_D2PPRE2_DIV1 +#define LL_RCC_APB2_DIV_2 RCC_D2CFGR_D2PPRE2_DIV2 +#define LL_RCC_APB2_DIV_4 RCC_D2CFGR_D2PPRE2_DIV4 +#define LL_RCC_APB2_DIV_8 RCC_D2CFGR_D2PPRE2_DIV8 +#define LL_RCC_APB2_DIV_16 RCC_D2CFGR_D2PPRE2_DIV16 +#else +#define LL_RCC_APB2_DIV_1 RCC_CDCFGR2_CDPPRE2_DIV1 +#define LL_RCC_APB2_DIV_2 RCC_CDCFGR2_CDPPRE2_DIV2 +#define LL_RCC_APB2_DIV_4 RCC_CDCFGR2_CDPPRE2_DIV4 +#define LL_RCC_APB2_DIV_8 RCC_CDCFGR2_CDPPRE2_DIV8 +#define LL_RCC_APB2_DIV_16 RCC_CDCFGR2_CDPPRE2_DIV16 +#endif /* RCC_D2CFGR_D2PPRE2_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB3_DIV APB low-speed prescaler (APB3) + * @{ + */ +#if defined(RCC_D1CFGR_D1PPRE_DIV1) +#define LL_RCC_APB3_DIV_1 RCC_D1CFGR_D1PPRE_DIV1 +#define LL_RCC_APB3_DIV_2 RCC_D1CFGR_D1PPRE_DIV2 +#define LL_RCC_APB3_DIV_4 RCC_D1CFGR_D1PPRE_DIV4 +#define LL_RCC_APB3_DIV_8 RCC_D1CFGR_D1PPRE_DIV8 +#define LL_RCC_APB3_DIV_16 RCC_D1CFGR_D1PPRE_DIV16 +#else +#define LL_RCC_APB3_DIV_1 RCC_CDCFGR1_CDPPRE_DIV1 +#define LL_RCC_APB3_DIV_2 RCC_CDCFGR1_CDPPRE_DIV2 +#define LL_RCC_APB3_DIV_4 RCC_CDCFGR1_CDPPRE_DIV4 +#define LL_RCC_APB3_DIV_8 RCC_CDCFGR1_CDPPRE_DIV8 +#define LL_RCC_APB3_DIV_16 RCC_CDCFGR1_CDPPRE_DIV16 +#endif /* RCC_D1CFGR_D1PPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB4_DIV APB low-speed prescaler (APB4) + * @{ + */ +#if defined(RCC_D3CFGR_D3PPRE_DIV1) +#define LL_RCC_APB4_DIV_1 RCC_D3CFGR_D3PPRE_DIV1 +#define LL_RCC_APB4_DIV_2 RCC_D3CFGR_D3PPRE_DIV2 +#define LL_RCC_APB4_DIV_4 RCC_D3CFGR_D3PPRE_DIV4 +#define LL_RCC_APB4_DIV_8 RCC_D3CFGR_D3PPRE_DIV8 +#define LL_RCC_APB4_DIV_16 RCC_D3CFGR_D3PPRE_DIV16 +#else +#define LL_RCC_APB4_DIV_1 RCC_SRDCFGR_SRDPPRE_DIV1 +#define LL_RCC_APB4_DIV_2 RCC_SRDCFGR_SRDPPRE_DIV2 +#define LL_RCC_APB4_DIV_4 RCC_SRDCFGR_SRDPPRE_DIV4 +#define LL_RCC_APB4_DIV_8 RCC_SRDCFGR_SRDPPRE_DIV8 +#define LL_RCC_APB4_DIV_16 RCC_SRDCFGR_SRDPPRE_DIV16 +#endif /* RCC_D3CFGR_D3PPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U) +#define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0) +#define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1) +#define LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) +#define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2) +#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U) +#define LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0) +#define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1) +#define LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) +#define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2) +#define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE) +#define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE) + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock + * @{ + */ +#define LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U) +#define LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4) +#define LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5) +#define LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4) +#define LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_USART16SEL) +#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U) +#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0) +#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1) +#define LL_RCC_USART16_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) +#define LL_RCC_USART16_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2) +#define LL_RCC_USART16_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) +/* Aliases */ +#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_RCC_USART16_CLKSOURCE_PCLK2 +#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_RCC_USART16_CLKSOURCE_PLL2Q +#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_RCC_USART16_CLKSOURCE_PLL3Q +#define LL_RCC_USART16910_CLKSOURCE_HSI LL_RCC_USART16_CLKSOURCE_HSI +#define LL_RCC_USART16910_CLKSOURCE_CSI LL_RCC_USART16_CLKSOURCE_CSI +#define LL_RCC_USART16910_CLKSOURCE_LSE LL_RCC_USART16_CLKSOURCE_LSE + +#elif defined(RCC_D2CCIP2R_USART16910SEL) +#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U) +#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0) +#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2) +#define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2) +/* Aliases */ +#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2 +#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q +#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q +#define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI +#define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI +#define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE + +#else +#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U) +#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0) +#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2) +#define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2) +/* Aliases */ +#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2 +#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q +#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q +#define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI +#define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI +#define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE +#endif /* RCC_D2CCIP2R_USART16SEL */ +#if defined(RCC_D2CCIP2R_USART28SEL) +#define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U) +#define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0) +#define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2) +#define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) +#else +#define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U) +#define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0) +#define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2) +#define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2) +#endif /* RCC_D2CCIP2R_USART28SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection + * @{ + */ +#if defined(RCC_D3CCIPR_LPUART1SEL) +#define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U) +#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_D3CCIPR_LPUART1SEL_0) +#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_D3CCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_D3CCIPR_LPUART1SEL_2) +#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2) +#else +#define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U) +#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_SRDCCIPR_LPUART1SEL_0) +#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_SRDCCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_SRDCCIPR_LPUART1SEL_2) +#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2) +#endif /* RCC_D3CCIPR_LPUART1SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#if defined (RCC_D2CCIP2R_I2C123SEL) +#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U) +#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0) +#define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1) +#define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1) +/* Aliases */ +#define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_RCC_I2C123_CLKSOURCE_PCLK1 +#define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_RCC_I2C123_CLKSOURCE_PLL3R +#define LL_RCC_I2C1235_CLKSOURCE_HSI LL_RCC_I2C123_CLKSOURCE_HSI +#define LL_RCC_I2C1235_CLKSOURCE_CSI LL_RCC_I2C123_CLKSOURCE_CSI + +#elif defined (RCC_D2CCIP2R_I2C1235SEL) +#define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U) +#define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0) +#define LL_RCC_I2C1235_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1) +#define LL_RCC_I2C1235_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1) +/* Aliases */ +#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_RCC_I2C1235_CLKSOURCE_PCLK1 +#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_RCC_I2C1235_CLKSOURCE_PLL3R +#define LL_RCC_I2C123_CLKSOURCE_HSI LL_RCC_I2C1235_CLKSOURCE_HSI +#define LL_RCC_I2C123_CLKSOURCE_CSI LL_RCC_I2C1235_CLKSOURCE_CSI + +#else +#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U) +#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0) +#define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1) +#define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1) +#endif /* RCC_D2CCIP2R_I2C123SEL */ +#if defined (RCC_D3CCIPR_I2C4SEL) +#define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U) +#define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0) +#define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_1) +#define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) +#else +#define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U) +#define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0) +#define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_1) +#define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1) +#endif /* RCC_D3CCIPR_I2C4SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_2) +#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) +#else +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_2) +#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_2) +#define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) +#else +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_2) +#define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2) +#define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) +#else +#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2) +#define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2) +/* aliases*/ +#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_RCC_LPTIM345_CLKSOURCE_PCLK4 +#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_RCC_LPTIM345_CLKSOURCE_PLL2P +#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_RCC_LPTIM345_CLKSOURCE_PLL3R +#define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_RCC_LPTIM345_CLKSOURCE_LSE +#define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_RCC_LPTIM345_CLKSOURCE_LSI +#define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_RCC_LPTIM345_CLKSOURCE_CLKP +#endif /* RCC_D3CCIPR_LPTIM345SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U) +#define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0) +#define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_2) +#else +#define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U) +#define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0) +#define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_2) +#endif +#if defined(SAI3) +#define LL_RCC_SAI23_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U) +#define LL_RCC_SAI23_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0) +#define LL_RCC_SAI23_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1) +#define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1) +#define LL_RCC_SAI23_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2) +#endif /* SAI3 */ +#if defined(RCC_CDCCIP1R_SAI2ASEL) +#define LL_RCC_SAI2A_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U) +#define LL_RCC_SAI2A_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0) +#define LL_RCC_SAI2A_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_1) +#define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1) +#define LL_RCC_SAI2A_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_2) +#define LL_RCC_SAI2A_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2) +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) +#define LL_RCC_SAI2B_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U) +#define LL_RCC_SAI2B_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0) +#define LL_RCC_SAI2B_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_1) +#define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1) +#define LL_RCC_SAI2B_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_2) +#define LL_RCC_SAI2B_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2) +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(SAI4_Block_A) +#define LL_RCC_SAI4A_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U) +#define LL_RCC_SAI4A_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0) +#define LL_RCC_SAI4A_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_1) +#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) +#define LL_RCC_SAI4A_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2) +#if defined(RCC_VER_3_0) +#define LL_RCC_SAI4A_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0) +#endif /* RCC_VER_3_0 */ +#endif /* SAI4_Block_A */ +#if defined(SAI4_Block_B) +#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U) +#define LL_RCC_SAI4B_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0) +#define LL_RCC_SAI4B_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_1) +#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) +#define LL_RCC_SAI4B_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2) +#if defined(RCC_VER_3_0) +#define LL_RCC_SAI4B_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0) +#endif /* RCC_VER_3_0 */ +#endif /* SAI4_Block_B */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_SDMMCSEL) +#else +#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_SDMMCSEL) +#endif /* RCC_D1CCIPR_SDMMCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_RNGSEL) +#define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U) +#define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_RNGSEL_0) +#define LL_RCC_RNG_CLKSOURCE_LSE (RCC_D2CCIP2R_RNGSEL_1) +#define LL_RCC_RNG_CLKSOURCE_LSI (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0) +#else +#define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U) +#define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_RNGSEL_0) +#define LL_RCC_RNG_CLKSOURCE_LSE (RCC_CDCCIP2R_RNGSEL_1) +#define LL_RCC_RNG_CLKSOURCE_LSI (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0) +#endif /* RCC_D2CCIP2R_RNGSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_USBSEL) +#define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U) +#define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_USBSEL_0) +#define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_D2CCIP2R_USBSEL_1) +#define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0) +#else +#define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U) +#define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_USBSEL_0) +#define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_CDCCIP2R_USBSEL_1) +#define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0) +#endif /* RCC_D2CCIP2R_USBSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_CECSEL) +#define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U) +#define LL_RCC_CEC_CLKSOURCE_LSI (RCC_D2CCIP2R_CECSEL_0) +#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_D2CCIP2R_CECSEL_1) +#else +#define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U) +#define LL_RCC_CEC_CLKSOURCE_LSI (RCC_CDCCIP2R_CECSEL_0) +#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_CDCCIP2R_CECSEL_1) +#endif +/** + * @} + */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY (0x00000000U) +#define LL_RCC_DSI_CLKSOURCE_PLL2Q (RCC_D1CCIPR_DSISEL) +/** + * @} + */ +#endif /* DSI */ + +/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U) +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_D2CCIP1R_DFSDM1SEL) +#else +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U) +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_CDCCIP1R_DFSDM1SEL) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +/** + * @} + */ + +#if defined(DFSDM2_BASE) +/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE Peripheral DFSDM2 clock source selection + * @{ + */ +#define LL_RCC_DFSDM2_CLKSOURCE_PCLK4 (0x00000000U) +#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (RCC_SRDCCIPR_DFSDM2SEL) +/** + * @} + */ +#endif /* DFSDM2_BASE */ + +/** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_D1CCIPR_FMCSEL_0) +#define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_FMCSEL_1) +#define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1) +#else +#define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_CDCCIPR_FMCSEL_0) +#define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_FMCSEL_1) +#define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1) +#endif /* RCC_D1CCIPR_FMCSEL */ +/** + * @} + */ + +#if defined(QUADSPI) +/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI clock source selection + * @{ + */ +#define LL_RCC_QSPI_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_QSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_QSPISEL_0) +#define LL_RCC_QSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_QSPISEL_1) +#define LL_RCC_QSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1) +/** + * @} + */ +#endif /* QUADSPI */ + + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE Peripheral OSPI clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_OCTOSPISEL) +#define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_OCTOSPISEL_0) +#define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_OCTOSPISEL_1) +#define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1) +#else +#define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0) +#define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1) +#define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1) +#endif /* RCC_D1CCIPR_OCTOSPISEL */ +/** + * @} + */ +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + + +/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U) +#define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_D1CCIPR_CKPERSEL_0) +#define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_D1CCIPR_CKPERSEL_1) +#else +#define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U) +#define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_CDCCIPR_CKPERSEL_0) +#define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_CDCCIPR_CKPERSEL_1) +#endif /* RCC_D1CCIPR_CKPERSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U) +#define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0) +#define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2) +#else +#define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U) +#define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0) +#define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2) +#endif /* RCC_D2CCIP1R_SPI123SEL */ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U) +#define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0) +#define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_2) +#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) +#else +#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U) +#define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0) +#define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_2) +#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2) +#endif /* (RCC_D2CCIP1R_SPI45SEL */ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U) +#define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) +#else +#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U) +#define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2) +#endif /* RCC_D3CCIPR_SPI6SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_D2CCIP1R_SPDIFSEL_0) +#define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_D2CCIP1R_SPDIFSEL_1) +#define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1) +#else +#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_CDCCIP1R_SPDIFSEL_0) +#define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_CDCCIP1R_SPDIFSEL_1) +#define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +/** + * @} + */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U) +#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_D2CCIP1R_FDCANSEL_0) +#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_D2CCIP1R_FDCANSEL_1) +#else +#define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U) +#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_CDCCIP1R_FDCANSEL_0) +#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_CDCCIP1R_FDCANSEL_1) +#endif /* RCC_D2CCIP1R_FDCANSEL */ +/** + * @} + */ +#endif /*FDCAN1 || FDCAN2*/ + +/** @defgroup RCC_LL_EC_SWP_CLKSOURCE Peripheral SWP clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U) +#define LL_RCC_SWP_CLKSOURCE_HSI (RCC_D2CCIP1R_SWPSEL) +#else +#define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U) +#define LL_RCC_SWP_CLKSOURCE_HSI (RCC_CDCCIP1R_SWPSEL) +#endif /* RCC_D2CCIP1R_SWPSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U) +#define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_D3CCIPR_ADCSEL_0) +#define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_D3CCIPR_ADCSEL_1) +#else +#define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U) +#define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_SRDCCIPR_ADCSEL_0) +#define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_SRDCCIPR_ADCSEL_1) +#endif /* RCC_D3CCIPR_ADCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source + * @{ + */ +#if defined (RCC_D2CCIP2R_USART16SEL) +#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U) +#elif defined (RCC_D2CCIP2R_USART16910SEL) +#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U) +/* alias*/ +#define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE +#else +#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U) +/* alias*/ +#define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ +#if defined (RCC_D2CCIP2R_USART28SEL) +#define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U) +#else +#define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP2R_USART28SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUARTx Peripheral LPUART get clock source + * @{ + */ +#if defined(RCC_D3CCIPR_LPUART1SEL) +#define LL_RCC_LPUART1_CLKSOURCE RCC_D3CCIPR_LPUART1SEL +#else +#define LL_RCC_LPUART1_CLKSOURCE RCC_SRDCCIPR_LPUART1SEL +#endif /* RCC_D3CCIPR_LPUART1SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source + * @{ + */ +#if defined(RCC_D2CCIP2R_I2C123SEL) +#define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U) +/* alias */ +#define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE +#elif defined(RCC_D2CCIP2R_I2C1235SEL) +#define LL_RCC_I2C1235_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U) +/* alias */ +#define LL_RCC_I2C123_CLKSOURCE LL_RCC_I2C1235_CLKSOURCE +#else +#define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U) +/* alias */ +#define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE +#endif /* RCC_D2CCIP2R_I2C123SEL */ +#if defined(RCC_D3CCIPR_I2C4SEL) +#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U) +#else +#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_I2C4SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIMx Peripheral LPTIM get clock source + * @{ + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#else +#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP2R_LPTIM1SEL) */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U) +#else +#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U) +#else +#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */ +#endif /* RCC_D3CCIPR_LPTIM345SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SAI1SEL */ +#if defined(RCC_D2CCIP1R_SAI23SEL) +#define LL_RCC_SAI23_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SAI23SEL */ +#if defined(RCC_CDCCIP1R_SAI2ASEL) +#define LL_RCC_SAI2A_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U) +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) +#define LL_RCC_SAI2B_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U) +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(RCC_D3CCIPR_SAI4ASEL) +#define LL_RCC_SAI4A_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_SAI4ASEL */ +#if defined(RCC_D3CCIPR_SAI4BSEL) +#define LL_RCC_SAI4B_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_SAI4BSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source + * @{ + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define LL_RCC_SDMMC_CLKSOURCE RCC_D1CCIPR_SDMMCSEL +#else +#define LL_RCC_SDMMC_CLKSOURCE RCC_CDCCIPR_SDMMCSEL +#endif /* RCC_D1CCIPR_SDMMCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#if (RCC_D2CCIP2R_RNGSEL) +#define LL_RCC_RNG_CLKSOURCE RCC_D2CCIP2R_RNGSEL +#else +#define LL_RCC_RNG_CLKSOURCE RCC_CDCCIP2R_RNGSEL +#endif /* RCC_D2CCIP2R_RNGSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#if (RCC_D2CCIP2R_USBSEL) +#define LL_RCC_USB_CLKSOURCE RCC_D2CCIP2R_USBSEL +#else +#define LL_RCC_USB_CLKSOURCE RCC_CDCCIP2R_USBSEL +#endif /* RCC_D2CCIP2R_USBSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#if (RCC_D2CCIP2R_CECSEL) +#define LL_RCC_CEC_CLKSOURCE RCC_D2CCIP2R_CECSEL +#else +#define LL_RCC_CEC_CLKSOURCE RCC_CDCCIP2R_CECSEL +#endif /* RCC_D2CCIP2R_CECSEL */ +/** + * @} + */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_D1CCIPR_DSISEL +/** + * @} + */ +#endif /* DSI */ + +/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE RCC_D2CCIP1R_DFSDM1SEL +#else +#define LL_RCC_DFSDM1_CLKSOURCE RCC_CDCCIP1R_DFSDM1SEL +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +/** + * @} + */ + +#if defined(DFSDM2_BASE) +/** @defgroup RCC_LL_EC_DFSDM2 Peripheral DFSDM2 get clock source + * @{ + */ +#define LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL +/** + * @} + */ +#endif /* DFSDM2_BASE */ + + + +/** @defgroup RCC_LL_EC_FMC Peripheral FMC get clock source + * @{ + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define LL_RCC_FMC_CLKSOURCE RCC_D1CCIPR_FMCSEL +#else +#define LL_RCC_FMC_CLKSOURCE RCC_CDCCIPR_FMCSEL +#endif +/** + * @} + */ + +#if defined(QUADSPI) +/** @defgroup RCC_LL_EC_QSPI Peripheral QSPI get clock source + * @{ + */ +#define LL_RCC_QSPI_CLKSOURCE RCC_D1CCIPR_QSPISEL +/** + * @} + */ +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @defgroup RCC_LL_EC_OSPI Peripheral OSPI get clock source + * @{ + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL +#else +#define LL_RCC_OSPI_CLKSOURCE RCC_D1CCIPR_OCTOSPISEL +#endif /* RCC_CDCCIPR_OCTOSPISEL */ +/** + * @} + */ +#endif /* OCTOSPI1 || OCTOSPI2 */ + +/** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source + * @{ + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define LL_RCC_CLKP_CLKSOURCE RCC_D1CCIPR_CKPERSEL +#else +#define LL_RCC_CLKP_CLKSOURCE RCC_CDCCIPR_CKPERSEL +#endif /* RCC_D1CCIPR_CKPERSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPIx Peripheral SPI get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SPI123SEL */ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SPI45SEL */ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_SPI6SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPDIF Peripheral SPDIF get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define LL_RCC_SPDIF_CLKSOURCE RCC_D2CCIP1R_SPDIFSEL +#else +#define LL_RCC_SPDIF_CLKSOURCE RCC_CDCCIP1R_SPDIFSEL +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +/** + * @} + */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define LL_RCC_FDCAN_CLKSOURCE RCC_D2CCIP1R_FDCANSEL +#else +#define LL_RCC_FDCAN_CLKSOURCE RCC_CDCCIP1R_FDCANSEL +#endif +/** + * @} + */ +#endif /*FDCAN1 || FDCAN2*/ + +/** @defgroup RCC_LL_EC_SWP Peripheral SWP get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define LL_RCC_SWP_CLKSOURCE RCC_D2CCIP1R_SWPSEL +#else +#define LL_RCC_SWP_CLKSOURCE RCC_CDCCIP1R_SWPSEL +#endif /* RCC_D2CCIP1R_SWPSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define LL_RCC_ADC_CLKSOURCE RCC_D3CCIPR_ADCSEL +#else +#define LL_RCC_ADC_CLKSOURCE RCC_SRDCCIPR_ADCSEL +#endif /* RCC_D3CCIPR_ADCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U) +#define LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0) +#define LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1) +#define LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + * @{ + */ +#define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U) +#define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE) +/** + * @} + */ + +#if defined(HRTIM1) +/** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE High Resolution Timers clock selection + * @{ + */ +#define LL_RCC_HRTIM_CLKSOURCE_TIM (uint32_t)(0x00000000U) /* HRTIM Clock source is same as other timers */ +#define LL_RCC_HRTIM_CLKSOURCE_CPU (uint32_t)(RCC_CFGR_HRTIMSEL) /* HRTIM Clock source is the CPU clock */ +/** + * @} + */ +#endif /* HRTIM1 */ + +/** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI +#define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE +#define LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input range + * @{ + */ +#define LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U) +#define LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001) +#define LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002) +#define LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLVCORANGE All PLLs VCO range + * @{ + */ +#define LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */ +#define LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */ +/** + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the SYSCLK frequency + * @param __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P) + * @param __SYSPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval SYSCLK clock frequency (in Hz) + */ +#if defined(RCC_D1CFGR_D1CPRE) +#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU)) +#endif /* RCC_D1CFGR_D1CPRE */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency. + * @param __HPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#if defined(RCC_D1CFGR_HPRE) +#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)) +#endif /* RCC_D1CFGR_HPRE */ + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#if defined(RCC_D2CFGR_D2PPRE1) +#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)) +#endif /* RCC_D2CFGR_D2PPRE1 */ + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#if defined(RCC_D2CFGR_D2PPRE2) +#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)) +#endif /* RCC_D2CFGR_D2PPRE2 */ + +/** + * @brief Helper macro to calculate the PCLK3 frequency (APB3) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB3PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#if defined(RCC_D1CFGR_D1PPRE) +#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU)) +#endif /* RCC_D1CFGR_D1PPRE */ + +/** + * @brief Helper macro to calculate the PCLK4 frequency (ABP4) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB4PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#if defined(RCC_D3CFGR_D3PPRE) +#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU)) +#endif /* RCC_D3CFGR_D3PPRE */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless + * a reset occurs or system enter in standby mode. + * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSHSEON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +#if defined(RCC_CR_HSEEXT) +/** + * @brief Select the Analog HSE external clock type in Bypass mode + * @rmtoll CR HSEEXT LL_RCC_HSE_SelectAnalogClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); +} + +/** + * @brief Select the Digital HSE external clock type in Bypass mode + * @rmtoll CR HSEEXT LL_RCC_HSE_SelectDigitalClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); +} +#endif /* RCC_CR_HSEEXT */ + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI new divider applied and ready + * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV1 + * @arg @ref LL_RCC_HSI_DIV2 + * @arg @ref LL_RCC_HSI_DIV4 + * @arg @ref LL_RCC_HSI_DIV8 + * @retval None. + */ +__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider); +} + +/** + * @brief Get HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider + * @retval can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV1 + * @arg @ref LL_RCC_HSI_DIV2 + * @arg @ref LL_RCC_HSI_DIV4 + * @arg @ref LL_RCC_HSI_DIV8 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIDIV)); +} + +/** + * @brief Enable HSI oscillator in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI oscillator in Stop mode + * @rmtoll CR HSION LL_RCC_HSI_DisableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration + * @retval A value between 0 and 4095 (0xFFF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value, + * should trim the HSI to 64 MHz +/- 1 % + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value can be a value between 0 and 127 (63 for Cut1.x) + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U); + } + else + { + /* STM32H7 Rev.V */ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); + } +#else + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval A value between 0 and 127 (63 for Cut1.x) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U); + } + else + { + /* STM32H7 Rev.V */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + } +#else + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_CSI CSI + * @{ + */ + +/** + * @brief Enable CSI oscillator + * @rmtoll CR CSION LL_RCC_CSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSION); +} + +/** + * @brief Disable CSI oscillator + * @rmtoll CR CSION LL_RCC_CSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSION); +} + +/** + * @brief Check if CSI clock is ready + * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable CSI oscillator in Stop mode + * @rmtoll CR CSIKERON LL_RCC_CSI_EnableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSIKERON); +} + +/** + * @brief Disable CSI oscillator in Stop mode + * @rmtoll CR CSIKERON LL_RCC_CSI_DisableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON); +} + +/** + * @brief Get CSI Calibration value + * @note When CSITRIM is written, CSICAL is updated with the sum of + * CSITRIM and the factory trim value + * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration + * @retval A value between 0 and 255 (0xFF) + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U); + } + else + { + /* STM32H7 Rev.V */ + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); + } +#else + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @brief Set CSI Calibration trimming + * @note user-programmable trimming value that is added to the CSICAL + * @note Default value is 16, which, when added to the CSICAL value, + * should trim the CSI to 4 MHz +/- 1 % + * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming + * @param Value can be a value between 0 and 31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U); + } + else + { + /* STM32H7 Rev.V */ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); + } +#else + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @brief Get CSI Calibration trimming + * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming + * @retval A value between 0 and 31 + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U); + } + else + { + /* STM32H7 Rev.V */ + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); + } +#else + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 oscillator + * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Disable HSI48 oscillator + * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Check if HSI48 clock is ready + * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY)) ? 1UL : 0UL); +} + +/** + * @brief Get HSI48 Calibration value + * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of + * HSI48TRIM and the factory trim value + * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval A value between 0 and 1023 (0x3FF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +} +/** + * @} + */ + +#if defined(RCC_CR_D1CKRDY) + +/** @defgroup RCC_LL_EF_D1CLK D1CKREADY + * @{ + */ + +/** + * @brief Check if D1 clock is ready + * @rmtoll CR D1CKRDY LL_RCC_D1CK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ +#else + +/** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY + * @{ + */ + +/** + * @brief Check if CPU clock is ready + * @rmtoll CR CPUCKRDY LL_RCC_CPUCK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY)) ? 1UL : 0UL); +} +/* alias */ +#define LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady +/** + * @} + */ +#endif /* RCC_CR_D1CKRDY */ + +#if defined(RCC_CR_D2CKRDY) + +/** @defgroup RCC_LL_EF_D2CLK D2CKREADY + * @{ + */ + +/** + * @brief Check if D2 clock is ready + * @rmtoll CR D2CKRDY LL_RCC_D2CK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY)) ? 1UL : 0UL); +} +/** + * @} + */ +#else + +/** @defgroup RCC_LL_EF_CDCLK CDCKREADY + * @{ + */ + +/** + * @brief Check if CD clock is ready + * @rmtoll CR CDCKRDY LL_RCC_CDCK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY)) ? 1UL : 0UL); +} +#define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady +/** + * @} + */ +#endif /* RCC_CR_D2CKRDY */ + +/** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET + * @{ + */ +#if defined(RCC_GCR_WW1RSC) + +/** + * @brief Enable system wide reset for Window Watch Dog 1 + * @rmtoll GCR WW1RSC LL_RCC_WWDG1_EnableSystemReset + * @retval None. + */ +__STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_WW1RSC); +} + +/** + * @brief Check if Window Watch Dog 1 reset is system wide + * @rmtoll GCR WW1RSC LL_RCC_WWDG1_IsSystemReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC) ? 1UL : 0UL); +} +#endif /* RCC_GCR_WW1RSC */ + +#if defined(DUAL_CORE) +/** + * @brief Enable system wide reset for Window Watch Dog 2 + * @rmtoll GCR WW1RSC LL_RCC_WWDG2_EnableSystemReset + * @retval None. + */ +__STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_WW2RSC); +} + +/** + * @brief Check if Window Watch Dog 2 reset is system wide + * @rmtoll GCR WW2RSC LL_RCC_WWDG2_IsSystemReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup RCC_LL_EF_BOOT_CPU CPU + * @{ + */ + +/** + * @brief Force CM4 boot (if hold by option byte BCM4 = 0) + * @rmtoll GCR BOOT_C2 LL_RCC_ForceCM4Boot + * @retval None. + */ +__STATIC_INLINE void LL_RCC_ForceCM4Boot(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2); +} + +/** + * @brief Check if CM4 boot is forced + * @rmtoll GCR BOOT_C2 LL_RCC_IsCM4BootForced + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2) ? 1UL : 0UL); +} + +/** + * @brief Force CM7 boot (if hold by option byte BCM7 = 0) + * @rmtoll GCR BOOT_C1 LL_RCC_ForceCM7Boot + * @retval None. + */ +__STATIC_INLINE void LL_RCC_ForceCM7Boot(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1); +} + +/** + * @brief Check if CM7 boot is forced + * @rmtoll GCR BOOT_C1 LL_RCC_IsCM7BootForced + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif /*DUAL_CORE*/ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable the Clock Security System on LSE. + * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless + * a clock failure is detected. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Check if LSE failure is detected by Clock Security System + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsFailureDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL); +} + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +#if defined(RCC_BDCR_LSEEXT) +/** + * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active). + * @note The external clock must be enabled with the LSEON bit, to be used by the device. + * The LSEEXT bit can be written only if the LSE oscillator is disabled. + * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectDigitalClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); +} + +/** + * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset). + * @note The external clock must be enabled with the LSEON bit, to be used by the device. + * The LSEEXT bit can be written only if the LSE oscillator is disabled. + * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectAnalogClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); +} +#endif /* RCC_BDCR_LSEEXT */ + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Configure the system wakeup clock source + * @rmtoll CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source); +} + +/** + * @brief Get the system wakeup clock source + * @rmtoll CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); +} + +/** + * @brief Configure the kernel wakeup clock source + * @rmtoll CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source); +} + +/** + * @brief Get the kernel wakeup clock source + * @rmtoll CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK)); +} + +/** + * @brief Set System prescaler + * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_SetSysPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler) +{ +#if defined(RCC_D1CFGR_D1CPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler); +#endif /* RCC_D1CFGR_D1CPRE */ +} + +/** + * @brief Set AHB prescaler + * @rmtoll D1CFGR/CDCFGR1 HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ +#if defined(RCC_D1CFGR_HPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler); +#endif /* RCC_D1CFGR_HPRE */ +} + +/** + * @brief Set APB1 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D2CFGR_D2PPRE1) + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler); +#endif /* RCC_D2CFGR_D2PPRE1 */ +} + +/** + * @brief Set APB2 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D2CFGR_D2PPRE2) + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler); +#endif /* RCC_D2CFGR_D2PPRE2 */ +} + +/** + * @brief Set APB3 prescaler + * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_SetAPB3Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D1CFGR_D1PPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler); +#endif /* RCC_D1CFGR_D1PPRE */ +} + +/** + * @brief Set APB4 prescaler + * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_SetAPB4Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D3CFGR_D3PPRE) + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler); +#else + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler); +#endif /* RCC_D3CFGR_D3PPRE */ +} + +/** + * @brief Get System prescaler + * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_GetSysPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void) +{ +#if defined(RCC_D1CFGR_D1CPRE) + return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE)); +#endif /* RCC_D1CFGR_D1CPRE */ +} + +/** + * @brief Get AHB prescaler + * @rmtoll D1CFGR/ CDCFGR1 HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ +#if defined(RCC_D1CFGR_HPRE) + return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE)); +#endif /* RCC_D1CFGR_HPRE */ +} + +/** + * @brief Get APB1 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ +#if defined(RCC_D2CFGR_D2PPRE1) + return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1)); +#endif /* RCC_D2CFGR_D2PPRE1 */ +} + +/** + * @brief Get APB2 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ +#if defined(RCC_D2CFGR_D2PPRE2) + return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2)); +#endif /* RCC_D2CFGR_D2PPRE2 */ +} + +/** + * @brief Get APB3 prescaler + * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_GetAPB3Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void) +{ +#if defined(RCC_D1CFGR_D1PPRE) + return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE)); +#endif /* RCC_D1CFGR_D1PPRE */ +} + +/** + * @brief Get APB4 prescaler + * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_GetAPB4Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void) +{ +#if defined(RCC_D3CFGR_D3PPRE) + return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE)); +#else + return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE)); +#endif /* RCC_D3CFGR_D3PPRE */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n + * CFGR MCO1PRE LL_RCC_ConfigMCO\n + * CFGR MCO2 LL_RCC_ConfigMCO\n + * CFGR MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK + * @arg @ref LL_RCC_MCO2SOURCE_CSI + * @arg @ref LL_RCC_MCO2SOURCE_LSI + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_3 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_5 + * @arg @ref LL_RCC_MCO1_DIV_6 + * @arg @ref LL_RCC_MCO1_DIV_7 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_9 + * @arg @ref LL_RCC_MCO1_DIV_10 + * @arg @ref LL_RCC_MCO1_DIV_11 + * @arg @ref LL_RCC_MCO1_DIV_12 + * @arg @ref LL_RCC_MCO1_DIV_13 + * @arg @ref LL_RCC_MCO1_DIV_14 + * @arg @ref LL_RCC_MCO1_DIV_15 + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_3 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_5 + * @arg @ref LL_RCC_MCO2_DIV_6 + * @arg @ref LL_RCC_MCO2_DIV_7 + * @arg @ref LL_RCC_MCO2_DIV_8 + * @arg @ref LL_RCC_MCO2_DIV_9 + * @arg @ref LL_RCC_MCO2_DIV_10 + * @arg @ref LL_RCC_MCO2_DIV_11 + * @arg @ref LL_RCC_MCO2_DIV_12 + * @arg @ref LL_RCC_MCO2_DIV_13 + * @arg @ref LL_RCC_MCO2_DIV_14 + * @arg @ref LL_RCC_MCO2_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure periph clock source + * @rmtoll D2CCIP1R/CDCCIP1R * LL_RCC_SetClockSource\n + * D2CCIP2R/CDCCIP2R * LL_RCC_SetClockSource\n + * D3CCIPR/SRDCCIPR * LL_RCC_SetClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_FMCSEL) + uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource)); +#else + uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource)); +#endif /* */ + MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource)); +} + +/** + * @brief Configure USARTx clock source + * @rmtoll D2CCIP2R / D2CCIP2R USART16SEL LL_RCC_SetUSARTClockSource\n + * D2CCIP2R / D2CCIP2R USART28SEL LL_RCC_SetUSARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure LPUARTx clock source + * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D3CCIPR_LPUART1SEL) + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource); +#else + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource); +#endif /* RCC_D3CCIPR_LPUART1SEL */ +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_SetI2CClockSource\n + * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_SetI2CClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_SetLPTIMClockSource + * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_SetLPTIMClockSource\n + * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_SetLPTIMClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SAIx clock source + * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_SetSAIClockSource\n + * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_SetSAIClockSource + * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_SetSAI4xClockSource\n + * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_SetSAI4xClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SDMMCx clock source + * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_SetSDMMCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_SDMMCSEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource); +#endif /* RCC_D1CCIPR_SDMMCSEL */ +} + +/** + * @brief Configure RNGx clock source + * @rmtoll D2CCIP2R / CDCCIP2R RNGSEL LL_RCC_SetRNGClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP2R_RNGSEL) + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource); +#endif /* RCC_D2CCIP2R_RNGSEL */ +} + +/** + * @brief Configure USBx clock source + * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_SetUSBClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP2R_USBSEL) + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource); +#endif /* RCC_D2CCIP2R_USBSEL */ +} + +/** + * @brief Configure CECx clock source + * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_SetCECClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI + * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP2R_CECSEL) + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource); +#endif /* RCC_D2CCIP2R_CECSEL */ +} + +#if defined(DSI) +/** + * @brief Configure DSIx clock source + * @rmtoll D1CCIPR DSISEL LL_RCC_SetDSIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource); +} +#endif /* DSI */ + +/** + * @brief Configure DFSDMx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_SetDFSDMClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource); +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +} + +#if defined(DFSDM2_BASE) +/** + * @brief Configure DFSDMx Kernel clock source + * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_SetDFSDM2ClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource); +} +#endif /* DFSDM2_BASE */ + +/** + * @brief Configure FMCx Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR FMCSEL LL_RCC_SetFMCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_FMCSEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource); +#endif /* RCC_D1CCIPR_FMCSEL */ +} + +#if defined(QUADSPI) +/** + * @brief Configure QSPIx Kernel clock source + * @rmtoll D1CCIPR QSPISEL LL_RCC_SetQSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource); +} +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** + * @brief Configure OSPIx Kernel clock source + * @rmtoll D1CCIPR OPISEL LL_RCC_SetOSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_OCTOSPISEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource); +#endif /* RCC_D1CCIPR_OCTOSPISEL */ +} +#endif /* OCTOSPI1 || OCTOSPI2 */ + +/** + * @brief Configure CLKP Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_SetCLKPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_CKPERSEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource); +#endif /* RCC_D1CCIPR_CKPERSEL */ +} + +/** + * @brief Configure SPIx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_SetSPIClockSource\n + * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_SetSPIClockSource\n + * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_SetSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SPDIFx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_SetSPDIFClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_SPDIFSEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource); +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +} + +/** + * @brief Configure FDCANx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_SetFDCANClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_FDCANSEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource); +#endif /* RCC_D2CCIP1R_FDCANSEL */ +} + +/** + * @brief Configure SWPx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_SetSWPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_SWPSEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource); +#endif /* RCC_D2CCIP1R_SWPSEL */ +} + +/** + * @brief Configure ADCx Kernel clock source + * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_SetADCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D3CCIPR_ADCSEL) + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource); +#else + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource); +#endif /* RCC_D3CCIPR_ADCSEL */ +} + +/** + * @brief Get periph clock source + * @rmtoll D1CCIPR / CDCCIPR * LL_RCC_GetClockSource\n + * D2CCIP1R / CDCCIP1R * LL_RCC_GetClockSource\n + * D2CCIP2R / CDCCIP2R * LL_RCC_GetClockSource\n + * D3CCIPR / SRDCCIPR * LL_RCC_GetClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @arg @ref LL_RCC_I2C123_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI23_CLKSOURCE + * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI123_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI45_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph) +{ +#if defined(RCC_D1CCIPR_FMCSEL) + const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph))); +#else + const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph))); +#endif /* RCC_D1CCIPR_FMCSEL */ + return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT)); +} + +/** + * @brief Get USARTx clock source + * @rmtoll D2CCIP2R / CDCCIP2R USART16SEL LL_RCC_GetUSARTClockSource\n + * D2CCIP2R / CDCCIP2R USART28SEL LL_RCC_GetUSARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get LPUART clock source + * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D3CCIPR_LPUART1SEL) + return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)); +#else + return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)); +#endif /* RCC_D3CCIPR_LPUART1SEL */ +} + +/** + * @brief Get I2Cx clock source + * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_GetI2CClockSource\n + * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_GetI2CClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C123_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get LPTIM clock source + * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_GetLPTIMClockSource\n + * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource\n + * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_GetLPTIMClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SAIx clock source + * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_GetSAIClockSource\n + * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_GetSAIClockSource + * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_GetSAIClockSource\n + * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_GetSAIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SDMMC clock source + * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_GetSDMMCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_SDMMCSEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)); +#endif /* RCC_D1CCIPR_SDMMCSEL */ +} + +/** + * @brief Get RNG clock source + * @rmtoll D2CCIP2R RNGSEL LL_RCC_GetRNGClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP2R_RNGSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)); +#endif /* RCC_D2CCIP2R_RNGSEL */ +} + +/** + * @brief Get USB clock source + * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_GetUSBClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP2R_USBSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)); +#endif /* RCC_D2CCIP2R_USBSEL */ +} + +/** + * @brief Get CEC clock source + * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_GetCECClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI + * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122 + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP2R_CECSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)); +#endif /* RCC_D2CCIP2R_CECSEL */ +} + +#if defined(DSI) +/** + * @brief Get DSI clock source + * @rmtoll D1CCIPR DSISEL LL_RCC_GetDSIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)); +} +#endif /* DSI */ + +/** + * @brief Get DFSDM Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_GetDFSDMClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_DFSDM1SEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)); +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +} + +#if defined(DFSDM2_BASE) +/** + * @brief Get DFSDM2 Kernel clock source + * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_GetDFSDM2ClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)); +} +#endif /* DFSDM2_BASE */ + +/** + * @brief Get FMC Kernel clock source + * @rmtoll D1CCIPR / D1CCIPR FMCSEL LL_RCC_GetFMCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_FMCSEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)); +#endif /* RCC_D1CCIPR_FMCSEL */ +} + +#if defined(QUADSPI) +/** + * @brief Get QSPI Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR QSPISEL LL_RCC_GetQSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_QSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)); +} +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** + * @brief Get OSPI Kernel clock source + * @rmtoll CDCCIPR OSPISEL LL_RCC_GetOSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_OCTOSPISEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)); +#endif /* RCC_D1CCIPR_OCTOSPISEL */ +} +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + +/** + * @brief Get CLKP Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_GetCLKPClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_CKPERSEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)); +#endif /* RCC_D1CCIPR_CKPERSEL */ +} + +/** + * @brief Get SPIx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_GetSPIClockSource\n + * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_GetSPIClockSource\n + * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_GetSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI123_CLKSOURCE + * @arg @ref LL_RCC_SPI45_CLKSOURCE + * @arg @ref LL_RCC_SPI6_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all stm32h7xx lines. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SPDIF Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_GetSPDIFClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIF_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_SPDIFSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)); +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +} + +/** + * @brief Get FDCAN Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_GetFDCANClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_FDCANSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)); +#endif /* RCC_D2CCIP1R_FDCANSEL */ +} + +/** + * @brief Get SWP Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_GetSWPClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SWP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_SWPSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)); +#endif /* RCC_D2CCIP1R_SWPSEL */ +} + +/** + * @brief Get ADC Kernel clock source + * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_GetADCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined (RCC_D3CCIPR_ADCSEL) + return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)); +#else + return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)); +#endif /* RCC_D3CCIPR_ADCSEL */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST / VSWRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST / VSWRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ +#if defined(RCC_BDCR_BDRST) + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +#else + CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST); +#endif /* RCC_BDCR_BDRST */ +} + +/** + * @brief Set HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @arg @ref LL_RCC_RTC_HSE_DIV_32 + * @arg @ref LL_RCC_RTC_HSE_DIV_33 + * @arg @ref LL_RCC_RTC_HSE_DIV_34 + * @arg @ref LL_RCC_RTC_HSE_DIV_35 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_37 + * @arg @ref LL_RCC_RTC_HSE_DIV_38 + * @arg @ref LL_RCC_RTC_HSE_DIV_39 + * @arg @ref LL_RCC_RTC_HSE_DIV_40 + * @arg @ref LL_RCC_RTC_HSE_DIV_41 + * @arg @ref LL_RCC_RTC_HSE_DIV_42 + * @arg @ref LL_RCC_RTC_HSE_DIV_43 + * @arg @ref LL_RCC_RTC_HSE_DIV_44 + * @arg @ref LL_RCC_RTC_HSE_DIV_45 + * @arg @ref LL_RCC_RTC_HSE_DIV_46 + * @arg @ref LL_RCC_RTC_HSE_DIV_47 + * @arg @ref LL_RCC_RTC_HSE_DIV_48 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_50 + * @arg @ref LL_RCC_RTC_HSE_DIV_51 + * @arg @ref LL_RCC_RTC_HSE_DIV_52 + * @arg @ref LL_RCC_RTC_HSE_DIV_53 + * @arg @ref LL_RCC_RTC_HSE_DIV_54 + * @arg @ref LL_RCC_RTC_HSE_DIV_55 + * @arg @ref LL_RCC_RTC_HSE_DIV_56 + * @arg @ref LL_RCC_RTC_HSE_DIV_57 + * @arg @ref LL_RCC_RTC_HSE_DIV_58 + * @arg @ref LL_RCC_RTC_HSE_DIV_59 + * @arg @ref LL_RCC_RTC_HSE_DIV_60 + * @arg @ref LL_RCC_RTC_HSE_DIV_61 + * @arg @ref LL_RCC_RTC_HSE_DIV_62 + * @arg @ref LL_RCC_RTC_HSE_DIV_63 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); +} + +/** + * @brief Get HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @arg @ref LL_RCC_RTC_HSE_DIV_32 + * @arg @ref LL_RCC_RTC_HSE_DIV_33 + * @arg @ref LL_RCC_RTC_HSE_DIV_34 + * @arg @ref LL_RCC_RTC_HSE_DIV_35 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_37 + * @arg @ref LL_RCC_RTC_HSE_DIV_38 + * @arg @ref LL_RCC_RTC_HSE_DIV_39 + * @arg @ref LL_RCC_RTC_HSE_DIV_40 + * @arg @ref LL_RCC_RTC_HSE_DIV_41 + * @arg @ref LL_RCC_RTC_HSE_DIV_42 + * @arg @ref LL_RCC_RTC_HSE_DIV_43 + * @arg @ref LL_RCC_RTC_HSE_DIV_44 + * @arg @ref LL_RCC_RTC_HSE_DIV_45 + * @arg @ref LL_RCC_RTC_HSE_DIV_46 + * @arg @ref LL_RCC_RTC_HSE_DIV_47 + * @arg @ref LL_RCC_RTC_HSE_DIV_48 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_50 + * @arg @ref LL_RCC_RTC_HSE_DIV_51 + * @arg @ref LL_RCC_RTC_HSE_DIV_52 + * @arg @ref LL_RCC_RTC_HSE_DIV_53 + * @arg @ref LL_RCC_RTC_HSE_DIV_54 + * @arg @ref LL_RCC_RTC_HSE_DIV_55 + * @arg @ref LL_RCC_RTC_HSE_DIV_56 + * @arg @ref LL_RCC_RTC_HSE_DIV_57 + * @arg @ref LL_RCC_RTC_HSE_DIV_58 + * @arg @ref LL_RCC_RTC_HSE_DIV_59 + * @arg @ref LL_RCC_RTC_HSE_DIV_60 + * @arg @ref LL_RCC_RTC_HSE_DIV_61 + * @arg @ref LL_RCC_RTC_HSE_DIV_62 + * @arg @ref LL_RCC_RTC_HSE_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM + * @{ + */ + +/** + * @brief Set Timers Clock Prescalers + * @rmtoll CFGR TIMPRE LL_RCC_SetTIMPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler); +} + +/** + * @brief Get Timers Clock Prescalers + * @rmtoll CFGR TIMPRE LL_RCC_GetTIMPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE)); +} + +/** + * @} + */ + +#if defined(HRTIM1) +/** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM + * @{ + */ + +/** + * @brief Set High Resolution Timers Clock Source + * @rmtoll CFGR HRTIMSEL LL_RCC_SetHRTIMClockSource + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler); +} +#endif /* HRTIM1 */ + +#if defined(HRTIM1) +/** + * @brief Get High Resolution Timers Clock Source + * @rmtoll CFGR HRTIMSEL LL_RCC_GetHRTIMClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU + */ +__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)); +} +/** + * @} + */ +#endif /* HRTIM1 */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Set the oscillator used as PLL clock source. + * @note PLLSRC can be written only when All PLLs are disabled. + * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_SetSource + * @param PLLSource parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_CSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_CSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_NONE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC)); +} + +/** + * @brief Enable PLL1 + * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Disable PLL1 + * @note Cannot be disabled if the PLL1 clock is used as the system clock + * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Check if PLL1 Ready + * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL1P + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN); +} + +/** + * @brief Enable PLL1Q + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN); +} + +/** + * @brief Enable PLL1R + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN); +} + +/** + * @brief Enable PLL1 FRACN + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); +} + +/** + * @brief Check if PLL1 P is enabled + * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 Q is enabled + * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 R is enabled + * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 FRACN is enabled + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL1P + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN); +} + +/** + * @brief Disable PLL1Q + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN); +} + +/** + * @brief Disable PLL1R + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN); +} + +/** + * @brief Disable PLL1 FRACN + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); +} + +/** + * @brief Set PLL1 VCO OutputRange + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOuputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos); +} + +/** + * @brief Set PLL1 VCO Input Range + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos); +} + +/** + * @brief Get PLL1 N Coefficient + * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_GetN + * @retval A value between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 M Coefficient + * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos); +} + +/** + * @brief Get PLL1 P Coefficient + * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_GetP + * @retval A value between 2 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 Q Coefficient + * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 R Coefficient + * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); +} + +/** + * @brief Set PLL1 N Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_SetN + * @param N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N - 1UL) << RCC_PLL1DIVR_N1_Pos); +} + +/** + * @brief Set PLL1 M Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_SetM + * @param M parameter can be a value between 0 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos); +} + +/** + * @brief Set PLL1 P Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_SetP + * @param P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines. + */ +__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P - 1UL) << RCC_PLL1DIVR_P1_Pos); +} + +/** + * @brief Set PLL1 Q Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q - 1UL) << RCC_PLL1DIVR_Q1_Pos); +} + +/** + * @brief Set PLL1 R Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos); +} + +/** + * @brief Set PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos); +} + +/** + * @brief Enable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Disable PLL2 + * @note Cannot be disabled if the PLL2 clock is used as the system clock + * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Check if PLL2 Ready + * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2P + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN); +} + +/** + * @brief Enable PLL2Q + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN); +} + +/** + * @brief Enable PLL2R + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN); +} + +/** + * @brief Enable PLL2 FRACN + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN); +} + +/** + * @brief Check if PLL2 P is enabled + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 Q is enabled + * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 R is enabled + * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 FRACN is enabled + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL2P + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN); +} + +/** + * @brief Disable PLL2Q + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN); +} + +/** + * @brief Disable PLL2R + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN); +} + +/** + * @brief Disable PLL2 FRACN + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN); +} + +/** + * @brief Set PLL2 VCO OutputRange + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOuputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos); +} + +/** + * @brief Set PLL2 VCO Input Range + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos); +} + +/** + * @brief Get PLL2 N Coefficient + * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_GetN + * @retval A value between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 M Coefficient + * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); +} + +/** + * @brief Get PLL2 P Coefficient + * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_GetP + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 Q Coefficient + * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 R Coefficient + * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >> RCC_PLL2FRACR_FRACN2_Pos); +} + +/** + * @brief Set PLL2 N Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_SetN + * @param N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N - 1UL) << RCC_PLL2DIVR_N2_Pos); +} + +/** + * @brief Set PLL2 M Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_SetM + * @param M parameter can be a value between 0 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos); +} + +/** + * @brief Set PLL2 P Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_SetP + * @param P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P - 1UL) << RCC_PLL2DIVR_P2_Pos); +} + +/** + * @brief Set PLL2 Q Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q - 1UL) << RCC_PLL2DIVR_Q2_Pos); +} + +/** + * @brief Set PLL2 R Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R - 1UL) << RCC_PLL2DIVR_R2_Pos); +} + +/** + * @brief Set PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos); +} + +/** + * @brief Enable PLL3 + * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Disable PLL3 + * @note Cannot be disabled if the PLL3 clock is used as the system clock + * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Check if PLL3 Ready + * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL3P + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN); +} + +/** + * @brief Enable PLL3Q + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN); +} + +/** + * @brief Enable PLL3R + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN); +} + +/** + * @brief Enable PLL3 FRACN + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); +} + +/** + * @brief Check if PLL3 P is enabled + * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 Q is enabled + * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 R is enabled + * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 FRACN is enabled + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL3P + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL3P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN); +} + +/** + * @brief Disable PLL3Q + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN); +} + +/** + * @brief Disable PLL3R + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN); +} + +/** + * @brief Disable PLL3 FRACN + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); +} + +/** + * @brief Set PLL3 VCO OutputRange + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOuputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos); +} + +/** + * @brief Set PLL3 VCO Input Range + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos); +} + +/** + * @brief Get PLL3 N Coefficient + * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_GetN + * @retval A value between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 M Coefficient + * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); +} + +/** + * @brief Get PLL3 P Coefficient + * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_GetP + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 Q Coefficient + * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 R Coefficient + * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >> RCC_PLL3FRACR_FRACN3_Pos); +} + +/** + * @brief Set PLL3 N Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_SetN + * @param N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N - 1UL) << RCC_PLL3DIVR_N3_Pos); +} + +/** + * @brief Set PLL3 M Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_SetM + * @param M parameter can be a value between 0 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos); +} + +/** + * @brief Set PLL3 P Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_SetP + * @param P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P - 1UL) << RCC_PLL3DIVR_P3_Pos); +} + +/** + * @brief Set PLL3 Q Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q - 1UL) << RCC_PLL3DIVR_Q3_Pos); +} + +/** + * @brief Set PLL3 R Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R - 1UL) << RCC_PLL3DIVR_R3_Pos); +} + +/** + * @brief Set PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos); +} + + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear CSI ready interrupt flag + * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC); +} + +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); +} + +/** + * @brief Clear PLL1 ready interrupt flag + * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); +} + +/** + * @brief Clear PLL2 ready interrupt flag + * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC); +} + +/** + * @brief Clear PLL3 ready interrupt flag + * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC); +} + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Clear HSE Clock security system interrupt flag + * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if CSI ready interrupt occurred or not + * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 ready interrupt occurred or not + * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 ready interrupt occurred or not + * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 ready interrupt occurred or not + * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE Clock security system interrupt occurred or not + * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power D1 reset is set or not. + * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST (*)\n + * RSR LPWR1RSTF LL_RCC_IsActiveFlag_LPWRRST (**) + * + * (*) Only available for single core devices + * (**) Only available for Dual core devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ +#if defined(DUAL_CORE) + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); +#else + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF)) ? 1UL : 0UL); +#endif /*DUAL_CORE*/ +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Low Power D2 reset is set or not. + * @rmtoll RSR LPWR2RSTF LL_RCC_IsActiveFlag_LPWR2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag Window Watchdog 1 reset is set or not. + * @rmtoll RSR WWDG1RSTF LL_RCC_IsActiveFlag_WWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Window Watchdog 2 reset is set or not. + * @rmtoll RSR WWDG2RSTF LL_RCC_IsActiveFlag_WWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag Independent Watchdog 1 reset is set or not. + * @rmtoll RSR IWDG1RSTF LL_RCC_IsActiveFlag_IWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Independent Watchdog 2 reset is set or not. + * @rmtoll RSR IWDG2RSTF LL_RCC_IsActiveFlag_IWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST (*)\n + * RSR SFT1RSTF LL_RCC_IsActiveFlag_SFTRST (**) + * + * (*) Only available for single core devices + * (**) Only available for Dual core devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ +#if defined(DUAL_CORE) + return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); +#else + return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF)) ? 1UL : 0UL); +#endif /*DUAL_CORE*/ +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll RSR SFT2RSTF LL_RCC_IsActiveFlag_SFT2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +#if defined(RCC_RSR_D1RSTF) +/** + * @brief Check if RCC flag D1 reset is set or not. + * @rmtoll RSR D1RSTF LL_RCC_IsActiveFlag_D1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); +} +#endif /* RCC_RSR_D1RSTF */ + +#if defined(RCC_RSR_CDRSTF) +/** + * @brief Check if RCC flag CD reset is set or not. + * @rmtoll RSR CDRSTF LL_RCC_IsActiveFlag_CDRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF)) ? 1UL : 0UL); +} +#endif /* RCC_RSR_CDRSTF */ + +#if defined(RCC_RSR_D2RSTF) +/** + * @brief Check if RCC flag D2 reset is set or not. + * @rmtoll RSR D2RSTF LL_RCC_IsActiveFlag_D2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); +} +#endif /* RCC_RSR_D2RSTF */ + +#if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) +/** + * @brief Check if RCC flag CPU reset is set or not. + * @rmtoll RSR CPURSTF LL_RCC_IsActiveFlag_CPURST (*)\n + * RSR C1RSTF LL_RCC_IsActiveFlag_CPURST (**) + * + * (*) Only available for single core devices + * (**) Only available for Dual core devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void) +{ +#if defined(DUAL_CORE) + return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); +#else + return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF)) ? 1UL : 0UL); +#endif/*DUAL_CORE*/ +} +#endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */ + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag CPU2 reset is set or not. + * @rmtoll RSR C2RSTF LL_RCC_IsActiveFlag_CPU2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Set RMVF bit to clear all reset flags. + * @rmtoll RSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC_C1 flag Low Power D1 reset is set or not. + * @rmtoll RSR LPWR1RSTF LL_C1_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Low Power D2 reset is set or not. + * @rmtoll RSR LPWR2RSTF LL_C1_RCC_IsActiveFlag_LPWR2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Window Watchdog 1 reset is set or not. + * @rmtoll RSR WWDG1RSTF LL_C1_RCC_IsActiveFlag_WWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Window Watchdog 2 reset is set or not. + * @rmtoll RSR WWDG2RSTF LL_C1_RCC_IsActiveFlag_WWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Independent Watchdog 1 reset is set or not. + * @rmtoll RSR IWDG1RSTF LL_C1_RCC_IsActiveFlag_IWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Independent Watchdog 2 reset is set or not. + * @rmtoll RSR IWDG2RSTF LL_C1_RCC_IsActiveFlag_IWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Software reset is set or not. + * @rmtoll RSR SFT1RSTF LL_C1_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Software reset is set or not. + * @rmtoll RSR SFT2RSTF LL_C1_RCC_IsActiveFlag_SFT2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_C1_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_C1_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_C1_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag D1 reset is set or not. + * @rmtoll RSR D1RSTF LL_C1_RCC_IsActiveFlag_D1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag D2 reset is set or not. + * @rmtoll RSR D2RSTF LL_C1_RCC_IsActiveFlag_D2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag CPU reset is set or not. + * @rmtoll RSR C1RSTF LL_C1_RCC_IsActiveFlag_CPURST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag CPU2 reset is set or not. + * @rmtoll RSR C2RSTF LL_C1_RCC_IsActiveFlag_CPU2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll RSR RMVF LL_C1_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF); +} + +/** + * @brief Check if RCC_C2 flag Low Power D1 reset is set or not. + * @rmtoll RSR LPWR1RSTF LL_C2_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Low Power D2 reset is set or not. + * @rmtoll RSR LPWR2RSTF LL_C2_RCC_IsActiveFlag_LPWR2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Window Watchdog 1 reset is set or not. + * @rmtoll RSR WWDG1RSTF LL_C2_RCC_IsActiveFlag_WWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Window Watchdog 2 reset is set or not. + * @rmtoll RSR WWDG2RSTF LL_C2_RCC_IsActiveFlag_WWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Independent Watchdog 1 reset is set or not. + * @rmtoll RSR IWDG1RSTF LL_C2_RCC_IsActiveFlag_IWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Independent Watchdog 2 reset is set or not. + * @rmtoll RSR IWDG2RSTF LL_C2_RCC_IsActiveFlag_IWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Software reset is set or not. + * @rmtoll RSR SFT1RSTF LL_C2_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Software reset is set or not. + * @rmtoll RSR SFT2RSTF LL_C2_RCC_IsActiveFlag_SFT2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_C2_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_C2_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_C2_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag D1 reset is set or not. + * @rmtoll RSR D1RSTF LL_C2_RCC_IsActiveFlag_D1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag D2 reset is set or not. + * @rmtoll RSR D2RSTF LL_C2_RCC_IsActiveFlag_D2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag CPU reset is set or not. + * @rmtoll RSR C1RSTF LL_C2_RCC_IsActiveFlag_CPURST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag CPU2 reset is set or not. + * @rmtoll RSR C2RSTF LL_C2_RCC_IsActiveFlag_CPU2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll RSR RMVF LL_C2_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF); +} +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable CSI ready interrupt + * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); +} + +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Enable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Enable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Enable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Enable LSECSS interrupt + * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable CSI ready interrupt + * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); +} + +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Disable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Disable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Disable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Disable LSECSS interrupt + * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if CSI ready interrupt source is enabled or disabled. + * @rmtoll CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL1 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL2 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL3 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSECSS interrupt source is enabled or disabled. + * @rmtoll CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +void LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR); + +void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); + +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); +#if defined(DFSDM2_BASE) +uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource); +#endif /* DFSDM2_BASE */ +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource); +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); +uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource); +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource); +#if defined(QUADSPI) +uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource); +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) +uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource); +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ +uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + + +/** + * @} + */ +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_RCC_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h new file mode 100644 index 0000000..aa5149a --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h @@ -0,0 +1,2442 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_LL_SYSTEM_H +#define __STM32H7xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ +/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status + * @{ + */ +#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U +#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U +#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U +#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U +#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U +#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U +#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U +#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status + * @{ + */ +#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U +#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U +#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U +#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U +#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U +#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U +#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U +#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */ +#if defined(I2C5) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus for I2C5 */ +#endif /*I2C5*/ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control +* @{ +*/ +#if defined(SYSCFG_PMCR_BOOSTEN) +#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */ +#endif /*SYSCFG_PMCR_BOOSTEN*/ +#define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< PA0 Switch Open */ +#define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< PA1 Switch Open */ +#define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< PC2 Switch Open */ +#define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< PC3 Switch Open */ +/** + * @} + */ + +#if defined(SYSCFG_PMCR_EPIS_SEL) +/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection +* @{ +*/ +#define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */ +#define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< ETH Media RMII interface */ +/** + * @} + */ +#endif /* SYSCFG_PMCR_EPIS_SEL */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ +#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ +#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ +#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ +#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ +#define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ +#if defined(GPIOI) +#define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ +#endif /*GPIOI*/ +#define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */ +#define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML /*!< Enables and locks the ITCM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML /*!< Enables and locks the DTCM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L /*!< Enables and locks the SRAM1 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L /*!< Enables and locks the SRAM2 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#if defined(SYSCFG_CFGR_SRAM3L) +#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L /*!< Enables and locks the SRAM3 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ +#endif /*SYSCFG_CFGR_SRAM3L*/ + +#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L /*!< Enables and locks the SRAM4 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML /*!< Enables and locks the BKRAM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L /*!< Enables and locks the Cortex-M7 LOCKUP signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL /*!< Enables and locks the FLASH double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL /*!< Enables and locks the PVD connection + with TIM1/8/15/16/17 and HRTIM Break Input + and also the PVDE and PLS bits of the Power Control Interface */ +#if defined(DUAL_CORE) +#define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L /*!< Enables and locks the Cortex-M4 LOCKUP signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_CELL_CODE 0U +#define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS +/** + * @} + */ + +/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes + * @{ + */ +#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U +#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M +/** + * @} + */ + +#if defined (DUAL_CORE) +/** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes + * @{ + */ +#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U +#define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration + * @{ + */ +#define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U +#define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U +#define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U +#define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U +/** + * @} + */ +#ifdef SYSCFG_UR17_TCM_AXI_CFG +/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package + * @{ + */ +#define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U +#define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U +#define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U +#define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U +/** + * @} + */ +#endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */ +#if defined(SYSCFG_PKGR_PKG) +/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package + * @{ + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define LL_SYSCFG_LQFP100_PACKAGE 0U +#define LL_SYSCFG_TQFP144_PACKAGE 2U +#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U +#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U +#elif (STM32H7_DEV_ID == 0x483UL) +#define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U +#define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U +#define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U +#define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U +#define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U +#define LL_SYSCFG_LQFP144_PACKAGE 5U +#define LL_SYSCFG_UFBGA144_PACKAGE 6U +#define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U +#define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U +#define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U +#define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U +#endif /* STM32H7_DEV_ID == 0x450UL */ +/** + * @} + */ +#endif /* SYSCFG_PKGR_PKG */ + +/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level + * @{ + */ +#define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U +#define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0 +#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1 +#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /*!< TIM2 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 /*!< TIM3 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 /*!< TIM4 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 /*!< TIM5 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 /*!< TIM6 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 /*!< TIM7 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 /*!< TIM12 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 /*!< TIM13 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 /*!< TIM14 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 /*!< LPTIM1 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ +#if defined(I2C5) +#define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5 /*!< I2C5 SMBUS timeout mode stopped when Core is halted */ +#endif /*I2C5*/ +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) +#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */ +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ +#if defined(TIM23) +#define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23 /*!< TIM23 is frozen while the core is in debug mode */ +#endif /*TIM23*/ +#if defined(TIM24) +#define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24 /*!< TIM24 is frozen while the core is in debug mode */ +#endif /*TIM24*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /*!< TIM1 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 /*!< TIM8 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /*!< TIM15 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /*!< TIM16 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /*!< TIM17 counter stopped when core is halted */ +#if defined(HRTIM1) +#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /*!< HRTIM counter stopped when core is halted */ +#endif /*HRTIM1*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /*!< WWDG1 is frozen while the core is in debug mode */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /*!< I2C4 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 /*!< LPTIM2 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 /*!< LPTIM3 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 /*!< LPTIM4 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 /*!< LPTIM5 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC /*!< RTC is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 /*!< IWDG1 is frozen while the core is in debug mode */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ +#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +#if defined(SYSCFG_PMCR_EPIS_SEL) +/** + * @brief Select Ethernet PHY interface + * @rmtoll PMCR EPIS_SEL LL_SYSCFG_SetPHYInterface + * @param Interface This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_ETH_MII + * @arg @ref LL_SYSCFG_ETH_RMII + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) +{ + MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface); +} + +/** + * @brief Get Ethernet PHY interface + * @rmtoll PMCR EPIS_SEL LL_SYSCFG_GetPHYInterface + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_ETH_MII + * @arg @ref LL_SYSCFG_ETH_RMII + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL)); +} + +#endif /* SYSCFG_PMCR_EPIS_SEL */ +/** + * @brief Open an Analog Switch + * @rmtoll PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch + * @rmtoll PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch + * @rmtoll PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch + * @rmtoll PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch + * @param AnalogSwitch This parameter can be one of the following values: + * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch) +{ + SET_BIT(SYSCFG->PMCR, AnalogSwitch); +} + +/** + * @brief Close an Analog Switch + * @rmtoll PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch + * @rmtoll PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch + * @rmtoll PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch + * @rmtoll PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch + * @param AnalogSwitch This parameter can be one of the following values: + * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch) +{ + CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch); +} +#ifdef SYSCFG_PMCR_BOOSTEN +/** + * @brief Enable the Analog booster to reduce the total harmonic distortion + * of the analog switch when the supply voltage is lower than 2.7 V + * @rmtoll PMCR BOOSTEN LL_SYSCFG_EnableAnalogBooster + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) +{ + SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} + +/** + * @brief Disable the Analog booster + * @rmtoll PMCR BOOSTEN LL_SYSCFG_DisableAnalogBooster + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) +{ + CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} +#endif /*SYSCFG_PMCR_BOOSTEN*/ +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->PMCR, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI (*) + * @arg @ref LL_SYSCFG_EXTI_PORTJ + * @arg @ref LL_SYSCFG_EXTI_PORTK + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI (*) + * @arg @ref LL_SYSCFG_EXTI_PORTJ + * @arg @ref LL_SYSCFG_EXTI_PORTK + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U)); +} + +/** + * @brief Set connections to TIM1/8/15/16/17 and HRTIM Break inputs + * @note this feature is available on STM32H7 rev.B and above + * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR ITCML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR DTCML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM1L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM2L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM3L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM4L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR BKRAML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR CM7L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR FLASHL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR PVDL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR_CM4L LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only) + * @retval None + * (*) value not defined in all devices + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ + SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break); +#elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L) + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ + SYSCFG_CFGR_PVDL, Break); +#elif defined(SYSCFG_CFGR_AXISRAML) + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\ + Break); +#else + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\ + SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ + SYSCFG_CFGR_PVDL, Break); +#endif /* DUAL_CORE */ +} + +/** + * @brief Get connections to TIM1/8/15/16/17 and HRTIM Break inputs + * @note this feature is available on STM32H7 rev.B and above + * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR ITCML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR DTCML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM1L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM2L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM3L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM4L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR BKRAML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR CM7L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR FLASHL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR PVDL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR_CM4L LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only) + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ +#if defined(DUAL_CORE) + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ + SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L)); +#elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L) + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ + SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); +#elif defined (SYSCFG_CFGR_AXISRAML) + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ + SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); +#else + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); +#endif /* DUAL_CORE */ +} + +/** + * @brief Enable the Compensation Cell + * @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); +} + +/** + * @brief Disable the Compensation Cell + * @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); +} + +/** + * @brief Check if the Compensation Cell is enabled + * @rmtoll CCCSR EN LL_SYSCFG_IsEnabledCompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL); +} + +/** + * @brief Get Compensation Cell ready Flag + * @rmtoll CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL); +} + +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +#if defined(SYSCFG_CCCSR_HSLV1) +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV1 LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1); +} + +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV2 LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2); +} + +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV3 LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3); +} +#endif /*SYSCFG_CCCSR_HSLV1*/ + + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +#if defined(SYSCFG_CCCSR_HSLV1) +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV1 LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1); +} + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV2 LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2); +} + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV3 LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3); +} +#endif /*SYSCFG_CCCSR_HSLV1*/ + +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL); +#endif /*SYSCFG_CCCSR_HSLV*/ +} + +#if defined(SYSCFG_CCCSR_HSLV1) +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV1 LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL); +} + +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV2 LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL); +} + +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV3 LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL); +} +#endif /*SYSCFG_CCCSR_HSLV1*/ + +/** + * @brief Set the code selection for the I/O Compensation cell + * @rmtoll CCCSR CS LL_SYSCFG_SetCellCompensationCode + * @param CompCode: Selects the code to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode) +{ + SET_BIT(SYSCFG->CCCSR, CompCode); +} + +/** + * @brief Get the code selected for the I/O Compensation cell + * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS)); +} + +#ifdef SYSCFG_CCCSR_CS_MMC + +/** + * @brief Get the code selected for the I/O Compensation cell on the VDDMMC power rail + * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC)); +} +#endif /*SYSCFG_CCCSR_CS_MMC*/ + +/** + * @brief Get I/O compensation cell value for PMOS transistors + * @rmtoll CCVR PCV LL_SYSCFG_GetPMOSCompensationValue + * @retval Returned value is the I/O compensation cell value for PMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV)); +} + +/** + * @brief Get I/O compensation cell value for NMOS transistors + * @rmtoll CCVR NCV LL_SYSCFG_GetNMOSCompensationValue + * @retval Returned value is the I/O compensation cell value for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV)); +} + +/** + * @brief Set I/O compensation cell code for PMOS transistors + * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode); +} + +/** + * @brief Get I/O compensation cell code for PMOS transistors + * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for PMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC)); +} + +#ifdef SYSCFG_CCCR_PCC_MMC + +/** + * @brief Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail + * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode); +} + +/** + * @brief Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail + * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for PMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC)); +} +#endif /* SYSCFG_CCCR_PCC_MMC */ + +/** + * @brief Set I/O compensation cell code for NMOS transistors + * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode); +} + +/** + * @brief Get I/O compensation cell code for NMOS transistors + * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC)); +} + +#ifdef SYSCFG_CCCR_NCC_MMC + +/** + * @brief Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail. + * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode + * @param NMOSCode: NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode); +} + +/** + * @brief Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail. + * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC)); +} +#endif /*SYSCFG_CCCR_NCC_MMC*/ + +#ifdef SYSCFG_PKGR_PKG +/** + * @brief Get the device package + * @rmtoll PKGR PKG LL_SYSCFG_GetPackage + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*) + * @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*) + * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*) + * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*) + * @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*) + * @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*) + * @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**) + * @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**) + * @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**) + * + * (*) : For stm32h74xxx and stm32h75xxx family lines. + * (**): For stm32h72xxx and stm32h73xxx family lines. + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG)); +} +#endif /*SYSCFG_PKGR_PKG*/ + +#ifdef SYSCFG_UR0_RDP +/** + * @brief Get the Flash memory protection level + * @rmtoll UR0 RDP LL_SYSCFG_GetFLashProtectionLevel + * @retval Returned value can be one of the following values: + * 0xAA : RDP level 0 + * 0xCC : RDP level 2 + * Any other value : RDP level 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP)); +} +#ifdef SYSCFG_UR0_BKS +/** + * @brief Indicate if the Flash memory bank addresses are inverted or not + * @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void) +{ + return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL); +} +#endif /*SYSCFG_UR0_BKS*/ + +/** + * @brief Get the BOR Threshold Reset Level + * @rmtoll UR2 BORH LL_SYSCFG_GetBrownoutResetLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL + * @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL + * @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL + * @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH)); +} +/** + * @brief BootCM7 address 0 configuration + * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_SetCM7BootAddress0 + * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress) +{ + /* Configure CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos)); +#else + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos)); +#endif /*DUAL_CORE*/ + +} + +/** + * @brief Get BootCM7 address 0 + * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_GetCM7BootAddress0 + * @retval Returned the CM7 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void) +{ + /* Get CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos); +#else + return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos); +#endif /*DUAL_CORE*/ +} + +/** + * @brief BootCM7 address 1 configuration + * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_SetCM7BootAddress1 + * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address1 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress) +{ + /* Configure CM7 BOOT ADD1 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress); +#else + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress); +#endif /*DUAL_CORE*/ +} + +/** + * @brief Get BootCM7 address 1 + * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_GetCM7BootAddress1 + * @retval Returned the CM7 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void) +{ + /* Get CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1)); +#else + return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1)); +#endif /* DUAL_CORE */ +} + +#if defined(DUAL_CORE) +/** + * @brief BootCM4 address 0 configuration + * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_SetCM4BootAddress0 + * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress) +{ + /* Configure CM4 BOOT ADD0 */ + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos)); +} + +/** + * @brief Get BootCM4 address 0 + * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_GetCM4BootAddress0 + * @retval Returned the CM4 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void) +{ + /* Get CM4 BOOT ADD0 */ + return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos); +} + +/** + * @brief BootCM4 address 1 configuration + * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_SetCM4BootAddress1 + * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address1 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress) +{ + /* Configure CM4 BOOT ADD1 */ + MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress); +} + +/** + * @brief Get BootCM4 address 1 + * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_GetCM4BootAddress1 + * @retval Returned the CM4 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void) +{ + /* Get CM4 BOOT ADD0 */ + return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1)); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Indicates if the flash protected area (Bank 1) is erased by a mass erase + * @rmtoll UR4 MEPAD_BANK1 LL_SYSCFG_IsFlashB1ProtectedAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the flash secured area (Bank 1) is erased by a mass erase + * @rmtoll UR5 MESAD_BANK1 LL_SYSCFG_IsFlashB1SecuredAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 0 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector0WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 1 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector1WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 2 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector2WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 3 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector3WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 4 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector4WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 5 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector5WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 6 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector6WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 7 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector7WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Get the protected area start address for Flash bank 1 + * @rmtoll UR6 PABEG_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress + * @retval Returned the protected area start address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1)); +} + +/** + * @brief Get the protected area end address for Flash bank 1 + * @rmtoll UR6 PAEND_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress + * @retval Returned the protected area end address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1)); +} + +/** + * @brief Get the secured area start address for Flash bank 1 + * @rmtoll UR7 SABEG_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaStartAddress + * @retval Returned the secured area start address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1)); +} + +/** + * @brief Get the secured area end address for Flash bank 1 + * @rmtoll UR7 SAEND_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaEndAddress + * @retval Returned the secured area end address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1)); +} + +#ifdef SYSCFG_UR8_MEPAD_BANK2 +/** + * @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase + * @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the flash secured area (Bank 2) is erased by a mass erase + * @rmtoll UR8 MESAD_BANK2 LL_SYSCFG_IsFlashB2SecuredAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL); +} +#endif /*SYSCFG_UR8_MEPAD_BANK2*/ + +#ifdef SYSCFG_UR9_WRPN_BANK2 +/** + * @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 1 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector1WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 2 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector2WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 3 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector3WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 4 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector4WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 5 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector5WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 6 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector6WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 7 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector7WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Get the protected area start address for Flash bank 2 + * @rmtoll UR9 PABEG_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress + * @retval Returned the protected area start address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2)); +} +#endif /*SYSCFG_UR9_WRPN_BANK2*/ + +#ifdef SYSCFG_UR10_PAEND_BANK2 +/** + * @brief Get the protected area end address for Flash bank 2 + * @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress + * @retval Returned the protected area end address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2)); +} + +/** + * @brief Get the secured area start address for Flash bank 2 + * @rmtoll UR10 SABEG_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaStartAddress + * @retval Returned the secured area start address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2)); +} +#endif /*SYSCFG_UR10_PAEND_BANK2*/ + +#ifdef SYSCFG_UR11_SAEND_BANK2 +/** + * @brief Get the secured area end address for Flash bank 2 + * @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress + * @retval Returned the secured area end address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2)); +} +#endif /*SYSCFG_UR11_SAEND_BANK2*/ + +/** + * @brief Get the Independent Watchdog 1 control mode (Software or Hardware) + * @rmtoll UR11 IWDG1M LL_SYSCFG_GetIWDG1ControlMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE + * @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M)); +} + +#if defined (DUAL_CORE) +/** + * @brief Get the Independent Watchdog 2 control mode (Software or Hardware) + * @rmtoll UR12 IWDG2M LL_SYSCFG_GetIWDG2ControlMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE + * @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M)); +} +#endif /* DUAL_CORE */ + +/** + * @brief Indicates the Secure mode status + * @rmtoll UR12 SECURE LL_SYSCFG_IsSecureModeEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void) +{ + return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL); +} + +/** + * @brief Indicates if a reset is generated when D1 domain enters DStandby mode + * @rmtoll UR13 D1SBRST LL_SYSCFG_IsD1StandbyGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Get the secured DTCM RAM size + * @rmtoll UR13 SDRS LL_SYSCFG_GetSecuredDTCMSize + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS)); +} + +/** + * @brief Indicates if a reset is generated when D1 domain enters DStop mode + * @rmtoll UR14 D1STPRST LL_SYSCFG_IsD1StopGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Indicates if a reset is generated when D2 domain enters DStandby mode + * @rmtoll UR14 D2SBRST LL_SYSCFG_IsD2StandbyGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Indicates if a reset is generated when D2 domain enters DStop mode + * @rmtoll UR15 D2STPRST LL_SYSCFG_IsD2StopGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Indicates if the independent watchdog is frozen in Standby mode + * @rmtoll UR15 FZIWDGSTB LL_SYSCFG_IsIWDGFrozenInStandbyMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void) +{ + return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the independent watchdog is frozen in Stop mode + * @rmtoll UR16 FZIWDGSTP LL_SYSCFG_IsIWDGFrozenInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void) +{ + return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the device private key is programmed + * @rmtoll UR16 PKP LL_SYSCFG_IsPrivateKeyProgrammed + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void) +{ + return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the Product is working on the full voltage range or not + * @rmtoll UR17 IOHSLV LL_SYSCFG_IsActiveFlag_IOHSLV + * @note When the IOHSLV option bit is set the Product is working below 2.7 V. + * When the IOHSLV option bit is reset the Product is working on the + * full voltage range. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void) +{ + return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL); +} + +#ifdef SYSCFG_UR17_TCM_AXI_CFG +/** + * @brief Get the size of ITCM-RAM and AXI-SRAM + * @rmtoll UR17 TCM_AXI_CFG LL_SYSCFG_Get_ITCM_AXI_RAM_Size + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB + * @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB + * @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB + * @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB + */ +__STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG)); +} +#endif /*SYSCFG_UR17_TCM_AXI_CFG*/ + +#ifdef SYSCFG_UR18_CPU_FREQ_BOOST +/** + * @brief Indicates if the CPU maximum frequency boost is enabled + * @rmtoll UR18 CPU_FREQ_BOOST LL_SYSCFG_IsCpuFreqBoostEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void) +{ + return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL); +} +#endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/ + +#endif /*SYSCFG_UR0_RDP*/ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable D1 Domain/CDomain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + +/** + * @brief Disable D1 Domain/CDomain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + +/** + * @brief Enable D1 Domain/CDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Disable D1 Domain/CDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Enable D1 Domain/CDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +/** + * @brief Disable D1 Domain/CDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +#if defined (DUAL_CORE) +/** + * @brief Enable D2 Domain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_EnableD2DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Disable D2 Domain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_DisableD2DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Enable D2 Domain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_EnableD2DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Disable D2 Domain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_DisableD2DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Enable D2 Domain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_EnableD2DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} + +/** + * @brief Disable D2 Domain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_DisableD2DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} +#endif /* DUAL_CORE */ + + +#if defined(DBGMCU_CR_DBG_STOPD3) +/** + * @brief Enable D3 Domain/SRDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} + +/** + * @brief Disable D3 Domain/SRDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_DisableD3DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} +#endif /*DBGMCU_CR_DBG_STOPD3*/ + +#if defined(DBGMCU_CR_DBG_STANDBYD3) +/** + * @brief Enable D3 Domain/SRDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} + +/** + * @brief Disable D3 Domain/SRDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_DisableD3DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ + +/** + * @brief Enable the trace port clock + * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN); +} + +/** + * @brief Disable the trace port clock + * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN); +} + +/** + * @brief Enable the Domain1/CDomain debug clock enable + * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_EnableD1DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN); +} + +/** + * @brief Disable the Domain1/CDomain debug clock enable + * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_DisableD1DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN); +} + +/** + * @brief Enable the Domain3/SRDomain debug clock enable + * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_EnableD3DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN); +} + +/** + * @brief Disable the Domain3/SRDomain debug clock enable + * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_DisableD3DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN); +} + +#define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U +#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN +/** + * @brief Set the direction of the bi-directional trigger pin TRGIO + * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n + * @param PinDirection This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION + * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection); +} + +/** + * @brief Get the direction of the bi-directional trigger pin TRGIO + * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION + * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN)); +} + +/** + * @brief Freeze APB1 group1 peripherals + * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1LFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs); +} + +#ifdef DBGMCU_APB1HFZ1_DBG_FDCAN +/** + * @brief Freeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1HFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); +} +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ + +#if defined(TIM23) || defined(TIM24) +/** + * @brief Freeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1HFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); +} +#endif /* TIM23 || TIM24 */ + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph + * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ1, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph + * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ1, Periphs); +} + +/** + * @brief Freeze APB3 peripherals + * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB3FZ1, Periphs); +} + +/** + * @brief Unfreeze APB3 peripherals + * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB3FZ1, Periphs); +} + +/** + * @brief Freeze APB4 peripherals + * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB4FZ1, Periphs); +} + +/** + * @brief Unfreeze APB4 peripherals + * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB4FZ1, Periphs); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup SYSTEM_LL_EF_ART ART + * @{ + */ + +/** + * @brief Enable the Cortex-M4 ART cache. + * @rmtoll ART_CTR EN LL_ART_Enable + * @retval None + */ +__STATIC_INLINE void LL_ART_Enable(void) +{ + SET_BIT(ART->CTR, ART_CTR_EN); +} + +/** + * @brief Disable the Cortex-M4 ART cache. + * @rmtoll ART_CTR EN LL_ART_Disable + * @retval None + */ +__STATIC_INLINE void LL_ART_Disable(void) +{ + CLEAR_BIT(ART->CTR, ART_CTR_EN); +} + +/** + * @brief Check if the Cortex-M4 ART cache is enabled + * @rmtoll ART_CTR EN LL_ART_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ART_IsEnabled(void) +{ + return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL); +} + +/** + * @brief Set the Cortex-M4 ART cache Base Address. + * @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress + * @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page) + from which the ART accelerator loads code to the cache. + * @retval None + */ +__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress) +{ + MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL)); +} + +/** + * @brief Get the Cortex-M4 ART cache Base Address. + * @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress + * @retval the Base address of 1 Mbyte address page (cacheable page) + from which the ART accelerator loads code to the cache + */ +__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void) +{ + return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_SYSTEM_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h new file mode 100644 index 0000000..41a5aa4 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h @@ -0,0 +1,401 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_UTILS_H +#define STM32H7xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include "stm32h7xx_ll_system.h" +#include "stm32h7xx_ll_bus.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetM(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetN(). */ + + uint32_t PLLP; /*!< Division for the main system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetP(). */ + + uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO. + This parameter can be a value between 0 and 8191 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetFRACN(). */ + + uint32_t VCO_Input; /*!< PLL clock Input range. + This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetVCOInputRange(). */ + + uint32_t VCO_Output; /*!< PLL clock Output range. + This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetVCOOutputRange(). */ + +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output. + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetSysPrescaler(). */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_AHB_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + + uint32_t APB3CLKDivider; /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB3_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB3Prescaler(). */ + + uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB4_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB4Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define LL_UTILS_PACKAGETYPE_LQFP100 LL_SYSCFG_LQFP100_PACKAGE /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_TQFP144 LL_SYSCFG_TQFP144_PACKAGE /*!< TQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL /*!< TFBGA100 or LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL /*!< LQFP100 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS 0x00000003UL /*!< TFBGA100 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS 0x00000004UL /*!< WLCSP132 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL /*!< LQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL /*!< LQFP144 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL /*!< UFBGA169 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000008UL /*!< UFBGA176 or LQFP176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000009UL /*!< LQFP176 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL /*!< UFBGA176 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL /*!< TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL /*!< TFBGA225 package type */ +#elif (STM32H7_DEV_ID == 0x483UL) +#define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS LL_SYSCFG_VFQFPN68_INDUS_PACKAGE /*!< VFQFPN68 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 LL_SYSCFG_TFBGA100_LQFP100_PACKAGE /*!< TFBGA100 or LQFP100 Legacy package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_INDUS LL_SYSCFG_LQFP100_INDUS_PACKAGE /*!< LQFP100 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS LL_SYSCFG_TFBGA100_INDUS_PACKAGE /*!< TFBGA100 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS LL_SYSCFG_WLCSP115_INDUS_PACKAGE /*!< WLCSP115 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 LL_SYSCFG_LQFP144_PACKAGE /*!< LQFP144 Legacy package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144 LL_SYSCFG_UFBGA144_PACKAGE /*!< UFBGA144 Legacy package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_INDUS LL_SYSCFG_LQFP144_INDUS_PACKAGE /*!< LQFP144 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS LL_SYSCFG_UFBGA169_INDUS_PACKAGE /*!< UFBGA169 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE /*!< UFBGA176+25 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_INDUS LL_SYSCFG_LQFP176_INDUS_PACKAGE /*!< LQFP176 Industrial package type */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 + * @arg @ref LL_UTILS_PACKAGETYPE_TQFP144 + * @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP115_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176+25_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_INDUS (*) + * + * (*) Packages available on some STM32H7 lines only. + * @note For some SM32H7 lines, enabling the SYSCFG clock is mandatory. + the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ +#if defined(SYSCFG_PKGR_PKG) + + return LL_SYSCFG_GetPackage(); +#else + return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS))); + +#endif /* SYSCFG_PKGR_PKG */ +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Frequency of Ticks (Hz) + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t CPU_Frequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t CPU_Frequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, + uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_UTILS_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt b/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt new file mode 100644 index 0000000..3edc4d1 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c new file mode 100644 index 0000000..7bb55a1 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c @@ -0,0 +1,1312 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** + * @brief STM32H7xx HAL Driver version number + */ +#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */ +#define __STM32H7xx_HAL_VERSION_SUB2 (0x05UL) /*!< [15:8] sub2 version */ +#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ +#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ + |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32H7xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32h7xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + +uint32_t common_system_clock; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure Cortex-M4 Instruction cache through ART accelerator */ + __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */ + __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ + __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Update the SystemCoreClock global variable */ +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB4_FORCE_RESET(); + __HAL_RCC_AHB4_RELEASE_RESET(); + + __HAL_RCC_APB3_FORCE_RESET(); + __HAL_RCC_APB3_RELEASE_RESET(); + + __HAL_RCC_APB1L_FORCE_RESET(); + __HAL_RCC_APB1L_RELEASE_RESET(); + + __HAL_RCC_APB1H_FORCE_RESET(); + __HAL_RCC_APB1H_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_APB4_FORCE_RESET(); + __HAL_RCC_APB4_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * the SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if((uint32_t)uwTickFreq == 0UL) + { + return HAL_ERROR; + } + + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup HAL_Group2 + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32H7xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Configure the internal voltage reference buffer voltage scale. + * @param VoltageScaling specifies the output voltage to achieve + * This parameter can be one of the following values: + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.5 V. + * This requires VDDA equal to or higher than 2.8 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.048 V. + * This requires VDDA equal to or higher than 2.4 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.8 V. + * This requires VDDA equal to or higher than 2.1 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.5 V. + * This requires VDDA equal to or higher than 1.8 V. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); +} + +/** + * @brief Configure the internal voltage reference buffer high impedance mode. + * @param Mode specifies the high impedance mode + * This parameter can be one of the following values: + * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. + * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); +} + +/** + * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @retval None + */ +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); +} + +/** + * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + * @retval HAL_OK/HAL_TIMEOUT + */ +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) +{ + uint32_t tickstart; + + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for VRR bit */ + while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL) + { + if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + * + * @retval None + */ +void HAL_SYSCFG_DisableVREFBUF(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +#if defined(SYSCFG_PMCR_EPIS_SEL) +/** + * @brief Ethernet PHY Interface Selection either MII or RMII + * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface + * This parameter can be one of the following values: + * @arg SYSCFG_ETH_MII : Select the Media Independent Interface + * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface + * @retval None + */ +void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface)); + + MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface)); +} +#endif /* SYSCFG_PMCR_EPIS_SEL */ + +/** + * @brief Analog Switch control for dual analog pads. + * @param SYSCFG_AnalogSwitch: Selects the analog pad + * This parameter can be one or a combination of the following values: + * @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch + * @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch + * @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch + * @arg SYSCFG_SWITCH_PC3: Select PC3 analog switch + * @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C) + * This parameter can be one or a combination of the following values: + * @arg SYSCFG_SWITCH_PA0_OPEN + * @arg SYSCFG_SWITCH_PA0_CLOSE + * @arg SYSCFG_SWITCH_PA1_OPEN + * @arg SYSCFG_SWITCH_PA1_CLOSE + * @arg SYSCFG_SWITCH_PC2_OPEN + * @arg SYSCFG_SWITCH_PC2_CLOSE + * @arg SYSCFG_SWITCH_PC3_OPEN + * @arg SYSCFG_SWITCH_PC3_CLOSE + * @retval None + */ + +void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); + assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); + + MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); +} + +#if defined(SYSCFG_PMCR_BOOSTEN) +/** + * @brief Enables the booster to reduce the total harmonic distortion of the analog + * switch when the supply voltage is lower than 2.7 V. + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +void HAL_SYSCFG_EnableBOOST(void) +{ + SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} + +/** + * @brief Disables the booster + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +void HAL_SYSCFG_DisableBOOST(void) +{ + CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} +#endif /* SYSCFG_PMCR_BOOSTEN */ + +#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0) +/** + * @brief BootCM7 address 0 configuration + * @param BootRegister :Specifies the Boot Address register (Address0 or Address1) + * This parameter can be one of the following values: + * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0 + * @arg SYSCFG_BOOT_ADDR1: Select the boot address1 + * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1 + * @retval None + */ +void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister)); + assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress)); + if ( BootRegister == SYSCFG_BOOT_ADDR0 ) + { + /* Configure CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos)); +#else + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos)); +#endif /*DUAL_CORE*/ + } + else + { + /* Configure CM7 BOOT ADD1 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16)); +#else + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16)); +#endif /*DUAL_CORE*/ + } +} +#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */ + +#if defined(DUAL_CORE) +/** + * @brief BootCM4 address 0 configuration + * @param BootRegister :Specifies the Boot Address register (Address0 or Address1) + * This parameter can be one of the following values: + * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0 + * @arg SYSCFG_BOOT_ADDR1: Select the boot address1 + * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1 + * @retval None + */ +void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister)); + assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress)); + + if ( BootRegister == SYSCFG_BOOT_ADDR0 ) + { + /* Configure CM4 BOOT ADD0 */ + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos)); + } + + else + { + /* Configure CM4 BOOT ADD1 */ + MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16)); + } +} + +/** + * @brief Enables the Cortex-M7 boot + * @retval None + */ +void HAL_SYSCFG_EnableCM7BOOT(void) +{ + SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7); +} + +/** + * @brief Disables the Cortex-M7 boot + * @note Disabling the boot will gate the CPU clock + * @retval None + */ +void HAL_SYSCFG_DisableCM7BOOT(void) +{ + CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ; +} + +/** + * @brief Enables the Cortex-M4 boot + * @retval None + */ +void HAL_SYSCFG_EnableCM4BOOT(void) +{ + SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4); +} + +/** + * @brief Disables the Cortex-M4 boot + * @note Disabling the boot will gate the CPU clock + * @retval None + */ +void HAL_SYSCFG_DisableCM4BOOT(void) +{ + CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4); +} +#endif /*DUAL_CORE*/ +/** + * @brief Enables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +void HAL_EnableCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ; +} + +/** + * @brief Power-down the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +void HAL_DisableCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); +} + + +/** + * @brief To Enable optimize the I/O speed when the product voltage is low. + * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be + * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is + * higher than 2.5 V might be destructive. + * @retval None + */ +void HAL_SYSCFG_EnableIOSpeedOptimize(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3)); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be + * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is + * higher than 2.5 V might be destructive. + * @retval None + */ +void HAL_SYSCFG_DisableIOSpeedOptimize(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3)); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +/** + * @brief Code selection for the I/O Compensation cell + * @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode)); + MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode)); +} + +/** + * @brief Code selection for the I/O Compensation cell + * @param SYSCFG_PMOSCode: PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @param SYSCFG_NMOSCode: NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode ) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode)); + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode)); + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) ); +} + +#if defined(SYSCFG_CCCR_NCC_MMC) +/** + * @brief Code selection for the I/O Compensation cell + * @param SYSCFG_PMOSCode: VDDMMC PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @param SYSCFG_NMOSCode: VDDMMC NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode ) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode)); + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode)); + MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) ); +} +#endif /* SYSCFG_CCCR_NCC_MMC */ + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) +/** @brief SYSCFG ADC2 internal input alternate connection macros + * @param Adc2AltRout0 This parameter can be a value of : + * @arg @ref SYSCFG_ADC2_ROUT0_DAC1_1 DAC1_out1 connected to ADC2 VINP[16] + * @arg @ref SYSCFG_ADC2_ROUT0_VBAT4 VBAT/4 connected to ADC2 VINP[16] + */ +void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_ADC2ALT_ROUT0(Adc2AltRout0)); + + MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0); +} +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +/** @brief SYSCFG ADC2 internal input alternate connection macros + * @param Adc2AltRout1 This parameter can be a value of : + * @arg @ref SYSCFG_ADC2_ROUT1_DAC1_2 DAC1_out2 connected to ADC2 VINP[17] + * @arg @ref SYSCFG_ADC2_ROUT1_VREFINT VREFINT connected to ADC2 VINP[17] + */ +void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_ADC2ALT_ROUT1(Adc2AltRout1)); + + MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1); +} +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ + +/** + * @brief Enable the Debug Module during Domain1/CDomain SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + +/** + * @brief Disable the Debug Module during Domain1/CDomain SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + + +/** + * @brief Enable the Debug Module during Domain1/CDomain STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Disable the Debug Module during Domain1/CDomain STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Enable the Debug Module during Domain1/CDomain STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +/** + * @brief Disable the Debug Module during Domain1/CDomain STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable the Debug Module during Domain1 SLEEP mode + * @retval None + */ +void HAL_EnableDomain2DBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Disable the Debug Module during Domain2 SLEEP mode + * @retval None + */ +void HAL_DisableDomain2DBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Enable the Debug Module during Domain2 STOP mode + * @retval None + */ +void HAL_EnableDomain2DBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Disable the Debug Module during Domain2 STOP mode + * @retval None + */ +void HAL_DisableDomain2DBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Enable the Debug Module during Domain2 STANDBY mode + * @retval None + */ +void HAL_EnableDomain2DBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} + +/** + * @brief Disable the Debug Module during Domain2 STANDBY mode + * @retval None + */ +void HAL_DisableDomain2DBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} +#endif /*DUAL_CORE*/ + +#if defined(DBGMCU_CR_DBG_STOPD3) +/** + * @brief Enable the Debug Module during Domain3/SRDomain STOP mode + * @retval None + */ +void HAL_EnableDomain3DBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} + +/** + * @brief Disable the Debug Module during Domain3/SRDomain STOP mode + * @retval None + */ +void HAL_DisableDomain3DBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} +#endif /*DBGMCU_CR_DBG_STOPD3*/ + +#if defined(DBGMCU_CR_DBG_STANDBYD3) +/** + * @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode + * @retval None + */ +void HAL_EnableDomain3DBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} + +/** + * @brief Disable the Debug Module during Domain3/SRDomain STANDBY mode + * @retval None + */ +void HAL_DisableDomain3DBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ + +/** + * @brief Set the FMC Memory Mapping Swapping config. + * @param BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be + FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2 + * @retval HAL state + */ +void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig) +{ + /* Check the parameter */ + assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig)); + MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig); +} + +/** + * @brief Get FMC Bank mapping mode. + * @retval The FMC Bank mapping mode. This parameter can be + FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2 +*/ +uint32_t HAL_GetFMCMemorySwappingConfig(void) +{ + return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP); +} + +/** + * @brief Configure the EXTI input event line edge + * @note No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21), + * EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86. + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @param EXTI_Edge: Specifies EXTI line Edge used. + * This parameter can be one of the following values : + * @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection + * @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection + * @retval None + */ +void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge ) +{ + /* Check the parameter */ + assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line)); + assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge)); + + /* Clear Rising Falling edge configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + + if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE) + { + SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE) + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } +} + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86. + * @retval None + */ +void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line)); + + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); +} + + +/** + * @brief Clears the EXTI's line pending flags for Domain D1 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @retval None + */ +void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_D1_LINE(EXTI_Line)); + WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + +} + +#if defined(DUAL_CORE) +/** + * @brief Clears the EXTI's line pending flags for Domain D2 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @retval None + */ +void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_D2_LINE(EXTI_Line)); + WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); +} + +#endif /*DUAL_CORE*/ +/** + * @brief Configure the EXTI input event line for Domain D1 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event. + * This parameter can be one or a combination of the following values : + * @arg EXTI_MODE_IT : Interrupt Mode selected + * @arg EXTI_MODE_EVT : Event Mode selected + * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. + + * @retval None + */ +void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd ) +{ + /* Check the parameter */ + assert_param(IS_EXTI_D1_LINE(EXTI_Line)); + assert_param(IS_EXTI_MODE_LINE(EXTI_Mode)); + + if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) ); + } + else + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } + + if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + else + { + SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } +} + +#if defined(DUAL_CORE) +/** + * @brief Configure the EXTI input event line for Domain D2 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event. + * This parameter can be one or a combination of the following values : + * @arg EXTI_MODE_IT : Interrupt Mode selected + * @arg EXTI_MODE_EVT : Event Mode selected + * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. + + * @retval None + */ +void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd ) +{ + /* Check the parameter */ + assert_param(IS_EXTI_D2_LINE(EXTI_Line)); + assert_param(IS_EXTI_MODE_LINE(EXTI_Mode)); + + if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) ); + } + else + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } + + if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + else + { + SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } +} +#endif /*DUAL_CORE*/ + +/** + * @brief Configure the EXTI input event line for Domain D3 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34, + * EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53) + * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. + * @param EXTI_ClearSrc: Specifies the clear source of D3 pending event. + * This parameter can be one of the following values : + * @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source + * @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source + * @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source + * @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source + * @retval None + */ +void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc ) +{ + __IO uint32_t *pRegv; + + /* Check the parameter */ + assert_param(IS_EXTI_D3_LINE(EXTI_Line)); + assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc)); + + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) ); + } + else + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + + if(((EXTI_Line>>4)%2UL) == 0UL) + { + pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL)); + } + else + { + pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL)); + } + MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL))); + +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c new file mode 100644 index 0000000..5c158d5 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c @@ -0,0 +1,558 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined + inside the stm32h7xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ +#if (__MPU_PRESENT == 1) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +/** + * @brief Enables the MPU + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Enables the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disables the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval status - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval status - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +#if defined(DUAL_CORE) + +/** + * @brief Returns the current CPU ID. + * @retval CPU identifier + */ +uint32_t HAL_GetCurrentCPUID(void) +{ + if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U) + { + return CM7_CPUID; + } + else + { + return CM4_CPUID; + } +} + +#else + +/** +* @brief Returns the current CPU ID. +* @retval CPU identifier +*/ +uint32_t HAL_GetCurrentCPUID(void) +{ + return CM7_CPUID; +} + +#endif /*DUAL_CORE*/ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c new file mode 100644 index 0000000..8714741 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c @@ -0,0 +1,2062 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests . + + (#) For a given Stream, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + [..] + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + Half-Word data size for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two half words will be packed and written in + a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + and Destination. In this case the Peripheral Data Size will be applied to both Source + and Destination. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/** @addtogroup DMA_Private_Types + * @{ + */ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + +typedef struct +{ + __IO uint32_t ISR; /*!< BDMA interrupt status register */ + __IO uint32_t IFCR; /*!< BDMA interrupt flag clear register */ +} BDMA_Base_Registers; +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Constants + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */ + +#define BDMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ +#define BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction */ + +/* DMA to BDMA conversion */ +#define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \ + ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \ + BDMA_PERIPH_TO_MEMORY) + +#define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U) +#define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U) + +#define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U) +#define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U) + +#define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U) + +#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U) + +#if defined(UART9) +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX ))) +#else +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX ))) + +#endif +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Stream source + and destination incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + The HAL_DMA_DeInit function allows to deinitialize the DMA stream. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t registerValue; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Get the CR register value */ + registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + registerValue |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be + lock when transferring data to/from USART/UART */ +#if (STM32H7_DEV_ID == 0x450UL) + if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) + { +#endif /* STM32H7_DEV_ID == 0x450UL */ + if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) + { + registerValue |= DMA_SxCR_TRBUFF; + } +#if (STM32H7_DEV_ID == 0x450UL) + } +#endif /* STM32H7_DEV_ID == 0x450UL */ + + /* Write to DMA Stream CR register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; + + /* Get the FCR register value */ + registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + registerValue |= hdma->Init.FIFOMode; + + /* the FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + registerValue |= hdma->Init.FIFOThreshold; + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 */ + if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + } + + /* Write to DMA Stream FCR */ + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* Check the request parameter */ + assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Get the CR register value */ + registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ + registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ + BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ + BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ + BDMA_CCR_CT)); + + /* Prepare the DMA Channel configuration */ + registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | + DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | + DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | + DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | + DMA_TO_BDMA_MODE(hdma->Init.Mode) | + DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); + + /* Write to DMA Channel CR register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; + + /* calculation of the channel index */ + hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + else + { + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Initialize parameters for DMAMUX request generator : + if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 + */ + if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register */ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Reset DMA Streamx control register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR = 0U; + + /* Reset DMA Streamx number of data to transfer register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = 0U; + + /* Reset DMA Streamx peripheral address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = 0U; + + /* Reset DMA Streamx memory 0 address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = 0U; + + /* Reset DMA Streamx memory 1 address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = 0U; + + /* Reset DMA Streamx FIFO control register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U; + + /* Get DMA steam Base Address */ + regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + /* Reset DMA Channel control register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = 0U; + + /* Reset DMA Channel memory 0 address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U; + + /* Reset DMA Channel memory 1 address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U; + + /* Get DMA steam Base Address */ + regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + else + { + /* Return error status */ + return HAL_ERROR; + } + +#if defined (BDMA1) /* No DMAMUX available for BDMA1 available on STM32H7Ax/Bx devices only */ + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ +#endif /* BDMA1 */ + { + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if(hdma->DMAmuxChannel != 0U) + { + /* Resett he DMAMUX channel that corresponds to the DMA stream */ + hdma->DMAmuxChannel->CCR = 0U; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + } + + if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register */ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Register and Unregister DMA callbacks + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable Common interrupts*/ + MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Enable Half Transfer IT if corresponding Callback is set */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; + } + } + else /* BDMA channel */ + { + /* Enable Common interrupts */ + MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); + + if(hdma->XferHalfCpltCallback != NULL) + { + /*Enable Half Transfer IT if corresponding Callback is set */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check if DMAMUX Synchronization is enabled */ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + const __IO uint32_t *enableRegister; + + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Disable DMA All Interrupts */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + + enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); + } + else /* BDMA channel */ + { + /* Disable DMA All Interrupts */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); + + enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* disable the DMAMUX sync overrun IT */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while(((*enableRegister) & DMA_SxCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ + /* disable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } + else /* BDMA channel */ + { + /* Disable DMA All Interrupts */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* disable the DMAMUX sync overrun IT */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear all flags */ + regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CompleteLevel: Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t cpltlevel_mask; + uint32_t tickstart = HAL_GetTick(); + + /* IT status register */ + __IO uint32_t *isr_reg; + /* IT clear flag register */ + __IO uint32_t *ifcr_reg; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Polling mode not supported in circular mode and double buffering mode */ + if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); + } + else + { + /* Half Transfer Complete flag */ + cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); + ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + } + else /* BDMA channel */ + { + /* Polling mode not supported in circular mode */ + if ((((BDMA_Channel_TypeDef *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU); + } + else + { + /* Half Transfer Complete flag */ + cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU); + } + + isr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); + ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + } + + while(((*isr_reg) & cpltlevel_mask) == 0U) + { + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + else /* BDMA channel */ + { + if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU)); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Check for the Timeout (Not applicable in circular mode)*/ + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* if timeout then abort the current transfer */ + /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code */ + (void) HAL_DMA_Abort(hdma); + /* + Note that the Abort function will + - Clear the transfer error flags + - Unlock + - Set the State + */ + + return HAL_ERROR; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check for DMAMUX Request generator (if used) overrun status */ + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + } + } + } + + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU)); + } + + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/ + { + /* Clear the half transfer and transfer complete flags */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU)); + } + } + + return status; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t tmpisr_dma, tmpisr_bdma; + uint32_t ccr_reg; + __IO uint32_t count = 0U; + uint32_t timeout = SystemCoreClock / 9600U; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr_dma = regs_dma->ISR; + tmpisr_bdma = regs_bdma->ISR; + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) + { + /* Disable the transfer error interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); + + /* Clear the transfer error flag */ + regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) + { + /* Clear the FIFO error flag */ + regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) + { + /* Clear the direct mode error flag */ + regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) + { + /* Clear the half transfer complete flag */ + regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Multi_Buffering mode enabled */ + if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) + { + /* Clear the transfer complete flag */ + regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); + + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) + { + /* Disable the transfer complete interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); + + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) + { + /* Change the DMA state to error if DMA disable fails */ + hdma->State = HAL_DMA_STATE_ERROR; + } + else + { + /* Change the DMA state to Ready if DMA disable success */ + hdma->State = HAL_DMA_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); + + /* Half Transfer Complete Interrupt management ******************************/ + if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) + { + /* Clear the half transfer complete flag */ + regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); + + /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ + if((ccr_reg & BDMA_CCR_DBM) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((ccr_reg & BDMA_CCR_CT) == 0U) + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer Callback for Memory 1 */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer Callback for Memory 0 */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + else + { + if((ccr_reg & BDMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) + { + /* Clear the transfer complete flag */ + regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); + + /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ + if((ccr_reg & BDMA_CCR_DBM) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((ccr_reg & BDMA_CCR_CT) == 0U) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for Memory 1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for Memory 0 */ + hdma->XferCpltCallback(hdma); + } + } + } + else + { + if((ccr_reg & BDMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Transfer Error Interrupt management **************************************/ + else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ + regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + else + { + /* Nothing To Do */ + } + } + else + { + /* Nothing To Do */ + } +} + +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifier + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback: pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval None + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + + /* Clear DBM bit */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; + + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; + } + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + /* Clear all flags */ + regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + + /* Configure DMA Channel data length */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Channel source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; + } + } + else + { + /* Nothing To Do */ + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); + } + } + else /* BDMA instance(s) */ + { + /* return pointer to ISR and IFCR */ + hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Memory Data size equal to Byte */ + if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_FULL: + break; + + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + default: + break; + } + } + + return status; +} + +/** + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number; + uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); + + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* BDMA Channels are connected to DMAMUX2 channels */ + stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); + hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + } + else + { + /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */ + stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; + + if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ + (stream_baseaddress >= ((uint32_t)DMA2_Stream0))) + { + stream_number += 8U; + } + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + } +} + +/** + * @brief Updates the DMA handle with the DMAMUX request generator params + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + + if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) + { + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* BDMA Channels are connected to DMAMUX2 request generator blocks */ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; + } + else + { + /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + } + + hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c new file mode 100644 index 0000000..a134b4e --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c @@ -0,0 +1,712 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function + for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. + + (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + + (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler . + As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be + called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project + (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) + + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + -@- Multi (Double) buffer mode is possible with DMA and BDMA instances. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer with interrupt + (+) Change on the fly the memory0 or memory1 address. + (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler + +@endverbatim + * @{ + */ + + +/** + * @brief Starts the multi_buffer DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + } + else + { + /* Process Locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable the Double buffer mode */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U)); + + /* Clear all flags */ + *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA instance(s) */ + { + /* Enable the Double buffer mode */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC); + + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U)); + + /* Clear all flags */ + *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable the Double buffer mode */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U)); + + /* Clear all flags */ + *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA instance(s) */ + { + /* Enable the Double buffer mode */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC); + + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U)); + + /* Clear all flags */ + *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + } + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable Common interrupts*/ + MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE; + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + /*Enable Half Transfer IT if corresponding Callback is set*/ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; + } + } + else /* BDMA instance(s) */ + { + /* Enable Common interrupts*/ + MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + /*Enable Half Transfer IT if corresponding Callback is set*/ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check if DMAMUX Synchronization is enabled*/ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Change the memory0 or memory1 address on the fly. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param Address: The new address + * @param memory: the memory to be changed, This parameter can be one of + * the following values: + * MEMORY0 / + * MEMORY1 + * @note The MEMORY0 address can be changed only when the current transfer use + * MEMORY1 and the MEMORY1 address can be changed only when the current + * transfer use MEMORY0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) +{ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + if(memory == MEMORY0) + { + /* change the memory0 address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address; + } + else + { + /* change the memory1 address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address; + } + } + else /* BDMA instance(s) */ + { + if(memory == MEMORY0) + { + /* change the memory0 address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address; + } + else + { + /* change the memory1 address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address; + } + } + + return HAL_OK; +} + +/** + * @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) +{ + uint32_t syncSignalID = 0; + uint32_t syncPolarity = 0; + + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + + if(pSyncConfig->SyncEnable == ENABLE) + { + assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity)); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + } + else + { + assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + } + syncSignalID = pSyncConfig->SyncSignalID; + syncPolarity = pSyncConfig->SyncPolarity; + } + + /*Check if the DMA state is ready */ + if(hdma->State == HAL_DMA_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Disable the synchronization and event generation before applying a new config */ + CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE)); + + /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + MODIFY_REG( hdma->DMAmuxChannel->CCR, \ + (~DMAMUX_CxCR_DMAREQ_ID) , \ + (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \ + ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ + syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); + + /* Process Locked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMAMUX request generator block used by the given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : + * contains the request generator parameters. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) +{ + HAL_StatusTypeDef status; + HAL_DMA_StateTypeDef temp_state = hdma->State; + + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + } + else + { + assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + } + + + assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if(hdma->DMAmuxRequestGen == 0U) + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* error status */ + status = HAL_ERROR; + } + else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY)) + { + /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */ + + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the request generator new parameters */ + hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \ + pRequestGeneratorConfig->Polarity; + /* Process Locked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Enable the DMAMUX request generator block used by the given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U)) + { + /* Enable the request generator*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the DMAMUX request generator block used by the given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U)) + { + /* Disable the request generator*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handles DMAMUX interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Disable the synchro overrun interrupt */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + + if(hdma->DMAmuxRequestGen != 0) + { + /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Configure DMA Stream data length */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; + + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; + } + } + else /* BDMA instance(s) */ + { + /* Configure DMA Stream data length */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; + + /* Configure DMA Stream source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; + + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; + } + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c new file mode 100644 index 0000000..07825da --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c @@ -0,0 +1,865 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt (CORE1 or CORE2 in case of dual core line ) + (++) Event (CORE1 or CORE2 in case of dual core line ) + (++) a combination of the previous + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two diffenrents + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear source. + It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain). + Value can be one of the following: + (++) EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 0 + (+++) On a configurable Line : the D3 domain wakeup signal is + automatically cleared after after the Delay + Rising Edge detect + (+++) On a direct Line : the D3 domain wakeup signal is + cleared after the direct event input signal is cleared + + (++) EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b00 : + DMA ch6 event selected as D3 domain pendclear source + + (++) EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b01 : + DMA ch7 event selected as D3 domain pendclear source + + (++) EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b10 : + LPTIM4 out selected as D3 domain pendclear source + + (++) EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b11 : + LPTIM5 out selected as D3 domain pendclear source + + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + (++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain), + choose gpio D3 PendClearSource using PendClearSource + member from EXTI_PendClear_Source structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04U /* 0x10: offset between CPU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between CPU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t pcrlinepos; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* The event mode cannot be configured if the line does not support it */ + assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT)); + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + +#if defined (DUAL_CORE) + /* Configure interrupt mode for Core2 : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* The event mode cannot be configured if the line does not support it */ + assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT)); + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; +#endif /* DUAL_CORE */ + + /* Configure the D3 PendClear source in case of Wakeup target is Any */ + if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + { + assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource)); + + /*Calc the PMR register address for the given line */ + regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE) + { + /* Clear D3PMRx register for the given line */ + regval &= ~maskline; + /* Store D3PMRx register value */ + *regaddr = regval; + } + else + { + /* Set D3PMRx register to 1 for the given line */ + regval |= maskline; + /* Store D3PMRx register value */ + *regaddr = regval; + + if(linepos < 16UL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << linepos; + } + else + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << (linepos - 16UL); + } + + regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiConfig->PendClearSource - 1UL)); + *regaddr = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t pcrlinepos; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + pExtiConfig->Mode = EXTI_MODE_NONE; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } +#if defined (DUAL_CORE) + regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT; + } +#endif /*DUAL_CORE*/ + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00U; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; + } + } + + /* Get default Pend Clear Source */ + pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE; + + /* 3] Get D3 Pend Clear source */ + if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + if(((*regaddr) & linepos) != 0UL) + { + /* if wakeup target is any and PMR set, the read pend clear source from D3PCRxL/H */ + if(linepos < 16UL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << linepos; + } + else + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << (linepos - 16UL); + } + + pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos)); + } + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t pcrlinepos; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + +#if defined (DUAL_CORE) + /* 1] Clear CM4 interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear CM4 event mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; +#endif /* DUAL_CORE */ + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL))); + SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* 4] Clear D3 Config lines */ + if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = (*regaddr & ~maskline); + + if(linepos < 16UL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << linepos; + } + else + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << (linepos - 16UL); + } + + /*Clear D3 PendClear source */ + *regaddr &= (~(pcrlinepos * pcrlinepos * 3UL)); + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + } + else /* Cortex-M4*/ + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + } +#else + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE */ + + /* Get pending bit */ + regval = (*regaddr & maskline); + + if (regval != 0x00U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Edge); + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + } + else /* Cortex-M4 */ + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + } +#else + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE */ + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Edge); + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + } + else /* Cortex-M4 */ + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + } +#else + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE */ + + /* Clear Pending bit */ + *regaddr = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c new file mode 100644 index 0000000..a0a86f1 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c @@ -0,0 +1,6257 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_fdcan.c + * @author MCD Application Team + * @brief FDCAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Flexible DataRate Controller Area Network + * (FDCAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Configuration and Control functions + * + Peripheral State and Error functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function. + + (#) If needed , configure the reception filters and optional features using + the following configuration functions: + (++) HAL_FDCAN_ConfigClockCalibration + (++) HAL_FDCAN_ConfigFilter + (++) HAL_FDCAN_ConfigGlobalFilter + (++) HAL_FDCAN_ConfigExtendedIdMask + (++) HAL_FDCAN_ConfigRxFifoOverwrite + (++) HAL_FDCAN_ConfigFifoWatermark + (++) HAL_FDCAN_ConfigRamWatchdog + (++) HAL_FDCAN_ConfigTimestampCounter + (++) HAL_FDCAN_EnableTimestampCounter + (++) HAL_FDCAN_DisableTimestampCounter + (++) HAL_FDCAN_ConfigTimeoutCounter + (++) HAL_FDCAN_EnableTimeoutCounter + (++) HAL_FDCAN_DisableTimeoutCounter + (++) HAL_FDCAN_ConfigTxDelayCompensation + (++) HAL_FDCAN_EnableTxDelayCompensation + (++) HAL_FDCAN_DisableTxDelayCompensation + (++) HAL_FDCAN_EnableISOMode + (++) HAL_FDCAN_DisableISOMode + (++) HAL_FDCAN_EnableEdgeFiltering + (++) HAL_FDCAN_DisableEdgeFiltering + (++) HAL_FDCAN_TT_ConfigOperation + (++) HAL_FDCAN_TT_ConfigReferenceMessage + (++) HAL_FDCAN_TT_ConfigTrigger + + (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level + the node is active on the bus: it can send and receive messages. + + (#) The following Tx control functions can only be called when the FDCAN + module is started: + (++) HAL_FDCAN_AddMessageToTxFifoQ + (++) HAL_FDCAN_EnableTxBufferRequest + (++) HAL_FDCAN_AbortTxRequest + + (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to + get Tx buffer location used to place the Tx request thanks to + HAL_FDCAN_GetLatestTxFifoQRequestBuffer API. + It is then possible to abort later on the corresponding Tx Request using + HAL_FDCAN_AbortTxRequest API. + + (#) When a message is received into the FDCAN message RAM, it can be + retrieved using the HAL_FDCAN_GetRxMessage function. + + (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering + it to initialization mode and re-enabling access to configuration + registers through the configuration functions listed here above. + + (#) All other control functions can be called any time after initialization + phase, no matter if the FDCAN module is started or stopped. + + *** Polling mode operation *** + ============================== + [..] + (#) Reception and transmission states can be monitored via the following + functions: + (++) HAL_FDCAN_IsRxBufferMessageAvailable + (++) HAL_FDCAN_IsTxBufferMessagePending + (++) HAL_FDCAN_GetRxFifoFillLevel + (++) HAL_FDCAN_GetTxFifoFreeLevel + + *** Interrupt mode operation *** + ================================ + [..] + (#) There are two interrupt lines: line 0 and 1. + By default, all interrupts are assigned to line 0. Interrupt lines + can be configured using HAL_FDCAN_ConfigInterruptLines function. + + (#) Notifications are activated using HAL_FDCAN_ActivateNotification + function. Then, the process can be controlled through one of the + available user callbacks: HAL_FDCAN_xxxCallback. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback() + to register an interrupt callback. + + Function HAL_FDCAN_RegisterCallback() allows to register following callbacks: + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) RxBufferNewMessageCallback : Rx Buffer New Message Callback. + (+) HighPriorityMessageCallback : High Priority Message Callback. + (+) TimestampWraparoundCallback : Timestamp Wraparound Callback. + (+) TimeoutOccurredCallback : Timeout Occurred Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : FDCAN MspInit. + (+) MspDeInitCallback : FDCAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, + TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback, + TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks: + respectively HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), + HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), + HAL_FDCAN_RegisterTxBufferCompleCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), + HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_TT_RegisterScheduleSyncCallback(), + HAL_FDCAN_TT_RegisterTimeMarkCallback(), HAL_FDCAN_TT_RegisterStopWatchCallback() and + HAL_FDCAN_TT_RegisterGlobalTimeCallback(). + + Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) RxBufferNewMessageCallback : Rx Buffer New Message Callback. + (+) HighPriorityMessageCallback : High Priority Message Callback. + (+) TimestampWraparoundCallback : Timestamp Wraparound Callback. + (+) TimeoutOccurredCallback : Timeout Occurred Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : FDCAN MspInit. + (+) MspDeInitCallback : FDCAN MspDeInit. + + For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, + RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback, + TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated + register callbacks: respectively HAL_FDCAN_UnRegisterClockCalibrationCallback(), + HAL_FDCAN_UnRegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), + HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferCompleCallback(), + HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), + HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), HAL_FDCAN_TT_UnRegisterTimeMarkCallback(), + HAL_FDCAN_TT_UnRegisterStopWatchCallback() and HAL_FDCAN_TT_UnRegisterGlobalTimeCallback(). + + By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + examples HAL_FDCAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit() + or HAL_FDCAN_Init() function. + + When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +#if defined(FDCAN1) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup FDCAN FDCAN + * @brief FDCAN HAL module driver + * @{ + */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FDCAN_Private_Constants + * @{ + */ +#define FDCAN_TIMEOUT_VALUE 10U +#define FDCAN_TIMEOUT_COUNT 50U + +#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN) +#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N) +#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N) +#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA) +#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO) +#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG) +#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI) +#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD) +#define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \ + FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC) +#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER) + +#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */ +#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */ +#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */ +#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */ +#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */ +#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */ +#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */ +#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */ +#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */ +#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */ +#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */ +#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */ +#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */ +#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */ + +#define FDCAN_MESSAGE_RAM_SIZE 0x2800U +#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* Message RAM width is 4 Bytes */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FDCAN_Private_Variables + * @{ + */ +static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FDCAN_Private_Functions_Prototypes + * @{ + */ +static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan); +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions + * @{ + */ + +/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the FDCAN. + (+) De-initialize the FDCAN. + (+) Enter FDCAN peripheral in power down mode. + (+) Exit power down mode. + (+) Register callbacks. + (+) Unregister callbacks. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FDCAN peripheral according to the specified + * parameters in the FDCAN_InitTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + HAL_StatusTypeDef status; + const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7}; + + /* Check FDCAN handle */ + if (hfdcan == NULL) + { + return HAL_ERROR; + } + + /* Check FDCAN instance */ + if (hfdcan->Instance == FDCAN1) + { + hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U); + } + + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat)); + assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException)); + assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler)); + assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth)); + assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1)); + assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2)); + if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) + { + assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler)); + assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth)); + assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1)); + assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2)); + } + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U)); + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U)); + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U)); + if (hfdcan->Init.RxFifo0ElmtsNbr > 0U) + { + assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize)); + } + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U)); + if (hfdcan->Init.RxFifo1ElmtsNbr > 0U) + { + assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize)); + } + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U)); + if (hfdcan->Init.RxBuffersNbr > 0U) + { + assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize)); + } + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U)); + assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U)); + if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U) + { + assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode)); + } + if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U) + { + assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize)); + } + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfdcan->Lock = HAL_UNLOCKED; + + /* Reset callbacks to legacy functions */ + hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* ClockCalibrationCallback */ + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* TxEventFifoCallback */ + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* RxFifo0Callback */ + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* RxFifo1Callback */ + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* TxFifoEmptyCallback */ + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* TxBufferCompleteCallback */ + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* TxBufferAbortCallback */ + hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback; /* RxBufferNewMessageCallback */ + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */ + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */ + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* TimeoutOccurredCallback */ + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* ErrorCallback */ + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* ErrorStatusCallback */ + hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* TT_ScheduleSyncCallback */ + hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* TT_TimeMarkCallback */ + hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* TT_StopWatchCallback */ + hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* TT_GlobalTimeCallback */ + + if (hfdcan->MspInitCallback == NULL) + { + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hfdcan->MspInitCallback(hfdcan); + } +#else + if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfdcan->Lock = HAL_UNLOCKED; + + /* Init the low level hardware: CLOCK, NVIC */ + HAL_FDCAN_MspInit(hfdcan); + } +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + + /* Exit from Sleep mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode acknowledge */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Request initialisation */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the INIT bit into CCCR register is set */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Enable configuration change */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); + + /* Set the no automatic retransmission */ + if (hfdcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); + } + else + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); + } + + /* Set the transmit pause feature */ + if (hfdcan->Init.TransmitPause == ENABLE) + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); + } + else + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); + } + + /* Set the Protocol Exception Handling */ + if (hfdcan->Init.ProtocolException == ENABLE) + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); + } + else + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); + } + + /* Set FDCAN Frame Format */ + MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat); + + /* Reset FDCAN Operation Mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM)); + CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); + + /* Set FDCAN Operating Mode: + | Normal | Restricted | Bus | Internal | External + | | Operation | Monitoring | LoopBack | LoopBack + CCCR.TEST | 0 | 0 | 0 | 1 | 1 + CCCR.MON | 0 | 0 | 1 | 1 | 0 + TEST.LBCK | 0 | 0 | 0 | 1 | 1 + CCCR.ASM | 0 | 1 | 0 | 0 | 0 + */ + if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION) + { + /* Enable Restricted Operation mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); + } + else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL) + { + if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING) + { + /* Enable write access to TEST register */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST); + + /* Enable LoopBack mode */ + SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); + + if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK) + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); + } + } + else + { + /* Enable bus monitoring mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); + } + } + else + { + /* Nothing to do: normal mode */ + } + + /* Set the nominal bit timing register */ + hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ + (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \ + (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \ + (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos)); + + /* If FD operation with BRS is selected, set the data bit timing register */ + if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) + { + hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ + (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \ + (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \ + (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos)); + } + + if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U) + { + /* Select between Tx FIFO and Tx Queue operation modes */ + SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode); + } + + /* Configure Tx element size */ + if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U) + { + MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]); + } + + /* Configure Rx FIFO 0 element size */ + if (hfdcan->Init.RxFifo0ElmtsNbr > 0U) + { + MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, + (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos)); + } + + /* Configure Rx FIFO 1 element size */ + if (hfdcan->Init.RxFifo1ElmtsNbr > 0U) + { + MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, + (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos)); + } + + /* Configure Rx buffer element size */ + if (hfdcan->Init.RxBuffersNbr > 0U) + { + MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, + (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos)); + } + + /* By default operation mode is set to Event-driven communication. + If Time-triggered communication is needed, user should call the + HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */ + if (hfdcan->Instance == FDCAN1) + { + CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM); + } + + /* Initialize the Latest Tx FIFO/Queue request buffer index */ + hfdcan->LatestTxFifoQRequest = 0U; + + /* Initialize the error code */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Initialize the FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_READY; + + /* Calculate each RAM block address */ + status = FDCAN_CalcultateRamBlockAddresses(hfdcan); + + /* Return function status */ + return status; +} + +/** + * @brief Deinitializes the FDCAN peripheral registers to their default reset values. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Check FDCAN handle */ + if (hfdcan == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + /* Stop the FDCAN module: return value is voluntary ignored */ + (void)HAL_FDCAN_Stop(hfdcan); + + /* Disable Interrupt lines */ + CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1)); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + if (hfdcan->MspDeInitCallback == NULL) + { + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hfdcan->MspDeInitCallback(hfdcan); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_FDCAN_MspDeInit(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + + /* Reset the FDCAN ErrorCode */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the FDCAN MSP. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the FDCAN MSP. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Enter FDCAN peripheral in sleep mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Request clock stop */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FDCAN is ready for power down */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Exit power down mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Reset clock stop request */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FDCAN exits sleep mode */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Enter normal operation */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Return function status */ + return HAL_OK; +} + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a FDCAN CallBack. + * To be used instead of the weak predefined callback + * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains + * the configuration information for FDCAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID + * @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID + * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID + * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID + * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID + * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : + hfdcan->TxFifoEmptyCallback = pCallback; + break; + + case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID : + hfdcan->RxBufferNewMessageCallback = pCallback; + break; + + case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : + hfdcan->HighPriorityMessageCallback = pCallback; + break; + + case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : + hfdcan->TimestampWraparoundCallback = pCallback; + break; + + case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : + hfdcan->TimeoutOccurredCallback = pCallback; + break; + + case HAL_FDCAN_ERROR_CALLBACK_CB_ID : + hfdcan->ErrorCallback = pCallback; + break; + + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = pCallback; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = pCallback; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a FDCAN CallBack. + * FDCAN callback is redirected to the weak predefined callback + * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains + * the configuration information for FDCAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID + * @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID + * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID + * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID + * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID + * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; + break; + + case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID : + hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback; + break; + + case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; + break; + + case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; + break; + + case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; + break; + + case HAL_FDCAN_ERROR_CALLBACK_CB_ID : + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; + break; + + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Clock Calibration FDCAN Callback + * To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Clock Calibration Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_ClockCalibrationCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ClockCalibrationCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Clock Calibration FDCAN Callback + * Clock Calibration FDCAN Callback is redirected to the weak + * HAL_FDCAN_ClockCalibrationCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak ClockCalibrationCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Event Fifo FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Event Fifo Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxEventFifoCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxEventFifoCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Event Fifo FDCAN Callback + * Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Rx Fifo 0 FDCAN Callback + * To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Rx Fifo 0 Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo0CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo0Callback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Rx Fifo 0 FDCAN Callback + * Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Rx Fifo 1 FDCAN Callback + * To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Rx Fifo 1 Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo1CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo1Callback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Rx Fifo 1 FDCAN Callback + * Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Buffer Complete FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Buffer Complete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferCompleteCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferCompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Buffer Complete FDCAN Callback + * Tx Buffer Complete FDCAN Callback is redirected to + * the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Buffer Abort FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Buffer Abort Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferAbortCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferAbortCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Buffer Abort FDCAN Callback + * Tx Buffer Abort FDCAN Callback is redirected to + * the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Error Status FDCAN Callback + * To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Error Status Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_ErrorStatusCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ErrorStatusCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Error Status FDCAN Callback + * Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register TT Schedule Synchronization FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the TT Schedule Synchronization Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_ScheduleSyncCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the TT Schedule Synchronization FDCAN Callback + * TT Schedule Synchronization Callback is redirected to the weak + * HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak TT_ScheduleSyncCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register TT Time Mark FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the TT Time Mark Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TT_TimeMarkCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_TimeMarkCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the TT Time Mark FDCAN Callback + * TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak TT_TimeMarkCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register TT Stop Watch FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the TT Stop Watch Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TT_StopWatchCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_StopWatchCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the TT Stop Watch FDCAN Callback + * TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak TT_StopWatchCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register TT Global Time FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the TT Global Time Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_GlobalTimeCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the TT Global Time FDCAN Callback + * TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak TT_GlobalTimeCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions + * @brief FDCAN Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_ConfigClockCalibration : Configure the FDCAN clock calibration unit + (+) HAL_FDCAN_GetClockCalibrationState : Get the clock calibration state + (+) HAL_FDCAN_ResetClockCalibrationState : Reset the clock calibration state + (+) HAL_FDCAN_GetClockCalibrationCounter : Get the clock calibration counters values + (+) HAL_FDCAN_ConfigFilter : Configure the FDCAN reception filters + (+) HAL_FDCAN_ConfigGlobalFilter : Configure the FDCAN global filter + (+) HAL_FDCAN_ConfigExtendedIdMask : Configure the extended ID mask + (+) HAL_FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO operation mode + (+) HAL_FDCAN_ConfigFifoWatermark : Configure the FIFO watermark + (+) HAL_FDCAN_ConfigRamWatchdog : Configure the RAM watchdog + (+) HAL_FDCAN_ConfigTimestampCounter : Configure the timestamp counter + (+) HAL_FDCAN_EnableTimestampCounter : Enable the timestamp counter + (+) HAL_FDCAN_DisableTimestampCounter : Disable the timestamp counter + (+) HAL_FDCAN_GetTimestampCounter : Get the timestamp counter value + (+) HAL_FDCAN_ResetTimestampCounter : Reset the timestamp counter to zero + (+) HAL_FDCAN_ConfigTimeoutCounter : Configure the timeout counter + (+) HAL_FDCAN_EnableTimeoutCounter : Enable the timeout counter + (+) HAL_FDCAN_DisableTimeoutCounter : Disable the timeout counter + (+) HAL_FDCAN_GetTimeoutCounter : Get the timeout counter value + (+) HAL_FDCAN_ResetTimeoutCounter : Reset the timeout counter to its start value + (+) HAL_FDCAN_ConfigTxDelayCompensation : Configure the transmitter delay compensation + (+) HAL_FDCAN_EnableTxDelayCompensation : Enable the transmitter delay compensation + (+) HAL_FDCAN_DisableTxDelayCompensation : Disable the transmitter delay compensation + (+) HAL_FDCAN_EnableISOMode : Enable ISO 11898-1 protocol mode + (+) HAL_FDCAN_DisableISOMode : Disable ISO 11898-1 protocol mode + (+) HAL_FDCAN_EnableEdgeFiltering : Enable edge filtering during bus integration + (+) HAL_FDCAN_DisableEdgeFiltering : Disable edge filtering during bus integration + +@endverbatim + * @{ + */ + +/** + * @brief Configure the FDCAN clock calibration unit according to the specified + * parameters in the FDCAN_ClkCalUnitTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param sCcuConfig pointer to an FDCAN_ClkCalUnitTypeDef structure that + * contains the clock calibration information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, + const FDCAN_ClkCalUnitTypeDef *sCcuConfig) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration)); + if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE) + { + assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider)); + } + else + { + assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFFU)); + assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength)); + assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4U)); + assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25U)); + assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFFU)); + } + + /* FDCAN1 should be initialized in order to use clock calibration */ + if (hfdcan->Instance != FDCAN1) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE) + { + /* Bypass clock calibration */ + SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC); + + /* Configure clock divider */ + MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, + (sCcuConfig->ClockDivider << FDCANCCU_CCFG_CDIV_Pos)); + } + else /* sCcuConfig->ClockCalibration == ENABLE */ + { + /* Clock calibration unit generates time quanta clock */ + CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC); + + /* Configure clock calibration unit */ + MODIFY_REG(FDCAN_CCU->CCFG, + (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM), + ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) | + sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos))); + + /* Configure the start value of the calibration watchdog counter */ + MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the clock calibration state. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state) + */ +uint32_t HAL_FDCAN_GetClockCalibrationState(const FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS); +} + +/** + * @brief Reset the clock calibration state. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan) +{ + /* FDCAN1 should be initialized in order to use clock calibration */ + if (hfdcan->Instance != FDCAN1) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Calibration software reset */ + SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the clock calibration counter value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param Counter clock calibration counter. + * This parameter can be a value of @arg FDCAN_calibration_counter. + * @retval Value clock calibration counter value + */ +uint32_t HAL_FDCAN_GetClockCalibrationCounter(const FDCAN_HandleTypeDef *hfdcan, uint32_t Counter) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* Check function parameters */ + assert_param(IS_FDCAN_CALIBRATION_COUNTER(Counter)); + + if (Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER) + { + return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> FDCANCCU_CSTAT_TQC_Pos); + } + else if (Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) + { + return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC); + } + else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */ + { + return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> FDCANCCU_CWD_WDV_Pos); + } +} + +/** + * @brief Configure the FDCAN reception filter according to the specified + * parameters in the FDCAN_FilterTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that + * contains the filter configuration information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig) +{ + uint32_t FilterElementW1; + uint32_t FilterElementW2; + uint32_t *FilterAddress; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check function parameters */ + assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType)); + assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig)); + if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER) + { + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U)); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U)); + } + + if (sFilterConfig->IdType == FDCAN_STANDARD_ID) + { + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); + if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER) + { + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); + assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); + } + + /* Build filter element */ + if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER) + { + FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U) | + (sFilterConfig->FilterID1 << 16U) | + (sFilterConfig->IsCalibrationMsg << 8U) | + sFilterConfig->RxBufferIndex); + } + else + { + FilterElementW1 = ((sFilterConfig->FilterType << 30U) | + (sFilterConfig->FilterConfig << 27U) | + (sFilterConfig->FilterID1 << 16U) | + sFilterConfig->FilterID2); + } + + /* Calculate filter address */ + FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4U)); + + /* Write filter element to the message RAM */ + *FilterAddress = FilterElementW1; + } + else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ + { + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); + if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER) + { + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); + assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); + } + + /* Build first word of filter element */ + FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1); + + /* Build second word of filter element */ + if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER) + { + FilterElementW2 = sFilterConfig->RxBufferIndex; + } + else + { + FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2); + } + + /* Calculate filter address */ + FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4U * 2U)); + + /* Write filter element to the message RAM */ + *FilterAddress = FilterElementW1; + FilterAddress++; + *FilterAddress = FilterElementW2; + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the FDCAN global filter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param NonMatchingStd Defines how received messages with 11-bit IDs that + * do not match any element of the filter list are treated. + * This parameter can be a value of @arg FDCAN_Non_Matching_Frames. + * @param NonMatchingExt Defines how received messages with 29-bit IDs that + * do not match any element of the filter list are treated. + * This parameter can be a value of @arg FDCAN_Non_Matching_Frames. + * @param RejectRemoteStd Filter or reject all the remote 11-bit IDs frames. + * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames. + * @param RejectRemoteExt Filter or reject all the remote 29-bit IDs frames. + * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, + uint32_t NonMatchingStd, + uint32_t NonMatchingExt, + uint32_t RejectRemoteStd, + uint32_t RejectRemoteExt) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd)); + assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt)); + assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd)); + assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure global filter */ + hfdcan->Instance->GFC = ((NonMatchingStd << FDCAN_GFC_ANFS_Pos) | + (NonMatchingExt << FDCAN_GFC_ANFE_Pos) | + (RejectRemoteStd << FDCAN_GFC_RRFS_Pos) | + (RejectRemoteExt << FDCAN_GFC_RRFE_Pos)); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the extended ID mask. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param Mask Extended ID Mask. + * This parameter must be a number between 0 and 0x1FFFFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure the extended ID mask */ + hfdcan->Instance->XIDAM = Mask; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the Rx FIFO operation mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo Rx FIFO. + * This parameter can be one of the following values: + * @arg FDCAN_RX_FIFO0: Rx FIFO 0 + * @arg FDCAN_RX_FIFO1: Rx FIFO 1 + * @param OperationMode operation mode. + * This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_RX_FIFO(RxFifo)); + assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + if (RxFifo == FDCAN_RX_FIFO0) + { + /* Select FIFO 0 Operation Mode */ + MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, (OperationMode << FDCAN_RXF0C_F0OM_Pos)); + } + else /* RxFifo == FDCAN_RX_FIFO1 */ + { + /* Select FIFO 1 Operation Mode */ + MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, (OperationMode << FDCAN_RXF1C_F1OM_Pos)); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the FIFO watermark. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param FIFO select the FIFO to be configured. + * This parameter can be a value of @arg FDCAN_FIFO_watermark. + * @param Watermark level for FIFO watermark interrupt. + * This parameter must be a number between: + * - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO + * - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO)); + if (FIFO == FDCAN_CFG_TX_EVENT_FIFO) + { + assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U)); + } + else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */ + { + assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U)); + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Set the level for FIFO watermark interrupt */ + if (FIFO == FDCAN_CFG_TX_EVENT_FIFO) + { + MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << FDCAN_TXEFC_EFWM_Pos)); + } + else if (FIFO == FDCAN_CFG_RX_FIFO0) + { + MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << FDCAN_RXF0C_F0WM_Pos)); + } + else /* FIFO == FDCAN_CFG_RX_FIFO1 */ + { + MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << FDCAN_RXF1C_F1WM_Pos)); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the RAM watchdog. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param CounterStartValue Start value of the Message RAM Watchdog Counter, + * This parameter must be a number between 0x00 and 0xFF, + * with the reset value of 0x00 the counter is disabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure the RAM watchdog counter start value */ + MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimestampPrescaler Timestamp Counter Prescaler. + * This parameter can be a value of @arg FDCAN_Timestamp_Prescaler. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure prescaler */ + MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimestampOperation Timestamp counter operation. + * This parameter can be a value of @arg FDCAN_Timestamp. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable timestamp counter */ + MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable timestamp counter */ + CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the timestamp counter value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Timestamp counter value + */ +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan) +{ + return (uint16_t)(hfdcan->Instance->TSCV); +} + +/** + * @brief Reset the timestamp counter to zero. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL) + { + /* Reset timestamp counter. + Actually any write operation to TSCV clears the counter */ + CLEAR_REG(hfdcan->Instance->TSCV); + } + else + { + /* Update error code. + Unable to reset external counter */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimeoutOperation Timeout counter operation. + * This parameter can be a value of @arg FDCAN_Timeout_Operation. + * @param TimeoutPeriod Start value of the timeout down-counter. + * This parameter must be a number between 0x0000 and 0xFFFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, + uint32_t TimeoutPeriod) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation)); + assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Select timeout operation and configure period */ + MODIFY_REG(hfdcan->Instance->TOCC, + (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos))); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable timeout counter */ + SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable timeout counter */ + CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the timeout counter value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Timeout counter value + */ +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan) +{ + return (uint16_t)(hfdcan->Instance->TOCV); +} + +/** + * @brief Reset the timeout counter to its start value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS) + { + /* Reset timeout counter to start value */ + CLEAR_REG(hfdcan->Instance->TOCV); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Unable to reset counter: controlled only by FIFO empty state */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TdcOffset Transmitter Delay Compensation Offset. + * This parameter must be a number between 0x00 and 0x7F. + * @param TdcFilter Transmitter Delay Compensation Filter Window Length. + * This parameter must be a number between 0x00 and 0x7F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, + uint32_t TdcFilter) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU)); + assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure TDC offset and filter window */ + hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos)); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable transmitter delay compensation */ + SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable transmitter delay compensation */ + CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable ISO 11898-1 protocol mode. + * CAN FD frame format is according to ISO 11898-1 standard. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable Non ISO protocol mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable ISO 11898-1 protocol mode. + * CAN FD frame format is according to Bosch CAN FD specification V1.0. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable Non ISO protocol mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable edge filtering during bus integration. + * Two consecutive dominant tq are required to detect an edge for hard synchronization. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable edge filtering */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable edge filtering during bus integration. + * One dominant tq is required to detect an edge for hard synchronization. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable edge filtering */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_Start : Start the FDCAN module + (+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers + (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding + transmission request + (+) HAL_FDCAN_AddMessageToTxBuffer : Add a message to a dedicated Tx buffer + (+) HAL_FDCAN_EnableTxBufferRequest : Enable transmission request + (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request + (+) HAL_FDCAN_AbortTxRequest : Abort transmission request + (+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx Buffer/FIFO zone into the + message RAM + (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone + into the message RAM + (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status + (+) HAL_FDCAN_GetProtocolStatus : Get protocol status + (+) HAL_FDCAN_GetErrorCounters : Get error counter values + (+) HAL_FDCAN_IsRxBufferMessageAvailable : Check if a new message is received in the selected Rx buffer + (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending + on the selected Tx buffer + (+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level + (+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level + (+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode + (+) HAL_FDCAN_ExitRestrictedOperationMode : Exit Restricted Operation Mode + +@endverbatim + * @{ + */ + +/** + * @brief Start the FDCAN module. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Change FDCAN peripheral state */ + hfdcan->State = HAL_FDCAN_STATE_BUSY; + + /* Request leave initialisation */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Reset the FDCAN ErrorCode */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the FDCAN module and enable access to configuration registers. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Request initialisation */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Wait until the INIT bit into CCCR register is set */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Reset counter */ + Counter = 0U; + + /* Exit from Sleep mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Wait until FDCAN exits sleep mode */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable configuration change */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); + + /* Reset Latest Tx FIFO/Queue Request Buffer Index */ + hfdcan->LatestTxFifoQRequest = 0U; + + /* Change FDCAN peripheral state */ + hfdcan->State = HAL_FDCAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Add a message to the Tx FIFO/Queue and activate the corresponding transmission request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. + * @param pTxData pointer to a buffer containing the payload of the Tx frame. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData) +{ + uint32_t PutIndex; + + /* Check function parameters */ + assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType)); + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU)); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU)); + } + assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType)); + assert_param(IS_FDCAN_DLC(pTxHeader->DataLength)); + assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator)); + assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch)); + assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat)); + assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl)); + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Check that the Tx FIFO/Queue has an allocated area into the RAM */ + if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + /* Check that the Tx FIFO/Queue is not full */ + if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL; + + return HAL_ERROR; + } + else + { + /* Retrieve the Tx FIFO PutIndex */ + PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos); + + /* Add the message to the Tx FIFO/Queue */ + FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex); + + /* Activate the corresponding transmission request */ + hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex); + + /* Store the Latest Tx FIFO/Queue Request Buffer Index */ + hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Add a message to a dedicated Tx buffer + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. + * @param pTxData pointer to a buffer containing the payload of the Tx frame. + * @param BufferIndex index of the buffer to be configured. + * This parameter can be a value of @arg FDCAN_Tx_location. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType)); + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU)); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU)); + } + assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType)); + assert_param(IS_FDCAN_DLC(pTxHeader->DataLength)); + assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator)); + assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch)); + assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat)); + assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl)); + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU)); + assert_param(IS_FDCAN_TX_LOCATION(BufferIndex)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that the selected buffer has an allocated area into the RAM */ + if (POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_Pos)) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + /* Check that there is no transmission request pending for the selected buffer */ + if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING; + + return HAL_ERROR; + } + else + { + /* Add the message to the Tx buffer */ + FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex)); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable transmission request. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndex buffer index. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex) +{ + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Add transmission request */ + hfdcan->Instance->TXBAR = BufferIndex; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get Tx buffer index of latest Tx FIFO/Queue request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Tx buffer index of last Tx FIFO/Queue request + * - Any value of @arg FDCAN_Tx_location if Tx request has been submitted. + * - 0 if no Tx FIFO/Queue request have been submitted. + */ +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan) +{ + /* Return Last Tx FIFO/Queue Request Buffer */ + return hfdcan->LatestTxFifoQRequest; +} + +/** + * @brief Abort transmission request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndex buffer index. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex) +{ + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Add cancellation request */ + hfdcan->Instance->TXBCR = BufferIndex; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxLocation Location of the received message to be read. + * This parameter can be a value of @arg FDCAN_Rx_location. + * @param pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure. + * @param pRxData pointer to a buffer where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, + FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData) +{ + uint32_t *RxAddress; + uint8_t *pData; + uint32_t ByteCounter; + uint32_t GetIndex = 0; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if (state == HAL_FDCAN_STATE_BUSY) + { + if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 has an allocated area into the RAM */ + if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + /* Check that the Rx FIFO 0 is not empty */ + if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + else + { + /* Check that the Rx FIFO 0 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) + { + if (((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0OM) >> FDCAN_RXF0C_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 0 element index */ + GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); + + /* Calculate Rx FIFO 0 element address */ + RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U)); + } + } + else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 has an allocated area into the RAM */ + if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + /* Check that the Rx FIFO 1 is not empty */ + if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + else + { + /* Check that the Rx FIFO 1 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) + { + if (((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1OM) >> FDCAN_RXF1C_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 1 element index */ + GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); + + /* Calculate Rx FIFO 1 element address */ + RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U)); + } + } + else /* Rx element is assigned to a dedicated Rx buffer */ + { + /* Check that the selected buffer has an allocated area into the RAM */ + if (RxLocation >= hfdcan->Init.RxBuffersNbr) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + else + { + /* Calculate Rx buffer address */ + RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U)); + } + } + + /* Retrieve IdType */ + pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD; + + /* Retrieve Identifier */ + if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ + { + pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U); + } + else /* Extended ID element */ + { + pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID); + } + + /* Retrieve RxFrameType */ + pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR); + + /* Retrieve ErrorStateIndicator */ + pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI); + + /* Increment RxAddress pointer to second word of Rx FIFO element */ + RxAddress++; + + /* Retrieve RxTimestamp */ + pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS); + + /* Retrieve DataLength */ + pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); + + /* Retrieve BitRateSwitch */ + pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS); + + /* Retrieve FDFormat */ + pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF); + + /* Retrieve FilterIndex */ + pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U); + + /* Retrieve NonMatchingFrame */ + pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U); + + /* Increment RxAddress pointer to payload of Rx FIFO element */ + RxAddress++; + + /* Retrieve Rx payload */ + pData = (uint8_t *)RxAddress; + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++) + { + pRxData[ByteCounter] = pData[ByteCounter]; + } + + if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ + { + /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->RXF0A = GetIndex; + } + else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->RXF1A = GetIndex; + } + else /* Rx element is assigned to a dedicated Rx buffer */ + { + /* Clear the New Data flag of the current Rx buffer */ + if (RxLocation < FDCAN_RX_BUFFER32) + { + hfdcan->Instance->NDAT1 = ((uint32_t)1U << RxLocation); + } + else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */ + { + hfdcan->Instance->NDAT2 = ((uint32_t)1U << (RxLocation & 0x1FU)); + } + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent) +{ + uint32_t *TxEventAddress; + uint32_t GetIndex; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1U)); + + if (state == HAL_FDCAN_STATE_BUSY) + { + /* Check that the Tx Event FIFO has an allocated area into the RAM */ + if ((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + /* Check that the Tx event FIFO is not empty */ + if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + + /* Calculate Tx event FIFO element address */ + GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos); + TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2U * 4U)); + + /* Retrieve IdType */ + pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD; + + /* Retrieve Identifier */ + if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ + { + pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U); + } + else /* Extended ID element */ + { + pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID); + } + + /* Retrieve TxFrameType */ + pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR); + + /* Retrieve ErrorStateIndicator */ + pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI); + + /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */ + TxEventAddress++; + + /* Retrieve TxTimestamp */ + pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS); + + /* Retrieve DataLength */ + pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); + + /* Retrieve BitRateSwitch */ + pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS); + + /* Retrieve FDFormat */ + pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF); + + /* Retrieve EventType */ + pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET); + + /* Retrieve MessageMarker */ + pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U); + + /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->TXEFA = GetIndex; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get high priority message status. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_HpMsgStatusTypeDef *HpMsgStatus) +{ + HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos); + HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos); + HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI); + HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get protocol status. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus) +{ + uint32_t StatusReg; + + /* Read the protocol status register */ + StatusReg = READ_REG(hfdcan->Instance->PSR); + + /* Fill the protocol status structure */ + ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC); + ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos); + ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT); + ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos); + ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos); + ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos); + ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos); + ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos); + ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos); + ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos); + ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get error counter values. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters) +{ + uint32_t CountersReg; + + /* Read the error counters register */ + CountersReg = READ_REG(hfdcan->Instance->ECR); + + /* Fill the error counters structure */ + ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos); + ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos); + ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos); + ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Check if a new message is received in the selected Rx buffer. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxBufferIndex Rx buffer index. + * This parameter must be a number between 0 and 63. + * @retval Status + * - 0 : No new message on RxBufferIndex. + * - 1 : New message received on RxBufferIndex. + */ +uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63U)); + uint32_t NewData1 = hfdcan->Instance->NDAT1; + uint32_t NewData2 = hfdcan->Instance->NDAT2; + + /* Check new message reception on the selected buffer */ + if (((RxBufferIndex < 32U) && ((NewData1 & (uint32_t)((uint32_t)1 << RxBufferIndex)) == 0U)) || + ((RxBufferIndex >= 32U) && ((NewData2 & (uint32_t)((uint32_t)1 << (RxBufferIndex & 0x1FU))) == 0U))) + { + return 0; + } + + /* Clear the New Data flag of the current Rx buffer */ + if (RxBufferIndex < 32U) + { + hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxBufferIndex); + } + else /* 32 <= RxBufferIndex <= 63 */ + { + hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxBufferIndex & 0x1FU)); + } + + return 1; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx buffer. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TxBufferIndex Tx buffer index. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval Status + * - 0 : No pending transmission request on TxBufferIndex. + * - 1 : Pending transmission request on TxBufferIndex. + */ +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) +{ + /* Check pending transmission request on the selected buffer */ + if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U) + { + return 0; + } + return 1; +} + +/** + * @brief Return Rx FIFO fill level. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo Rx FIFO. + * This parameter can be one of the following values: + * @arg FDCAN_RX_FIFO0: Rx FIFO 0 + * @arg FDCAN_RX_FIFO1: Rx FIFO 1 + * @retval Rx FIFO fill level. + */ +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo) +{ + uint32_t FillLevel; + + /* Check function parameters */ + assert_param(IS_FDCAN_RX_FIFO(RxFifo)); + + if (RxFifo == FDCAN_RX_FIFO0) + { + FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL; + } + else /* RxFifo == FDCAN_RX_FIFO1 */ + { + FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL; + } + + /* Return Rx FIFO fill level */ + return FillLevel; +} + +/** + * @brief Return Tx FIFO free level: number of consecutive free Tx FIFO + * elements starting from Tx FIFO GetIndex. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Tx FIFO free level. + */ +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t FreeLevel; + + FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL; + + /* Return Tx FIFO free level */ + return FreeLevel; +} + +/** + * @brief Check if the FDCAN peripheral entered Restricted Operation Mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Status + * - 0 : Normal FDCAN operation. + * - 1 : Restricted Operation Mode active. + */ +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t OperationMode; + + /* Get Operation Mode */ + OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos); + + return OperationMode; +} + +/** + * @brief Exit Restricted Operation Mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Exit Restricted Operation mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions + * @brief TT Configuration and control functions + * +@verbatim + ============================================================================== + ##### TT Configuration and control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_TT_ConfigOperation : Initialize TT operation parameters + (+) HAL_FDCAN_TT_ConfigReferenceMessage : Configure the reference message + (+) HAL_FDCAN_TT_ConfigTrigger : Configure the FDCAN trigger + (+) HAL_FDCAN_TT_SetGlobalTime : Schedule global time adjustment + (+) HAL_FDCAN_TT_SetClockSynchronization : Schedule TUR numerator update + (+) HAL_FDCAN_TT_ConfigStopWatch : Configure stop watch source and polarity + (+) HAL_FDCAN_TT_ConfigRegisterTimeMark : Configure register time mark pulse generation + (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse : Enable register time mark pulse generation + (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse : Disable register time mark pulse generation + (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse : Enable trigger time mark pulse generation + (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse : Disable trigger time mark pulse generation + (+) HAL_FDCAN_TT_EnableHardwareGapControl : Enable gap control by input pin fdcan1_evt + (+) HAL_FDCAN_TT_DisableHardwareGapControl : Disable gap control by input pin fdcan1_evt + (+) HAL_FDCAN_TT_EnableTimeMarkGapControl : Enable gap control (finish only) by register time mark IT + (+) HAL_FDCAN_TT_DisableTimeMarkGapControl : Disable gap control by register time mark interrupt + (+) HAL_FDCAN_TT_SetNextIsGap : Transmit next reference message with Next_is_Gap = "1" + (+) HAL_FDCAN_TT_SetEndOfGap : Finish a Gap by requesting start of reference message + (+) HAL_FDCAN_TT_ConfigExternalSyncPhase : Configure target phase used for external synchronization + (+) HAL_FDCAN_TT_EnableExternalSynchronization : Synchronize the phase of the FDCAN schedule to an external + schedule + (+) HAL_FDCAN_TT_DisableExternalSynchronization : Disable external schedule synchronization + (+) HAL_FDCAN_TT_GetOperationStatus : Get TT operation status + +@endverbatim + * @{ + */ + +/** + * @brief Initialize TT operation parameters. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TT_ConfigTypeDef *pTTParams) +{ + uint32_t tickstart; + uint32_t RAMcounter; + uint32_t StartAddress; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator)); + assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator)); + assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster)); + assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7U)); + assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127U)); + assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64U)); + assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync)); + assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel)); + assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel)); + if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER) + { + assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr)); + } + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0) + { + assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable)); + assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255U)); + assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity)); + assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow)); + assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095U)); + } + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1) + { + assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator)); + assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync)); + assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter)); + assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration)); + } + else + { + assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator)); + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Stop local time in order to enable write access to the other bits of TURCF register */ + CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the ELT bit into TURCF register is reset */ + while ((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Configure TUR (Time Unit Ratio) */ + MODIFY_REG(hfdcan->ttcan->TURCF, + (FDCAN_TURCF_NCL | FDCAN_TURCF_DC), + (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) | + (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos))); + + /* Enable local time */ + SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT); + + /* Configure TT operation */ + MODIFY_REG(hfdcan->ttcan->TTOCF, + (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO), + (pTTParams->OperationMode | \ + pTTParams->TimeMaster | \ + (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_Pos) | \ + (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_Pos))); + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0) + { + MODIFY_REG(hfdcan->ttcan->TTOCF, + (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP), + (pTTParams->GapEnable | \ + (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_Pos) | \ + pTTParams->EvtTrigPolarity)); + } + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1) + { + MODIFY_REG(hfdcan->ttcan->TTOCF, + (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC), + (pTTParams->ExternalClkSync | \ + pTTParams->GlobalTimeFilter | \ + pTTParams->ClockCalibration)); + } + + /* Configure system matrix limits */ + MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync); + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0) + { + MODIFY_REG(hfdcan->ttcan->TTMLM, + (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT), + (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) | + (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos))); + } + if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER) + { + MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr); + } + + /* Configure input triggers: Stop watch and Event */ + MODIFY_REG(hfdcan->ttcan->TTTS, + (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL), + (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel)); + + /* Configure trigger memory start address */ + StartAddress = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4U; + MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (StartAddress << FDCAN_TTTMC_TMSA_Pos)); + + /* Trigger memory elements number */ + MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << FDCAN_TTTMC_TME_Pos)); + + /* Recalculate End Address */ + hfdcan->msgRam.TTMemorySA = hfdcan->msgRam.EndAddress; + hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2U * 4U); + + if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */ + { + /* Update error code. + Message RAM overflow */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + else + { + /* Flush the allocated Message RAM area */ + for (RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U) + { + *(uint32_t *)(RAMcounter) = 0x00000000; + } + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the reference message. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param IdType Identifier Type. + * This parameter can be a value of @arg FDCAN_id_type. + * @param Identifier Reference Identifier. + * This parameter must be a number between: + * - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + * - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + * @param Payload Enable or disable the additional payload. + * This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload. + * This parameter is ignored in case of time slaves. + * If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the + * following elements are taken from Tx Buffer 0: + * - MessageMarker + * - TxEventFifoControl + * - DataLength + * - Data Bytes (payload): + * - bytes 2-8, for Level 1 + * - bytes 5-8, for Level 0 and Level 2 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, + uint32_t Identifier, uint32_t Payload) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_ID_TYPE(IdType)); + if (IdType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU)); + } + else /* IdType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU)); + } + assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure reference message identifier type, identifier and payload */ + if (IdType == FDCAN_EXTENDED_ID) + { + MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), + (Payload | IdType | Identifier)); + } + else /* IdType == FDCAN_STANDARD_ID */ + { + MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), + (Payload | IdType | (Identifier << 18))); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the FDCAN trigger according to the specified + * parameters in the FDCAN_TriggerTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param sTriggerConfig pointer to an FDCAN_TriggerTypeDef structure that + * contains the trigger configuration information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TriggerTypeDef *sTriggerConfig) +{ + uint32_t CycleCode; + uint32_t MessageNumber; + uint32_t TriggerElementW1; + uint32_t TriggerElementW2; + uint32_t *TriggerAddress; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63U)); + assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFFU)); + assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor)); + if (sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE) + { + assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1U))); + } + assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt)); + assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt)); + assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType)); + assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType)); + if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED)) + { + assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex)); + } + if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER) + { + if (sTriggerConfig->FilterType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63U)); + } + else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127U)); + } + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Calculate cycle code */ + if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE) + { + CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE; + } + else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */ + { + CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle; + } + + /* Build first word of trigger element */ + TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \ + (CycleCode << 8) | \ + sTriggerConfig->TmEventInt | \ + sTriggerConfig->TmEventExt | \ + sTriggerConfig->TriggerType); + + /* Select message number depending on trigger type (transmission or reception) */ + if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER) + { + MessageNumber = sTriggerConfig->FilterIndex; + } + else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED)) + { + MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex); + } + else + { + MessageNumber = 0U; + } + + /* Build second word of trigger element */ + TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16)); + + /* Calculate trigger address */ + TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4U * 2U)); + + /* Write trigger element to the message RAM */ + *TriggerAddress = TriggerElementW1; + TriggerAddress++; + *TriggerAddress = TriggerElementW2; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Schedule global time adjustment for the next reference message. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimePreset time preset value. + * This parameter must be a number between: + * - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset + * or + * - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that the external clock synchronization is enabled */ + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Check that no global time preset is pending */ + if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING; + + return HAL_ERROR; + } + + /* Configure time preset */ + MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, (TimePreset << FDCAN_TTGTP_TP_Pos)); + + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Schedule time preset to take effect by the next reference message */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Schedule TUR numerator update for the next reference message. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param NewTURNumerator new value of the TUR numerator. + * This parameter must be a number between 0x10000 and 0x1FFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that the external clock synchronization is enabled */ + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Check that no external clock synchronization is pending */ + if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING; + + return HAL_ERROR; + } + + /* Configure new TUR numerator */ + MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000U)); + + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Schedule TUR numerator update by the next reference message */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure stop watch source and polarity. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param Source stop watch source. + * This parameter can be a value of @arg FDCAN_TT_stop_watch_source. + * @param Polarity stop watch polarity. + * This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source)); + assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Select stop watch source and polarity */ + MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity)); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure register time mark pulse generation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimeMarkSource time mark source. + * This parameter can be a value of @arg FDCAN_TT_time_mark_source. + * @param TimeMarkValue time mark value (reference). + * This parameter must be a number between 0 and 0xFFFF. + * @param RepeatFactor repeat factor of the cycle for which the time mark is valid. + * This parameter can be a value of @arg FDCAN_TT_Repeat_Factor. + * @param StartCycle index of the first cycle in which the time mark becomes valid. + * This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. + * This parameter must be a number between 0 and RepeatFactor. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, + uint32_t TimeMarkSource, uint32_t TimeMarkValue, + uint32_t RepeatFactor, uint32_t StartCycle) +{ + uint32_t Counter = 0U; + uint32_t CycleCode; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource)); + assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFFU)); + assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor)); + if (RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE) + { + assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1U))); + } + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable the time mark compare function */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC); + + if (TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED) + { + /* Calculate cycle code */ + if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE) + { + CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE; + } + else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */ + { + CycleCode = RepeatFactor + StartCycle; + } + + Counter = 0U; + + /* Wait until the LCKM bit into TTTMK register is reset */ + while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Configure time mark value and cycle code */ + hfdcan->ttcan->TTTMK = ((TimeMarkValue << FDCAN_TTTMK_TM_Pos) | (CycleCode << FDCAN_TTTMK_TICC_Pos)); + + Counter = 0U; + + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Update the register time mark compare source */ + MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable register time mark pulse generation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable Register Time Mark Interrupt output on fdcan1_rtp */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable register time mark pulse generation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable Register Time Mark Interrupt output on fdcan1_rtp */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable trigger time mark pulse generation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable trigger time mark pulse generation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable gap control by input pin fdcan1_evt. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable gap control by pin fdcan1_evt */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable gap control by input pin fdcan1_evt. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable gap control by pin fdcan1_evt */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable gap control (finish only) by register time mark interrupt. + * The next register time mark interrupt (TTIR.RTMI = "1") will finish + * the Gap and start the reference message. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable gap control by register time mark interrupt */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable gap control by register time mark interrupt. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable gap control by register time mark interrupt */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Transmit next reference message with Next_is_Gap = "1". + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that the node is configured for external event-synchronized TT operation */ + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Set Next is Gap */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Finish a Gap by requesting start of reference message. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that the node is configured for external event-synchronized TT operation */ + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Set Finish Gap */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure target phase used for external synchronization by event + * trigger input pin fdcan1_evt. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TargetPhase defines target value of cycle time when a rising edge + * of fdcan1_evt is expected. + * This parameter must be a number between 0 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFFU)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that no external schedule synchronization is pending */ + if ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING; + + return HAL_ERROR; + } + + /* Configure cycle time target phase */ + MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << FDCAN_TTGTP_CTP_Pos)); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Synchronize the phase of the FDCAN schedule to an external schedule + * using event trigger input pin fdcan1_evt. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable external synchronization */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable external schedule synchronization. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable external synchronization */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Get TT operation status. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_TTOperationStatusTypeDef *TTOpStatus) +{ + uint32_t TTStatusReg; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + /* Read the TT operation status register */ + TTStatusReg = READ_REG(hfdcan->ttcan->TTOST); + + /* Fill the TT operation status structure */ + TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL); + TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS); + TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS); + TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> FDCAN_TTOST_QGTP_Pos); + TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> FDCAN_TTOST_QCS_Pos); + TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_Pos); + TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> FDCAN_TTOST_WGTD_Pos); + TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> FDCAN_TTOST_GFI_Pos); + TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_Pos); + TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> FDCAN_TTOST_GSI_Pos); + TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> FDCAN_TTOST_WFE_Pos); + TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> FDCAN_TTOST_AWE_Pos); + TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> FDCAN_TTOST_WECS_Pos); + TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> FDCAN_TTOST_SPL_Pos); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_ConfigInterruptLines : Assign interrupts to either Interrupt line 0 or 1 + (+) HAL_FDCAN_TT_ConfigInterruptLines : Assign TT interrupts to either Interrupt line 0 or 1 + (+) HAL_FDCAN_ActivateNotification : Enable interrupts + (+) HAL_FDCAN_DeactivateNotification : Disable interrupts + (+) HAL_FDCAN_TT_ActivateNotification : Enable TT interrupts + (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts + (+) HAL_FDCAN_IRQHandler : Handles FDCAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Assign interrupts to either Interrupt line 0 or 1. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ITList indicates which interrupts will be assigned to the selected interrupt line. + * This parameter can be any combination of @arg FDCAN_Interrupts. + * @param InterruptLine Interrupt line. + * This parameter can be a value of @arg FDCAN_Interrupt_Line. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT(ITList)); + assert_param(IS_FDCAN_IT_LINE(InterruptLine)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Assign list of interrupts to the selected line */ + if (InterruptLine == FDCAN_INTERRUPT_LINE0) + { + CLEAR_BIT(hfdcan->Instance->ILS, ITList); + } + else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */ + { + SET_BIT(hfdcan->Instance->ILS, ITList); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Assign TT interrupts to either Interrupt line 0 or 1. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TTITList indicates which interrupts will be assigned to the selected interrupt line. + * This parameter can be any combination of @arg FDCAN_TTInterrupts. + * @param InterruptLine Interrupt line. + * This parameter can be a value of @arg FDCAN_Interrupt_Line. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, + uint32_t InterruptLine) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_IT(TTITList)); + assert_param(IS_FDCAN_IT_LINE(InterruptLine)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Assign list of interrupts to the selected line */ + if (InterruptLine == FDCAN_INTERRUPT_LINE0) + { + CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList); + } + else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */ + { + SET_BIT(hfdcan->ttcan->TTILS, TTITList); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg FDCAN_Interrupts. + * @param BufferIndexes Tx Buffer Indexes. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * This parameter is ignored if ActiveITs does not include one of the following: + * - FDCAN_IT_TX_COMPLETE + * - FDCAN_IT_TX_ABORT_COMPLETE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, + uint32_t BufferIndexes) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT(ActiveITs)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Enable Interrupt lines */ + if ((ActiveITs & hfdcan->Instance->ILS) == 0U) + { + /* Enable Interrupt line 0 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs) + { + /* Enable Interrupt line 1 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + else + { + /* Enable Interrupt lines 0 and 1 */ + hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1); + } + + if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U) + { + /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register, + but interrupt will only occur if TC is enabled in IE register */ + SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes); + } + + if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + { + /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register, + but interrupt will only occur if TCF is enabled in IE register */ + SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes); + } + + /* Enable the selected interrupts */ + __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg FDCAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs) +{ + uint32_t ITLineSelection; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT(InactiveITs)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Disable the selected interrupts */ + __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs); + + if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U) + { + /* Disable Tx Buffer Transmission Interrupts */ + CLEAR_REG(hfdcan->Instance->TXBTIE); + } + + if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + { + /* Disable Tx Buffer Cancellation Finished Interrupt */ + CLEAR_REG(hfdcan->Instance->TXBCIE); + } + + ITLineSelection = hfdcan->Instance->ILS; + + if ((hfdcan->Instance->IE | ITLineSelection) == ITLineSelection) + { + /* Disable Interrupt line 0 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + + if ((hfdcan->Instance->IE & ITLineSelection) == 0U) + { + /* Disable Interrupt line 1 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable TT interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ActiveTTITs indicates which TT interrupts will be enabled. + * This parameter can be any combination of @arg FDCAN_TTInterrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_IT(ActiveTTITs)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Enable Interrupt lines */ + if ((ActiveTTITs & hfdcan->ttcan->TTILS) == 0U) + { + /* Enable Interrupt line 0 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + else if ((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs) + { + /* Enable Interrupt line 1 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + else + { + /* Enable Interrupt lines 0 and 1 */ + hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1); + } + + /* Enable the selected TT interrupts */ + __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable TT interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param InactiveTTITs indicates which TT interrupts will be disabled. + * This parameter can be any combination of @arg FDCAN_TTInterrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs) +{ + uint32_t ITLineSelection; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_IT(InactiveTTITs)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Disable the selected TT interrupts */ + __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs); + + ITLineSelection = hfdcan->ttcan->TTILS; + + if ((hfdcan->ttcan->TTIE | ITLineSelection) == ITLineSelection) + { + /* Disable Interrupt line 0 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + + if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U) + { + /* Disable interrupt line 1 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles FDCAN interrupt request. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t ClkCalibrationITs; + uint32_t TxEventFifoITs; + uint32_t RxFifo0ITs; + uint32_t RxFifo1ITs; + uint32_t Errors; + uint32_t ErrorStatusITs; + uint32_t TransmittedBuffers; + uint32_t AbortedBuffers; + uint32_t TTSchedSyncITs; + uint32_t TTTimeMarkITs; + uint32_t TTGlobTimeITs; + uint32_t TTDistErrors; + uint32_t TTFatalErrors; + uint32_t SWTime; + uint32_t SWCycleCount; + uint32_t itsourceIE; + uint32_t itsourceTTIE; + uint32_t itflagIR; + uint32_t itflagTTIR; + + ClkCalibrationITs = (FDCAN_CCU->IR << 30); + ClkCalibrationITs &= (FDCAN_CCU->IE << 30); + TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK; + TxEventFifoITs &= hfdcan->Instance->IE; + RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK; + RxFifo0ITs &= hfdcan->Instance->IE; + RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK; + RxFifo1ITs &= hfdcan->Instance->IE; + Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK; + Errors &= hfdcan->Instance->IE; + ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK; + ErrorStatusITs &= hfdcan->Instance->IE; + itsourceIE = hfdcan->Instance->IE; + itflagIR = hfdcan->Instance->IR; + + /* High Priority Message interrupt management *******************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET) + { + /* Clear the High Priority Message flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->HighPriorityMessageCallback(hfdcan); +#else + /* High Priority Message Callback */ + HAL_FDCAN_HighPriorityMessageCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Transmission Abort interrupt management **********************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET) + { + /* List of aborted monitored buffers */ + AbortedBuffers = hfdcan->Instance->TXBCF; + AbortedBuffers &= hfdcan->Instance->TXBCIE; + + /* Clear the Transmission Cancellation flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers); +#else + /* Transmission Cancellation Callback */ + HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Clock calibration unit interrupts management *****************************/ + if (ClkCalibrationITs != 0U) + { + /* Clear the Clock Calibration flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs); +#else + /* Clock Calibration Callback */ + HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Tx event FIFO interrupts management **************************************/ + if (TxEventFifoITs != 0U) + { + /* Clear the Tx Event FIFO flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs); +#else + /* Tx Event FIFO Callback */ + HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Rx FIFO 0 interrupts management ******************************************/ + if (RxFifo0ITs != 0U) + { + /* Clear the Rx FIFO 0 flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs); +#else + /* Rx FIFO 0 Callback */ + HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Rx FIFO 1 interrupts management ******************************************/ + if (RxFifo1ITs != 0U) + { + /* Clear the Rx FIFO 1 flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs); +#else + /* Rx FIFO 1 Callback */ + HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Tx FIFO empty interrupt management ***************************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET) + { + /* Clear the Tx FIFO empty flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxFifoEmptyCallback(hfdcan); +#else + /* Tx FIFO empty Callback */ + HAL_FDCAN_TxFifoEmptyCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Transmission Complete interrupt management *******************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET) + { + /* List of transmitted monitored buffers */ + TransmittedBuffers = hfdcan->Instance->TXBTO; + TransmittedBuffers &= hfdcan->Instance->TXBTIE; + + /* Clear the Transmission Complete flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers); +#else + /* Transmission Complete Callback */ + HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Rx Buffer New Message interrupt management *******************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET) + { + /* Clear the Rx Buffer New Message flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->RxBufferNewMessageCallback(hfdcan); +#else + /* Rx Buffer New Message Callback */ + HAL_FDCAN_RxBufferNewMessageCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Timestamp Wraparound interrupt management ********************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET) + { + /* Clear the Timestamp Wraparound flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TimestampWraparoundCallback(hfdcan); +#else + /* Timestamp Wraparound Callback */ + HAL_FDCAN_TimestampWraparoundCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Timeout Occurred interrupt management ************************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET) + { + /* Clear the Timeout Occurred flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TimeoutOccurredCallback(hfdcan); +#else + /* Timeout Occurred Callback */ + HAL_FDCAN_TimeoutOccurredCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Message RAM access failure interrupt management **************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET) + { + /* Clear the Message RAM access failure flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE); + + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS; + } + } + + /* Error Status interrupts management ***************************************/ + if (ErrorStatusITs != 0U) + { + /* Clear the Error flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs); +#else + /* Error Status Callback */ + HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Error interrupts management **********************************************/ + if (Errors != 0U) + { + /* Clear the Error flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors); + + /* Update error code */ + hfdcan->ErrorCode |= Errors; + } + + if (hfdcan->Instance == FDCAN1) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U) + { + TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK; + TTSchedSyncITs &= hfdcan->ttcan->TTIE; + TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK; + TTTimeMarkITs &= hfdcan->ttcan->TTIE; + TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK; + TTGlobTimeITs &= hfdcan->ttcan->TTIE; + TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK; + TTDistErrors &= hfdcan->ttcan->TTIE; + TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK; + TTFatalErrors &= hfdcan->ttcan->TTIE; + itsourceTTIE = hfdcan->ttcan->TTIE; + itflagTTIR = hfdcan->ttcan->TTIR; + + /* TT Schedule Synchronization interrupts management **********************/ + if (TTSchedSyncITs != 0U) + { + /* Clear the TT Schedule Synchronization flags */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs); +#else + /* TT Schedule Synchronization Callback */ + HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* TT Time Mark interrupts management *************************************/ + if (TTTimeMarkITs != 0U) + { + /* Clear the TT Time Mark flags */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs); +#else + /* TT Time Mark Callback */ + HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* TT Stop Watch interrupt management *************************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET) + { + /* Retrieve Stop watch Time and Cycle count */ + SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos); + SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos); + + /* Clear the TT Stop Watch flag */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount); +#else + /* TT Stop Watch Callback */ + HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* TT Global Time interrupts management ***********************************/ + if (TTGlobTimeITs != 0U) + { + /* Clear the TT Global Time flags */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs); +#else + /* TT Global Time Callback */ + HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* TT Disturbing Error interrupts management ******************************/ + if (TTDistErrors != 0U) + { + /* Clear the TT Disturbing Error flags */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors); + + /* Update error code */ + hfdcan->ErrorCode |= TTDistErrors; + } + + /* TT Fatal Error interrupts management ***********************************/ + if (TTFatalErrors != 0U) + { + /* Clear the TT Fatal Error flags */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors); + + /* Update error code */ + hfdcan->ErrorCode |= TTFatalErrors; + } + } + } + + if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE) + { +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->ErrorCallback(hfdcan); +#else + /* Error Callback */ + HAL_FDCAN_ErrorCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group6 Callback functions + * @brief FDCAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_FDCAN_ClockCalibrationCallback + (+) HAL_FDCAN_TxEventFifoCallback + (+) HAL_FDCAN_RxFifo0Callback + (+) HAL_FDCAN_RxFifo1Callback + (+) HAL_FDCAN_TxFifoEmptyCallback + (+) HAL_FDCAN_TxBufferCompleteCallback + (+) HAL_FDCAN_TxBufferAbortCallback + (+) HAL_FDCAN_RxBufferNewMessageCallback + (+) HAL_FDCAN_HighPriorityMessageCallback + (+) HAL_FDCAN_TimestampWraparoundCallback + (+) HAL_FDCAN_TimeoutOccurredCallback + (+) HAL_FDCAN_ErrorCallback + (+) HAL_FDCAN_ErrorStatusCallback + (+) HAL_FDCAN_TT_ScheduleSyncCallback + (+) HAL_FDCAN_TT_TimeMarkCallback + (+) HAL_FDCAN_TT_StopWatchCallback + (+) HAL_FDCAN_TT_GlobalTimeCallback + +@endverbatim + * @{ + */ + +/** + * @brief Clock Calibration callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ClkCalibrationITs indicates which Clock Calibration interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(ClkCalibrationITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Event callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(TxEventFifoITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file + */ +} + +/** + * @brief Rx FIFO 0 callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(RxFifo0ITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxFifo0Callback could be implemented in the user file + */ +} + +/** + * @brief Rx FIFO 1 callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(RxFifo1ITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxFifo1Callback could be implemented in the user file + */ +} + +/** + * @brief Tx FIFO Empty callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission Complete callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndexes Indexes of the transmitted buffers. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval None + */ +__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(BufferIndexes); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission Cancellation callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndexes Indexes of the aborted buffers. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval None + */ +__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(BufferIndexes); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Buffer New Message callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +/** + * @brief Timestamp Wraparound callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file + */ +} + +/** + * @brief Timeout Occurred callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file + */ +} + +/** + * @brief High Priority Message callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file + */ +} + +/** + * @brief Error callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Error status callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ErrorStatusITs indicates which Error Status interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(ErrorStatusITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file + */ +} + +/** + * @brief TT Schedule Synchronization callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(TTSchedSyncITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file + */ +} + +/** + * @brief TT Time Mark callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(TTTimeMarkITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file + */ +} + +/** + * @brief TT Stop Watch callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param SWTime Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising + * edge (as configured via HAL_FDCAN_TTConfigStopWatch). + * This parameter is a number between 0 and 0xFFFF. + * @param SWCycleCount Cycle count value captured together with SWTime. + * This parameter is a number between 0 and 0x3F. + * @retval None + */ +__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(SWTime); + UNUSED(SWCycleCount); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file + */ +} + +/** + * @brief TT Global Time callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TTGlobTimeITs indicates which TT Global Time interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(TTGlobTimeITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions + * @brief FDCAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) HAL_FDCAN_GetState() : Return the FDCAN state. + (+) HAL_FDCAN_GetError() : Return the FDCAN error code if any. + +@endverbatim + * @{ + */ +/** + * @brief Return the FDCAN state + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL state + */ +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan) +{ + /* Return FDCAN state */ + return hfdcan->State; +} + +/** + * @brief Return the FDCAN error code + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval FDCAN Error Code + */ +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan) +{ + /* Return FDCAN error code */ + return hfdcan->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FDCAN_Private_Functions FDCAN Private Functions + * @{ + */ + +/** + * @brief Calculate each RAM block start address and size + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t RAMcounter; + uint32_t StartAddress; + + StartAddress = hfdcan->Init.MessageRAMOffset; + + /* Standard filter list start address */ + MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos)); + + /* Standard filter elements number */ + MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos)); + + /* Extended filter list start address */ + StartAddress += hfdcan->Init.StdFiltersNbr; + MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos)); + + /* Extended filter elements number */ + MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos)); + + /* Rx FIFO 0 start address */ + StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U); + MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos)); + + /* Rx FIFO 0 elements number */ + MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos)); + + /* Rx FIFO 1 start address */ + StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize); + MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos)); + + /* Rx FIFO 1 elements number */ + MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos)); + + /* Rx buffer list start address */ + StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize); + MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos)); + + /* Tx event FIFO start address */ + StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize); + MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos)); + + /* Tx event FIFO elements number */ + MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos)); + + /* Tx buffer list start address */ + StartAddress += (hfdcan->Init.TxEventsNbr * 2U); + MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos)); + + /* Dedicated Tx buffers number */ + MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos)); + + /* Tx FIFO/queue elements number */ + MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos)); + + hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U); + hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U); + hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U); + hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U); + hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U); + hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U); + hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U); + hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U); + + hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U); + + if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */ + { + /* Update error code. + Message RAM overflow */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + else + { + /* Flush the allocated Message RAM area */ + for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U) + { + *(uint32_t *)(RAMcounter) = 0x00000000; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Copy Tx message to the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. + * @param pTxData pointer to a buffer containing the payload of the Tx frame. + * @param BufferIndex index of the buffer to be configured. + * @retval none + */ +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex) +{ + uint32_t TxElementW1; + uint32_t TxElementW2; + uint32_t *TxAddress; + uint32_t ByteCounter; + + /* Build first word of Tx header element */ + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + TxElementW1 = (pTxHeader->ErrorStateIndicator | + FDCAN_STANDARD_ID | + pTxHeader->TxFrameType | + (pTxHeader->Identifier << 18U)); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + TxElementW1 = (pTxHeader->ErrorStateIndicator | + FDCAN_EXTENDED_ID | + pTxHeader->TxFrameType | + pTxHeader->Identifier); + } + + /* Build second word of Tx header element */ + TxElementW2 = ((pTxHeader->MessageMarker << 24U) | + pTxHeader->TxEventFifoControl | + pTxHeader->FDFormat | + pTxHeader->BitRateSwitch | + (pTxHeader->DataLength << 16U)); + + /* Calculate Tx element address */ + TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U)); + + /* Write Tx element header to the message RAM */ + *TxAddress = TxElementW1; + TxAddress++; + *TxAddress = TxElementW2; + TxAddress++; + + /* Write Tx payload to the message RAM */ + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U) + { + *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) | + ((uint32_t)pTxData[ByteCounter + 2U] << 16U) | + ((uint32_t)pTxData[ByteCounter + 1U] << 8U) | + (uint32_t)pTxData[ByteCounter]); + TxAddress++; + } +} + +/** + * @} + */ +#endif /* HAL_FDCAN_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* FDCAN1 */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c new file mode 100644 index 0000000..3706941 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c @@ -0,0 +1,1270 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Option bytes programming + (+) Error code correction (ECC) : Data in flash are 266-bits word + (10 bits added per flash word) + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32H7xx devices. + + (#) FLASH Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: 256-bit word only + (++) There Two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_FLASH_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. + In this case, a reset is generated + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + [..] + (@) For any Flash memory program operation (erase or program), the CPU clock frequency + (HCLK) must be at least 1MHz. + (@) The contents of the Flash memory are not guaranteed if a device reset occurs during + a Flash memory operation. + (@) The application can simultaneously request a read and a write operation through each AXI + interface. + As the Flash memory is divided into two independent banks, the embedded Flash + memory interface can drive different operations at the same time on each bank. For + example a read, write or erase operation can be executed on bank 1 while another read, + write or erase operation is executed on bank 2. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Functions FLASH Exported functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program a flash word at a specified address + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param FlashAddress specifies the address to be programmed. + * This parameter shall be aligned to the Flash word: + * - 256 bits for STM32H74x/5X devices (8x 32bits words) + * - 128 bits for STM32H7Ax/BX devices (4x 32bits words) + * - 256 bits for STM32H72x/3X devices (8x 32bits words) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress; + __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; + uint32_t bank; + uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + +#if defined (FLASH_OPTCR_PG_OTP) + if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress))) +#else + if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) +#endif /* FLASH_OPTCR_PG_OTP */ + { + bank = FLASH_BANK_1; + /* Prevent unused argument(s) compilation warning */ + UNUSED(TypeProgram); + } +#if defined (DUAL_BANK) + else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) + { + bank = FLASH_BANK_2; + } +#endif /* DUAL_BANK */ + else + { + return HAL_ERROR; + } + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + + if(status == HAL_OK) + { +#if defined (DUAL_BANK) + if(bank == FLASH_BANK_1) + { +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } + } + else + { + /* Set PG bit */ + SET_BIT(FLASH->CR2, FLASH_CR_PG); + } +#else /* Single Bank */ +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } +#endif /* DUAL_BANK */ + + __ISB(); + __DSB(); + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Program an OTP word (16 bits) */ + *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress; + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Program the flash word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); + } + + __ISB(); + __DSB(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + +#if defined (DUAL_BANK) +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* If the program operation is completed, disable the OTP_PG */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + if(bank == FLASH_BANK_1) + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); + } + else + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR2, FLASH_CR_PG); + } + } +#else /* Single Bank */ +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* If the program operation is completed, disable the OTP_PG */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); + } +#endif /* DUAL_BANK */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program a flash word at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param FlashAddress specifies the address to be programmed. + * This parameter shall be aligned to the Flash word: + * - 256 bits for STM32H74x/5X devices (8x 32bits words) + * - 128 bits for STM32H7Ax/BX devices (4x 32bits words) + * - 256 bits for STM32H72x/3X devices (8x 32bits words) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *dest_addr = (__IO uint32_t*)FlashAddress; + __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; + uint32_t bank; + uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined (FLASH_OPTCR_PG_OTP) + if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress))) +#else + if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) +#endif /* FLASH_OPTCR_PG_OTP */ + { + bank = FLASH_BANK_1; + /* Prevent unused argument(s) compilation warning */ + UNUSED(TypeProgram); + } +#if defined (DUAL_BANK) + else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) + { + bank = FLASH_BANK_2; + } +#endif /* DUAL_BANK */ + else + { + return HAL_ERROR; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + pFlash.Address = FlashAddress; + +#if defined (DUAL_BANK) + if(bank == FLASH_BANK_1) + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1; + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } + + /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2; + + /* Set PG bit */ + SET_BIT(FLASH->CR2, FLASH_CR_PG); + + /* Enable End of Operation and Error interrupts for Bank2 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#else + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* FLASH_CR_OPERRIE */ + } +#else /* Single Bank */ + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1; + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } + + /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ +#endif /* DUAL_BANK */ + + __ISB(); + __DSB(); + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Program an OTP word (16 bits) */ + *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress; + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Program the flash word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); + } + + __ISB(); + __DSB(); + } + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t temp; + uint32_t errorflag; + FLASH_ProcedureTypeDef procedure; + + /* Check FLASH Bank1 End of Operation flag */ + if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1) + { + /* Nb of sector to erased can be decreased */ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase */ + if(pFlash.NbSectorsToErase != 0U) + { + /* Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear bank 1 End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + + /* Increment sector number */ + pFlash.Sector++; + temp = pFlash.Sector; + FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase); + } + else + { + /* No more sectors to Erase, user callback can be called */ + /* Reset Sector and stop Erase sectors procedure */ + pFlash.Sector = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + } + } + else + { + procedure = pFlash.ProcedureOnGoing; + + if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /* MassErase ended. Return the selected bank */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1); + } + else if(procedure == FLASH_PROC_PROGRAM_BANK1) + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else + { + /* Nothing to do */ + } + + if((procedure != FLASH_PROC_SECTERASE_BANK2) && \ + (procedure != FLASH_PROC_MASSERASE_BANK2) && \ + (procedure != FLASH_PROC_PROGRAM_BANK2)) + { + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + } + } + } + +#if defined (DUAL_BANK) + /* Check FLASH Bank2 End of Operation flag */ + if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2) + { + /*Nb of sector to erased can be decreased*/ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase*/ + if(pFlash.NbSectorsToErase != 0U) + { + /*Indicate user which sector has been erased*/ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear bank 2 End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + + /*Increment sector number*/ + pFlash.Sector++; + temp = pFlash.Sector; + FLASH_Erase_Sector(temp, FLASH_BANK_2, pFlash.VoltageForErase); + } + else + { + /* No more sectors to Erase, user callback can be called */ + /* Reset Sector and stop Erase sectors procedure */ + pFlash.Sector = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + } + } + else + { + procedure = pFlash.ProcedureOnGoing; + + if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /*MassErase ended. Return the selected bank*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2); + } + else if(procedure == FLASH_PROC_PROGRAM_BANK2) + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else + { + /* Nothing to do */ + } + + if((procedure != FLASH_PROC_SECTERASE_BANK1) && \ + (procedure != FLASH_PROC_MASSERASE_BANK1) && \ + (procedure != FLASH_PROC_PROGRAM_BANK1)) + { + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + } + } + } +#endif /* DUAL_BANK */ + + /* Check FLASH Bank1 operation error flags */ +#if defined (FLASH_SR_OPERR) + errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \ + FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1); +#else + errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \ + FLASH_FLAG_INCERR_BANK1); +#endif /* FLASH_SR_OPERR */ + + if(errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= errorflag; + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag); + + procedure = pFlash.ProcedureOnGoing; + + if(procedure == FLASH_PROC_SECTERASE_BANK1) + { + /* Return the faulty sector */ + temp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + } + else if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /* Return the faulty bank */ + temp = FLASH_BANK_1; + } + else + { + /* Return the faulty address */ + temp = pFlash.Address; + } + + /* Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(temp); + } + +#if (USE_FLASH_ECC == 1U) + /* Check FLASH Bank1 ECC single correction error flag */ + errorflag = FLASH->SR1 & FLASH_FLAG_SNECCERR_BANK1; + + if(errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= errorflag; + + /* Call User callback */ + HAL_FLASHEx_EccCorrectionCallback(); + + /* Clear FLASH Bank1 ECC single correction error flag in order to allow new ECC error record */ + __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag); + } + + /* Check FLASH Bank1 ECC double detection error flag */ + errorflag = FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1; + + if(errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= errorflag; + + /* Call User callback */ + HAL_FLASHEx_EccDetectionCallback(); + + /* Clear FLASH Bank1 ECC double detection error flag in order to allow new ECC error record */ + __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag); + } +#endif /* USE_FLASH_ECC */ + +#if defined (DUAL_BANK) + /* Check FLASH Bank2 operation error flags */ +#if defined (FLASH_SR_OPERR) + errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \ + FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU); +#else + errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \ + FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU); +#endif /* FLASH_SR_OPERR */ + + if(errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= (errorflag | 0x80000000U); + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag); + + procedure = pFlash.ProcedureOnGoing; + + if(procedure== FLASH_PROC_SECTERASE_BANK2) + { + /*return the faulty sector*/ + temp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + } + else if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /*return the faulty bank*/ + temp = FLASH_BANK_2; + } + else + { + /*return the faulty address*/ + temp = pFlash.Address; + } + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(temp); + } + +#if (USE_FLASH_ECC == 1U) + /* Check FLASH Bank2 ECC single correction error flag */ + errorflag = FLASH->SR2 & FLASH_FLAG_SNECCERR_BANK2; + + if(errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= (errorflag | 0x80000000U); + + /* Call User callback */ + HAL_FLASHEx_EccCorrectionCallback(); + + /* Clear FLASH Bank2 ECC single correction error flag in order to allow new ECC error record */ + __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag); + } + + /* Check FLASH Bank2 ECC double detection error flag */ + errorflag = FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2; + + if(errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= (errorflag | 0x80000000U); + + /* Call User callback */ + HAL_FLASHEx_EccDetectionCallback(); + + /* Clear FLASH Bank2 ECC double detection error flag in order to allow new ECC error record */ + __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag); + } + +#endif /* USE_FLASH_ECC */ +#endif /* DUAL_BANK */ + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { +#if defined (FLASH_CR_OPERRIE) + /* Disable Bank1 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); + +#if defined (DUAL_BANK) + /* Disable Bank2 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#endif /* DUAL_BANK */ +#else + /* Disable Bank1 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); + +#if defined (DUAL_BANK) + /* Disable Bank2 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* DUAL_BANK */ +#endif /* FLASH_CR_OPERRIE */ + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector which has been erased + * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank1 Registers access */ + WRITE_REG(FLASH->KEYR1, FLASH_KEY1); + WRITE_REG(FLASH->KEYR1, FLASH_KEY2); + + /* Verify Flash Bank1 is unlocked */ + if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } + +#if defined (DUAL_BANK) + if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank2 Registers access */ + WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + + /* Verify Flash Bank2 is unlocked */ + if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + return HAL_OK; +} + +/** + * @brief Locks the FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Bank1 Control Register access */ + SET_BIT(FLASH->CR1, FLASH_CR_LOCK); + + /* Verify Flash Bank1 is locked */ + if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) == 0U) + { + return HAL_ERROR; + } + +#if defined (DUAL_BANK) + /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */ + SET_BIT(FLASH->CR2, FLASH_CR_LOCK); + + /* Verify Flash Bank2 is locked */ + if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) == 0U) + { + return HAL_ERROR; + } +#endif /* DUAL_BANK */ + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte registers programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2); + + /* Verify that the Option Bytes are unlocked */ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK); + + /* Verify that the Option Bytes are locked */ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Launch the option bytes loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + HAL_StatusTypeDef status; + + /* Wait for CRC computation to be completed */ + if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } +#if defined (DUAL_BANK) + else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } +#endif /* DUAL_BANK */ + else + { + status = HAL_OK; + } + + if (status == HAL_OK) + { + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART); + + /* Wait for OB change operation to be completed */ + status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval HAL_FLASH_ERRORCode The returned value can be: + * @arg HAL_FLASH_ERROR_NONE : No error set + * + * @arg HAL_FLASH_ERROR_WRP_BANK1 : Write Protection Error on Bank 1 + * @arg HAL_FLASH_ERROR_PGS_BANK1 : Program Sequence Error on Bank 1 + * @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1 + * @arg HAL_FLASH_ERROR_INC_BANK1 : Inconsistency Error on Bank 1 + * @arg HAL_FLASH_ERROR_OPE_BANK1 : Operation Error on Bank 1 + * @arg HAL_FLASH_ERROR_RDP_BANK1 : Read Protection Error on Bank 1 + * @arg HAL_FLASH_ERROR_RDS_BANK1 : Read Secured Error on Bank 1 + * @arg HAL_FLASH_ERROR_SNECC_BANK1: ECC Single Correction Error on Bank 1 + * @arg HAL_FLASH_ERROR_DBECC_BANK1: ECC Double Detection Error on Bank 1 + * @arg HAL_FLASH_ERROR_CRCRD_BANK1: CRC Read Error on Bank 1 + * + * @arg HAL_FLASH_ERROR_WRP_BANK2 : Write Protection Error on Bank 2 + * @arg HAL_FLASH_ERROR_PGS_BANK2 : Program Sequence Error on Bank 2 + * @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2 + * @arg HAL_FLASH_ERROR_INC_BANK2 : Inconsistency Error on Bank 2 + * @arg HAL_FLASH_ERROR_OPE_BANK2 : Operation Error on Bank 2 + * @arg HAL_FLASH_ERROR_RDP_BANK2 : Read Protection Error on Bank 2 + * @arg HAL_FLASH_ERROR_RDS_BANK2 : Read Secured Error on Bank 2 + * @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2 + * @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2 + * @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2 + */ + +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @param Bank flash FLASH_BANK_1 or FLASH_BANK_2 + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) +{ + /* Wait for the FLASH operation to complete by polling on QW flag to be reset. + Even if the FLASH operation fails, the QW flag will be reset and an error + flag will be set */ + + uint32_t bsyflag = FLASH_FLAG_QW_BANK1; + uint32_t errorflag = 0; + uint32_t tickstart = HAL_GetTick(); + + assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); + +#if defined (DUAL_BANK) + + if (Bank == FLASH_BANK_2) + { + /* Select bsyflag depending on Bank */ + bsyflag = FLASH_FLAG_QW_BANK2; + } +#endif /* DUAL_BANK */ + + while(__HAL_FLASH_GET_FLAG(bsyflag)) + { + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Get Error Flags */ + if (Bank == FLASH_BANK_1) + { + errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1; + } +#if defined (DUAL_BANK) + else + { + errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U; + } +#endif /* DUAL_BANK */ + + /* In case of error reported in Flash SR1 or SR2 register */ + if((errorflag & 0x7FFFFFFFU) != 0U) + { + /*Save the error code*/ + pFlash.ErrorCode |= errorflag; + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(errorflag); + + return HAL_ERROR; + } + + /* Check FLASH End of Operation flag */ + if(Bank == FLASH_BANK_1) + { + if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + } + } +#if defined (DUAL_BANK) + else + { + if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + } + } +#endif /* DUAL_BANK */ + + return HAL_OK; +} + +/** + * @brief Wait for a FLASH Option Bytes change operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout) +{ + /* Get timeout */ + uint32_t tickstart = HAL_GetTick(); + + /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be reset */ + while(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPT_BUSY) != 0U) + { + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check option byte change error */ + if(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPTCHANGEERR) != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE; + + /* Clear the OB error flag */ + FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR; + + return HAL_ERROR; + } + + /* If there is no error flag set */ + return HAL_OK; +} + +/** + * @brief Wait for a FLASH CRC computation to complete. + * @param Timeout maximum flash operation timeout + * @param Bank flash FLASH_BANK_1 or FLASH_BANK_2 + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) +{ + uint32_t bsyflag; + uint32_t tickstart = HAL_GetTick(); + + assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); + + /* Select bsyflag depending on Bank */ + if(Bank == FLASH_BANK_1) + { + bsyflag = FLASH_FLAG_CRC_BUSY_BANK1; + } + else + { + bsyflag = FLASH_FLAG_CRC_BUSY_BANK2; + } + + /* Wait for the FLASH CRC computation to complete by polling on CRC_BUSY flag to be reset */ + while(__HAL_FLASH_GET_FLAG(bsyflag)) + { + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH CRC read error flag */ + if(Bank == FLASH_BANK_1) + { + if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1)) + { + /* Save the error code */ + pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK1; + + /* Clear FLASH CRC read error pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1); + + return HAL_ERROR; + } + } +#if defined (DUAL_BANK) + else + { + if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2)) + { + /* Save the error code */ + pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK2; + + /* Clear FLASH CRC read error pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2); + + return HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + /* If there is no error flag set */ + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c new file mode 100644 index 0000000..e72871f --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c @@ -0,0 +1,2115 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extension peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32H7xx + devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) PCROP protection for all banks + (+) Global readout protection (RDP) + (+) Write protection + (+) Secure access only protection + (+) Bank / register swapping (when Dual-Bank) + (+) Cyclic Redundancy Check (CRC) + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32H7xx devices. It includes + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Sector erase, bank erase and dual-bank mass erase + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to: + (++) Set/Reset the write protection per bank + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + (++) PCROP protection configuration and control per bank + (++) Secure area configuration and control per bank + (++) Core Boot address configuration + (++) TCM / AXI shared RAM configuration + (++) CPU Frequency Boost configuration + + (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(), + HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions + + (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to: + (++) Enable CRC feature + (++) Program the desired burst size + (++) Define the user Flash Area on which the CRC has be computed + (++) Perform the CRC computation + (++) Disable CRC feature + + (#) Error correction code error functions: + (++) Use the HAL_FLASHEx_EnableEccCorrectionInterrupt() and HAL_FLASHEx_DisableEccCorrectionInterrupt() + functions to enable and disable the FLASH ECC correction interruption. + (++) Use the HAL_FLASHEx_EnableEccDetectionInterrupt() and HAL_FLASHEx_DisableEccDetectionInterrupt() + functions to enable and disable the FLASH ECC Detection interruption. + (++) Handle ECCD interrupt by calling HAL_FLASHEx_BusFault_IRQHandler() + (++) Use HAL_FLASHEx_BusFault_IRQHandler() function called under BusFault_IRQHandler() interrupt subroutine + to handle the ECCD interrupt. + (++) Use HAL_FLASHEx_GetEccInfo() function to get the flash ECC fail information. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks); +static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks); +static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank); +static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank); +static void FLASH_OB_RDPConfig(uint32_t RDPLevel); +static uint32_t FLASH_OB_GetRDP(void); +static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks); +static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank); +static void FLASH_OB_BOR_LevelConfig(uint32_t Level); +static uint32_t FLASH_OB_GetBOR(void); +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); +static uint32_t FLASH_OB_GetUser(void); +static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1); +static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1); +static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks); +static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank); +static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank); +static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank); + +#if defined (DUAL_CORE) +static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1); +static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1); +#endif /*DUAL_CORE*/ + +#if defined (FLASH_OTPBL_LOCKBL) +static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block); +static uint32_t FLASH_OB_OTP_GetLock(void); +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig); +static uint32_t FLASH_OB_SharedRAM_GetConfig(void); +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost); +static uint32_t FLASH_OB_CPUFreq_GetBoost(void); +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extension FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that contains the configuration + * information on faulty sector in case of error (0xFFFFFFFF means that all + * the sectors have been correctly erased) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t sector_index; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_BANK(pEraseInit->Banks)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed on Bank1 */ + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } + } + +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank2 */ + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + if(status == HAL_OK) + { + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); + + /* Wait for last operation to be completed on Bank 1 */ + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } + /* if the erase operation is completed, disable the Bank1 BER Bit */ + FLASH->CR1 &= (~FLASH_CR_BER); + } +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank 2 */ + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } + /* if the erase operation is completed, disable the Bank2 BER Bit */ + FLASH->CR2 &= (~FLASH_CR_BER); + } +#endif /* DUAL_BANK */ + } + else + { + /*Initialization of SectorError variable*/ + *SectorError = 0xFFFFFFFFU; + + /* Erase by sector by sector to be done*/ + for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++) + { + FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange); + + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1); + + /* If the erase operation is completed, disable the SER Bit */ + FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); + } +#if defined (DUAL_BANK) + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2); + + /* If the erase operation is completed, disable the SER Bit */ + FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); + } +#endif /* DUAL_BANK */ + + if(status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector */ + *SectorError = sector_index; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_BANK(pEraseInit->Banks)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed on Bank 1 */ + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } + } + +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank 2 */ + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ + } +#if defined (DUAL_BANK) + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Enable End of Operation and Error interrupts for Bank 2 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#else + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* FLASH_CR_OPERRIE */ + } +#endif /* DUAL_BANK */ + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + if(pEraseInit->Banks == FLASH_BANK_1) + { + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1; + } +#if defined (DUAL_BANK) + else if(pEraseInit->Banks == FLASH_BANK_2) + { + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2; + } +#endif /* DUAL_BANK */ + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE; + } + + FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); + } + else + { + /* Erase by sector to be done */ +#if defined (DUAL_BANK) + if(pEraseInit->Banks == FLASH_BANK_1) + { + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2; + } +#else + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; +#endif /* DUAL_BANK */ + + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + pFlash.VoltageForErase = pEraseInit->VoltageRange; + + /* Erase first sector and wait for IT */ + FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange); + } + } + + return status; +} + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset Error Code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } +#if defined (DUAL_BANK) + else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } +#endif /* DUAL_BANK */ + else + { + status = HAL_OK; + } + + if(status == HAL_OK) + { + /*Write protection configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + + if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks); + } + else + { + /*Disable of Write protection on the selected Sector*/ + FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) + { + /* Configure the Read protection level */ + FLASH_OB_RDPConfig(pOBInit->RDPLevel); + } + + /* User Configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) + { + /* Configure the user option bytes */ + FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig); + } + + /* PCROP Configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) + { + assert_param(IS_FLASH_BANK(pOBInit->Banks)); + + /*Configure the Proprietary code readout protection */ + FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks); + } + + /* BOR Level configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + } + +#if defined(DUAL_CORE) + /* CM7 Boot Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD) + { + FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); + } + + /* CM4 Boot Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD) + { + FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1); + } +#else /* Single Core*/ + /* Boot Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD) + { + FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); + } +#endif /*DUAL_CORE*/ + + /* Secure area configuration */ + if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA) + { + FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks); + } + +#if defined(FLASH_OTPBL_LOCKBL) + /* OTP Block Lock configuration */ + if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK) + { + FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock); + } +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined(FLASH_OPTSR2_TCM_AXI_SHARED) + /* TCM / AXI Shared RAM configuration */ + if((pOBInit->OptionType & OPTIONBYTE_SHARED_RAM) == OPTIONBYTE_SHARED_RAM) + { + FLASH_OB_SharedRAM_Config(pOBInit->SharedRamConfig); + } +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined(FLASH_OPTSR2_CPUFREQ_BOOST) + /* CPU Frequency Boost configuration */ + if((pOBInit->OptionType & OPTIONBYTE_FREQ_BOOST) == OPTIONBYTE_FREQ_BOOST) + { + FLASH_OB_CPUFreq_BoostConfig(pOBInit->FreqBoostState); + } +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2, + * as this parameter is use to get the given Bank WRP, PCROP and secured area configuration. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR); + + /* Get Read protection level */ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /* Get the user option bytes */ + pOBInit->USERConfig = FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = FLASH_OB_GetBOR(); + +#if defined (DUAL_BANK) + if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2)) +#else + if (pOBInit->Banks == FLASH_BANK_1) +#endif /* DUAL_BANK */ + { + pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA); + + /* Get write protection on the selected area */ + FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks); + + /* Get the Proprietary code readout protection */ + FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks); + + /*Get Bank Secure area*/ + FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks); + } + + /*Get Boot Address*/ + FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1)); +#if defined(DUAL_CORE) + pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD; + + /*Get CM4 Boot Address*/ + FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1)); +#else + pOBInit->OptionType |= OPTIONBYTE_BOOTADD; +#endif /*DUAL_CORE*/ + +#if defined (FLASH_OTPBL_LOCKBL) + pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK; + + /* Get OTP Block Lock */ + pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock(); +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + pOBInit->OptionType |= OPTIONBYTE_SHARED_RAM; + + /* Get TCM / AXI Shared RAM */ + pOBInit->SharedRamConfig = FLASH_OB_SharedRAM_GetConfig(); +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + pOBInit->OptionType |= OPTIONBYTE_FREQ_BOOST; + + /* Get CPU Frequency Boost */ + pOBInit->FreqBoostState = FLASH_OB_CPUFreq_GetBoost(); +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ +} + +/** + * @brief Unlock the FLASH Bank1 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void) +{ + if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank1 Registers access */ + WRITE_REG(FLASH->KEYR1, FLASH_KEY1); + WRITE_REG(FLASH->KEYR1, FLASH_KEY2); + + /* Verify Flash Bank1 is unlocked */ + if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Locks the FLASH Bank1 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void) +{ + /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */ + SET_BIT(FLASH->CR1, FLASH_CR_LOCK); + return HAL_OK; +} + +#if defined (DUAL_BANK) +/** + * @brief Unlock the FLASH Bank2 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void) +{ + if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank2 Registers access */ + WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + + /* Verify Flash Bank1 is unlocked */ + if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Locks the FLASH Bank2 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void) +{ + /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */ + SET_BIT(FLASH->CR2, FLASH_CR_LOCK); + return HAL_OK; +} +#endif /* DUAL_BANK */ + +/* + * @brief Perform a CRC computation on the specified FLASH memory area + * @param pCRCInit pointer to an FLASH_CRCInitTypeDef structure that + * contains the configuration information for the CRC computation. + * @note CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7 + * @note The application should avoid running a CRC on PCROP or secure-only + * user Flash memory area since it may alter the expected CRC value. + * A special error flag (CRC read error: CRCRDERR) can be used to + * detect such a case. + * @retval HAL Status +*/ +HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result) +{ + HAL_StatusTypeDef status; + uint32_t sector_index; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank)); + assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC)); + + /* Wait for OB change operation to be completed */ + status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (pCRCInit->Bank == FLASH_BANK_1) + { + /* Enable CRC feature */ + FLASH->CR1 |= FLASH_CR_CRC_EN; + + /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */ + FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR); + + /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */ + FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC; + + if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS) + { + /* Clear sectors list */ + FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT; + + /* Select CRC sectors */ + for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++) + { + FLASH_CRC_AddSector(sector_index, FLASH_BANK_1); + } + } + else if (pCRCInit->TypeCRC == FLASH_CRC_BANK) + { + /* Enable Bank 1 CRC select bit */ + FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK; + } + else + { + /* Select CRC start and end addresses */ + FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1); + } + + /* Start the CRC calculation */ + FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC; + + /* Wait on CRC busy flag */ + status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1); + + /* Return CRC result */ + (*CRC_Result) = FLASH->CRCDATA; + + /* Disable CRC feature */ + FLASH->CR1 &= (~FLASH_CR_CRC_EN); + + /* Clear CRC flags */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1); + } +#if defined (DUAL_BANK) + else + { + /* Enable CRC feature */ + FLASH->CR2 |= FLASH_CR_CRC_EN; + + /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */ + FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR); + + /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */ + FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC; + + if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS) + { + /* Clear sectors list */ + FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT; + + /* Add CRC sectors */ + for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++) + { + FLASH_CRC_AddSector(sector_index, FLASH_BANK_2); + } + } + else if (pCRCInit->TypeCRC == FLASH_CRC_BANK) + { + /* Enable Bank 2 CRC select bit */ + FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK; + } + else + { + /* Select CRC start and end addresses */ + FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2); + } + + /* Start the CRC calculation */ + FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC; + + /* Wait on CRC busy flag */ + status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2); + + /* Return CRC result */ + (*CRC_Result) = FLASH->CRCDATA; + + /* Disable CRC feature */ + FLASH->CR2 &= (~FLASH_CR_CRC_EN); + + /* Clear CRC flags */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2); + } +#endif /* DUAL_BANK */ + } + + return status; +} + +/** + * @} + */ + +#if (USE_FLASH_ECC == 1U) +/** @defgroup FLASHEx_Exported_Functions_Group2 Extended ECC operation functions + * @brief Extended ECC operation functions + * +@verbatim + =============================================================================== + ##### Extended ECC operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + ECC Operations. + +@endverbatim + * @{ + */ + +/** + * @brief Enable ECC correction interrupts on FLASH BANK1 and BANK2. + * @param None + * @retval None + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1); + +#if defined (DUAL_BANK) + __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2); +#endif /* DUAL_BANK */ +} + +/** + * @brief Disable ECC correction interrupts on FLASH BANK1 and BANK2. + * @param None + * @retval None + */ +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1); + +#if defined (DUAL_BANK) + __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2); +#endif /* DUAL_BANK */ +} + +/** + * @brief Enable ECC correction interrupt on FLASH BANK1. + * @param None + * @retval None + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1); +} + +/** + * @brief Disable ECC correction interrupt on FLASH BANK1. + * @param None + * @retval None + */ +void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1); +} + +#if defined (DUAL_BANK) +/** + * @brief Enable ECC correction interrupt on FLASH BANK2. + * @param None + * @retval None + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2); +} + +/** + * @brief Disable ECC correction interrupt on FLASH BANK2. + * @param None + * @retval None + */ +void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2); +} +#endif /* DUAL_BANK */ + +/** + * @brief Enable ECC Detection interrupts on FLASH BANK1 and BANK2. + * @param None + * @retval None + */ +void HAL_FLASHEx_EnableEccDetectionInterrupt(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1); + +#if defined (DUAL_BANK) + __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2); +#endif /* DUAL_BANK */ +} + +/** + * @brief Disable ECC Detection interrupts on FLASH BANK1 and BANK2. + * @param None + * @retval None + */ +void HAL_FLASHEx_DisableEccDetectionInterrupt(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1); + +#if defined (DUAL_BANK) + __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2); +#endif /* DUAL_BANK */ +} + +/** + * @brief Enable ECC Detection interrupt on FLASH BANK1. + * @param None + * @retval None + */ +void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1); +} + +/** + * @brief Disable ECC correction interrupt on FLASH BANK1. + * @param None + * @retval None + */ +void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1); +} + +#if defined (DUAL_BANK) +/** + * @brief Enable ECC Detection interrupt on FLASH BANK2. + * @param None + * @retval None + */ +void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2); +} + +/** + * @brief Disable ECC Detection interrupt on FLASH BANK2. + * @param None + * @retval None + */ +void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2); +} +#endif /* DUAL_BANK */ + +/** + * @brief Get the ECC error information. + * @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the + * ECC error information. + * @note This function should be called before ECC bit is cleared + * (in callback function) + * @retval None + */ +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData) +{ + uint32_t errorflag; + + /* Check FLASH Bank1 ECC single correction and double detection error flags */ + errorflag = FLASH->SR1 & (FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1); + if(errorflag != 0U) + { + pData->Area = FLASH_ECC_AREA_USER_BANK1; + pData->Address = ((((FLASH->ECC_FA1 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK1_BASE); + } +#if defined (DUAL_BANK) + /* Check FLASH Bank2 ECC single correction and double detection error flags */ + errorflag = FLASH->SR2 & (FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2); + if(errorflag != 0U) + { + pData->Area = FLASH_ECC_AREA_USER_BANK2; + pData->Address = ((((FLASH->ECC_FA2 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK2_BASE); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Handle Flash ECC Detection interrupt request. + * @retval None + */ +void HAL_FLASHEx_BusFault_IRQHandler(void) +{ + /* Check if the ECC double error occurred*/ + if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1) != 0) + { + /* FLASH ECC detection user callback */ + HAL_FLASHEx_EccDetectionCallback(); + + /* Clear Bank 1 ECC double detection error flag + note : this step will clear all the information related to the flash ECC detection + */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1); + } +#if defined (DUAL_BANK) + /* Check if the ECC double error occurred*/ + if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2) != 0) + { + /* FLASH ECC detection user callback */ + HAL_FLASHEx_EccDetectionCallback(); + + /* Clear Bank 2 ECC double detection error flag + note : this step will clear all the information related to the flash ECC detection + */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief FLASH ECC Correction interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccCorrectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH ECC Detection interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccDetectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file + */ +} + +/** + * @} + */ +#endif /* USE_FLASH_ECC */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Mass erase of FLASH memory + * @param VoltageRange The device program/erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits + * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits + * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits + * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits + * + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ +#if defined (FLASH_CR_PSIZE) + assert_param(IS_VOLTAGERANGE(VoltageRange)); +#else + UNUSED(VoltageRange); +#endif /* FLASH_CR_PSIZE */ + assert_param(IS_FLASH_BANK(Banks)); + +#if defined (DUAL_BANK) + /* Flash Mass Erase */ + if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH) + { +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange for Bank1 and Bank2 */ + FLASH->CR1 &= (~FLASH_CR_PSIZE); + FLASH->CR2 &= (~FLASH_CR_PSIZE); + + /* Set voltage range */ + FLASH->CR1 |= VoltageRange; + FLASH->CR2 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ + + /* Set Mass Erase Bit */ + FLASH->OPTCR |= FLASH_OPTCR_MER; + } + else +#endif /* DUAL_BANK */ + { + /* Proceed to erase Flash Bank */ + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { +#if defined (FLASH_CR_PSIZE) + /* Set Program/erase VoltageRange for Bank1 */ + FLASH->CR1 &= (~FLASH_CR_PSIZE); + FLASH->CR1 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ + + /* Erase Bank1 */ + FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { +#if defined (FLASH_CR_PSIZE) + /* Set Program/erase VoltageRange for Bank2 */ + FLASH->CR2 &= (~FLASH_CR_PSIZE); + FLASH->CR2 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ + + /* Erase Bank2 */ + FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START); + } +#endif /* DUAL_BANK */ + } +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * This parameter can be a value of @ref FLASH_Sectors + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * @param VoltageRange The device program/erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits + * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits + * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits + * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange) +{ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); +#if defined (FLASH_CR_PSIZE) + assert_param(IS_VOLTAGERANGE(VoltageRange)); +#else + UNUSED(VoltageRange); +#endif /* FLASH_CR_PSIZE */ + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange and Sector Number for Bank1 */ + FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); + + FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#else + /* Reset Sector Number for Bank1 */ + FLASH->CR1 &= ~(FLASH_CR_SNB); + + FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#endif /* FLASH_CR_PSIZE */ + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange and Sector Number for Bank2 */ + FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); + + FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#else + /* Reset Sector Number for Bank2 */ + FLASH->CR2 &= ~(FLASH_CR_SNB); + + FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#endif /* FLASH_CR_PSIZE */ + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Enable the write protection of the desired bank1 or bank 2 sectors + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_ALL + * + * @param Banks the specific bank to apply WRP sectors + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: enable WRP on specified bank1 sectors + * @arg FLASH_BANK_2: enable WRP on specified bank2 sectors + * @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors + * + * @retval HAL FLASH State + */ +static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Enable Write Protection for bank 1 */ + FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN)); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Enable Write Protection for bank 2 */ + FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN)); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Disable the write protection of the desired bank1 or bank 2 sectors + * @param WRPSector specifies the sector(s) to disable write protection. + * This parameter can be one of the following values: + * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL + * + * @param Banks the specific bank to apply WRP sectors + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: disable WRP on specified bank1 sectors + * @arg FLASH_BANK_2: disable WRP on specified bank2 sectors + * @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors + * + * @retval HAL FLASH State + */ +static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Disable Write Protection for bank 1 */ + FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Disable Write Protection for bank 2 */ + FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Get the write protection of the given bank 1 or bank 2 sectors + * @param WRPState gives the write protection state on the given bank. + * This parameter can be one of the following values: + * @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE + + * @param WRPSector gives the write protected sector(s) on the given bank . + * This parameter can be one of the following values: + * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL + * + * @param Bank the specific bank to apply WRP sectors + * This parameter can be exclusively one of the following values: + * @arg FLASH_BANK_1: Get bank1 WRP sectors + * @arg FLASH_BANK_2: Get bank2 WRP sectors + * @arg FLASH_BANK_BOTH: note allowed in this functions + * + * @retval HAL FLASH State + */ +static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank) +{ + uint32_t regvalue = 0U; + + if(Bank == FLASH_BANK_1) + { + regvalue = FLASH->WPSN_CUR1; + } + +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) + { + regvalue = FLASH->WPSN_CUR2; + } +#endif /* DUAL_BANK */ + + (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN; + + if(*WRPSector == 0U) + { + (*WRPState) = OB_WRPSTATE_DISABLE; + } + else + { + (*WRPState) = OB_WRPSTATE_ENABLE; + } +} + +/** + * @brief Set the read protection level. + * + * @note To configure the RDP level, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the RDP level, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible + * to go back to level 1 or 0 !!! + * + * @param RDPLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @retval HAL status + */ +static void FLASH_OB_RDPConfig(uint32_t RDPLevel) +{ + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + + /* Configure the RDP level in the option bytes register */ + MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel); +} + +/** + * @brief Get the read protection level. + * @retval RDPLevel specifies the read protection level. + * This return value can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP); + + if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) + { + return (OB_RDP_LEVEL_1); + } + else + { + return rdp_level; + } +} + +#if defined(DUAL_CORE) +/** + * @brief Program the FLASH User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @note To validate the user option bytes, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param UserType The FLASH User Option Bytes to be modified : + * a combination of @ref FLASHEx_OB_USER_Type + * + * @param UserConfig The FLASH User Option Bytes values: + * IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24), + * nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + * + * @retval HAL status + */ +#else +/** + * @brief Program the FLASH User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @note To validate the user option bytes, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param UserType The FLASH User Option Bytes to be modified : + * a combination of @arg FLASHEx_OB_USER_Type + * + * @param UserConfig The FLASH User Option Bytes values: + * IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + * + * @retval HAL status + */ +#endif /*DUAL_CORE*/ +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) +{ + uint32_t optr_reg_val = 0; + uint32_t optr_reg_mask = 0; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + + if((UserType & OB_USER_IWDG1_SW) != 0U) + { + /* IWDG_HW option byte should be modified */ + assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW)); + + /* Set value and mask for IWDG_HW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW); + optr_reg_mask |= FLASH_OPTSR_IWDG1_SW; + } +#if defined(DUAL_CORE) + if((UserType & OB_USER_IWDG2_SW) != 0U) + { + /* IWDG2_SW option byte should be modified */ + assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW)); + + /* Set value and mask for IWDG2_SW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW); + optr_reg_mask |= FLASH_OPTSR_IWDG2_SW; + } +#endif /*DUAL_CORE*/ + if((UserType & OB_USER_NRST_STOP_D1) != 0U) + { + /* NRST_STOP option byte should be modified */ + assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1)); + + /* Set value and mask for NRST_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1); + optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1; + } + + if((UserType & OB_USER_NRST_STDBY_D1) != 0U) + { + /* NRST_STDBY option byte should be modified */ + assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1)); + + /* Set value and mask for NRST_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1); + optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1; + } + + if((UserType & OB_USER_IWDG_STOP) != 0U) + { + /* IWDG_STOP option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP)); + + /* Set value and mask for IWDG_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP); + optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP; + } + + if((UserType & OB_USER_IWDG_STDBY) != 0U) + { + /* IWDG_STDBY option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY)); + + /* Set value and mask for IWDG_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY); + optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY; + } + + if((UserType & OB_USER_ST_RAM_SIZE) != 0U) + { + /* ST_RAM_SIZE option byte should be modified */ + assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE)); + + /* Set value and mask for ST_RAM_SIZE option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE); + optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE; + } + + if((UserType & OB_USER_SECURITY) != 0U) + { + /* SECURITY option byte should be modified */ + assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY)); + + /* Set value and mask for SECURITY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY); + optr_reg_mask |= FLASH_OPTSR_SECURITY; + } + +#if defined(DUAL_CORE) + if((UserType & OB_USER_BCM4) != 0U) + { + /* BCM4 option byte should be modified */ + assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4)); + + /* Set value and mask for BCM4 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4); + optr_reg_mask |= FLASH_OPTSR_BCM4; + } + + if((UserType & OB_USER_BCM7) != 0U) + { + /* BCM7 option byte should be modified */ + assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7)); + + /* Set value and mask for BCM7 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7); + optr_reg_mask |= FLASH_OPTSR_BCM7; + } +#endif /* DUAL_CORE */ + +#if defined (FLASH_OPTSR_NRST_STOP_D2) + if((UserType & OB_USER_NRST_STOP_D2) != 0U) + { + /* NRST_STOP option byte should be modified */ + assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2)); + + /* Set value and mask for NRST_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2); + optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2; + } + + if((UserType & OB_USER_NRST_STDBY_D2) != 0U) + { + /* NRST_STDBY option byte should be modified */ + assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2)); + + /* Set value and mask for NRST_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2); + optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2; + } +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_BANK) + if((UserType & OB_USER_SWAP_BANK) != 0U) + { + /* SWAP_BANK_OPT option byte should be modified */ + assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT)); + + /* Set value and mask for SWAP_BANK_OPT option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT); + optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT; + } +#endif /* DUAL_BANK */ + + if((UserType & OB_USER_IOHSLV) != 0U) + { + /* IOHSLV_OPT option byte should be modified */ + assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV)); + + /* Set value and mask for IOHSLV_OPT option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV); + optr_reg_mask |= FLASH_OPTSR_IO_HSLV; + } + +#if defined (FLASH_OPTSR_VDDMMC_HSLV) + if((UserType & OB_USER_VDDMMC_HSLV) != 0U) + { + /* VDDMMC_HSLV option byte should be modified */ + assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV)); + + /* Set value and mask for VDDMMC_HSLV option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV); + optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV; + } +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + + /* Configure the option bytes register */ + MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val); +} + +#if defined(DUAL_CORE) +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values + * IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24), + * nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + */ +#else +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values + * IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + */ +#endif /*DUAL_CORE*/ +static uint32_t FLASH_OB_GetUser(void) +{ + uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR); + userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP)); + + return userConfig; +} + +/** + * @brief Configure the Proprietary code readout protection of the desired addresses + * + * @note To configure the PCROP options, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the PCROP options, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not + * when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection removal + * This parameter must be a value of @arg FLASHEx_OB_PCROP_RDP enumeration + * + * @param PCROPStartAddr specifies the start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the bank + * + * @param PCROPEndAddr specifies the end address of the Proprietary code readout protection + * This parameter can be an address between PCROPStartAddr and end of the bank + * + * @param Banks the specific bank to apply PCROP protection + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: PCROP on specified bank1 area + * @arg FLASH_BANK_2: PCROP on specified bank2 area + * @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks) + * + * @retval None + */ +static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_OB_PCROP_RDP(PCROPConfig)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr)); + + /* Configure the Proprietary code readout protection */ + FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8) | \ + (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \ + PCROPConfig; + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr)); + + /* Configure the Proprietary code readout protection */ + FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8) | \ + (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \ + PCROPConfig; + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Get the Proprietary code readout protection configuration on a given Bank + * + * @param PCROPConfig indicates if the PCROP area for the given Bank shall be erased or not + * when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection removal + * + * @param PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank + * + * @param PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank + * + * @param Bank the specific bank to apply PCROP protection + * This parameter can be exclusively one of the following values: + * @arg FLASH_BANK_1: PCROP on specified bank1 area + * @arg FLASH_BANK_2: PCROP on specified bank2 area + * @arg FLASH_BANK_BOTH: is not allowed here + * + * @retval None + */ +static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank) +{ + uint32_t regvalue = 0; + uint32_t bankBase = 0; + + if(Bank == FLASH_BANK_1) + { + regvalue = FLASH->PRAR_CUR1; + bankBase = FLASH_BANK1_BASE; + } + +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) + { + regvalue = FLASH->PRAR_CUR2; + bankBase = FLASH_BANK2_BASE; + } +#endif /* DUAL_BANK */ + + (*PCROPConfig) = (regvalue & FLASH_PRAR_DMEP); + + (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase; + (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos; + (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase; +} + +/** + * @brief Set the BOR Level. + * @param Level specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V + * @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V + * @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V + * @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V + * @retval None + */ +static void FLASH_OB_BOR_LevelConfig(uint32_t Level) +{ + assert_param(IS_OB_BOR_LEVEL(Level)); + + /* Configure BOR_LEV option byte */ + MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level); +} + +/** + * @brief Get the BOR Level. + * @retval The Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V + * @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V + * @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V + * @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V + */ +static uint32_t FLASH_OB_GetBOR(void) +{ + return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV); +} + +/** + * @brief Set Boot address + * @param BootOption Boot address option byte to be programmed, + * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION + (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH) + * + * @param BootAddress0 Specifies the Boot Address 0 + * @param BootAddress1 Specifies the Boot Address 1 + * @retval HAL Status + */ +static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT_ADD_OPTION(BootOption)); + + if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress0)); + + /* Configure CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16)); +#else /* Single Core*/ + MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16)); +#endif /* DUAL_CORE */ + } + + if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress1)); + + /* Configure CM7 BOOT ADD1 */ +#if defined(DUAL_CORE) + MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1); +#else /* Single Core*/ + MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1); +#endif /* DUAL_CORE */ + } +} + +/** + * @brief Get Boot address + * @param BootAddress0 Specifies the Boot Address 0. + * @param BootAddress1 Specifies the Boot Address 1. + * @retval HAL Status + */ +static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1) +{ + uint32_t regvalue; + +#if defined(DUAL_CORE) + regvalue = FLASH->BOOT7_CUR; + + (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16; + (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1); +#else /* Single Core */ + regvalue = FLASH->BOOT_CUR; + + (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16; + (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1); +#endif /* DUAL_CORE */ +} + +#if defined(DUAL_CORE) +/** + * @brief Set CM4 Boot address + * @param BootOption Boot address option byte to be programmed, + * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION + (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH) + * + * @param BootAddress0 Specifies the CM4 Boot Address 0. + * @param BootAddress1 Specifies the CM4 Boot Address 1. + * @retval HAL Status + */ +static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT_ADD_OPTION(BootOption)); + + if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress0)); + + /* Configure CM4 BOOT ADD0 */ + MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16)); + + } + + if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress1)); + + /* Configure CM4 BOOT ADD1 */ + MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1); + } +} + +/** + * @brief Get CM4 Boot address + * @param BootAddress0 Specifies the CM4 Boot Address 0. + * @param BootAddress1 Specifies the CM4 Boot Address 1. + * @retval HAL Status + */ +static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1) +{ + uint32_t regvalue; + + regvalue = FLASH->BOOT4_CUR; + + (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16; + (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Set secure area configuration + * @param SecureAreaConfig specify if the secure area will be deleted or not + * when RDP level decreased from Level 1 to Level 0 or during a mass erase. + * + * @param SecureAreaStartAddr Specifies the secure area start address + * @param SecureAreaEndAddr Specifies the secure area end address + * @param Banks the specific bank to apply Security protection + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Secure area on specified bank1 area + * @arg FLASH_BANK_2: Secure area on specified bank2 area + * @arg FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config will be applied on both banks) + * @retval None + */ +static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_OB_SECURE_RDP(SecureAreaConfig)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr)); + + /* Configure the secure area */ + FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8) | \ + (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \ + (SecureAreaConfig & FLASH_SCAR_DMES); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr)); + + /* Configure the secure area */ + FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8) | \ + (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \ + (SecureAreaConfig & FLASH_SCAR_DMES); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Get secure area configuration + * @param SecureAreaConfig indicates if the secure area will be deleted or not + * when RDP level decreased from Level 1 to Level 0 or during a mass erase. + * @param SecureAreaStartAddr gives the secure area start address + * @param SecureAreaEndAddr gives the secure area end address + * @param Bank Specifies the Bank + * @retval None + */ +static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank) +{ + uint32_t regvalue = 0; + uint32_t bankBase = 0; + + /* Check Bank parameter value */ + if(Bank == FLASH_BANK_1) + { + regvalue = FLASH->SCAR_CUR1; + bankBase = FLASH_BANK1_BASE; + } + +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) + { + regvalue = FLASH->SCAR_CUR2; + bankBase = FLASH_BANK2_BASE; + } +#endif /* DUAL_BANK */ + + /* Get the secure area settings */ + (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES); + (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase; + (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos; + (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase; +} + +/** + * @brief Add a CRC sector to the list of sectors on which the CRC will be calculated + * @param Sector Specifies the CRC sector number + * @param Bank Specifies the Bank + * @retval None + */ +static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + + if (Bank == FLASH_BANK_1) + { + /* Clear CRC sector */ + FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT); + + /* Select CRC Sector and activate ADD_SECT bit */ + FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT; + } +#if defined (DUAL_BANK) + else + { + /* Clear CRC sector */ + FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT); + + /* Select CRC Sector and activate ADD_SECT bit */ + FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT; + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Select CRC start and end memory addresses on which the CRC will be calculated + * @param CRCStartAddr Specifies the CRC start address + * @param CRCEndAddr Specifies the CRC end address + * @param Bank Specifies the Bank + * @retval None + */ +static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank) +{ + if (Bank == FLASH_BANK_1) + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr)); + + /* Write CRC Start and End addresses */ + FLASH->CRCSADD1 = CRCStartAddr; + FLASH->CRCEADD1 = CRCEndAddr; + } +#if defined (DUAL_BANK) + else + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr)); + + /* Write CRC Start and End addresses */ + FLASH->CRCSADD2 = CRCStartAddr; + FLASH->CRCEADD2 = CRCEndAddr; + } +#endif /* DUAL_BANK */ +} +/** + * @} + */ + +#if defined (FLASH_OTPBL_LOCKBL) +/** + * @brief Configure the OTP Block Lock. + * @param OTP_Block specifies the OTP Block to lock. + * This parameter can be a value of @ref FLASHEx_OTP_Blocks + * @retval None + */ +static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block) +{ + /* Check the parameters */ + assert_param(IS_OTP_BLOCK(OTP_Block)); + + /* Configure the OTP Block lock in the option bytes register */ + FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL); +} + +/** + * @brief Get the OTP Block Lock. + * @retval OTP_Block specifies the OTP Block to lock. + * This return value can be a value of @ref FLASHEx_OTP_Blocks + */ +static uint32_t FLASH_OB_OTP_GetLock(void) +{ + return (FLASH->OTPBL_CUR); +} +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +/** + * @brief Configure the TCM / AXI Shared RAM. + * @param SharedRamConfig specifies the Shared RAM configuration. + * This parameter can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED + * @retval None + */ +static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig) +{ + /* Check the parameters */ + assert_param(IS_OB_USER_TCM_AXI_SHARED(SharedRamConfig)); + + /* Configure the TCM / AXI Shared RAM in the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_TCM_AXI_SHARED, SharedRamConfig); +} + +/** + * @brief Get the TCM / AXI Shared RAM configuration. + * @retval SharedRamConfig returns the TCM / AXI Shared RAM configuration. + * This return value can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED + */ +static uint32_t FLASH_OB_SharedRAM_GetConfig(void) +{ + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED); +} +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +/** + * @brief Configure the CPU Frequency Boost. + * @param FreqBoost specifies the CPU Frequency Boost state. + * This parameter can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST + * @retval None + */ +static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost) +{ + /* Check the parameters */ + assert_param(IS_OB_USER_CPUFREQ_BOOST(FreqBoost)); + + /* Configure the CPU Frequency Boost in the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_CPUFREQ_BOOST, FreqBoost); +} + +/** + * @brief Get the CPU Frequency Boost state. + * @retval FreqBoost returns the CPU Frequency Boost state. + * This return value can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST + */ +static uint32_t FLASH_OB_CPUFreq_GetBoost(void) +{ + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST); +} +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c new file mode 100644 index 0000000..7133e81 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c @@ -0,0 +1,555 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +#if defined(DUAL_CORE) +#define EXTI_CPU1 (0x01000000U) +#define EXTI_CPU2 (0x02000000U) +#endif /*DUAL_CORE*/ +#define GPIO_NUMBER (16U) +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t temp; + EXTI_Core_TypeDef *EXTI_CurrentCPU; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ +#else + EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ +#endif + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00U) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1UL << position); + + if (iocurrent != 0x00U) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2U]; + temp &= ~(0x0FUL << (4U * (position & 0x03U))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + + temp = EXTI_CurrentCPU->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + { + temp |= iocurrent; + } + EXTI_CurrentCPU->EMR1 = temp; + + /* Clear EXTI line configuration */ + temp = EXTI_CurrentCPU->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + { + temp |= iocurrent; + } + EXTI_CurrentCPU->IMR1 = temp; + } + } + + position++; + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t tmp; + EXTI_Core_TypeDef *EXTI_CurrentCPU; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ +#else + EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ +#endif + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position) ; + + if (iocurrent != 0x00U) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= (0x0FUL << (4U * (position & 0x03U))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + { + /* Clear EXTI line configuration for Current CPU */ + EXTI_CurrentCPU->IMR1 &= ~(iocurrent); + EXTI_CurrentCPU->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR1 &= ~(iocurrent); + EXTI->RTSR1 &= ~(iocurrent); + + tmp = 0x0FUL << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00U) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState: specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; + } +} + +/** + * @brief Toggles the specified GPIO pins. + * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family + * @param GPIO_Pin: specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence*/ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ +#if defined(DUAL_CORE) && defined(CORE_CM4) + if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U) + { + __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +#else + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +#endif +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c new file mode 100644 index 0000000..01a01c2 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c @@ -0,0 +1,447 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_hsem.c + * @author MCD Application Team + * @brief HSEM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the semaphore peripheral: + * + Semaphore Take function (2-Step Procedure) , non blocking + * + Semaphore FastTake function (1-Step Procedure) , non blocking + * + Semaphore Status check + * + Semaphore Clear Key Set and Get + * + Release and release all functions + * + Semaphore notification enabling and disabling and callnack functions + * + IRQ handler management + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters : + (++) the semaphore ID from 0 to 31 + (++) the process ID from 0 to 255 + (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter : + (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero + (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter : + (++) the semaphore ID from 0_ID to 31 + (++) It returns 1 if the given semaphore is taken otherwise (Free) zero + (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters : + (++) the semaphore ID from 0 to 31 + (++) the process ID from 0 to 255: + (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt + may be generated when enabled (notification activated). If ProcessID or MasterID does not match, + semaphore remains taken (locked) + + (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All + This function takes as parameters : + (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by + HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions + (++) the Master ID: + (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds + to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the + Key or the MasterID doesn't match, semaphores remains taken (locked) + + (#)Semaphores Release all key functions: + (++) HAL_HSEM_SetClearKey() to set semaphore release all Key + (++) HAL_HSEM_GetClearKey() to get release all Key + (#)Semaphores notification functions : + (++) HAL_HSEM_ActivateNotification to activate a notification callback on + a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released + the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released + semaphores (bitfield). + + (++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield). + (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask + Used by the notification functions + *** HSEM HAL driver macros list *** + ============================================= + [..] Below the list of most used macros in HSEM HAL driver. + + (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask. + [..] Example of use : + [..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25). + [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example. + (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts. + (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts. + (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not. + (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags. + (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup HSEM HSEM + * @brief HSEM HAL module driver + * @{ + */ + +#ifdef HAL_HSEM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#if defined(DUAL_CORE) +/** @defgroup HSEM_Private_Constants HSEM Private Constants + * @{ + */ + +#ifndef HSEM_R_MASTERID +#define HSEM_R_MASTERID HSEM_R_COREID +#endif + +#ifndef HSEM_RLR_MASTERID +#define HSEM_RLR_MASTERID HSEM_RLR_COREID +#endif + +#ifndef HSEM_CR_MASTERID +#define HSEM_CR_MASTERID HSEM_CR_COREID +#endif + +/** + * @} + */ +#endif /* DUAL_CORE */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HSEM_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions + * @brief HSEM Take and Release functions + * +@verbatim + ============================================================================== + ##### HSEM Take and Release functions ##### + ============================================================================== +[..] This section provides functions allowing to: + (+) Take a semaphore with 2 Step method + (+) Fast Take a semaphore with 1 Step method + (+) Check semaphore state Taken or not + (+) Release a semaphore + (+) Release all semaphore at once + +@endverbatim + * @{ + */ + + +/** + * @brief Take a semaphore in 2 Step mode. + * @param SemID: semaphore ID from 0 to 31 + * @param ProcessID: Process ID from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + assert_param(IS_HSEM_PROCESSID(ProcessID)); + +#if USE_MULTI_CORE_SHARED_CODE != 0U + /* First step write R register with MasterID, processID and take bit=1*/ + HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK); + + /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */ + if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK)) + { + /*take success when MasterID and ProcessID match and take bit set*/ + return HAL_OK; + } +#else + /* First step write R register with MasterID, processID and take bit=1*/ + HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK); + + /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */ + if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK)) + { + /*take success when MasterID and ProcessID match and take bit set*/ + return HAL_OK; + } +#endif + + /* Semaphore take fails*/ + return HAL_ERROR; +} + +/** + * @brief Fast Take a semaphore with 1 Step mode. + * @param SemID: semaphore ID from 0 to 31 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + +#if USE_MULTI_CORE_SHARED_CODE != 0U + /* Read the RLR register to take the semaphore */ + if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK)) + { + /*take success when MasterID match and take bit set*/ + return HAL_OK; + } +#else + /* Read the RLR register to take the semaphore */ + if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK)) + { + /*take success when MasterID match and take bit set*/ + return HAL_OK; + } +#endif + + /* Semaphore take fails */ + return HAL_ERROR; +} +/** + * @brief Check semaphore state Taken or not. + * @param SemID: semaphore ID + * @retval HAL HSEM state + */ +uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID) +{ + return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL); +} + + +/** + * @brief Release a semaphore. + * @param SemID: semaphore ID from 0 to 31 + * @param ProcessID: Process ID from 0 to 255 + * @retval None + */ +void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + assert_param(IS_HSEM_PROCESSID(ProcessID)); + + /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */ +#if USE_MULTI_CORE_SHARED_CODE != 0U + HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID)); +#else + HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT); +#endif + +} + +/** + * @brief Release All semaphore used by a given Master . + * @param Key: Semaphore Key , value from 0 to 0xFFFF + * @param CoreID: CoreID of the CPU that is using semaphores to be released + * @retval None + */ +void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID) +{ + assert_param(IS_HSEM_KEY(Key)); + assert_param(IS_HSEM_COREID(CoreID)); + + HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos)); +} + +/** + * @} + */ + +/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions + * @brief HSEM Set and Get Key functions. + * +@verbatim + ============================================================================== + ##### HSEM Set and Get Key functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Set semaphore Key + (+) Get semaphore Key +@endverbatim + + * @{ + */ + +/** + * @brief Set semaphore Key . + * @param Key: Semaphore Key , value from 0 to 0xFFFF + * @retval None + */ +void HAL_HSEM_SetClearKey(uint32_t Key) +{ + assert_param(IS_HSEM_KEY(Key)); + + MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos)); + +} + +/** + * @brief Get semaphore Key . + * @retval Semaphore Key , value from 0 to 0xFFFF + */ +uint32_t HAL_HSEM_GetClearKey(void) +{ + return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos); +} + +/** + * @} + */ + +/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management + * @brief HSEM Notification functions. + * +@verbatim + ============================================================================== + ##### HSEM IRQ handler management and Notification functions ##### + ============================================================================== +[..] This section provides HSEM IRQ handler and Notification function. + +@endverbatim + * @{ + */ + +/** + * @brief Activate Semaphore release Notification for a given Semaphores Mask . + * @param SemMask: Mask of Released semaphores + * @retval Semaphore Key + */ +void HAL_HSEM_ActivateNotification(uint32_t SemMask) +{ +#if USE_MULTI_CORE_SHARED_CODE != 0U + /*enable the semaphore mask interrupts */ + if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + { + /*Use interrupt line 0 for CPU1 Master */ + HSEM->C1IER |= SemMask; + } + else /* HSEM_CPU2_COREID */ + { + /*Use interrupt line 1 for CPU2 Master*/ + HSEM->C2IER |= SemMask; + } +#else + HSEM_COMMON->IER |= SemMask; +#endif +} + +/** + * @brief Deactivate Semaphore release Notification for a given Semaphores Mask . + * @param SemMask: Mask of Released semaphores + * @retval Semaphore Key + */ +void HAL_HSEM_DeactivateNotification(uint32_t SemMask) +{ +#if USE_MULTI_CORE_SHARED_CODE != 0U + /*enable the semaphore mask interrupts */ + if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + { + /*Use interrupt line 0 for CPU1 Master */ + HSEM->C1IER &= ~SemMask; + } + else /* HSEM_CPU2_COREID */ + { + /*Use interrupt line 1 for CPU2 Master*/ + HSEM->C2IER &= ~SemMask; + } +#else + HSEM_COMMON->IER &= ~SemMask; +#endif +} + +/** + * @brief This function handles HSEM interrupt request + * @retval None + */ +void HAL_HSEM_IRQHandler(void) +{ + uint32_t statusreg; +#if USE_MULTI_CORE_SHARED_CODE != 0U + if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + { + /* Get the list of masked freed semaphores*/ + statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/ + + /*Disable Interrupts*/ + HSEM->C1IER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM->C1ICR = ((uint32_t)statusreg); + } + else /* HSEM_CPU2_COREID */ + { + /* Get the list of masked freed semaphores*/ + statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/ + + /*Disable Interrupts*/ + HSEM->C2IER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM->C2ICR = ((uint32_t)statusreg); + } +#else + /* Get the list of masked freed semaphores*/ + statusreg = HSEM_COMMON->MISR; + + /*Disable Interrupts*/ + HSEM_COMMON->IER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM_COMMON->ICR = ((uint32_t)statusreg); + +#endif + /* Call FreeCallback */ + HAL_HSEM_FreeCallback(statusreg); +} + +/** + * @brief Semaphore Released Callback. + * @param SemMask: Mask of Released semaphores + * @retval None + */ +__weak void HAL_HSEM_FreeCallback(uint32_t SemMask) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(SemMask); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HSEM_FreeCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_HSEM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c new file mode 100644 index 0000000..665cab0 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c @@ -0,0 +1,7544 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive stream or channel depends on Instance + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx stream or channel depends on Instance + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream or channel depends on Instance + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macro + * @{ + */ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until AF flag is set */ + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_START_WRITE); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), + xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferCount != 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->XferSize = 0U; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + HAL_StatusTypeDef status = HAL_OK; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } + } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + } + else + { + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } + + /* Increment Trials */ + I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + uint32_t sizetoxfer = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \ + ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))) + { + /* Write data to TXDR */ + if (hi2c->XferCount != 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + uint32_t tmppreviousstate; + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + } + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream or channel depends on Instance */ + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream or channel depends on Instance */ + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t treatdmaerror = 0U; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + if (hi2c->hdmatx != NULL) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmaerror = 1U; + } + } + + if (hi2c->hdmarx != NULL) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmaerror = 1U; + } + } + + /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */ + if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } +} + + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + + +/** + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + status = HAL_OK; + } + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + } + + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + } + } + return status; +} + +/** + * @brief This function handles errors detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ + /* AutoEnd should be initiate after AF */ + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + error_code |= HAL_I2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } + } + } + } + + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= error_code; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return status; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, \ + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + (hi2c->XferISR != I2C_Mem_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c new file mode 100644 index 0000000..d9b8e46 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c @@ -0,0 +1,372 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32H7xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * +@verbatim + =============================================================================== + ##### Filter Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C5 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C5 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); +} +/** + * @} + */ +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c new file mode 100644 index 0000000..064949b --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c @@ -0,0 +1,1899 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_mdma.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Master Direct Memory Access (MDMA) peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the MDMA Channel + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and MDMA requests. + + (#) + For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters: + transfer request , channel priority, data endianness, Source increment, destination increment , + source data size, destination data size, data alignment, source Burst, destination Burst , + buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer + or full transfer) source and destination block address offset, mask address and data. + + If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node. + Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero. + Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position. + User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the + last node of the list to the first one in order to make the list circular. + In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init + + -@- The initial transfer itself (node 0 corresponding to the Init). + User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove + the connection between last node and first one. + + Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list. + When a linked list is circular (last node connected to first one), if removing node1 (node where the linked list loops), + the linked list remains circular and node 2 becomes the first one. + Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user). + + [..] + (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be + transfer upon a request : + (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data + with BufferTransferLength defined within the HAL_MDMA_Init. + (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block + with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT + or within the current linked list node parameters. + (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks + with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT + or within the current linked list node parameters. + (++) MDMA_FULL_TRANSFER : each request triggers a full transfer + all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode). + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred. + (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level + In this case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns + when the abort ends or timeout (should not be called from an interrupt service routine). + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the MDMA interrupt is configured. + (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of MDMA handle structure). + + (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately + then the callback XferAbortCallback (if specified by the user) is asserted once the MDMA channel has effectively aborted. + (could be called from an interrupt service routine). + + (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks + from the following list : + (++) XferCpltCallback : transfer complete callback. + (++) XferBufferCpltCallback : buffer transfer complete callback. + (++) XferBlockCpltCallback : block transfer complete callback. + (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback. + (++) XferErrorCallback : transfer error callback. + (++) XferAbortCallback : transfer abort complete callback. + + [..] + (+) If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to + trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions: + (++) This function returns an error if used while the Transfer has ended or not started. + (++) If used while the current request has not been served yet (current request transfer on going) + this function returns an error and the new request is ignored. + + Generally this function should be used in conjunctions with the MDMA callbacks: + (++) example 1: + (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER + (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID) + (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data. + (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer + request using HAL_MDMA_GenerateSWRequest. + + (++) example 2: + (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER + (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID) + (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data. + (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask + for a new block transfer request using HAL_MDMA_GenerateSWRequest. + + [..] Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection. + + *** MDMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in MDMA HAL driver. + + (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel. + (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel. + (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags. + (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags. + (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts. + (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts. + (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the header file of the MDMA HAL driver for more useful macros. + + [..] + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup MDMA MDMA + * @brief MDMA HAL module driver + * @{ + */ + +#ifdef HAL_MDMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup MDMA_Private_Constants + * @{ + */ +#define HAL_TIMEOUT_MDMA_ABORT 5U /* 5 ms */ +#define HAL_MDMA_CHANNEL_SIZE 0x40U /* an MDMA instance channel size is 64 byte */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup MDMA_Private_Functions_Prototypes + * @{ + */ +static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); +static void MDMA_Init(MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions MDMA Exported Functions + * @{ + */ + +/** @addtogroup MDMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to : + Initialize and de-initialize the MDMA channel. + Register and Unregister MDMA callbacks + [..] + The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in + reference manual. + The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel. + HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback functions allows + respectevely to register/unregister an MDMA callback function. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MDMA according to the specified + * parameters in the MDMA_InitTypeDef and create the associated handle. + * @param hmdma: Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance)); + assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority)); + assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness)); + assert_param(IS_MDMA_REQUEST(hmdma->Init.Request)); + assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc)); + assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc)); + assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize)); + assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize)); + assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment)); + assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst)); + assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst)); + assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength)); + assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset)); + + + /* Allocate lock resource */ + __HAL_UNLOCK(hmdma); + + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Disable the MDMA channel */ + __HAL_MDMA_DISABLE(hmdma); + + /* Check if the MDMA channel is effectively disabled */ + while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT) + { + /* Update error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT; + + /* Change the MDMA state */ + hmdma->State = HAL_MDMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the MDMA channel registers */ + MDMA_Init(hmdma); + + /* Reset the MDMA first/last linkedlist node addresses and node counter */ + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Initialize the MDMA state */ + hmdma->State = HAL_MDMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the MDMA peripheral + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma) +{ + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Disable the selected MDMA Channelx */ + __HAL_MDMA_DISABLE(hmdma); + + /* Reset MDMA Channel control register */ + hmdma->Instance->CCR = 0; + hmdma->Instance->CTCR = 0; + hmdma->Instance->CBNDTR = 0; + hmdma->Instance->CSAR = 0; + hmdma->Instance->CDAR = 0; + hmdma->Instance->CBRUR = 0; + hmdma->Instance->CLAR = 0; + hmdma->Instance->CTBR = 0; + hmdma->Instance->CMAR = 0; + hmdma->Instance->CMDR = 0; + + /* Clear all flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC)); + + /* Reset the MDMA first/last linkedlist node addresses and node counter */ + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Initialize the MDMA state */ + hmdma->State = HAL_MDMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return HAL_OK; +} + +/** + * @brief Config the Post request Mask address and Mask data + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param MaskAddress: specifies the address to be updated (written) with MaskData after a request is served. + * @param MaskData: specifies the value to be written to MaskAddress after a request is served. + * MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* if HW request set Post Request MaskAddress and MaskData, */ + if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U) + { + /* Set the HW request clear Mask and Data */ + hmdma->Instance->CMAR = MaskAddress; + hmdma->Instance->CMDR = MaskData; + + /* + -If the request is done by SW : BWM could be set to 1 or 0. + -If the request is done by a peripheral : + If mask address not set (0) => BWM must be set to 0 + If mask address set (different than 0) => BWM could be set to 1 or 0 + */ + if(MaskAddress == 0U) + { + hmdma->Instance->CTCR &= ~MDMA_CTCR_BWM; + } + else + { + hmdma->Instance->CTCR |= MDMA_CTCR_BWM; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return status; +} + +/** + * @brief Register callbacks + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param CallbackID: User Callback identifier + * @param pCallback: pointer to callbacsk function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + switch (CallbackID) + { + case HAL_MDMA_XFER_CPLT_CB_ID: + hmdma->XferCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_BUFFERCPLT_CB_ID: + hmdma->XferBufferCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_BLOCKCPLT_CB_ID: + hmdma->XferBlockCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID: + hmdma->XferRepeatBlockCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_ERROR_CB_ID: + hmdma->XferErrorCallback = pCallback; + break; + + case HAL_MDMA_XFER_ABORT_CB_ID: + hmdma->XferAbortCallback = pCallback; + break; + + default: + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param CallbackID: User Callback identifier + * a HAL_MDMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + switch (CallbackID) + { + case HAL_MDMA_XFER_CPLT_CB_ID: + hmdma->XferCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_BUFFERCPLT_CB_ID: + hmdma->XferBufferCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_BLOCKCPLT_CB_ID: + hmdma->XferBlockCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID: + hmdma->XferRepeatBlockCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_ERROR_CB_ID: + hmdma->XferErrorCallback = NULL; + break; + + case HAL_MDMA_XFER_ABORT_CB_ID: + hmdma->XferAbortCallback = NULL; + break; + + case HAL_MDMA_XFER_ALL_CB_ID: + hmdma->XferCpltCallback = NULL; + hmdma->XferBufferCpltCallback = NULL; + hmdma->XferBlockCpltCallback = NULL; + hmdma->XferRepeatBlockCpltCallback = NULL; + hmdma->XferErrorCallback = NULL; + hmdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### Linked list operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Create a linked list node + (+) Add a node to the MDMA linked list + (+) Remove a node from the MDMA linked list + (+) Enable/Disable linked list circular mode +@endverbatim + * @{ + */ + +/** + * @brief Initializes an MDMA Link Node according to the specified + * parameters in the pMDMA_LinkedListNodeConfig . + * @param pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * registers configurations. + * @param pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains + * the configuration information for the specified MDMA Linked List Node. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig) +{ + uint32_t addressMask; + uint32_t blockoffset; + + /* Check the MDMA peripheral state */ + if((pNode == NULL) || (pNodeConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority)); + assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness)); + assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request)); + assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc)); + assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc)); + assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize)); + assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize)); + assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment)); + assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst)); + assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst)); + assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength)); + assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset)); + + assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength)); + assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount)); + + + /* Configure next Link node Address Register to zero */ + pNode->CLAR = 0; + + /* Configure the Link Node registers*/ + pNode->CTBR = 0; + pNode->CMAR = 0; + pNode->CMDR = 0; + pNode->Reserved = 0; + + /* Write new CTCR Register value */ + pNode->CTCR = pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \ + pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ + pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \ + pNodeConfig->Init.DestBurst | \ + ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + pNodeConfig->Init.TransferTriggerMode; + + /* If SW request set the CTCR register to SW Request Mode*/ + if(pNodeConfig->Init.Request == MDMA_REQUEST_SW) + { + pNode->CTCR |= MDMA_CTCR_SWRM; + } + + /* + -If the request is done by SW : BWM could be set to 1 or 0. + -If the request is done by a peripheral : + If mask address not set (0) => BWM must be set to 0 + If mask address set (different than 0) => BWM could be set to 1 or 0 + */ + if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U)) + { + pNode->CTCR |= MDMA_CTCR_BWM; + } + + /* Set the new CBNDTR Register value */ + pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC; + + /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */ + if(pNodeConfig->Init.SourceBlockAddressOffset < 0) + { + pNode->CBNDTR |= MDMA_CBNDTR_BRSUM; + /*write new CBRUR Register value : source repeat block offset */ + blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset); + pNode->CBRUR = blockoffset & 0x0000FFFFU; + } + else + { + /*write new CBRUR Register value : source repeat block offset */ + pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU); + } + + /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */ + if(pNodeConfig->Init.DestBlockAddressOffset < 0) + { + pNode->CBNDTR |= MDMA_CBNDTR_BRDUM; + /*write new CBRUR Register value : destination repeat block offset */ + blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset); + pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + else + { + /*write new CBRUR Register value : destination repeat block offset */ + pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + + /* Configure MDMA Link Node data length */ + pNode->CBNDTR |= pNodeConfig->BlockDataLength; + + /* Configure MDMA Link Node destination address */ + pNode->CDAR = pNodeConfig->DstAddress; + + /* Configure MDMA Link Node Source address */ + pNode->CSAR = pNodeConfig->SrcAddress; + + /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ + if(pNodeConfig->Init.Request != MDMA_REQUEST_SW) + { + /* Set the HW request in CTBR register */ + pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL; + /* Set the HW request clear Mask and Data */ + pNode->CMAR = pNodeConfig->PostRequestMaskAddress; + pNode->CMDR = pNodeConfig->PostRequestMaskData; + } + + addressMask = pNodeConfig->SrcAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHBSbus is used as source (read operation) on channel x */ + pNode->CTBR |= MDMA_CTBR_SBUS; + } + + addressMask = pNodeConfig->DstAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHB bus is used as destination (write operation) on channel x */ + pNode->CTBR |= MDMA_CTBR_DBUS; + } + + return HAL_OK; +} + +/** + * @brief Connect a node to the linked list. + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * to be add to the list. + * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node + * at the end of the list + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode) +{ + MDMA_LinkNodeTypeDef *pNode; + uint32_t counter = 0, nodeInserted = 0; + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if((hmdma == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Check if this is the first node (after the Inititlization node) */ + if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) + { + if(pPrevNode == NULL) + { + /* if this is the first node after the initialization + connect this node to the node 0 by updating + the MDMA channel CLAR register to this node address */ + hmdma->Instance->CLAR = (uint32_t)pNewNode; + /* Set the MDMA handle First linked List node*/ + hmdma->FirstLinkedListNodeAddress = pNewNode; + + /*reset New node link */ + pNewNode->CLAR = 0; + + /* Update the Handle last node address */ + hmdma->LastLinkedListNodeAddress = pNewNode; + + hmdma->LinkedListNodeCounter = 1; + } + else + { + hal_status = HAL_ERROR; + } + } + else if(hmdma->FirstLinkedListNodeAddress != pNewNode) + { + /* Check if the node to insert already exists*/ + pNode = hmdma->FirstLinkedListNodeAddress; + while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK)) + { + if(pNode->CLAR == (uint32_t)pNewNode) + { + hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */ + } + pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR; + counter++; + } + + if(hal_status == HAL_OK) + { + /* Check if the previous node is the last one in the current list or zero */ + if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL)) + { + /* insert the new node at the end of the list */ + pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR; + hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode; + /* Update the Handle last node address */ + hmdma->LastLinkedListNodeAddress = pNewNode; + /* Increment the linked list node counter */ + hmdma->LinkedListNodeCounter++; + } + else + { + /*insert the new node after the pPreviousNode node */ + pNode = hmdma->FirstLinkedListNodeAddress; + counter = 0; + while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U)) + { + counter++; + if(pNode == pPrevNode) + { + /*Insert the new node after the previous one */ + pNewNode->CLAR = pNode->CLAR; + pNode->CLAR = (uint32_t)pNewNode; + /* Increment the linked list node counter */ + hmdma->LinkedListNodeCounter++; + nodeInserted = 1; + } + else + { + pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR; + } + } + + if(nodeInserted == 0U) + { + hal_status = HAL_ERROR; + } + } + } + } + else + { + hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } +} + +/** + * @brief Disconnect/Remove a node from the transfer linked list. + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * to be removed from the list. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode) +{ + MDMA_LinkNodeTypeDef *ptmpNode; + uint32_t counter = 0, nodeDeleted = 0; + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if((hmdma == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* If first and last node are null (no nodes in the list) : return error*/ + if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) + { + hal_status = HAL_ERROR; + } + else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */ + { + /* Delete 1st node */ + if(hmdma->LastLinkedListNodeAddress == pNode) + { + /*if the last node is at the same time the first one (1 single node after the init node 0) + then update the last node too */ + + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + + hmdma->Instance->CLAR = 0; + } + else + { + if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR) + { + /* if last node is looping to first (circular list) one update the last node connection */ + hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR; + } + + /* if deleting the first node after the initialization + connect the next node to the node 0 by updating + the MDMA channel CLAR register to this node address */ + hmdma->Instance->CLAR = pNode->CLAR; + hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR; + /* Update the Handle node counter */ + hmdma->LinkedListNodeCounter--; + } + } + else /* Deleting any other node */ + { + /*Deleted node is not the first one : find it */ + ptmpNode = hmdma->FirstLinkedListNodeAddress; + while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U)) + { + counter++; + if(ptmpNode->CLAR == ((uint32_t)pNode)) + { + /* if deleting the last node */ + if(pNode == hmdma->LastLinkedListNodeAddress) + { + /*Update the linked list last node address in the handle*/ + hmdma->LastLinkedListNodeAddress = ptmpNode; + } + /* update the next node link after deleting pMDMA_LinkedListNode */ + ptmpNode->CLAR = pNode->CLAR; + nodeDeleted = 1; + /* Update the Handle node counter */ + hmdma->LinkedListNodeCounter--; + } + else + { + ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR; + } + } + + if(nodeDeleted == 0U) + { + /* last node reashed without finding the node to delete : return error */ + hal_status = HAL_ERROR; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } +} + +/** + * @brief Make the linked list circular by connecting the last node to the first. + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* If first and last node are null (no nodes in the list) : return error*/ + if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) + { + hal_status = HAL_ERROR; + } + else + { + /* to enable circular mode Last Node should be connected to first node */ + hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; + } + + } + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; +} + +/** + * @brief Disable the linked list circular mode by setting the last node connection to null + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* If first and last node are null (no nodes in the list) : return error*/ + if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) + { + hal_status = HAL_ERROR; + } + else + { + /* to disable circular mode Last Node should be connected to NULL */ + hmdma->LastLinkedListNodeAddress->CLAR = 0; + } + + } + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; +} + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start MDMA transfer + (+) Configure the source, destination address and data length and + Start MDMA transfer with interrupt + (+) Abort MDMA transfer + (+) Poll for transfer complete + (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW) + (+) Handle MDMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the MDMA Transfer. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param SrcAddress : The source memory Buffer address + * @param DstAddress : The destination memory Buffer address + * @param BlockDataLength : The length of a block transfer in bytes + * @param BlockCount : The number of a blocks to be transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) +{ + /* Check the parameters */ + assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength)); + assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_MDMA_DISABLE(hmdma); + + /* Configure the source, destination address and the data length */ + MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount); + + /* Enable the Peripheral */ + __HAL_MDMA_ENABLE(hmdma); + + if(hmdma->Init.Request == MDMA_REQUEST_SW) + { + /* activate If SW request mode*/ + hmdma->Instance->CCR |= MDMA_CCR_SWRQ; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Starts the MDMA Transfer with interrupts enabled. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param SrcAddress : The source memory Buffer address + * @param DstAddress : The destination memory Buffer address + * @param BlockDataLength : The length of a block transfer in bytes + * @param BlockCount : The number of a blocks to be transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) +{ + /* Check the parameters */ + assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength)); + assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_MDMA_DISABLE(hmdma); + + /* Configure the source, destination address and the data length */ + MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount); + + /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC)); + + if(hmdma->XferBlockCpltCallback != NULL) + { + /* if Block transfer complete Callback is set enable the corresponding IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT); + } + + if(hmdma->XferRepeatBlockCpltCallback != NULL) + { + /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT); + } + + if(hmdma->XferBufferCpltCallback != NULL) + { + /* if buffer transfer complete Callback is set enable the corresponding IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC); + } + + /* Enable the Peripheral */ + __HAL_MDMA_ENABLE(hmdma); + + if(hmdma->Init.Request == MDMA_REQUEST_SW) + { + /* activate If SW request mode*/ + hmdma->Instance->CCR |= MDMA_CCR_SWRQ; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Aborts the MDMA Transfer. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * + * @note After disabling a MDMA Channel, a check for wait until the MDMA Channel is + * effectively disabled is added. If a Channel is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Channel will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_MDMA_STATE_BUSY != hmdma->State) + { + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC)); + + /* Disable the channel */ + __HAL_MDMA_DISABLE(hmdma); + + /* Check if the MDMA Channel is effectively disabled */ + while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT) + { + /* Update error code */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change the MDMA state */ + hmdma->State = HAL_MDMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Clear all interrupt flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC)); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change the MDMA state*/ + hmdma->State = HAL_MDMA_STATE_READY; + } + + return HAL_OK; +} + +/** + * @brief Aborts the MDMA Transfer in Interrupt mode. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma) +{ + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_MDMA_STATE_BUSY != hmdma->State) + { + /* No transfer ongoing */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hmdma->State = HAL_MDMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_MDMA_DISABLE(hmdma); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param CompleteLevel: Specifies the MDMA level complete. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + uint32_t levelFlag, errorFlag; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel)); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_MDMA_STATE_BUSY != hmdma->State) + { + /* No transfer ongoing */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC : \ + (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \ + (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT : \ + MDMA_FLAG_BRT); + + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U) + { + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) + { + /* Get the transfer error source flag */ + errorFlag = hmdma->Instance->CESR; + + if((errorFlag & MDMA_CESR_TED) == 0U) + { + /* Update error code : Read Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER; + } + else + { + /* Update error code : Write Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; + } + + if((errorFlag & MDMA_CESR_TEMD) != 0U) + { + /* Update error code : Error Mask Data */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; + } + + if((errorFlag & MDMA_CESR_TELD) != 0U) + { + /* Update error code : Error Linked list */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; + } + + if((errorFlag & MDMA_CESR_ASE) != 0U) + { + /* Update error code : Address/Size alignment error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; + } + + if((errorFlag & MDMA_CESR_BSE) != 0U) + { + /* Update error code : Block Size error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; + } + + (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */ + + /* + Note that the Abort function will + - Clear all transfer flags + - Unlock + - Set the State + */ + + return HAL_ERROR; + + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U)) + { + /* Update error code */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT; + + (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */ + + /* + Note that the Abort function will + - Clear all transfer flags + - Unlock + - Set the State + */ + + return HAL_ERROR; + } + } + } + + /* Clear the transfer level flag */ + if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); + + } + else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT)); + + } + else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT)); + } + else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC)); + + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Generate an MDMA SW request trigger to activate the request on the given Channel. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma) +{ + uint32_t request_mode; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Get the softawre request mode */ + request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM; + + if((hmdma->Instance->CCR & MDMA_CCR_EN) == 0U) + { + /* if no Transfer on going (MDMA enable bit not set) return error */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != 0U) || (request_mode == 0U)) + { + /* if an MDMA ongoing request has not yet end or if request mode is not SW request return error */ + hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY; + + return HAL_ERROR; + } + else + { + /* Set the SW request bit to activate the request on the Channel */ + hmdma->Instance->CCR |= MDMA_CCR_SWRQ; + + return HAL_OK; + } +} + +/** + * @brief Handles MDMA interrupt request. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval None + */ +void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) +{ + __IO uint32_t count = 0; + uint32_t timeout = SystemCoreClock / 9600U; + + uint32_t generalIntFlag, errorFlag; + + /* General Interrupt Flag management ****************************************/ + generalIntFlag = 1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU); + if((MDMA->GISR0 & generalIntFlag) == 0U) + { + return; /* the General interrupt flag for the current channel is down , nothing to do */ + } + + /* Transfer Error Interrupt management ***************************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U) + { + /* Disable the transfer error interrupt */ + __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE); + + /* Get the transfer error source flag */ + errorFlag = hmdma->Instance->CESR; + + if((errorFlag & MDMA_CESR_TED) == 0U) + { + /* Update error code : Read Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER; + } + else + { + /* Update error code : Write Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; + } + + if((errorFlag & MDMA_CESR_TEMD) != 0U) + { + /* Update error code : Error Mask Data */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; + } + + if((errorFlag & MDMA_CESR_TELD) != 0U) + { + /* Update error code : Error Linked list */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; + } + + if((errorFlag & MDMA_CESR_ASE) != 0U) + { + /* Update error code : Address/Size alignment error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; + } + + if((errorFlag & MDMA_CESR_BSE) != 0U) + { + /* Update error code : Block Size error error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; + } + + /* Clear the transfer error flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE); + } + } + + /* Buffer Transfer Complete Interrupt management ******************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U) + { + /* Clear the buffer transfer complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); + + if(hmdma->XferBufferCpltCallback != NULL) + { + /* Buffer transfer callback */ + hmdma->XferBufferCpltCallback(hmdma); + } + } + } + + /* Block Transfer Complete Interrupt management ******************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U) + { + /* Clear the block transfer complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT); + + if(hmdma->XferBlockCpltCallback != NULL) + { + /* Block transfer callback */ + hmdma->XferBlockCpltCallback(hmdma); + } + } + } + + /* Repeated Block Transfer Complete Interrupt management ******************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U) + { + /* Clear the repeat block transfer complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT); + + if(hmdma->XferRepeatBlockCpltCallback != NULL) + { + /* Repeated Block transfer callback */ + hmdma->XferRepeatBlockCpltCallback(hmdma); + } + } + } + + /* Channel Transfer Complete Interrupt management ***********************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U) + { + /* Disable all the transfer interrupts */ + __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC)); + + if(HAL_MDMA_STATE_ABORT == hmdma->State) + { + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change the DMA state */ + hmdma->State = HAL_MDMA_STATE_READY; + + if(hmdma->XferAbortCallback != NULL) + { + hmdma->XferAbortCallback(hmdma); + } + return; + } + + /* Clear the Channel Transfer Complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_READY; + + if(hmdma->XferCpltCallback != NULL) + { + /* Channel Transfer Complete callback */ + hmdma->XferCpltCallback(hmdma); + } + } + } + + /* manage error case */ + if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE) + { + hmdma->State = HAL_MDMA_STATE_ABORT; + + /* Disable the channel */ + __HAL_MDMA_DISABLE(hmdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) + { + /* Change the MDMA state to error if MDMA disable fails */ + hmdma->State = HAL_MDMA_STATE_ERROR; + } + else + { + /* Change the MDMA state to Ready if MDMA disable success */ + hmdma->State = HAL_MDMA_STATE_READY; + } + + + if (hmdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hmdma->XferErrorCallback(hmdma); + } + } +} + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions_Group4 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the MDMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the MDMA state. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL state + */ +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma) +{ + return hmdma->State; +} + +/** + * @brief Return the MDMA error code + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval MDMA Error Code + */ +uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma) +{ + return hmdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup MDMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the MDMA Transfer parameter. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param BlockDataLength : The length of a block transfer in bytes + * @param BlockCount: The number of blocks to be transferred + * @retval HAL status + */ +static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) +{ + uint32_t addressMask; + + /* Configure the MDMA Channel data length */ + MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT)); + + /* Configure the MDMA block repeat count */ + MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC); + + /* Clear all interrupt flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF); + + /* Configure MDMA Channel destination address */ + hmdma->Instance->CDAR = DstAddress; + + /* Configure MDMA Channel Source address */ + hmdma->Instance->CSAR = SrcAddress; + + addressMask = SrcAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHBSbus is used as source (read operation) on channel x */ + hmdma->Instance->CTBR |= MDMA_CTBR_SBUS; + } + else + { + /*The AXI bus is used as source (read operation) on channel x */ + hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS); + } + + addressMask = DstAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHB bus is used as destination (write operation) on channel x */ + hmdma->Instance->CTBR |= MDMA_CTBR_DBUS; + } + else + { + /*The AXI bus is used as destination (write operation) on channel x */ + hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS); + } + + /* Set the linked list register to the first node of the list */ + hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; +} + +/** + * @brief Initializes the MDMA handle according to the specified + * parameters in the MDMA_InitTypeDef + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval None + */ +static void MDMA_Init(MDMA_HandleTypeDef *hmdma) +{ + uint32_t blockoffset; + + /* Prepare the MDMA Channel configuration */ + hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.Endianness; + + /* Write new CTCR Register value */ + hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \ + hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ + hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \ + hmdma->Init.DestBurst | \ + ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + hmdma->Init.TransferTriggerMode; + + /* If SW request set the CTCR register to SW Request Mode */ + if(hmdma->Init.Request == MDMA_REQUEST_SW) + { + /* + -If the request is done by SW : BWM could be set to 1 or 0. + -If the request is done by a peripheral : + If mask address not set (0) => BWM must be set to 0 + If mask address set (different than 0) => BWM could be set to 1 or 0 + */ + hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM); + } + + /* Reset CBNDTR Register */ + hmdma->Instance->CBNDTR = 0; + + /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */ + if(hmdma->Init.SourceBlockAddressOffset < 0) + { + hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM; + /* Write new CBRUR Register value : source repeat block offset */ + blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset); + hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU); + } + else + { + /* Write new CBRUR Register value : source repeat block offset */ + hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU); + } + + /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */ + if(hmdma->Init.DestBlockAddressOffset < 0) + { + hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM; + /* Write new CBRUR Register value : destination repeat block offset */ + blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset); + hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + else + { + /*write new CBRUR Register value : destination repeat block offset */ + hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + + /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ + if(hmdma->Init.Request != MDMA_REQUEST_SW) + { + /* Set the HW request in CTRB register */ + hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL; + } + else /* SW request : reset the CTBR register */ + { + hmdma->Instance->CTBR = 0; + } + + /* Write Link Address Register */ + hmdma->Instance->CLAR = 0; +} + +/** + * @} + */ + +#endif /* HAL_MDMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c new file mode 100644 index 0000000..345a9f5 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c @@ -0,0 +1,876 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization and de-initialization functions. + * + Peripheral Control functions. + * + Interrupt Handling functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### PWR peripheral overview ##### + ============================================================================== + [..] + (#) The Power control (PWR) provides an overview of the supply architecture + for the different power domains and of the supply configuration + controller. + In the H7 family, the number of power domains is different between + device lines. This difference is due to characteristics of each device. + + (#) Domain architecture overview for the different H7 lines: + (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757. + These devices have 3 power domains (D1, D2 and D3). + The domain D1 contains a CPU (Cortex-M7), a Flash memory and some + peripherals. The D2 domain contains peripherals and a CPU + (Cortex-M4). The D3 domain contains the system control, I/O logic + and low-power peripherals. + (+) STM32H72x, STM32H73x, STM32H742, STM32H743, STM32H750 and STM32H753 + devices have 3 power domains (D1, D2 and D3). + The domain D1 contains a CPU (Cortex-M7), a Flash memory and some + peripherals. The D2 domain contains peripherals. The D3 domains + contains the system control, I/O logic and low-power peripherals. + (+) STM32H7Axxx and STM32H7Bxxx devices have 2 power domains (CD and SRD). + The core domain (CD) contains a CPU (Cortex-M7), a Flash + memory and peripherals. The SmartRun domain contains the system + control, I/O logic and low-power peripherals. + + (#) Every entity have low power mode as described below : + (#) The CPU low power modes are : + (+) CPU CRUN. + (+) CPU CSLEEP. + (+) CPU CSTOP. + (#) The domain low power modes are : + (+) DRUN. + (+) DSTOP. + (+) DSTANDBY. + (#) The SYSTEM low power modes are : + (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from + Standby. In Run* mode, the performance is limited and the + system supply configuration shall be programmed. The system + enters Run mode only when the ACTVOSRDY bit in PWR control + status register 1 (PWR_CSR1) is set to 1. + (+) RUN. + (+) STOP. + (+) STANDBY. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Power management peripheral is active by default at startup level in + STM32h7xx lines. + + (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions + to enable/disable access to the backup domain (RTC registers, RTC backup + data registers and backup SRAM). + + (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event + mode and voltage threshold) in order to set up the Power Voltage Detector, + then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() functions to start + and stop the PVD detection. + (+) PVD level could be one of the following values : + (++) 1V95 + (++) 2V1 + (++) 2V25 + (++) 2V4 + (++) 2V55 + (++) 2V7 + (++) 2V85 + (++) External voltage level + + (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions + with the right parameter to configure the wake up pin polarity (Low or + High) and to enable and disable it. + + (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP + mode. Wake-up from SLEEP mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in SLEEP mode with __WFE() entry. + + (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0 + mode for single core devices. For dual core devices, this API will enter + the domain (containing Cortex-Mx that executing this function) in DSTOP + mode. According to the used parameter, user could select the regulator to + be kept actif in low power mode and wake-up event type. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in CSTOP mode with __WFE() entry. + + (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in + STANDBY mode for single core devices. For dual core devices, this API + will enter the domain (containing Cortex-Mx that executing this function) + in DSTANDBY mode. + + (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to + enable and disable the Cortex-Mx re-entring in SLEEP mode after an + interruption handling is over. + + (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions + to configure the Cortex-Mx to wake-up after any pending event / interrupt + even if it's disabled or has insufficient priority to cause exception + entry. + + (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt + request. + + *** PWR HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in PWR HAL driver. + + (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal + regulator output voltage. + (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags. + (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#if !defined (DUAL_CORE) +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#endif /* !defined (DUAL_CORE) */ + +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) +#define PVD_RISING_FALLING_EDGE (0x00000003U) +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and De-Initialization Functions ##### + =============================================================================== + [..] + This section provides functions allowing to deinitialize power peripheral. + + [..] + After system reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + The HAL_PWR_EnableBkUpAccess() function enables the access to the backup + domain. + The HAL_PWR_DisableBkUpAccess() function disables the access to the backup + domain. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + * values. + * @note This functionality is not available in this product. + * The prototype is kept just to maintain compatibility with other + * products. + * @retval None. + */ +void HAL_PWR_DeInit (void) +{ +} + +/** + * @brief Enable access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None. + */ +void HAL_PWR_EnableBkUpAccess (void) +{ + /* Enable access to RTC and backup registers */ + SET_BIT (PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None. + */ +void HAL_PWR_DisableBkUpAccess (void) +{ + /* Disable access to RTC and backup registers */ + CLEAR_BIT (PWR->CR1, PWR_CR1_DBP); +} +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @brief Power Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control Functions ##### + =============================================================================== + [..] + This section provides functions allowing to control power peripheral. + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 + register). + + (+) A PVDO flag is available to indicate if VDD is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line 16 to generate an interrupt if enabled. + It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + + (+) The PVD is stopped in STANDBY mode. + + *** Wake-up pin configuration *** + ================================= + [..] + (+) Wake-up pin is used to wake up the system from STANDBY mode. + The pin pull is configurable through the WKUPEPR register to be in + No-pull, Pull-up and Pull-down. + The pin polarity is configurable through the WKUPEPR register to be + active on rising or falling edges. + + (+) There are up to six Wake-up pin in the STM32H7 devices family. + + *** Low Power modes configuration *** + ===================================== + [..] + The device present 3 principles low-power modes features: + (+) SLEEP mode : Cortex-Mx is stopped and all PWR domains are remaining + active (Powered and Clocked). + + (+) STOP mode : Cortex-Mx is stopped, clocks are stopped and the + regulator is running. The Main regulator or the LP + regulator could be selected. + + (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE + supply regulator is powered off. + + *** SLEEP mode *** + ================== + [..] + (+) Entry: + The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, + SLEEPEntry) function. + + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction. + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction. + + -@@- The Regulator parameter is not used for the STM32H7 family + and is kept as parameter just to maintain compatibility with the + lower power families (STM32L). + + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from SLEEP mode. + + *** STOP mode *** + ================= + [..] + In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL, + the HSI, and the HSE RC oscillators are disabled. Internal SRAM and + register contents are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption in STOP mode, FLASH can be powered off before + entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the STOP mode using + the HAL_PWREx_DisableFlashPowerDown() function. + + (+) Entry: + The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, + STOPEntry) function with: + + (++) Regulator: + (+++) PWR_MAINREGULATOR_ON: Main regulator ON. + (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. + + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction. + + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** STANDBY mode *** + ==================== + [..] + (+) + The system STANDBY mode allows to achieve the lowest power consumption. + It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator + disabled. The system is consequently powered off. The PLL, the HSI + oscillator and the HSE oscillator are also switched off. SRAM and register + contents are lost except for the RTC registers, RTC backup registers, + backup SRAM and standby circuitry. + + [..] + The voltage regulator is OFF. + + (++) Entry: + (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode() + function. + + (++) Exit: + (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), + RTC wakeup, tamper event, time stamp event, external reset in NRST + pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an + RTC Wakeup event, a tamper event or a time-stamp event, without + depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes + + (++) To wake up from the STOP mode with an RTC alarm event, it is + necessary to configure the RTC to generate the RTC alarm using the + HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the STOP mode with an RTC Tamper or time stamp event, + it is necessary to configure the RTC to detect the tamper or time + stamp event using the HAL_RTCEx_SetTimeStamp_IT() or + HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the STOP mode with an RTC WakeUp event, it is + necessary to configure the RTC to generate the RTC WakeUp event + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the event mode and the voltage threshold detected by the + * Programmable Voltage Detector(PVD). + * @param sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains + * the configuration information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx through PWR_Exported_Macro provided by this + * driver. All combination are allowed: wake up only Cortex-M7, wake up + * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. + * @retval None. + */ +void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the PVD configuration parameter */ + if (sConfigPVD == NULL) + { + return; + } + + /* Check the parameters */ + assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); + assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); + + /* Clear previous config */ +#if !defined (DUAL_CORE) + __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); + __HAL_PWR_PVD_EXTI_DISABLE_IT (); +#endif /* !defined (DUAL_CORE) */ + + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); + +#if !defined (DUAL_CORE) + /* Interrupt mode configuration */ + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT (); + } + + /* Event mode configuration */ + if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); + } +#endif /* !defined (DUAL_CORE) */ + + /* Rising edge configuration */ + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); + } + + /* Falling edge configuration */ + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); + } +} + +/** + * @brief Enable the Programmable Voltage Detector (PVD). + * @retval None. + */ +void HAL_PWR_EnablePVD (void) +{ + /* Enable the power voltage detector */ + SET_BIT (PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Disable the Programmable Voltage Detector (PVD). + * @retval None. + */ +void HAL_PWR_DisablePVD (void) +{ + /* Disable the power voltage detector */ + CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values, which + * sets the default (rising edge): + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6. + * or one of the following values where the user can explicitly states + * the enabled pin and the chosen polarity: + * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW. + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH + * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes + * GPIOI port. + * @retval None. + */ +void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity) +{ + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity)); + + /* + Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge). + */ + MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity); +} + +/** + * @brief Disable the WakeUp PINx functionality. + * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6, + * PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW. + * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH + * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes + * GPIOI port. + * @retval None. + */ +void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx)); + + /* Disable the wake up pin selected */ + CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx)); +} + +/** + * @brief Enter the current core in SLEEP mode (CSLEEP). + * @param Regulator : Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power + * regulator ON. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with the lower power + * families. + * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction. + * @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction. + * @note Ensure to clear pending events before calling this API through + * HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE. + * @retval None. + */ +void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry */ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } +} + +/** + * @brief Enter STOP mode. + * @note For single core devices, this API will enter the system in STOP mode + * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR register is + * cleared. + * For dual core devices, this API will enter the domain (containing + * Cortex-Mx that executing this function) in DSTOP mode. If all + * Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is + * cleared, all the system will enter in STOP mode. + * @param Regulator : Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @note In System STOP mode, all I/O pins keep the same state as in Run mode. + * @note When exiting System STOP mode by issuing an interrupt or a wakeup + * event, the HSI RC oscillator is selected as default system wakeup + * clock. + * @note In System STOP mode, when the voltage regulator operates in low + * power mode, an additional startup delay is incurred when the system + * is waking up. By keeping the internal regulator ON during STOP mode, + * the consumption is higher although the startup time is reduced. + * @retval None. + */ +void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + + /* Select the regulator state in STOP mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + + /* Configure the PWR mode for the different Domains */ +#if defined (DUAL_CORE) + /* Check CPU ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + } + else + { + /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); + } +#else /* Single core devices */ + /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + +#if defined (PWR_CPUCR_PDDS_D2) + /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* PWR_CPUCR_PDDS_D2 */ +#endif /* defined (DUAL_CORE) */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select STOP mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enter STANDBY mode. + * @note For single core devices, this API will enter the system in STANDBY + * mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR + * register is cleared. + * For dual core devices, this API will enter the domain (containing + * Cortex-Mx that executing this function) in DSTANDBY mode. If all + * Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register + * is cleared, all the system will enter in STANDBY mode. + * @note The system enters Standby mode only when all domains are in DSTANDBY. + * @note When the System exit STANDBY mode by issuing an interrupt or a + * wakeup event, the HSI RC oscillator is selected as system clock. + * @note It is recommended to disable all regulators before entring STANDBY + * mode for power consumption saving purpose. + * @retval None. + */ +void HAL_PWR_EnterSTANDBYMode (void) +{ + /* Configure the PWR mode for the different Domains */ +#if defined (DUAL_CORE) + /* Check CPU ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3)); + } + else + { + /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); + SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3)); + } +#else /* Single core devices */ + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + +#if defined (PWR_CPUCR_PDDS_D2) + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* PWR_CPUCR_PDDS_D2 */ +#endif /* defined (DUAL_CORE) */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores(); +#endif /* defined (__CC_ARM) */ + + /* Request Wait For Interrupt */ + __WFI (); +} + +/** + * @brief Indicate Sleep-On-Exit feature when returning from Handler mode to + * Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run + * only on interruptions handling. + * @retval None. + */ +void HAL_PWR_EnableSleepOnExit (void) +{ + /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Disable Sleep-On-Exit feature when returning from Handler mode to + * Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit (void) +{ + /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable CORTEX SEVONPEND feature. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, any + * pending event / interrupt even if it's disabled or has insufficient + * priority to cause exception entry wakes up the Cortex-Mx. + * @retval None. + */ +void HAL_PWR_EnableSEVOnPend (void) +{ + /* Set SEVONPEND bit of Cortex-Mx System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Disable CORTEX SEVONPEND feature. + * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only + * enabled pending causes exception entry wakes up the Cortex-Mx. + * @retval None. + */ +void HAL_PWR_DisableSEVOnPend (void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions + * @brief Interrupt Handling functions + * +@verbatim + =============================================================================== + ##### Interrupt Handling Functions ##### + =============================================================================== + [..] + This section provides functions allowing to handle the PVD pending + interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @retval None. + */ +void HAL_PWR_PVD_IRQHandler (void) +{ +#if defined (DUAL_CORE) + /* Check Cortex-Mx ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Check PWR EXTI D1 flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + { + /* Clear PWR EXTI D1 pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + } + } + else + { + /* Check PWR EXTI D2 flag */ + if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U) + { + /* Clear PWR EXTI D2 pending bit */ + __HAL_PWR_PVD_EXTID2_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + } + } +#else /* Single core devices */ + /* PVD EXTI line interrupt detected */ + if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + { + /* Clear PWR EXTI pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + } +#endif /* defined (DUAL_CORE) */ +} + +/** + * @brief PWR PVD interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_PVDCallback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c new file mode 100644 index 0000000..6faff73 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c @@ -0,0 +1,2158 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: + * + Peripheral Extended features functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply + with the following different setups according to hardware (support SMPS): + (+) PWR_DIRECT_SMPS_SUPPLY + (+) PWR_SMPS_1V8_SUPPLIES_LDO + (+) PWR_SMPS_2V5_SUPPLIES_LDO + (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + (+) PWR_SMPS_1V8_SUPPLIES_EXT + (+) PWR_SMPS_2V5_SUPPLIES_EXT + (+) PWR_LDO_SUPPLY + (+) PWR_EXTERNAL_SOURCE_SUPPLY + + (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup. + + (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main + internal regulator output voltage. The voltage scaling could be one of + the following scales : + (+) PWR_REGULATOR_VOLTAGE_SCALE0 + (+) PWR_REGULATOR_VOLTAGE_SCALE1 + (+) PWR_REGULATOR_VOLTAGE_SCALE2 + (+) PWR_REGULATOR_VOLTAGE_SCALE3 + + (#) Call HAL_PWREx_GetVoltageRange() function to get the current output + voltage applied to the main regulator. + + (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the + main internal regulator output voltage in STOP mode. The voltage scaling + in STOP mode could be one of the following scales : + (+) PWR_REGULATOR_SVOS_SCALE3 + (+) PWR_REGULATOR_SVOS_SCALE4 + (+) PWR_REGULATOR_SVOS_SCALE5 + + (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current + output voltage applied to the main regulator in STOP mode. + + (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode + with core domain in D2STOP mode. This API is used only for STM32H7Axxx + and STM32H7Bxxx devices. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in DEEP-SLEEP mode with __WFE() entry. + + (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in + DSTOP mode. Call this API with all available power domains to enter the + system in STOP mode. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in DEEP-SLEEP mode with __WFE() entry. + + (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the + Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry. + + (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain + in DSTANDBY mode. Call this API with all available power domains to enter + the system in STANDBY mode. + + (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state + (RUN/STOP) when the system enter to low power mode. + + (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the + selected power domain. This API is used only for dual core devices. + + (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold + and release the selected CPU and and their domain peripherals when + exiting STOP mode. These APIs are used only for dual core devices. + + (#) Call HAL_PWREx_EnableFlashPowerDown() and + HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the + Flash Power Down in STOP mode. + + (#) Call HAL_PWREx_EnableMemoryShutOff() and + HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the + memory block shut-off in DStop or DStop2. These APIs are used only for + STM32H7Axxx and STM32H7Bxxx lines. + + (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin() + functions to enable and disable the Wake-up pin functionality for + the selected pin. + + (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag() + functions to manage wake-up flag for the selected pin. + + (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up + pins interrupts. + + (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions + to enable and disable the backup domain regulator. + + (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(), + HAL_PWREx_EnableUSBVoltageDetector() and + HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power + regulation functionalities. + + (#) Call HAL_PWREx_EnableBatteryCharging() and + HAL_PWREx_DisableBatteryCharging() functions to enable and disable the + battery charging feature with the selected resistor. + + (#) Call HAL_PWREx_EnableAnalogBooster() and + HAL_PWREx_DisableAnalogBooster() functions to enable and disable the + AVD boost feature when the VDD supply voltage is below 2V7. + + (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() + functions to enable and disable the VBAT and Temperature monitoring. + When VBAT and Temperature monitoring feature is enables, use + HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get + respectively the Temperature level and VBAT level. + + (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring() + function to get VDDMMC voltage level. This API is used only for + STM32H7Axxx and STM32H7Bxxx lines + + (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured + (event mode and voltage threshold) in order to set up the Analog Voltage + Detector then use HAL_PWREx_EnableAVD() and HAL_PWREx_DisableAVD() + functions to start and stop the AVD detection. + (+) AVD level could be one of the following values : + (++) 1V7 + (++) 2V1 + (++) 2V5 + (++) 2V8 + + (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and + AVD interrupt request. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @addtogroup PWREx_Private_Constants + * @{ + */ + +/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask + * @{ + */ +#define AVD_MODE_IT (0x00010000U) +#define AVD_MODE_EVT (0x00020000U) +#define AVD_RISING_EDGE (0x00000001U) +#define AVD_FALLING_EDGE (0x00000002U) +#define AVD_RISING_FALLING_EDGE (0x00000003U) +/** + * @} + */ + +/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value + * @{ + */ +#define PWR_FLAG_SETTING_DELAY (1000U) +/** + * @} + */ + +/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets + * @{ + */ +/* Wake-Up Pins EXTI register mask */ +#if defined (EXTI_IMR2_IM57) +#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\ + EXTI_IMR2_IM59 | EXTI_IMR2_IM60) +#else +#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + EXTI_IMR2_IM58 | EXTI_IMR2_IM60) +#endif /* defined (EXTI_IMR2_IM57) */ + +/* Wake-Up Pins PWR Pin Pull shift offsets */ +#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U) +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @brief Power supply control functions + * +@verbatim + =============================================================================== + ##### Power supply control functions ##### + =============================================================================== + [..] + (#) When the system is powered on, the POR monitors VDD supply. Once VDD is + above the POR threshold level, the voltage regulator is enabled in the + default supply configuration: + (+) The Voltage converter output level is set at 1V0 in accordance with + the VOS3 level configured in PWR (D3/SRD) domain control register + (PWR_D3CR/PWR_SRDCR). + (+) The system is kept in reset mode as long as VCORE is not ok. + (+) Once VCORE is ok, the system is taken out of reset and the HSI + oscillator is enabled. + (+) Once the oscillator is stable, the system is initialized: Flash memory + and option bytes are loaded and the CPU starts in Run* mode. + (+) The software shall then initialize the system including supply + configuration programming using the HAL_PWREx_ConfigSupply(). + (+) Once the supply configuration has been configured, the + HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR + control status register 1 (PWR_CSR1) to guarantee a valid voltage + levels: + (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the + system is in limited Run* mode, write accesses to the RAMs are not + permitted and VOS shall not be changed. + (++) Once ACTVOSRDY indicates that voltage levels are valid, the system + is in normal Run mode, write accesses to RAMs are allowed and VOS + can be changed. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the system Power Supply. + * @param SupplySource : Specifies the Power Supply source to set after a + * system startup. + * This parameter can be one of the following values : + * @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power + * Domains. The LDO is Bypassed. + * @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies + * the LDO. The Vcore Power Domains + * are supplied from the LDO. + * @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies + * the LDO. The Vcore Power Domains + * are supplied from the LDO. + * @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output + * supplies external + * circuits and the LDO. + * The Vcore Power Domains + * are supplied from the + * LDO. + * @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output + * supplies external + * circuits and the LDO. + * The Vcore Power Domains + * are supplied from the + * LDO. + * @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies + * external circuits. The LDO is + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies + * external circuits. The LDO is + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power + * Domains. The SMPS regulator is Bypassed. + * @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @note The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all + * H7 lines. + * The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO, + * PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO, + * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and + * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS + * regulator. + * @note This API is deprecated and is kept only for backward compatibility's sake. + * The power supply configuration is handled as part of the system initialization + * process during startup. + * For more details, please refer to the power control chapter in the reference manual + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param (IS_PWR_SUPPLY (SupplySource)); + + /* Check if supply source was configured */ +#if defined (PWR_FLAG_SCUEN) + if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) +#else + if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) +#endif /* defined (PWR_FLAG_SCUEN) */ + { + /* Check supply configuration */ + if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) + { + /* Supply configuration update locked, can't apply a new supply config */ + return HAL_ERROR; + } + else + { + /* Supply configuration update locked, but new supply configuration + matches with old supply configuration : nothing to do + */ + return HAL_OK; + } + } + + /* Set the power supply configuration */ + MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + +#if defined (SMPS) + /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */ + if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || + (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || + (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) || + (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT)) + { + /* Get the current tick number */ + tickstart = HAL_GetTick (); + + /* Wait till SMPS external supply ready flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + } +#endif /* defined (SMPS) */ + + return HAL_OK; +} + +/** + * @brief Get the power supply configuration. + * @retval The supply configuration. + */ +uint32_t HAL_PWREx_GetSupplyConfig (void) +{ + return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK); +} + +/** + * @brief Configure the main internal regulator output voltage. + * @param VoltageScaling : Specifies the regulator output voltage to achieve + * a tradeoff between performance and power + * consumption. + * This parameter can be one of the following values : + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output + * Scale 0 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output + * range 1 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output + * range 2 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output + * range 3 mode. + * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is + * only possible when Vcore is supplied from LDO (Low DropOut). The + * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() + * macro before configuring Voltage Scale 0. + * To enter low power mode , and if current regulator voltage is + * Voltage Scale 0 then first switch to Voltage Scale 1 before entering + * low power mode. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling)); + + /* Get the voltage scaling */ + if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling) + { + /* Old and new voltage scaling configuration match : nothing to do */ + return HAL_OK; + } + +#if defined (PWR_SRDCR_VOS) + /* Set the voltage range */ + MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); +#else +#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0) + { + if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN) + { + /* Set the voltage range */ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + /* Enable the PWR overdrive */ + SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); + } + else + { + /* The voltage scale 0 is only possible when LDO regulator is enabled */ + return HAL_ERROR; + } + } + else + { + if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1) + { + if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U) + { + /* Disable the PWR overdrive */ + CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + } + } + + /* Set the voltage range */ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); + } +#else /* STM32H72xxx and STM32H73xxx lines */ + /* Set the voltage range */ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); +#endif /* defined (SYSCFG_PWRCR_ODEN) */ +#endif /* defined (PWR_SRDCR_VOS) */ + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage. Reflecting the last + * VOS value applied to the PMU. + * @retval The current applied VOS selection. + */ +uint32_t HAL_PWREx_GetVoltageRange (void) +{ + /* Get the active voltage scaling */ + return (PWR->CSR1 & PWR_CSR1_ACTVOS); +} + +/** + * @brief Configure the main internal regulator output voltage in STOP mode. + * @param VoltageScaling : Specifies the regulator output voltage when the + * system enters Stop mode to achieve a tradeoff between performance + * and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range + * 3 mode. + * @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range + * 4 mode. + * @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range + * 5 mode. + * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage + * regulator in Low-power (LP) mode to further reduce power consumption. + * When preselecting SVOS3, the use of the voltage regulator low-power + * mode (LP) can be selected by LPDS register bit. + * @note The selected SVOS4 and SVOS5 levels add an additional startup delay + * when exiting from system Stop mode. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling)); + + /* Return the stop mode voltage range */ + MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling); + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage in STOP mode. + * @retval The actual applied VOS selection. + */ +uint32_t HAL_PWREx_GetStopModeVoltageRange (void) +{ + /* Return the stop voltage scaling */ + return (PWR->CR1 & PWR_CR1_SVOS); +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @brief Low power control functions + * +@verbatim + =============================================================================== + ##### Low power control functions ##### + =============================================================================== + + *** Domains Low Power modes configuration *** + ============================================= + [..] + This section provides the extended low power mode control APIs. + The system presents 3 principles domains (D1, D2 and D3) that can be + operated in low-power modes (DSTOP or DSTANDBY mode): + + (+) DSTOP mode to enters a domain to STOP mode: + (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU + subsystem is in CSTOP mode and has allocated peripheral in the + domain. + In DSTOP mode the domain bus matrix clock is stopped. + (++) The system enters STOP mode using one of the following scenarios: + (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains + enter DSTOP mode. + (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains + enter DSTOP mode. + (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains + enter DSTOP mode. + (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain + enters DSTOP mode. + (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain + enters DSTOP mode. + (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain + enters DSTOP mode. + (+++) D1, D2 and D3 domains enter DSTOP mode. + (++) When the system enters STOP mode, the clocks are stopped and the + regulator is running in main or low power mode. + (++) D3 domain can be kept in Run mode regardless of the CPU status when + enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function. + + (+) DSTANDBY mode to enters a domain to STANDBY mode: + (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control + register (PWR_CPUCR) for the Dn domain selects Standby mode. + (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter + DSTANDBY mode. Consequently the VCORE supply regulator is powered + off. + + *** DSTOP mode *** + ================== + [..] + In DStop mode the domain bus matrix clock is stopped. + The Flash memory can enter low-power Stop mode when it is enabled through + FLPS in PWR_CR1 register. This allows a trade-off between domain DStop + restart time and low power consumption. + [..] + In DStop mode domain peripherals using the LSI or LSE clock and + peripherals having a kernel clock request are still able to operate. + [..] + Before entering DSTOP mode it is recommended to call SCB_CleanDCache + function in order to clean the D-Cache and guarantee the data integrity + for the SRAM memories. + + (+) Entry: + The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator, + STOPEntry, Domain) function with: + (++) Regulator: + (+++) PWR_MAINREGULATOR_ON : Main regulator ON. + (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON. + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction + (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction + (++) Domain: + (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTOP mode. + (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode. + (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTOP mode. + + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** DSTANDBY mode *** + ===================== + [..] + In DStandby mode: + (+) The domain bus matrix clock is stopped. + (+) The domain is powered down and the domain RAM and register contents + are lost. + [..] + Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache + function in order to clean the D-Cache and guarantee the data integrity + for the SRAM memories. + + (+) Entry: + The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode + (Domain) function with: + (++) Domain: + (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTANDBY mode. + (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode. + (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTANDBY mode. + + (+) Exit: + WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC + wakeup, tamper event, time stamp event, external reset in NRST pin, + IWDG reset. + + *** Keep D3/SRD in RUN mode *** + =============================== + [..] + D3/SRD domain can be kept in Run mode regardless of the CPU status when + entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function + with : + (+) D3State: + (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system + mode. + (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless + of CPU subsystem mode. + + *** FLASH Power Down configuration **** + ======================================= + [..] + By setting the FLPS bit in the PWR_CR1 register using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters + power down mode when the device enters STOP mode. When the Flash memory is + in power down mode, an additional startup delay is incurred when waking up + from STOP mode. + + *** Wakeup Pins configuration **** + =================================== + [..] + Wakeup pins allow the system to exit from Standby mode. The configuration + of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) + function with: + (+) sPinParams: structure to enable and configure a wakeup pin: + (++) WakeUpPin: Wakeup pin to be enabled. + (++) PinPolarity: Wakeup pin polarity (rising or falling edge). + (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down). + [..] + The wakeup pins are internally connected to the EXTI lines [55-60] to + generate an interrupt if enabled. The EXTI lines configuration is done by + the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c + file. + [..] + When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is + called and the appropriate flag is set in the PWR_WKUPFR register. Then in + the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be + cleared and the appropriate user callback will be called. The user can add + his own code by customization of function pointer HAL_PWREx_WKUPx_Callback. + +@endverbatim + * @{ + */ + +#if defined (PWR_CPUCR_RETDS_CD) +/** + * @brief Enter the system to STOP mode with main domain in DSTOP2. + * @note In STOP mode, the domain bus matrix clock is stalled. + * @note In STOP mode, memories and registers are maintained and peripherals + * in CPU domain are no longer operational. + * @note All clocks in the VCORE domain are stopped, the PLL, the HSI and the + * HSE oscillators are disabled. Only Peripherals that have wakeup + * capability can switch on the HSI to receive a frame, and switch off + * the HSI after receiving the frame if it is not a wakeup frame. In + * this case the HSI clock is propagated only to the peripheral + * requesting it. + * @note When exiting STOP mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock if STOPWUCK bit in + * RCC_CFGR register is set. + * @param Regulator : Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @retval None. + */ +void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + + /* Select the regulator state in Stop mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + + /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD); + + /* Keep DSTOP mode when SmartRun domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __ISB (); + __DSB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} +#endif /* defined (PWR_CPUCR_RETDS_CD) */ + +/** + * @brief Enter a Domain to DSTOP mode. + * @note This API gives flexibility to manage independently each domain STOP + * mode. For dual core lines, this API should be executed with the + * corresponding Cortex-Mx to enter domain to DSTOP mode. When it is + * executed by all available Cortex-Mx, the system enter to STOP mode. + * For single core lines, calling this API with domain parameter set to + * PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode + * independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the + * CPUCR_RUN_D3 is cleared. + * @note In DStop mode the domain bus matrix clock is stopped. + * @note The system D3/SRD domain enter Stop mode only when the CPU subsystem + * is in CStop mode, the EXTI wakeup sources are inactive and at least + * one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for + * any domain request Stop. + * @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache + * function in order to clean the D-Cache and guarantee the data + * integrity for the SRAM memories. + * @note In System Stop mode, the domain peripherals that use the LSI or LSE + * clock, and the peripherals that have a kernel clock request to + * select HSI or CSI as source, are still able to operate. + * @param Regulator : Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @param Domain : Specifies the Domain to enter in DSTOP mode. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode. + * @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode. + * @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode. + * @retval None. + */ +void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + assert_param (IS_PWR_DOMAIN (Domain)); + + /* Select the regulator state in Stop mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + + /* Select the domain Power Down DeepSleep */ + if (Domain == PWR_D1_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM7_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering stop + mode will not be performed + */ + return; + } +#endif /* defined (DUAL_CORE) */ + + /* Keep DSTOP mode when D1/CD domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + } +#if defined (PWR_CPUCR_PDDS_D2) + else if (Domain == PWR_D2_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM4_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering stop + mode will not be performed + */ + return; + } + + /* Keep DSTOP mode when D2 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D2); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +#else + /* Keep DSTOP mode when D2 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* defined (DUAL_CORE) */ + } +#endif /* defined (PWR_CPUCR_PDDS_D2) */ + else + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Keep DSTOP mode when D3 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); + } + else + { + /* Keep DSTOP mode when D3 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); + } +#else + /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); +#endif /* defined (DUAL_CORE) */ + } +} + +/** + * @brief Clear pending event. + * @note This API clears the pending event in order to enter a given CPU + * to CSLEEP or CSTOP. It should be called just before APIs performing + * enter low power mode using Wait For Event request. + * @note Cortex-M7 must be in CRUN mode when calling this API by Cortex-M4. + * @retval None. + */ +void HAL_PWREx_ClearPendingEvent (void) +{ +#if defined (DUAL_CORE) + /* Check the current Core */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + __WFE (); + } + else + { + __SEV (); + __WFE (); + } +#else + __WFE (); +#endif /* defined (DUAL_CORE) */ +} + +/** + * @brief Enter a Domain to DSTANDBY mode. + * @note This API gives flexibility to manage independently each domain + * STANDBY mode. For dual core lines, this API should be executed with + * the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When + * it is executed by all available Cortex-Mx, the system enter STANDBY + * mode. + * For single core lines, calling this API with D1/SRD the selected + * domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0 + * and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1. + * @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for + * the Dn domain select Standby mode. When the system enters Standby + * mode, the voltage regulator is disabled. + * @note When D2 or D3 domain is in DStandby mode and the CPU sets the + * domain PDDS_Dn bit to select Stop mode, the domain remains in + * DStandby mode. The domain will only exit DStandby when the CPU + * allocates a peripheral in the domain. + * @note The system D3/SRD domain enters Standby mode only when the D1 and D2 + * domain are in DStandby. + * @note Before entering DSTANDBY mode it is recommended to call + * SCB_CleanDCache function in order to clean the D-Cache and guarantee + * the data integrity for the SRAM memories. + * @param Domain : Specifies the Domain to enter to STANDBY mode. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode. + * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode. + * @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode. + * @retval None + */ +void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain) +{ + /* Check the parameters */ + assert_param (IS_PWR_DOMAIN (Domain)); + + /* Select the domain Power Down DeepSleep */ + if (Domain == PWR_D1_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM7_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering + standby mode will not be performed + */ + return; + } +#endif /* defined (DUAL_CORE) */ + + /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */ + SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1); + +#if defined (DUAL_CORE) + /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */ + SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1); +#endif /*DUAL_CORE*/ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores (); +#endif /* defined (__CC_ARM) */ + + /* Request Wait For Interrupt */ + __WFI (); + } +#if defined (PWR_CPUCR_PDDS_D2) + else if (Domain == PWR_D2_DOMAIN) + { + /* Allow DSTANDBY mode when D2 domain enters Deepsleep */ + SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2); + +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM4_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering + standby mode will not be performed + */ + return; + } + + /* Allow DSTANDBY mode when D2 domain enters Deepsleep */ + SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores (); +#endif /* defined (__CC_ARM) */ + + /* Request Wait For Interrupt */ + __WFI (); +#endif /* defined (DUAL_CORE) */ + } +#endif /* defined (PWR_CPUCR_PDDS_D2) */ + else + { + /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); + +#if defined (DUAL_CORE) + /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); +#endif /* defined (DUAL_CORE) */ + } +} + +/** + * @brief Configure the D3/SRD Domain state when the System in low power mode. + * @param D3State : Specifies the D3/SRD state. + * This parameter can be one of the following values : + * @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep + * CPU sub-system low power mode. + * @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode + * regardless of the CPU sub-system low + * power mode. + * @retval None + */ +void HAL_PWREx_ConfigD3Domain (uint32_t D3State) +{ + /* Check the parameter */ + assert_param (IS_D3_STATE (D3State)); + + /* Keep D3/SRD in run mode */ + MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State); +} + +#if defined (DUAL_CORE) +/** + * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a + * given domain. + * @param DomainFlags : Specifies the Domain flags to be cleared. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags. + * @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags. + * @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags. + * @retval None. + */ +void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags) +{ + /* Check the parameter */ + assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags)); + + /* D1 CPU flags */ + if (DomainFlags == PWR_D1_DOMAIN_FLAGS) + { + /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); + } + /* D2 CPU flags */ + else if (DomainFlags == PWR_D2_DOMAIN_FLAGS) + { + /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); + } + else + { + /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); + /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); + } +} + +/** + * @brief Hold the CPU and their domain peripherals when exiting STOP mode. + * @param CPU : Specifies the core to be held. + * This parameter can be one of the following values: + * @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master. + * @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param (IS_PWR_CORE (CPU)); + + /* Check CPU index */ + if (CPU == PWR_CORE_CPU2) + { + /* If CPU1 is not held */ + if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1) + { + /* Set HOLD2 bit */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2); + } + else + { + status = HAL_ERROR; + } + } + else + { + /* If CPU2 is not held */ + if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2) + { + /* Set HOLD1 bit */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Release the CPU and their domain peripherals after a wake-up from + * STOP mode. + * @param CPU: Specifies the core to be released. + * This parameter can be one of the following values: + * @arg PWR_CORE_CPU1: Release the CPU1 and their domain + * peripherals from holding. + * @arg PWR_CORE_CPU2: Release the CPU2 and their domain + * peripherals from holding. + * @retval None + */ +void HAL_PWREx_ReleaseCore (uint32_t CPU) +{ + /* Check the parameters */ + assert_param (IS_PWR_CORE (CPU)); + + /* Check CPU index */ + if (CPU == PWR_CORE_CPU2) + { + /* Reset HOLD2 bit */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2); + } + else + { + /* Reset HOLD1 bit */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); + } +} +#endif /* defined (DUAL_CORE) */ + + +/** + * @brief Enable the Flash Power Down in Stop mode. + * @note When Flash Power Down is enabled the Flash memory enters low-power + * mode when D1/SRD domain is in DStop mode. This feature allows to + * obtain the best trade-off between low-power consumption and restart + * time when exiting from DStop mode. + * @retval None. + */ +void HAL_PWREx_EnableFlashPowerDown (void) +{ + /* Enable the Flash Power Down */ + SET_BIT (PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Disable the Flash Power Down in Stop mode. + * @note When Flash Power Down is disabled the Flash memory is kept on + * normal mode when D1/SRD domain is in DStop mode. This feature allows + * to obtain the best trade-off between low-power consumption and + * restart time when exiting from DStop mode. + * @retval None. + */ +void HAL_PWREx_DisableFlashPowerDown (void) +{ + /* Disable the Flash Power Down */ + CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS); +} + +#if defined (PWR_CR1_SRDRAMSO) +/** + * @brief Enable memory block shut-off in DStop or DStop2 modes + * @note In DStop or DStop2 mode, the content of the memory blocks is + * maintained. Further power optimization can be obtained by switching + * off some memory blocks. This optimization implies loss of the memory + * content. The user can select which memory is discarded during STOP + * mode by means of xxSO bits. + * @param MemoryBlock : Specifies the memory block to shut-off during DStop or + * DStop2 mode. + * This parameter can be one of the following values: + * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory. + * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and + * FDCAN memories. + * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories. + * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories. + * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory. + * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory. + * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory. + * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory. + * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory. + * @retval None. + */ +void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock) +{ + /* Check the parameter */ + assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock)); + + /* Enable memory block shut-off */ + SET_BIT (PWR->CR1, MemoryBlock); +} + +/** + * @brief Disable memory block shut-off in DStop or DStop2 modes + * @param MemoryBlock : Specifies the memory block to keep content during + * DStop or DStop2 mode. + * This parameter can be one of the following values: + * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory. + * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and + * FDCAN memories. + * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories. + * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories. + * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory. + * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory. + * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory. + * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory. + * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory. + * @retval None. + */ +void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock) +{ + /* Check the parameter */ + assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock)); + + /* Disable memory block shut-off */ + CLEAR_BIT (PWR->CR1, MemoryBlock); +} +#endif /* defined (PWR_CR1_SRDRAMSO) */ + +/** + * @brief Enable the Wake-up PINx functionality. + * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that + * contains the configuration information for the wake-up + * Pin. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx. All combination are allowed: wake up only + * Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and + * Cortex-M4. + * @retval None. + */ +void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams) +{ + uint32_t pinConfig; + uint32_t regMask; + const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1; + + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin)); + assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity)); + assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull)); + + pinConfig = sPinParams->WakeUpPin | \ + (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \ + (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU)); + + regMask = sPinParams->WakeUpPin | \ + (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \ + (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU)); + + /* Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge) */ + MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig); +#ifndef DUAL_CORE + /* Configure the Wakeup Pin EXTI Line */ + MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos)); +#endif /* !DUAL_CORE */ +} + +/** + * @brief Disable the Wake-up PINx functionality. + * @param WakeUpPin : Specifies the Wake-Up pin to be disabled. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 : Disable PA0 wake-up PIN. + * @arg PWR_WAKEUP_PIN2 : Disable PA2 wake-up PIN. + * @arg PWR_WAKEUP_PIN3 : Disable PI8 wake-up PIN. + * @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN. + * @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN. + * @arg PWR_WAKEUP_PIN6 : Disable PC1 wake-up PIN. + * @note The PWR_WAKEUP_PIN3 and PWR_WAKEUP_PIN5 are available only for + * devices that support GPIOI port. + * @retval None + */ +void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin) +{ + /* Check the parameter */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin)); + + /* Disable the WakeUpPin */ + CLEAR_BIT (PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Get the Wake-Up Pin pending flags. + * @param WakeUpFlag : Specifies the Wake-Up PIN flag to be checked. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_FLAG1 : Get wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Get wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Get wakeup event received from PI8. + * @arg PWR_WAKEUP_FLAG4 : Get wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG5 : Get wakeup event received from PI11. + * @arg PWR_WAKEUP_FLAG6 : Get wakeup event received from PC1. + * @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all + * wake up pins. + * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for + * devices that support GPIOI port. + * @retval The Wake-Up pin flag. + */ +uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag) +{ + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag)); + + /* Return the wake up pin flag */ + return (PWR->WKUPFR & WakeUpFlag); +} + +/** + * @brief Clear the Wake-Up pin pending flag. + * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8. + * @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11. + * @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1. + * @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from + * all wake up pins. + * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for + * devices that support GPIOI port. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag) +{ + /* Check the parameter */ + assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag)); + + /* Clear the wake up event received from wake up pin x */ + SET_BIT (PWR->WKUPCR, WakeUpFlag); + + /* Check if the wake up event is well cleared */ + if ((PWR->WKUPFR & WakeUpFlag) != 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief This function handles the PWR WAKEUP PIN interrupt request. + * @note This API should be called under the WAKEUP_PIN_IRQHandler(). + * @retval None. + */ +void HAL_PWREx_WAKEUP_PIN_IRQHandler (void) +{ + /* Wakeup pin EXTI line interrupt detected */ + if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U) + { + /* Clear PWR WKUPF1 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1); + + /* PWR WKUP1 interrupt user callback */ + HAL_PWREx_WKUP1_Callback (); + } + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U) + { + /* Clear PWR WKUPF2 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2); + + /* PWR WKUP2 interrupt user callback */ + HAL_PWREx_WKUP2_Callback (); + } +#if defined (PWR_WKUPFR_WKUPF3) + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U) + { + /* Clear PWR WKUPF3 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3); + + /* PWR WKUP3 interrupt user callback */ + HAL_PWREx_WKUP3_Callback (); + } +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U) + { + /* Clear PWR WKUPF4 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4); + + /* PWR WKUP4 interrupt user callback */ + HAL_PWREx_WKUP4_Callback (); + } +#if defined (PWR_WKUPFR_WKUPF5) + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U) + { + /* Clear PWR WKUPF5 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5); + + /* PWR WKUP5 interrupt user callback */ + HAL_PWREx_WKUP5_Callback (); + } +#endif /* defined (PWR_WKUPFR_WKUPF5) */ + else + { + /* Clear PWR WKUPF6 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6); + + /* PWR WKUP6 interrupt user callback */ + HAL_PWREx_WKUP6_Callback (); + } +} + +/** + * @brief PWR WKUP1 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP1_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP1Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP2 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP2_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP2Callback can be implemented in the user file + */ +} + +#if defined (PWR_WKUPFR_WKUPF3) +/** + * @brief PWR WKUP3 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP3_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP3Callback can be implemented in the user file + */ +} +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + +/** + * @brief PWR WKUP4 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP4_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP4Callback can be implemented in the user file + */ +} + +#if defined (PWR_WKUPFR_WKUPF5) +/** + * @brief PWR WKUP5 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP5_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP5Callback can be implemented in the user file + */ +} +#endif /* defined (PWR_WKUPFR_WKUPF5) */ + +/** + * @brief PWR WKUP6 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP6_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP6Callback can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions + * @brief Peripherals control functions + * +@verbatim + =============================================================================== + ##### Peripherals control functions ##### + =============================================================================== + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only + from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its + content is retained even in Standby or VBAT mode when the low power + backup regulator is enabled. It can be considered as an internal + EEPROM when VBAT is always present. You can use the + HAL_PWREx_EnableBkUpReg() function to enable the low power backup + regulator. + (+) When the backup domain is supplied by VDD (analog switch connected to + VDD) the backup SRAM is powered from VDD which replaces the VBAT power + supply to save battery life. + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + (+) The main internal regulator can be configured to have a tradeoff + between performance and power consumption when the device does not + operate at the maximum frequency. This is done through + HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS + bit in PWR_D3CR register. + (+) The main internal regulator can be configured to operate in Low Power + mode when the system enters STOP mode to further reduce power + consumption. + This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS) + function which configure the SVOS bit in PWR_CR1 register. + The selected SVOS4 and SVOS5 levels add an additional startup delay + when exiting from system Stop mode. + -@- Refer to the product datasheets for more details. + + *** USB Regulator configuration *** + =================================== + [..] + (+) The USB transceivers are supplied from a dedicated VDD33USB supply + that can be provided either by the integrated USB regulator, or by an + external USB supply. + (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the + VDD33USB is then provided from the USB regulator. + (+) When the USB regulator is enabled, the VDD33USB supply level detector + shall be enabled through HAL_PWREx_EnableUSBVoltageDetector() + function. + (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() + function and VDD33USB can be provided from an external supply. In this + case VDD33USB and VDD50USB shall be connected together. + + *** VBAT battery charging *** + ============================= + [..] + (+) When VDD is present, the external battery connected to VBAT can be + charged through an internal resistance. VBAT charging can be performed + either through a 5 KOhm resistor or through a 1.5 KOhm resistor. + (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging + (ResistorValue) function with: + (++) ResistorValue: + (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor. + (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor. + (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() + function. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Backup Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void) +{ + uint32_t tickstart; + + /* Enable the Backup regulator */ + SET_BIT (PWR->CR2, PWR_CR2_BREN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till Backup regulator ready flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Backup Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void) +{ + uint32_t tickstart; + + /* Disable the Backup regulator */ + CLEAR_BIT (PWR->CR2, PWR_CR2_BREN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till Backup regulator ready flag is reset */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Enable the USB Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void) +{ + uint32_t tickstart; + + /* Enable the USB regulator */ + SET_BIT (PWR->CR3, PWR_CR3_USBREGEN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till the USB regulator ready flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the USB Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void) +{ + uint32_t tickstart; + + /* Disable the USB regulator */ + CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till the USB regulator ready flag is reset */ + while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Enable the USB voltage level detector. + * @retval None. + */ +void HAL_PWREx_EnableUSBVoltageDetector (void) +{ + /* Enable the USB voltage detector */ + SET_BIT (PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Disable the USB voltage level detector. + * @retval None. + */ +void HAL_PWREx_DisableUSBVoltageDetector (void) +{ + /* Disable the USB voltage detector */ + CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Enable the Battery charging. + * @note When VDD is present, charge the external battery through an internal + * resistor. + * @param ResistorValue : Specifies the charging resistor. + * This parameter can be one of the following values : + * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor. + * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor. + * @retval None. + */ +void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue) +{ + /* Check the parameter */ + assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue)); + + /* Specify the charging resistor */ + MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue); + + /* Enable the Battery charging */ + SET_BIT (PWR->CR3, PWR_CR3_VBE); +} + +/** + * @brief Disable the Battery charging. + * @retval None. + */ +void HAL_PWREx_DisableBatteryCharging (void) +{ + /* Disable the Battery charging */ + CLEAR_BIT (PWR->CR3, PWR_CR3_VBE); +} + +#if defined (PWR_CR1_BOOSTE) +/** + * @brief Enable the booster to guarantee the analog switch AC performance when + * the VDD supply voltage is below 2V7. + * @note The VDD supply voltage can be monitored through the PVD and the PLS + * field bits. + * @retval None. + */ +void HAL_PWREx_EnableAnalogBooster (void) +{ + /* Enable the Analog voltage */ + SET_BIT (PWR->CR1, PWR_CR1_AVD_READY); + + /* Enable VDDA booster */ + SET_BIT (PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Disable the analog booster. + * @retval None. + */ +void HAL_PWREx_DisableAnalogBooster (void) +{ + /* Disable VDDA booster */ + CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE); + + /* Disable the Analog voltage */ + CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY); +} +#endif /* defined (PWR_CR1_BOOSTE) */ +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions + * @brief Power Monitoring functions + * +@verbatim + =============================================================================== + ##### Power Monitoring functions ##### + =============================================================================== + + *** VBAT and Temperature supervision *** + ======================================== + [..] + (+) The VBAT battery voltage supply can be monitored by comparing it with + two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags + in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or + lower than the threshold. + (+) The temperature can be monitored by comparing it with two threshold + levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR + control register 2 (PWR_CR2), indicate whether the device temperature + is higher or lower than the threshold. + (+) The VBAT and the temperature monitoring is enabled by + HAL_PWREx_EnableMonitoring() function and disabled by + HAL_PWREx_DisableMonitoring() function. + (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can + be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or + PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD. + (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature + level which can be : + PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or + PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD. + + *** AVD configuration *** + ========================= + [..] + (+) The AVD is used to monitor the VDDA power supply by comparing it to a + threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 + register). + (+) A AVDO flag is available to indicate if VDDA is higher or lower + than the AVD threshold. This event is internally connected to the EXTI + line 16 to generate an interrupt if enabled. + It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro. + (+) The AVD is stopped in System Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the VBAT and temperature monitoring. + * @retval HAL status. + */ +void HAL_PWREx_EnableMonitoring (void) +{ + /* Enable the VBAT and Temperature monitoring */ + SET_BIT (PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Disable the VBAT and temperature monitoring. + * @retval HAL status. + */ +void HAL_PWREx_DisableMonitoring (void) +{ + /* Disable the VBAT and Temperature monitoring */ + CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Indicate whether the junction temperature is between, above or below + * the thresholds. + * @retval Temperature level. + */ +uint32_t HAL_PWREx_GetTemperatureLevel (void) +{ + uint32_t tempLevel, regValue; + + /* Read the temperature flags */ + regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL)); + + /* Check if the temperature is below the threshold */ + if (regValue == PWR_CR2_TEMPL) + { + tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD; + } + /* Check if the temperature is above the threshold */ + else if (regValue == PWR_CR2_TEMPH) + { + tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD; + } + /* The temperature is between the thresholds */ + else + { + tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return tempLevel; +} + +/** + * @brief Indicate whether the Battery voltage level is between, above or below + * the thresholds. + * @retval VBAT level. + */ +uint32_t HAL_PWREx_GetVBATLevel (void) +{ + uint32_t VBATLevel, regValue; + + /* Read the VBAT flags */ + regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL)); + + /* Check if the VBAT is below the threshold */ + if (regValue == PWR_CR2_VBATL) + { + VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD; + } + /* Check if the VBAT is above the threshold */ + else if (regValue == PWR_CR2_VBATH) + { + VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD; + } + /* The VBAT is between the thresholds */ + else + { + VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return VBATLevel; +} + +#if defined (PWR_CSR1_MMCVDO) +/** + * @brief Get the VDDMMC voltage level. + * @retval The VDDMMC voltage level. + */ +PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void) +{ + PWREx_MMC_VoltageLevel mmc_voltage; + + /* Check voltage detector output on VDDMMC value */ + if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U) + { + mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2; + } + else + { + mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2; + } + + return mmc_voltage; +} +#endif /* defined (PWR_CSR1_MMCVDO) */ + +/** + * @brief Configure the event mode and the voltage threshold detected by the + * Analog Voltage Detector (AVD). + * @param sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains + * the configuration information for the AVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx through PWR_Exported_Macro provided by this + * driver. All combination are allowed: wake up only Cortex-M7, wake up + * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. + * @retval None. + */ +void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD) +{ + /* Check the parameters */ + assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); + assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); + + /* Set the ALS[18:17] bits according to AVDLevel value */ + MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); + + /* Clear any previous config */ +#if !defined (DUAL_CORE) + __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); + __HAL_PWR_AVD_EXTI_DISABLE_IT (); +#endif /* !defined (DUAL_CORE) */ + + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); + +#if !defined (DUAL_CORE) + /* Configure the interrupt mode */ + if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) + { + __HAL_PWR_AVD_EXTI_ENABLE_IT (); + } + + /* Configure the event mode */ + if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) + { + __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); + } +#endif /* !defined (DUAL_CORE) */ + + /* Rising edge configuration */ + if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) + { + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); + } + + /* Falling edge configuration */ + if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) + { + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); + } +} + +/** + * @brief Enable the Analog Voltage Detector (AVD). + * @retval None. + */ +void HAL_PWREx_EnableAVD (void) +{ + /* Enable the Analog Voltage Detector */ + SET_BIT (PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Disable the Analog Voltage Detector(AVD). + * @retval None. + */ +void HAL_PWREx_DisableAVD (void) +{ + /* Disable the Analog Voltage Detector */ + CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief This function handles the PWR PVD/AVD interrupt request. + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @retval None + */ +void HAL_PWREx_PVD_AVD_IRQHandler (void) +{ + /* Check if the Programmable Voltage Detector is enabled (PVD) */ + if (READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U) + { +#if defined (DUAL_CORE) + if (HAL_GetCurrentCPUID () == CM7_CPUID) +#endif /* defined (DUAL_CORE) */ + { + /* Check PWR D1/CD EXTI flag */ + if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + + if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U) + { + /* Clear PWR EXTI D1/CD pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + } + } + } +#if defined (DUAL_CORE) + else + { + /* Check PWR EXTI D2 flag */ + if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + + if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U) + { + /* Clear PWR EXTI D2 pending bit */ + __HAL_PWR_PVD_EXTID2_CLEAR_FLAG (); + } + } + } +#endif /* defined (DUAL_CORE) */ + } + + /* Check if the Analog Voltage Detector is enabled (AVD) */ + if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U) + { +#if defined (DUAL_CORE) + if (HAL_GetCurrentCPUID () == CM7_CPUID) +#endif /* defined (DUAL_CORE) */ + { + /* Check PWR EXTI D1/CD flag */ + if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U) + { + /* PWR AVD interrupt user callback */ + HAL_PWREx_AVDCallback (); + + if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U) + { + /* Clear PWR EXTI D1/CD pending bit */ + __HAL_PWR_AVD_EXTI_CLEAR_FLAG (); + } + } + } +#if defined (DUAL_CORE) + else + { + /* Check PWR EXTI D2 flag */ + if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U) + { + /* PWR AVD interrupt user callback */ + HAL_PWREx_AVDCallback (); + + if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U) + { + /* Clear PWR EXTI D2 pending bit */ + __HAL_PWR_AVD_EXTID2_CLEAR_FLAG (); + } + } + } +#endif /* defined (DUAL_CORE) */ + } +} + +/** + * @brief PWR AVD interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_AVDCallback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_AVDCallback can be implemented in the user file + */ +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c new file mode 100644 index 0000000..dad8854 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c @@ -0,0 +1,1814 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except + internal SRAM, Flash, JTAG and PWR + (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analogue mode , except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses pre-scalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock kernel source(s) for peripherals which clocks are not + derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R + and RCC_D3CCIPR registers + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOC +#define MCO2_PIN GPIO_PIN_9 + +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1 + AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral + clock, or PLL input.But even with frequency calibration, is less accurate than an + external crystal oscillator or ceramic resonator. + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI), + featuring three different output clocks and able to work either in integer or Fractional mode. + (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU + and to some peripherals. + (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals. + + + (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt) + exception vector. + + (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q) + or HSI48 clock (through a configurable pre-scaler) on PA8 pin. + + (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK, + LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin. + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System core clock through configurable + pre-scaler and used to clock the CPU, memory and peripherals mapped + on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers + and used to clock the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those + with dual clock domain where kernel source clock could be selected through + RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers. + + (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines. +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL1, PLL2 and PLL3 OFF + * - AHB, APB Bus pre-scaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Increasing the CPU frequency */ + if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + + } + + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[6:0] bits to the reset value */ + SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Update the SystemCoreClock and SystemD2Clock global variables */ + SystemCoreClock = HSI_VALUE; + SystemD2Clock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON \ + | RCC_CR_HSI48ON | RCC_CR_CSSHSEON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLL2ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLL3 bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + + /* Wait till PLL3 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_D1CFGR_HPRE) + /* Reset D1CFGR register */ + CLEAR_REG(RCC->D1CFGR); + + /* Reset D2CFGR register */ + CLEAR_REG(RCC->D2CFGR); + + /* Reset D3CFGR register */ + CLEAR_REG(RCC->D3CFGR); +#else + /* Reset CDCFGR1 register */ + CLEAR_REG(RCC->CDCFGR1); + + /* Reset CDCFGR2 register */ + CLEAR_REG(RCC->CDCFGR2); + + /* Reset SRDCFGR register */ + CLEAR_REG(RCC->SRDCFGR); +#endif + + /* Reset PLLCKSELR register to default value */ + RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5; + + /* Reset PLLCFGR register to default value */ + WRITE_REG(RCC->PLLCFGR, 0x01FF0000U); + + /* Reset PLL1DIVR register to default value */ + WRITE_REG(RCC->PLL1DIVR, 0x01010280U); + + /* Reset PLL1FRACR register */ + CLEAR_REG(RCC->PLL1FRACR); + + /* Reset PLL2DIVR register to default value */ + WRITE_REG(RCC->PLL2DIVR, 0x01010280U); + + /* Reset PLL2FRACR register */ + CLEAR_REG(RCC->PLL2FRACR); + + /* Reset PLL3DIVR register to default value */ + WRITE_REG(RCC->PLL3DIVR, 0x01010280U); + + /* Reset PLL3FRACR register */ + CLEAR_REG(RCC->PLL3FRACR); + +#if defined(RCC_CR_HSEEXT) + /* Reset HSEEXT */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); +#endif /* RCC_CR_HSEEXT */ + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all interrupts flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Reset all RSR flags */ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + + } + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t temp1_pllckcfg, temp2_pllckcfg; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* When the HSI is used as system clock it will not be disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) + { + /* When HSI is used as system clock it will not be disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + { + return HAL_ERROR; + } + /* Otherwise, only HSI division and calibration are allowed */ + else + { + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- CSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) + { + /* Check the parameters */ + assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); + assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); + + /* When the CSI is used as system clock it will not disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) + { + /* When CSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); + } + } + else + { + /* Check the CSI State */ + if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) + { + /* Enable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till CSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till CSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*------------------------------ HSI48 Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the HSI48 State */ + if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLRGE_VALUE(RCC_OscInitStruct->PLL.PLLRGE)); + assert_param(IS_RCC_PLLVCO_VALUE(RCC_OscInitStruct->PLL.PLLVCOSEL)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Disable PLLFRACN . */ + __HAL_RCC_PLLFRACN_DISABLE(); + + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + + /* Select PLL1 input reference frequency range: VCI */ + __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; + + /* Select PLL1 output frequency range : VCO */ + __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + + /* Enable PLL1Q Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* Enable PLL1R Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + + /* Enable PLL1FRACN . */ + __HAL_RCC_PLLFRACN_ENABLE(); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp1_pllckcfg = RCC->PLLCKSELR; + temp2_pllckcfg = RCC->PLL1DIVR; + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) + { + return HAL_ERROR; + } + else + { + /* Check if only fractional part needs to be updated */ + temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); + if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) + { + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + /* Disable PLL1FRACEN */ + __HAL_RCC_PLLFRACN_DISABLE(); + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ + while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) + { + } + /* Configure PLL1 PLL1FRACN */ + __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + /* Enable PLL1FRACEN to latch new value. */ + __HAL_RCC_PLLFRACN_ENABLE(); + } + } + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency: FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency + * and updated by HAL_InitTick() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @note Depending on the device voltage range, the software has to set correctly + * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + HAL_StatusTypeDef halstatus; + uint32_t tickstart; + uint32_t common_system_clock; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + + } + + /* Increasing the BUS frequency divider */ + /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + { +#if defined (RCC_D1CFGR_D1PPRE) + if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + { + assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#else + if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + { + assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#endif + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { +#if defined (RCC_D2CFGR_D2PPRE1) + if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#endif + } + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { +#if defined(RCC_D2CFGR_D2PPRE2) + if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#endif + } + + /*-------------------------- D3PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + { +#if defined(RCC_D3CFGR_D3PPRE) + if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#endif + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { +#if defined (RCC_D1CFGR_HPRE) + if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#else + if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#endif + } + + /*------------------------- SYSCLK Configuration -------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); +#if defined(RCC_D1CFGR_D1CPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); +#endif + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + { + return HAL_ERROR; + } + } + /* CSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + /* Decreasing the BUS frequency divider */ + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { +#if defined(RCC_D1CFGR_HPRE) + if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#else + if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#endif + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + { +#if defined(RCC_D1CFGR_D1PPRE) + if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + { + assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#else + if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + { + assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#endif + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { +#if defined(RCC_D2CFGR_D2PPRE1) + if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#endif + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { +#if defined (RCC_D2CFGR_D2PPRE2) + if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#endif + } + + /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + { +#if defined(RCC_D3CFGR_D3PPRE) + if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + { + assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#endif + } + + /* Update the SystemCoreClock global variable */ +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Configure the source of time base considering new system clocks settings*/ + halstatus = HAL_InitTick(uwTickPrio); + + return halstatus; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx: specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source + * @param RCC_MCODiv: specifies the MCOx pre-scaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO1 */ + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + } + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U))); + } +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M NMI (Non-Mask-able Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON); +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(*) + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue; + float_t fracn1, pllvco; + uint32_t sysclockfreq; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + sysclockfreq = (uint32_t) HSI_VALUE; + } + + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + sysclockfreq = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; + pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + break; + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; + sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); + } + else + { + sysclockfreq = 0U; + } + break; + + default: + sysclockfreq = CSI_VALUE; + break; + } + + return sysclockfreq; +} + + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + uint32_t common_system_clock; + +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + return SystemD2Clock; +} + + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ +#if defined (RCC_D2CFGR_D2PPRE1) + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); +#else + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); +#endif +} + + +/** + * @brief Returns the D2 PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +#if defined(RCC_D2CFGR_D2PPRE2) + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); +#else + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); +#endif +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; + + /* Get the HSE configuration -----------------------------------------------*/ +#if defined(RCC_CR_HSEEXT) + if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } +#else + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } +#endif /* RCC_CR_HSEEXT */ + + /* Get the CSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_CSION) == RCC_CR_CSION) + { + RCC_OscInitStruct->CSIState = RCC_CSI_ON; + } + else + { + RCC_OscInitStruct->CSIState = RCC_CSI_OFF; + } + +#if defined(RCC_VER_X) + if (HAL_GetREVID() <= REV_ID_Y) + { + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos); + } + else + { + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); + } +#else + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); +#endif /*RCC_VER_X*/ + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + +#if defined(RCC_VER_X) + if (HAL_GetREVID() <= REV_ID_Y) + { + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos); + } + else + { + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + } +#else + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); +#endif /*RCC_VER_X*/ + + /* Get the LSE configuration -----------------------------------------------*/ +#if defined(RCC_BDCR_LSEEXT) + if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } +#else + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } +#endif /* RCC_BDCR_LSEEXT */ + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the HSI48 configuration ---------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON) + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; + } + else + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE)); + RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos); + RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos)); +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency: Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + +#if defined(RCC_D1CFGR_D1CPRE) + /* Get the SYSCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); + + /* Get the D1HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); + + /* Get the APB3 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); + + /* Get the APB4 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); +#else + /* Get the SYSCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE); + + /* Get the D1HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE); + + /* Get the APB3 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2); + + /* Get the APB4 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); +#endif + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c new file mode 100644 index 0000000..25307c3 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c @@ -0,0 +1,3935 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_defines RCCEx Private Defines + * @{ + */ +#define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ +#define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ + +#define DIVIDER_P_UPDATE 0U +#define DIVIDER_Q_UPDATE 1U +#define DIVIDER_R_UPDATE 2U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123, + * USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, + * SAI4A*, SAI4B*, SPI6, RTC). + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * (*) : Available on some STM32H7 lines only. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpreg; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /*---------------------------- SPDIFRX configuration -------------------------------*/ + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + + switch (PeriphClkInit->SpdifrxClockSelection) + { + case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ + /* Enable PLL1Q Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_HSI: + /* Internal OSC clock is used as source of SPDIFRX clock*/ + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPDIFRX clock*/ + __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SAI1 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + { + switch (PeriphClkInit->Sai1ClockSelection) + { + case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PIN: + /* External clock is used as source of SAI1 clock*/ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(SAI3) + /*---------------------------- SAI2/3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) + { + switch (PeriphClkInit->Sai23ClockSelection) + { + case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PIN: + /* External clock is used as source of SAI2/3 clock*/ + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2/3 clock*/ + __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) + /*---------------------------- SAI2A configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) + { + switch (PeriphClkInit->Sai2AClockSelection) + { + case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ + /* Enable SAI2A Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PIN: + /* External clock is used as source of SAI2A clock*/ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2A clock*/ + __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI2A*/ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) + + /*---------------------------- SAI2B configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) + { + switch (PeriphClkInit->Sai2BClockSelection) + { + case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PIN: + /* External clock is used as source of SAI2B clock*/ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2B clock*/ + __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI2B*/ + +#if defined(SAI4) + /*---------------------------- SAI4A configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) + { + switch (PeriphClkInit->Sai4AClockSelection) + { + case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PIN: + /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_VER_3_0) + case RCC_SAI4ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4A clock */ + /* SAI4A clock source configuration done later after clock selection check */ + break; +#endif /* RCC_VER_3_0 */ + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI4A clock*/ + __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + /*---------------------------- SAI4B configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) + { + switch (PeriphClkInit->Sai4BClockSelection) + { + case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PIN: + /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_VER_3_0) + case RCC_SAI4BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4B clock */ + /* SAI4B clock source configuration done later after clock selection check */ + break; +#endif /* RCC_VER_3_0 */ + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI4B clock*/ + __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI4*/ + +#if defined(QUADSPI) + /*---------------------------- QSPI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) + { + switch (PeriphClkInit->QspiClockSelection) + { + case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ + /* Enable QSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* QSPI clock source configuration done later after clock selection check */ + break; + + case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* QSPI clock source configuration done later after clock selection check */ + break; + + + case RCC_QSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */ + /* QSPI clock source configuration done later after clock selection check */ + break; + + case RCC_QSPICLKSOURCE_D1HCLK: + /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of QSPI clock*/ + __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*QUADSPI*/ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /*---------------------------- OCTOSPI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + { + switch (PeriphClkInit->OspiClockSelection) + { + case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ + /* Enable OSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* OSPI clock source configuration done later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* OSPI clock source configuration done later after clock selection check */ + break; + + + case RCC_OSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */ + /* OSPI clock source configuration done later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_HCLK: + /* HCLK clock selected as OSPI kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of OSPI clock*/ + __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*OCTOSPI*/ + + /*---------------------------- SPI1/2/3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) + { + switch (PeriphClkInit->Spi123ClockSelection) + { + case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ + /* Enable SPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PIN: + /* External clock is used as source of SPI1/2/3 clock*/ + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI1/2/3 clock*/ + __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI4/5 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) + { + switch (PeriphClkInit->Spi45ClockSelection) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for SPI4/5 */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of SPI4/5 clock*/ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of SPI4/5 clock */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_HSE: + /* HSE, oscillator is used as source of SPI4/5 clock */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI4/5 clock*/ + __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI6 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) + { + switch (PeriphClkInit->Spi6ClockSelection) + { + case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* SPI6 clock source configuration done later after clock selection check */ + break; + case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of SPI6 clock*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSE: + /* HSE, oscillator is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; +#if defined(RCC_SPI6CLKSOURCE_PIN) + case RCC_SPI6CLKSOURCE_PIN: + /* 2S_CKIN is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; +#endif + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI6 clock*/ + __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(DSI) + /*---------------------------- DSI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + { + switch (PeriphClkInit->DsiClockSelection) + { + + case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* DSI clock source configuration done later after clock selection check */ + break; + + case RCC_DSICLKSOURCE_PHY: + /* PHY is used as clock source for DSI*/ + /* DSI clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of DSI clock*/ + __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*DSI*/ + +#if defined(FDCAN1) || defined(FDCAN2) + /*---------------------------- FDCAN configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + { + switch (PeriphClkInit->FdcanClockSelection) + { + case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ + /* Enable FDCAN Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* FDCAN clock source configuration done later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* FDCAN clock source configuration done later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_HSE: + /* HSE is used as clock source for FDCAN*/ + /* FDCAN clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FDCAN clock*/ + __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*FDCAN1 || FDCAN2*/ + + /*---------------------------- FMC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) + { + switch (PeriphClkInit->FmcClockSelection) + { + case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ + /* Enable FMC Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* FMC clock source configuration done later after clock selection check */ + break; + + case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* FMC clock source configuration done later after clock selection check */ + break; + + + case RCC_FMCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of FMC clock */ + /* FMC clock source configuration done later after clock selection check */ + break; + + case RCC_FMCCLKSOURCE_HCLK: + /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FMC clock*/ + __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- RTC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if (ret == HAL_OK) + { + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg; + } + + /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ + if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + } + + + /*-------------------------- USART1/6 configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) + { + switch (PeriphClkInit->Usart16ClockSelection) + { + case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART1/6 clock */ + __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) + { + switch (PeriphClkInit->Usart234578ClockSelection) + { + case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART2/3/4/5/7/8 clock */ + __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- LPUART1 Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + switch (PeriphClkInit->Lpuart1ClockSelection) + { + case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_LSE: + /* LSE, oscillator is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPUART1 clock */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM1 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + switch (PeriphClkInit->Lptim1ClockSelection) + { + case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM1 clock*/ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM2 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) + { + switch (PeriphClkInit->Lptim2ClockSelection) + { + case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM2CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM2 clock*/ + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM345 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) + { + switch (PeriphClkInit->Lptim345ClockSelection) + { + + case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM345CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM3/4/5 clock */ + __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ +#if defined(I2C5) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); + + if ((PeriphClkInit->I2c1235ClockSelection) == RCC_I2C1235CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); + + } +#else + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); + + if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); + + } +#endif /* I2C5 */ + + /*------------------------------ I2C4 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + + } + + /*---------------------------- ADC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + switch (PeriphClkInit->AdcClockSelection) + { + + case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* ADC clock source configuration done later after clock selection check */ + break; + + case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* ADC clock source configuration done later after clock selection check */ + break; + + case RCC_ADCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ + /* ADC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of ADC clock*/ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ USB Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + + switch (PeriphClkInit->UsbClockSelection) + { + case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ + /* Enable USB Clock output generated form System USB . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* USB clock source configuration done later after clock selection check */ + break; + + case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ + + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + + /* USB clock source configuration done later after clock selection check */ + break; + + case RCC_USBCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of USB clock */ + /* USB clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USB clock*/ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*------------------------------------- SDMMC Configuration ------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); + + switch (PeriphClkInit->SdmmcClockSelection) + { + case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ + /* Enable SDMMC Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SDMMC clock source configuration done later after clock selection check */ + break; + + case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* SDMMC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SDMMC clock*/ + __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(LTDC) + /*-------------------------------------- LTDC Configuration -----------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } +#endif /* LTDC */ + + /*------------------------------ RNG Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) + { + + switch (PeriphClkInit->RngClockSelection) + { + case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ + /* Enable RNG Clock output generated form System RNG . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* RNG clock source configuration done later after clock selection check */ + break; + + case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/ + + /* RNG clock source configuration done later after clock selection check */ + break; + + case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/ + + /* RNG clock source configuration done later after clock selection check */ + break; + case RCC_RNGCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of RNG clock */ + /* RNG clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of RNG clock*/ + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*------------------------------ SWPMI1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); + + /* Configure the SWPMI1 interface clock source */ + __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); + } +#if defined(HRTIM1) + /*------------------------------ HRTIM1 clock Configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); + + /* Configure the HRTIM1 clock source */ + __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); + } +#endif /*HRTIM1*/ + /*------------------------------ DFSDM1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + +#if defined(DFSDM2_BASE) + /*------------------------------ DFSDM2 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); + + /* Configure the DFSDM2 interface clock source */ + __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); + } +#endif /* DFSDM2 */ + + /*------------------------------------ TIM configuration --------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*------------------------------------ CKPER configuration --------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) + { + /* Check the parameters */ + assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); + + /* Configure the CKPER clock source */ + __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); + } + + /*------------------------------ CEC Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC interface clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + + /*---------------------------- PLL2 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + /*---------------------------- PLL3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + if (status == HAL_OK) + { + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks : + * (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123, + * USART234578, USART16, RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC. + * SAI4A*, SAI4B*, SPI6, RTC, TIM). + * @retval None + * + * (*) : Available on some STM32H7 lines only. + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = + RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 | + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | + RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM | + RCC_PERIPHCLK_CKPER; + +#if defined(I2C5) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235; +#else + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; +#endif /*I2C5*/ +#if defined(RCC_CDCCIP1R_SAI2ASEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A; +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B; +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(SAI3) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23; +#endif /* SAI3 */ +#if defined(SAI4) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A; + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B; +#endif /* SAI4 */ +#if defined(DFSDM2_BASE) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2; +#endif /* DFSDM2 */ +#if defined(QUADSPI) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI; +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI; +#endif /* OCTOSPI1 || OCTOSPI2 */ +#if defined(HRTIM1) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; +#endif /* HRTIM1 */ +#if defined(LTDC) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC; +#endif /* LTDC */ +#if defined(DSI) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI; +#endif /* DSI */ + + /* Get the PLL3 Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); + PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos); + PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos); + + /* Get the PLL2 Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); + PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos); + PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos); + + /* Get the USART1 configuration --------------------------------------------*/ + PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE(); + /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/ + PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE(); + /* Get the LPUART1 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +#if defined(I2C5) + /* Get the I2C1/2/3/5 clock source -----------------------------------------*/ + PeriphClkInit->I2c1235ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#else + /* Get the I2C1/2/3 clock source -------------------------------------------*/ + PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#endif /*I2C5*/ + /* Get the LPTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + /* Get the LPTIM2 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); + /* Get the LPTIM3/4/5 clock source -----------------------------------------*/ + PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE(); + /* Get the SAI1 clock source -----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#if defined(SAI3) + /* Get the SAI2/3 clock source ---------------------------------------------*/ + PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE(); +#endif /*SAI3*/ +#if defined(RCC_CDCCIP1R_SAI2ASEL_0) + /* Get the SAI2A clock source ---------------------------------------------*/ + PeriphClkInit->Sai2AClockSelection = __HAL_RCC_GET_SAI2A_SOURCE(); +#endif /*SAI2A*/ +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) + /* Get the SAI2B clock source ---------------------------------------------*/ + PeriphClkInit->Sai2BClockSelection = __HAL_RCC_GET_SAI2B_SOURCE(); +#endif /*SAI2B*/ +#if defined(SAI4) + /* Get the SAI4A clock source ----------------------------------------------*/ + PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE(); + /* Get the SAI4B clock source ----------------------------------------------*/ + PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE(); +#endif /*SAI4*/ + /* Get the RTC clock source ------------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the USB clock source ------------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); + /* Get the SDMMC clock source ----------------------------------------------*/ + PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); + /* Get the RNG clock source ------------------------------------------------*/ + PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); +#if defined(HRTIM1) + /* Get the HRTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); +#endif /* HRTIM1 */ + /* Get the ADC clock source ------------------------------------------------*/ + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + /* Get the SWPMI1 clock source ---------------------------------------------*/ + PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); + /* Get the DFSDM1 clock source ---------------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); +#if defined(DFSDM2_BASE) + /* Get the DFSDM2 clock source ---------------------------------------------*/ + PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); +#endif /* DFSDM2 */ + /* Get the SPDIFRX clock source --------------------------------------------*/ + PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); + /* Get the SPI1/2/3 clock source -------------------------------------------*/ + PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE(); + /* Get the SPI4/5 clock source ---------------------------------------------*/ + PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE(); + /* Get the SPI6 clock source -----------------------------------------------*/ + PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE(); + /* Get the FDCAN clock source ----------------------------------------------*/ + PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); + /* Get the CEC clock source ------------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + /* Get the FMC clock source ------------------------------------------------*/ + PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE(); +#if defined(QUADSPI) + /* Get the QSPI clock source -----------------------------------------------*/ + PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE(); +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /* Get the OSPI clock source -----------------------------------------------*/ + PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); +#endif /* OCTOSPI1 || OCTOSPI2 */ + +#if defined(DSI) + /* Get the DSI clock source ------------------------------------------------*/ + PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); +#endif /*DSI*/ + + /* Get the CKPER clock source ----------------------------------------------*/ + PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE(); + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk: Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*) + * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock + * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock + * @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock + * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock + * @retval Frequency in KHz + * + * (*) : Available on some STM32H7 lines only. + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) +{ + PLL1_ClocksTypeDef pll1_clocks; + PLL2_ClocksTypeDef pll2_clocks; + PLL3_ClocksTypeDef pll3_clocks; + + /* This variable is used to store the clock frequency (value in Hz) */ + uint32_t frequency; + /* This variable is used to store the SAI and CKP clock source */ + uint32_t saiclocksource; + uint32_t ckpclocksource; + uint32_t srcclk; + + if (PeriphClk == RCC_PERIPHCLK_SAI1) + { + + saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } + +#if defined(SAI3) + else if (PeriphClk == RCC_PERIPHCLK_SAI23) + { + + saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) + + else if (PeriphClk == RCC_PERIPHCLK_SAI2A) + { + saiclocksource = __HAL_RCC_GET_SAI2A_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + + } +#endif + +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) + else if (PeriphClk == RCC_PERIPHCLK_SAI2B) + { + + saiclocksource = __HAL_RCC_GET_SAI2B_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + break; + } + + case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } +#endif + +#if defined(SAI4) + else if (PeriphClk == RCC_PERIPHCLK_SAI4A) + { + + saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } + + else if (PeriphClk == RCC_PERIPHCLK_SAI4B) + { + + saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } +#endif /*SAI4*/ + else if (PeriphClk == RCC_PERIPHCLK_SPI123) + { + /* Get SPI1/2/3 clock source */ + srcclk = __HAL_RCC_GET_SPI123_SOURCE(); + + switch (srcclk) + { + case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI45) + { + /* Get SPI45 clock source */ + srcclk = __HAL_RCC_GET_SPI45_SOURCE(); + switch (srcclk) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + break; + } + case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) + { + frequency = CSI_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_ADC) + { + /* Get ADC clock source */ + srcclk = __HAL_RCC_GET_ADC_SOURCE(); + + switch (srcclk) + { + case RCC_ADCCLKSOURCE_PLL2: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_ADCCLKSOURCE_PLL3: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_ADCCLKSOURCE_CLKP: + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SDMMC) + { + /* Get SDMMC clock source */ + srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); + + switch (srcclk) + { + case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } + else + { + frequency = 0; + } + break; + } + + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI6) + { + /* Get SPI6 clock source */ + srcclk = __HAL_RCC_GET_SPI6_SOURCE(); + + switch (srcclk) + { + case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ + { + frequency = HAL_RCCEx_GetD3PCLK1Freq(); + break; + } + case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) + { + frequency = CSI_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } +#if defined(RCC_SPI6CLKSOURCE_PIN) + case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#endif /* RCC_SPI6CLKSOURCE_PIN */ + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_FDCAN) + { + /* Get FDCAN clock source */ + srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); + + switch (srcclk) + { + case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + default : + { + frequency = 0; + break; + } + } + } + else + { + frequency = 0; + } + + return frequency; +} + + +/** + * @brief Returns the D1PCLK1 frequency + * @note Each time D1PCLK1 changes, this function must be called to update the + * right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval D1PCLK1 frequency + */ +uint32_t HAL_RCCEx_GetD1PCLK1Freq(void) +{ +#if defined(RCC_D1CFGR_D1PPRE) + /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU)); +#else + /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU)); +#endif +} + +/** + * @brief Returns the D3PCLK1 frequency + * @note Each time D3PCLK1 changes, this function must be called to update the + * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval D3PCLK1 frequency + */ +uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) +{ +#if defined(RCC_D3CFGR_D3PPRE) + /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); +#else + /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); +#endif +} +/** +* @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency + * @note The PLL2 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL2CLK changes, this function must be called to update the + * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL2_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) +{ + uint32_t pllsource, pll2m, pll2fracen, hsivalue; + float_t fracn2, pll2vco; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N + PLL2xCLK = PLL2_VCO / PLL2x + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); + pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; + fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); + + if (pll2m != 0U) + { + switch (pllsource) + { + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + } + else + { + pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + } + break; + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + } + PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; + PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; + PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; + } + else + { + PLL2_Clocks->PLL2_P_Frequency = 0U; + PLL2_Clocks->PLL2_Q_Frequency = 0U; + PLL2_Clocks->PLL2_R_Frequency = 0U; + } +} + +/** +* @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency + * @note The PLL3 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL3CLK changes, this function must be called to update the + * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL3_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) +{ + uint32_t pllsource, pll3m, pll3fracen, hsivalue; + float_t fracn3, pll3vco; + + /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N + PLL3xCLK = PLL3_VCO / PLLxR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; + pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; + fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); + + if (pll3m != 0U) + { + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + } + else + { + pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + } + break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + } + PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; + PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; + PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; + } + else + { + PLL3_Clocks->PLL3_P_Frequency = 0U; + PLL3_Clocks->PLL3_Q_Frequency = 0U; + PLL3_Clocks->PLL3_R_Frequency = 0U; + } + +} + +/** +* @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency + * @note The PLL1 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL1CLK changes, this function must be called to update the + * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL1_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) +{ + uint32_t pllsource, pll1m, pll1fracen, hsivalue; + float_t fracn1, pll1vco; + + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); + pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; + fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); + + if (pll1m != 0U) + { + switch (pllsource) + { + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + + PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; + PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; + PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; + } + else + { + PLL1_Clocks->PLL1_P_Frequency = 0U; + PLL1_Clocks->PLL1_Q_Frequency = 0U; + PLL1_Clocks->PLL1_R_Frequency = 0U; + } + +} + +/** + * @brief Returns the main System frequency + * @note Each time System clock changes, this function must be called to update the + * right core clock value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCCEx_GetD1SysClockFreq(void) +{ + uint32_t common_system_clock; + +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + return common_system_clock; +} +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions + * @brief Extended Peripheral Control functions + * @{ + */ +/** + * @brief Enables the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Disables the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + /* Disable LSE CSS IT if any */ + __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); +} + +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note LSE Clock Security System Interrupt is mapped on EXTI line 18 + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + /* Enable IT on EXTI Line 18 */ +#if defined(DUAL_CORE) && defined(CORE_CM4) + __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT(); +#else + __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); +#endif /* DUAL_CORE && CORE_CM4 */ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); +} + +/** + * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock + * @param WakeUpClk: Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection + * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection + * @note This function shall not be called after the Clock Security System on HSE has been + * enabled. + * @retval None + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Configure the oscillator Kernel clock source for wakeup from Stop + * @param WakeUpClk: Kernel Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection + * @retval None + */ +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable COREx boot independently of CMx_B option byte value + * @param RCC_BootCx: Boot Core to be enabled + * This parameter can be one of the following values: + * @arg RCC_BOOT_C1: CM7 core selection + * @arg RCC_BOOT_C2: CM4 core selection + * @note This bit can be set by software but is cleared by hardware after a system reset or STANDBY + * + * @retval None + */ +void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx) +{ + assert_param(IS_RCC_BOOT_CORE(RCC_BootCx)); + SET_BIT(RCC->GCR, RCC_BootCx) ; +} + +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +/** + * @brief Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs + * @param RCC_WWDGx: WWDGx to be configured + * This parameter can be one of the following values: + * @arg RCC_WWDG1: WWDG1 generates system reset + * @arg RCC_WWDG2: WWDG2 generates system reset + * @note This bit can be set by software but is cleared by hardware during a system reset + * + * @retval None + */ +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) +{ + assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); + SET_BIT(RCC->GCR, RCC_WWDGx) ; +} + +#else +#if defined(RCC_GCR_WW1RSC) +/** + * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs + * @param RCC_WWDGx: WWDGx to be configured + * This parameter can be one of the following values: + * @arg RCC_WWDG1: WWDG1 generates system reset + * @note This bit can be set by software but is cleared by hardware during a system reset + * + * @retval None + */ +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) +{ + assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); + SET_BIT(RCC->GCR, RCC_WWDGx) ; +} +#endif +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Resets CRS registers to their default values. + (+++) Configures CRS registers with synchronization configuration + (+++) Enables automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the up-counting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (CRS_IRQn/CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable CRS_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit) +{ + uint32_t value; + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2)) + { + /* Use Rev.Y value of USB2 */ + value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity); + } + else + { + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + } + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != (void *)NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** +* @brief Wait for CRS Synchronization status. +* @param Timeout Duration of the time-out +* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization +* frequency. +* @note If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. +* @retval Combination of Synchronization status +* This parameter can be a combination of the following values: +* @arg @ref RCC_CRS_TIMEOUT +* @arg @ref RCC_CRS_SYNCOK +* @arg @ref RCC_CRS_SYNCWARN +* @arg @ref RCC_CRS_SYNCERR +* @arg @ref RCC_CRS_SYNCMISS +* @arg @ref RCC_CRS_TRIMOVF +*/ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart; + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or time-out detection */ + do + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } + while (RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + { + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + { + crserror |= RCC_CRS_SYNCERR; + } + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + { + crserror |= RCC_CRS_SYNCMISS; + } + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCCEx_Private_functions RCCEx Private Functions + * @{ + */ +/** + * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it + * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration parameters as well as VCI, VCO clock ranges. + * @param Divider divider parameter to be updated + * @note PLL2 is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider) +{ + + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M)); + assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N)); + assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P)); + assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R)); + assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q)); + assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); + assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); + assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); + + /* Check that PLL2 OSC clock source is already set */ + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + { + return HAL_ERROR; + } + + + else + { + /* Disable PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure PLL2 multiplication and division factors. */ + __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, + pll2->PLL2N, + pll2->PLL2P, + pll2->PLL2Q, + pll2->PLL2R); + + /* Select PLL2 input reference frequency range: VCI */ + __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; + + /* Select PLL2 output frequency range : VCO */ + __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; + + /* Disable PLL2FRACN . */ + __HAL_RCC_PLL2FRACN_DISABLE(); + + /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); + + /* Enable PLL2FRACN . */ + __HAL_RCC_PLL2FRACN_ENABLE(); + + /* Enable the PLL2 clock output */ + if (Divider == DIVIDER_P_UPDATE) + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); + } + else if (Divider == DIVIDER_Q_UPDATE) + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); + } + else + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); + } + + /* Enable PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + + return status; +} + + +/** + * @brief Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it + * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that + * contains the configuration parameters as well as VCI, VCO clock ranges. + * @param Divider divider parameter to be updated + * @note PLL3 is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M)); + assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N)); + assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P)); + assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R)); + assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q)); + assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); + assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); + assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); + + /* Check that PLL3 OSC clock source is already set */ + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + { + return HAL_ERROR; + } + + + else + { + /* Disable PLL3. */ + __HAL_RCC_PLL3_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait till PLL3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the PLL3 multiplication and division factors. */ + __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, + pll3->PLL3N, + pll3->PLL3P, + pll3->PLL3Q, + pll3->PLL3R); + + /* Select PLL3 input reference frequency range: VCI */ + __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; + + /* Select PLL3 output frequency range : VCO */ + __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; + + /* Disable PLL3FRACN . */ + __HAL_RCC_PLL3FRACN_DISABLE(); + + /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); + + /* Enable PLL3FRACN . */ + __HAL_RCC_PLL3FRACN_ENABLE(); + + /* Enable the PLL3 clock output */ + if (Divider == DIVIDER_P_UPDATE) + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); + } + else if (Divider == DIVIDER_Q_UPDATE) + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); + } + else + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); + } + + /* Enable PLL3. */ + __HAL_RCC_PLL3_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + + return status; +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + + /* Clear RCC LSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + + + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c new file mode 100644 index 0000000..c0a36ed --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c @@ -0,0 +1,7922 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) + { + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + case TIM_CLOCKSOURCE_ITR4: + case TIM_CLOCKSOURCE_ITR5: + case TIM_CLOCKSOURCE_ITR6: + case TIM_CLOCKSOURCE_ITR7: + case TIM_CLOCKSOURCE_ITR8: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + case TIM_TS_ITR4: + case TIM_TS_ITR5: + case TIM_TS_ITR6: + case TIM_TS_ITR7: + case TIM_TS_ITR8: + case TIM_TS_ITR9: + case TIM_TS_ITR10: + case TIM_TS_ITR11: + case TIM_TS_ITR12: + case TIM_TS_ITR13: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_ITR4: Internal Trigger 4 (*) + * @arg TIM_TS_ITR5: Internal Trigger 5 + * @arg TIM_TS_ITR6: Internal Trigger 6 + * @arg TIM_TS_ITR7: Internal Trigger 7 + * @arg TIM_TS_ITR8: Internal Trigger 8 (*) + * @arg TIM_TS_ITR9: Internal Trigger 9 (*) + * @arg TIM_TS_ITR10: Internal Trigger 10 (*) + * @arg TIM_TS_ITR11: Internal Trigger 11 (*) + * @arg TIM_TS_ITR12: Internal Trigger 12 (*) + * @arg TIM_TS_ITR13: Internal Trigger 13 (*) + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * + * (*) Value not defined in all devices. + * + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c new file mode 100644 index 0000000..21ef06b --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c @@ -0,0 +1,2921 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#if defined(TIM_BDTR_BKBID) +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants + * @{ + */ +/* Timeout for break input rearm */ +#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +#endif /* TIM_BDTR_BKBID */ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Select timer input source. + (+) Enable or disable channel grouping. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR12: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR13: Internal trigger 13 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR12: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR13: Internal trigger 13 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR12: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR13: Internal trigger 13 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); +#if defined(TIM_BDTR_BKBID) + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); +#endif /* TIM_BDTR_BKBID */ + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); +#if defined(TIM_BDTR_BKBID) + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); +#endif /* TIM_BDTR_BKBID */ + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); +#if defined(TIM_BDTR_BKBID) + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); +#endif /* TIM_BDTR_BKBID */ + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); +#if defined(TIM_BDTR_BKBID) + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); +#endif /* TIM_BDTR_BKBID */ + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + } + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; + bkin_polarity_mask = TIM1_AF1_BKINP; + bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP1: + { + bkin_enable_mask = TIM1_AF1_BKCMP1E; + bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP1P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP2: + { + bkin_enable_mask = TIM1_AF1_BKCMP2E; + bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP2P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_DFSDM1: + { + bkin_enable_mask = TIM1_AF1_BKDF1BK0E; + bkin_enable_bitpos = TIM1_AF1_BKDF1BK0E_Pos; + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; + break; + } + + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} +#endif /*TIM_BREAK_INPUT_SUPPORT */ + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter is one of the following values: + * @arg TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO + * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output + * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output + * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 + * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 + * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 + * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 + * + * For TIM2, the parameter is one of the following values: + * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO + * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output + * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output + * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE + * @arg TIM_TIM2_ETR_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A + * @arg TIM_TIM2_ETR_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B + * + * For TIM3, the parameter is one of the following values: + * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO + * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output + * + * For TIM5, the parameter is one of the following values: + * @arg TIM_TIM5_ETR_GPIO: TIM5_ETR is connected to GPIO + * @arg TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*) + * @arg TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*) + * @arg TIM_TIM5_ETR_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*) + * @arg TIM_TIM5_ETR_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*) + * + * For TIM8, the parameter is one of the following values: + * @arg TIM_TIM8_ETR_GPIO: TIM8_ETR is connected to GPIO + * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output + * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output + * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 + * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 + * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 + * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 + * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 + * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 + * + * For TIM23, the parameter is one of the following values: (*) + * @arg TIM_TIM23_ETR_GPIO TIM23_ETR is connected to GPIO + * @arg TIM_TIM23_ETR_COMP1 TIM23_ETR is connected to COMP1 output + * @arg TIM_TIM23_ETR_COMP2 TIM23_ETR is connected to COMP2 output + * + * For TIM24, the parameter is one of the following values: (*) + * @arg TIM_TIM24_ETR_GPIO TIM24_ETR is connected to GPIO + * @arg TIM_TIM24_ETR_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A + * @arg TIM_TIM24_ETR_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B + * @arg TIM_TIM24_ETR_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A + * @arg TIM_TIM24_ETR_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B + * + * (*) Value not defined in all devices. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + __HAL_LOCK(htim); + + MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Select the timer input source + * @param htim TIM handle. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TI1 input channel + * @arg TIM_CHANNEL_2: TI2 input channel + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: + * For TIM1, the parameter is one of the following values: + * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output + * + * For TIM2, the parameter is one of the following values: + * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO + * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output + * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output + * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output + * + * For TIM3, the parameter is one of the following values: + * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO + * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output + * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output + * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output + * + * For TIM5, the parameter is one of the following values: + * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO + * @arg TIM_TIM5_TI1_CAN_TMP: TIM5 TI1 is connected to CAN TMP + * @arg TIM_TIM5_TI1_CAN_RTP: TIM5 TI1 is connected to CAN RTP + * + * For TIM8, the parameter is one of the following values: + * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO + * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output + * + * For TIM12, the parameter can have the following values: (*) + * @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO + * @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS + * + * For TIM15, the parameter is one of the following values: + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1 + * @arg TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1 + * @arg TIM_TIM15_TI1_TIM4_CH1: TIM15 TI1 is connected to TIM4 CH1 + * @arg TIM_TIM15_TI1_RCC_LSE: TIM15 TI1 is connected to LSE + * @arg TIM_TIM15_TI1_RCC_CSI: TIM15 TI1 is connected to CSI + * @arg TIM_TIM15_TI1_RCC_MCO2: TIM15 TI1 is connected to MCO2 + * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO + * @arg TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2 + * @arg TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2 + * @arg TIM_TIM15_TI2_TIM4_CH2: TIM15 TI2 is connected to TIM4 CH2 + * + * For TIM16, the parameter can have the following values: + * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_TI1_RCC_LSI: TIM16 TI1 is connected to LSI + * @arg TIM_TIM16_TI1_RCC_LSE: TIM16 TI1 is connected to LSE + * @arg TIM_TIM16_TI1_WKUP_IT: TIM16 TI1 is connected to RTC wakeup interrupt + * + * For TIM17, the parameter can have the following values: + * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO + * @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*) + * @arg TIM_TIM17_TI1_RCC_HSE1MHZ: TIM17 TI1 is connected to HSE 1MHz + * @arg TIM_TIM17_TI1_RCC_MCO1: TIM17 TI1 is connected to MCO1 + * + * For TIM23, the parameter can have the following values: (*) + * @arg TIM_TIM23_TI4_GPIO TIM23_TI4 is connected to GPIO + * @arg TIM_TIM23_TI4_COMP1 TIM23_TI4 is connected to COMP1 output + * @arg TIM_TIM23_TI4_COMP2 TIM23_TI4 is connected to COMP2 output + * @arg TIM_TIM23_TI4_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output + * + * For TIM24, the parameter can have the following values: (*) + * @arg TIM_TIM24_TI1_GPIO TIM24_TI1 is connected to GPIO + * @arg TIM_TIM24_TI1_CAN_TMP TIM24_TI1 is connected to CAN_TMP + * @arg TIM_TIM24_TI1_CAN_RTP TIM24_TI1 is connected to CAN_RTP + * @arg TIM_TIM24_TI1_CAN_SOC TIM24_TI1 is connected to CAN_SOC + * + * (*) Value not defined in all devices. \n + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TISEL(TISelection)); + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); + break; + case TIM_CHANNEL_2: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); + break; + case TIM_CHANNEL_3: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection); + break; + case TIM_CHANNEL_4: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection); + break; + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#if defined(TIM_BDTR_BKBID) + +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to disarm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); + } + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Arm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to arm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note Arming is possible at anytime, even if fault is present. + * @note Break input is automatically armed as soon as MOE bit is set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) + { + /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif /* TIM_BDTR_BKBID */ + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Commutation callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Commutation half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/FDCAN.ioc b/FDCAN.ioc new file mode 100644 index 0000000..c7f357b --- /dev/null +++ b/FDCAN.ioc @@ -0,0 +1,282 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +CORTEX_M7.IPParameters=default_mode_Activation +CORTEX_M7.default_mode_Activation=1 +FDCAN1.AutoRetransmission=ENABLE +FDCAN1.CalculateBaudRateNominal=1000000 +FDCAN1.CalculateTimeBitNominal=1000 +FDCAN1.CalculateTimeQuantumNominal=50.0 +FDCAN1.DataPrescaler=5 +FDCAN1.DataSyncJumpWidth=5 +FDCAN1.DataTimeSeg1=14 +FDCAN1.DataTimeSeg2=5 +FDCAN1.ExtFiltersNbr=1 +FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,ProtocolException,NominalSyncJumpWidth,DataPrescaler,DataSyncJumpWidth,DataTimeSeg1,DataTimeSeg2,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2,RxFifo0ElmtsNbr,TxFifoQueueElmtsNbr,StdFiltersNbr,RxFifo0ElmtSize,TxElmtSize,AutoRetransmission,ExtFiltersNbr +FDCAN1.NominalPrescaler=5 +FDCAN1.NominalSyncJumpWidth=5 +FDCAN1.NominalTimeSeg1=14 +FDCAN1.NominalTimeSeg2=5 +FDCAN1.ProtocolException=ENABLE +FDCAN1.RxFifo0ElmtSize=FDCAN_DATA_BYTES_64 +FDCAN1.RxFifo0ElmtsNbr=8 +FDCAN1.StdFiltersNbr=1 +FDCAN1.TxElmtSize=FDCAN_DATA_BYTES_64 +FDCAN1.TxFifoQueueElmtsNbr=8 +FDCAN2.AutoRetransmission=ENABLE +FDCAN2.CalculateBaudRateNominal=1000000 +FDCAN2.CalculateTimeBitNominal=1000 +FDCAN2.CalculateTimeQuantumNominal=50.0 +FDCAN2.DataPrescaler=1 +FDCAN2.DataSyncJumpWidth=5 +FDCAN2.DataTimeSeg1=14 +FDCAN2.DataTimeSeg2=5 +FDCAN2.ExtFiltersNbr=1 +FDCAN2.FrameFormat=FDCAN_FRAME_FD_BRS +FDCAN2.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,FrameFormat,AutoRetransmission,StdFiltersNbr,ExtFiltersNbr,RxFifo0ElmtsNbr,NominalSyncJumpWidth,DataPrescaler,DataSyncJumpWidth,DataTimeSeg1,DataTimeSeg2,MessageRAMOffset,RxFifo1ElmtsNbr,RxFifo1ElmtSize,TxFifoQueueElmtsNbr,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2,ProtocolException +FDCAN2.MessageRAMOffset=831 +FDCAN2.NominalPrescaler=5 +FDCAN2.NominalSyncJumpWidth=5 +FDCAN2.NominalTimeSeg1=14 +FDCAN2.NominalTimeSeg2=5 +FDCAN2.ProtocolException=ENABLE +FDCAN2.RxFifo0ElmtsNbr=0 +FDCAN2.RxFifo1ElmtSize=FDCAN_DATA_BYTES_64 +FDCAN2.RxFifo1ElmtsNbr=8 +FDCAN2.StdFiltersNbr=1 +FDCAN2.TxFifoQueueElmtsNbr=8 +FDCAN3.AutoRetransmission=ENABLE +FDCAN3.CalculateBaudRateNominal=1000000 +FDCAN3.CalculateTimeBitNominal=1000 +FDCAN3.CalculateTimeQuantumNominal=50.0 +FDCAN3.DataPrescaler=5 +FDCAN3.DataSyncJumpWidth=5 +FDCAN3.DataTimeSeg1=14 +FDCAN3.DataTimeSeg2=5 +FDCAN3.FrameFormat=FDCAN_FRAME_FD_NO_BRS +FDCAN3.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,MessageRAMOffset,FrameFormat,AutoRetransmission,ProtocolException,NominalSyncJumpWidth,DataPrescaler,DataSyncJumpWidth,DataTimeSeg1,DataTimeSeg2,StdFiltersNbr,RxFifo1ElmtsNbr,RxFifo1ElmtSize,TxFifoQueueElmtsNbr,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2 +FDCAN3.MessageRAMOffset=1662 +FDCAN3.NominalPrescaler=5 +FDCAN3.NominalSyncJumpWidth=5 +FDCAN3.NominalTimeSeg1=14 +FDCAN3.NominalTimeSeg2=5 +FDCAN3.ProtocolException=ENABLE +FDCAN3.RxFifo1ElmtSize=FDCAN_DATA_BYTES_64 +FDCAN3.RxFifo1ElmtsNbr=8 +FDCAN3.StdFiltersNbr=1 +FDCAN3.TxFifoQueueElmtsNbr=8 +FREERTOS.IPParameters=Tasks01 +FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +MMTAppRegionsCount=0 +MMTConfigApplied=false +Mcu.CPN=STM32H723VGT6 +Mcu.Family=STM32H7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=FDCAN1 +Mcu.IP2=FDCAN2 +Mcu.IP3=FDCAN3 +Mcu.IP4=FREERTOS +Mcu.IP5=MEMORYMAP +Mcu.IP6=NVIC +Mcu.IP7=RCC +Mcu.IP8=SYS +Mcu.IPNb=9 +Mcu.Name=STM32H723VGTx +Mcu.Package=LQFP100 +Mcu.Pin0=PC13 +Mcu.Pin1=PC14-OSC32_IN +Mcu.Pin10=PB6 +Mcu.Pin11=VP_FREERTOS_VS_CMSIS_V2 +Mcu.Pin12=VP_SYS_VS_tim2 +Mcu.Pin13=VP_MEMORYMAP_VS_MEMORYMAP +Mcu.Pin2=PC15-OSC32_OUT +Mcu.Pin3=PH0-OSC_IN +Mcu.Pin4=PH1-OSC_OUT +Mcu.Pin5=PD12 +Mcu.Pin6=PD13 +Mcu.Pin7=PD0 +Mcu.Pin8=PD1 +Mcu.Pin9=PB5 +Mcu.PinsNb=14 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32H723VGTx +MxCube.Version=6.15.0 +MxDb.Version=DB.6.0.150 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.FDCAN1_IT0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.FDCAN2_IT1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.FDCAN3_IT1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false +NVIC.SavedPendsvIrqHandlerGenerated=true +NVIC.SavedSvcallIrqHandlerGenerated=true +NVIC.SavedSystickIrqHandlerGenerated=true +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true\:false +NVIC.TIM2_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.TimeBase=TIM2_IRQn +NVIC.TimeBaseIP=TIM2 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +PB5.Locked=true +PB5.Mode=FDCAN_Activate +PB5.Signal=FDCAN2_RX +PB6.Locked=true +PB6.Mode=FDCAN_Activate +PB6.Signal=FDCAN2_TX +PC13.GPIOParameters=GPIO_Label +PC13.GPIO_Label=Power_OUT2_EN +PC13.Locked=true +PC13.Signal=GPIO_Output +PC14-OSC32_IN.GPIOParameters=GPIO_Label +PC14-OSC32_IN.GPIO_Label=Power_OUT1_EN +PC14-OSC32_IN.Locked=true +PC14-OSC32_IN.Signal=GPIO_Output +PC15-OSC32_OUT.GPIOParameters=GPIO_Label +PC15-OSC32_OUT.GPIO_Label=Power_5V_EN +PC15-OSC32_OUT.Locked=true +PC15-OSC32_OUT.Signal=GPIO_Output +PD0.Locked=true +PD0.Mode=FDCAN_Activate +PD0.Signal=FDCAN1_RX +PD1.Locked=true +PD1.Mode=FDCAN_Activate +PD1.Signal=FDCAN1_TX +PD12.Mode=FDCAN_Activate +PD12.Signal=FDCAN3_RX +PD13.Mode=FDCAN_Activate +PD13.Signal=FDCAN3_TX +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32H723VGTx +ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.12.1 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=FDCAN.ioc +ProjectManager.ProjectName=FDCAN +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5.32 +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_FDCAN1_Init-FDCAN1-false-HAL-true,4-MX_FDCAN2_Init-FDCAN2-false-HAL-true,5-MX_FDCAN3_Init-FDCAN3-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.ADCFreq_Value=100000000 +RCC.AHB12Freq_Value=240000000 +RCC.AHB4Freq_Value=240000000 +RCC.APB1Freq_Value=120000000 +RCC.APB2Freq_Value=120000000 +RCC.APB3Freq_Value=120000000 +RCC.APB4Freq_Value=120000000 +RCC.AXIClockFreq_Value=240000000 +RCC.CECFreq_Value=32000 +RCC.CKPERFreq_Value=64000000 +RCC.CortexFreq_Value=480000000 +RCC.CpuClockFreq_Value=480000000 +RCC.D1CPREFreq_Value=480000000 +RCC.D1PPRE=RCC_APB3_DIV2 +RCC.D2PPRE1=RCC_APB1_DIV2 +RCC.D2PPRE2=RCC_APB2_DIV2 +RCC.D3PPRE=RCC_APB4_DIV2 +RCC.DFSDMACLkFreq_Value=120000000 +RCC.DFSDMFreq_Value=120000000 +RCC.DIVM1=2 +RCC.DIVM2=24 +RCC.DIVN1=40 +RCC.DIVN2=200 +RCC.DIVP1=1 +RCC.DIVP1Freq_Value=480000000 +RCC.DIVP2Freq_Value=100000000 +RCC.DIVP3Freq_Value=48375000 +RCC.DIVQ1=4 +RCC.DIVQ1Freq_Value=120000000 +RCC.DIVQ2Freq_Value=100000000 +RCC.DIVQ3Freq_Value=48375000 +RCC.DIVR1Freq_Value=240000000 +RCC.DIVR2Freq_Value=100000000 +RCC.DIVR3Freq_Value=48375000 +RCC.FDCANCLockSelection=RCC_FDCANCLKSOURCE_PLL2 +RCC.FDCANFreq_Value=100000000 +RCC.FMCFreq_Value=240000000 +RCC.FamilyName=M +RCC.HCLK3ClockFreq_Value=240000000 +RCC.HCLKFreq_Value=240000000 +RCC.HPRE=RCC_HCLK_DIV2 +RCC.HSE_VALUE=24000000 +RCC.I2C123Freq_Value=120000000 +RCC.I2C4Freq_Value=120000000 +RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVN1,DIVN2,DIVP1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANCLockSelection,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value +RCC.LPTIM1Freq_Value=120000000 +RCC.LPTIM2Freq_Value=120000000 +RCC.LPTIM345Freq_Value=120000000 +RCC.LPUART1Freq_Value=120000000 +RCC.LTDCFreq_Value=48375000 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=480000000 +RCC.PLLFRACN=0 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.QSPIFreq_Value=240000000 +RCC.RNGFreq_Value=48000000 +RCC.RTCFreq_Value=32000 +RCC.SAI1Freq_Value=120000000 +RCC.SAI4AFreq_Value=120000000 +RCC.SAI4BFreq_Value=120000000 +RCC.SDMMCFreq_Value=120000000 +RCC.SPDIFRXFreq_Value=120000000 +RCC.SPI123Freq_Value=120000000 +RCC.SPI45Freq_Value=120000000 +RCC.SPI6Freq_Value=120000000 +RCC.SWPMI1Freq_Value=120000000 +RCC.SYSCLKFreq_VALUE=480000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.Tim1OutputFreq_Value=240000000 +RCC.Tim2OutputFreq_Value=240000000 +RCC.TraceFreq_Value=64000000 +RCC.USART16Freq_Value=120000000 +RCC.USART234578Freq_Value=120000000 +RCC.USBFreq_Value=120000000 +RCC.VCO1OutputFreq_Value=480000000 +RCC.VCO2OutputFreq_Value=200000000 +RCC.VCO3OutputFreq_Value=96750000 +RCC.VCOInput1Freq_Value=12000000 +RCC.VCOInput2Freq_Value=1000000 +RCC.VCOInput3Freq_Value=750000 +VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 +VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 +VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg +VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP +VP_SYS_VS_tim2.Mode=TIM2 +VP_SYS_VS_tim2.Signal=SYS_VS_tim2 +board=custom +rtos.0.ip=FREERTOS diff --git a/MDK-ARM/DebugConfig/FDCAN_STM32H723VGTx_1.0.2.dbgconf b/MDK-ARM/DebugConfig/FDCAN_STM32H723VGTx_1.0.2.dbgconf new file mode 100644 index 0000000..baeb2bb --- /dev/null +++ b/MDK-ARM/DebugConfig/FDCAN_STM32H723VGTx_1.0.2.dbgconf @@ -0,0 +1,102 @@ +// File: STM32H723_725_730_733_735.dbgconf +// Version: 1.0.2 +// Note: refer to STM32H723/733, STM32H725/735 and STM32H730 Value line reference manual (RM0468) +// refer to STM32H723 STM32H725 STM32H730 STM32H733 STM32H735 datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// DBGMCU configuration register (DBGMCU_CR) +// TRGOEN External trigger output enable +// DBGSTBY_D3 Allow debug in D3 Standby mode +// DBGSTOP_D3 Allow debug in D3 Stop mode +// DBGSTBY_D2 Allow D2 domain debug in Standby mode +// DBGSTOP_D2 Allow D2 domain debug in Stop mode +// DBGSLEEP_D2 Allow D2 domain debug in Sleep mode +// DBGSTBY_D1 Allow D1 domain debug in Standby mode +// DBGSTOP_D1 Allow D1 domain debug in Stop mode +// DBGSLEEP_D1 Allow D1 domain debug in Sleep mode +// +DbgMCU_CR = 0x00000007; + +// DBGMCU APB3 peripheral freeze register (DBGMCU_APB3FZ1) +// Reserved bits must be kept at reset value +// WWDG1 WWDG1 stop in debug +// +DbgMCU_APB3_Fz1 = 0x00000040; + +// DBGMCU APB1L peripheral freeze register (DBGMCU_APB1LFZ1) +// Reserved bits must be kept at reset value +// I2C5 I2C SMBUS timeout stop in debug +// I2C3 I2C3 SMBUS timeout stop in debug +// I2C2 I2C2 SMBUS timeout stop in debug +// I2C1 I2C1 SMBUS timeout stop in debug +// LPTIM1 LPTIM1 stop in debug +// TIM14 TIM14 stop in debug +// TIM13 TIM13 stop in debug +// TIM12 TIM12 stop in debug +// TIM7 TIM7 stop in debug +// TIM6 TIM6 stop in debug +// TIM5 TIM5 stop in debug +// TIM4 TIM4 stop in debug +// TIM3 TIM3 stop in debug +// TIM2 TIM2 stop in debug +// +DbgMCU_APB1L_Fz1 = 0x02E003FF; + +// DBGMCU APB1H peripheral freeze register (DBGMCU_APB1HFZ1) +// Reserved bits must be kept at reset value +// TIM24 TIM24 stop in debug +// TIM23 TIM23 stop in debug +// +DbgMCU_APB1H_Fz1 = 0x03000000; + +// DBGMCU APB2 peripheral freeze register (DBGMCU_APB2FZ1) +// Reserved bits must be kept at reset value +// TIM17 TIM17 stop in debug +// TIM16 TIM16 stop in debug +// TIM15 TIM15 stop in debug +// TIM8 TIM8 stop in debug +// TIM1 TIM1 stop in debug +// +DbgMCU_APB2_Fz1 = 0x00070003; + +// DBGMCU APB4 peripheral freeze register (DBGMCU_APB4FZ1) +// Reserved bits must be kept at reset value +// IWDG1 Independent watchdog for D1 stop in debug +// RTC RTC stop in debug +// LPTIM5 LPTIM5 stop in debug +// LPTIM4 LPTIM4 stop in debug +// LPTIM3 LPTIM2 stop in debug +// LPTIM2 LPTIM2 stop in debug +// I2C4 I2C4 SMBUS timeout stop in debug +// +DbgMCU_APB4_Fz1 = 0x00041E80; + +// TPIU Pin Routing (TRACECLK fixed on Pin PE2) +// TRACECLK: Pin PE2 +// TRACED0 +// ETM Trace Data 0 +// <0x00040003=> Pin PE3 +// <0x00020001=> Pin PC1 +// <0x0006000D=> Pin PG13 +// TRACED1 +// ETM Trace Data 1 +// <0x00040004=> Pin PE4 +// <0x00020008=> Pin PC8 +// <0x0006000E=> Pin PG14 +// TRACED2 +// ETM Trace Data 2 +// <0x00040005=> Pin PE5 +// <0x00030002=> Pin PD2 +// TRACED3 +// ETM Trace Data 3 +// <0x00040006=> Pin PE6 +// <0x0002000C=> Pin PC12 +// +TraceClk_Pin = 0x00040002; +TraceD0_Pin = 0x00040003; +TraceD1_Pin = 0x00040004; +TraceD2_Pin = 0x00040005; +TraceD3_Pin = 0x00040006; + +// <<< end of configuration section >>> diff --git a/MDK-ARM/FDCAN.uvguix.yxm23 b/MDK-ARM/FDCAN.uvguix.yxm23 new file mode 100644 index 0000000..54d95b6 --- /dev/null +++ b/MDK-ARM/FDCAN.uvguix.yxm23 @@ -0,0 +1,1977 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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b/MDK-ARM/FDCAN.uvoptx @@ -0,0 +1,968 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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100644 index 0000000..d0c5118 --- /dev/null +++ b/MDK-ARM/FDCAN/FDCAN.build_log.htm @@ -0,0 +1,195 @@ + + +
+
Vision Build Log

+
Tool Versions:

+IDE-Version: Vision V5.34.0.0
+Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: jasmine yxm2389287465@outlook.com, qut, LIC=JL28G-VQ49I-NNHAF-6ERW1-ZPP1C-KLZJD
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Plus  Version: 5.34.0.0
+Toolchain Path:  D:\cangming\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 7 (build 960)
+Assembler:       Armasm.exe V5.06 update 7 (build 960)
+Linker/Locator:  ArmLink.exe V5.06 update 7 (build 960)
+Library Manager: ArmAr.exe V5.06 update 7 (build 960)
+Hex Converter:   FromElf.exe V5.06 update 7 (build 960)
+CPU DLL:         SARMCM3.DLL V5.34.0.0
+Dialog DLL:      DCM.DLL V1.17.3.0
+Target DLL:      STLink\ST-LINKIII-KEIL_SWO.dll V3.0.8.0
+Dialog DLL:      TCM.DLL V1.48.0.0
+ 
+
Project:

+D:\STM32Projects_HAL\board-H7\FDCAN\MDK-ARM\FDCAN.uvprojx
+Project File Date:  12/26/2025
+
+
Output:

+*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'D:\cangming\ARM\ARMCC\Bin'
+Rebuild target 'FDCAN'
+Note: source file '..\User\bsp\fdcan.c' - object file renamed from 'FDCAN\fdcan.o' to 'FDCAN\fdcan_1.o'.
+assembling startup_stm32h723xx.s...
+compiling list.c...
+compiling croutine.c...
+compiling event_groups.c...
+compiling queue.c...
+compiling stream_buffer.c...
+compiling tasks.c...
+compiling timers.c...
+compiling freertos.c...
+compiling stm32h7xx_it.c...
+compiling gpio.c...
+compiling stm32h7xx_hal_pwr.c...
+compiling stm32h7xx_hal_flash.c...
+compiling stm32h7xx_hal_cortex.c...
+compiling heap_4.c...
+compiling stm32h7xx_hal_flash_ex.c...
+compiling system_stm32h7xx.c...
+compiling main.c...
+compiling stm32h7xx_hal_timebase_tim.c...
+compiling fdcan.c...
+compiling stm32h7xx_hal.c...
+compiling stm32h7xx_hal_gpio.c...
+compiling stm32h7xx_hal_msp.c...
+compiling stm32h7xx_hal_exti.c...
+compiling stm32h7xx_hal_i2c_ex.c...
+compiling stm32h7xx_hal_hsem.c...
+compiling stm32h7xx_hal_dma_ex.c...
+compiling stm32h7xx_hal_fdcan.c...
+compiling stm32h7xx_hal_pwr_ex.c...
+compiling stm32h7xx_hal_mdma.c...
+compiling stm32h7xx_hal_rcc_ex.c...
+compiling stm32h7xx_hal_tim_ex.c...
+compiling stm32h7xx_hal_tim.c...
+compiling stm32h7xx_hal_rcc.c...
+compiling port.c...
+compiling mm.c...
+compiling stm32h7xx_hal_i2c.c...
+compiling stm32h7xx_hal_dma.c...
+compiling crc16.c...
+..\User\component\user_math.h(179): warning:  #1-D: last line of file ends without a newline
+  /* USER FUNCTION END */
+..\User\component\crc16.c: 1 warning, 0 errors
+compiling filter.c...
+..\User\component\user_math.h(179): warning:  #1-D: last line of file ends without a newline
+  /* USER FUNCTION END */
+..\User\component\filter.c: 1 warning, 0 errors
+compiling pid.c...
+..\User\component\user_math.h(179): warning:  #1-D: last line of file ends without a newline
+  /* USER FUNCTION END */
+..\User\component\pid.c: 1 warning, 0 errors
+compiling user_math.c...
+..\User\component\user_math.h(179): warning:  #1-D: last line of file ends without a newline
+  /* USER FUNCTION END */
+..\User\component\user_math.c(147): warning:  #1-D: last line of file ends without a newline
+  /* USER FUNCTION END */
+..\User\component\user_math.c: 2 warnings, 0 errors
+compiling init.c...
+compiling user_task.c...
+compiling cmsis_os2.c...
+compiling blink.c...
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h(3901): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h(7969): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_RCC_DeInit(void);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h(7970): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h(7971): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h(142): error:  #20: identifier "HAL_LockTypeDef" is undefined
+    HAL_LockTypeDef                 Lock;                                                             /*!< DMA locking object                            */
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h(237): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h(238): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h(239): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h(240): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h(241): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h(242): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h(243): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h(1187): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h(1188): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h(1197): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h(1198): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h(1199): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h(1200): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h(1201): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h(1203): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h(1204): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h(208): error:  #20: identifier "HAL_LockTypeDef" is undefined
+    HAL_LockTypeDef       Lock;                                                                  /*!< MDMA locking object                    */
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h(640): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h(641): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h(642): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h(644): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h(645): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h(657): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h(658): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode);
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h(659): error:  #20: identifier "HAL_StatusTypeDef" is undefined
+  HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
+..\User\task\blink.c: 0 warnings, 30 errors
+compiling fdcan.c...
+..\User\bsp\fdcan.h(16): error:  #5: cannot open source input file "stdatomic.h": No such file or directory
+  #include 
+..\User\bsp\fdcan.c: 0 warnings, 1 error
+compiling time.c...
+../User/bsp/time.h(24): warning:  #1295-D: Deprecated declaration BSP_TIME_Get_ms - give arg types
+  uint32_t BSP_TIME_Get_ms();
+../User/bsp/time.h(26): warning:  #1295-D: Deprecated declaration BSP_TIME_Get_us - give arg types
+  uint64_t BSP_TIME_Get_us();
+../User/bsp/time.h(28): warning:  #1295-D: Deprecated declaration BSP_TIME_Get - give arg types
+  uint64_t BSP_TIME_Get();
+..\User\bsp\time.c(43): warning:  #1295-D: Deprecated declaration BSP_TIME_Get - give arg types
+  uint64_t BSP_TIME_Get() __attribute__((alias("BSP_TIME_Get_us")));
+..\User\bsp\time.c(81): warning:  #1-D: last line of file ends without a newline
+  /* USER FUNCTION END */
+..\User\bsp\time.c: 5 warnings, 0 errors
+"FDCAN\FDCAN.axf" - 31 Error(s), 10 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
+                ARM.CMSIS.5.7.0
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.4.0
+
+Package Vendor: Keil
+                https://www.keil.com/pack/Keil.STM32H7xx_DFP.4.1.3.pack
+                Keil.STM32H7xx_DFP.4.1.3
+                STMicroelectronics STM32H7 Series Device Support
+
+
Collection of Component include folders:

+  .\RTE\_FDCAN
+  D:\cangming\ARM\CMSIS\5.7.0\CMSIS\Core\Include
+
+
Collection of Component Files used:

+
+   * Component: ARM::CMSIS:CORE:5.4.0
+      Include file:  CMSIS\Core\Include\tz_context.h
+Target not created.
+Build Time Elapsed:  00:00:13
+
+ + diff --git a/MDK-ARM/FDCAN/FDCAN.hex b/MDK-ARM/FDCAN/FDCAN.hex new file mode 100644 index 0000000..f411457 --- /dev/null +++ b/MDK-ARM/FDCAN/FDCAN.hex @@ -0,0 +1,746 @@ +:020000040800F2 +:10000000600700246D030008B927000801270008D5 +:10001000B127000881040008392D00080000000005 +:10002000000000000000000000000000392A000865 +:100030008904000800000000F1270008412A000898 +:100040008B0300088B0300088B0300088B03000858 +:100050008B0300088B0300088B0300088B03000848 +:100060008B0300088B0300088B0300088B03000838 +:100070008B0300088B0300088B0300088B03000828 +:100080008B0300088B0300088B030008C1040008E1 +:100090008B0300088B0300088B0300088B03000808 +:1000A0008B0300088B0300088B0300088B030008F8 +:1000B000C92B00088B0300088B0300088B03000882 +:1000C0008B0300088B0300088B0300088B030008D8 +:1000D0008B0300088B0300088B0300088B030008C8 +:1000E0008B0300088B030008000000008B0300084E +:1000F0008B0300088B0300088B0300088B030008A8 +:100100008B0300088B0300088B0300088B03000897 +:100110008B0300088B0300088B0300088B03000887 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a/MDK-ARM/FDCAN/FDCAN.htm b/MDK-ARM/FDCAN/FDCAN.htm new file mode 100644 index 0000000..6848603 --- /dev/null +++ b/MDK-ARM/FDCAN/FDCAN.htm @@ -0,0 +1,1295 @@ + + +Static Call Graph - [FDCAN\FDCAN.axf] +
+

Static Call Graph for image FDCAN\FDCAN.axf

+

#<CALLGRAPH># ARM Linker, 6160001: Last Updated: Fri Dec 19 01:44:25 2025 +

+

Maximum Stack Usage = 320 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+__rt_entry_main ⇒ main ⇒ MX_FDCAN1_Init ⇒ HAL_FDCAN_Init ⇒ HAL_FDCAN_MspInit ⇒ HAL_RCCEx_PeriphCLKConfig ⇒ RCCEx_PLL3_Config +

+

+Functions with no stack information +

+ +

+

+Mutually Recursive functions +

  • ADC3_IRQHandler   ⇒   ADC3_IRQHandler
    +
  • BusFault_Handler   ⇒   BusFault_Handler
    +
  • HardFault_Handler   ⇒   HardFault_Handler
    +
  • MemManage_Handler   ⇒   MemManage_Handler
    +
  • NMI_Handler   ⇒   NMI_Handler
    +
  • UsageFault_Handler   ⇒   UsageFault_Handler
    + +

    +

    +Function Pointers +

      +
    • ADC3_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • ADC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • BDMA_Channel0_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • BDMA_Channel1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • BDMA_Channel2_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • BDMA_Channel3_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • BDMA_Channel4_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • BDMA_Channel5_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • BDMA_Channel6_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • BDMA_Channel7_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • BusFault_Handler from stm32h7xx_it.o(.text.BusFault_Handler) referenced from startup_stm32h723xx.o(RESET) +
    • CEC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • COMP1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • CORDIC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • CRS_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DCMI_PSSI_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DFSDM1_FLT0_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DFSDM1_FLT1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DFSDM1_FLT2_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DFSDM1_FLT3_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA1_Stream0_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA1_Stream1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA1_Stream2_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA1_Stream3_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA1_Stream4_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA1_Stream5_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA1_Stream6_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA1_Stream7_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA2D_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA2_Stream0_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA2_Stream1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA2_Stream2_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA2_Stream3_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA2_Stream4_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA2_Stream5_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA2_Stream6_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMA2_Stream7_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMAMUX1_OVR_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DMAMUX2_OVR_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DTS_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • DebugMon_Handler from stm32h7xx_it.o(.text.DebugMon_Handler) referenced from startup_stm32h723xx.o(RESET) +
    • ECC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • ETH_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • ETH_WKUP_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • EXTI0_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • EXTI15_10_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • EXTI1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • EXTI2_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • EXTI3_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • EXTI4_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • EXTI9_5_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • ExitRun0Mode from system_stm32h7xx.o(.text.ExitRun0Mode) referenced from startup_stm32h723xx.o(.text) +
    • FDCAN1_IT0_IRQHandler from stm32h7xx_it.o(.text.FDCAN1_IT0_IRQHandler) referenced from startup_stm32h723xx.o(RESET) +
    • FDCAN1_IT1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • FDCAN2_IT0_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • FDCAN2_IT1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • FDCAN3_IT0_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • FDCAN3_IT1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • FDCAN_CAL_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • FLASH_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • FMAC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • FMC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • FPU_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • HSEM1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • HardFault_Handler from stm32h7xx_it.o(.text.HardFault_Handler) referenced from startup_stm32h723xx.o(RESET) +
    • I2C1_ER_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • I2C1_EV_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • I2C2_ER_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • I2C2_EV_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • I2C3_ER_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • I2C3_EV_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • I2C4_ER_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • I2C4_EV_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • I2C5_ER_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • I2C5_EV_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • LPTIM1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • LPTIM2_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • LPTIM3_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • LPTIM4_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • LPTIM5_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • LPUART1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • LTDC_ER_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • LTDC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • MDIOS_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • MDIOS_WKUP_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • MDMA_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • MemManage_Handler from stm32h7xx_it.o(.text.MemManage_Handler) referenced from startup_stm32h723xx.o(RESET) +
    • NMI_Handler from stm32h7xx_it.o(.text.NMI_Handler) referenced from startup_stm32h723xx.o(RESET) +
    • OCTOSPI1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • OCTOSPI2_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • OTG_HS_EP1_IN_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • OTG_HS_EP1_OUT_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • OTG_HS_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • OTG_HS_WKUP_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • PVD_AVD_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • PendSV_Handler from stm32h7xx_it.o(.text.PendSV_Handler) referenced from startup_stm32h723xx.o(RESET) +
    • RCC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • RNG_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • RTC_Alarm_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • RTC_WKUP_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • Reset_Handler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SAI1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SAI4_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SDMMC1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SDMMC2_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SPDIF_RX_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SPI1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SPI2_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SPI3_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SPI4_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SPI5_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SPI6_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SVC_Handler from stm32h7xx_it.o(.text.SVC_Handler) referenced from startup_stm32h723xx.o(RESET) +
    • SWPMI1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • SysTick_Handler from stm32h7xx_it.o(.text.SysTick_Handler) referenced from startup_stm32h723xx.o(RESET) +
    • SystemInit from system_stm32h7xx.o(.text.SystemInit) referenced from startup_stm32h723xx.o(.text) +
    • TAMP_STAMP_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM15_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM16_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM17_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM1_BRK_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM1_CC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM1_TRG_COM_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM1_UP_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM23_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM24_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM2_IRQHandler from stm32h7xx_it.o(.text.TIM2_IRQHandler) referenced from startup_stm32h723xx.o(RESET) +
    • TIM3_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM4_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM5_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM6_DAC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM7_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM8_BRK_TIM12_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM8_CC_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM8_TRG_COM_TIM14_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • TIM8_UP_TIM13_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • UART4_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • UART5_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • UART7_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • UART8_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • UART9_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • USART10_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • USART1_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • USART2_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • USART3_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • USART6_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • UsageFault_Handler from stm32h7xx_it.o(.text.UsageFault_Handler) referenced from startup_stm32h723xx.o(RESET) +
    • WAKEUP_PIN_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • WWDG_IRQHandler from startup_stm32h723xx.o(.text) referenced from startup_stm32h723xx.o(RESET) +
    • __main from __main.o(!!!main) referenced from startup_stm32h723xx.o(.text) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main)) +

    [Calls]

    • >>   __rt_entry +
    • >>   __scatterload +
    +
    [Address Reference Count : 1]
    • startup_stm32h723xx.o(.text) +
    +

    __scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter)) +

    [Called By]

    • >>   __main +
    + +

    __scatterload_rt2 (Thumb, 44 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) +

    [Calls]

    • >>   __rt_entry +
    + +

    __scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_null (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_copy (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED) +

    [Calls]

    • >>   __scatterload_copy +
    +
    [Called By]
    • >>   __scatterload_copy +
    + +

    __scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED) + +

    __rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000)) +

    [Called By]

    • >>   __rt_entry_li +
    + +

    __rt_lib_init_fp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000001)) +

    [Calls]

    • >>   _fp_init +
    + +

    __rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E)) + +

    __rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C)) + +

    __rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B)) + +

    __rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021)) + +

    __rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032)) + +

    __rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030)) + +

    __rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F)) + +

    __rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023)) + +

    __rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A)) + +

    __rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011)) + +

    __rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013)) + +

    __rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015)) + +

    __rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017)) + +

    __rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019)) + +

    __rt_lib_init_preinit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004)) + +

    __rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E)) + +

    __rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033)) + +

    __rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D)) + +

    __rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025)) + +

    __rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C)) + +

    __rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000)) +

    [Called By]

    • >>   __rt_exit_ls +
    + +

    __rt_lib_shutdown_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)) + +

    __rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)) + +

    __rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)) + +

    __rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)) + +

    __rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)) + +

    __rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)) + +

    __rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)) + +

    __rt_entry (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000)) +

    [Called By]

    • >>   __main +
    • >>   __scatterload_rt2 +
    + +

    __rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002)) + +

    __rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __rt_entry_sh ⇒ __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_setup_stackheap +
    + +

    __rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)) +

    [Calls]

    • >>   __rt_lib_init +
    + +

    __rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009)) + +

    __rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)) +

    [Stack]

    • Max Depth = 320 + Unknown Stack Size +
    • Call Chain = __rt_entry_main ⇒ main ⇒ MX_FDCAN1_Init ⇒ HAL_FDCAN_Init ⇒ HAL_FDCAN_MspInit ⇒ HAL_RCCEx_PeriphCLKConfig ⇒ RCCEx_PLL3_Config +
    +
    [Calls]
    • >>   main +
    • >>   exit +
    + +

    __rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)) + +

    __rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000)) +

    [Called By]

    • >>   exit +
    + +

    __rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003)) +

    [Calls]

    • >>   __rt_lib_shutdown +
    + +

    __rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002)) + +

    __rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004)) +

    [Calls]

    • >>   _sys_exit +
    + +

    Reset_Handler (Thumb, 12 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    ADC3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +

    [Calls]

    • >>   ADC3_IRQHandler +
    +
    [Called By]
    • >>   ADC3_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32h723xx.o(RESET) +
    +

    ADC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    BDMA_Channel0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    BDMA_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    BDMA_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    BDMA_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    BDMA_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    BDMA_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    BDMA_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    BDMA_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    CEC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    COMP1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    CORDIC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    CRS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DCMI_PSSI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DFSDM1_FLT0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DFSDM1_FLT1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DFSDM1_FLT2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DFSDM1_FLT3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA1_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA1_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA1_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA1_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA1_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA1_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA1_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA1_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA2D_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA2_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA2_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA2_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA2_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA2_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA2_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA2_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMA2_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMAMUX1_OVR_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DMAMUX2_OVR_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    DTS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    ECC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    ETH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    ETH_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    FDCAN1_IT1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    FDCAN2_IT0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    FDCAN2_IT1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    FDCAN3_IT0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    FDCAN3_IT1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    FDCAN_CAL_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    FMAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    FMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    FPU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    HSEM1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    I2C3_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    I2C3_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    I2C4_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    I2C4_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    I2C5_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    I2C5_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    LPTIM1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    LPTIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    LPTIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    LPTIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    LPTIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    LPUART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    LTDC_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    LTDC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    MDIOS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    MDIOS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    MDMA_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    OCTOSPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    OCTOSPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    OTG_HS_EP1_IN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    OTG_HS_EP1_OUT_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    OTG_HS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    OTG_HS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    PVD_AVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    RNG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    RTC_Alarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    RTC_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SAI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SAI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SDMMC1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SDMMC2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SPDIF_RX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SPI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SPI5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SPI6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SWPMI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TAMP_STAMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM16_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM17_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM23_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM24_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM6_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM8_BRK_TIM12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM8_TRG_COM_TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    TIM8_UP_TIM13_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    UART7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    UART8_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    UART9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    USART10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    USART6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    WAKEUP_PIN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h723xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    __user_initial_stackheap (Thumb, 0 bytes, Stack size unknown bytes, startup_stm32h723xx.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    __aeabi_memclr4 (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text)) +

    [Called By]

    • >>   SystemClock_Config +
    + +

    __aeabi_memclr8 (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text)) +

    [Called By]

    • >>   HAL_FDCAN_MspInit +
    + +

    __rt_memclr_w (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text), UNUSED) + +

    _memset_w (Thumb, 74 bytes, Stack size 4 bytes, rt_memclr_w.o(.text), UNUSED) + +

    __use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __user_setup_stackheap (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_initial_stackheap +
    • >>   __user_perproc_libspace +
    +
    [Called By]
    • >>   __rt_entry_sh +
    + +

    exit (Thumb, 18 bytes, Stack size 8 bytes, exit.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = exit +
    +
    [Calls]
    • >>   __rt_exit +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    __user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    __user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    __user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    _sys_exit (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text)) +

    [Called By]

    • >>   __rt_exit_exit +
    + +

    __I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __semihosting_library_function (Thumb, 0 bytes, Stack size unknown bytes, indicate_semi.o(.text), UNUSED) + +

    BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_it.o(.text.BusFault_Handler)) +

    [Calls]

    • >>   BusFault_Handler +
    +
    [Called By]
    • >>   BusFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32h723xx.o(RESET) +
    +

    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_it.o(.text.DebugMon_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    Error_Handler (Thumb, 10 bytes, Stack size 0 bytes, main.o(.text.Error_Handler)) +

    [Called By]

    • >>   HAL_FDCAN_MspInit +
    • >>   SystemClock_Config +
    • >>   MX_FDCAN1_Init +
    + +

    ExitRun0Mode (Thumb, 26 bytes, Stack size 0 bytes, system_stm32h7xx.o(.text.ExitRun0Mode)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(.text) +
    +

    FDCAN1_IT0_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32h7xx_it.o(.text.FDCAN1_IT0_IRQHandler)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = FDCAN1_IT0_IRQHandler ⇒ HAL_FDCAN_IRQHandler +
    +
    [Calls]
    • >>   HAL_FDCAN_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32h723xx.o(RESET) +
    +

    HAL_FDCAN_ClockCalibrationCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ClockCalibrationCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_ErrorCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ErrorCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_ErrorStatusCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ErrorStatusCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_HighPriorityMessageCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_HighPriorityMessageCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_IRQHandler (Thumb, 754 bytes, Stack size 64 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = HAL_FDCAN_IRQHandler +
    +
    [Calls]
    • >>   HAL_FDCAN_TxFifoEmptyCallback +
    • >>   HAL_FDCAN_TxEventFifoCallback +
    • >>   HAL_FDCAN_TxBufferCompleteCallback +
    • >>   HAL_FDCAN_TxBufferAbortCallback +
    • >>   HAL_FDCAN_TimestampWraparoundCallback +
    • >>   HAL_FDCAN_TimeoutOccurredCallback +
    • >>   HAL_FDCAN_TT_TimeMarkCallback +
    • >>   HAL_FDCAN_TT_StopWatchCallback +
    • >>   HAL_FDCAN_TT_ScheduleSyncCallback +
    • >>   HAL_FDCAN_TT_GlobalTimeCallback +
    • >>   HAL_FDCAN_RxFifo1Callback +
    • >>   HAL_FDCAN_RxFifo0Callback +
    • >>   HAL_FDCAN_RxBufferNewMessageCallback +
    • >>   HAL_FDCAN_HighPriorityMessageCallback +
    • >>   HAL_FDCAN_ErrorStatusCallback +
    • >>   HAL_FDCAN_ErrorCallback +
    • >>   HAL_FDCAN_ClockCalibrationCallback +
    +
    [Called By]
    • >>   FDCAN1_IT0_IRQHandler +
    + +

    HAL_FDCAN_Init (Thumb, 534 bytes, Stack size 24 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Init)) +

    [Stack]

    • Max Depth = 312 + Unknown Stack Size +
    • Call Chain = HAL_FDCAN_Init ⇒ HAL_FDCAN_MspInit ⇒ HAL_RCCEx_PeriphCLKConfig ⇒ RCCEx_PLL3_Config +
    +
    [Calls]
    • >>   FDCAN_CalcultateRamBlockAddresses +
    • >>   HAL_GetTick +
    • >>   HAL_FDCAN_MspInit +
    +
    [Called By]
    • >>   MX_FDCAN1_Init +
    + +

    HAL_FDCAN_MspInit (Thumb, 166 bytes, Stack size 232 bytes, fdcan.o(.text.HAL_FDCAN_MspInit)) +

    [Stack]

    • Max Depth = 288 + Unknown Stack Size +
    • Call Chain = HAL_FDCAN_MspInit ⇒ HAL_RCCEx_PeriphCLKConfig ⇒ RCCEx_PLL3_Config +
    +
    [Calls]
    • >>   HAL_RCCEx_PeriphCLKConfig +
    • >>   HAL_NVIC_SetPriority +
    • >>   HAL_NVIC_EnableIRQ +
    • >>   HAL_GPIO_Init +
    • >>   Error_Handler +
    • >>   __aeabi_memclr8 +
    +
    [Called By]
    • >>   HAL_FDCAN_Init +
    + +

    HAL_FDCAN_RxBufferNewMessageCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxBufferNewMessageCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_RxFifo0Callback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxFifo0Callback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_RxFifo1Callback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxFifo1Callback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_TT_GlobalTimeCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_GlobalTimeCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_TT_ScheduleSyncCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ScheduleSyncCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_TT_StopWatchCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_StopWatchCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_TT_TimeMarkCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_TimeMarkCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_TimeoutOccurredCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TimeoutOccurredCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_TimestampWraparoundCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TimestampWraparoundCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_TxBufferAbortCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxBufferAbortCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_TxBufferCompleteCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxBufferCompleteCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_TxEventFifoCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxEventFifoCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_FDCAN_TxFifoEmptyCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxFifoEmptyCallback)) +

    [Called By]

    • >>   HAL_FDCAN_IRQHandler +
    + +

    HAL_GPIO_Init (Thumb, 416 bytes, Stack size 48 bytes, stm32h7xx_hal_gpio.o(.text.HAL_GPIO_Init)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = HAL_GPIO_Init +
    +
    [Called By]
    • >>   HAL_FDCAN_MspInit +
    + +

    HAL_GetTick (Thumb, 12 bytes, Stack size 0 bytes, stm32h7xx_hal.o(.text.HAL_GetTick)) +

    [Called By]

    • >>   RCCEx_PLL3_Config +
    • >>   RCCEx_PLL2_Config +
    • >>   HAL_RCCEx_PeriphCLKConfig +
    • >>   HAL_FDCAN_Init +
    • >>   HAL_RCC_OscConfig +
    • >>   HAL_RCC_ClockConfig +
    • >>   HAL_PWREx_ConfigSupply +
    + +

    HAL_IncTick (Thumb, 26 bytes, Stack size 0 bytes, stm32h7xx_hal.o(.text.HAL_IncTick)) +

    [Called By]

    • >>   HAL_TIM_PeriodElapsedCallback +
    + +

    HAL_Init (Thumb, 100 bytes, Stack size 8 bytes, stm32h7xx_hal.o(.text.HAL_Init)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = HAL_Init ⇒ HAL_InitTick ⇒ HAL_TIM_Base_Init ⇒ TIM_Base_SetConfig +
    +
    [Calls]
    • >>   HAL_RCC_GetSysClockFreq +
    • >>   HAL_NVIC_SetPriorityGrouping +
    • >>   HAL_InitTick +
    • >>   HAL_MspInit +
    +
    [Called By]
    • >>   main +
    + +

    HAL_InitTick (Thumb, 160 bytes, Stack size 56 bytes, stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = HAL_InitTick ⇒ HAL_TIM_Base_Init ⇒ TIM_Base_SetConfig +
    +
    [Calls]
    • >>   HAL_TIM_Base_Start_IT +
    • >>   HAL_TIM_Base_Init +
    • >>   HAL_RCC_GetPCLK1Freq +
    • >>   HAL_RCC_GetClockConfig +
    • >>   HAL_NVIC_SetPriority +
    • >>   HAL_NVIC_EnableIRQ +
    +
    [Called By]
    • >>   HAL_RCC_ClockConfig +
    • >>   HAL_Init +
    + +

    HAL_MspInit (Thumb, 32 bytes, Stack size 4 bytes, stm32h7xx_hal_msp.o(.text.HAL_MspInit)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = HAL_MspInit +
    +
    [Called By]
    • >>   HAL_Init +
    + +

    HAL_NVIC_EnableIRQ (Thumb, 8 bytes, Stack size 8 bytes, stm32h7xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_NVIC_EnableIRQ +
    +
    [Calls]
    • >>   __NVIC_EnableIRQ +
    +
    [Called By]
    • >>   HAL_InitTick +
    • >>   HAL_FDCAN_MspInit +
    + +

    HAL_NVIC_SetPriority (Thumb, 30 bytes, Stack size 16 bytes, stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriority)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_NVIC_SetPriority +
    +
    [Calls]
    • >>   __NVIC_SetPriority +
    • >>   __NVIC_GetPriorityGrouping +
    • >>   NVIC_EncodePriority +
    +
    [Called By]
    • >>   HAL_InitTick +
    • >>   HAL_FDCAN_MspInit +
    + +

    HAL_NVIC_SetPriorityGrouping (Thumb, 8 bytes, Stack size 8 bytes, stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_NVIC_SetPriorityGrouping +
    +
    [Calls]
    • >>   __NVIC_SetPriorityGrouping +
    +
    [Called By]
    • >>   HAL_Init +
    + +

    HAL_PWREx_ConfigSupply (Thumb, 72 bytes, Stack size 16 bytes, stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigSupply)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_PWREx_ConfigSupply +
    +
    [Calls]
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   SystemClock_Config +
    + +

    HAL_RCCEx_PeriphCLKConfig (Thumb, 2436 bytes, Stack size 32 bytes, stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = HAL_RCCEx_PeriphCLKConfig ⇒ RCCEx_PLL3_Config +
    +
    [Calls]
    • >>   RCCEx_PLL3_Config +
    • >>   RCCEx_PLL2_Config +
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   HAL_FDCAN_MspInit +
    + +

    HAL_RCC_ClockConfig (Thumb, 596 bytes, Stack size 32 bytes, stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = HAL_RCC_ClockConfig ⇒ HAL_InitTick ⇒ HAL_TIM_Base_Init ⇒ TIM_Base_SetConfig +
    +
    [Calls]
    • >>   HAL_RCC_GetSysClockFreq +
    • >>   HAL_GetTick +
    • >>   HAL_InitTick +
    +
    [Called By]
    • >>   SystemClock_Config +
    + +

    HAL_RCC_GetClockConfig (Thumb, 88 bytes, Stack size 0 bytes, stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig)) +

    [Called By]

    • >>   HAL_InitTick +
    + +

    HAL_RCC_GetHCLKFreq (Thumb, 76 bytes, Stack size 8 bytes, stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_RCC_GetHCLKFreq +
    +
    [Calls]
    • >>   HAL_RCC_GetSysClockFreq +
    +
    [Called By]
    • >>   HAL_RCC_GetPCLK1Freq +
    + +

    HAL_RCC_GetPCLK1Freq (Thumb, 38 bytes, Stack size 8 bytes, stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_RCC_GetPCLK1Freq ⇒ HAL_RCC_GetHCLKFreq +
    +
    [Calls]
    • >>   HAL_RCC_GetHCLKFreq +
    +
    [Called By]
    • >>   HAL_InitTick +
    + +

    HAL_RCC_GetSysClockFreq (Thumb, 264 bytes, Stack size 0 bytes, stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq)) +

    [Called By]

    • >>   HAL_RCC_GetHCLKFreq +
    • >>   HAL_RCC_ClockConfig +
    • >>   HAL_Init +
    + +

    HAL_RCC_OscConfig (Thumb, 1562 bytes, Stack size 32 bytes, stm32h7xx_hal_rcc.o(.text.HAL_RCC_OscConfig)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = HAL_RCC_OscConfig +
    +
    [Calls]
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   SystemClock_Config +
    + +

    HAL_TIMEx_Break2Callback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback)) +

    [Called By]

    • >>   HAL_TIM_IRQHandler +
    + +

    HAL_TIMEx_BreakCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback)) +

    [Called By]

    • >>   HAL_TIM_IRQHandler +
    + +

    HAL_TIMEx_CommutCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback)) +

    [Called By]

    • >>   HAL_TIM_IRQHandler +
    + +

    HAL_TIM_Base_Init (Thumb, 96 bytes, Stack size 8 bytes, stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Init)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_TIM_Base_Init ⇒ TIM_Base_SetConfig +
    +
    [Calls]
    • >>   TIM_Base_SetConfig +
    • >>   HAL_TIM_Base_MspInit +
    +
    [Called By]
    • >>   HAL_InitTick +
    + +

    HAL_TIM_Base_MspInit (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_MspInit)) +

    [Called By]

    • >>   HAL_TIM_Base_Init +
    + +

    HAL_TIM_Base_Start_IT (Thumb, 198 bytes, Stack size 0 bytes, stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT)) +

    [Called By]

    • >>   HAL_InitTick +
    + +

    HAL_TIM_IC_CaptureCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback)) +

    [Called By]

    • >>   HAL_TIM_IRQHandler +
    + +

    HAL_TIM_IRQHandler (Thumb, 346 bytes, Stack size 24 bytes, stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = HAL_TIM_IRQHandler ⇒ HAL_TIM_PeriodElapsedCallback +
    +
    [Calls]
    • >>   HAL_TIM_TriggerCallback +
    • >>   HAL_TIM_PWM_PulseFinishedCallback +
    • >>   HAL_TIM_OC_DelayElapsedCallback +
    • >>   HAL_TIM_IC_CaptureCallback +
    • >>   HAL_TIMEx_CommutCallback +
    • >>   HAL_TIMEx_BreakCallback +
    • >>   HAL_TIMEx_Break2Callback +
    • >>   HAL_TIM_PeriodElapsedCallback +
    +
    [Called By]
    • >>   TIM2_IRQHandler +
    + +

    HAL_TIM_OC_DelayElapsedCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback)) +

    [Called By]

    • >>   HAL_TIM_IRQHandler +
    + +

    HAL_TIM_PWM_PulseFinishedCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback)) +

    [Called By]

    • >>   HAL_TIM_IRQHandler +
    + +

    HAL_TIM_PeriodElapsedCallback (Thumb, 18 bytes, Stack size 8 bytes, main.o(.text.HAL_TIM_PeriodElapsedCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_TIM_PeriodElapsedCallback +
    +
    [Calls]
    • >>   HAL_IncTick +
    +
    [Called By]
    • >>   HAL_TIM_IRQHandler +
    + +

    HAL_TIM_TriggerCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_hal_tim.o(.text.HAL_TIM_TriggerCallback)) +

    [Called By]

    • >>   HAL_TIM_IRQHandler +
    + +

    HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_it.o(.text.HardFault_Handler)) +

    [Calls]

    • >>   HardFault_Handler +
    +
    [Called By]
    • >>   HardFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32h723xx.o(RESET) +
    +

    MX_FDCAN1_Init (Thumb, 108 bytes, Stack size 8 bytes, fdcan.o(.text.MX_FDCAN1_Init)) +

    [Stack]

    • Max Depth = 320 + Unknown Stack Size +
    • Call Chain = MX_FDCAN1_Init ⇒ HAL_FDCAN_Init ⇒ HAL_FDCAN_MspInit ⇒ HAL_RCCEx_PeriphCLKConfig ⇒ RCCEx_PLL3_Config +
    +
    [Calls]
    • >>   HAL_FDCAN_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   main +
    + +

    MX_GPIO_Init (Thumb, 50 bytes, Stack size 8 bytes, gpio.o(.text.MX_GPIO_Init)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = MX_GPIO_Init +
    +
    [Called By]
    • >>   main +
    + +

    MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_it.o(.text.MemManage_Handler)) +

    [Calls]

    • >>   MemManage_Handler +
    +
    [Called By]
    • >>   MemManage_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32h723xx.o(RESET) +
    +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_it.o(.text.NMI_Handler)) +

    [Calls]

    • >>   NMI_Handler +
    +
    [Called By]
    • >>   NMI_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32h723xx.o(RESET) +
    +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_it.o(.text.PendSV_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_it.o(.text.SVC_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_it.o(.text.SysTick_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(RESET) +
    +

    SystemClock_Config (Thumb, 166 bytes, Stack size 128 bytes, main.o(.text.SystemClock_Config)) +

    [Stack]

    • Max Depth = 232 + Unknown Stack Size +
    • Call Chain = SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_InitTick ⇒ HAL_TIM_Base_Init ⇒ TIM_Base_SetConfig +
    +
    [Calls]
    • >>   HAL_RCC_OscConfig +
    • >>   HAL_RCC_ClockConfig +
    • >>   HAL_PWREx_ConfigSupply +
    • >>   Error_Handler +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   main +
    + +

    SystemInit (Thumb, 210 bytes, Stack size 0 bytes, system_stm32h7xx.o(.text.SystemInit)) +
    [Address Reference Count : 1]

    • startup_stm32h723xx.o(.text) +
    +

    TIM2_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32h7xx_it.o(.text.TIM2_IRQHandler)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = TIM2_IRQHandler ⇒ HAL_TIM_IRQHandler ⇒ HAL_TIM_PeriodElapsedCallback +
    +
    [Calls]
    • >>   HAL_TIM_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32h723xx.o(RESET) +
    +

    TIM_Base_SetConfig (Thumb, 346 bytes, Stack size 8 bytes, stm32h7xx_hal_tim.o(.text.TIM_Base_SetConfig)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = TIM_Base_SetConfig +
    +
    [Called By]
    • >>   HAL_TIM_Base_Init +
    + +

    UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32h7xx_it.o(.text.UsageFault_Handler)) +

    [Calls]

    • >>   UsageFault_Handler +
    +
    [Called By]
    • >>   UsageFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32h723xx.o(RESET) +
    +

    main (Thumb, 18 bytes, Stack size 0 bytes, main.o(.text.main)) +

    [Stack]

    • Max Depth = 320 + Unknown Stack Size +
    • Call Chain = main ⇒ MX_FDCAN1_Init ⇒ HAL_FDCAN_Init ⇒ HAL_FDCAN_MspInit ⇒ HAL_RCCEx_PeriphCLKConfig ⇒ RCCEx_PLL3_Config +
    +
    [Calls]
    • >>   SystemClock_Config +
    • >>   MX_GPIO_Init +
    • >>   MX_FDCAN1_Init +
    • >>   HAL_Init +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    _fp_init (Thumb, 26 bytes, Stack size 0 bytes, fpinit.o(x$fpl$fpinit)) +

    [Called By]

    • >>   __rt_lib_init_fp_1 +
    + +

    __fplib_config_fpu_vfp (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED) + +

    __fplib_config_pureend_doubles (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED) +

    +

    +Local Symbols +

    +

    NVIC_EncodePriority (Thumb, 46 bytes, Stack size 0 bytes, stm32h7xx_hal_cortex.o(.text.NVIC_EncodePriority)) +

    [Called By]

    • >>   HAL_NVIC_SetPriority +
    + +

    __NVIC_EnableIRQ (Thumb, 32 bytes, Stack size 0 bytes, stm32h7xx_hal_cortex.o(.text.__NVIC_EnableIRQ)) +

    [Called By]

    • >>   HAL_NVIC_EnableIRQ +
    + +

    __NVIC_GetPriorityGrouping (Thumb, 16 bytes, Stack size 0 bytes, stm32h7xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping)) +

    [Called By]

    • >>   HAL_NVIC_SetPriority +
    + +

    __NVIC_SetPriority (Thumb, 34 bytes, Stack size 0 bytes, stm32h7xx_hal_cortex.o(.text.__NVIC_SetPriority)) +

    [Called By]

    • >>   HAL_NVIC_SetPriority +
    + +

    __NVIC_SetPriorityGrouping (Thumb, 32 bytes, Stack size 0 bytes, stm32h7xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping)) +

    [Called By]

    • >>   HAL_NVIC_SetPriorityGrouping +
    + +

    FDCAN_CalcultateRamBlockAddresses (Thumb, 456 bytes, Stack size 44 bytes, stm32h7xx_hal_fdcan.o(.text.FDCAN_CalcultateRamBlockAddresses)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = FDCAN_CalcultateRamBlockAddresses +
    +
    [Called By]
    • >>   HAL_FDCAN_Init +
    + +

    RCCEx_PLL2_Config (Thumb, 286 bytes, Stack size 24 bytes, stm32h7xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = RCCEx_PLL2_Config +
    +
    [Calls]
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   HAL_RCCEx_PeriphCLKConfig +
    + +

    RCCEx_PLL3_Config (Thumb, 286 bytes, Stack size 24 bytes, stm32h7xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = RCCEx_PLL3_Config +
    +
    [Calls]
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   HAL_RCCEx_PeriphCLKConfig +
    +

    +

    +Undefined Global Symbols +

    diff --git a/MDK-ARM/FDCAN/FDCAN.lnp b/MDK-ARM/FDCAN/FDCAN.lnp new file mode 100644 index 0000000..d2d0ee1 --- /dev/null +++ b/MDK-ARM/FDCAN/FDCAN.lnp @@ -0,0 +1,32 @@ +--cpu Cortex-M7.fp.dp +"fdcan\startup_stm32h723xx.o" +"fdcan\main.o" +"fdcan\gpio.o" +"fdcan\fdcan.o" +"fdcan\stm32h7xx_it.o" +"fdcan\stm32h7xx_hal_msp.o" +"fdcan\stm32h7xx_hal_timebase_tim.o" +"fdcan\stm32h7xx_hal_tim.o" +"fdcan\stm32h7xx_hal_tim_ex.o" +"fdcan\stm32h7xx_hal_cortex.o" +"fdcan\stm32h7xx_hal_fdcan.o" +"fdcan\stm32h7xx_hal_rcc.o" +"fdcan\stm32h7xx_hal_rcc_ex.o" +"fdcan\stm32h7xx_hal_flash.o" +"fdcan\stm32h7xx_hal_flash_ex.o" +"fdcan\stm32h7xx_hal_gpio.o" +"fdcan\stm32h7xx_hal_hsem.o" +"fdcan\stm32h7xx_hal_dma.o" +"fdcan\stm32h7xx_hal_dma_ex.o" +"fdcan\stm32h7xx_hal_mdma.o" +"fdcan\stm32h7xx_hal_pwr.o" +"fdcan\stm32h7xx_hal_pwr_ex.o" +"fdcan\stm32h7xx_hal.o" +"fdcan\stm32h7xx_hal_i2c.o" +"fdcan\stm32h7xx_hal_i2c_ex.o" +"fdcan\stm32h7xx_hal_exti.o" +"fdcan\system_stm32h7xx.o" +--strict --scatter "FDCAN\FDCAN.sct" +--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list "FDCAN.map" -o FDCAN\FDCAN.axf \ No newline at end of file diff --git a/MDK-ARM/FDCAN/FDCAN.map b/MDK-ARM/FDCAN/FDCAN.map new file mode 100644 index 0000000..7fa1c17 --- /dev/null +++ b/MDK-ARM/FDCAN/FDCAN.map @@ -0,0 +1,3725 @@ +Component: ARM Compiler 6.16 Tool: armlink [5dfeaa00] + +============================================================================== + +Section Cross References + + startup_stm32h723xx.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32h723xx.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32h723xx.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32h723xx.o(RESET) refers to startup_stm32h723xx.o(STACK) for __initial_sp + startup_stm32h723xx.o(RESET) refers to startup_stm32h723xx.o(.text) for Reset_Handler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.NMI_Handler) for NMI_Handler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.HardFault_Handler) for HardFault_Handler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.MemManage_Handler) for MemManage_Handler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.BusFault_Handler) for BusFault_Handler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.UsageFault_Handler) for UsageFault_Handler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.SVC_Handler) for SVC_Handler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.DebugMon_Handler) for DebugMon_Handler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.PendSV_Handler) for PendSV_Handler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.SysTick_Handler) for SysTick_Handler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.FDCAN1_IT0_IRQHandler) for FDCAN1_IT0_IRQHandler + startup_stm32h723xx.o(RESET) refers to stm32h7xx_it.o(.text.TIM2_IRQHandler) for TIM2_IRQHandler + startup_stm32h723xx.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32h723xx.o(.text) refers to system_stm32h7xx.o(.text.ExitRun0Mode) for ExitRun0Mode + startup_stm32h723xx.o(.text) refers to system_stm32h7xx.o(.text.SystemInit) for SystemInit + startup_stm32h723xx.o(.text) refers to __main.o(!!!main) for __main + startup_stm32h723xx.o(.text) refers to startup_stm32h723xx.o(HEAP) for Heap_Mem + startup_stm32h723xx.o(.text) refers to startup_stm32h723xx.o(STACK) for Stack_Mem + main.o(.text.main) refers to stm32h7xx_hal.o(.text.HAL_Init) for HAL_Init + main.o(.text.main) refers to main.o(.text.SystemClock_Config) for SystemClock_Config + main.o(.text.main) refers to gpio.o(.text.MX_GPIO_Init) for MX_GPIO_Init + main.o(.text.main) refers to fdcan.o(.text.MX_FDCAN1_Init) for MX_FDCAN1_Init + main.o(.ARM.exidx.text.main) refers to main.o(.text.main) for [Anonymous Symbol] + main.o(.text.SystemClock_Config) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + main.o(.text.SystemClock_Config) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigSupply) for HAL_PWREx_ConfigSupply + main.o(.text.SystemClock_Config) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_OscConfig) for HAL_RCC_OscConfig + main.o(.text.SystemClock_Config) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) for HAL_RCC_ClockConfig + main.o(.text.SystemClock_Config) refers to main.o(.text.Error_Handler) for Error_Handler + main.o(.ARM.exidx.text.SystemClock_Config) refers to main.o(.text.SystemClock_Config) for [Anonymous Symbol] + main.o(.ARM.exidx.text.Error_Handler) refers to main.o(.text.Error_Handler) for [Anonymous Symbol] + main.o(.text.HAL_TIM_PeriodElapsedCallback) refers to stm32h7xx_hal.o(.text.HAL_IncTick) for HAL_IncTick + main.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedCallback) refers to main.o(.text.HAL_TIM_PeriodElapsedCallback) for [Anonymous Symbol] + gpio.o(.ARM.exidx.text.MX_GPIO_Init) refers to gpio.o(.text.MX_GPIO_Init) for [Anonymous Symbol] + fdcan.o(.text.MX_FDCAN1_Init) refers to fdcan.o(.bss.hfdcan1) for hfdcan1 + fdcan.o(.text.MX_FDCAN1_Init) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Init) for HAL_FDCAN_Init + fdcan.o(.text.MX_FDCAN1_Init) refers to main.o(.text.Error_Handler) for Error_Handler + fdcan.o(.ARM.exidx.text.MX_FDCAN1_Init) refers to fdcan.o(.text.MX_FDCAN1_Init) for [Anonymous Symbol] + fdcan.o(.text.HAL_FDCAN_MspInit) refers to rt_memclr_w.o(.text) for __aeabi_memclr8 + fdcan.o(.text.HAL_FDCAN_MspInit) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) for HAL_RCCEx_PeriphCLKConfig + fdcan.o(.text.HAL_FDCAN_MspInit) refers to main.o(.text.Error_Handler) for Error_Handler + fdcan.o(.text.HAL_FDCAN_MspInit) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + fdcan.o(.text.HAL_FDCAN_MspInit) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + fdcan.o(.text.HAL_FDCAN_MspInit) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ + fdcan.o(.ARM.exidx.text.HAL_FDCAN_MspInit) refers to fdcan.o(.text.HAL_FDCAN_MspInit) for [Anonymous Symbol] + fdcan.o(.text.HAL_FDCAN_MspDeInit) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for HAL_GPIO_DeInit + fdcan.o(.text.HAL_FDCAN_MspDeInit) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) for HAL_NVIC_DisableIRQ + fdcan.o(.ARM.exidx.text.HAL_FDCAN_MspDeInit) refers to fdcan.o(.text.HAL_FDCAN_MspDeInit) for [Anonymous Symbol] + stm32h7xx_it.o(.ARM.exidx.text.NMI_Handler) refers to stm32h7xx_it.o(.text.NMI_Handler) for [Anonymous Symbol] + stm32h7xx_it.o(.ARM.exidx.text.HardFault_Handler) refers to stm32h7xx_it.o(.text.HardFault_Handler) for [Anonymous Symbol] + stm32h7xx_it.o(.ARM.exidx.text.MemManage_Handler) refers to stm32h7xx_it.o(.text.MemManage_Handler) for [Anonymous Symbol] + stm32h7xx_it.o(.ARM.exidx.text.BusFault_Handler) refers to stm32h7xx_it.o(.text.BusFault_Handler) for [Anonymous Symbol] + stm32h7xx_it.o(.ARM.exidx.text.UsageFault_Handler) refers to stm32h7xx_it.o(.text.UsageFault_Handler) for [Anonymous Symbol] + stm32h7xx_it.o(.ARM.exidx.text.SVC_Handler) refers to stm32h7xx_it.o(.text.SVC_Handler) for [Anonymous Symbol] + stm32h7xx_it.o(.ARM.exidx.text.DebugMon_Handler) refers to stm32h7xx_it.o(.text.DebugMon_Handler) for [Anonymous Symbol] + stm32h7xx_it.o(.ARM.exidx.text.PendSV_Handler) refers to stm32h7xx_it.o(.text.PendSV_Handler) for [Anonymous Symbol] + stm32h7xx_it.o(.ARM.exidx.text.SysTick_Handler) refers to stm32h7xx_it.o(.text.SysTick_Handler) for [Anonymous Symbol] + stm32h7xx_it.o(.text.FDCAN1_IT0_IRQHandler) refers to fdcan.o(.bss.hfdcan1) for hfdcan1 + stm32h7xx_it.o(.text.FDCAN1_IT0_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) for HAL_FDCAN_IRQHandler + stm32h7xx_it.o(.ARM.exidx.text.FDCAN1_IT0_IRQHandler) refers to stm32h7xx_it.o(.text.FDCAN1_IT0_IRQHandler) for [Anonymous Symbol] + stm32h7xx_it.o(.text.TIM2_IRQHandler) refers to stm32h7xx_hal_timebase_tim.o(.bss.htim2) for htim2 + stm32h7xx_it.o(.text.TIM2_IRQHandler) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) for HAL_TIM_IRQHandler + stm32h7xx_it.o(.ARM.exidx.text.TIM2_IRQHandler) refers to stm32h7xx_it.o(.text.TIM2_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_msp.o(.ARM.exidx.text.HAL_MspInit) refers to stm32h7xx_hal_msp.o(.text.HAL_MspInit) for [Anonymous Symbol] + stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ + stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h7xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig) for HAL_RCC_GetClockConfig + stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) for HAL_RCC_GetPCLK1Freq + stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h7xx_hal_timebase_tim.o(.bss.htim2) for htim2 + stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Init) for HAL_TIM_Base_Init + stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT) for HAL_TIM_Base_Start_IT + stm32h7xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_InitTick) refers to stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) for [Anonymous Symbol] + stm32h7xx_hal_timebase_tim.o(.text.HAL_SuspendTick) refers to stm32h7xx_hal_timebase_tim.o(.bss.htim2) for htim2 + stm32h7xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_SuspendTick) refers to stm32h7xx_hal_timebase_tim.o(.text.HAL_SuspendTick) for [Anonymous Symbol] + stm32h7xx_hal_timebase_tim.o(.text.HAL_ResumeTick) refers to stm32h7xx_hal_timebase_tim.o(.bss.htim2) for htim2 + stm32h7xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_ResumeTick) refers to stm32h7xx_hal_timebase_tim.o(.text.HAL_ResumeTick) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_MspInit) for HAL_TIM_Base_MspInit + stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Init) refers to stm32h7xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Init) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_MspInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_Base_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_Base_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_MspDeInit) for HAL_TIM_Base_MspDeInit + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_MspDeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Stop) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Stop_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for TIM_DMAPeriodElapsedCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for TIM_DMAPeriodElapsedHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) refers to main.o(.text.HAL_TIM_PeriodElapsedCallback) for HAL_TIM_PeriodElapsedCallback + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedCplt) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedHalfCpltCallback) for HAL_TIM_PeriodElapsedHalfCpltCallback + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedHalfCplt) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.TIM_DMAError) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_ErrorCallback) for HAL_TIM_ErrorCallback + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMAError) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAError) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Stop_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_DMA) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Stop_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_MspInit) for HAL_TIM_OC_MspInit + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Init) refers to stm32h7xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Init) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_MspInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_MspDeInit) for HAL_TIM_OC_MspDeInit + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspDeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_MspDeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_CCxChannelCmd) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Stop) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Stop) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Stop_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for TIM_DMADelayPulseCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for HAL_TIM_PWM_PulseFinishedCallback + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseCplt) refers to stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback) for HAL_TIM_PWM_PulseFinishedHalfCpltCallback + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseHalfCplt) refers to stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_DMA) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit) for HAL_TIM_PWM_MspInit + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Init) refers to stm32h7xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Init) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_MspDeInit) for HAL_TIM_PWM_MspDeInit + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspDeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_MspDeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Stop) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Stop) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for TIM_DMADelayPulseCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_DMA) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_MspInit) for HAL_TIM_IC_MspInit + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Init) refers to stm32h7xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Init) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_MspInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_MspDeInit) for HAL_TIM_IC_MspDeInit + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspDeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_MspDeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Stop) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Stop) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Stop_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.TIM_DMACaptureCplt) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for HAL_TIM_IC_CaptureCallback + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureCplt) refers to stm32h7xx_hal_tim.o(.text.TIM_DMACaptureCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_CaptureHalfCpltCallback) for HAL_TIM_IC_CaptureHalfCpltCallback + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureHalfCplt) refers to stm32h7xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_DMA) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspInit) for HAL_TIM_OnePulse_MspInit + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init) refers to stm32h7xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspDeInit) for HAL_TIM_OnePulse_MspDeInit + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspDeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspDeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_MspInit) for HAL_TIM_Encoder_MspInit + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Init) refers to stm32h7xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Init) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Init) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_MspInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_MspDeInit) for HAL_TIM_Encoder_MspDeInit + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_DeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspDeInit) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_MspDeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to main.o(.text.HAL_TIM_PeriodElapsedCallback) for HAL_TIM_PeriodElapsedCallback + stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback) for HAL_TIMEx_BreakCallback + stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for HAL_TIM_IC_CaptureCallback + stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback) for HAL_TIMEx_Break2Callback + stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) for HAL_TIM_TriggerCallback + stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) for HAL_TIMEx_CommutCallback + stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback) for HAL_TIM_OC_DelayElapsedCallback + stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for HAL_TIM_PWM_PulseFinishedCallback + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IRQHandler) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureCallback) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DelayElapsedCallback) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedCallback) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedCallback) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerCallback) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC1_SetConfig) for TIM_OC1_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC3_SetConfig) for TIM_OC3_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC4_SetConfig) for TIM_OC4_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC5_SetConfig) for TIM_OC5_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC6_SetConfig) for TIM_OC6_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC1_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_OC1_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC2_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_OC2_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC3_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_OC3_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC4_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_OC4_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC5_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_OC5_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC6_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_OC6_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_TI1_SetConfig) for TIM_TI1_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_TI2_SetConfig) for TIM_TI2_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_TI3_SetConfig) for TIM_TI3_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_TI4_SetConfig) for TIM_TI4_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_TI1_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_TI2_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI3_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_TI3_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI4_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_TI4_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC1_SetConfig) for TIM_OC1_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC3_SetConfig) for TIM_OC3_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC4_SetConfig) for TIM_OC4_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC5_SetConfig) for TIM_OC5_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC6_SetConfig) for TIM_OC6_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC1_SetConfig) for TIM_OC1_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_TI1_SetConfig) for TIM_TI1_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.TIM_TI2_SetConfig) for TIM_TI2_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStart) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) for HAL_TIM_DMABurst_MultiWriteStart + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStart) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStart) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for TIM_DMADelayPulseCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMATriggerCplt) for TIM_DMATriggerCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) for TIM_DMATriggerHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for TIM_DMAPeriodElapsedCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for TIM_DMAPeriodElapsedHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for TIMEx_DMACommutationCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for TIMEx_DMACommutationHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.TIM_DMATriggerCplt) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) for HAL_TIM_TriggerCallback + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerCplt) refers to stm32h7xx_hal_tim.o(.text.TIM_DMATriggerCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_TriggerHalfCpltCallback) for HAL_TIM_TriggerHalfCpltCallback + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerHalfCplt) refers to stm32h7xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStop) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStop) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStop) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStart) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) for HAL_TIM_DMABurst_MultiReadStart + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStart) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStart) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMATriggerCplt) for TIM_DMATriggerCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) for TIM_DMATriggerHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for TIM_DMAPeriodElapsedCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for TIM_DMAPeriodElapsedHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for TIMEx_DMACommutationCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for TIMEx_DMACommutationHalfCplt + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStop) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStop) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStop) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GenerateEvent) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_GenerateEvent) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigOCrefClear) refers to stm32h7xx_hal_tim.o(.text.TIM_ETR_SetConfig) for TIM_ETR_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigOCrefClear) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigOCrefClear) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_ETR_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_ETR_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32h7xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage) for TIM_TI1_ConfigInputStage + stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32h7xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage) for TIM_TI2_ConfigInputStage + stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32h7xx_hal_tim.o(.text.TIM_ETR_SetConfig) for TIM_ETR_SetConfig + stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32h7xx_hal_tim.o(.text.TIM_ITRx_SetConfig) for TIM_ITRx_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigClockSource) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_ConfigInputStage) refers to stm32h7xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_ITRx_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_ITRx_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_ConfigInputStage) refers to stm32h7xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigTI1Input) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigTI1Input) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro) refers to stm32h7xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) for TIM_SlaveTimer_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage) for TIM_TI1_ConfigInputStage + stm32h7xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage) for TIM_TI2_ConfigInputStage + stm32h7xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_ETR_SetConfig) for TIM_ETR_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_SlaveTimer_SetConfig) refers to stm32h7xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) for TIM_SlaveTimer_SetConfig + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro_IT) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ReadCapturedValue) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_ReadCapturedValue) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedHalfCpltCallback) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedHalfCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureHalfCpltCallback) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_CaptureHalfCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerHalfCpltCallback) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_TriggerHalfCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ErrorCallback) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_ErrorCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_GetState) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_GetState) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_GetState) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_GetState) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_GetState) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_GetState) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_GetState) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_GetState) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_GetState) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_GetState) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_GetState) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_GetState) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetActiveChannel) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_GetActiveChannel) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetChannelState) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_GetChannelState) for [Anonymous Symbol] + stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurstState) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurstState) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspInit) for HAL_TIMEx_HallSensor_MspInit + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32h7xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32h7xx_hal_tim.o(.text.TIM_TI1_SetConfig) for TIM_TI1_SetConfig + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32h7xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Init) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspInit) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspInit) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_DeInit) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspDeInit) for HAL_TIMEx_HallSensor_MspDeInit + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_DeInit) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspDeInit) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspDeInit) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_IT) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_IT) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.TIM_CCxNChannelCmd) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_IT) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_IT) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_IT) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_IT) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) for TIM_DMADelayPulseNCplt + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) for TIM_DMAErrorCCxN + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for HAL_TIM_PWM_PulseFinishedCallback + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMADelayPulseNCplt) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) refers to stm32h7xx_hal_tim.o(.text.HAL_TIM_ErrorCallback) for HAL_TIM_ErrorCallback + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMAErrorCCxN) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_IT) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_IT) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_IT) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_IT) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) for TIM_DMADelayPulseNCplt + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) for TIM_DMAErrorCCxN + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start_IT) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT) refers to stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT) refers to stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop_IT) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_IT) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_IT) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for TIMEx_DMACommutationCplt + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for TIMEx_DMACommutationHalfCplt + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32h7xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) for HAL_TIMEx_CommutCallback + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationCplt) refers to stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutHalfCpltCallback) for HAL_TIMEx_CommutHalfCpltCallback + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationHalfCplt) refers to stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_MasterConfigSynchronization) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_MasterConfigSynchronization) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakDeadTime) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakDeadTime) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakInput) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakInput) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_RemapConfig) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_RemapConfig) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_TISelection) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_TISelection) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_GroupChannel5) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_GroupChannel5) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisarmBreakInput) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_DisarmBreakInput) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ReArmBreakInput) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ReArmBreakInput) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ReArmBreakInput) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutCallback) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutHalfCpltCallback) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutHalfCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_BreakCallback) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_Break2Callback) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_GetState) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_GetState) for [Anonymous Symbol] + stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_GetChannelNState) refers to stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_GetChannelNState) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping) for __NVIC_SetPriorityGrouping + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriorityGrouping) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriorityGrouping) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) for __NVIC_GetPriorityGrouping + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) refers to stm32h7xx_hal_cortex.o(.text.NVIC_EncodePriority) for NVIC_EncodePriority + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_SetPriority) for __NVIC_SetPriority + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriority) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriorityGrouping) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriority) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_SetPriority) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.NVIC_EncodePriority) refers to stm32h7xx_hal_cortex.o(.text.NVIC_EncodePriority) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_EnableIRQ) for __NVIC_EnableIRQ + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_EnableIRQ) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_EnableIRQ) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_EnableIRQ) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_DisableIRQ) for __NVIC_DisableIRQ + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_DisableIRQ) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_DisableIRQ) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_DisableIRQ) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SystemReset) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_SystemReset) for __NVIC_SystemReset + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SystemReset) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SystemReset) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SystemReset) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_SystemReset) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_Config) refers to stm32h7xx_hal_cortex.o(.text.SysTick_Config) for SysTick_Config + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Config) refers to stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_Config) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.SysTick_Config) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_SetPriority) for __NVIC_SetPriority + stm32h7xx_hal_cortex.o(.ARM.exidx.text.SysTick_Config) refers to stm32h7xx_hal_cortex.o(.text.SysTick_Config) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Disable) refers to stm32h7xx_hal_cortex.o(.text.HAL_MPU_Disable) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Enable) refers to stm32h7xx_hal_cortex.o(.text.HAL_MPU_Enable) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_EnableRegion) refers to stm32h7xx_hal_cortex.o(.text.HAL_MPU_EnableRegion) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_DisableRegion) refers to stm32h7xx_hal_cortex.o(.text.HAL_MPU_DisableRegion) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_ConfigRegion) refers to stm32h7xx_hal_cortex.o(.text.HAL_MPU_ConfigRegion) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetPriorityGrouping) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) for __NVIC_GetPriorityGrouping + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriorityGrouping) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetPriorityGrouping) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetPriority) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_GetPriority) for __NVIC_GetPriority + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetPriority) refers to stm32h7xx_hal_cortex.o(.text.NVIC_DecodePriority) for NVIC_DecodePriority + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriority) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetPriority) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.NVIC_DecodePriority) refers to stm32h7xx_hal_cortex.o(.text.NVIC_DecodePriority) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriority) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_GetPriority) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPendingIRQ) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_SetPendingIRQ) for __NVIC_SetPendingIRQ + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPendingIRQ) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPendingIRQ) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPendingIRQ) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_SetPendingIRQ) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetPendingIRQ) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_GetPendingIRQ) for __NVIC_GetPendingIRQ + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPendingIRQ) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetPendingIRQ) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPendingIRQ) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_GetPendingIRQ) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_ClearPendingIRQ) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_ClearPendingIRQ) for __NVIC_ClearPendingIRQ + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_ClearPendingIRQ) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_ClearPendingIRQ) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_ClearPendingIRQ) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_ClearPendingIRQ) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetActive) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_GetActive) for __NVIC_GetActive + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetActive) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetActive) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetActive) refers to stm32h7xx_hal_cortex.o(.text.__NVIC_GetActive) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_CLKSourceConfig) refers to stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_IRQHandler) refers to stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_Callback) for HAL_SYSTICK_Callback + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_IRQHandler) refers to stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Callback) refers to stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_Callback) for [Anonymous Symbol] + stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_GetCurrentCPUID) refers to stm32h7xx_hal_cortex.o(.text.HAL_GetCurrentCPUID) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Init) refers to fdcan.o(.text.HAL_FDCAN_MspInit) for HAL_FDCAN_MspInit + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Init) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Init) refers to stm32h7xx_hal_fdcan.o(.rodata..L__const.HAL_FDCAN_Init.CvtEltSize) for .L__const.HAL_FDCAN_Init.CvtEltSize + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Init) refers to stm32h7xx_hal_fdcan.o(.text.FDCAN_CalcultateRamBlockAddresses) for FDCAN_CalcultateRamBlockAddresses + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_Init) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Init) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_MspInit) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_MspInit) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.FDCAN_CalcultateRamBlockAddresses) refers to stm32h7xx_hal_fdcan.o(.text.FDCAN_CalcultateRamBlockAddresses) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DeInit) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Stop) for HAL_FDCAN_Stop + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DeInit) refers to fdcan.o(.text.HAL_FDCAN_MspDeInit) for HAL_FDCAN_MspDeInit + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DeInit) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_Stop) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Stop) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_MspDeInit) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_MspDeInit) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnterPowerDownMode) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnterPowerDownMode) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnterPowerDownMode) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ExitPowerDownMode) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ExitPowerDownMode) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ExitPowerDownMode) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigClockCalibration) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigClockCalibration) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetClockCalibrationState) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetClockCalibrationState) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ResetClockCalibrationState) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ResetClockCalibrationState) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetClockCalibrationCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetClockCalibrationCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigFilter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigFilter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigGlobalFilter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigGlobalFilter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigExtendedIdMask) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigExtendedIdMask) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigRxFifoOverwrite) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigRxFifoOverwrite) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigFifoWatermark) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigFifoWatermark) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigRamWatchdog) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigRamWatchdog) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigTimestampCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigTimestampCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableTimestampCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableTimestampCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DisableTimestampCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DisableTimestampCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetTimestampCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetTimestampCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ResetTimestampCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ResetTimestampCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigTimeoutCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigTimeoutCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableTimeoutCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableTimeoutCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DisableTimeoutCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DisableTimeoutCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetTimeoutCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetTimeoutCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ResetTimeoutCounter) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ResetTimeoutCounter) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigTxDelayCompensation) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigTxDelayCompensation) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableTxDelayCompensation) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableTxDelayCompensation) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DisableTxDelayCompensation) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DisableTxDelayCompensation) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableISOMode) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableISOMode) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DisableISOMode) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DisableISOMode) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableEdgeFiltering) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableEdgeFiltering) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DisableEdgeFiltering) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DisableEdgeFiltering) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_Start) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Start) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_AddMessageToTxFifoQ) refers to stm32h7xx_hal_fdcan.o(.text.FDCAN_CopyMessageToRAM) for FDCAN_CopyMessageToRAM + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_AddMessageToTxFifoQ) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_AddMessageToTxFifoQ) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.text.FDCAN_CopyMessageToRAM) refers to stm32h7xx_hal_fdcan.o(.rodata.cst16) for DLCtoBytes + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.FDCAN_CopyMessageToRAM) refers to stm32h7xx_hal_fdcan.o(.text.FDCAN_CopyMessageToRAM) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_AddMessageToTxBuffer) refers to stm32h7xx_hal_fdcan.o(.text.FDCAN_CopyMessageToRAM) for FDCAN_CopyMessageToRAM + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_AddMessageToTxBuffer) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_AddMessageToTxBuffer) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableTxBufferRequest) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableTxBufferRequest) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetLatestTxFifoQRequestBuffer) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetLatestTxFifoQRequestBuffer) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_AbortTxRequest) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_AbortTxRequest) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetRxMessage) refers to stm32h7xx_hal_fdcan.o(.rodata.cst16) for DLCtoBytes + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetRxMessage) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetRxMessage) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetTxEvent) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetTxEvent) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetHighPriorityMessageStatus) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetHighPriorityMessageStatus) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetProtocolStatus) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetProtocolStatus) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetErrorCounters) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetErrorCounters) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_IsRxBufferMessageAvailable) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IsRxBufferMessageAvailable) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_IsTxBufferMessagePending) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IsTxBufferMessagePending) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetRxFifoFillLevel) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetRxFifoFillLevel) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetTxFifoFreeLevel) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetTxFifoFreeLevel) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_IsRestrictedOperationMode) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IsRestrictedOperationMode) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ExitRestrictedOperationMode) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ExitRestrictedOperationMode) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigOperation) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigOperation) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigOperation) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigReferenceMessage) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigReferenceMessage) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigTrigger) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigTrigger) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_SetGlobalTime) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_SetGlobalTime) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_SetClockSynchronization) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_SetClockSynchronization) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigStopWatch) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigStopWatch) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigRegisterTimeMark) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigRegisterTimeMark) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_EnableRegisterTimeMarkPulse) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_EnableRegisterTimeMarkPulse) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DisableRegisterTimeMarkPulse) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DisableRegisterTimeMarkPulse) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_EnableTriggerTimeMarkPulse) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_EnableTriggerTimeMarkPulse) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DisableTriggerTimeMarkPulse) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DisableTriggerTimeMarkPulse) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_EnableHardwareGapControl) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_EnableHardwareGapControl) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DisableHardwareGapControl) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DisableHardwareGapControl) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_EnableTimeMarkGapControl) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_EnableTimeMarkGapControl) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DisableTimeMarkGapControl) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DisableTimeMarkGapControl) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_SetNextIsGap) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_SetNextIsGap) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_SetEndOfGap) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_SetEndOfGap) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigExternalSyncPhase) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigExternalSyncPhase) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_EnableExternalSynchronization) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_EnableExternalSynchronization) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DisableExternalSynchronization) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DisableExternalSynchronization) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_GetOperationStatus) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_GetOperationStatus) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigInterruptLines) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigInterruptLines) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigInterruptLines) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigInterruptLines) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ActivateNotification) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ActivateNotification) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DeactivateNotification) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DeactivateNotification) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ActivateNotification) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ActivateNotification) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DeactivateNotification) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DeactivateNotification) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_HighPriorityMessageCallback) for HAL_FDCAN_HighPriorityMessageCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxBufferAbortCallback) for HAL_FDCAN_TxBufferAbortCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ClockCalibrationCallback) for HAL_FDCAN_ClockCalibrationCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxEventFifoCallback) for HAL_FDCAN_TxEventFifoCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxFifo0Callback) for HAL_FDCAN_RxFifo0Callback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxFifo1Callback) for HAL_FDCAN_RxFifo1Callback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TimestampWraparoundCallback) for HAL_FDCAN_TimestampWraparoundCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TimeoutOccurredCallback) for HAL_FDCAN_TimeoutOccurredCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ErrorStatusCallback) for HAL_FDCAN_ErrorStatusCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ScheduleSyncCallback) for HAL_FDCAN_TT_ScheduleSyncCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_TimeMarkCallback) for HAL_FDCAN_TT_TimeMarkCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_StopWatchCallback) for HAL_FDCAN_TT_StopWatchCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_GlobalTimeCallback) for HAL_FDCAN_TT_GlobalTimeCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ErrorCallback) for HAL_FDCAN_ErrorCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxFifoEmptyCallback) for HAL_FDCAN_TxFifoEmptyCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxBufferCompleteCallback) for HAL_FDCAN_TxBufferCompleteCallback + stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxBufferNewMessageCallback) for HAL_FDCAN_RxBufferNewMessageCallback + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_IRQHandler) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_HighPriorityMessageCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_HighPriorityMessageCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TxBufferAbortCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxBufferAbortCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ClockCalibrationCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ClockCalibrationCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TxEventFifoCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxEventFifoCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_RxFifo0Callback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxFifo0Callback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_RxFifo1Callback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxFifo1Callback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TxFifoEmptyCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxFifoEmptyCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TxBufferCompleteCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxBufferCompleteCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_RxBufferNewMessageCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxBufferNewMessageCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TimestampWraparoundCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TimestampWraparoundCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TimeoutOccurredCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TimeoutOccurredCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ErrorStatusCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ErrorStatusCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ScheduleSyncCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ScheduleSyncCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_TimeMarkCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_TimeMarkCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_StopWatchCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_StopWatchCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_GlobalTimeCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_GlobalTimeCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ErrorCallback) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ErrorCallback) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetState) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetState) for [Anonymous Symbol] + stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetError) refers to stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetError) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to system_stm32h7xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h7xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to stm32h7xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h7xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to system_stm32h7xx.o(.data.SystemD2Clock) for SystemD2Clock + stm32h7xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) for HAL_InitTick + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DeInit) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.text.HAL_RCC_OscConfig) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_OscConfig) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_OscConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for HAL_RCC_GetSysClockFreq + stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to system_stm32h7xx.o(.rodata.D1CorePrescTable) for D1CorePrescTable + stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to system_stm32h7xx.o(.data.SystemD2Clock) for SystemD2Clock + stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to system_stm32h7xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32h7xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) for HAL_InitTick + stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_ClockConfig) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetSysClockFreq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.text.HAL_RCC_MCOConfig) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_MCOConfig) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_MCOConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_EnableCSS) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_EnableCSS) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DisableCSS) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_DisableCSS) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for HAL_RCC_GetSysClockFreq + stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) refers to system_stm32h7xx.o(.rodata.D1CorePrescTable) for D1CorePrescTable + stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) refers to system_stm32h7xx.o(.data.SystemD2Clock) for SystemD2Clock + stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) refers to system_stm32h7xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetHCLKFreq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) refers to system_stm32h7xx.o(.rodata.D1CorePrescTable) for D1CorePrescTable + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK1Freq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) refers to system_stm32h7xx.o(.rodata.D1CorePrescTable) for D1CorePrescTable + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK2Freq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetOscConfig) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetOscConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetClockConfig) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.text.HAL_RCC_NMI_IRQHandler) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_CSSCallback) for HAL_RCC_CSSCallback + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_NMI_IRQHandler) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_NMI_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_CSSCallback) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_CSSCallback) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) refers to stm32h7xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config) for RCCEx_PLL2_Config + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) refers to stm32h7xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config) for RCCEx_PLL3_Config + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_PeriphCLKConfig) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.RCCEx_PLL2_Config) refers to stm32h7xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.RCCEx_PLL3_Config) refers to stm32h7xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKConfig) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD3PCLK1Freq) for HAL_RCCEx_GetD3PCLK1Freq + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) for HAL_RCC_GetPCLK1Freq + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL2ClockFreq) for HAL_RCCEx_GetPLL2ClockFreq + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL3ClockFreq) for HAL_RCCEx_GetPLL3ClockFreq + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL1ClockFreq) for HAL_RCCEx_GetPLL1ClockFreq + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL1ClockFreq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL1ClockFreq) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL2ClockFreq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL2ClockFreq) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL3ClockFreq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL3ClockFreq) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD3PCLK1Freq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD3PCLK1Freq) refers to system_stm32h7xx.o(.rodata.D1CorePrescTable) for D1CorePrescTable + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetD3PCLK1Freq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD3PCLK1Freq) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD1PCLK1Freq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD1PCLK1Freq) refers to system_stm32h7xx.o(.rodata.D1CorePrescTable) for D1CorePrescTable + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetD1PCLK1Freq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD1PCLK1Freq) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD1SysClockFreq) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for HAL_RCC_GetSysClockFreq + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD1SysClockFreq) refers to system_stm32h7xx.o(.rodata.D1CorePrescTable) for D1CorePrescTable + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD1SysClockFreq) refers to system_stm32h7xx.o(.data.SystemD2Clock) for SystemD2Clock + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD1SysClockFreq) refers to system_stm32h7xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetD1SysClockFreq) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD1SysClockFreq) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnableLSECSS) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnableLSECSS) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisableLSECSS) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisableLSECSS) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnableLSECSS_IT) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnableLSECSS_IT) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_WakeUpStopCLKConfig) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_WakeUpStopCLKConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_KerWakeUpStopCLKConfig) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_KerWakeUpStopCLKConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_WWDGxSysResetConfig) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_WWDGxSysResetConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSConfig) refers to stm32h7xx_hal.o(.text.HAL_GetREVID) for HAL_GetREVID + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSConfig) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSConfig) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSGetSynchronizationInfo) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSGetSynchronizationInfo) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSWaitSynchronization) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSWaitSynchronization) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSWaitSynchronization) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ErrorCallback) for HAL_RCCEx_CRS_ErrorCallback + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncOkCallback) for HAL_RCCEx_CRS_SyncOkCallback + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncWarnCallback) for HAL_RCCEx_CRS_SyncWarnCallback + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ExpectedSyncCallback) for HAL_RCCEx_CRS_ExpectedSyncCallback + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_IRQHandler) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_SyncOkCallback) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncOkCallback) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_SyncWarnCallback) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncWarnCallback) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_ExpectedSyncCallback) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ExpectedSyncCallback) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_ErrorCallback) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ErrorCallback) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_IRQHandler) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_Callback) for HAL_RCCEx_LSECSS_Callback + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_LSECSS_IRQHandler) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_LSECSS_Callback) refers to stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_Callback) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32h7xx_hal_flash.o(.bss.pFlash) for pFlash + stm32h7xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32h7xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_Program) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.text.FLASH_WaitForLastOperation) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_flash.o(.text.FLASH_WaitForLastOperation) refers to stm32h7xx_hal_flash.o(.bss.pFlash) for pFlash + stm32h7xx_hal_flash.o(.ARM.exidx.text.FLASH_WaitForLastOperation) refers to stm32h7xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32h7xx_hal_flash.o(.bss.pFlash) for pFlash + stm32h7xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32h7xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program_IT) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_Program_IT) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32h7xx_hal_flash.o(.bss.pFlash) for pFlash + stm32h7xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_EndOfOperationCallback) for HAL_FLASH_EndOfOperationCallback + stm32h7xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for FLASH_Erase_Sector + stm32h7xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_OperationErrorCallback) for HAL_FLASH_OperationErrorCallback + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_IRQHandler) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_EndOfOperationCallback) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_EndOfOperationCallback) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OperationErrorCallback) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_OperationErrorCallback) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Unlock) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_Unlock) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Lock) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_Lock) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Unlock) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_OB_Unlock) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Lock) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_OB_Lock) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.text.HAL_FLASH_OB_Launch) refers to stm32h7xx_hal_flash.o(.text.FLASH_CRC_WaitForLastOperation) for FLASH_CRC_WaitForLastOperation + stm32h7xx_hal_flash.o(.text.HAL_FLASH_OB_Launch) refers to stm32h7xx_hal_flash.o(.text.FLASH_OB_WaitForLastOperation) for FLASH_OB_WaitForLastOperation + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Launch) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_OB_Launch) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.text.FLASH_CRC_WaitForLastOperation) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_flash.o(.text.FLASH_CRC_WaitForLastOperation) refers to stm32h7xx_hal_flash.o(.bss.pFlash) for pFlash + stm32h7xx_hal_flash.o(.ARM.exidx.text.FLASH_CRC_WaitForLastOperation) refers to stm32h7xx_hal_flash.o(.text.FLASH_CRC_WaitForLastOperation) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.text.FLASH_OB_WaitForLastOperation) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_flash.o(.text.FLASH_OB_WaitForLastOperation) refers to stm32h7xx_hal_flash.o(.bss.pFlash) for pFlash + stm32h7xx_hal_flash.o(.ARM.exidx.text.FLASH_OB_WaitForLastOperation) refers to stm32h7xx_hal_flash.o(.text.FLASH_OB_WaitForLastOperation) for [Anonymous Symbol] + stm32h7xx_hal_flash.o(.text.HAL_FLASH_GetError) refers to stm32h7xx_hal_flash.o(.bss.pFlash) for pFlash + stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_GetError) refers to stm32h7xx_hal_flash.o(.text.HAL_FLASH_GetError) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32h7xx_hal_flash.o(.bss.pFlash) for pFlash + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32h7xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_MassErase) for FLASH_MassErase + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for FLASH_Erase_Sector + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase) refers to stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_MassErase) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_MassErase) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_Erase_Sector) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32h7xx_hal_flash.o(.bss.pFlash) for pFlash + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32h7xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_MassErase) for FLASH_MassErase + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for FLASH_Erase_Sector + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase_IT) refers to stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash.o(.bss.pFlash) for pFlash + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_EnableWRP) for FLASH_OB_EnableWRP + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_DisableWRP) for FLASH_OB_DisableWRP + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_RDPConfig) for FLASH_OB_RDPConfig + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_UserConfig) for FLASH_OB_UserConfig + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_PCROPConfig) for FLASH_OB_PCROPConfig + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_BOR_LevelConfig) for FLASH_OB_BOR_LevelConfig + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_BootAddConfig) for FLASH_OB_BootAddConfig + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_SecureAreaConfig) for FLASH_OB_SecureAreaConfig + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_SharedRAM_Config) for FLASH_OB_SharedRAM_Config + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_CPUFreq_BoostConfig) for FLASH_OB_CPUFreq_BoostConfig + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBProgram) refers to stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_EnableWRP) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_EnableWRP) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_DisableWRP) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_DisableWRP) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_RDPConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_RDPConfig) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_UserConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_UserConfig) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_PCROPConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_PCROPConfig) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_BOR_LevelConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_BOR_LevelConfig) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_BootAddConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_BootAddConfig) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_SecureAreaConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_SecureAreaConfig) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_SharedRAM_Config) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_SharedRAM_Config) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_CPUFreq_BoostConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_CPUFreq_BoostConfig) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetRDP) for FLASH_OB_GetRDP + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetUser) for FLASH_OB_GetUser + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetBOR) for FLASH_OB_GetBOR + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetWRP) for FLASH_OB_GetWRP + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetPCROP) for FLASH_OB_GetPCROP + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetSecureArea) for FLASH_OB_GetSecureArea + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetBootAdd) for FLASH_OB_GetBootAdd + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_SharedRAM_GetConfig) for FLASH_OB_SharedRAM_GetConfig + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_CPUFreq_GetBoost) for FLASH_OB_CPUFreq_GetBoost + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBGetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetRDP) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetRDP) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetUser) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetUser) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetBOR) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetBOR) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetWRP) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetWRP) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetPCROP) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetPCROP) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetSecureArea) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetSecureArea) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetBootAdd) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetBootAdd) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_SharedRAM_GetConfig) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_SharedRAM_GetConfig) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_CPUFreq_GetBoost) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_CPUFreq_GetBoost) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Unlock_Bank1) refers to stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Unlock_Bank1) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Lock_Bank1) refers to stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Lock_Bank1) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_ComputeCRC) refers to stm32h7xx_hal_flash.o(.text.FLASH_OB_WaitForLastOperation) for FLASH_OB_WaitForLastOperation + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_ComputeCRC) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_CRC_AddSector) for FLASH_CRC_AddSector + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_ComputeCRC) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_CRC_SelectAddress) for FLASH_CRC_SelectAddress + stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_ComputeCRC) refers to stm32h7xx_hal_flash.o(.text.FLASH_CRC_WaitForLastOperation) for FLASH_CRC_WaitForLastOperation + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_ComputeCRC) refers to stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_ComputeCRC) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_CRC_AddSector) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_CRC_AddSector) for [Anonymous Symbol] + stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_CRC_SelectAddress) refers to stm32h7xx_hal_flash_ex.o(.text.FLASH_CRC_SelectAddress) for [Anonymous Symbol] + stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_Init) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_Init) for [Anonymous Symbol] + stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_DeInit) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_ReadPin) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_ReadPin) for [Anonymous Symbol] + stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_WritePin) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for [Anonymous Symbol] + stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_TogglePin) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_TogglePin) for [Anonymous Symbol] + stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_LockPin) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_LockPin) for [Anonymous Symbol] + stm32h7xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Callback) for HAL_GPIO_EXTI_Callback + stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_IRQHandler) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Callback) refers to stm32h7xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Callback) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_Take) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_Take) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_FastTake) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_FastTake) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_IsSemTaken) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_IsSemTaken) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_Release) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_Release) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_ReleaseAll) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_ReleaseAll) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_SetClearKey) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_SetClearKey) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_GetClearKey) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_GetClearKey) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_ActivateNotification) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_ActivateNotification) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_DeactivateNotification) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_DeactivateNotification) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.text.HAL_HSEM_IRQHandler) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_FreeCallback) for HAL_HSEM_FreeCallback + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_IRQHandler) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_FreeCallback) refers to stm32h7xx_hal_hsem.o(.text.HAL_HSEM_FreeCallback) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h7xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift) for DMA_CalcBaseAndBitshift + stm32h7xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h7xx_hal_dma.o(.text.DMA_CheckFifoParam) for DMA_CheckFifoParam + stm32h7xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h7xx_hal_dma.o(.text.DMA_CalcDMAMUXChannelBaseAndMask) for DMA_CalcDMAMUXChannelBaseAndMask + stm32h7xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h7xx_hal_dma.o(.text.DMA_CalcDMAMUXRequestGenBaseAndMask) for DMA_CalcDMAMUXRequestGenBaseAndMask + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Init) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Init) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.ARM.exidx.text.DMA_CheckFifoParam) refers to stm32h7xx_hal_dma.o(.text.DMA_CheckFifoParam) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.ARM.exidx.text.DMA_CalcBaseAndBitshift) refers to stm32h7xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.ARM.exidx.text.DMA_CalcDMAMUXChannelBaseAndMask) refers to stm32h7xx_hal_dma.o(.text.DMA_CalcDMAMUXChannelBaseAndMask) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.ARM.exidx.text.DMA_CalcDMAMUXRequestGenBaseAndMask) refers to stm32h7xx_hal_dma.o(.text.DMA_CalcDMAMUXRequestGenBaseAndMask) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.text.HAL_DMA_DeInit) refers to stm32h7xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift) for DMA_CalcBaseAndBitshift + stm32h7xx_hal_dma.o(.text.HAL_DMA_DeInit) refers to stm32h7xx_hal_dma.o(.text.DMA_CalcDMAMUXChannelBaseAndMask) for DMA_CalcDMAMUXChannelBaseAndMask + stm32h7xx_hal_dma.o(.text.HAL_DMA_DeInit) refers to stm32h7xx_hal_dma.o(.text.DMA_CalcDMAMUXRequestGenBaseAndMask) for DMA_CalcDMAMUXRequestGenBaseAndMask + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_DeInit) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.text.HAL_DMA_Start) refers to stm32h7xx_hal_dma.o(.text.DMA_SetConfig) for DMA_SetConfig + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.ARM.exidx.text.DMA_SetConfig) refers to stm32h7xx_hal_dma.o(.text.DMA_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) refers to stm32h7xx_hal_dma.o(.text.DMA_SetConfig) for DMA_SetConfig + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start_IT) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort_IT) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_PollForTransfer) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.text.HAL_DMA_IRQHandler) refers to system_stm32h7xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_IRQHandler) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_RegisterCallback) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_RegisterCallback) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_UnRegisterCallback) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_UnRegisterCallback) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetState) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_GetState) for [Anonymous Symbol] + stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetError) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_GetError) for [Anonymous Symbol] + stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart) refers to stm32h7xx_hal_dma_ex.o(.text.DMA_MultiBufferSetConfig) for DMA_MultiBufferSetConfig + stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_MultiBufferStart) refers to stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart) for [Anonymous Symbol] + stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.DMA_MultiBufferSetConfig) refers to stm32h7xx_hal_dma_ex.o(.text.DMA_MultiBufferSetConfig) for [Anonymous Symbol] + stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart_IT) refers to stm32h7xx_hal_dma_ex.o(.text.DMA_MultiBufferSetConfig) for DMA_MultiBufferSetConfig + stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_MultiBufferStart_IT) refers to stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart_IT) for [Anonymous Symbol] + stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ChangeMemory) refers to stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_ChangeMemory) for [Anonymous Symbol] + stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigMuxSync) refers to stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigMuxSync) for [Anonymous Symbol] + stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigMuxRequestGenerator) refers to stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigMuxRequestGenerator) for [Anonymous Symbol] + stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_EnableMuxRequestGenerator) refers to stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_EnableMuxRequestGenerator) for [Anonymous Symbol] + stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_DisableMuxRequestGenerator) refers to stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_DisableMuxRequestGenerator) for [Anonymous Symbol] + stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_MUX_IRQHandler) refers to stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_MUX_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Init) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Init) refers to stm32h7xx_hal_mdma.o(.text.MDMA_Init) for MDMA_Init + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_Init) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Init) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.MDMA_Init) refers to stm32h7xx_hal_mdma.o(.text.MDMA_Init) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_DeInit) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_ConfigPostRequestMask) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_ConfigPostRequestMask) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_RegisterCallback) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_RegisterCallback) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_UnRegisterCallback) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_UnRegisterCallback) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_LinkedList_CreateNode) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_LinkedList_CreateNode) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_LinkedList_AddNode) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_LinkedList_AddNode) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_LinkedList_RemoveNode) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_LinkedList_RemoveNode) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_LinkedList_EnableCircularMode) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_LinkedList_EnableCircularMode) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_LinkedList_DisableCircularMode) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_LinkedList_DisableCircularMode) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Start) refers to stm32h7xx_hal_mdma.o(.text.MDMA_SetConfig) for MDMA_SetConfig + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_Start) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Start) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.MDMA_SetConfig) refers to stm32h7xx_hal_mdma.o(.text.MDMA_SetConfig) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Start_IT) refers to stm32h7xx_hal_mdma.o(.text.MDMA_SetConfig) for MDMA_SetConfig + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_Start_IT) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Start_IT) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Abort) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_Abort) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Abort) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_Abort_IT) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Abort_IT) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.text.HAL_MDMA_PollForTransfer) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_mdma.o(.text.HAL_MDMA_PollForTransfer) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Abort) for HAL_MDMA_Abort + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_PollForTransfer) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_PollForTransfer) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_GenerateSWRequest) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_GenerateSWRequest) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.text.HAL_MDMA_IRQHandler) refers to system_stm32h7xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_IRQHandler) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_GetState) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_GetState) for [Anonymous Symbol] + stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_GetError) refers to stm32h7xx_hal_mdma.o(.text.HAL_MDMA_GetError) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DeInit) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableBkUpAccess) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnableBkUpAccess) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableBkUpAccess) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_DisableBkUpAccess) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_ConfigPVD) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_ConfigPVD) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnablePVD) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnablePVD) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisablePVD) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_DisablePVD) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableWakeUpPin) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnableWakeUpPin) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableWakeUpPin) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_DisableWakeUpPin) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSLEEPMode) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnterSLEEPMode) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTOPMode) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnterSTOPMode) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTANDBYMode) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnterSTANDBYMode) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSleepOnExit) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnableSleepOnExit) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSleepOnExit) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_DisableSleepOnExit) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSEVOnPend) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnableSEVOnPend) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSEVOnPend) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_DisableSEVOnPend) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.text.HAL_PWR_PVD_IRQHandler) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_PVDCallback) for HAL_PWR_PVDCallback + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVD_IRQHandler) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_PVD_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVDCallback) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_PVDCallback) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigSupply) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ConfigSupply) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigSupply) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetSupplyConfig) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetSupplyConfig) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlVoltageScaling) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ControlVoltageScaling) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlVoltageScaling) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetVoltageRange) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetVoltageRange) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ControlStopModeVoltageScaling) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlStopModeVoltageScaling) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetStopModeVoltageRange) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetStopModeVoltageRange) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnterSTOPMode) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnterSTOPMode) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ClearPendingEvent) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ClearPendingEvent) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnterSTANDBYMode) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnterSTANDBYMode) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ConfigD3Domain) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigD3Domain) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableFlashPowerDown) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableFlashPowerDown) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableFlashPowerDown) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableFlashPowerDown) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableWakeUpPin) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableWakeUpPin) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableWakeUpPin) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableWakeUpPin) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetWakeupFlag) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetWakeupFlag) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ClearWakeupFlag) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ClearWakeupFlag) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WAKEUP_PIN_IRQHandler) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP6_Callback) for HAL_PWREx_WKUP6_Callback + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WAKEUP_PIN_IRQHandler) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP1_Callback) for HAL_PWREx_WKUP1_Callback + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WAKEUP_PIN_IRQHandler) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP2_Callback) for HAL_PWREx_WKUP2_Callback + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WAKEUP_PIN_IRQHandler) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP4_Callback) for HAL_PWREx_WKUP4_Callback + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_WAKEUP_PIN_IRQHandler) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WAKEUP_PIN_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_WKUP1_Callback) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP1_Callback) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_WKUP2_Callback) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP2_Callback) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_WKUP4_Callback) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP4_Callback) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_WKUP6_Callback) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP6_Callback) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBkUpReg) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableBkUpReg) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBkUpReg) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBkUpReg) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableBkUpReg) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBkUpReg) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUSBReg) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableUSBReg) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUSBReg) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUSBReg) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableUSBReg) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUSBReg) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableUSBVoltageDetector) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUSBVoltageDetector) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableUSBVoltageDetector) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUSBVoltageDetector) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableBatteryCharging) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBatteryCharging) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableBatteryCharging) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBatteryCharging) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableMonitoring) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableMonitoring) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableMonitoring) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableMonitoring) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetTemperatureLevel) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetTemperatureLevel) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetVBATLevel) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetVBATLevel) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ConfigAVD) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigAVD) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableAVD) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableAVD) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableAVD) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableAVD) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_IRQHandler) refers to stm32h7xx_hal_pwr.o(.text.HAL_PWR_PVDCallback) for HAL_PWR_PVDCallback + stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_IRQHandler) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_AVDCallback) for HAL_PWREx_AVDCallback + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_PVD_AVD_IRQHandler) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_AVDCallback) refers to stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_AVDCallback) for [Anonymous Symbol] + stm32h7xx_hal.o(.text.HAL_Init) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) for HAL_NVIC_SetPriorityGrouping + stm32h7xx_hal.o(.text.HAL_Init) refers to stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for HAL_RCC_GetSysClockFreq + stm32h7xx_hal.o(.text.HAL_Init) refers to system_stm32h7xx.o(.rodata.D1CorePrescTable) for D1CorePrescTable + stm32h7xx_hal.o(.text.HAL_Init) refers to system_stm32h7xx.o(.data.SystemD2Clock) for SystemD2Clock + stm32h7xx_hal.o(.text.HAL_Init) refers to system_stm32h7xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h7xx_hal.o(.text.HAL_Init) refers to stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) for HAL_InitTick + stm32h7xx_hal.o(.text.HAL_Init) refers to stm32h7xx_hal_msp.o(.text.HAL_MspInit) for HAL_MspInit + stm32h7xx_hal.o(.ARM.exidx.text.HAL_Init) refers to stm32h7xx_hal.o(.text.HAL_Init) for [Anonymous Symbol] + stm32h7xx_hal.o(.text.HAL_InitTick) refers to stm32h7xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32h7xx_hal.o(.text.HAL_InitTick) refers to system_stm32h7xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h7xx_hal.o(.text.HAL_InitTick) refers to stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_Config) for HAL_SYSTICK_Config + stm32h7xx_hal.o(.text.HAL_InitTick) refers to stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + stm32h7xx_hal.o(.text.HAL_InitTick) refers to stm32h7xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h7xx_hal.o(.ARM.exidx.text.HAL_InitTick) refers to stm32h7xx_hal.o(.text.HAL_InitTick) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_MspInit) refers to stm32h7xx_hal.o(.text.HAL_MspInit) for [Anonymous Symbol] + stm32h7xx_hal.o(.text.HAL_DeInit) refers to stm32h7xx_hal.o(.text.HAL_MspDeInit) for HAL_MspDeInit + stm32h7xx_hal.o(.ARM.exidx.text.HAL_DeInit) refers to stm32h7xx_hal.o(.text.HAL_DeInit) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_MspDeInit) refers to stm32h7xx_hal.o(.text.HAL_MspDeInit) for [Anonymous Symbol] + stm32h7xx_hal.o(.text.HAL_IncTick) refers to stm32h7xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32h7xx_hal.o(.text.HAL_IncTick) refers to stm32h7xx_hal.o(.bss.uwTick) for uwTick + stm32h7xx_hal.o(.ARM.exidx.text.HAL_IncTick) refers to stm32h7xx_hal.o(.text.HAL_IncTick) for [Anonymous Symbol] + stm32h7xx_hal.o(.text.HAL_GetTick) refers to stm32h7xx_hal.o(.bss.uwTick) for uwTick + stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetTick) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for [Anonymous Symbol] + stm32h7xx_hal.o(.text.HAL_GetTickPrio) refers to stm32h7xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetTickPrio) refers to stm32h7xx_hal.o(.text.HAL_GetTickPrio) for [Anonymous Symbol] + stm32h7xx_hal.o(.text.HAL_SetTickFreq) refers to stm32h7xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32h7xx_hal.o(.text.HAL_SetTickFreq) refers to stm32h7xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h7xx_hal.o(.text.HAL_SetTickFreq) refers to stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) for HAL_InitTick + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SetTickFreq) refers to stm32h7xx_hal.o(.text.HAL_SetTickFreq) for [Anonymous Symbol] + stm32h7xx_hal.o(.text.HAL_GetTickFreq) refers to stm32h7xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetTickFreq) refers to stm32h7xx_hal.o(.text.HAL_GetTickFreq) for [Anonymous Symbol] + stm32h7xx_hal.o(.text.HAL_Delay) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal.o(.text.HAL_Delay) refers to stm32h7xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32h7xx_hal.o(.ARM.exidx.text.HAL_Delay) refers to stm32h7xx_hal.o(.text.HAL_Delay) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SuspendTick) refers to stm32h7xx_hal.o(.text.HAL_SuspendTick) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_ResumeTick) refers to stm32h7xx_hal.o(.text.HAL_ResumeTick) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetHalVersion) refers to stm32h7xx_hal.o(.text.HAL_GetHalVersion) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetREVID) refers to stm32h7xx_hal.o(.text.HAL_GetREVID) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetDEVID) refers to stm32h7xx_hal.o(.text.HAL_GetDEVID) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetUIDw0) refers to stm32h7xx_hal.o(.text.HAL_GetUIDw0) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetUIDw1) refers to stm32h7xx_hal.o(.text.HAL_GetUIDw1) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetUIDw2) refers to stm32h7xx_hal.o(.text.HAL_GetUIDw2) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_VREFBUF_VoltageScalingConfig) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_VREFBUF_VoltageScalingConfig) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_VREFBUF_HighImpedanceConfig) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_VREFBUF_HighImpedanceConfig) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_VREFBUF_TrimmingConfig) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_VREFBUF_TrimmingConfig) for [Anonymous Symbol] + stm32h7xx_hal.o(.text.HAL_SYSCFG_EnableVREFBUF) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_EnableVREFBUF) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_EnableVREFBUF) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_DisableVREFBUF) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_DisableVREFBUF) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_ETHInterfaceSelect) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_ETHInterfaceSelect) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_AnalogSwitchConfig) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_AnalogSwitchConfig) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_EnableBOOST) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_EnableBOOST) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_DisableBOOST) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_DisableBOOST) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_CM7BootAddConfig) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_CM7BootAddConfig) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_EnableCompensationCell) refers to stm32h7xx_hal.o(.text.HAL_EnableCompensationCell) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_DisableCompensationCell) refers to stm32h7xx_hal.o(.text.HAL_DisableCompensationCell) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_EnableIOSpeedOptimize) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_EnableIOSpeedOptimize) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_DisableIOSpeedOptimize) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_DisableIOSpeedOptimize) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_CompensationCodeSelect) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_CompensationCodeSelect) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_CompensationCodeConfig) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_CompensationCodeConfig) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_ADC2ALT_Rout0Config) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_ADC2ALT_Rout0Config) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_ADC2ALT_Rout1Config) refers to stm32h7xx_hal.o(.text.HAL_SYSCFG_ADC2ALT_Rout1Config) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGSleepMode) refers to stm32h7xx_hal.o(.text.HAL_DBGMCU_EnableDBGSleepMode) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGSleepMode) refers to stm32h7xx_hal.o(.text.HAL_DBGMCU_DisableDBGSleepMode) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStopMode) refers to stm32h7xx_hal.o(.text.HAL_DBGMCU_EnableDBGStopMode) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStopMode) refers to stm32h7xx_hal.o(.text.HAL_DBGMCU_DisableDBGStopMode) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStandbyMode) refers to stm32h7xx_hal.o(.text.HAL_DBGMCU_EnableDBGStandbyMode) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStandbyMode) refers to stm32h7xx_hal.o(.text.HAL_DBGMCU_DisableDBGStandbyMode) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_EnableDomain3DBGStopMode) refers to stm32h7xx_hal.o(.text.HAL_EnableDomain3DBGStopMode) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_DisableDomain3DBGStopMode) refers to stm32h7xx_hal.o(.text.HAL_DisableDomain3DBGStopMode) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_EnableDomain3DBGStandbyMode) refers to stm32h7xx_hal.o(.text.HAL_EnableDomain3DBGStandbyMode) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_DisableDomain3DBGStandbyMode) refers to stm32h7xx_hal.o(.text.HAL_DisableDomain3DBGStandbyMode) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_SetFMCMemorySwappingConfig) refers to stm32h7xx_hal.o(.text.HAL_SetFMCMemorySwappingConfig) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetFMCMemorySwappingConfig) refers to stm32h7xx_hal.o(.text.HAL_GetFMCMemorySwappingConfig) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_EXTI_EdgeConfig) refers to stm32h7xx_hal.o(.text.HAL_EXTI_EdgeConfig) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_EXTI_GenerateSWInterrupt) refers to stm32h7xx_hal.o(.text.HAL_EXTI_GenerateSWInterrupt) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_EXTI_D1_ClearFlag) refers to stm32h7xx_hal.o(.text.HAL_EXTI_D1_ClearFlag) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_EXTI_D1_EventInputConfig) refers to stm32h7xx_hal.o(.text.HAL_EXTI_D1_EventInputConfig) for [Anonymous Symbol] + stm32h7xx_hal.o(.ARM.exidx.text.HAL_EXTI_D3_EventInputConfig) refers to stm32h7xx_hal.o(.text.HAL_EXTI_D3_EventInputConfig) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Init) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MspInit) for HAL_I2C_MspInit + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Init) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Init) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MspInit) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MspInit) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_DeInit) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MspDeInit) for HAL_I2C_MspDeInit + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_DeInit) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_DeInit) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MspDeInit) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MspDeInit) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnTXISFlagUntilTimeout) for I2C_WaitOnTXISFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) for I2C_WaitOnSTOPFlagUntilTimeout + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) refers to stm32h7xx_hal_i2c.o(.text.I2C_IsErrorOccurred) for I2C_IsErrorOccurred + stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnFlagUntilTimeout) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_TransferConfig) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_WaitOnTXISFlagUntilTimeout) refers to stm32h7xx_hal_i2c.o(.text.I2C_IsErrorOccurred) for I2C_IsErrorOccurred + stm32h7xx_hal_i2c.o(.text.I2C_WaitOnTXISFlagUntilTimeout) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnTXISFlagUntilTimeout) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnTXISFlagUntilTimeout) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) refers to stm32h7xx_hal_i2c.o(.text.I2C_IsErrorOccurred) for I2C_IsErrorOccurred + stm32h7xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnSTOPFlagUntilTimeout) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout) for I2C_WaitOnRXNEFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) for I2C_WaitOnSTOPFlagUntilTimeout + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout) refers to stm32h7xx_hal_i2c.o(.text.I2C_IsErrorOccurred) for I2C_IsErrorOccurred + stm32h7xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnRXNEFlagUntilTimeout) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnTXISFlagUntilTimeout) for I2C_WaitOnTXISFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) for I2C_WaitOnSTOPFlagUntilTimeout + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Flush_TXDR) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout) for I2C_WaitOnRXNEFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) for I2C_WaitOnSTOPFlagUntilTimeout + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) for I2C_Master_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) for I2C_ITMasterCplt + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITMasterSeqCplt) for I2C_ITMasterSeqCplt + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Master_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) refers to stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA) for I2C_Mem_ISR_DMA + stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) for I2C_Master_ISR_DMA + stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) for I2C_Slave_ISR_DMA + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Enable_IRQ) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) for I2C_Master_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) for I2C_Slave_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) for I2C_ITSlaveCplt + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveSeqCplt) for I2C_ITSlaveSeqCplt + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITAddrCplt) for I2C_ITAddrCplt + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITListenCplt) for I2C_ITListenCplt + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Slave_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) for I2C_Slave_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) for I2C_Master_ISR_DMA + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterTransmitCplt) for I2C_DMAMasterTransmitCplt + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) for I2C_Master_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) for I2C_ITMasterCplt + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITMasterSeqCplt) for I2C_ITMasterSeqCplt + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Master_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterTransmitCplt) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterTransmitCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterTransmitCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAMasterTransmitCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterTransmitCplt) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_DMAError) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_GetError) for HAL_DMA_GetError + stm32h7xx_hal_i2c.o(.text.I2C_DMAError) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAError) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) for I2C_Master_ISR_DMA + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterReceiveCplt) for I2C_DMAMasterReceiveCplt + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) for I2C_Master_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterReceiveCplt) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterReceiveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterReceiveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAMasterReceiveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterReceiveCplt) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) for I2C_Slave_ISR_DMA + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMASlaveTransmitCplt) for I2C_DMASlaveTransmitCplt + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITAddrCplt) for I2C_ITAddrCplt + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) for I2C_ITSlaveCplt + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveSeqCplt) for I2C_ITSlaveSeqCplt + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITListenCplt) for I2C_ITListenCplt + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Slave_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_DMASlaveTransmitCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveSeqCplt) for I2C_ITSlaveSeqCplt + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMASlaveTransmitCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMASlaveTransmitCplt) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) for I2C_Slave_ISR_DMA + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMASlaveReceiveCplt) for I2C_DMASlaveReceiveCplt + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_DMASlaveReceiveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveSeqCplt) for I2C_ITSlaveSeqCplt + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMASlaveReceiveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMASlaveReceiveCplt) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) for I2C_RequestMemoryWrite + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnTXISFlagUntilTimeout) for I2C_WaitOnTXISFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) for I2C_WaitOnSTOPFlagUntilTimeout + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnTXISFlagUntilTimeout) for I2C_WaitOnTXISFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_RequestMemoryWrite) refers to stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) refers to stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryRead) for I2C_RequestMemoryRead + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) for I2C_WaitOnSTOPFlagUntilTimeout + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryRead) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryRead) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnTXISFlagUntilTimeout) for I2C_WaitOnTXISFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryRead) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_RequestMemoryRead) refers to stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryRead) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_IT) for I2C_Mem_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) for I2C_ITMasterCplt + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Mem_ISR_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_IT) for I2C_Mem_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA) for I2C_Mem_ISR_DMA + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterTransmitCplt) for I2C_DMAMasterTransmitCplt + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write_DMA) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) for I2C_ITMasterCplt + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Mem_ISR_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA) for I2C_Mem_ISR_DMA + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterReceiveCplt) for I2C_DMAMasterReceiveCplt + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read_DMA) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_IsDeviceReady) refers to stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32h7xx_hal_i2c.o(.text.HAL_I2C_IsDeviceReady) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_IsDeviceReady) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_IsDeviceReady) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) for I2C_Master_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ConvertOtherXferOptions) for I2C_ConvertOtherXferOptions + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ConvertOtherXferOptions) refers to stm32h7xx_hal_i2c.o(.text.I2C_ConvertOtherXferOptions) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) for I2C_Master_ISR_DMA + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ConvertOtherXferOptions) for I2C_ConvertOtherXferOptions + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterTransmitCplt) for I2C_DMAMasterTransmitCplt + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) for I2C_Master_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) for I2C_Master_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_ConvertOtherXferOptions) for I2C_ConvertOtherXferOptions + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA) for I2C_Master_ISR_DMA + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_ConvertOtherXferOptions) for I2C_ConvertOtherXferOptions + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterReceiveCplt) for I2C_DMAMasterReceiveCplt + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT) for I2C_Master_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAAbort) for I2C_DMAAbort + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_IT) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) for I2C_Slave_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Transmit_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Disable_IRQ) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_DMAAbort) refers to stm32h7xx_hal_i2c.o(.text.I2C_TreatErrorCallback) for I2C_TreatErrorCallback + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAAbort) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAAbort) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAAbort) for I2C_DMAAbort + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) for I2C_Slave_ISR_DMA + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMASlaveTransmitCplt) for I2C_DMASlaveTransmitCplt + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAAbort) for I2C_DMAAbort + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_IT) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) for I2C_Slave_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Receive_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAAbort) for I2C_DMAAbort + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA) for I2C_Slave_ISR_DMA + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMASlaveReceiveCplt) for I2C_DMASlaveReceiveCplt + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_EnableListen_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) for I2C_Slave_ISR_IT + stm32h7xx_hal_i2c.o(.text.HAL_I2C_EnableListen_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_EnableListen_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_EnableListen_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_DisableListen_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_DisableListen_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_DisableListen_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Abort_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Abort_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig) for I2C_TransferConfig + stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Abort_IT) refers to stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ) for I2C_Enable_IRQ + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Abort_IT) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Abort_IT) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_EV_IRQHandler) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.HAL_I2C_ER_IRQHandler) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ER_IRQHandler) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_ER_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_ITError) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_ITError) refers to stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT) for I2C_Slave_ISR_IT + stm32h7xx_hal_i2c.o(.text.I2C_ITError) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.text.I2C_ITError) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_GetState) for HAL_DMA_GetState + stm32h7xx_hal_i2c.o(.text.I2C_ITError) refers to stm32h7xx_hal_i2c.o(.text.I2C_DMAAbort) for I2C_DMAAbort + stm32h7xx_hal_i2c.o(.text.I2C_ITError) refers to stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h7xx_hal_i2c.o(.text.I2C_ITError) refers to stm32h7xx_hal_i2c.o(.text.I2C_TreatErrorCallback) for I2C_TreatErrorCallback + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITError) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MasterTxCpltCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MasterTxCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MasterRxCpltCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MasterRxCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_SlaveTxCpltCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_SlaveTxCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_SlaveRxCpltCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_SlaveRxCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_AddrCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_AddrCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ListenCpltCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_ListenCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MemTxCpltCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MemTxCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MemRxCpltCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MemRxCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ErrorCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_ErrorCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_AbortCpltCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_AbortCpltCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetState) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_GetState) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetMode) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_GetMode) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetError) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_GetError) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_ITMasterSeqCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_ITMasterSeqCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MasterTxCpltCallback) for HAL_I2C_MasterTxCpltCallback + stm32h7xx_hal_i2c.o(.text.I2C_ITMasterSeqCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MasterRxCpltCallback) for HAL_I2C_MasterRxCpltCallback + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITMasterSeqCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITMasterSeqCplt) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MemTxCpltCallback) for HAL_I2C_MemTxCpltCallback + stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MemRxCpltCallback) for HAL_I2C_MemRxCpltCallback + stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MasterTxCpltCallback) for HAL_I2C_MasterTxCpltCallback + stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_MasterRxCpltCallback) for HAL_I2C_MasterRxCpltCallback + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITMasterCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveSeqCplt) for I2C_ITSlaveSeqCplt + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITListenCplt) for I2C_ITListenCplt + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_SlaveRxCpltCallback) for HAL_I2C_SlaveRxCpltCallback + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_ListenCpltCallback) for HAL_I2C_ListenCpltCallback + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_SlaveTxCpltCallback) for HAL_I2C_SlaveTxCpltCallback + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITSlaveCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_ITListenCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_ITListenCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_ListenCpltCallback) for HAL_I2C_ListenCpltCallback + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITListenCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITListenCplt) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveSeqCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveSeqCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_SlaveTxCpltCallback) for HAL_I2C_SlaveTxCpltCallback + stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveSeqCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_SlaveRxCpltCallback) for HAL_I2C_SlaveRxCpltCallback + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITSlaveSeqCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveSeqCplt) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_ITAddrCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ) for I2C_Disable_IRQ + stm32h7xx_hal_i2c.o(.text.I2C_ITAddrCplt) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_AddrCallback) for HAL_I2C_AddrCallback + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITAddrCplt) refers to stm32h7xx_hal_i2c.o(.text.I2C_ITAddrCplt) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_TreatErrorCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_AbortCpltCallback) for HAL_I2C_AbortCpltCallback + stm32h7xx_hal_i2c.o(.text.I2C_TreatErrorCallback) refers to stm32h7xx_hal_i2c.o(.text.HAL_I2C_ErrorCallback) for HAL_I2C_ErrorCallback + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_TreatErrorCallback) refers to stm32h7xx_hal_i2c.o(.text.I2C_TreatErrorCallback) for [Anonymous Symbol] + stm32h7xx_hal_i2c.o(.text.I2C_IsErrorOccurred) refers to stm32h7xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h7xx_hal_i2c.o(.text.I2C_IsErrorOccurred) refers to stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR) for I2C_Flush_TXDR + stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_IsErrorOccurred) refers to stm32h7xx_hal_i2c.o(.text.I2C_IsErrorOccurred) for [Anonymous Symbol] + stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_ConfigAnalogFilter) refers to stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_ConfigAnalogFilter) for [Anonymous Symbol] + stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_ConfigDigitalFilter) refers to stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_ConfigDigitalFilter) for [Anonymous Symbol] + stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_EnableWakeUp) refers to stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_EnableWakeUp) for [Anonymous Symbol] + stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_DisableWakeUp) refers to stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_DisableWakeUp) for [Anonymous Symbol] + stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_EnableFastModePlus) refers to stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_EnableFastModePlus) for [Anonymous Symbol] + stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_DisableFastModePlus) refers to stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_DisableFastModePlus) for [Anonymous Symbol] + stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_SetConfigLine) refers to stm32h7xx_hal_exti.o(.text.HAL_EXTI_SetConfigLine) for [Anonymous Symbol] + stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetConfigLine) refers to stm32h7xx_hal_exti.o(.text.HAL_EXTI_GetConfigLine) for [Anonymous Symbol] + stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearConfigLine) refers to stm32h7xx_hal_exti.o(.text.HAL_EXTI_ClearConfigLine) for [Anonymous Symbol] + stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_RegisterCallback) refers to stm32h7xx_hal_exti.o(.text.HAL_EXTI_RegisterCallback) for [Anonymous Symbol] + stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetHandle) refers to stm32h7xx_hal_exti.o(.text.HAL_EXTI_GetHandle) for [Anonymous Symbol] + stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_IRQHandler) refers to stm32h7xx_hal_exti.o(.text.HAL_EXTI_IRQHandler) for [Anonymous Symbol] + stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetPending) refers to stm32h7xx_hal_exti.o(.text.HAL_EXTI_GetPending) for [Anonymous Symbol] + stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearPending) refers to stm32h7xx_hal_exti.o(.text.HAL_EXTI_ClearPending) for [Anonymous Symbol] + stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GenerateSWI) refers to stm32h7xx_hal_exti.o(.text.HAL_EXTI_GenerateSWI) for [Anonymous Symbol] + system_stm32h7xx.o(.ARM.exidx.text.SystemInit) refers to system_stm32h7xx.o(.text.SystemInit) for [Anonymous Symbol] + system_stm32h7xx.o(.text.SystemCoreClockUpdate) refers to system_stm32h7xx.o(.rodata.D1CorePrescTable) for D1CorePrescTable + system_stm32h7xx.o(.text.SystemCoreClockUpdate) refers to system_stm32h7xx.o(.data.SystemD2Clock) for SystemD2Clock + system_stm32h7xx.o(.text.SystemCoreClockUpdate) refers to system_stm32h7xx.o(.data.SystemCoreClock) for SystemCoreClock + system_stm32h7xx.o(.ARM.exidx.text.SystemCoreClockUpdate) refers to system_stm32h7xx.o(.text.SystemCoreClockUpdate) for [Anonymous Symbol] + system_stm32h7xx.o(.ARM.exidx.text.ExitRun0Mode) refers to system_stm32h7xx.o(.text.ExitRun0Mode) for [Anonymous Symbol] + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text.main) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_stm32h723xx.o(.text) for __user_initial_stackheap + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000001) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1 + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + libinit2.o(.ARM.Collect$$libinit$$00000001) refers to fpinit.o(x$fpl$fpinit) for _fp_init + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv + sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_exit_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_command_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_wrch_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.text), (0 bytes). + Removing main.o(.ARM.exidx.text.main), (8 bytes). + Removing main.o(.ARM.exidx.text.SystemClock_Config), (8 bytes). + Removing main.o(.ARM.exidx.text.Error_Handler), (8 bytes). + Removing main.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedCallback), (8 bytes). + Removing main.o(.ARM.use_no_argv), (4 bytes). + Removing gpio.o(.text), (0 bytes). + Removing gpio.o(.ARM.exidx.text.MX_GPIO_Init), (8 bytes). + Removing fdcan.o(.text), (0 bytes). + Removing fdcan.o(.ARM.exidx.text.MX_FDCAN1_Init), (8 bytes). + Removing fdcan.o(.ARM.exidx.text.HAL_FDCAN_MspInit), (8 bytes). + Removing fdcan.o(.text.HAL_FDCAN_MspDeInit), (56 bytes). + Removing fdcan.o(.ARM.exidx.text.HAL_FDCAN_MspDeInit), (8 bytes). + Removing stm32h7xx_it.o(.text), (0 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.NMI_Handler), (8 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.HardFault_Handler), (8 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.MemManage_Handler), (8 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.BusFault_Handler), (8 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.UsageFault_Handler), (8 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.SVC_Handler), (8 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.DebugMon_Handler), (8 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.PendSV_Handler), (8 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.SysTick_Handler), (8 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.FDCAN1_IT0_IRQHandler), (8 bytes). + Removing stm32h7xx_it.o(.ARM.exidx.text.TIM2_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_msp.o(.text), (0 bytes). + Removing stm32h7xx_hal_msp.o(.ARM.exidx.text.HAL_MspInit), (8 bytes). + Removing stm32h7xx_hal_timebase_tim.o(.text), (0 bytes). + Removing stm32h7xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_InitTick), (8 bytes). + Removing stm32h7xx_hal_timebase_tim.o(.text.HAL_SuspendTick), (20 bytes). + Removing stm32h7xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_SuspendTick), (8 bytes). + Removing stm32h7xx_hal_timebase_tim.o(.text.HAL_ResumeTick), (20 bytes). + Removing stm32h7xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_ResumeTick), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text), (0 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Init), (8 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_Base_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_DeInit), (104 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_DeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_MspDeInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start), (190 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Stop), (42 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop), (8 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Stop_IT), (50 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA), (276 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_DMA), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt), (28 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedCplt), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt), (10 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedHalfCplt), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_DMAError), (92 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMAError), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Stop_DMA), (60 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_DMA), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Init), (96 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Init), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_MspInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_DeInit), (104 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_MspDeInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspDeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start), (478 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_CCxChannelCmd), (30 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_CCxChannelCmd), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Stop), (214 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start_IT), (532 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Stop_IT), (264 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA), (832 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_DMA), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseCplt), (116 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseCplt), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt), (56 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseHalfCplt), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA), (304 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_DMA), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Init), (96 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Init), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_DeInit), (104 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_DeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_MspDeInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspDeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start), (478 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Stop), (214 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start_IT), (532 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_IT), (264 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA), (832 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_DMA), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA), (304 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_DMA), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Init), (96 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Init), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_MspInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_DeInit), (104 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_DeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_MspDeInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspDeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start), (388 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Stop), (158 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start_IT), (440 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Stop_IT), (216 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA), (698 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_DMA), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_DMACaptureCplt), (132 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureCplt), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt), (56 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureHalfCplt), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA), (244 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_DMA), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init), (90 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Init), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_DeInit), (80 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_DeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspDeInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspDeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start), (162 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop), (168 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start_IT), (178 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop_IT), (184 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Init), (184 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Init), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_MspInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_DeInit), (80 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_DeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_MspDeInit), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspDeInit), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start), (160 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop), (186 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_IT), (206 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_IT), (238 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA), (526 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_DMA), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA), (266 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_DMA), (8 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureCallback), (8 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DelayElapsedCallback), (8 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedCallback), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedCallback), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedCallback), (8 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerCallback), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel), (96 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_ConfigChannel), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_OC1_SetConfig), (194 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC1_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_OC2_SetConfig), (172 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC2_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_OC3_SetConfig), (172 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC3_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_OC4_SetConfig), (132 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC4_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_OC5_SetConfig), (130 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC5_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_OC6_SetConfig), (132 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_OC6_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel), (154 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_ConfigChannel), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_TI1_SetConfig), (192 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_TI2_SetConfig), (58 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_TI3_SetConfig), (52 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI3_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_TI4_SetConfig), (58 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI4_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel), (188 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_ConfigChannel), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel), (238 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_ConfigChannel), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStart), (28 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStart), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart), (458 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiWriteStart), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_DMATriggerCplt), (28 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerCplt), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt), (10 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerHalfCplt), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStop), (136 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStop), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStart), (28 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStart), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart), (460 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiReadStart), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStop), (136 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStop), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_GenerateEvent), (36 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GenerateEvent), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigOCrefClear), (272 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigOCrefClear), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_ETR_SetConfig), (20 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_ETR_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource), (270 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigClockSource), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage), (34 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_ConfigInputStage), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_ITRx_SetConfig), (22 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_ITRx_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage), (36 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_ConfigInputStage), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_ConfigTI1Input), (16 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigTI1Input), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro), (74 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig), (320 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.TIM_SlaveTimer_SetConfig), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro_IT), (74 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro_IT), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_ReadCapturedValue), (52 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ReadCapturedValue), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedHalfCpltCallback), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedHalfCpltCallback), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_CaptureHalfCpltCallback), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureHalfCpltCallback), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_TriggerHalfCpltCallback), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerHalfCpltCallback), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_ErrorCallback), (2 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ErrorCallback), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_GetState), (6 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_GetState), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_GetState), (6 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_GetState), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_GetState), (6 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_GetState), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_GetState), (6 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_GetState), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_OnePulse_GetState), (6 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_GetState), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_Encoder_GetState), (6 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_GetState), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_GetActiveChannel), (4 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetActiveChannel), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_GetChannelState), (54 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetChannelState), (8 bytes). + Removing stm32h7xx_hal_tim.o(.text.HAL_TIM_DMABurstState), (6 bytes). + Removing stm32h7xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurstState), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text), (0 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init), (206 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Init), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspInit), (2 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspInit), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_DeInit), (80 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_DeInit), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspDeInit), (2 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspDeInit), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start), (240 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop), (66 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_IT), (248 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_IT), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_IT), (74 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_IT), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA), (326 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_DMA), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA), (74 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_DMA), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start), (268 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd), (30 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.TIM_CCxNChannelCmd), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop), (112 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_IT), (328 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_IT), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_IT), (184 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_IT), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA), (534 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_DMA), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt), (90 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMADelayPulseNCplt), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN), (66 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMAErrorCCxN), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA), (190 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_DMA), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start), (268 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop), (112 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_IT), (328 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_IT), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_IT), (184 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_IT), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA), (534 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_DMA), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA), (190 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_DMA), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start), (100 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop), (106 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT), (116 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start_IT), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT), (122 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop_IT), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent), (144 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_IT), (144 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_IT), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA), (184 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_DMA), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt), (16 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationCplt), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt), (16 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationHalfCplt), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_MasterConfigSynchronization), (224 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_MasterConfigSynchronization), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakDeadTime), (206 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakDeadTime), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakInput), (316 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakInput), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_RemapConfig), (34 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_RemapConfig), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_TISelection), (76 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_TISelection), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_GroupChannel5), (48 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_GroupChannel5), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_DisarmBreakInput), (76 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisarmBreakInput), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_ReArmBreakInput), (130 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ReArmBreakInput), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutCallback), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutHalfCpltCallback), (2 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutHalfCpltCallback), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_BreakCallback), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_Break2Callback), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_GetState), (6 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_GetState), (8 bytes). + Removing stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_GetChannelNState), (32 bytes). + Removing stm32h7xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_GetChannelNState), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text), (0 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriorityGrouping), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriorityGrouping), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriority), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriorityGrouping), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriority), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.NVIC_EncodePriority), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_EnableIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_EnableIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_DisableIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.__NVIC_DisableIRQ), (40 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_DisableIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SystemReset), (4 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SystemReset), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.__NVIC_SystemReset), (36 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SystemReset), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_Config), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Config), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.SysTick_Config), (46 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.SysTick_Config), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_MPU_Disable), (26 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Disable), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_MPU_Enable), (32 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Enable), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_MPU_EnableRegion), (22 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_EnableRegion), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_MPU_DisableRegion), (22 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_DisableRegion), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_MPU_ConfigRegion), (94 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_ConfigRegion), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetPriorityGrouping), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriorityGrouping), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetPriority), (24 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriority), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.NVIC_DecodePriority), (56 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.NVIC_DecodePriority), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.__NVIC_GetPriority), (34 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriority), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPendingIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPendingIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.__NVIC_SetPendingIRQ), (32 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPendingIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetPendingIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPendingIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.__NVIC_GetPendingIRQ), (36 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPendingIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_NVIC_ClearPendingIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_ClearPendingIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.__NVIC_ClearPendingIRQ), (32 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_ClearPendingIRQ), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_NVIC_GetActive), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetActive), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.__NVIC_GetActive), (36 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetActive), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig), (24 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_CLKSourceConfig), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_SYSTICK_Callback), (2 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Callback), (8 bytes). + Removing stm32h7xx_hal_cortex.o(.text.HAL_GetCurrentCPUID), (4 bytes). + Removing stm32h7xx_hal_cortex.o(.ARM.exidx.text.HAL_GetCurrentCPUID), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text), (0 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_Init), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_MspInit), (2 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_MspInit), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.FDCAN_CalcultateRamBlockAddresses), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DeInit), (42 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DeInit), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Stop), (128 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_Stop), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_MspDeInit), (2 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_MspDeInit), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnterPowerDownMode), (64 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnterPowerDownMode), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ExitPowerDownMode), (72 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ExitPowerDownMode), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigClockCalibration), (142 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigClockCalibration), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetClockCalibrationState), (16 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetClockCalibrationState), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ResetClockCalibrationState), (64 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ResetClockCalibrationState), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetClockCalibrationCounter), (36 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetClockCalibrationCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigFilter), (136 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigFilter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigGlobalFilter), (54 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigGlobalFilter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigExtendedIdMask), (34 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigExtendedIdMask), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigRxFifoOverwrite), (62 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigRxFifoOverwrite), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigFifoWatermark), (84 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigFifoWatermark), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigRamWatchdog), (40 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigRamWatchdog), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigTimestampCounter), (40 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigTimestampCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableTimestampCounter), (40 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableTimestampCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DisableTimestampCounter), (38 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DisableTimestampCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetTimestampCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetTimestampCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ResetTimestampCounter), (34 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ResetTimestampCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigTimeoutCounter), (50 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigTimeoutCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableTimeoutCounter), (36 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableTimeoutCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DisableTimeoutCounter), (38 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DisableTimeoutCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetTimeoutCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetTimeoutCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ResetTimeoutCounter), (32 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ResetTimeoutCounter), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigTxDelayCompensation), (36 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigTxDelayCompensation), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableTxDelayCompensation), (38 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableTxDelayCompensation), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DisableTxDelayCompensation), (38 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DisableTxDelayCompensation), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableISOMode), (38 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableISOMode), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DisableISOMode), (38 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DisableISOMode), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableEdgeFiltering), (38 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableEdgeFiltering), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DisableEdgeFiltering), (38 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DisableEdgeFiltering), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Start), (50 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_Start), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_AddMessageToTxFifoQ), (102 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_AddMessageToTxFifoQ), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.FDCAN_CopyMessageToRAM), (134 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.FDCAN_CopyMessageToRAM), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_AddMessageToTxBuffer), (96 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_AddMessageToTxBuffer), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_EnableTxBufferRequest), (34 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_EnableTxBufferRequest), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetLatestTxFifoQRequestBuffer), (6 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetLatestTxFifoQRequestBuffer), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_AbortTxRequest), (34 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_AbortTxRequest), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetRxMessage), (404 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetRxMessage), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetTxEvent), (176 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetTxEvent), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetHighPriorityMessageStatus), (46 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetHighPriorityMessageStatus), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetProtocolStatus), (74 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetProtocolStatus), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetErrorCounters), (30 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetErrorCounters), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IsRxBufferMessageAvailable), (70 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_IsRxBufferMessageAvailable), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IsTxBufferMessagePending), (14 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_IsTxBufferMessagePending), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetRxFifoFillLevel), (18 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetRxFifoFillLevel), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetTxFifoFreeLevel), (12 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetTxFifoFreeLevel), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IsRestrictedOperationMode), (10 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_IsRestrictedOperationMode), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ExitRestrictedOperationMode), (40 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ExitRestrictedOperationMode), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigOperation), (418 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigOperation), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigReferenceMessage), (72 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigReferenceMessage), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigTrigger), (128 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigTrigger), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_SetGlobalTime), (130 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_SetGlobalTime), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_SetClockSynchronization), (126 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_SetClockSynchronization), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigStopWatch), (108 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigStopWatch), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigRegisterTimeMark), (196 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigRegisterTimeMark), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_EnableRegisterTimeMarkPulse), (86 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_EnableRegisterTimeMarkPulse), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DisableRegisterTimeMarkPulse), (86 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DisableRegisterTimeMarkPulse), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_EnableTriggerTimeMarkPulse), (100 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_EnableTriggerTimeMarkPulse), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DisableTriggerTimeMarkPulse), (100 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DisableTriggerTimeMarkPulse), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_EnableHardwareGapControl), (100 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_EnableHardwareGapControl), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DisableHardwareGapControl), (100 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DisableHardwareGapControl), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_EnableTimeMarkGapControl), (100 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_EnableTimeMarkGapControl), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DisableTimeMarkGapControl), (100 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DisableTimeMarkGapControl), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_SetNextIsGap), (108 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_SetNextIsGap), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_SetEndOfGap), (108 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_SetEndOfGap), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigExternalSyncPhase), (60 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigExternalSyncPhase), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_EnableExternalSynchronization), (86 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_EnableExternalSynchronization), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DisableExternalSynchronization), (86 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DisableExternalSynchronization), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_GetOperationStatus), (90 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_GetOperationStatus), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ConfigInterruptLines), (52 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ConfigInterruptLines), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ConfigInterruptLines), (52 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ConfigInterruptLines), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ActivateNotification), (120 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ActivateNotification), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_DeactivateNotification), (124 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_DeactivateNotification), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ActivateNotification), (72 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ActivateNotification), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_DeactivateNotification), (86 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_DeactivateNotification), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_HighPriorityMessageCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TxBufferAbortCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ClockCalibrationCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TxEventFifoCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_RxFifo0Callback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_RxFifo1Callback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TxFifoEmptyCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TxBufferCompleteCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_RxBufferNewMessageCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TimestampWraparoundCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TimeoutOccurredCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ErrorStatusCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_ScheduleSyncCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_TimeMarkCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_StopWatchCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_TT_GlobalTimeCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_ErrorCallback), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetState), (6 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetState), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_GetError), (6 bytes). + Removing stm32h7xx_hal_fdcan.o(.ARM.exidx.text.HAL_FDCAN_GetError), (8 bytes). + Removing stm32h7xx_hal_fdcan.o(.rodata.cst16), (16 bytes). + Removing stm32h7xx_hal_rcc.o(.text), (0 bytes). + Removing stm32h7xx_hal_rcc.o(.text.HAL_RCC_DeInit), (442 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DeInit), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_OscConfig), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_ClockConfig), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetSysClockFreq), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.text.HAL_RCC_MCOConfig), (154 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_MCOConfig), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.text.HAL_RCC_EnableCSS), (18 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_EnableCSS), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.text.HAL_RCC_DisableCSS), (18 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DisableCSS), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetHCLKFreq), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK1Freq), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq), (38 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK2Freq), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetOscConfig), (212 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetOscConfig), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetClockConfig), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.text.HAL_RCC_NMI_IRQHandler), (30 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_NMI_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_rcc.o(.text.HAL_RCC_CSSCallback), (2 bytes). + Removing stm32h7xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_CSSCallback), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text), (0 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_PeriphCLKConfig), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.RCCEx_PLL2_Config), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.RCCEx_PLL3_Config), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKConfig), (432 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKConfig), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq), (808 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKFreq), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL1ClockFreq), (296 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL1ClockFreq), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL2ClockFreq), (292 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL2ClockFreq), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL3ClockFreq), (292 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL3ClockFreq), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD3PCLK1Freq), (38 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetD3PCLK1Freq), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD1PCLK1Freq), (38 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetD1PCLK1Freq), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetD1SysClockFreq), (74 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetD1SysClockFreq), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnableLSECSS), (18 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnableLSECSS), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisableLSECSS), (26 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisableLSECSS), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnableLSECSS_IT), (52 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnableLSECSS_IT), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_WakeUpStopCLKConfig), (20 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_WakeUpStopCLKConfig), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_KerWakeUpStopCLKConfig), (20 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_KerWakeUpStopCLKConfig), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_WWDGxSysResetConfig), (16 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_WWDGxSysResetConfig), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSConfig), (112 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSConfig), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate), (18 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSGetSynchronizationInfo), (42 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSGetSynchronizationInfo), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSWaitSynchronization), (150 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSWaitSynchronization), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler), (84 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncOkCallback), (2 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_SyncOkCallback), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncWarnCallback), (2 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_SyncWarnCallback), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ExpectedSyncCallback), (2 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_ExpectedSyncCallback), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ErrorCallback), (2 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_ErrorCallback), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_IRQHandler), (30 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_LSECSS_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_Callback), (2 bytes). + Removing stm32h7xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_LSECSS_Callback), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text), (0 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_Program), (158 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.FLASH_WaitForLastOperation), (140 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.FLASH_WaitForLastOperation), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_Program_IT), (132 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program_IT), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_IRQHandler), (214 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_EndOfOperationCallback), (2 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_EndOfOperationCallback), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_OperationErrorCallback), (2 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OperationErrorCallback), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_Unlock), (48 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Unlock), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_Lock), (26 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Lock), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_OB_Unlock), (44 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Unlock), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_OB_Lock), (26 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Lock), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_OB_Launch), (46 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Launch), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.FLASH_CRC_WaitForLastOperation), (144 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.FLASH_CRC_WaitForLastOperation), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.FLASH_OB_WaitForLastOperation), (106 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.FLASH_OB_WaitForLastOperation), (8 bytes). + Removing stm32h7xx_hal_flash.o(.text.HAL_FLASH_GetError), (12 bytes). + Removing stm32h7xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_GetError), (8 bytes). + Removing stm32h7xx_hal_flash.o(.bss.pFlash), (28 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text), (0 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase), (232 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_MassErase), (38 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_MassErase), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_Erase_Sector), (38 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_Erase_Sector), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT), (144 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase_IT), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram), (200 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBProgram), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_EnableWRP), (30 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_EnableWRP), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_DisableWRP), (24 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_DisableWRP), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_RDPConfig), (20 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_RDPConfig), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_UserConfig), (194 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_UserConfig), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_PCROPConfig), (36 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_PCROPConfig), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_BOR_LevelConfig), (20 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_BOR_LevelConfig), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_BootAddConfig), (44 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_BootAddConfig), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_SecureAreaConfig), (40 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_SecureAreaConfig), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_SharedRAM_Config), (20 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_SharedRAM_Config), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_CPUFreq_BoostConfig), (20 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_CPUFreq_BoostConfig), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig), (128 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBGetConfig), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetRDP), (36 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetRDP), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetUser), (18 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetUser), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetBOR), (16 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetBOR), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetWRP), (34 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetWRP), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetPCROP), (64 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetPCROP), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetSecureArea), (64 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetSecureArea), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_GetBootAdd), (26 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetBootAdd), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_SharedRAM_GetConfig), (16 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_SharedRAM_GetConfig), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_OB_CPUFreq_GetBoost), (16 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_CPUFreq_GetBoost), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Unlock_Bank1), (48 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Unlock_Bank1), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_Lock_Bank1), (20 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Lock_Bank1), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.HAL_FLASHEx_ComputeCRC), (196 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_ComputeCRC), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_CRC_AddSector), (28 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_CRC_AddSector), (8 bytes). + Removing stm32h7xx_hal_flash_ex.o(.text.FLASH_CRC_SelectAddress), (14 bytes). + Removing stm32h7xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_CRC_SelectAddress), (8 bytes). + Removing stm32h7xx_hal_gpio.o(.text), (0 bytes). + Removing stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_Init), (8 bytes). + Removing stm32h7xx_hal_gpio.o(.text.HAL_GPIO_DeInit), (276 bytes). + Removing stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_DeInit), (8 bytes). + Removing stm32h7xx_hal_gpio.o(.text.HAL_GPIO_ReadPin), (10 bytes). + Removing stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_ReadPin), (8 bytes). + Removing stm32h7xx_hal_gpio.o(.text.HAL_GPIO_WritePin), (10 bytes). + Removing stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_WritePin), (8 bytes). + Removing stm32h7xx_hal_gpio.o(.text.HAL_GPIO_TogglePin), (16 bytes). + Removing stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_TogglePin), (8 bytes). + Removing stm32h7xx_hal_gpio.o(.text.HAL_GPIO_LockPin), (40 bytes). + Removing stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_LockPin), (8 bytes). + Removing stm32h7xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler), (24 bytes). + Removing stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Callback), (2 bytes). + Removing stm32h7xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Callback), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text), (0 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_Take), (32 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_Take), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_FastTake), (28 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_FastTake), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_IsSemTaken), (16 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_IsSemTaken), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_Release), (18 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_Release), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_ReleaseAll), (18 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_ReleaseAll), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_SetClearKey), (18 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_SetClearKey), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_GetClearKey), (14 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_GetClearKey), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_ActivateNotification), (16 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_ActivateNotification), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_DeactivateNotification), (18 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_DeactivateNotification), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_IRQHandler), (26 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_hsem.o(.text.HAL_HSEM_FreeCallback), (2 bytes). + Removing stm32h7xx_hal_hsem.o(.ARM.exidx.text.HAL_HSEM_FreeCallback), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text), (0 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_Init), (1432 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Init), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.DMA_CheckFifoParam), (80 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.DMA_CheckFifoParam), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift), (284 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.DMA_CalcBaseAndBitshift), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.DMA_CalcDMAMUXChannelBaseAndMask), (236 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.DMA_CalcDMAMUXChannelBaseAndMask), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.DMA_CalcDMAMUXRequestGenBaseAndMask), (174 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.DMA_CalcDMAMUXRequestGenBaseAndMask), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_DeInit), (704 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_DeInit), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_Start), (510 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.DMA_SetConfig), (750 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.DMA_SetConfig), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_Start_IT), (1120 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start_IT), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort), (1470 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_Abort_IT), (686 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort_IT), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_PollForTransfer), (1640 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_PollForTransfer), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_IRQHandler), (2976 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_RegisterCallback), (90 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_RegisterCallback), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_UnRegisterCallback), (110 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_UnRegisterCallback), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_GetState), (6 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetState), (8 bytes). + Removing stm32h7xx_hal_dma.o(.text.HAL_DMA_GetError), (4 bytes). + Removing stm32h7xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetError), (8 bytes). + Removing stm32h7xx_hal_dma_ex.o(.text), (0 bytes). + Removing stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart), (914 bytes). + Removing stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_MultiBufferStart), (8 bytes). + Removing stm32h7xx_hal_dma_ex.o(.text.DMA_MultiBufferSetConfig), (288 bytes). + Removing stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.DMA_MultiBufferSetConfig), (8 bytes). + Removing stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart_IT), (1534 bytes). + Removing stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_MultiBufferStart_IT), (8 bytes). + Removing stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_ChangeMemory), (252 bytes). + Removing stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ChangeMemory), (8 bytes). + Removing stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigMuxSync), (112 bytes). + Removing stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigMuxSync), (8 bytes). + Removing stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigMuxRequestGenerator), (82 bytes). + Removing stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigMuxRequestGenerator), (8 bytes). + Removing stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_EnableMuxRequestGenerator), (26 bytes). + Removing stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_EnableMuxRequestGenerator), (8 bytes). + Removing stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_DisableMuxRequestGenerator), (26 bytes). + Removing stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_DisableMuxRequestGenerator), (8 bytes). + Removing stm32h7xx_hal_dma_ex.o(.text.HAL_DMAEx_MUX_IRQHandler), (94 bytes). + Removing stm32h7xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_MUX_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text), (0 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Init), (92 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_Init), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.MDMA_Init), (156 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.MDMA_Init), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_DeInit), (62 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_DeInit), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_ConfigPostRequestMask), (96 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_ConfigPostRequestMask), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_RegisterCallback), (84 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_RegisterCallback), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_UnRegisterCallback), (110 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_UnRegisterCallback), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_LinkedList_CreateNode), (252 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_LinkedList_CreateNode), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_LinkedList_AddNode), (260 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_LinkedList_AddNode), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_LinkedList_RemoveNode), (222 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_LinkedList_RemoveNode), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_LinkedList_EnableCircularMode), (90 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_LinkedList_EnableCircularMode), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_LinkedList_DisableCircularMode), (86 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_LinkedList_DisableCircularMode), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Start), (122 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_Start), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.MDMA_SetConfig), (122 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.MDMA_SetConfig), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Start_IT), (168 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_Start_IT), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Abort), (114 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_Abort), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_Abort_IT), (42 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_Abort_IT), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_PollForTransfer), (280 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_PollForTransfer), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_GenerateSWRequest), (54 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_GenerateSWRequest), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_IRQHandler), (426 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_GetState), (6 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_GetState), (8 bytes). + Removing stm32h7xx_hal_mdma.o(.text.HAL_MDMA_GetError), (4 bytes). + Removing stm32h7xx_hal_mdma.o(.ARM.exidx.text.HAL_MDMA_GetError), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text), (0 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_DeInit), (2 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DeInit), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnableBkUpAccess), (18 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableBkUpAccess), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_DisableBkUpAccess), (18 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableBkUpAccess), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_ConfigPVD), (144 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_ConfigPVD), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnablePVD), (18 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnablePVD), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_DisablePVD), (18 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisablePVD), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnableWakeUpPin), (26 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableWakeUpPin), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_DisableWakeUpPin), (24 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableWakeUpPin), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnterSLEEPMode), (28 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSLEEPMode), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnterSTOPMode), (84 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTOPMode), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnterSTANDBYMode), (52 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTANDBYMode), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnableSleepOnExit), (18 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSleepOnExit), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_DisableSleepOnExit), (18 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSleepOnExit), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_EnableSEVOnPend), (18 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSEVOnPend), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_DisableSEVOnPend), (18 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSEVOnPend), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_PVD_IRQHandler), (30 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVD_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_pwr.o(.text.HAL_PWR_PVDCallback), (2 bytes). + Removing stm32h7xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVDCallback), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text), (0 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ConfigSupply), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetSupplyConfig), (16 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetSupplyConfig), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlVoltageScaling), (62 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ControlVoltageScaling), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetVoltageRange), (16 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetVoltageRange), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlStopModeVoltageScaling), (24 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ControlStopModeVoltageScaling), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetStopModeVoltageRange), (16 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetStopModeVoltageRange), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnterSTOPMode), (112 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnterSTOPMode), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ClearPendingEvent), (4 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ClearPendingEvent), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnterSTANDBYMode), (78 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnterSTANDBYMode), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigD3Domain), (20 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ConfigD3Domain), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableFlashPowerDown), (18 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableFlashPowerDown), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableFlashPowerDown), (18 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableFlashPowerDown), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableWakeUpPin), (116 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableWakeUpPin), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableWakeUpPin), (18 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableWakeUpPin), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetWakeupFlag), (14 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetWakeupFlag), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ClearWakeupFlag), (24 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ClearWakeupFlag), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WAKEUP_PIN_IRQHandler), (82 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_WAKEUP_PIN_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP1_Callback), (2 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_WKUP1_Callback), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP2_Callback), (2 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_WKUP2_Callback), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP4_Callback), (2 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_WKUP4_Callback), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_WKUP6_Callback), (2 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_WKUP6_Callback), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBkUpReg), (50 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableBkUpReg), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBkUpReg), (50 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableBkUpReg), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUSBReg), (50 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableUSBReg), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUSBReg), (50 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableUSBReg), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUSBVoltageDetector), (18 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableUSBVoltageDetector), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUSBVoltageDetector), (18 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableUSBVoltageDetector), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBatteryCharging), (28 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableBatteryCharging), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBatteryCharging), (18 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableBatteryCharging), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableMonitoring), (18 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableMonitoring), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableMonitoring), (18 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableMonitoring), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetTemperatureLevel), (36 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetTemperatureLevel), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_GetVBATLevel), (36 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetVBATLevel), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigAVD), (142 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ConfigAVD), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableAVD), (18 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableAVD), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableAVD), (18 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableAVD), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_IRQHandler), (88 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_PVD_AVD_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_AVDCallback), (2 bytes). + Removing stm32h7xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_AVDCallback), (8 bytes). + Removing stm32h7xx_hal.o(.text), (0 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_Init), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_InitTick), (84 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_InitTick), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_MspInit), (2 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_MspInit), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_DeInit), (122 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_DeInit), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_MspDeInit), (2 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_MspDeInit), (8 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_IncTick), (8 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetTick), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_GetTickPrio), (12 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetTickPrio), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SetTickFreq), (44 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SetTickFreq), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_GetTickFreq), (12 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetTickFreq), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_Delay), (40 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_Delay), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SuspendTick), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SuspendTick), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_ResumeTick), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_ResumeTick), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_GetHalVersion), (10 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetHalVersion), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_GetREVID), (14 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetREVID), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_GetDEVID), (16 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetDEVID), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_GetUIDw0), (12 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetUIDw0), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_GetUIDw1), (12 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetUIDw1), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_GetUIDw2), (12 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetUIDw2), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_VREFBUF_VoltageScalingConfig), (20 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_VREFBUF_VoltageScalingConfig), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_VREFBUF_HighImpedanceConfig), (20 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_VREFBUF_HighImpedanceConfig), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_VREFBUF_TrimmingConfig), (20 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_VREFBUF_TrimmingConfig), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_EnableVREFBUF), (48 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_EnableVREFBUF), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_DisableVREFBUF), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_DisableVREFBUF), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_ETHInterfaceSelect), (20 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_ETHInterfaceSelect), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_AnalogSwitchConfig), (20 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_AnalogSwitchConfig), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_EnableBOOST), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_EnableBOOST), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_DisableBOOST), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_DisableBOOST), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_CM7BootAddConfig), (32 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_CM7BootAddConfig), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_EnableCompensationCell), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_EnableCompensationCell), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_DisableCompensationCell), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_DisableCompensationCell), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_EnableIOSpeedOptimize), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_EnableIOSpeedOptimize), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_DisableIOSpeedOptimize), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_DisableIOSpeedOptimize), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_CompensationCodeSelect), (20 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_CompensationCodeSelect), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_CompensationCodeConfig), (24 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_CompensationCodeConfig), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_ADC2ALT_Rout0Config), (20 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_ADC2ALT_Rout0Config), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SYSCFG_ADC2ALT_Rout1Config), (20 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SYSCFG_ADC2ALT_Rout1Config), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_DBGMCU_EnableDBGSleepMode), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGSleepMode), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_DBGMCU_DisableDBGSleepMode), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGSleepMode), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_DBGMCU_EnableDBGStopMode), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStopMode), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_DBGMCU_DisableDBGStopMode), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStopMode), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_DBGMCU_EnableDBGStandbyMode), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStandbyMode), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_DBGMCU_DisableDBGStandbyMode), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStandbyMode), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_EnableDomain3DBGStopMode), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_EnableDomain3DBGStopMode), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_DisableDomain3DBGStopMode), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_DisableDomain3DBGStopMode), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_EnableDomain3DBGStandbyMode), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_EnableDomain3DBGStandbyMode), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_DisableDomain3DBGStandbyMode), (18 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_DisableDomain3DBGStandbyMode), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_SetFMCMemorySwappingConfig), (20 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_SetFMCMemorySwappingConfig), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_GetFMCMemorySwappingConfig), (16 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_GetFMCMemorySwappingConfig), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_EXTI_EdgeConfig), (82 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_EXTI_EdgeConfig), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_EXTI_GenerateSWInterrupt), (28 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_EXTI_GenerateSWInterrupt), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_EXTI_D1_ClearFlag), (26 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_EXTI_D1_ClearFlag), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_EXTI_D1_EventInputConfig), (100 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_EXTI_D1_EventInputConfig), (8 bytes). + Removing stm32h7xx_hal.o(.text.HAL_EXTI_D3_EventInputConfig), (102 bytes). + Removing stm32h7xx_hal.o(.ARM.exidx.text.HAL_EXTI_D3_EventInputConfig), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text), (0 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Init), (166 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Init), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_MspInit), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MspInit), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_DeInit), (52 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_DeInit), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_MspDeInit), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MspDeInit), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit), (340 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout), (156 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnFlagUntilTimeout), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_TransferConfig), (46 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_TransferConfig), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_WaitOnTXISFlagUntilTimeout), (108 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnTXISFlagUntilTimeout), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout), (100 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnSTOPFlagUntilTimeout), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive), (328 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout), (232 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnRXNEFlagUntilTimeout), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit), (440 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_Flush_TXDR), (30 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Flush_TXDR), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive), (342 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_IT), (180 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_IT), (292 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Master_ISR_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_Enable_IRQ), (110 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Enable_IRQ), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_IT), (146 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_IT), (134 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_IT), (248 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Slave_ISR_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_IT), (96 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA), (352 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_Master_ISR_DMA), (262 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Master_ISR_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterTransmitCplt), (74 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAMasterTransmitCplt), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_DMAError), (504 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAError), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA), (314 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_DMAMasterReceiveCplt), (74 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAMasterReceiveCplt), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA), (288 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_Slave_ISR_DMA), (740 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Slave_ISR_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_DMASlaveTransmitCplt), (32 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMASlaveTransmitCplt), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA), (228 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_DMASlaveReceiveCplt), (258 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMASlaveReceiveCplt), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write), (374 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryWrite), (116 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_RequestMemoryWrite), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read), (390 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_RequestMemoryRead), (114 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_RequestMemoryRead), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_IT), (188 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_IT), (320 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Mem_ISR_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_IT), (184 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA), (292 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_Mem_ISR_DMA), (310 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Mem_ISR_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA), (284 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_IsDeviceReady), (296 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_IsDeviceReady), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_IT), (226 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Transmit_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_ConvertOtherXferOptions), (30 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ConvertOtherXferOptions), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA), (396 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Transmit_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_IT), (174 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Receive_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA), (350 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Receive_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_IT), (220 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Transmit_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_Disable_IRQ), (94 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_Disable_IRQ), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_DMAAbort), (30 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAAbort), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA), (374 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Transmit_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_IT), (220 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Receive_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA), (376 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Receive_DMA), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_EnableListen_IT), (42 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_EnableListen_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_DisableListen_IT), (58 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_DisableListen_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_Master_Abort_IT), (124 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Abort_IT), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler), (20 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_EV_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_ER_IRQHandler), (100 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ER_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_ITError), (280 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITError), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_MasterTxCpltCallback), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MasterTxCpltCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_MasterRxCpltCallback), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MasterRxCpltCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_SlaveTxCpltCallback), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_SlaveTxCpltCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_SlaveRxCpltCallback), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_SlaveRxCpltCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_AddrCallback), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_AddrCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_ListenCpltCallback), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ListenCpltCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_MemTxCpltCallback), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MemTxCpltCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_MemRxCpltCallback), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MemRxCpltCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_ErrorCallback), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ErrorCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_AbortCpltCallback), (2 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_AbortCpltCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_GetState), (6 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetState), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_GetMode), (6 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetMode), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.HAL_I2C_GetError), (4 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetError), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_ITMasterSeqCplt), (78 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITMasterSeqCplt), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_ITMasterCplt), (246 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITMasterCplt), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveCplt), (878 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITSlaveCplt), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_ITListenCplt), (96 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITListenCplt), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_ITSlaveSeqCplt), (122 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITSlaveSeqCplt), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_ITAddrCplt), (156 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_ITAddrCplt), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_TreatErrorCallback), (44 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_TreatErrorCallback), (8 bytes). + Removing stm32h7xx_hal_i2c.o(.text.I2C_IsErrorOccurred), (298 bytes). + Removing stm32h7xx_hal_i2c.o(.ARM.exidx.text.I2C_IsErrorOccurred), (8 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.text), (0 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_ConfigAnalogFilter), (74 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_ConfigAnalogFilter), (8 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_ConfigDigitalFilter), (72 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_ConfigDigitalFilter), (8 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_EnableWakeUp), (68 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_EnableWakeUp), (8 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_DisableWakeUp), (68 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_DisableWakeUp), (8 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_EnableFastModePlus), (46 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_EnableFastModePlus), (8 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.text.HAL_I2CEx_DisableFastModePlus), (48 bytes). + Removing stm32h7xx_hal_i2c_ex.o(.ARM.exidx.text.HAL_I2CEx_DisableFastModePlus), (8 bytes). + Removing stm32h7xx_hal_exti.o(.text), (0 bytes). + Removing stm32h7xx_hal_exti.o(.text.HAL_EXTI_SetConfigLine), (300 bytes). + Removing stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_SetConfigLine), (8 bytes). + Removing stm32h7xx_hal_exti.o(.text.HAL_EXTI_GetConfigLine), (234 bytes). + Removing stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetConfigLine), (8 bytes). + Removing stm32h7xx_hal_exti.o(.text.HAL_EXTI_ClearConfigLine), (216 bytes). + Removing stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearConfigLine), (8 bytes). + Removing stm32h7xx_hal_exti.o(.text.HAL_EXTI_RegisterCallback), (20 bytes). + Removing stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_RegisterCallback), (8 bytes). + Removing stm32h7xx_hal_exti.o(.text.HAL_EXTI_GetHandle), (12 bytes). + Removing stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetHandle), (8 bytes). + Removing stm32h7xx_hal_exti.o(.text.HAL_EXTI_IRQHandler), (54 bytes). + Removing stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_IRQHandler), (8 bytes). + Removing stm32h7xx_hal_exti.o(.text.HAL_EXTI_GetPending), (30 bytes). + Removing stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetPending), (8 bytes). + Removing stm32h7xx_hal_exti.o(.text.HAL_EXTI_ClearPending), (26 bytes). + Removing stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearPending), (8 bytes). + Removing stm32h7xx_hal_exti.o(.text.HAL_EXTI_GenerateSWI), (26 bytes). + Removing stm32h7xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GenerateSWI), (8 bytes). + Removing system_stm32h7xx.o(.text), (0 bytes). + Removing system_stm32h7xx.o(.ARM.exidx.text.SystemInit), (8 bytes). + Removing system_stm32h7xx.o(.text.SystemCoreClockUpdate), (320 bytes). + Removing system_stm32h7xx.o(.ARM.exidx.text.SystemCoreClockUpdate), (8 bytes). + Removing system_stm32h7xx.o(.ARM.exidx.text.ExitRun0Mode), (8 bytes). + +1327 unused section(s) (total 80794 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_copy.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/scatter.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch_hlt.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE + ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memclr_w.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE + ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE + ../fplib/fpinit.s 0x00000000 Number 0 fpinit.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + fdcan.c 0x00000000 Number 0 fdcan.o ABSOLUTE + gpio.c 0x00000000 Number 0 gpio.o ABSOLUTE + main.c 0x00000000 Number 0 main.o ABSOLUTE + startup_stm32h723xx.s 0x00000000 Number 0 startup_stm32h723xx.o ABSOLUTE + stm32h7xx_hal.c 0x00000000 Number 0 stm32h7xx_hal.o ABSOLUTE + stm32h7xx_hal_cortex.c 0x00000000 Number 0 stm32h7xx_hal_cortex.o ABSOLUTE + stm32h7xx_hal_dma.c 0x00000000 Number 0 stm32h7xx_hal_dma.o ABSOLUTE + stm32h7xx_hal_dma_ex.c 0x00000000 Number 0 stm32h7xx_hal_dma_ex.o ABSOLUTE + stm32h7xx_hal_exti.c 0x00000000 Number 0 stm32h7xx_hal_exti.o ABSOLUTE + stm32h7xx_hal_fdcan.c 0x00000000 Number 0 stm32h7xx_hal_fdcan.o ABSOLUTE + stm32h7xx_hal_flash.c 0x00000000 Number 0 stm32h7xx_hal_flash.o ABSOLUTE + stm32h7xx_hal_flash_ex.c 0x00000000 Number 0 stm32h7xx_hal_flash_ex.o ABSOLUTE + stm32h7xx_hal_gpio.c 0x00000000 Number 0 stm32h7xx_hal_gpio.o ABSOLUTE + stm32h7xx_hal_hsem.c 0x00000000 Number 0 stm32h7xx_hal_hsem.o ABSOLUTE + stm32h7xx_hal_i2c.c 0x00000000 Number 0 stm32h7xx_hal_i2c.o ABSOLUTE + stm32h7xx_hal_i2c_ex.c 0x00000000 Number 0 stm32h7xx_hal_i2c_ex.o ABSOLUTE + stm32h7xx_hal_mdma.c 0x00000000 Number 0 stm32h7xx_hal_mdma.o ABSOLUTE + stm32h7xx_hal_msp.c 0x00000000 Number 0 stm32h7xx_hal_msp.o ABSOLUTE + stm32h7xx_hal_pwr.c 0x00000000 Number 0 stm32h7xx_hal_pwr.o ABSOLUTE + stm32h7xx_hal_pwr_ex.c 0x00000000 Number 0 stm32h7xx_hal_pwr_ex.o ABSOLUTE + stm32h7xx_hal_rcc.c 0x00000000 Number 0 stm32h7xx_hal_rcc.o ABSOLUTE + stm32h7xx_hal_rcc_ex.c 0x00000000 Number 0 stm32h7xx_hal_rcc_ex.o ABSOLUTE + stm32h7xx_hal_tim.c 0x00000000 Number 0 stm32h7xx_hal_tim.o ABSOLUTE + stm32h7xx_hal_tim_ex.c 0x00000000 Number 0 stm32h7xx_hal_tim_ex.o ABSOLUTE + stm32h7xx_hal_timebase_tim.c 0x00000000 Number 0 stm32h7xx_hal_timebase_tim.o ABSOLUTE + stm32h7xx_it.c 0x00000000 Number 0 stm32h7xx_it.o ABSOLUTE + system_stm32h7xx.c 0x00000000 Number 0 system_stm32h7xx.o ABSOLUTE + RESET 0x08000000 Section 716 startup_stm32h723xx.o(RESET) + !!!main 0x080002cc Section 8 __main.o(!!!main) + !!!scatter 0x080002d4 Section 52 __scatter.o(!!!scatter) + !!handler_copy 0x08000308 Section 26 __scatter_copy.o(!!handler_copy) + !!handler_zi 0x08000324 Section 28 __scatter_zi.o(!!handler_zi) + .ARM.Collect$$libinit$$00000000 0x08000340 Section 2 libinit.o(.ARM.Collect$$libinit$$00000000) + .ARM.Collect$$libinit$$00000001 0x08000342 Section 4 libinit2.o(.ARM.Collect$$libinit$$00000001) + .ARM.Collect$$libinit$$00000004 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + .ARM.Collect$$libinit$$0000000A 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + .ARM.Collect$$libinit$$0000000C 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + .ARM.Collect$$libinit$$0000000E 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + .ARM.Collect$$libinit$$00000011 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + .ARM.Collect$$libinit$$00000013 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + .ARM.Collect$$libinit$$00000015 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + .ARM.Collect$$libinit$$00000017 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + .ARM.Collect$$libinit$$00000019 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + .ARM.Collect$$libinit$$0000001B 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + .ARM.Collect$$libinit$$0000001D 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + .ARM.Collect$$libinit$$0000001F 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + .ARM.Collect$$libinit$$00000021 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + .ARM.Collect$$libinit$$00000023 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + .ARM.Collect$$libinit$$00000025 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + .ARM.Collect$$libinit$$0000002C 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + .ARM.Collect$$libinit$$0000002E 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + .ARM.Collect$$libinit$$00000030 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + .ARM.Collect$$libinit$$00000032 0x08000346 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + .ARM.Collect$$libinit$$00000033 0x08000346 Section 2 libinit2.o(.ARM.Collect$$libinit$$00000033) + .ARM.Collect$$libshutdown$$00000000 0x08000348 Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + .ARM.Collect$$libshutdown$$00000002 0x0800034a Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + .ARM.Collect$$libshutdown$$00000004 0x0800034a Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + .ARM.Collect$$libshutdown$$00000007 0x0800034a Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + .ARM.Collect$$libshutdown$$0000000A 0x0800034a Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + .ARM.Collect$$libshutdown$$0000000C 0x0800034a Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + .ARM.Collect$$libshutdown$$0000000F 0x0800034a Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + .ARM.Collect$$libshutdown$$00000010 0x0800034a Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + .ARM.Collect$$rtentry$$00000000 0x0800034c Section 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + .ARM.Collect$$rtentry$$00000002 0x0800034c Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + .ARM.Collect$$rtentry$$00000004 0x0800034c Section 6 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + .ARM.Collect$$rtentry$$00000009 0x08000352 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + .ARM.Collect$$rtentry$$0000000A 0x08000352 Section 4 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + .ARM.Collect$$rtentry$$0000000C 0x08000356 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + .ARM.Collect$$rtentry$$0000000D 0x08000356 Section 8 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + .ARM.Collect$$rtexit$$00000000 0x0800035e Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000) + .ARM.Collect$$rtexit$$00000002 0x08000360 Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + .ARM.Collect$$rtexit$$00000003 0x08000360 Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + .ARM.Collect$$rtexit$$00000004 0x08000364 Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + $v0 0x0800036c Number 0 startup_stm32h723xx.o(.text) + .text 0x0800036c Section 72 startup_stm32h723xx.o(.text) + .text 0x080003b4 Section 78 rt_memclr_w.o(.text) + .text 0x08000402 Section 0 heapauxi.o(.text) + .text 0x08000408 Section 74 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startup_stm32h723xx.o(.text) + BDMA_Channel0_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + BDMA_Channel1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + BDMA_Channel2_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + BDMA_Channel3_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + BDMA_Channel4_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + BDMA_Channel5_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + BDMA_Channel6_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + BDMA_Channel7_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + CEC_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + COMP1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + CORDIC_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + CRS_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DCMI_PSSI_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DFSDM1_FLT0_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DFSDM1_FLT1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DFSDM1_FLT2_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DFSDM1_FLT3_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA1_Stream0_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA1_Stream1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA1_Stream2_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA1_Stream3_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA1_Stream4_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA1_Stream5_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA1_Stream6_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA1_Stream7_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA2D_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA2_Stream0_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA2_Stream1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA2_Stream2_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA2_Stream3_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA2_Stream4_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA2_Stream5_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA2_Stream6_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMA2_Stream7_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMAMUX1_OVR_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DMAMUX2_OVR_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + DTS_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + ECC_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + ETH_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + ETH_WKUP_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + EXTI0_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + EXTI15_10_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + EXTI1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + EXTI2_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + EXTI3_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + EXTI4_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + EXTI9_5_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + FDCAN1_IT1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + FDCAN2_IT0_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + FDCAN2_IT1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + FDCAN3_IT0_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + FDCAN3_IT1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + FDCAN_CAL_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + FLASH_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + FMAC_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + FMC_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + FPU_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + HSEM1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + I2C1_ER_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + I2C1_EV_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + I2C2_ER_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + I2C2_EV_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + I2C3_ER_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + I2C3_EV_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + I2C4_ER_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + I2C4_EV_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + I2C5_ER_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + I2C5_EV_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + LPTIM1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + LPTIM2_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + LPTIM3_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + LPTIM4_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + LPTIM5_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + LPUART1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + LTDC_ER_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + LTDC_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + MDIOS_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + MDIOS_WKUP_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + MDMA_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + OCTOSPI1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + OCTOSPI2_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + OTG_HS_EP1_IN_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + OTG_HS_EP1_OUT_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + OTG_HS_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + OTG_HS_WKUP_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + PVD_AVD_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + RCC_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + RNG_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + RTC_Alarm_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + RTC_WKUP_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SAI1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SAI4_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SDMMC1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SDMMC2_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SPDIF_RX_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SPI1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SPI2_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SPI3_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SPI4_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SPI5_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SPI6_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + SWPMI1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TAMP_STAMP_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM15_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM16_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM17_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM1_BRK_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM1_CC_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM1_TRG_COM_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM1_UP_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM23_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM24_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM3_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM4_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM5_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM6_DAC_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM7_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM8_BRK_TIM12_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM8_CC_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM8_TRG_COM_TIM14_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + TIM8_UP_TIM13_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + UART4_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + UART5_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + UART7_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + UART8_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + UART9_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + USART10_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + USART1_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + USART2_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + USART3_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + USART6_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + WAKEUP_PIN_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + WWDG_IRQHandler 0x0800038b Thumb Code 0 startup_stm32h723xx.o(.text) + __user_initial_stackheap 0x0800038d Thumb Code 0 startup_stm32h723xx.o(.text) + __aeabi_memclr4 0x080003b5 Thumb Code 0 rt_memclr_w.o(.text) + __aeabi_memclr8 0x080003b5 Thumb Code 0 rt_memclr_w.o(.text) + __rt_memclr_w 0x080003b5 Thumb Code 0 rt_memclr_w.o(.text) + _memset_w 0x080003b9 Thumb Code 74 rt_memclr_w.o(.text) + __use_two_region_memory 0x08000403 Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x08000405 Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x08000407 Thumb Code 2 heapauxi.o(.text) + __user_setup_stackheap 0x08000409 Thumb Code 74 sys_stackheap_outer.o(.text) + exit 0x08000453 Thumb Code 18 exit.o(.text) + __user_libspace 0x08000465 Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x08000465 Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x08000465 Thumb Code 0 libspace.o(.text) + _sys_exit 0x0800046d Thumb Code 8 sys_exit.o(.text) + __I$use$semihosting 0x08000479 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x08000479 Thumb Code 2 use_no_semi.o(.text) + __semihosting_library_function 0x0800047b Thumb Code 0 indicate_semi.o(.text) + BusFault_Handler 0x08000481 Thumb Code 2 stm32h7xx_it.o(.text.BusFault_Handler) + DebugMon_Handler 0x08000489 Thumb Code 2 stm32h7xx_it.o(.text.DebugMon_Handler) + Error_Handler 0x08000491 Thumb Code 10 main.o(.text.Error_Handler) + ExitRun0Mode 0x080004a1 Thumb Code 26 system_stm32h7xx.o(.text.ExitRun0Mode) + FDCAN1_IT0_IRQHandler 0x080004c1 Thumb Code 16 stm32h7xx_it.o(.text.FDCAN1_IT0_IRQHandler) + HAL_FDCAN_ClockCalibrationCallback 0x08000699 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ClockCalibrationCallback) + HAL_FDCAN_ErrorCallback 0x080006a1 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ErrorCallback) + HAL_FDCAN_ErrorStatusCallback 0x080006a9 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_ErrorStatusCallback) + HAL_FDCAN_HighPriorityMessageCallback 0x080006b1 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_HighPriorityMessageCallback) + HAL_FDCAN_IRQHandler 0x080006b9 Thumb Code 754 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_IRQHandler) + HAL_FDCAN_Init 0x080009b1 Thumb Code 534 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_Init) + HAL_FDCAN_MspInit 0x08000bc9 Thumb Code 166 fdcan.o(.text.HAL_FDCAN_MspInit) + HAL_FDCAN_RxBufferNewMessageCallback 0x08000c71 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxBufferNewMessageCallback) + HAL_FDCAN_RxFifo0Callback 0x08000c79 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxFifo0Callback) + HAL_FDCAN_RxFifo1Callback 0x08000c81 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_RxFifo1Callback) + HAL_FDCAN_TT_GlobalTimeCallback 0x08000c89 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_GlobalTimeCallback) + HAL_FDCAN_TT_ScheduleSyncCallback 0x08000c91 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_ScheduleSyncCallback) + HAL_FDCAN_TT_StopWatchCallback 0x08000c99 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_StopWatchCallback) + HAL_FDCAN_TT_TimeMarkCallback 0x08000ca1 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TT_TimeMarkCallback) + HAL_FDCAN_TimeoutOccurredCallback 0x08000ca9 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TimeoutOccurredCallback) + HAL_FDCAN_TimestampWraparoundCallback 0x08000cb1 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TimestampWraparoundCallback) + HAL_FDCAN_TxBufferAbortCallback 0x08000cb9 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxBufferAbortCallback) + HAL_FDCAN_TxBufferCompleteCallback 0x08000cc1 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxBufferCompleteCallback) + HAL_FDCAN_TxEventFifoCallback 0x08000cc9 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxEventFifoCallback) + HAL_FDCAN_TxFifoEmptyCallback 0x08000cd1 Thumb Code 2 stm32h7xx_hal_fdcan.o(.text.HAL_FDCAN_TxFifoEmptyCallback) + HAL_GPIO_Init 0x08000cd9 Thumb Code 416 stm32h7xx_hal_gpio.o(.text.HAL_GPIO_Init) + HAL_GetTick 0x08000e79 Thumb Code 12 stm32h7xx_hal.o(.text.HAL_GetTick) + HAL_IncTick 0x08000e89 Thumb Code 26 stm32h7xx_hal.o(.text.HAL_IncTick) + HAL_Init 0x08000ea9 Thumb Code 100 stm32h7xx_hal.o(.text.HAL_Init) + HAL_InitTick 0x08000f11 Thumb Code 160 stm32h7xx_hal_timebase_tim.o(.text.HAL_InitTick) + HAL_MspInit 0x08000fb1 Thumb Code 32 stm32h7xx_hal_msp.o(.text.HAL_MspInit) + HAL_NVIC_EnableIRQ 0x08000fd1 Thumb Code 8 stm32h7xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) + HAL_NVIC_SetPriority 0x08000fd9 Thumb Code 30 stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) + HAL_NVIC_SetPriorityGrouping 0x08000ff9 Thumb Code 8 stm32h7xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) + HAL_PWREx_ConfigSupply 0x08001001 Thumb Code 72 stm32h7xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigSupply) + HAL_RCCEx_PeriphCLKConfig 0x08001049 Thumb Code 2436 stm32h7xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) + HAL_RCC_ClockConfig 0x080019d1 Thumb Code 596 stm32h7xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) + HAL_RCC_GetClockConfig 0x08001c29 Thumb Code 88 stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig) + HAL_RCC_GetHCLKFreq 0x08001c81 Thumb Code 76 stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) + HAL_RCC_GetPCLK1Freq 0x08001cd1 Thumb Code 38 stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) + HAL_RCC_GetSysClockFreq 0x08001cf9 Thumb Code 264 stm32h7xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) + HAL_RCC_OscConfig 0x08001e01 Thumb Code 1562 stm32h7xx_hal_rcc.o(.text.HAL_RCC_OscConfig) + HAL_TIMEx_Break2Callback 0x08002421 Thumb Code 2 stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback) + HAL_TIMEx_BreakCallback 0x08002429 Thumb Code 2 stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback) + HAL_TIMEx_CommutCallback 0x08002431 Thumb Code 2 stm32h7xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) + HAL_TIM_Base_Init 0x08002439 Thumb Code 96 stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Init) + HAL_TIM_Base_MspInit 0x08002499 Thumb Code 2 stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_MspInit) + HAL_TIM_Base_Start_IT 0x080024a1 Thumb Code 198 stm32h7xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT) + HAL_TIM_IC_CaptureCallback 0x08002569 Thumb Code 2 stm32h7xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) + HAL_TIM_IRQHandler 0x08002571 Thumb Code 346 stm32h7xx_hal_tim.o(.text.HAL_TIM_IRQHandler) + HAL_TIM_OC_DelayElapsedCallback 0x080026d1 Thumb Code 2 stm32h7xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback) + HAL_TIM_PWM_PulseFinishedCallback 0x080026d9 Thumb Code 2 stm32h7xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) + HAL_TIM_PeriodElapsedCallback 0x080026e1 Thumb Code 18 main.o(.text.HAL_TIM_PeriodElapsedCallback) + HAL_TIM_TriggerCallback 0x080026f9 Thumb Code 2 stm32h7xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) + HardFault_Handler 0x08002701 Thumb Code 2 stm32h7xx_it.o(.text.HardFault_Handler) + MX_FDCAN1_Init 0x08002709 Thumb Code 108 fdcan.o(.text.MX_FDCAN1_Init) + MX_GPIO_Init 0x08002779 Thumb Code 50 gpio.o(.text.MX_GPIO_Init) + MemManage_Handler 0x080027b1 Thumb Code 2 stm32h7xx_it.o(.text.MemManage_Handler) + NMI_Handler 0x080027b9 Thumb Code 2 stm32h7xx_it.o(.text.NMI_Handler) + PendSV_Handler 0x080027f1 Thumb Code 2 stm32h7xx_it.o(.text.PendSV_Handler) + SVC_Handler 0x08002a39 Thumb Code 2 stm32h7xx_it.o(.text.SVC_Handler) + SysTick_Handler 0x08002a41 Thumb Code 2 stm32h7xx_it.o(.text.SysTick_Handler) + SystemClock_Config 0x08002a49 Thumb Code 166 main.o(.text.SystemClock_Config) + SystemInit 0x08002af1 Thumb Code 210 system_stm32h7xx.o(.text.SystemInit) + TIM2_IRQHandler 0x08002bc9 Thumb Code 16 stm32h7xx_it.o(.text.TIM2_IRQHandler) + TIM_Base_SetConfig 0x08002bd9 Thumb Code 346 stm32h7xx_hal_tim.o(.text.TIM_Base_SetConfig) + UsageFault_Handler 0x08002d39 Thumb Code 2 stm32h7xx_it.o(.text.UsageFault_Handler) + main 0x08002db9 Thumb Code 18 main.o(.text.main) + _fp_init 0x08002dcb Thumb Code 26 fpinit.o(x$fpl$fpinit) + __fplib_config_fpu_vfp 0x08002de3 Thumb Code 0 fpinit.o(x$fpl$fpinit) + __fplib_config_pureend_doubles 0x08002de3 Thumb Code 0 fpinit.o(x$fpl$fpinit) + D1CorePrescTable 0x08002e30 Data 16 system_stm32h7xx.o(.rodata.D1CorePrescTable) + Region$$Table$$Base 0x08002e40 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08002e60 Number 0 anon$$obj.o(Region$$Table) + SystemCoreClock 0x24000000 Data 4 system_stm32h7xx.o(.data.SystemCoreClock) + SystemD2Clock 0x24000004 Data 4 system_stm32h7xx.o(.data.SystemD2Clock) + uwTickFreq 0x24000008 Data 1 stm32h7xx_hal.o(.data.uwTickFreq) + uwTickPrio 0x2400000c Data 4 stm32h7xx_hal.o(.data.uwTickPrio) + __libspace_start 0x24000010 Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x24000070 Data 0 libspace.o(.bss) + hfdcan1 0x24000070 Data 160 fdcan.o(.bss.hfdcan1) + htim2 0x24000110 Data 76 stm32h7xx_hal_timebase_tim.o(.bss.htim2) + uwTick 0x2400015c Data 4 stm32h7xx_hal.o(.bss.uwTick) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x080002cd + + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00002e70, Max: 0x00100000, ABSOLUTE) + + Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00002e60, Max: 0x00100000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x08000000 0x000002cc Data RO 3 RESET startup_stm32h723xx.o + 0x080002cc 0x080002cc 0x00000008 Code RO 1605 * !!!main c_w.l(__main.o) + 0x080002d4 0x080002d4 0x00000034 Code RO 1768 !!!scatter c_w.l(__scatter.o) + 0x08000308 0x08000308 0x0000001a Code RO 1770 !!handler_copy c_w.l(__scatter_copy.o) + 0x08000322 0x08000322 0x00000002 PAD + 0x08000324 0x08000324 0x0000001c Code RO 1772 !!handler_zi c_w.l(__scatter_zi.o) + 0x08000340 0x08000340 0x00000002 Code RO 1632 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) + 0x08000342 0x08000342 0x00000004 Code RO 1638 .ARM.Collect$$libinit$$00000001 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1641 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1644 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1646 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1648 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1651 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1653 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1655 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1657 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1659 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1661 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1663 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1665 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1667 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1669 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1671 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1675 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1677 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1679 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000000 Code RO 1681 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) + 0x08000346 0x08000346 0x00000002 Code RO 1682 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o) + 0x08000348 0x08000348 0x00000002 Code RO 1704 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) + 0x0800034a 0x0800034a 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0x08000402 0x08000402 0x00000006 Code RO 1603 .text c_w.l(heapauxi.o) + 0x08000408 0x08000408 0x0000004a Code RO 1623 .text c_w.l(sys_stackheap_outer.o) + 0x08000452 0x08000452 0x00000012 Code RO 1625 .text c_w.l(exit.o) + 0x08000464 0x08000464 0x00000008 Code RO 1633 .text c_w.l(libspace.o) + 0x0800046c 0x0800046c 0x0000000c Code RO 1694 .text c_w.l(sys_exit.o) + 0x08000478 0x08000478 0x00000002 Code RO 1709 .text c_w.l(use_no_semi.o) + 0x0800047a 0x0800047a 0x00000000 Code RO 1711 .text c_w.l(indicate_semi.o) + 0x0800047a 0x0800047a 0x00000006 PAD + 0x08000480 0x08000480 0x00000002 Code RO 57 .text.BusFault_Handler stm32h7xx_it.o + 0x08000482 0x08000482 0x00000006 PAD + 0x08000488 0x08000488 0x00000002 Code RO 63 .text.DebugMon_Handler stm32h7xx_it.o + 0x0800048a 0x0800048a 0x00000006 PAD + 0x08000490 0x08000490 0x0000000a Code RO 15 .text.Error_Handler main.o + 0x0800049a 0x0800049a 0x00000006 PAD + 0x080004a0 0x080004a0 0x0000001a Code RO 1587 .text.ExitRun0Mode system_stm32h7xx.o + 0x080004ba 0x080004ba 0x00000006 PAD + 0x080004c0 0x080004c0 0x00000010 Code RO 69 .text.FDCAN1_IT0_IRQHandler stm32h7xx_it.o + 0x080004d0 0x080004d0 0x000001c8 Code RO 539 .text.FDCAN_CalcultateRamBlockAddresses stm32h7xx_hal_fdcan.o + 0x08000698 0x08000698 0x00000002 Code RO 701 .text.HAL_FDCAN_ClockCalibrationCallback stm32h7xx_hal_fdcan.o + 0x0800069a 0x0800069a 0x00000006 PAD + 0x080006a0 0x080006a0 0x00000002 Code RO 729 .text.HAL_FDCAN_ErrorCallback stm32h7xx_hal_fdcan.o + 0x080006a2 0x080006a2 0x00000006 PAD + 0x080006a8 0x080006a8 0x00000002 Code RO 719 .text.HAL_FDCAN_ErrorStatusCallback stm32h7xx_hal_fdcan.o + 0x080006aa 0x080006aa 0x00000006 PAD + 0x080006b0 0x080006b0 0x00000002 Code RO 697 .text.HAL_FDCAN_HighPriorityMessageCallback stm32h7xx_hal_fdcan.o + 0x080006b2 0x080006b2 0x00000006 PAD + 0x080006b8 0x080006b8 0x000002f2 Code RO 695 .text.HAL_FDCAN_IRQHandler stm32h7xx_hal_fdcan.o + 0x080009aa 0x080009aa 0x00000006 PAD + 0x080009b0 0x080009b0 0x00000216 Code RO 535 .text.HAL_FDCAN_Init stm32h7xx_hal_fdcan.o + 0x08000bc6 0x08000bc6 0x00000002 PAD + 0x08000bc8 0x08000bc8 0x000000a6 Code RO 38 .text.HAL_FDCAN_MspInit fdcan.o + 0x08000c6e 0x08000c6e 0x00000002 PAD + 0x08000c70 0x08000c70 0x00000002 Code RO 713 .text.HAL_FDCAN_RxBufferNewMessageCallback stm32h7xx_hal_fdcan.o + 0x08000c72 0x08000c72 0x00000006 PAD + 0x08000c78 0x08000c78 0x00000002 Code RO 705 .text.HAL_FDCAN_RxFifo0Callback stm32h7xx_hal_fdcan.o + 0x08000c7a 0x08000c7a 0x00000006 PAD + 0x08000c80 0x08000c80 0x00000002 Code RO 707 .text.HAL_FDCAN_RxFifo1Callback stm32h7xx_hal_fdcan.o + 0x08000c82 0x08000c82 0x00000006 PAD + 0x08000c88 0x08000c88 0x00000002 Code RO 727 .text.HAL_FDCAN_TT_GlobalTimeCallback stm32h7xx_hal_fdcan.o + 0x08000c8a 0x08000c8a 0x00000006 PAD + 0x08000c90 0x08000c90 0x00000002 Code RO 721 .text.HAL_FDCAN_TT_ScheduleSyncCallback stm32h7xx_hal_fdcan.o + 0x08000c92 0x08000c92 0x00000006 PAD + 0x08000c98 0x08000c98 0x00000002 Code RO 725 .text.HAL_FDCAN_TT_StopWatchCallback stm32h7xx_hal_fdcan.o + 0x08000c9a 0x08000c9a 0x00000006 PAD + 0x08000ca0 0x08000ca0 0x00000002 Code RO 723 .text.HAL_FDCAN_TT_TimeMarkCallback stm32h7xx_hal_fdcan.o + 0x08000ca2 0x08000ca2 0x00000006 PAD + 0x08000ca8 0x08000ca8 0x00000002 Code RO 717 .text.HAL_FDCAN_TimeoutOccurredCallback stm32h7xx_hal_fdcan.o + 0x08000caa 0x08000caa 0x00000006 PAD + 0x08000cb0 0x08000cb0 0x00000002 Code RO 715 .text.HAL_FDCAN_TimestampWraparoundCallback stm32h7xx_hal_fdcan.o + 0x08000cb2 0x08000cb2 0x00000006 PAD + 0x08000cb8 0x08000cb8 0x00000002 Code RO 699 .text.HAL_FDCAN_TxBufferAbortCallback stm32h7xx_hal_fdcan.o + 0x08000cba 0x08000cba 0x00000006 PAD + 0x08000cc0 0x08000cc0 0x00000002 Code RO 711 .text.HAL_FDCAN_TxBufferCompleteCallback stm32h7xx_hal_fdcan.o + 0x08000cc2 0x08000cc2 0x00000006 PAD + 0x08000cc8 0x08000cc8 0x00000002 Code RO 703 .text.HAL_FDCAN_TxEventFifoCallback stm32h7xx_hal_fdcan.o + 0x08000cca 0x08000cca 0x00000006 PAD + 0x08000cd0 0x08000cd0 0x00000002 Code RO 709 .text.HAL_FDCAN_TxFifoEmptyCallback stm32h7xx_hal_fdcan.o + 0x08000cd2 0x08000cd2 0x00000006 PAD + 0x08000cd8 0x08000cd8 0x000001a0 Code RO 950 .text.HAL_GPIO_Init stm32h7xx_hal_gpio.o + 0x08000e78 0x08000e78 0x0000000c Code RO 1260 .text.HAL_GetTick stm32h7xx_hal.o + 0x08000e84 0x08000e84 0x00000004 PAD + 0x08000e88 0x08000e88 0x0000001a Code RO 1258 .text.HAL_IncTick stm32h7xx_hal.o + 0x08000ea2 0x08000ea2 0x00000006 PAD + 0x08000ea8 0x08000ea8 0x00000064 Code RO 1248 .text.HAL_Init stm32h7xx_hal.o + 0x08000f0c 0x08000f0c 0x00000004 PAD + 0x08000f10 0x08000f10 0x000000a0 Code RO 88 .text.HAL_InitTick stm32h7xx_hal_timebase_tim.o + 0x08000fb0 0x08000fb0 0x00000020 Code RO 80 .text.HAL_MspInit stm32h7xx_hal_msp.o + 0x08000fd0 0x08000fd0 0x00000008 Code RO 469 .text.HAL_NVIC_EnableIRQ stm32h7xx_hal_cortex.o + 0x08000fd8 0x08000fd8 0x0000001e Code RO 461 .text.HAL_NVIC_SetPriority stm32h7xx_hal_cortex.o + 0x08000ff6 0x08000ff6 0x00000002 PAD + 0x08000ff8 0x08000ff8 0x00000008 Code RO 457 .text.HAL_NVIC_SetPriorityGrouping stm32h7xx_hal_cortex.o + 0x08001000 0x08001000 0x00000048 Code RO 1164 .text.HAL_PWREx_ConfigSupply stm32h7xx_hal_pwr_ex.o + 0x08001048 0x08001048 0x00000984 Code RO 781 .text.HAL_RCCEx_PeriphCLKConfig stm32h7xx_hal_rcc_ex.o + 0x080019cc 0x080019cc 0x00000004 PAD + 0x080019d0 0x080019d0 0x00000254 Code RO 749 .text.HAL_RCC_ClockConfig stm32h7xx_hal_rcc.o + 0x08001c24 0x08001c24 0x00000004 PAD + 0x08001c28 0x08001c28 0x00000058 Code RO 767 .text.HAL_RCC_GetClockConfig stm32h7xx_hal_rcc.o + 0x08001c80 0x08001c80 0x0000004c Code RO 759 .text.HAL_RCC_GetHCLKFreq stm32h7xx_hal_rcc.o + 0x08001ccc 0x08001ccc 0x00000004 PAD + 0x08001cd0 0x08001cd0 0x00000026 Code RO 761 .text.HAL_RCC_GetPCLK1Freq stm32h7xx_hal_rcc.o + 0x08001cf6 0x08001cf6 0x00000002 PAD + 0x08001cf8 0x08001cf8 0x00000108 Code RO 751 .text.HAL_RCC_GetSysClockFreq stm32h7xx_hal_rcc.o + 0x08001e00 0x08001e00 0x0000061a Code RO 747 .text.HAL_RCC_OscConfig stm32h7xx_hal_rcc.o + 0x0800241a 0x0800241a 0x00000006 PAD + 0x08002420 0x08002420 0x00000002 Code RO 443 .text.HAL_TIMEx_Break2Callback stm32h7xx_hal_tim_ex.o + 0x08002422 0x08002422 0x00000006 PAD + 0x08002428 0x08002428 0x00000002 Code RO 441 .text.HAL_TIMEx_BreakCallback stm32h7xx_hal_tim_ex.o + 0x0800242a 0x0800242a 0x00000006 PAD + 0x08002430 0x08002430 0x00000002 Code RO 437 .text.HAL_TIMEx_CommutCallback stm32h7xx_hal_tim_ex.o + 0x08002432 0x08002432 0x00000006 PAD + 0x08002438 0x08002438 0x00000060 Code RO 103 .text.HAL_TIM_Base_Init stm32h7xx_hal_tim.o + 0x08002498 0x08002498 0x00000002 Code RO 105 .text.HAL_TIM_Base_MspInit stm32h7xx_hal_tim.o + 0x0800249a 0x0800249a 0x00000006 PAD + 0x080024a0 0x080024a0 0x000000c6 Code RO 117 .text.HAL_TIM_Base_Start_IT stm32h7xx_hal_tim.o + 0x08002566 0x08002566 0x00000002 PAD + 0x08002568 0x08002568 0x00000002 Code RO 239 .text.HAL_TIM_IC_CaptureCallback stm32h7xx_hal_tim.o + 0x0800256a 0x0800256a 0x00000006 PAD + 0x08002570 0x08002570 0x0000015a Code RO 237 .text.HAL_TIM_IRQHandler stm32h7xx_hal_tim.o + 0x080026ca 0x080026ca 0x00000006 PAD + 0x080026d0 0x080026d0 0x00000002 Code RO 241 .text.HAL_TIM_OC_DelayElapsedCallback stm32h7xx_hal_tim.o + 0x080026d2 0x080026d2 0x00000006 PAD + 0x080026d8 0x080026d8 0x00000002 Code RO 243 .text.HAL_TIM_PWM_PulseFinishedCallback stm32h7xx_hal_tim.o + 0x080026da 0x080026da 0x00000006 PAD + 0x080026e0 0x080026e0 0x00000012 Code RO 17 .text.HAL_TIM_PeriodElapsedCallback main.o + 0x080026f2 0x080026f2 0x00000006 PAD + 0x080026f8 0x080026f8 0x00000002 Code RO 247 .text.HAL_TIM_TriggerCallback stm32h7xx_hal_tim.o + 0x080026fa 0x080026fa 0x00000006 PAD + 0x08002700 0x08002700 0x00000002 Code RO 53 .text.HardFault_Handler stm32h7xx_it.o + 0x08002702 0x08002702 0x00000006 PAD + 0x08002708 0x08002708 0x0000006c Code RO 36 .text.MX_FDCAN1_Init fdcan.o + 0x08002774 0x08002774 0x00000004 PAD + 0x08002778 0x08002778 0x00000032 Code RO 28 .text.MX_GPIO_Init gpio.o + 0x080027aa 0x080027aa 0x00000006 PAD + 0x080027b0 0x080027b0 0x00000002 Code RO 55 .text.MemManage_Handler stm32h7xx_it.o + 0x080027b2 0x080027b2 0x00000006 PAD + 0x080027b8 0x080027b8 0x00000002 Code RO 51 .text.NMI_Handler stm32h7xx_it.o + 0x080027ba 0x080027ba 0x00000006 PAD + 0x080027c0 0x080027c0 0x0000002e Code RO 467 .text.NVIC_EncodePriority stm32h7xx_hal_cortex.o + 0x080027ee 0x080027ee 0x00000002 PAD + 0x080027f0 0x080027f0 0x00000002 Code RO 65 .text.PendSV_Handler stm32h7xx_it.o + 0x080027f2 0x080027f2 0x00000006 PAD + 0x080027f8 0x080027f8 0x0000011e Code RO 783 .text.RCCEx_PLL2_Config stm32h7xx_hal_rcc_ex.o + 0x08002916 0x08002916 0x00000002 PAD + 0x08002918 0x08002918 0x0000011e Code RO 785 .text.RCCEx_PLL3_Config stm32h7xx_hal_rcc_ex.o + 0x08002a36 0x08002a36 0x00000002 PAD + 0x08002a38 0x08002a38 0x00000002 Code RO 61 .text.SVC_Handler stm32h7xx_it.o + 0x08002a3a 0x08002a3a 0x00000006 PAD + 0x08002a40 0x08002a40 0x00000002 Code RO 67 .text.SysTick_Handler stm32h7xx_it.o + 0x08002a42 0x08002a42 0x00000006 PAD + 0x08002a48 0x08002a48 0x000000a6 Code RO 13 .text.SystemClock_Config main.o + 0x08002aee 0x08002aee 0x00000002 PAD + 0x08002af0 0x08002af0 0x000000d2 Code RO 1583 .text.SystemInit system_stm32h7xx.o + 0x08002bc2 0x08002bc2 0x00000006 PAD + 0x08002bc8 0x08002bc8 0x00000010 Code RO 71 .text.TIM2_IRQHandler stm32h7xx_it.o + 0x08002bd8 0x08002bd8 0x0000015a Code RO 107 .text.TIM_Base_SetConfig stm32h7xx_hal_tim.o + 0x08002d32 0x08002d32 0x00000006 PAD + 0x08002d38 0x08002d38 0x00000002 Code RO 59 .text.UsageFault_Handler stm32h7xx_it.o + 0x08002d3a 0x08002d3a 0x00000006 PAD + 0x08002d40 0x08002d40 0x00000020 Code RO 471 .text.__NVIC_EnableIRQ stm32h7xx_hal_cortex.o + 0x08002d60 0x08002d60 0x00000010 Code RO 463 .text.__NVIC_GetPriorityGrouping stm32h7xx_hal_cortex.o + 0x08002d70 0x08002d70 0x00000022 Code RO 465 .text.__NVIC_SetPriority stm32h7xx_hal_cortex.o + 0x08002d92 0x08002d92 0x00000006 PAD + 0x08002d98 0x08002d98 0x00000020 Code RO 459 .text.__NVIC_SetPriorityGrouping stm32h7xx_hal_cortex.o + 0x08002db8 0x08002db8 0x00000012 Code RO 11 .text.main main.o + 0x08002dca 0x08002dca 0x0000001a Code RO 1692 x$fpl$fpinit fz_wv.l(fpinit.o) + 0x08002de4 0x08002de4 0x0000004c Data RO 735 .rodata..L__const.HAL_FDCAN_Init.CvtEltSize stm32h7xx_hal_fdcan.o + 0x08002e30 0x08002e30 0x00000010 Data RO 1591 .rodata.D1CorePrescTable system_stm32h7xx.o + 0x08002e40 0x08002e40 0x00000020 Data RO 1767 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08002e60, Size: 0x00000000, Max: 0x00020000, ABSOLUTE) + + **** No section assigned to this execution region **** + + + Execution Region RW_IRAM2 (Exec base: 0x24000000, Load base: 0x08002e60, Size: 0x00000760, Max: 0x00050000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x24000000 0x08002e60 0x00000004 Data RW 1589 .data.SystemCoreClock system_stm32h7xx.o + 0x24000004 0x08002e64 0x00000004 Data RW 1590 .data.SystemD2Clock system_stm32h7xx.o + 0x24000008 0x08002e68 0x00000001 Data RW 1357 .data.uwTickFreq stm32h7xx_hal.o + 0x24000009 0x08002e69 0x00000003 PAD + 0x2400000c 0x08002e6c 0x00000004 Data RW 1356 .data.uwTickPrio stm32h7xx_hal.o + 0x24000010 - 0x00000060 Zero RW 1634 .bss c_w.l(libspace.o) + 0x24000070 - 0x000000a0 Zero RW 42 .bss.hfdcan1 fdcan.o + 0x24000110 - 0x0000004c Zero RW 94 .bss.htim2 stm32h7xx_hal_timebase_tim.o + 0x2400015c - 0x00000004 Zero RW 1358 .bss.uwTick stm32h7xx_hal.o + 0x24000160 - 0x00000200 Zero RW 2 HEAP startup_stm32h723xx.o + 0x24000360 - 0x00000400 Zero RW 1 STACK startup_stm32h723xx.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 274 0 0 0 160 10963 fdcan.o + 50 0 0 0 0 2194 gpio.o + 212 0 0 0 0 5763 main.o + 72 30 716 0 1536 828 startup_stm32h723xx.o + 138 0 0 5 4 15918 stm32h7xx_hal.o + 206 0 0 0 0 12846 stm32h7xx_hal_cortex.o + 1778 0 76 0 0 40904 stm32h7xx_hal_fdcan.o + 416 0 0 0 0 6947 stm32h7xx_hal_gpio.o + 32 0 0 0 0 2193 stm32h7xx_hal_msp.o + 72 0 0 0 0 9582 stm32h7xx_hal_pwr_ex.o + 2624 16 0 0 0 11020 stm32h7xx_hal_rcc.o + 3008 84 0 0 0 17085 stm32h7xx_hal_rcc_ex.o + 996 0 0 0 0 51401 stm32h7xx_hal_tim.o + 6 0 0 0 0 23532 stm32h7xx_hal_tim_ex.o + 160 0 0 0 76 9722 stm32h7xx_hal_timebase_tim.o + 50 0 0 0 0 1186 stm32h7xx_it.o + 236 0 16 8 0 5612 system_stm32h7xx.o + + ---------------------------------------------------------------------- + 10642 130 840 16 1776 227696 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 312 0 0 3 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 8 0 0 0 0 68 __main.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 52 8 0 0 0 0 __scatter.o + 26 0 0 0 0 0 __scatter_copy.o + 28 0 0 0 0 0 __scatter_zi.o + 18 0 0 0 0 80 exit.o + 6 0 0 0 0 152 heapauxi.o + 0 0 0 0 0 0 indicate_semi.o + 2 0 0 0 0 0 libinit.o + 6 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 78 0 0 0 0 80 rt_memclr_w.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 12 4 0 0 0 68 sys_exit.o + 74 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + 26 0 0 0 0 116 fpinit.o + + ---------------------------------------------------------------------- + 390 16 0 0 96 780 Library Totals + 10 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 354 16 0 0 96 664 c_w.l + 26 0 0 0 0 116 fz_wv.l + + ---------------------------------------------------------------------- + 390 16 0 0 96 780 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 11032 146 840 16 1872 228028 Grand Totals + 11032 146 840 16 1872 228028 ELF Image Totals + 11032 146 840 16 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 11872 ( 11.59kB) + Total RW Size (RW Data + ZI Data) 1888 ( 1.84kB) + Total ROM Size (Code + RO Data + RW Data) 11888 ( 11.61kB) + +============================================================================== + diff --git a/MDK-ARM/FDCAN/FDCAN.sct b/MDK-ARM/FDCAN/FDCAN.sct new file mode 100644 index 0000000..eca34f2 --- /dev/null +++ b/MDK-ARM/FDCAN/FDCAN.sct @@ -0,0 +1,19 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM2 0x24000000 0x00050000 { + .ANY (+RW +ZI) + } +} + diff --git a/MDK-ARM/FDCAN/FDCAN_FDCAN.dep b/MDK-ARM/FDCAN/FDCAN_FDCAN.dep new file mode 100644 index 0000000..4232190 --- /dev/null +++ b/MDK-ARM/FDCAN/FDCAN_FDCAN.dep @@ -0,0 +1,1359 @@ +Dependencies for Project 'FDCAN', Target 'FDCAN': (DO NOT MODIFY !) +CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC +F (startup_stm32h723xx.s)(0x694E3400)(--cpu Cortex-M7.fp.dp -g --apcs=interwork -I ../Drivers/CMSIS/Include -I.\RTE\_FDCAN -ID:\cangming\ARM\CMSIS\5.7.0\CMSIS\Core\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32H723xx SETA 1" --pd "_RTE_ SETA 1" --list startup_stm32h723xx.lst --xref -o fdcan\startup_stm32h723xx.o --depend fdcan\startup_stm32h723xx.d) +F (../Core/Src/main.c)(0x694E2F79)(--c99 --gnu -c --cpu Cortex-M7.fp.dp -g -O3 --apcs=interwork --split_sections -I ../Core/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I.\RTE\_FDCAN -ID:\cangming\ARM\CMSIS\5.7.0\CMSIS\Core\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32H723xx -D_RTE_ -DUSE_PWR_LDO_SUPPLY -DUSE_HAL_DRIVER -DSTM32H723xx -o fdcan\main.o --omf_browse fdcan\main.crf --depend fdcan\main.d) +I (../Core/Inc/main.h)(0x694E28D6) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h)(0x6944350B) +I (../Core/Inc/stm32h7xx_hal_conf.h)(0x6946871A) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h)(0x6944350B) +I (../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h)(0x6944350B) +I (../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h)(0x6944350B) +I (../Drivers/CMSIS/Include/core_cm7.h)(0x694434DE) +I (D:\cangming\ARM\ARMCC\include\stdint.h)(0x5E8E3CC2) +I (../Drivers/CMSIS/Include/cmsis_version.h)(0x694434DE) +I (../Drivers/CMSIS/Include/cmsis_compiler.h)(0x694434DE) +I (../Drivers/CMSIS/Include/cmsis_armcc.h)(0x694434DE) +I (../Drivers/CMSIS/Include/mpu_armv7.h)(0x694434DE) +I (../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h)(0x6944350B) +I (D:\cangming\ARM\ARMCC\include\stddef.h)(0x5E8E3CC2) +I (D:\cangming\ARM\ARMCC\include\math.h)(0x5E8E3CC2) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h)(0x6944350B) +I (../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h)(0x694434DA) +I (../Core/Inc/FreeRTOSConfig.h)(0x6946749D) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/task.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/list.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h)(0x694434DA) +I (../Core/Inc/fdcan.h)(0x69469E17) +I (../Core/Inc/gpio.h)(0x6944350E) +F (../Core/Src/gpio.c)(0x694E28D3)(--c99 --gnu -c --cpu Cortex-M7.fp.dp -g -O3 --apcs=interwork --split_sections -I ../Core/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I.\RTE\_FDCAN -ID:\cangming\ARM\CMSIS\5.7.0\CMSIS\Core\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32H723xx -D_RTE_ -DUSE_PWR_LDO_SUPPLY -DUSE_HAL_DRIVER -DSTM32H723xx -o fdcan\gpio.o --omf_browse fdcan\gpio.crf --depend fdcan\gpio.d) +I (../Core/Inc/gpio.h)(0x6944350E) +I (../Core/Inc/main.h)(0x694E28D6) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h)(0x6944350B) +I (../Core/Inc/stm32h7xx_hal_conf.h)(0x6946871A) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h)(0x6944350B) +I (../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h)(0x6944350B) +I (../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h)(0x6944350B) +I (../Drivers/CMSIS/Include/core_cm7.h)(0x694434DE) +I (D:\cangming\ARM\ARMCC\include\stdint.h)(0x5E8E3CC2) +I (../Drivers/CMSIS/Include/cmsis_version.h)(0x694434DE) +I (../Drivers/CMSIS/Include/cmsis_compiler.h)(0x694434DE) +I (../Drivers/CMSIS/Include/cmsis_armcc.h)(0x694434DE) +I (../Drivers/CMSIS/Include/mpu_armv7.h)(0x694434DE) +I (../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h)(0x6944350B) +I (D:\cangming\ARM\ARMCC\include\stddef.h)(0x5E8E3CC2) +I (D:\cangming\ARM\ARMCC\include\math.h)(0x5E8E3CC2) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h)(0x6944350B) +F (../Core/Src/freertos.c)(0x6946749D)(--c99 --gnu -c --cpu Cortex-M7.fp.dp -g -O3 --apcs=interwork --split_sections -I ../Core/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I.\RTE\_FDCAN -ID:\cangming\ARM\CMSIS\5.7.0\CMSIS\Core\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32H723xx -D_RTE_ -DUSE_PWR_LDO_SUPPLY -DUSE_HAL_DRIVER -DSTM32H723xx -o fdcan\freertos.o --omf_browse fdcan\freertos.crf --depend fdcan\freertos.d) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h)(0x694434DA) +I (D:\cangming\ARM\ARMCC\include\stddef.h)(0x5E8E3CC2) +I (D:\cangming\ARM\ARMCC\include\stdint.h)(0x5E8E3CC2) +I (../Core/Inc/FreeRTOSConfig.h)(0x6946749D) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h)(0x694434DA) +I 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(../Drivers/CMSIS/Include/cmsis_compiler.h)(0x694434DE) +I (../Drivers/CMSIS/Include/cmsis_armcc.h)(0x694434DE) +I (../Drivers/CMSIS/Include/mpu_armv7.h)(0x694434DE) +I (../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h)(0x6944350B) +I (D:\cangming\ARM\ARMCC\include\math.h)(0x5E8E3CC2) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h)(0x6944350B) +I (../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h)(0x694434DA) +F (../Core/Src/fdcan.c)(0x69469E17)(--c99 --gnu -c --cpu Cortex-M7.fp.dp -g -O3 --apcs=interwork --split_sections -I ../Core/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I.\RTE\_FDCAN -ID:\cangming\ARM\CMSIS\5.7.0\CMSIS\Core\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32H723xx -D_RTE_ -DUSE_PWR_LDO_SUPPLY -DUSE_HAL_DRIVER -DSTM32H723xx -o fdcan\fdcan.o --omf_browse fdcan\fdcan.crf --depend fdcan\fdcan.d) +I (../Core/Inc/fdcan.h)(0x69469E17) +I (../Core/Inc/main.h)(0x694E28D6) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h)(0x6944350B) +I (../Core/Inc/stm32h7xx_hal_conf.h)(0x6946871A) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h)(0x6944350B) +I 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(D:\cangming\ARM\ARMCC\include\math.h)(0x5E8E3CC2) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h)(0x6944350B) +F (../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c)(0x6944350B)(--c99 --gnu -c --cpu Cortex-M7.fp.dp -g -O3 --apcs=interwork --split_sections -I ../Core/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I.\RTE\_FDCAN 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(../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h)(0x6944350B) +F (../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c)(0x6944350B)(--c99 --gnu -c --cpu Cortex-M7.fp.dp -g -O3 --apcs=interwork --split_sections -I ../Core/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I ../Drivers/CMSIS/Include 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(D:\cangming\ARM\ARMCC\include\math.h)(0x5E8E3CC2) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h)(0x6944350B) +I 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../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I.\RTE\_FDCAN -ID:\cangming\ARM\CMSIS\5.7.0\CMSIS\Core\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32H723xx -D_RTE_ -DUSE_PWR_LDO_SUPPLY -DUSE_HAL_DRIVER -DSTM32H723xx -o fdcan\filter.o --omf_browse fdcan\filter.crf --depend fdcan\filter.d) +I (..\User\component\filter.h)(0x690DC361) +I (..\User\component\user_math.h)(0x690DD4C7) +I (D:\cangming\ARM\ARMCC\include\float.h)(0x5E8E3CC2) +I (D:\cangming\ARM\ARMCC\include\math.h)(0x5E8E3CC2) +I (D:\cangming\ARM\ARMCC\include\stdbool.h)(0x5E8E3CC2) +I (D:\cangming\ARM\ARMCC\include\stdint.h)(0x5E8E3CC2) +I (D:\cangming\ARM\ARMCC\include\stddef.h)(0x5E8E3CC2) +F (..\User\component\filter.h)(0x690DC361)() +F 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(../Core/Inc/stm32h7xx_hal_conf.h)(0x6946871A) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h)(0x6944350B) +I (../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h)(0x6944350B) +F (..\User\task\init.c)(0x694675AA)(--c99 --gnu -c --cpu Cortex-M7.fp.dp -g -O3 --apcs=interwork --split_sections -I ../Core/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I.\RTE\_FDCAN -ID:\cangming\ARM\CMSIS\5.7.0\CMSIS\Core\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32H723xx -D_RTE_ -DUSE_PWR_LDO_SUPPLY -DUSE_HAL_DRIVER -DSTM32H723xx -o fdcan\init.o --omf_browse fdcan\init.crf --depend fdcan\init.d) +I (..\User\task/user_task.h)(0x693967A8) +I (../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h)(0x694434DA) +I (D:\cangming\ARM\ARMCC\include\stdint.h)(0x5E8E3CC2) +I (D:\cangming\ARM\ARMCC\include\stddef.h)(0x5E8E3CC2) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h)(0x694434DA) +I (../Core/Inc/FreeRTOSConfig.h)(0x6946749D) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/task.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/list.h)(0x694434DA) +F (..\User\task\user_task.c)(0x694675AA)(--c99 --gnu -c --cpu Cortex-M7.fp.dp -g -O3 --apcs=interwork --split_sections -I ../Core/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc -I ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I.\RTE\_FDCAN -ID:\cangming\ARM\CMSIS\5.7.0\CMSIS\Core\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32H723xx -D_RTE_ -DUSE_PWR_LDO_SUPPLY -DUSE_HAL_DRIVER -DSTM32H723xx -o fdcan\user_task.o --omf_browse fdcan\user_task.crf --depend fdcan\user_task.d) +I (..\User\task/user_task.h)(0x693967A8) +I (../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h)(0x694434DA) +I (D:\cangming\ARM\ARMCC\include\stdint.h)(0x5E8E3CC2) +I (D:\cangming\ARM\ARMCC\include\stddef.h)(0x5E8E3CC2) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h)(0x694434DA) +I (../Core/Inc/FreeRTOSConfig.h)(0x6946749D) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/task.h)(0x694434DA) +I (../Middlewares/Third_Party/FreeRTOS/Source/include/list.h)(0x694434DA) +F (..\User\task\user_task.h)(0x693967A8)() diff --git a/MDK-ARM/FDCAN/blink.d b/MDK-ARM/FDCAN/blink.d new file mode 100644 index 0000000..d1bd610 --- /dev/null +++ b/MDK-ARM/FDCAN/blink.d @@ -0,0 +1,21 @@ +fdcan\blink.o: ..\User\task\blink.c +fdcan\blink.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\blink.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\blink.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\blink.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\blink.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\blink.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\blink.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\blink.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\blink.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\blink.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\blink.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\blink.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\blink.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\blink.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\blink.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\blink.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\blink.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\blink.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\blink.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\blink.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h diff --git a/MDK-ARM/FDCAN/cmsis_os2.crf b/MDK-ARM/FDCAN/cmsis_os2.crf new file mode 100644 index 0000000..4e4b6b1 Binary files /dev/null and b/MDK-ARM/FDCAN/cmsis_os2.crf differ diff --git a/MDK-ARM/FDCAN/cmsis_os2.d b/MDK-ARM/FDCAN/cmsis_os2.d new file mode 100644 index 0000000..196ae97 --- /dev/null +++ b/MDK-ARM/FDCAN/cmsis_os2.d @@ -0,0 +1,53 @@ +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c +fdcan\cmsis_os2.o: D:\cangming\ARM\ARMCC\Bin\..\include\string.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h +fdcan\cmsis_os2.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\cmsis_os2.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\cmsis_os2.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\cmsis_os2.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\cmsis_os2.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h +fdcan\cmsis_os2.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h +fdcan\cmsis_os2.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\cmsis_os2.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\cmsis_os2.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\cmsis_os2.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\cmsis_os2.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\cmsis_os2.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\cmsis_os2.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\cmsis_os2.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\cmsis_os2.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\cmsis_os2.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/cmsis_os2.o b/MDK-ARM/FDCAN/cmsis_os2.o new file mode 100644 index 0000000..b94e74b Binary files /dev/null and b/MDK-ARM/FDCAN/cmsis_os2.o differ diff --git a/MDK-ARM/FDCAN/crc16.crf b/MDK-ARM/FDCAN/crc16.crf new file mode 100644 index 0000000..a82c599 Binary files /dev/null and b/MDK-ARM/FDCAN/crc16.crf differ diff --git a/MDK-ARM/FDCAN/crc16.d b/MDK-ARM/FDCAN/crc16.d new file mode 100644 index 0000000..edf7cb2 --- /dev/null +++ b/MDK-ARM/FDCAN/crc16.d @@ -0,0 +1,8 @@ +fdcan\crc16.o: ..\User\component\crc16.c +fdcan\crc16.o: ..\User\component\crc16.h +fdcan\crc16.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdbool.h +fdcan\crc16.o: ..\User\component\user_math.h +fdcan\crc16.o: D:\cangming\ARM\ARMCC\Bin\..\include\float.h +fdcan\crc16.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\crc16.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\crc16.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h diff --git a/MDK-ARM/FDCAN/crc16.o b/MDK-ARM/FDCAN/crc16.o new file mode 100644 index 0000000..f15632b Binary files /dev/null and b/MDK-ARM/FDCAN/crc16.o differ diff --git a/MDK-ARM/FDCAN/croutine.crf b/MDK-ARM/FDCAN/croutine.crf new file mode 100644 index 0000000..140f140 Binary files /dev/null and b/MDK-ARM/FDCAN/croutine.crf differ diff --git a/MDK-ARM/FDCAN/croutine.d b/MDK-ARM/FDCAN/croutine.d new file mode 100644 index 0000000..c051722 --- /dev/null +++ b/MDK-ARM/FDCAN/croutine.d @@ -0,0 +1,14 @@ +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/croutine.c +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\croutine.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\croutine.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\croutine.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h +fdcan\croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h diff --git a/MDK-ARM/FDCAN/croutine.o b/MDK-ARM/FDCAN/croutine.o new file mode 100644 index 0000000..f6a9798 Binary files /dev/null and b/MDK-ARM/FDCAN/croutine.o differ diff --git a/MDK-ARM/FDCAN/event_groups.crf b/MDK-ARM/FDCAN/event_groups.crf new file mode 100644 index 0000000..a689913 Binary files /dev/null and b/MDK-ARM/FDCAN/event_groups.crf differ diff --git a/MDK-ARM/FDCAN/event_groups.d b/MDK-ARM/FDCAN/event_groups.d new file mode 100644 index 0000000..6005931 --- /dev/null +++ b/MDK-ARM/FDCAN/event_groups.d @@ -0,0 +1,15 @@ +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c +fdcan\event_groups.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdlib.h +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\event_groups.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\event_groups.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\event_groups.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +fdcan\event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h diff --git a/MDK-ARM/FDCAN/event_groups.o b/MDK-ARM/FDCAN/event_groups.o new file mode 100644 index 0000000..5ed3b61 Binary files /dev/null and b/MDK-ARM/FDCAN/event_groups.o differ diff --git a/MDK-ARM/FDCAN/fdcan.crf b/MDK-ARM/FDCAN/fdcan.crf new file mode 100644 index 0000000..943a98b Binary files /dev/null and b/MDK-ARM/FDCAN/fdcan.crf differ diff --git a/MDK-ARM/FDCAN/fdcan.d b/MDK-ARM/FDCAN/fdcan.d new file mode 100644 index 0000000..70a3ba9 --- /dev/null +++ b/MDK-ARM/FDCAN/fdcan.d @@ -0,0 +1,38 @@ +fdcan\fdcan.o: ../Core/Src/fdcan.c +fdcan\fdcan.o: ../Core/Inc/fdcan.h +fdcan\fdcan.o: ../Core/Inc/main.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\fdcan.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\fdcan.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\fdcan.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\fdcan.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\fdcan.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\fdcan.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\fdcan.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\fdcan.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\fdcan.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\fdcan.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\fdcan.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\fdcan.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/fdcan.o b/MDK-ARM/FDCAN/fdcan.o new file mode 100644 index 0000000..d7e6dea Binary files /dev/null and b/MDK-ARM/FDCAN/fdcan.o differ diff --git a/MDK-ARM/FDCAN/fdcan_1.d b/MDK-ARM/FDCAN/fdcan_1.d new file mode 100644 index 0000000..330abe4 --- /dev/null +++ b/MDK-ARM/FDCAN/fdcan_1.d @@ -0,0 +1,53 @@ +fdcan\fdcan_1.o: ..\User\bsp\fdcan.c +fdcan\fdcan_1.o: ..\User\bsp\fdcan.h +fdcan\fdcan_1.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\fdcan_1.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdbool.h +fdcan\fdcan_1.o: ../User/bsp/bsp.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\fdcan_1.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\fdcan_1.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\fdcan_1.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\fdcan_1.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\fdcan_1.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\fdcan_1.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\fdcan_1.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\fdcan_1.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\fdcan_1.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\fdcan_1.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\fdcan_1.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\fdcan_1.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h +fdcan\fdcan_1.o: ../User/bsp/mm.h +fdcan\fdcan_1.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h +fdcan\fdcan_1.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\fdcan_1.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\fdcan_1.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\fdcan_1.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\fdcan_1.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\fdcan_1.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\fdcan_1.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\fdcan_1.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\fdcan_1.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +fdcan\fdcan_1.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h +fdcan\fdcan_1.o: ../Core/Inc/fdcan.h +fdcan\fdcan_1.o: ../Core/Inc/main.h diff --git a/MDK-ARM/FDCAN/filter.crf b/MDK-ARM/FDCAN/filter.crf new file mode 100644 index 0000000..6503520 Binary files /dev/null and b/MDK-ARM/FDCAN/filter.crf differ diff --git a/MDK-ARM/FDCAN/filter.d b/MDK-ARM/FDCAN/filter.d new file mode 100644 index 0000000..98f3c28 --- /dev/null +++ b/MDK-ARM/FDCAN/filter.d @@ -0,0 +1,8 @@ +fdcan\filter.o: ..\User\component\filter.c +fdcan\filter.o: ..\User\component\filter.h +fdcan\filter.o: ..\User\component\user_math.h +fdcan\filter.o: D:\cangming\ARM\ARMCC\Bin\..\include\float.h +fdcan\filter.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\filter.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdbool.h +fdcan\filter.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\filter.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h diff --git a/MDK-ARM/FDCAN/filter.o b/MDK-ARM/FDCAN/filter.o new file mode 100644 index 0000000..8fa354c Binary files /dev/null and b/MDK-ARM/FDCAN/filter.o differ diff --git a/MDK-ARM/FDCAN/freertos.crf b/MDK-ARM/FDCAN/freertos.crf new file mode 100644 index 0000000..f49942e Binary files /dev/null and b/MDK-ARM/FDCAN/freertos.crf differ diff --git a/MDK-ARM/FDCAN/freertos.d b/MDK-ARM/FDCAN/freertos.d new file mode 100644 index 0000000..bd037a2 --- /dev/null +++ b/MDK-ARM/FDCAN/freertos.d @@ -0,0 +1,48 @@ +fdcan\freertos.o: ../Core/Src/freertos.c +fdcan\freertos.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\freertos.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\freertos.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\freertos.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\freertos.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\freertos.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\freertos.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\freertos.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\freertos.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\freertos.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\freertos.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +fdcan\freertos.o: ../Core/Inc/main.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\freertos.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\freertos.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\freertos.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\freertos.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\freertos.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\freertos.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\freertos.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\freertos.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\freertos.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\freertos.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\freertos.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h +fdcan\freertos.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h +fdcan\freertos.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h diff --git a/MDK-ARM/FDCAN/freertos.o b/MDK-ARM/FDCAN/freertos.o new file mode 100644 index 0000000..2a007d4 Binary files /dev/null and b/MDK-ARM/FDCAN/freertos.o differ diff --git a/MDK-ARM/FDCAN/gpio.crf b/MDK-ARM/FDCAN/gpio.crf new file mode 100644 index 0000000..cf7be94 Binary files /dev/null and b/MDK-ARM/FDCAN/gpio.crf differ diff --git a/MDK-ARM/FDCAN/gpio.d b/MDK-ARM/FDCAN/gpio.d new file mode 100644 index 0000000..35bd842 --- /dev/null +++ b/MDK-ARM/FDCAN/gpio.d @@ -0,0 +1,38 @@ +fdcan\gpio.o: ../Core/Src/gpio.c +fdcan\gpio.o: ../Core/Inc/gpio.h +fdcan\gpio.o: ../Core/Inc/main.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\gpio.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\gpio.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\gpio.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\gpio.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\gpio.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\gpio.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\gpio.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\gpio.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\gpio.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\gpio.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\gpio.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\gpio.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/gpio.o b/MDK-ARM/FDCAN/gpio.o new file mode 100644 index 0000000..519f104 Binary files /dev/null and b/MDK-ARM/FDCAN/gpio.o differ diff --git a/MDK-ARM/FDCAN/heap_4.crf b/MDK-ARM/FDCAN/heap_4.crf new file mode 100644 index 0000000..707526c Binary files /dev/null and b/MDK-ARM/FDCAN/heap_4.crf differ diff --git a/MDK-ARM/FDCAN/heap_4.d b/MDK-ARM/FDCAN/heap_4.d new file mode 100644 index 0000000..454c542 --- /dev/null +++ b/MDK-ARM/FDCAN/heap_4.d @@ -0,0 +1,13 @@ +fdcan\heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c +fdcan\heap_4.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdlib.h +fdcan\heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\heap_4.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\heap_4.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\heap_4.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h diff --git a/MDK-ARM/FDCAN/heap_4.o b/MDK-ARM/FDCAN/heap_4.o new file mode 100644 index 0000000..9ac8adb Binary files /dev/null and b/MDK-ARM/FDCAN/heap_4.o differ diff --git a/MDK-ARM/FDCAN/init.crf b/MDK-ARM/FDCAN/init.crf new file mode 100644 index 0000000..7c5c2d6 Binary files /dev/null and b/MDK-ARM/FDCAN/init.crf differ diff --git a/MDK-ARM/FDCAN/init.d b/MDK-ARM/FDCAN/init.d new file mode 100644 index 0000000..b148647 --- /dev/null +++ b/MDK-ARM/FDCAN/init.d @@ -0,0 +1,14 @@ +fdcan\init.o: ..\User\task\init.c +fdcan\init.o: ../User/task/user_task.h +fdcan\init.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h +fdcan\init.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\init.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\init.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\init.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\init.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\init.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\init.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\init.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\init.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\init.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\init.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h diff --git a/MDK-ARM/FDCAN/init.o b/MDK-ARM/FDCAN/init.o new file mode 100644 index 0000000..b013929 Binary files /dev/null and b/MDK-ARM/FDCAN/init.o differ diff --git a/MDK-ARM/FDCAN/list.crf b/MDK-ARM/FDCAN/list.crf new file mode 100644 index 0000000..3c2a02c Binary files /dev/null and b/MDK-ARM/FDCAN/list.crf differ diff --git a/MDK-ARM/FDCAN/list.d b/MDK-ARM/FDCAN/list.d new file mode 100644 index 0000000..e7b56b3 --- /dev/null +++ b/MDK-ARM/FDCAN/list.d @@ -0,0 +1,12 @@ +fdcan\list.o: ../Middlewares/Third_Party/FreeRTOS/Source/list.c +fdcan\list.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdlib.h +fdcan\list.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\list.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\list.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\list.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\list.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\list.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\list.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\list.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\list.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\list.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h diff --git a/MDK-ARM/FDCAN/list.o b/MDK-ARM/FDCAN/list.o new file mode 100644 index 0000000..3d583de Binary files /dev/null and b/MDK-ARM/FDCAN/list.o differ diff --git a/MDK-ARM/FDCAN/main.crf b/MDK-ARM/FDCAN/main.crf new file mode 100644 index 0000000..156594f Binary files /dev/null and b/MDK-ARM/FDCAN/main.crf differ diff --git a/MDK-ARM/FDCAN/main.d b/MDK-ARM/FDCAN/main.d new file mode 100644 index 0000000..196e5c3 --- /dev/null +++ b/MDK-ARM/FDCAN/main.d @@ -0,0 +1,50 @@ +fdcan\main.o: ../Core/Src/main.c +fdcan\main.o: ../Core/Inc/main.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\main.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\main.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\main.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\main.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\main.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\main.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\main.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\main.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\main.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\main.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\main.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\main.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\main.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h +fdcan\main.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h +fdcan\main.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\main.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\main.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\main.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\main.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\main.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\main.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\main.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\main.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +fdcan\main.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h +fdcan\main.o: ../Core/Inc/fdcan.h +fdcan\main.o: ../Core/Inc/gpio.h diff --git a/MDK-ARM/FDCAN/main.o b/MDK-ARM/FDCAN/main.o new file mode 100644 index 0000000..2250a16 Binary files /dev/null and b/MDK-ARM/FDCAN/main.o differ diff --git a/MDK-ARM/FDCAN/mm.crf b/MDK-ARM/FDCAN/mm.crf new file mode 100644 index 0000000..85f277c Binary files /dev/null and b/MDK-ARM/FDCAN/mm.crf differ diff --git a/MDK-ARM/FDCAN/mm.d b/MDK-ARM/FDCAN/mm.d new file mode 100644 index 0000000..2549350 --- /dev/null +++ b/MDK-ARM/FDCAN/mm.d @@ -0,0 +1,11 @@ +fdcan\mm.o: ..\User\bsp\mm.c +fdcan\mm.o: ../User/bsp/mm.h +fdcan\mm.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\mm.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\mm.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\mm.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\mm.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\mm.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\mm.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\mm.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\mm.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h diff --git a/MDK-ARM/FDCAN/mm.o b/MDK-ARM/FDCAN/mm.o new file mode 100644 index 0000000..479509f Binary files /dev/null and b/MDK-ARM/FDCAN/mm.o differ diff --git a/MDK-ARM/FDCAN/pid.crf b/MDK-ARM/FDCAN/pid.crf new file mode 100644 index 0000000..5e0901e Binary files /dev/null and b/MDK-ARM/FDCAN/pid.crf differ diff --git a/MDK-ARM/FDCAN/pid.d b/MDK-ARM/FDCAN/pid.d new file mode 100644 index 0000000..572f2b6 --- /dev/null +++ b/MDK-ARM/FDCAN/pid.d @@ -0,0 +1,9 @@ +fdcan\pid.o: ..\User\component\pid.c +fdcan\pid.o: ..\User\component\pid.h +fdcan\pid.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\pid.o: ..\User\component\filter.h +fdcan\pid.o: ..\User\component\user_math.h +fdcan\pid.o: D:\cangming\ARM\ARMCC\Bin\..\include\float.h +fdcan\pid.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\pid.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdbool.h +fdcan\pid.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h diff --git a/MDK-ARM/FDCAN/pid.o b/MDK-ARM/FDCAN/pid.o new file mode 100644 index 0000000..f9953e2 Binary files /dev/null and b/MDK-ARM/FDCAN/pid.o differ diff --git a/MDK-ARM/FDCAN/port.crf b/MDK-ARM/FDCAN/port.crf new file mode 100644 index 0000000..737904a Binary files /dev/null and b/MDK-ARM/FDCAN/port.crf differ diff --git a/MDK-ARM/FDCAN/port.d b/MDK-ARM/FDCAN/port.d new file mode 100644 index 0000000..123d84a --- /dev/null +++ b/MDK-ARM/FDCAN/port.d @@ -0,0 +1,12 @@ +fdcan\port.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c +fdcan\port.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\port.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\port.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\port.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\port.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\port.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\port.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\port.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\port.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\port.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\port.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h diff --git a/MDK-ARM/FDCAN/port.o b/MDK-ARM/FDCAN/port.o new file mode 100644 index 0000000..e930067 Binary files /dev/null and b/MDK-ARM/FDCAN/port.o differ diff --git a/MDK-ARM/FDCAN/queue.crf b/MDK-ARM/FDCAN/queue.crf new file mode 100644 index 0000000..dc52a9b Binary files /dev/null and b/MDK-ARM/FDCAN/queue.crf differ diff --git a/MDK-ARM/FDCAN/queue.d b/MDK-ARM/FDCAN/queue.d new file mode 100644 index 0000000..fee3700 --- /dev/null +++ b/MDK-ARM/FDCAN/queue.d @@ -0,0 +1,15 @@ +fdcan\queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/queue.c +fdcan\queue.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdlib.h +fdcan\queue.o: D:\cangming\ARM\ARMCC\Bin\..\include\string.h +fdcan\queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\queue.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\queue.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\queue.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +fdcan\queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h diff --git a/MDK-ARM/FDCAN/queue.o b/MDK-ARM/FDCAN/queue.o new file mode 100644 index 0000000..5f7e521 Binary files /dev/null and b/MDK-ARM/FDCAN/queue.o differ diff --git a/MDK-ARM/FDCAN/startup_stm32h723xx.d b/MDK-ARM/FDCAN/startup_stm32h723xx.d new file mode 100644 index 0000000..7bffbbd --- /dev/null +++ b/MDK-ARM/FDCAN/startup_stm32h723xx.d @@ -0,0 +1 @@ +fdcan\startup_stm32h723xx.o: startup_stm32h723xx.s diff --git a/MDK-ARM/FDCAN/startup_stm32h723xx.o b/MDK-ARM/FDCAN/startup_stm32h723xx.o new file mode 100644 index 0000000..efc5615 Binary files /dev/null and b/MDK-ARM/FDCAN/startup_stm32h723xx.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal.crf b/MDK-ARM/FDCAN/stm32h7xx_hal.crf new file mode 100644 index 0000000..227e42d Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal.d b/MDK-ARM/FDCAN/stm32h7xx_hal.d new file mode 100644 index 0000000..07be485 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal.o b/MDK-ARM/FDCAN/stm32h7xx_hal.o new file mode 100644 index 0000000..49f1b00 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_cortex.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_cortex.crf new file mode 100644 index 0000000..d051a48 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_cortex.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_cortex.d b/MDK-ARM/FDCAN/stm32h7xx_hal_cortex.d new file mode 100644 index 0000000..7be17fc --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_cortex.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_cortex.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_cortex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_cortex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_cortex.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_cortex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_cortex.o b/MDK-ARM/FDCAN/stm32h7xx_hal_cortex.o new file mode 100644 index 0000000..0fb5685 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_cortex.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_dma.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_dma.crf new file mode 100644 index 0000000..0640696 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_dma.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_dma.d b/MDK-ARM/FDCAN/stm32h7xx_hal_dma.d new file mode 100644 index 0000000..159466f --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_dma.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_dma.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_dma.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_dma.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_dma.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_dma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_dma.o b/MDK-ARM/FDCAN/stm32h7xx_hal_dma.o new file mode 100644 index 0000000..488b822 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_dma.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_dma_ex.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_dma_ex.crf new file mode 100644 index 0000000..a81f3d2 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_dma_ex.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_dma_ex.d b/MDK-ARM/FDCAN/stm32h7xx_hal_dma_ex.d new file mode 100644 index 0000000..fd2e765 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_dma_ex.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_dma_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_dma_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_dma_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_dma_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_dma_ex.o b/MDK-ARM/FDCAN/stm32h7xx_hal_dma_ex.o new file mode 100644 index 0000000..d465291 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_dma_ex.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_exti.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_exti.crf new file mode 100644 index 0000000..a40d72e Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_exti.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_exti.d b/MDK-ARM/FDCAN/stm32h7xx_hal_exti.d new file mode 100644 index 0000000..744ece9 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_exti.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_exti.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_exti.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_exti.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_exti.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_exti.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_exti.o b/MDK-ARM/FDCAN/stm32h7xx_hal_exti.o new file mode 100644 index 0000000..cce6447 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_exti.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_fdcan.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_fdcan.crf new file mode 100644 index 0000000..a6b17f4 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_fdcan.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_fdcan.d b/MDK-ARM/FDCAN/stm32h7xx_hal_fdcan.d new file mode 100644 index 0000000..62a5d4a --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_fdcan.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_fdcan.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_fdcan.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_fdcan.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_fdcan.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_fdcan.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_fdcan.o b/MDK-ARM/FDCAN/stm32h7xx_hal_fdcan.o new file mode 100644 index 0000000..c96beb2 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_fdcan.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_flash.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_flash.crf new file mode 100644 index 0000000..85257fe Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_flash.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_flash.d b/MDK-ARM/FDCAN/stm32h7xx_hal_flash.d new file mode 100644 index 0000000..d820bff --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_flash.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_flash.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_flash.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_flash.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_flash.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_flash.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_flash.o b/MDK-ARM/FDCAN/stm32h7xx_hal_flash.o new file mode 100644 index 0000000..ddc2518 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_flash.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_flash_ex.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_flash_ex.crf new file mode 100644 index 0000000..b1f6a1a Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_flash_ex.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_flash_ex.d b/MDK-ARM/FDCAN/stm32h7xx_hal_flash_ex.d new file mode 100644 index 0000000..61b5e89 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_flash_ex.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_flash_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_flash_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_flash_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_flash_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_flash_ex.o b/MDK-ARM/FDCAN/stm32h7xx_hal_flash_ex.o new file mode 100644 index 0000000..02f1b3c Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_flash_ex.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_gpio.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_gpio.crf new file mode 100644 index 0000000..77d1de0 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_gpio.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_gpio.d b/MDK-ARM/FDCAN/stm32h7xx_hal_gpio.d new file mode 100644 index 0000000..6b992a6 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_gpio.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_gpio.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_gpio.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_gpio.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_gpio.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_gpio.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_gpio.o b/MDK-ARM/FDCAN/stm32h7xx_hal_gpio.o new file mode 100644 index 0000000..ce5220d Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_gpio.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_hsem.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_hsem.crf new file mode 100644 index 0000000..f33f03e Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_hsem.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_hsem.d b/MDK-ARM/FDCAN/stm32h7xx_hal_hsem.d new file mode 100644 index 0000000..cbc1c04 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_hsem.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_hsem.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_hsem.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_hsem.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_hsem.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_hsem.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_hsem.o b/MDK-ARM/FDCAN/stm32h7xx_hal_hsem.o new file mode 100644 index 0000000..7047b0d Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_hsem.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_i2c.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c.crf new file mode 100644 index 0000000..0061d53 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_i2c.d b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c.d new file mode 100644 index 0000000..bec5a18 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_i2c.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_i2c.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_i2c.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_i2c.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_i2c.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_i2c.o b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c.o new file mode 100644 index 0000000..8190e4e Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_i2c_ex.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c_ex.crf new file mode 100644 index 0000000..606e3ba Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c_ex.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_i2c_ex.d b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c_ex.d new file mode 100644 index 0000000..1e6ad53 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c_ex.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_i2c_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_i2c_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_i2c_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_i2c_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_i2c_ex.o b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c_ex.o new file mode 100644 index 0000000..c63cba9 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_i2c_ex.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_mdma.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_mdma.crf new file mode 100644 index 0000000..ce81cf8 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_mdma.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_mdma.d b/MDK-ARM/FDCAN/stm32h7xx_hal_mdma.d new file mode 100644 index 0000000..0fea1fa --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_mdma.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_mdma.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_mdma.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_mdma.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_mdma.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_mdma.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_mdma.o b/MDK-ARM/FDCAN/stm32h7xx_hal_mdma.o new file mode 100644 index 0000000..1a88bc1 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_mdma.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_msp.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_msp.crf new file mode 100644 index 0000000..a376be7 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_msp.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_msp.d b/MDK-ARM/FDCAN/stm32h7xx_hal_msp.d new file mode 100644 index 0000000..1ac915e --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_msp.d @@ -0,0 +1,37 @@ +fdcan\stm32h7xx_hal_msp.o: ../Core/Src/stm32h7xx_hal_msp.c +fdcan\stm32h7xx_hal_msp.o: ../Core/Inc/main.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_msp.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_msp.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_msp.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_msp.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_msp.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_msp.o b/MDK-ARM/FDCAN/stm32h7xx_hal_msp.o new file mode 100644 index 0000000..cc46061 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_msp.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_pwr.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr.crf new file mode 100644 index 0000000..c3a6517 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_pwr.d b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr.d new file mode 100644 index 0000000..7f2a519 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_pwr.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_pwr.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_pwr.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_pwr.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_pwr.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_pwr.o b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr.o new file mode 100644 index 0000000..9ead883 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_pwr_ex.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr_ex.crf new file mode 100644 index 0000000..9d92781 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr_ex.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_pwr_ex.d b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr_ex.d new file mode 100644 index 0000000..d1a5920 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr_ex.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_pwr_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_pwr_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_pwr_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_pwr_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_pwr_ex.o b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr_ex.o new file mode 100644 index 0000000..a25a178 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_pwr_ex.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_rcc.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc.crf new file mode 100644 index 0000000..529990d Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_rcc.d b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc.d new file mode 100644 index 0000000..1545231 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_rcc.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_rcc.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_rcc.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_rcc.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_rcc.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_rcc.o b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc.o new file mode 100644 index 0000000..e0cd676 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_rcc_ex.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc_ex.crf new file mode 100644 index 0000000..434f9b3 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc_ex.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_rcc_ex.d b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc_ex.d new file mode 100644 index 0000000..544f70c --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc_ex.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_rcc_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_rcc_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_rcc_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_rcc_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_rcc_ex.o b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc_ex.o new file mode 100644 index 0000000..5b5bea7 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_rcc_ex.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_tim.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_tim.crf new file mode 100644 index 0000000..6ee4cd5 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_tim.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_tim.d b/MDK-ARM/FDCAN/stm32h7xx_hal_tim.d new file mode 100644 index 0000000..324831c --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_tim.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_tim.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_tim.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_tim.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_tim.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_tim.o b/MDK-ARM/FDCAN/stm32h7xx_hal_tim.o new file mode 100644 index 0000000..898d466 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_tim.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_tim_ex.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_tim_ex.crf new file mode 100644 index 0000000..9d1475f Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_tim_ex.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_tim_ex.d b/MDK-ARM/FDCAN/stm32h7xx_hal_tim_ex.d new file mode 100644 index 0000000..3fe791a --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_tim_ex.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_tim_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_tim_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_tim_ex.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_tim_ex.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_tim_ex.o b/MDK-ARM/FDCAN/stm32h7xx_hal_tim_ex.o new file mode 100644 index 0000000..9f9d1f0 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_tim_ex.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_timebase_tim.crf b/MDK-ARM/FDCAN/stm32h7xx_hal_timebase_tim.crf new file mode 100644 index 0000000..68d6dfe Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_timebase_tim.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_timebase_tim.d b/MDK-ARM/FDCAN/stm32h7xx_hal_timebase_tim.d new file mode 100644 index 0000000..dc67015 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_hal_timebase_tim.d @@ -0,0 +1,36 @@ +fdcan\stm32h7xx_hal_timebase_tim.o: ../Core/Src/stm32h7xx_hal_timebase_tim.c +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_hal_timebase_tim.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_hal_timebase_tim.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_hal_timebase_tim.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_hal_timebase_tim.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_hal_timebase_tim.o b/MDK-ARM/FDCAN/stm32h7xx_hal_timebase_tim.o new file mode 100644 index 0000000..871c80a Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_hal_timebase_tim.o differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_it.crf b/MDK-ARM/FDCAN/stm32h7xx_it.crf new file mode 100644 index 0000000..0e2390f Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_it.crf differ diff --git a/MDK-ARM/FDCAN/stm32h7xx_it.d b/MDK-ARM/FDCAN/stm32h7xx_it.d new file mode 100644 index 0000000..4d253c3 --- /dev/null +++ b/MDK-ARM/FDCAN/stm32h7xx_it.d @@ -0,0 +1,38 @@ +fdcan\stm32h7xx_it.o: ../Core/Src/stm32h7xx_it.c +fdcan\stm32h7xx_it.o: ../Core/Inc/main.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_it.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\stm32h7xx_it.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\stm32h7xx_it.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\stm32h7xx_it.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\stm32h7xx_it.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stm32h7xx_it.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\stm32h7xx_it.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\stm32h7xx_it.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\stm32h7xx_it.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\stm32h7xx_it.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\stm32h7xx_it.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stm32h7xx_it.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\stm32h7xx_it.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h +fdcan\stm32h7xx_it.o: ../Core/Inc/stm32h7xx_it.h diff --git a/MDK-ARM/FDCAN/stm32h7xx_it.o b/MDK-ARM/FDCAN/stm32h7xx_it.o new file mode 100644 index 0000000..57e7753 Binary files /dev/null and b/MDK-ARM/FDCAN/stm32h7xx_it.o differ diff --git a/MDK-ARM/FDCAN/stream_buffer.crf b/MDK-ARM/FDCAN/stream_buffer.crf new file mode 100644 index 0000000..46aa232 Binary files /dev/null and b/MDK-ARM/FDCAN/stream_buffer.crf differ diff --git a/MDK-ARM/FDCAN/stream_buffer.d b/MDK-ARM/FDCAN/stream_buffer.d new file mode 100644 index 0000000..15d31d8 --- /dev/null +++ b/MDK-ARM/FDCAN/stream_buffer.d @@ -0,0 +1,14 @@ +fdcan\stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c +fdcan\stream_buffer.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\stream_buffer.o: D:\cangming\ARM\ARMCC\Bin\..\include\string.h +fdcan\stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\stream_buffer.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\stream_buffer.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +fdcan\stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h diff --git a/MDK-ARM/FDCAN/stream_buffer.o b/MDK-ARM/FDCAN/stream_buffer.o new file mode 100644 index 0000000..056530b Binary files /dev/null and b/MDK-ARM/FDCAN/stream_buffer.o differ diff --git a/MDK-ARM/FDCAN/system_stm32h7xx.crf b/MDK-ARM/FDCAN/system_stm32h7xx.crf new file mode 100644 index 0000000..885fc8f Binary files /dev/null and b/MDK-ARM/FDCAN/system_stm32h7xx.crf differ diff --git a/MDK-ARM/FDCAN/system_stm32h7xx.d b/MDK-ARM/FDCAN/system_stm32h7xx.d new file mode 100644 index 0000000..5fb68d0 --- /dev/null +++ b/MDK-ARM/FDCAN/system_stm32h7xx.d @@ -0,0 +1,36 @@ +fdcan\system_stm32h7xx.o: ../Core/Src/system_stm32h7xx.c +fdcan\system_stm32h7xx.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\system_stm32h7xx.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\system_stm32h7xx.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\system_stm32h7xx.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\system_stm32h7xx.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\system_stm32h7xx.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\system_stm32h7xx.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\system_stm32h7xx.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\system_stm32h7xx.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\system_stm32h7xx.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\system_stm32h7xx.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\system_stm32h7xx.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\system_stm32h7xx.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\system_stm32h7xx.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h diff --git a/MDK-ARM/FDCAN/system_stm32h7xx.o b/MDK-ARM/FDCAN/system_stm32h7xx.o new file mode 100644 index 0000000..021bb8d Binary files /dev/null and b/MDK-ARM/FDCAN/system_stm32h7xx.o differ diff --git a/MDK-ARM/FDCAN/tasks.crf b/MDK-ARM/FDCAN/tasks.crf new file mode 100644 index 0000000..08b6bac Binary files /dev/null and b/MDK-ARM/FDCAN/tasks.crf differ diff --git a/MDK-ARM/FDCAN/tasks.d b/MDK-ARM/FDCAN/tasks.d new file mode 100644 index 0000000..aca8383 --- /dev/null +++ b/MDK-ARM/FDCAN/tasks.d @@ -0,0 +1,16 @@ +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/tasks.c +fdcan\tasks.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdlib.h +fdcan\tasks.o: D:\cangming\ARM\ARMCC\Bin\..\include\string.h +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\tasks.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\tasks.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\tasks.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +fdcan\tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h diff --git a/MDK-ARM/FDCAN/tasks.o b/MDK-ARM/FDCAN/tasks.o new file mode 100644 index 0000000..a124364 Binary files /dev/null and b/MDK-ARM/FDCAN/tasks.o differ diff --git a/MDK-ARM/FDCAN/time.crf b/MDK-ARM/FDCAN/time.crf new file mode 100644 index 0000000..0e020ef Binary files /dev/null and b/MDK-ARM/FDCAN/time.crf differ diff --git a/MDK-ARM/FDCAN/time.d b/MDK-ARM/FDCAN/time.d new file mode 100644 index 0000000..0ac571d --- /dev/null +++ b/MDK-ARM/FDCAN/time.d @@ -0,0 +1,49 @@ +fdcan\time.o: ..\User\bsp\time.c +fdcan\time.o: ../User/bsp/time.h +fdcan\time.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\time.o: ../User/bsp/bsp.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\time.o: ../Core/Inc/stm32h7xx_hal_conf.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +fdcan\time.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h +fdcan\time.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +fdcan\time.o: ../Drivers/CMSIS/Include/core_cm7.h +fdcan\time.o: ../Drivers/CMSIS/Include/cmsis_version.h +fdcan\time.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +fdcan\time.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +fdcan\time.o: ../Drivers/CMSIS/Include/mpu_armv7.h +fdcan\time.o: ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +fdcan\time.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\time.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +fdcan\time.o: ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h +fdcan\time.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h +fdcan\time.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\time.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\time.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\time.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\time.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\time.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\time.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\time.o: ../Core/Inc/main.h +fdcan\time.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\time.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h diff --git a/MDK-ARM/FDCAN/time.o b/MDK-ARM/FDCAN/time.o new file mode 100644 index 0000000..5acfcad Binary files /dev/null and b/MDK-ARM/FDCAN/time.o differ diff --git a/MDK-ARM/FDCAN/timers.crf b/MDK-ARM/FDCAN/timers.crf new file mode 100644 index 0000000..44ac3c4 Binary files /dev/null and b/MDK-ARM/FDCAN/timers.crf differ diff --git a/MDK-ARM/FDCAN/timers.d b/MDK-ARM/FDCAN/timers.d new file mode 100644 index 0000000..071f9b9 --- /dev/null +++ b/MDK-ARM/FDCAN/timers.d @@ -0,0 +1,15 @@ +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/timers.c +fdcan\timers.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdlib.h +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\timers.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\timers.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\timers.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h +fdcan\timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h diff --git a/MDK-ARM/FDCAN/timers.o b/MDK-ARM/FDCAN/timers.o new file mode 100644 index 0000000..8e3863f Binary files /dev/null and b/MDK-ARM/FDCAN/timers.o differ diff --git a/MDK-ARM/FDCAN/user_math.crf b/MDK-ARM/FDCAN/user_math.crf new file mode 100644 index 0000000..9d1152c Binary files /dev/null and b/MDK-ARM/FDCAN/user_math.crf differ diff --git a/MDK-ARM/FDCAN/user_math.d b/MDK-ARM/FDCAN/user_math.d new file mode 100644 index 0000000..e48db89 --- /dev/null +++ b/MDK-ARM/FDCAN/user_math.d @@ -0,0 +1,8 @@ +fdcan\user_math.o: ..\User\component\user_math.c +fdcan\user_math.o: ..\User\component\user_math.h +fdcan\user_math.o: D:\cangming\ARM\ARMCC\Bin\..\include\float.h +fdcan\user_math.o: D:\cangming\ARM\ARMCC\Bin\..\include\math.h +fdcan\user_math.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdbool.h +fdcan\user_math.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\user_math.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\user_math.o: D:\cangming\ARM\ARMCC\Bin\..\include\string.h diff --git a/MDK-ARM/FDCAN/user_math.o b/MDK-ARM/FDCAN/user_math.o new file mode 100644 index 0000000..415927d Binary files /dev/null and b/MDK-ARM/FDCAN/user_math.o differ diff --git a/MDK-ARM/FDCAN/user_task.crf b/MDK-ARM/FDCAN/user_task.crf new file mode 100644 index 0000000..1084963 Binary files /dev/null and b/MDK-ARM/FDCAN/user_task.crf differ diff --git a/MDK-ARM/FDCAN/user_task.d b/MDK-ARM/FDCAN/user_task.d new file mode 100644 index 0000000..a9c9240 --- /dev/null +++ b/MDK-ARM/FDCAN/user_task.d @@ -0,0 +1,14 @@ +fdcan\user_task.o: ..\User\task\user_task.c +fdcan\user_task.o: ../User/task/user_task.h +fdcan\user_task.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h +fdcan\user_task.o: D:\cangming\ARM\ARMCC\Bin\..\include\stdint.h +fdcan\user_task.o: D:\cangming\ARM\ARMCC\Bin\..\include\stddef.h +fdcan\user_task.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +fdcan\user_task.o: ../Core/Inc/FreeRTOSConfig.h +fdcan\user_task.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +fdcan\user_task.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +fdcan\user_task.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +fdcan\user_task.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +fdcan\user_task.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +fdcan\user_task.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +fdcan\user_task.o: ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h diff --git a/MDK-ARM/FDCAN/user_task.o b/MDK-ARM/FDCAN/user_task.o new file mode 100644 index 0000000..914bed2 Binary files /dev/null and b/MDK-ARM/FDCAN/user_task.o differ diff --git a/MDK-ARM/RTE/_FDCAN/RTE_Components.h b/MDK-ARM/RTE/_FDCAN/RTE_Components.h new file mode 100644 index 0000000..81c8a21 --- /dev/null +++ b/MDK-ARM/RTE/_FDCAN/RTE_Components.h @@ -0,0 +1,15 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'FDCAN' + * Target: 'FDCAN' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/MDK-ARM/startup_stm32h723xx.lst b/MDK-ARM/startup_stm32h723xx.lst new file mode 100644 index 0000000..0df8b0c --- /dev/null +++ b/MDK-ARM/startup_stm32h723xx.lst @@ -0,0 +1,2946 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************************************************* + ************************* + 2 00000000 ;* File Name : startup_stm32h723xx.s + 3 00000000 ;* @author MCD Application Team + 4 00000000 ;* Description : STM32H7xx devices vector table f + or MDK-ARM toolchain. + 5 00000000 ;* This module performs: + 6 00000000 ;* - Set the initial SP + 7 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 8 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 9 00000000 ;* - Branches to __main in the C li + brary (which eventually + 10 00000000 ;* calls main()). + 11 00000000 ;* After Reset the Cortex-M process + or is in Thread mode, + 12 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 13 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 14 00000000 ;******************************************************* + *********************** + 15 00000000 ;* @attention + 16 00000000 ;* + 17 00000000 ;* Copyright (c) 2019 STMicroelectronics. + 18 00000000 ;* All rights reserved. + 19 00000000 ;* + 20 00000000 ;* This software is licensed under terms that can be fou + nd in the LICENSE file + 21 00000000 ;* in the root directory of this software component. + 22 00000000 ;* If no LICENSE file comes with this software, it is pr + ovided AS-IS. + 23 00000000 ;* + 24 00000000 ;******************************************************* + ************************ + 25 00000000 + 26 00000000 ; Amount of memory (in bytes) allocated for Stack + 27 00000000 ; Tailor this value to your application needs + 28 00000000 ; Stack Configuration + 29 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 30 00000000 ; + 31 00000000 + 32 00000000 00000400 + Stack_Size + EQU 0x400 + 33 00000000 + 34 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 35 00000000 Stack_Mem + SPACE Stack_Size + 36 00000400 __initial_sp + 37 00000400 + 38 00000400 + 39 00000400 ; Heap Configuration + 40 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 41 00000400 ; + 42 00000400 + 43 00000400 00000200 + Heap_Size + + + +ARM Macro Assembler Page 2 + + + EQU 0x200 + 44 00000400 + 45 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 46 00000000 __heap_base + 47 00000000 Heap_Mem + SPACE Heap_Size + 48 00000200 __heap_limit + 49 00000200 + 50 00000200 PRESERVE8 + 51 00000200 THUMB + 52 00000200 + 53 00000200 + 54 00000200 ; Vector Table Mapped to Address 0 at Reset + 55 00000200 AREA RESET, DATA, READONLY + 56 00000000 EXPORT __Vectors + 57 00000000 EXPORT __Vectors_End + 58 00000000 EXPORT __Vectors_Size + 59 00000000 + 60 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 61 00000004 00000000 DCD Reset_Handler ; Reset Handler + 62 00000008 00000000 DCD NMI_Handler ; NMI Handler + 63 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 64 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 65 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 66 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 67 0000001C 00000000 DCD 0 ; Reserved + 68 00000020 00000000 DCD 0 ; Reserved + 69 00000024 00000000 DCD 0 ; Reserved + 70 00000028 00000000 DCD 0 ; Reserved + 71 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 72 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 73 00000034 00000000 DCD 0 ; Reserved + 74 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 75 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 76 00000040 + 77 00000040 ; External Interrupts + 78 00000040 00000000 DCD WWDG_IRQHandler ; Window WatchD + og interrupt ( wwdg + 1_it) + + + 79 00000044 00000000 DCD PVD_AVD_IRQHandler ; PVD/AVD th + rough EXTI Line det + ection + + 80 00000048 00000000 DCD TAMP_STAMP_IRQHandler ; Tamper + and TimeStamps thro + + + +ARM Macro Assembler Page 3 + + + ugh the EXTI line + + 81 0000004C 00000000 DCD RTC_WKUP_IRQHandler ; RTC Wakeu + p through the EXTI + line + + 82 00000050 00000000 DCD FLASH_IRQHandler ; FLASH + + + 83 00000054 00000000 DCD RCC_IRQHandler ; RCC + + + 84 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line0 + + + + 85 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line1 + + + + 86 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line2 + + + + 87 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line3 + + + + 88 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line4 + 89 0000006C 00000000 DCD DMA1_Stream0_IRQHandler + ; DMA1 Stream 0 + 90 00000070 00000000 DCD DMA1_Stream1_IRQHandler ; DMA1 + Stream 1 + + + 91 00000074 00000000 DCD DMA1_Stream2_IRQHandler ; DMA1 + Stream 2 + + + 92 00000078 00000000 DCD DMA1_Stream3_IRQHandler ; DMA1 + Stream 3 + + + 93 0000007C 00000000 DCD DMA1_Stream4_IRQHandler ; DMA1 + Stream 4 + + + 94 00000080 00000000 DCD DMA1_Stream5_IRQHandler ; DMA1 + Stream 5 + + + 95 00000084 00000000 DCD DMA1_Stream6_IRQHandler + ; DMA1 Stream 6 + 96 00000088 00000000 DCD ADC_IRQHandler ; ADC1, ADC2 + + + 97 0000008C 00000000 DCD FDCAN1_IT0_IRQHandler ; FDCAN1 + interrupt line 0 + + + + +ARM Macro Assembler Page 4 + + + + 98 00000090 00000000 DCD FDCAN2_IT0_IRQHandler ; FDCAN2 + interrupt line 0 + + + 99 00000094 00000000 DCD FDCAN1_IT1_IRQHandler ; FDCAN1 + interrupt line 1 + + + 100 00000098 00000000 DCD FDCAN2_IT1_IRQHandler ; FDCAN2 + interrupt line 1 + + + + 101 0000009C 00000000 DCD EXTI9_5_IRQHandler ; External L + ine[9:5]s + + + 102 000000A0 00000000 DCD TIM1_BRK_IRQHandler ; TIM1 Brea + k interrupt + + 103 000000A4 00000000 DCD TIM1_UP_IRQHandler ; TIM1 Updat + e Interrupt + + 104 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1 + Trigger and Commuta + tion Interrupt + 105 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + + + 106 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 + + + 107 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 + + + 108 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 + + + 109 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event + + + + 110 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error + + + + 111 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event + + + + 112 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error + + + + 113 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 + + + + + +ARM Macro Assembler Page 5 + + + 114 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 + + + 115 000000D4 00000000 DCD USART1_IRQHandler ; USART1 + + + 116 000000D8 00000000 DCD USART2_IRQHandler ; USART2 + + + 117 000000DC 00000000 DCD USART3_IRQHandler ; USART3 + + + 118 000000E0 00000000 DCD EXTI15_10_IRQHandler ; External + Line[15:10] + 119 000000E4 00000000 DCD RTC_Alarm_IRQHandler ; RTC Alar + m (A and B) through + EXTI Line + 120 000000E8 00000000 DCD 0 ; Reserved + + + 121 000000EC 00000000 DCD TIM8_BRK_TIM12_IRQHandler ; TIM + 8 Break Interrupt a + nd TIM12 global int + errupt + + 122 000000F0 00000000 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 + Update Interrupt a + nd TIM13 global int + errupt + 123 000000F4 00000000 DCD TIM8_TRG_COM_TIM14_IRQHandler ; + TIM8 Trigger and C + ommutation Interrup + t and TIM14 global + interrupt + 124 000000F8 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu + re Compare Interrup + t + 125 000000FC 00000000 DCD DMA1_Stream7_IRQHandler ; DMA1 + Stream7 + + + 126 00000100 00000000 DCD FMC_IRQHandler ; FMC + + 127 00000104 00000000 DCD SDMMC1_IRQHandler ; SDMMC1 + + + 128 00000108 00000000 DCD TIM5_IRQHandler ; TIM5 + + + 129 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3 + + + 130 00000110 00000000 DCD UART4_IRQHandler ; UART4 + + + 131 00000114 00000000 DCD UART5_IRQHandler ; UART5 + + + 132 00000118 00000000 DCD TIM6_DAC_IRQHandler ; TIM6 and + + + +ARM Macro Assembler Page 6 + + + DAC1&2 underrun err + ors + 133 0000011C 00000000 DCD TIM7_IRQHandler + ; TIM7 + 134 00000120 00000000 DCD DMA2_Stream0_IRQHandler ; DMA2 + Stream 0 + + 135 00000124 00000000 DCD DMA2_Stream1_IRQHandler ; DMA2 + Stream 1 + + 136 00000128 00000000 DCD DMA2_Stream2_IRQHandler ; DMA2 + Stream 2 + + 137 0000012C 00000000 DCD DMA2_Stream3_IRQHandler ; DMA2 + Stream 3 + + 138 00000130 00000000 DCD DMA2_Stream4_IRQHandler ; DMA2 + Stream 4 + + 139 00000134 00000000 DCD ETH_IRQHandler ; Ethernet + + 140 00000138 00000000 DCD ETH_WKUP_IRQHandler ; Ethernet + Wakeup through EXTI + line + + 141 0000013C 00000000 DCD FDCAN_CAL_IRQHandler ; FDCAN ca + libration unit inte + rrupt + + 142 00000140 00000000 DCD 0 ; Reserved + + + 143 00000144 00000000 DCD 0 ; Reserved + 144 00000148 00000000 DCD 0 ; Reserved + 145 0000014C 00000000 DCD 0 ; Reserved + + 146 00000150 00000000 DCD DMA2_Stream5_IRQHandler ; DMA2 + Stream 5 + + 147 00000154 00000000 DCD DMA2_Stream6_IRQHandler ; DMA2 + Stream 6 + + 148 00000158 00000000 DCD DMA2_Stream7_IRQHandler ; DMA2 + Stream 7 + + 149 0000015C 00000000 DCD USART6_IRQHandler ; USART6 + + + 150 00000160 00000000 DCD I2C3_EV_IRQHandler ; I2C3 event + + + 151 00000164 00000000 DCD I2C3_ER_IRQHandler ; I2C3 error + + + 152 00000168 00000000 DCD OTG_HS_EP1_OUT_IRQHandler ; USB + OTG HS End Point 1 + Out + + 153 0000016C 00000000 DCD OTG_HS_EP1_IN_IRQHandler ; USB + + + +ARM Macro Assembler Page 7 + + + OTG HS End Point 1 + In + + 154 00000170 00000000 DCD OTG_HS_WKUP_IRQHandler ; USB OT + G HS Wakeup through + EXTI + + 155 00000174 00000000 DCD OTG_HS_IRQHandler ; USB OTG HS + + + 156 00000178 00000000 DCD DCMI_PSSI_IRQHandler ; DCMI, PS + SI + + 157 0000017C 00000000 DCD 0 ; Reserved + + + 158 00000180 00000000 DCD RNG_IRQHandler ; Rng + 159 00000184 00000000 DCD FPU_IRQHandler ; FPU + 160 00000188 00000000 DCD UART7_IRQHandler ; UART7 + 161 0000018C 00000000 DCD UART8_IRQHandler ; UART8 + 162 00000190 00000000 DCD SPI4_IRQHandler ; SPI4 + 163 00000194 00000000 DCD SPI5_IRQHandler ; SPI5 + 164 00000198 00000000 DCD SPI6_IRQHandler ; SPI6 + 165 0000019C 00000000 DCD SAI1_IRQHandler ; SAI1 + 166 000001A0 00000000 DCD LTDC_IRQHandler ; LTDC + 167 000001A4 00000000 DCD LTDC_ER_IRQHandler ; LTDC error + + 168 000001A8 00000000 DCD DMA2D_IRQHandler ; DMA2D + 169 000001AC 00000000 DCD 0 ; Reserved + 170 000001B0 00000000 DCD OCTOSPI1_IRQHandler ; OCTOSPI1 + 171 000001B4 00000000 DCD LPTIM1_IRQHandler ; LPTIM1 + 172 000001B8 00000000 DCD CEC_IRQHandler ; HDMI_CEC + 173 000001BC 00000000 DCD I2C4_EV_IRQHandler ; I2C4 Event + + + 174 000001C0 00000000 DCD I2C4_ER_IRQHandler + ; I2C4 Error + 175 000001C4 00000000 DCD SPDIF_RX_IRQHandler ; SPDIF_RX + 176 000001C8 00000000 DCD 0 ; Reserved + + 177 000001CC 00000000 DCD 0 ; Reserved + + 178 000001D0 00000000 DCD 0 ; Reserved + + 179 000001D4 00000000 DCD 0 ; Reserved + + 180 000001D8 00000000 DCD DMAMUX1_OVR_IRQHandler ; DMAMUX + 1 Overrun interrupt + + 181 000001DC 00000000 DCD 0 ; Reserved + + + 182 000001E0 00000000 DCD 0 ; Reserved + + + 183 000001E4 00000000 DCD 0 ; Reserved + + + 184 000001E8 00000000 DCD 0 ; Reserved + + + +ARM Macro Assembler Page 8 + + + + + 185 000001EC 00000000 DCD 0 ; Reserved + + + 186 000001F0 00000000 DCD 0 ; Reserved + + + 187 000001F4 00000000 DCD 0 ; Reserved + 188 000001F8 00000000 DCD DFSDM1_FLT0_IRQHandler ; DFSDM + Filter0 Interrupt + + 189 000001FC 00000000 DCD DFSDM1_FLT1_IRQHandler ; DFSDM + Filter1 Interrupt + + + + 190 00000200 00000000 DCD DFSDM1_FLT2_IRQHandler ; DFSDM + Filter2 Interrupt + + + + 191 00000204 00000000 DCD DFSDM1_FLT3_IRQHandler ; DFSDM + Filter3 Interrupt + + + + + + 192 00000208 00000000 DCD 0 ; Reserved + + + 193 0000020C 00000000 DCD SWPMI1_IRQHandler ; Serial Wire + Interface 1 global + interrupt + + 194 00000210 00000000 DCD TIM15_IRQHandler ; TIM15 global + Interrupt + + + 195 00000214 00000000 DCD TIM16_IRQHandler ; TIM16 global + Interrupt + + + 196 00000218 00000000 DCD TIM17_IRQHandler ; TIM17 global + Interrupt + + + 197 0000021C 00000000 DCD MDIOS_WKUP_IRQHandler ; MDIOS W + akeup Interrupt + + + + 198 00000220 00000000 DCD MDIOS_IRQHandler ; MDIOS global + Interrupt + + + 199 00000224 00000000 DCD 0 ; Reserved + + + + +ARM Macro Assembler Page 9 + + + + 200 00000228 00000000 DCD MDMA_IRQHandler ; MDMA global I + nterrupt + + + 201 0000022C 00000000 DCD 0 ; Reserved + + + + 202 00000230 00000000 DCD SDMMC2_IRQHandler ; SDMMC2 glob + al Interrupt + + + 203 00000234 00000000 DCD HSEM1_IRQHandler ; HSEM1 global + Interrupt + + + 204 00000238 00000000 DCD 0 ; Reserved + + + 205 0000023C 00000000 DCD ADC3_IRQHandler ; ADC3 global I + nterrupt + + + 206 00000240 00000000 DCD DMAMUX2_OVR_IRQHandler ; DMAMUX + Overrun interrupt + + + + 207 00000244 00000000 DCD BDMA_Channel0_IRQHandler ; BDMA + Channel 0 global I + nterrupt + + + 208 00000248 00000000 DCD BDMA_Channel1_IRQHandler ; BDMA + Channel 1 global I + nterrupt + + + 209 0000024C 00000000 DCD BDMA_Channel2_IRQHandler ; BDMA + Channel 2 global I + nterrupt + + + 210 00000250 00000000 DCD BDMA_Channel3_IRQHandler ; BDMA + Channel 3 global I + nterrupt + + + 211 00000254 00000000 DCD BDMA_Channel4_IRQHandler ; BDMA + Channel 4 global I + nterrupt + + + 212 00000258 00000000 DCD BDMA_Channel5_IRQHandler ; BDMA + Channel 5 global I + nterrupt + + + + + +ARM Macro Assembler Page 10 + + + 213 0000025C 00000000 DCD BDMA_Channel6_IRQHandler ; BDMA + Channel 6 global I + nterrupt + + + 214 00000260 00000000 DCD BDMA_Channel7_IRQHandler ; BDMA + Channel 7 global I + nterrupt + + + 215 00000264 00000000 DCD COMP1_IRQHandler ; COMP1 global + Interrupt + + + 216 00000268 00000000 DCD LPTIM2_IRQHandler ; LP TIM2 glo + bal interrupt + + + 217 0000026C 00000000 DCD LPTIM3_IRQHandler ; LP TIM3 glo + bal interrupt + + + 218 00000270 00000000 DCD LPTIM4_IRQHandler ; LP TIM4 glo + bal interrupt + + + 219 00000274 00000000 DCD LPTIM5_IRQHandler ; LP TIM5 glo + bal interrupt + + + 220 00000278 00000000 DCD LPUART1_IRQHandler ; LP UART1 i + nterrupt + + + 221 0000027C 00000000 DCD 0 ; Reserved + + + + + 222 00000280 00000000 DCD CRS_IRQHandler ; Clock Recovery + Global Interrupt + + + 223 00000284 00000000 DCD ECC_IRQHandler ; ECC diagnostic + Global Interrupt + + + + 224 00000288 00000000 DCD SAI4_IRQHandler ; SAI4 global i + nterrupt + + + 225 0000028C 00000000 DCD DTS_IRQHandler ; DTS interrupt + + + 226 00000290 00000000 DCD 0 ; Reserved + + + 227 00000294 00000000 DCD WAKEUP_PIN_IRQHandler ; Interru + + + +ARM Macro Assembler Page 11 + + + pt for all 6 wake-u + p pins + 228 00000298 00000000 DCD OCTOSPI2_IRQHandler ; OCTOSPI2 + Interrupt + 229 0000029C 00000000 DCD 0 ; Reserved + + 230 000002A0 00000000 DCD 0 ; Reserved + 231 000002A4 00000000 DCD FMAC_IRQHandler + ; FMAC Interrupt + 232 000002A8 00000000 DCD CORDIC_IRQHandler + ; CORDIC Interrupt + 233 000002AC 00000000 DCD UART9_IRQHandler + ; UART9 Interrupt + 234 000002B0 00000000 DCD USART10_IRQHandler + ; UART10 Interrupt + 235 000002B4 00000000 DCD I2C5_EV_IRQHandler ; I2C5 Event + Interrupt + 236 000002B8 00000000 DCD I2C5_ER_IRQHandler ; I2C5 Error + Interrupt + 237 000002BC 00000000 DCD FDCAN3_IT0_IRQHandler ; FDCAN3 + interrupt line 0 + 238 000002C0 00000000 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 + interrupt line 1 + 239 000002C4 00000000 DCD TIM23_IRQHandler ; TIM23 global + interrupt + 240 000002C8 00000000 DCD TIM24_IRQHandler ; TIM24 global + interrupt + 241 000002CC + 242 000002CC __Vectors_End + 243 000002CC + 244 000002CC 000002CC + __Vectors_Size + EQU __Vectors_End - __Vectors + 245 000002CC + 246 000002CC AREA |.text|, CODE, READONLY + 247 00000000 + 248 00000000 ; Reset handler + 249 00000000 Reset_Handler + PROC + 250 00000000 EXPORT Reset_Handler + [WEAK] + 251 00000000 IMPORT ExitRun0Mode + 252 00000000 IMPORT SystemInit + 253 00000000 IMPORT __main + 254 00000000 + 255 00000000 480A LDR R0, =ExitRun0Mode + 256 00000002 4780 BLX R0 + 257 00000004 480A LDR R0, =SystemInit + 258 00000006 4780 BLX R0 + 259 00000008 480A LDR R0, =__main + 260 0000000A 4700 BX R0 + 261 0000000C ENDP + 262 0000000C + 263 0000000C ; Dummy Exception Handlers (infinite loops which can be + modified) + 264 0000000C + 265 0000000C NMI_Handler + PROC + 266 0000000C EXPORT NMI_Handler + + + +ARM Macro Assembler Page 12 + + + [WEAK] + 267 0000000C E7FE B . + 268 0000000E ENDP + 270 0000000E HardFault_Handler + PROC + 271 0000000E EXPORT HardFault_Handler + [WEAK] + 272 0000000E E7FE B . + 273 00000010 ENDP + 275 00000010 MemManage_Handler + PROC + 276 00000010 EXPORT MemManage_Handler + [WEAK] + 277 00000010 E7FE B . + 278 00000012 ENDP + 280 00000012 BusFault_Handler + PROC + 281 00000012 EXPORT BusFault_Handler + [WEAK] + 282 00000012 E7FE B . + 283 00000014 ENDP + 285 00000014 UsageFault_Handler + PROC + 286 00000014 EXPORT UsageFault_Handler + [WEAK] + 287 00000014 E7FE B . + 288 00000016 ENDP + 289 00000016 SVC_Handler + PROC + 290 00000016 EXPORT SVC_Handler + [WEAK] + 291 00000016 E7FE B . + 292 00000018 ENDP + 294 00000018 DebugMon_Handler + PROC + 295 00000018 EXPORT DebugMon_Handler + [WEAK] + 296 00000018 E7FE B . + 297 0000001A ENDP + 298 0000001A PendSV_Handler + PROC + 299 0000001A EXPORT PendSV_Handler + [WEAK] + 300 0000001A E7FE B . + 301 0000001C ENDP + 302 0000001C SysTick_Handler + PROC + 303 0000001C EXPORT SysTick_Handler + [WEAK] + 304 0000001C E7FE B . + 305 0000001E ENDP + 306 0000001E + 307 0000001E Default_Handler + PROC + 308 0000001E + 309 0000001E EXPORT WWDG_IRQHandler + [WEAK] + 310 0000001E EXPORT PVD_AVD_IRQHandler + [WEAK] + + + +ARM Macro Assembler Page 13 + + + 311 0000001E EXPORT TAMP_STAMP_IRQHandler + [WEAK] + 312 0000001E EXPORT RTC_WKUP_IRQHandler + [WEAK] + 313 0000001E EXPORT FLASH_IRQHandler + [WEAK] + 314 0000001E EXPORT RCC_IRQHandler + [WEAK] + 315 0000001E EXPORT EXTI0_IRQHandler + [WEAK] + 316 0000001E EXPORT EXTI1_IRQHandler + [WEAK] + 317 0000001E EXPORT EXTI2_IRQHandler + [WEAK] + 318 0000001E EXPORT EXTI3_IRQHandler + [WEAK] + 319 0000001E EXPORT EXTI4_IRQHandler + [WEAK] + 320 0000001E EXPORT DMA1_Stream0_IRQHandler + [WEAK] + 321 0000001E EXPORT DMA1_Stream1_IRQHandler + [WEAK] + 322 0000001E EXPORT DMA1_Stream2_IRQHandler + [WEAK] + 323 0000001E EXPORT DMA1_Stream3_IRQHandler + [WEAK] + 324 0000001E EXPORT DMA1_Stream4_IRQHandler + [WEAK] + 325 0000001E EXPORT DMA1_Stream5_IRQHandler + [WEAK] + 326 0000001E EXPORT DMA1_Stream6_IRQHandler + [WEAK] + 327 0000001E EXPORT DMA1_Stream7_IRQHandler + [WEAK] + 328 0000001E EXPORT ADC_IRQHandler + [WEAK] + 329 0000001E EXPORT FDCAN1_IT0_IRQHandler + [WEAK] + 330 0000001E EXPORT FDCAN2_IT0_IRQHandler + [WEAK] + 331 0000001E EXPORT FDCAN1_IT1_IRQHandler + [WEAK] + 332 0000001E EXPORT FDCAN2_IT1_IRQHandler + [WEAK] + 333 0000001E EXPORT EXTI9_5_IRQHandler + [WEAK] + 334 0000001E EXPORT TIM1_BRK_IRQHandler + [WEAK] + 335 0000001E EXPORT TIM1_UP_IRQHandler + [WEAK] + 336 0000001E EXPORT TIM1_TRG_COM_IRQHandler + [WEAK] + 337 0000001E EXPORT TIM1_CC_IRQHandler + [WEAK] + 338 0000001E EXPORT TIM2_IRQHandler + [WEAK] + 339 0000001E EXPORT TIM3_IRQHandler + [WEAK] + 340 0000001E EXPORT TIM4_IRQHandler + + + +ARM Macro Assembler Page 14 + + + [WEAK] + 341 0000001E EXPORT I2C1_EV_IRQHandler + [WEAK] + 342 0000001E EXPORT I2C1_ER_IRQHandler + [WEAK] + 343 0000001E EXPORT I2C2_EV_IRQHandler + [WEAK] + 344 0000001E EXPORT I2C2_ER_IRQHandler + [WEAK] + 345 0000001E EXPORT SPI1_IRQHandler + [WEAK] + 346 0000001E EXPORT SPI2_IRQHandler + [WEAK] + 347 0000001E EXPORT USART1_IRQHandler + [WEAK] + 348 0000001E EXPORT USART2_IRQHandler + [WEAK] + 349 0000001E EXPORT USART3_IRQHandler + [WEAK] + 350 0000001E EXPORT EXTI15_10_IRQHandler + [WEAK] + 351 0000001E EXPORT RTC_Alarm_IRQHandler + [WEAK] + 352 0000001E EXPORT TIM8_BRK_TIM12_IRQHandler + [WEAK] + 353 0000001E EXPORT TIM8_UP_TIM13_IRQHandler + [WEAK] + 354 0000001E EXPORT TIM8_TRG_COM_TIM14_IRQHandler + [WEAK] + 355 0000001E EXPORT TIM8_CC_IRQHandler + [WEAK] + 356 0000001E EXPORT DMA1_Stream7_IRQHandler + [WEAK] + 357 0000001E EXPORT FMC_IRQHandler + [WEAK] + 358 0000001E EXPORT SDMMC1_IRQHandler + [WEAK] + 359 0000001E EXPORT TIM5_IRQHandler + [WEAK] + 360 0000001E EXPORT SPI3_IRQHandler + [WEAK] + 361 0000001E EXPORT UART4_IRQHandler + [WEAK] + 362 0000001E EXPORT UART5_IRQHandler + [WEAK] + 363 0000001E EXPORT TIM6_DAC_IRQHandler + [WEAK] + 364 0000001E EXPORT TIM7_IRQHandler + [WEAK] + 365 0000001E EXPORT DMA2_Stream0_IRQHandler + [WEAK] + 366 0000001E EXPORT DMA2_Stream1_IRQHandler + [WEAK] + 367 0000001E EXPORT DMA2_Stream2_IRQHandler + [WEAK] + 368 0000001E EXPORT DMA2_Stream3_IRQHandler + [WEAK] + 369 0000001E EXPORT DMA2_Stream4_IRQHandler + [WEAK] + + + +ARM Macro Assembler Page 15 + + + 370 0000001E EXPORT ETH_IRQHandler + [WEAK] + 371 0000001E EXPORT ETH_WKUP_IRQHandler + [WEAK] + 372 0000001E EXPORT FDCAN_CAL_IRQHandler + [WEAK] + 373 0000001E EXPORT DMA2_Stream5_IRQHandler + [WEAK] + 374 0000001E EXPORT DMA2_Stream6_IRQHandler + [WEAK] + 375 0000001E EXPORT DMA2_Stream7_IRQHandler + [WEAK] + 376 0000001E EXPORT USART6_IRQHandler + [WEAK] + 377 0000001E EXPORT I2C3_EV_IRQHandler + [WEAK] + 378 0000001E EXPORT I2C3_ER_IRQHandler + [WEAK] + 379 0000001E EXPORT OTG_HS_EP1_OUT_IRQHandler + [WEAK] + 380 0000001E EXPORT OTG_HS_EP1_IN_IRQHandler + [WEAK] + 381 0000001E EXPORT OTG_HS_WKUP_IRQHandler + [WEAK] + 382 0000001E EXPORT OTG_HS_IRQHandler + [WEAK] + 383 0000001E EXPORT DCMI_PSSI_IRQHandler + [WEAK] + 384 0000001E EXPORT RNG_IRQHandler + [WEAK] + 385 0000001E EXPORT FPU_IRQHandler + [WEAK] + 386 0000001E EXPORT UART7_IRQHandler + [WEAK] + 387 0000001E EXPORT UART8_IRQHandler + [WEAK] + 388 0000001E EXPORT SPI4_IRQHandler + [WEAK] + 389 0000001E EXPORT SPI5_IRQHandler + [WEAK] + 390 0000001E EXPORT SPI6_IRQHandler + [WEAK] + 391 0000001E EXPORT SAI1_IRQHandler + [WEAK] + 392 0000001E EXPORT LTDC_IRQHandler + [WEAK] + 393 0000001E EXPORT LTDC_ER_IRQHandler + [WEAK] + 394 0000001E EXPORT DMA2D_IRQHandler + [WEAK] + 395 0000001E EXPORT OCTOSPI1_IRQHandler + [WEAK] + 396 0000001E EXPORT LPTIM1_IRQHandler + [WEAK] + 397 0000001E EXPORT CEC_IRQHandler + [WEAK] + 398 0000001E EXPORT I2C4_EV_IRQHandler + [WEAK] + 399 0000001E EXPORT I2C4_ER_IRQHandler + + + +ARM Macro Assembler Page 16 + + + [WEAK] + 400 0000001E EXPORT SPDIF_RX_IRQHandler + [WEAK] + 401 0000001E EXPORT DMAMUX1_OVR_IRQHandler + [WEAK] + 402 0000001E EXPORT DFSDM1_FLT0_IRQHandler + [WEAK] + 403 0000001E EXPORT DFSDM1_FLT1_IRQHandler + [WEAK] + 404 0000001E EXPORT DFSDM1_FLT2_IRQHandler + [WEAK] + 405 0000001E EXPORT DFSDM1_FLT3_IRQHandler + [WEAK] + 406 0000001E EXPORT SWPMI1_IRQHandler + [WEAK] + 407 0000001E EXPORT TIM15_IRQHandler + [WEAK] + 408 0000001E EXPORT TIM16_IRQHandler + [WEAK] + 409 0000001E EXPORT TIM17_IRQHandler + [WEAK] + 410 0000001E EXPORT MDIOS_WKUP_IRQHandler + [WEAK] + 411 0000001E EXPORT MDIOS_IRQHandler + [WEAK] + 412 0000001E EXPORT MDMA_IRQHandler + [WEAK] + 413 0000001E EXPORT SDMMC2_IRQHandler + [WEAK] + 414 0000001E EXPORT HSEM1_IRQHandler + [WEAK] + 415 0000001E EXPORT ADC3_IRQHandler + [WEAK] + 416 0000001E EXPORT DMAMUX2_OVR_IRQHandler + [WEAK] + 417 0000001E EXPORT BDMA_Channel0_IRQHandler + [WEAK] + 418 0000001E EXPORT BDMA_Channel1_IRQHandler + [WEAK] + 419 0000001E EXPORT BDMA_Channel2_IRQHandler + [WEAK] + 420 0000001E EXPORT BDMA_Channel3_IRQHandler + [WEAK] + 421 0000001E EXPORT BDMA_Channel4_IRQHandler + [WEAK] + 422 0000001E EXPORT BDMA_Channel5_IRQHandler + [WEAK] + 423 0000001E EXPORT BDMA_Channel6_IRQHandler + [WEAK] + 424 0000001E EXPORT BDMA_Channel7_IRQHandler + [WEAK] + 425 0000001E EXPORT COMP1_IRQHandler + [WEAK] + 426 0000001E EXPORT LPTIM2_IRQHandler + [WEAK] + 427 0000001E EXPORT LPTIM3_IRQHandler + [WEAK] + 428 0000001E EXPORT LPTIM4_IRQHandler + [WEAK] + + + +ARM Macro Assembler Page 17 + + + 429 0000001E EXPORT LPTIM5_IRQHandler + [WEAK] + 430 0000001E EXPORT LPUART1_IRQHandler + [WEAK] + 431 0000001E EXPORT CRS_IRQHandler + [WEAK] + 432 0000001E EXPORT ECC_IRQHandler + [WEAK] + 433 0000001E EXPORT SAI4_IRQHandler + [WEAK] + 434 0000001E EXPORT DTS_IRQHandler + [WEAK] + 435 0000001E EXPORT WAKEUP_PIN_IRQHandler + [WEAK] + 436 0000001E EXPORT OCTOSPI2_IRQHandler + [WEAK] + 437 0000001E EXPORT FMAC_IRQHandler + [WEAK] + 438 0000001E EXPORT CORDIC_IRQHandler + [WEAK] + 439 0000001E EXPORT UART9_IRQHandler + [WEAK] + 440 0000001E EXPORT USART10_IRQHandler + [WEAK] + 441 0000001E EXPORT I2C5_EV_IRQHandler + [WEAK] + 442 0000001E EXPORT I2C5_ER_IRQHandler + [WEAK] + 443 0000001E EXPORT FDCAN3_IT0_IRQHandler + [WEAK] + 444 0000001E EXPORT FDCAN3_IT1_IRQHandler + [WEAK] + 445 0000001E EXPORT TIM23_IRQHandler + [WEAK] + 446 0000001E EXPORT TIM24_IRQHandler + [WEAK] + 447 0000001E + 448 0000001E WWDG_IRQHandler + 449 0000001E PVD_AVD_IRQHandler + 450 0000001E TAMP_STAMP_IRQHandler + 451 0000001E RTC_WKUP_IRQHandler + 452 0000001E FLASH_IRQHandler + 453 0000001E RCC_IRQHandler + 454 0000001E EXTI0_IRQHandler + 455 0000001E EXTI1_IRQHandler + 456 0000001E EXTI2_IRQHandler + 457 0000001E EXTI3_IRQHandler + 458 0000001E EXTI4_IRQHandler + 459 0000001E DMA1_Stream0_IRQHandler + 460 0000001E DMA1_Stream1_IRQHandler + 461 0000001E DMA1_Stream2_IRQHandler + 462 0000001E DMA1_Stream3_IRQHandler + 463 0000001E DMA1_Stream4_IRQHandler + 464 0000001E DMA1_Stream5_IRQHandler + 465 0000001E DMA1_Stream6_IRQHandler + 466 0000001E ADC_IRQHandler + 467 0000001E FDCAN1_IT0_IRQHandler + 468 0000001E FDCAN2_IT0_IRQHandler + 469 0000001E FDCAN1_IT1_IRQHandler + + + +ARM Macro Assembler Page 18 + + + 470 0000001E FDCAN2_IT1_IRQHandler + 471 0000001E EXTI9_5_IRQHandler + 472 0000001E TIM1_BRK_IRQHandler + 473 0000001E TIM1_UP_IRQHandler + 474 0000001E TIM1_TRG_COM_IRQHandler + 475 0000001E TIM1_CC_IRQHandler + 476 0000001E TIM2_IRQHandler + 477 0000001E TIM3_IRQHandler + 478 0000001E TIM4_IRQHandler + 479 0000001E I2C1_EV_IRQHandler + 480 0000001E I2C1_ER_IRQHandler + 481 0000001E I2C2_EV_IRQHandler + 482 0000001E I2C2_ER_IRQHandler + 483 0000001E SPI1_IRQHandler + 484 0000001E SPI2_IRQHandler + 485 0000001E USART1_IRQHandler + 486 0000001E USART2_IRQHandler + 487 0000001E USART3_IRQHandler + 488 0000001E EXTI15_10_IRQHandler + 489 0000001E RTC_Alarm_IRQHandler + 490 0000001E TIM8_BRK_TIM12_IRQHandler + 491 0000001E TIM8_UP_TIM13_IRQHandler + 492 0000001E TIM8_TRG_COM_TIM14_IRQHandler + 493 0000001E TIM8_CC_IRQHandler + 494 0000001E DMA1_Stream7_IRQHandler + 495 0000001E FMC_IRQHandler + 496 0000001E SDMMC1_IRQHandler + 497 0000001E TIM5_IRQHandler + 498 0000001E SPI3_IRQHandler + 499 0000001E UART4_IRQHandler + 500 0000001E UART5_IRQHandler + 501 0000001E TIM6_DAC_IRQHandler + 502 0000001E TIM7_IRQHandler + 503 0000001E DMA2_Stream0_IRQHandler + 504 0000001E DMA2_Stream1_IRQHandler + 505 0000001E DMA2_Stream2_IRQHandler + 506 0000001E DMA2_Stream3_IRQHandler + 507 0000001E DMA2_Stream4_IRQHandler + 508 0000001E ETH_IRQHandler + 509 0000001E ETH_WKUP_IRQHandler + 510 0000001E FDCAN_CAL_IRQHandler + 511 0000001E DMA2_Stream5_IRQHandler + 512 0000001E DMA2_Stream6_IRQHandler + 513 0000001E DMA2_Stream7_IRQHandler + 514 0000001E USART6_IRQHandler + 515 0000001E I2C3_EV_IRQHandler + 516 0000001E I2C3_ER_IRQHandler + 517 0000001E OTG_HS_EP1_OUT_IRQHandler + 518 0000001E OTG_HS_EP1_IN_IRQHandler + 519 0000001E OTG_HS_WKUP_IRQHandler + 520 0000001E OTG_HS_IRQHandler + 521 0000001E DCMI_PSSI_IRQHandler + 522 0000001E RNG_IRQHandler + 523 0000001E FPU_IRQHandler + 524 0000001E UART7_IRQHandler + 525 0000001E UART8_IRQHandler + 526 0000001E SPI4_IRQHandler + 527 0000001E SPI5_IRQHandler + 528 0000001E SPI6_IRQHandler + + + +ARM Macro Assembler Page 19 + + + 529 0000001E SAI1_IRQHandler + 530 0000001E LTDC_IRQHandler + 531 0000001E LTDC_ER_IRQHandler + 532 0000001E DMA2D_IRQHandler + 533 0000001E OCTOSPI1_IRQHandler + 534 0000001E LPTIM1_IRQHandler + 535 0000001E CEC_IRQHandler + 536 0000001E I2C4_EV_IRQHandler + 537 0000001E I2C4_ER_IRQHandler + 538 0000001E SPDIF_RX_IRQHandler + 539 0000001E DMAMUX1_OVR_IRQHandler + 540 0000001E DFSDM1_FLT0_IRQHandler + 541 0000001E DFSDM1_FLT1_IRQHandler + 542 0000001E DFSDM1_FLT2_IRQHandler + 543 0000001E DFSDM1_FLT3_IRQHandler + 544 0000001E SWPMI1_IRQHandler + 545 0000001E TIM15_IRQHandler + 546 0000001E TIM16_IRQHandler + 547 0000001E TIM17_IRQHandler + 548 0000001E MDIOS_WKUP_IRQHandler + 549 0000001E MDIOS_IRQHandler + 550 0000001E MDMA_IRQHandler + 551 0000001E SDMMC2_IRQHandler + 552 0000001E HSEM1_IRQHandler + 553 0000001E ADC3_IRQHandler + 554 0000001E DMAMUX2_OVR_IRQHandler + 555 0000001E BDMA_Channel0_IRQHandler + 556 0000001E BDMA_Channel1_IRQHandler + 557 0000001E BDMA_Channel2_IRQHandler + 558 0000001E BDMA_Channel3_IRQHandler + 559 0000001E BDMA_Channel4_IRQHandler + 560 0000001E BDMA_Channel5_IRQHandler + 561 0000001E BDMA_Channel6_IRQHandler + 562 0000001E BDMA_Channel7_IRQHandler + 563 0000001E COMP1_IRQHandler + 564 0000001E LPTIM2_IRQHandler + 565 0000001E LPTIM3_IRQHandler + 566 0000001E LPTIM4_IRQHandler + 567 0000001E LPTIM5_IRQHandler + 568 0000001E LPUART1_IRQHandler + 569 0000001E CRS_IRQHandler + 570 0000001E ECC_IRQHandler + 571 0000001E SAI4_IRQHandler + 572 0000001E DTS_IRQHandler + 573 0000001E WAKEUP_PIN_IRQHandler + 574 0000001E OCTOSPI2_IRQHandler + 575 0000001E FMAC_IRQHandler + 576 0000001E CORDIC_IRQHandler + 577 0000001E UART9_IRQHandler + 578 0000001E USART10_IRQHandler + 579 0000001E I2C5_EV_IRQHandler + 580 0000001E I2C5_ER_IRQHandler + 581 0000001E FDCAN3_IT0_IRQHandler + 582 0000001E FDCAN3_IT1_IRQHandler + 583 0000001E TIM23_IRQHandler + 584 0000001E TIM24_IRQHandler + 585 0000001E + 586 0000001E E7FE B . + 587 00000020 + + + +ARM Macro Assembler Page 20 + + + 588 00000020 ENDP + 589 00000020 + 590 00000020 ALIGN + 591 00000020 + 592 00000020 ;******************************************************* + ************************ + 593 00000020 ; User Stack and Heap initialization + 594 00000020 ;******************************************************* + ************************ + 595 00000020 IF :DEF:__MICROLIB + 602 00000020 + 603 00000020 IMPORT __use_two_region_memory + 604 00000020 EXPORT __user_initial_stackheap + 605 00000020 + 606 00000020 __user_initial_stackheap + 607 00000020 + 608 00000020 4805 LDR R0, = Heap_Mem + 609 00000022 4906 LDR R1, =(Stack_Mem + Stack_Size) + 610 00000024 4A06 LDR R2, = (Heap_Mem + Heap_Size) + 611 00000026 4B07 LDR R3, = Stack_Mem + 612 00000028 4770 BX LR + 613 0000002A + 614 0000002A 00 00 ALIGN + 615 0000002C + 616 0000002C ENDIF + 617 0000002C + 618 0000002C END + 00000000 + 00000000 + 00000000 + 00000000 + 00000400 + 00000200 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M7.fp.dp --apcs= +interwork --depend=fdcan\startup_stm32h723xx.d -ofdcan\startup_stm32h723xx.o -I +../Drivers/CMSIS/Include -I.\RTE\_FDCAN -ID:\cangming\ARM\CMSIS\5.7.0\CMSIS\Cor +e\Include --predefine="__UVISION_VERSION SETA 534" --predefine="_RTE_ SETA 1" - +-predefine="STM32H723xx SETA 1" --predefine="_RTE_ SETA 1" --list=startup_stm32 +h723xx.lst startup_stm32h723xx.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 34 in file startup_stm32h723xx.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 35 in file startup_stm32h723xx.s + Uses + At line 609 in file startup_stm32h723xx.s + At line 611 in file startup_stm32h723xx.s + +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 36 in file startup_stm32h723xx.s + Uses + At line 60 in file startup_stm32h723xx.s +Comment: __initial_sp used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 45 in file startup_stm32h723xx.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 47 in file startup_stm32h723xx.s + Uses + At line 608 in file startup_stm32h723xx.s + At line 610 in file startup_stm32h723xx.s + +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 46 in file startup_stm32h723xx.s + Uses + None +Comment: __heap_base unused +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 48 in file startup_stm32h723xx.s + Uses + None +Comment: __heap_limit unused +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 55 in file startup_stm32h723xx.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 60 in file startup_stm32h723xx.s + Uses + At line 56 in file startup_stm32h723xx.s + At line 244 in file startup_stm32h723xx.s + +__Vectors_End 000002CC + +Symbol: __Vectors_End + Definitions + At line 242 in file startup_stm32h723xx.s + Uses + At line 57 in file startup_stm32h723xx.s + At line 244 in file startup_stm32h723xx.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 246 in file startup_stm32h723xx.s + Uses + None +Comment: .text unused +ADC3_IRQHandler 0000001E + +Symbol: ADC3_IRQHandler + Definitions + At line 553 in file startup_stm32h723xx.s + Uses + At line 205 in file startup_stm32h723xx.s + At line 415 in file startup_stm32h723xx.s + +ADC_IRQHandler 0000001E + +Symbol: ADC_IRQHandler + Definitions + At line 466 in file startup_stm32h723xx.s + Uses + At line 96 in file startup_stm32h723xx.s + At line 328 in file startup_stm32h723xx.s + +BDMA_Channel0_IRQHandler 0000001E + +Symbol: BDMA_Channel0_IRQHandler + Definitions + At line 555 in file startup_stm32h723xx.s + Uses + At line 207 in file startup_stm32h723xx.s + At line 417 in file startup_stm32h723xx.s + +BDMA_Channel1_IRQHandler 0000001E + +Symbol: BDMA_Channel1_IRQHandler + Definitions + At line 556 in file startup_stm32h723xx.s + Uses + At line 208 in file startup_stm32h723xx.s + At line 418 in file startup_stm32h723xx.s + +BDMA_Channel2_IRQHandler 0000001E + +Symbol: BDMA_Channel2_IRQHandler + Definitions + At line 557 in file startup_stm32h723xx.s + Uses + At line 209 in file startup_stm32h723xx.s + At line 419 in file startup_stm32h723xx.s + +BDMA_Channel3_IRQHandler 0000001E + +Symbol: BDMA_Channel3_IRQHandler + Definitions + At line 558 in file startup_stm32h723xx.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 210 in file startup_stm32h723xx.s + At line 420 in file startup_stm32h723xx.s + +BDMA_Channel4_IRQHandler 0000001E + +Symbol: BDMA_Channel4_IRQHandler + Definitions + At line 559 in file startup_stm32h723xx.s + Uses + At line 211 in file startup_stm32h723xx.s + At line 421 in file startup_stm32h723xx.s + +BDMA_Channel5_IRQHandler 0000001E + +Symbol: BDMA_Channel5_IRQHandler + Definitions + At line 560 in file startup_stm32h723xx.s + Uses + At line 212 in file startup_stm32h723xx.s + At line 422 in file startup_stm32h723xx.s + +BDMA_Channel6_IRQHandler 0000001E + +Symbol: BDMA_Channel6_IRQHandler + Definitions + At line 561 in file startup_stm32h723xx.s + Uses + At line 213 in file startup_stm32h723xx.s + At line 423 in file startup_stm32h723xx.s + +BDMA_Channel7_IRQHandler 0000001E + +Symbol: BDMA_Channel7_IRQHandler + Definitions + At line 562 in file startup_stm32h723xx.s + Uses + At line 214 in file startup_stm32h723xx.s + At line 424 in file startup_stm32h723xx.s + +BusFault_Handler 00000012 + +Symbol: BusFault_Handler + Definitions + At line 280 in file startup_stm32h723xx.s + Uses + At line 65 in file startup_stm32h723xx.s + At line 281 in file startup_stm32h723xx.s + +CEC_IRQHandler 0000001E + +Symbol: CEC_IRQHandler + Definitions + At line 535 in file startup_stm32h723xx.s + Uses + At line 172 in file startup_stm32h723xx.s + At line 397 in file startup_stm32h723xx.s + +COMP1_IRQHandler 0000001E + + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + +Symbol: COMP1_IRQHandler + Definitions + At line 563 in file startup_stm32h723xx.s + Uses + At line 215 in file startup_stm32h723xx.s + At line 425 in file startup_stm32h723xx.s + +CORDIC_IRQHandler 0000001E + +Symbol: CORDIC_IRQHandler + Definitions + At line 576 in file startup_stm32h723xx.s + Uses + At line 232 in file startup_stm32h723xx.s + At line 438 in file startup_stm32h723xx.s + +CRS_IRQHandler 0000001E + +Symbol: CRS_IRQHandler + Definitions + At line 569 in file startup_stm32h723xx.s + Uses + At line 222 in file startup_stm32h723xx.s + At line 431 in file startup_stm32h723xx.s + +DCMI_PSSI_IRQHandler 0000001E + +Symbol: DCMI_PSSI_IRQHandler + Definitions + At line 521 in file startup_stm32h723xx.s + Uses + At line 156 in file startup_stm32h723xx.s + At line 383 in file startup_stm32h723xx.s + +DFSDM1_FLT0_IRQHandler 0000001E + +Symbol: DFSDM1_FLT0_IRQHandler + Definitions + At line 540 in file startup_stm32h723xx.s + Uses + At line 188 in file startup_stm32h723xx.s + At line 402 in file startup_stm32h723xx.s + +DFSDM1_FLT1_IRQHandler 0000001E + +Symbol: DFSDM1_FLT1_IRQHandler + Definitions + At line 541 in file startup_stm32h723xx.s + Uses + At line 189 in file startup_stm32h723xx.s + At line 403 in file startup_stm32h723xx.s + +DFSDM1_FLT2_IRQHandler 0000001E + +Symbol: DFSDM1_FLT2_IRQHandler + Definitions + At line 542 in file startup_stm32h723xx.s + Uses + At line 190 in file startup_stm32h723xx.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + At line 404 in file startup_stm32h723xx.s + +DFSDM1_FLT3_IRQHandler 0000001E + +Symbol: DFSDM1_FLT3_IRQHandler + Definitions + At line 543 in file startup_stm32h723xx.s + Uses + At line 191 in file startup_stm32h723xx.s + At line 405 in file startup_stm32h723xx.s + +DMA1_Stream0_IRQHandler 0000001E + +Symbol: DMA1_Stream0_IRQHandler + Definitions + At line 459 in file startup_stm32h723xx.s + Uses + At line 89 in file startup_stm32h723xx.s + At line 320 in file startup_stm32h723xx.s + +DMA1_Stream1_IRQHandler 0000001E + +Symbol: DMA1_Stream1_IRQHandler + Definitions + At line 460 in file startup_stm32h723xx.s + Uses + At line 90 in file startup_stm32h723xx.s + At line 321 in file startup_stm32h723xx.s + +DMA1_Stream2_IRQHandler 0000001E + +Symbol: DMA1_Stream2_IRQHandler + Definitions + At line 461 in file startup_stm32h723xx.s + Uses + At line 91 in file startup_stm32h723xx.s + At line 322 in file startup_stm32h723xx.s + +DMA1_Stream3_IRQHandler 0000001E + +Symbol: DMA1_Stream3_IRQHandler + Definitions + At line 462 in file startup_stm32h723xx.s + Uses + At line 92 in file startup_stm32h723xx.s + At line 323 in file startup_stm32h723xx.s + +DMA1_Stream4_IRQHandler 0000001E + +Symbol: DMA1_Stream4_IRQHandler + Definitions + At line 463 in file startup_stm32h723xx.s + Uses + At line 93 in file startup_stm32h723xx.s + At line 324 in file startup_stm32h723xx.s + +DMA1_Stream5_IRQHandler 0000001E + +Symbol: DMA1_Stream5_IRQHandler + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 464 in file startup_stm32h723xx.s + Uses + At line 94 in file startup_stm32h723xx.s + At line 325 in file startup_stm32h723xx.s + +DMA1_Stream6_IRQHandler 0000001E + +Symbol: DMA1_Stream6_IRQHandler + Definitions + At line 465 in file startup_stm32h723xx.s + Uses + At line 95 in file startup_stm32h723xx.s + At line 326 in file startup_stm32h723xx.s + +DMA1_Stream7_IRQHandler 0000001E + +Symbol: DMA1_Stream7_IRQHandler + Definitions + At line 494 in file startup_stm32h723xx.s + Uses + At line 125 in file startup_stm32h723xx.s + At line 327 in file startup_stm32h723xx.s + At line 356 in file startup_stm32h723xx.s + +DMA2D_IRQHandler 0000001E + +Symbol: DMA2D_IRQHandler + Definitions + At line 532 in file startup_stm32h723xx.s + Uses + At line 168 in file startup_stm32h723xx.s + At line 394 in file startup_stm32h723xx.s + +DMA2_Stream0_IRQHandler 0000001E + +Symbol: DMA2_Stream0_IRQHandler + Definitions + At line 503 in file startup_stm32h723xx.s + Uses + At line 134 in file startup_stm32h723xx.s + At line 365 in file startup_stm32h723xx.s + +DMA2_Stream1_IRQHandler 0000001E + +Symbol: DMA2_Stream1_IRQHandler + Definitions + At line 504 in file startup_stm32h723xx.s + Uses + At line 135 in file startup_stm32h723xx.s + At line 366 in file startup_stm32h723xx.s + +DMA2_Stream2_IRQHandler 0000001E + +Symbol: DMA2_Stream2_IRQHandler + Definitions + At line 505 in file startup_stm32h723xx.s + Uses + At line 136 in file startup_stm32h723xx.s + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + + At line 367 in file startup_stm32h723xx.s + +DMA2_Stream3_IRQHandler 0000001E + +Symbol: DMA2_Stream3_IRQHandler + Definitions + At line 506 in file startup_stm32h723xx.s + Uses + At line 137 in file startup_stm32h723xx.s + At line 368 in file startup_stm32h723xx.s + +DMA2_Stream4_IRQHandler 0000001E + +Symbol: DMA2_Stream4_IRQHandler + Definitions + At line 507 in file startup_stm32h723xx.s + Uses + At line 138 in file startup_stm32h723xx.s + At line 369 in file startup_stm32h723xx.s + +DMA2_Stream5_IRQHandler 0000001E + +Symbol: DMA2_Stream5_IRQHandler + Definitions + At line 511 in file startup_stm32h723xx.s + Uses + At line 146 in file startup_stm32h723xx.s + At line 373 in file startup_stm32h723xx.s + +DMA2_Stream6_IRQHandler 0000001E + +Symbol: DMA2_Stream6_IRQHandler + Definitions + At line 512 in file startup_stm32h723xx.s + Uses + At line 147 in file startup_stm32h723xx.s + At line 374 in file startup_stm32h723xx.s + +DMA2_Stream7_IRQHandler 0000001E + +Symbol: DMA2_Stream7_IRQHandler + Definitions + At line 513 in file startup_stm32h723xx.s + Uses + At line 148 in file startup_stm32h723xx.s + At line 375 in file startup_stm32h723xx.s + +DMAMUX1_OVR_IRQHandler 0000001E + +Symbol: DMAMUX1_OVR_IRQHandler + Definitions + At line 539 in file startup_stm32h723xx.s + Uses + At line 180 in file startup_stm32h723xx.s + At line 401 in file startup_stm32h723xx.s + +DMAMUX2_OVR_IRQHandler 0000001E + +Symbol: DMAMUX2_OVR_IRQHandler + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 554 in file startup_stm32h723xx.s + Uses + At line 206 in file startup_stm32h723xx.s + At line 416 in file startup_stm32h723xx.s + +DTS_IRQHandler 0000001E + +Symbol: DTS_IRQHandler + Definitions + At line 572 in file startup_stm32h723xx.s + Uses + At line 225 in file startup_stm32h723xx.s + At line 434 in file startup_stm32h723xx.s + +DebugMon_Handler 00000018 + +Symbol: DebugMon_Handler + Definitions + At line 294 in file startup_stm32h723xx.s + Uses + At line 72 in file startup_stm32h723xx.s + At line 295 in file startup_stm32h723xx.s + +Default_Handler 0000001E + +Symbol: Default_Handler + Definitions + At line 307 in file startup_stm32h723xx.s + Uses + None +Comment: Default_Handler unused +ECC_IRQHandler 0000001E + +Symbol: ECC_IRQHandler + Definitions + At line 570 in file startup_stm32h723xx.s + Uses + At line 223 in file startup_stm32h723xx.s + At line 432 in file startup_stm32h723xx.s + +ETH_IRQHandler 0000001E + +Symbol: ETH_IRQHandler + Definitions + At line 508 in file startup_stm32h723xx.s + Uses + At line 139 in file startup_stm32h723xx.s + At line 370 in file startup_stm32h723xx.s + +ETH_WKUP_IRQHandler 0000001E + +Symbol: ETH_WKUP_IRQHandler + Definitions + At line 509 in file startup_stm32h723xx.s + Uses + At line 140 in file startup_stm32h723xx.s + At line 371 in file startup_stm32h723xx.s + + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + +EXTI0_IRQHandler 0000001E + +Symbol: EXTI0_IRQHandler + Definitions + At line 454 in file startup_stm32h723xx.s + Uses + At line 84 in file startup_stm32h723xx.s + At line 315 in file startup_stm32h723xx.s + +EXTI15_10_IRQHandler 0000001E + +Symbol: EXTI15_10_IRQHandler + Definitions + At line 488 in file startup_stm32h723xx.s + Uses + At line 118 in file startup_stm32h723xx.s + At line 350 in file startup_stm32h723xx.s + +EXTI1_IRQHandler 0000001E + +Symbol: EXTI1_IRQHandler + Definitions + At line 455 in file startup_stm32h723xx.s + Uses + At line 85 in file startup_stm32h723xx.s + At line 316 in file startup_stm32h723xx.s + +EXTI2_IRQHandler 0000001E + +Symbol: EXTI2_IRQHandler + Definitions + At line 456 in file startup_stm32h723xx.s + Uses + At line 86 in file startup_stm32h723xx.s + At line 317 in file startup_stm32h723xx.s + +EXTI3_IRQHandler 0000001E + +Symbol: EXTI3_IRQHandler + Definitions + At line 457 in file startup_stm32h723xx.s + Uses + At line 87 in file startup_stm32h723xx.s + At line 318 in file startup_stm32h723xx.s + +EXTI4_IRQHandler 0000001E + +Symbol: EXTI4_IRQHandler + Definitions + At line 458 in file startup_stm32h723xx.s + Uses + At line 88 in file startup_stm32h723xx.s + At line 319 in file startup_stm32h723xx.s + +EXTI9_5_IRQHandler 0000001E + +Symbol: EXTI9_5_IRQHandler + Definitions + At line 471 in file startup_stm32h723xx.s + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 101 in file startup_stm32h723xx.s + At line 333 in file startup_stm32h723xx.s + +FDCAN1_IT0_IRQHandler 0000001E + +Symbol: FDCAN1_IT0_IRQHandler + Definitions + At line 467 in file startup_stm32h723xx.s + Uses + At line 97 in file startup_stm32h723xx.s + At line 329 in file startup_stm32h723xx.s + +FDCAN1_IT1_IRQHandler 0000001E + +Symbol: FDCAN1_IT1_IRQHandler + Definitions + At line 469 in file startup_stm32h723xx.s + Uses + At line 99 in file startup_stm32h723xx.s + At line 331 in file startup_stm32h723xx.s + +FDCAN2_IT0_IRQHandler 0000001E + +Symbol: FDCAN2_IT0_IRQHandler + Definitions + At line 468 in file startup_stm32h723xx.s + Uses + At line 98 in file startup_stm32h723xx.s + At line 330 in file startup_stm32h723xx.s + +FDCAN2_IT1_IRQHandler 0000001E + +Symbol: FDCAN2_IT1_IRQHandler + Definitions + At line 470 in file startup_stm32h723xx.s + Uses + At line 100 in file startup_stm32h723xx.s + At line 332 in file startup_stm32h723xx.s + +FDCAN3_IT0_IRQHandler 0000001E + +Symbol: FDCAN3_IT0_IRQHandler + Definitions + At line 581 in file startup_stm32h723xx.s + Uses + At line 237 in file startup_stm32h723xx.s + At line 443 in file startup_stm32h723xx.s + +FDCAN3_IT1_IRQHandler 0000001E + +Symbol: FDCAN3_IT1_IRQHandler + Definitions + At line 582 in file startup_stm32h723xx.s + Uses + At line 238 in file startup_stm32h723xx.s + At line 444 in file startup_stm32h723xx.s + +FDCAN_CAL_IRQHandler 0000001E + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: FDCAN_CAL_IRQHandler + Definitions + At line 510 in file startup_stm32h723xx.s + Uses + At line 141 in file startup_stm32h723xx.s + At line 372 in file startup_stm32h723xx.s + +FLASH_IRQHandler 0000001E + +Symbol: FLASH_IRQHandler + Definitions + At line 452 in file startup_stm32h723xx.s + Uses + At line 82 in file startup_stm32h723xx.s + At line 313 in file startup_stm32h723xx.s + +FMAC_IRQHandler 0000001E + +Symbol: FMAC_IRQHandler + Definitions + At line 575 in file startup_stm32h723xx.s + Uses + At line 231 in file startup_stm32h723xx.s + At line 437 in file startup_stm32h723xx.s + +FMC_IRQHandler 0000001E + +Symbol: FMC_IRQHandler + Definitions + At line 495 in file startup_stm32h723xx.s + Uses + At line 126 in file startup_stm32h723xx.s + At line 357 in file startup_stm32h723xx.s + +FPU_IRQHandler 0000001E + +Symbol: FPU_IRQHandler + Definitions + At line 523 in file startup_stm32h723xx.s + Uses + At line 159 in file startup_stm32h723xx.s + At line 385 in file startup_stm32h723xx.s + +HSEM1_IRQHandler 0000001E + +Symbol: HSEM1_IRQHandler + Definitions + At line 552 in file startup_stm32h723xx.s + Uses + At line 203 in file startup_stm32h723xx.s + At line 414 in file startup_stm32h723xx.s + +HardFault_Handler 0000000E + +Symbol: HardFault_Handler + Definitions + At line 270 in file startup_stm32h723xx.s + Uses + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + + At line 63 in file startup_stm32h723xx.s + At line 271 in file startup_stm32h723xx.s + +I2C1_ER_IRQHandler 0000001E + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 480 in file startup_stm32h723xx.s + Uses + At line 110 in file startup_stm32h723xx.s + At line 342 in file startup_stm32h723xx.s + +I2C1_EV_IRQHandler 0000001E + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 479 in file startup_stm32h723xx.s + Uses + At line 109 in file startup_stm32h723xx.s + At line 341 in file startup_stm32h723xx.s + +I2C2_ER_IRQHandler 0000001E + +Symbol: I2C2_ER_IRQHandler + Definitions + At line 482 in file startup_stm32h723xx.s + Uses + At line 112 in file startup_stm32h723xx.s + At line 344 in file startup_stm32h723xx.s + +I2C2_EV_IRQHandler 0000001E + +Symbol: I2C2_EV_IRQHandler + Definitions + At line 481 in file startup_stm32h723xx.s + Uses + At line 111 in file startup_stm32h723xx.s + At line 343 in file startup_stm32h723xx.s + +I2C3_ER_IRQHandler 0000001E + +Symbol: I2C3_ER_IRQHandler + Definitions + At line 516 in file startup_stm32h723xx.s + Uses + At line 151 in file startup_stm32h723xx.s + At line 378 in file startup_stm32h723xx.s + +I2C3_EV_IRQHandler 0000001E + +Symbol: I2C3_EV_IRQHandler + Definitions + At line 515 in file startup_stm32h723xx.s + Uses + At line 150 in file startup_stm32h723xx.s + At line 377 in file startup_stm32h723xx.s + +I2C4_ER_IRQHandler 0000001E + + + + +ARM Macro Assembler Page 12 Alphabetic symbol ordering +Relocatable symbols + +Symbol: I2C4_ER_IRQHandler + Definitions + At line 537 in file startup_stm32h723xx.s + Uses + At line 174 in file startup_stm32h723xx.s + At line 399 in file startup_stm32h723xx.s + +I2C4_EV_IRQHandler 0000001E + +Symbol: I2C4_EV_IRQHandler + Definitions + At line 536 in file startup_stm32h723xx.s + Uses + At line 173 in file startup_stm32h723xx.s + At line 398 in file startup_stm32h723xx.s + +I2C5_ER_IRQHandler 0000001E + +Symbol: I2C5_ER_IRQHandler + Definitions + At line 580 in file startup_stm32h723xx.s + Uses + At line 236 in file startup_stm32h723xx.s + At line 442 in file startup_stm32h723xx.s + +I2C5_EV_IRQHandler 0000001E + +Symbol: I2C5_EV_IRQHandler + Definitions + At line 579 in file startup_stm32h723xx.s + Uses + At line 235 in file startup_stm32h723xx.s + At line 441 in file startup_stm32h723xx.s + +LPTIM1_IRQHandler 0000001E + +Symbol: LPTIM1_IRQHandler + Definitions + At line 534 in file startup_stm32h723xx.s + Uses + At line 171 in file startup_stm32h723xx.s + At line 396 in file startup_stm32h723xx.s + +LPTIM2_IRQHandler 0000001E + +Symbol: LPTIM2_IRQHandler + Definitions + At line 564 in file startup_stm32h723xx.s + Uses + At line 216 in file startup_stm32h723xx.s + At line 426 in file startup_stm32h723xx.s + +LPTIM3_IRQHandler 0000001E + +Symbol: LPTIM3_IRQHandler + Definitions + At line 565 in file startup_stm32h723xx.s + Uses + At line 217 in file startup_stm32h723xx.s + + + +ARM Macro Assembler Page 13 Alphabetic symbol ordering +Relocatable symbols + + At line 427 in file startup_stm32h723xx.s + +LPTIM4_IRQHandler 0000001E + +Symbol: LPTIM4_IRQHandler + Definitions + At line 566 in file startup_stm32h723xx.s + Uses + At line 218 in file startup_stm32h723xx.s + At line 428 in file startup_stm32h723xx.s + +LPTIM5_IRQHandler 0000001E + +Symbol: LPTIM5_IRQHandler + Definitions + At line 567 in file startup_stm32h723xx.s + Uses + At line 219 in file startup_stm32h723xx.s + At line 429 in file startup_stm32h723xx.s + +LPUART1_IRQHandler 0000001E + +Symbol: LPUART1_IRQHandler + Definitions + At line 568 in file startup_stm32h723xx.s + Uses + At line 220 in file startup_stm32h723xx.s + At line 430 in file startup_stm32h723xx.s + +LTDC_ER_IRQHandler 0000001E + +Symbol: LTDC_ER_IRQHandler + Definitions + At line 531 in file startup_stm32h723xx.s + Uses + At line 167 in file startup_stm32h723xx.s + At line 393 in file startup_stm32h723xx.s + +LTDC_IRQHandler 0000001E + +Symbol: LTDC_IRQHandler + Definitions + At line 530 in file startup_stm32h723xx.s + Uses + At line 166 in file startup_stm32h723xx.s + At line 392 in file startup_stm32h723xx.s + +MDIOS_IRQHandler 0000001E + +Symbol: MDIOS_IRQHandler + Definitions + At line 549 in file startup_stm32h723xx.s + Uses + At line 198 in file startup_stm32h723xx.s + At line 411 in file startup_stm32h723xx.s + +MDIOS_WKUP_IRQHandler 0000001E + +Symbol: MDIOS_WKUP_IRQHandler + + + +ARM Macro Assembler Page 14 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 548 in file startup_stm32h723xx.s + Uses + At line 197 in file startup_stm32h723xx.s + At line 410 in file startup_stm32h723xx.s + +MDMA_IRQHandler 0000001E + +Symbol: MDMA_IRQHandler + Definitions + At line 550 in file startup_stm32h723xx.s + Uses + At line 200 in file startup_stm32h723xx.s + At line 412 in file startup_stm32h723xx.s + +MemManage_Handler 00000010 + +Symbol: MemManage_Handler + Definitions + At line 275 in file startup_stm32h723xx.s + Uses + At line 64 in file startup_stm32h723xx.s + At line 276 in file startup_stm32h723xx.s + +NMI_Handler 0000000C + +Symbol: NMI_Handler + Definitions + At line 265 in file startup_stm32h723xx.s + Uses + At line 62 in file startup_stm32h723xx.s + At line 266 in file startup_stm32h723xx.s + +OCTOSPI1_IRQHandler 0000001E + +Symbol: OCTOSPI1_IRQHandler + Definitions + At line 533 in file startup_stm32h723xx.s + Uses + At line 170 in file startup_stm32h723xx.s + At line 395 in file startup_stm32h723xx.s + +OCTOSPI2_IRQHandler 0000001E + +Symbol: OCTOSPI2_IRQHandler + Definitions + At line 574 in file startup_stm32h723xx.s + Uses + At line 228 in file startup_stm32h723xx.s + At line 436 in file startup_stm32h723xx.s + +OTG_HS_EP1_IN_IRQHandler 0000001E + +Symbol: OTG_HS_EP1_IN_IRQHandler + Definitions + At line 518 in file startup_stm32h723xx.s + Uses + At line 153 in file startup_stm32h723xx.s + At line 380 in file startup_stm32h723xx.s + + + +ARM Macro Assembler Page 15 Alphabetic symbol ordering +Relocatable symbols + + +OTG_HS_EP1_OUT_IRQHandler 0000001E + +Symbol: OTG_HS_EP1_OUT_IRQHandler + Definitions + At line 517 in file startup_stm32h723xx.s + Uses + At line 152 in file startup_stm32h723xx.s + At line 379 in file startup_stm32h723xx.s + +OTG_HS_IRQHandler 0000001E + +Symbol: OTG_HS_IRQHandler + Definitions + At line 520 in file startup_stm32h723xx.s + Uses + At line 155 in file startup_stm32h723xx.s + At line 382 in file startup_stm32h723xx.s + +OTG_HS_WKUP_IRQHandler 0000001E + +Symbol: OTG_HS_WKUP_IRQHandler + Definitions + At line 519 in file startup_stm32h723xx.s + Uses + At line 154 in file startup_stm32h723xx.s + At line 381 in file startup_stm32h723xx.s + +PVD_AVD_IRQHandler 0000001E + +Symbol: PVD_AVD_IRQHandler + Definitions + At line 449 in file startup_stm32h723xx.s + Uses + At line 79 in file startup_stm32h723xx.s + At line 310 in file startup_stm32h723xx.s + +PendSV_Handler 0000001A + +Symbol: PendSV_Handler + Definitions + At line 298 in file startup_stm32h723xx.s + Uses + At line 74 in file startup_stm32h723xx.s + At line 299 in file startup_stm32h723xx.s + +RCC_IRQHandler 0000001E + +Symbol: RCC_IRQHandler + Definitions + At line 453 in file startup_stm32h723xx.s + Uses + At line 83 in file startup_stm32h723xx.s + At line 314 in file startup_stm32h723xx.s + +RNG_IRQHandler 0000001E + +Symbol: RNG_IRQHandler + Definitions + + + +ARM Macro Assembler Page 16 Alphabetic symbol ordering +Relocatable symbols + + At line 522 in file startup_stm32h723xx.s + Uses + At line 158 in file startup_stm32h723xx.s + At line 384 in file startup_stm32h723xx.s + +RTC_Alarm_IRQHandler 0000001E + +Symbol: RTC_Alarm_IRQHandler + Definitions + At line 489 in file startup_stm32h723xx.s + Uses + At line 119 in file startup_stm32h723xx.s + At line 351 in file startup_stm32h723xx.s + +RTC_WKUP_IRQHandler 0000001E + +Symbol: RTC_WKUP_IRQHandler + Definitions + At line 451 in file startup_stm32h723xx.s + Uses + At line 81 in file startup_stm32h723xx.s + At line 312 in file startup_stm32h723xx.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 249 in file startup_stm32h723xx.s + Uses + At line 61 in file startup_stm32h723xx.s + At line 250 in file startup_stm32h723xx.s + +SAI1_IRQHandler 0000001E + +Symbol: SAI1_IRQHandler + Definitions + At line 529 in file startup_stm32h723xx.s + Uses + At line 165 in file startup_stm32h723xx.s + At line 391 in file startup_stm32h723xx.s + +SAI4_IRQHandler 0000001E + +Symbol: SAI4_IRQHandler + Definitions + At line 571 in file startup_stm32h723xx.s + Uses + At line 224 in file startup_stm32h723xx.s + At line 433 in file startup_stm32h723xx.s + +SDMMC1_IRQHandler 0000001E + +Symbol: SDMMC1_IRQHandler + Definitions + At line 496 in file startup_stm32h723xx.s + Uses + At line 127 in file startup_stm32h723xx.s + At line 358 in file startup_stm32h723xx.s + + + + +ARM Macro Assembler Page 17 Alphabetic symbol ordering +Relocatable symbols + +SDMMC2_IRQHandler 0000001E + +Symbol: SDMMC2_IRQHandler + Definitions + At line 551 in file startup_stm32h723xx.s + Uses + At line 202 in file startup_stm32h723xx.s + At line 413 in file startup_stm32h723xx.s + +SPDIF_RX_IRQHandler 0000001E + +Symbol: SPDIF_RX_IRQHandler + Definitions + At line 538 in file startup_stm32h723xx.s + Uses + At line 175 in file startup_stm32h723xx.s + At line 400 in file startup_stm32h723xx.s + +SPI1_IRQHandler 0000001E + +Symbol: SPI1_IRQHandler + Definitions + At line 483 in file startup_stm32h723xx.s + Uses + At line 113 in file startup_stm32h723xx.s + At line 345 in file startup_stm32h723xx.s + +SPI2_IRQHandler 0000001E + +Symbol: SPI2_IRQHandler + Definitions + At line 484 in file startup_stm32h723xx.s + Uses + At line 114 in file startup_stm32h723xx.s + At line 346 in file startup_stm32h723xx.s + +SPI3_IRQHandler 0000001E + +Symbol: SPI3_IRQHandler + Definitions + At line 498 in file startup_stm32h723xx.s + Uses + At line 129 in file startup_stm32h723xx.s + At line 360 in file startup_stm32h723xx.s + +SPI4_IRQHandler 0000001E + +Symbol: SPI4_IRQHandler + Definitions + At line 526 in file startup_stm32h723xx.s + Uses + At line 162 in file startup_stm32h723xx.s + At line 388 in file startup_stm32h723xx.s + +SPI5_IRQHandler 0000001E + +Symbol: SPI5_IRQHandler + Definitions + At line 527 in file startup_stm32h723xx.s + + + +ARM Macro Assembler Page 18 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 163 in file startup_stm32h723xx.s + At line 389 in file startup_stm32h723xx.s + +SPI6_IRQHandler 0000001E + +Symbol: SPI6_IRQHandler + Definitions + At line 528 in file startup_stm32h723xx.s + Uses + At line 164 in file startup_stm32h723xx.s + At line 390 in file startup_stm32h723xx.s + +SVC_Handler 00000016 + +Symbol: SVC_Handler + Definitions + At line 289 in file startup_stm32h723xx.s + Uses + At line 71 in file startup_stm32h723xx.s + At line 290 in file startup_stm32h723xx.s + +SWPMI1_IRQHandler 0000001E + +Symbol: SWPMI1_IRQHandler + Definitions + At line 544 in file startup_stm32h723xx.s + Uses + At line 193 in file startup_stm32h723xx.s + At line 406 in file startup_stm32h723xx.s + +SysTick_Handler 0000001C + +Symbol: SysTick_Handler + Definitions + At line 302 in file startup_stm32h723xx.s + Uses + At line 75 in file startup_stm32h723xx.s + At line 303 in file startup_stm32h723xx.s + +TAMP_STAMP_IRQHandler 0000001E + +Symbol: TAMP_STAMP_IRQHandler + Definitions + At line 450 in file startup_stm32h723xx.s + Uses + At line 80 in file startup_stm32h723xx.s + At line 311 in file startup_stm32h723xx.s + +TIM15_IRQHandler 0000001E + +Symbol: TIM15_IRQHandler + Definitions + At line 545 in file startup_stm32h723xx.s + Uses + At line 194 in file startup_stm32h723xx.s + At line 407 in file startup_stm32h723xx.s + +TIM16_IRQHandler 0000001E + + + +ARM Macro Assembler Page 19 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: TIM16_IRQHandler + Definitions + At line 546 in file startup_stm32h723xx.s + Uses + At line 195 in file startup_stm32h723xx.s + At line 408 in file startup_stm32h723xx.s + +TIM17_IRQHandler 0000001E + +Symbol: TIM17_IRQHandler + Definitions + At line 547 in file startup_stm32h723xx.s + Uses + At line 196 in file startup_stm32h723xx.s + At line 409 in file startup_stm32h723xx.s + +TIM1_BRK_IRQHandler 0000001E + +Symbol: TIM1_BRK_IRQHandler + Definitions + At line 472 in file startup_stm32h723xx.s + Uses + At line 102 in file startup_stm32h723xx.s + At line 334 in file startup_stm32h723xx.s + +TIM1_CC_IRQHandler 0000001E + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 475 in file startup_stm32h723xx.s + Uses + At line 105 in file startup_stm32h723xx.s + At line 337 in file startup_stm32h723xx.s + +TIM1_TRG_COM_IRQHandler 0000001E + +Symbol: TIM1_TRG_COM_IRQHandler + Definitions + At line 474 in file startup_stm32h723xx.s + Uses + At line 104 in file startup_stm32h723xx.s + At line 336 in file startup_stm32h723xx.s + +TIM1_UP_IRQHandler 0000001E + +Symbol: TIM1_UP_IRQHandler + Definitions + At line 473 in file startup_stm32h723xx.s + Uses + At line 103 in file startup_stm32h723xx.s + At line 335 in file startup_stm32h723xx.s + +TIM23_IRQHandler 0000001E + +Symbol: TIM23_IRQHandler + Definitions + At line 583 in file startup_stm32h723xx.s + Uses + + + +ARM Macro Assembler Page 20 Alphabetic symbol ordering +Relocatable symbols + + At line 239 in file startup_stm32h723xx.s + At line 445 in file startup_stm32h723xx.s + +TIM24_IRQHandler 0000001E + +Symbol: TIM24_IRQHandler + Definitions + At line 584 in file startup_stm32h723xx.s + Uses + At line 240 in file startup_stm32h723xx.s + At line 446 in file startup_stm32h723xx.s + +TIM2_IRQHandler 0000001E + +Symbol: TIM2_IRQHandler + Definitions + At line 476 in file startup_stm32h723xx.s + Uses + At line 106 in file startup_stm32h723xx.s + At line 338 in file startup_stm32h723xx.s + +TIM3_IRQHandler 0000001E + +Symbol: TIM3_IRQHandler + Definitions + At line 477 in file startup_stm32h723xx.s + Uses + At line 107 in file startup_stm32h723xx.s + At line 339 in file startup_stm32h723xx.s + +TIM4_IRQHandler 0000001E + +Symbol: TIM4_IRQHandler + Definitions + At line 478 in file startup_stm32h723xx.s + Uses + At line 108 in file startup_stm32h723xx.s + At line 340 in file startup_stm32h723xx.s + +TIM5_IRQHandler 0000001E + +Symbol: TIM5_IRQHandler + Definitions + At line 497 in file startup_stm32h723xx.s + Uses + At line 128 in file startup_stm32h723xx.s + At line 359 in file startup_stm32h723xx.s + +TIM6_DAC_IRQHandler 0000001E + +Symbol: TIM6_DAC_IRQHandler + Definitions + At line 501 in file startup_stm32h723xx.s + Uses + At line 132 in file startup_stm32h723xx.s + At line 363 in file startup_stm32h723xx.s + +TIM7_IRQHandler 0000001E + + + + +ARM Macro Assembler Page 21 Alphabetic symbol ordering +Relocatable symbols + +Symbol: TIM7_IRQHandler + Definitions + At line 502 in file startup_stm32h723xx.s + Uses + At line 133 in file startup_stm32h723xx.s + At line 364 in file startup_stm32h723xx.s + +TIM8_BRK_TIM12_IRQHandler 0000001E + +Symbol: TIM8_BRK_TIM12_IRQHandler + Definitions + At line 490 in file startup_stm32h723xx.s + Uses + At line 121 in file startup_stm32h723xx.s + At line 352 in file startup_stm32h723xx.s + +TIM8_CC_IRQHandler 0000001E + +Symbol: TIM8_CC_IRQHandler + Definitions + At line 493 in file startup_stm32h723xx.s + Uses + At line 124 in file startup_stm32h723xx.s + At line 355 in file startup_stm32h723xx.s + +TIM8_TRG_COM_TIM14_IRQHandler 0000001E + +Symbol: TIM8_TRG_COM_TIM14_IRQHandler + Definitions + At line 492 in file startup_stm32h723xx.s + Uses + At line 123 in file startup_stm32h723xx.s + At line 354 in file startup_stm32h723xx.s + +TIM8_UP_TIM13_IRQHandler 0000001E + +Symbol: TIM8_UP_TIM13_IRQHandler + Definitions + At line 491 in file startup_stm32h723xx.s + Uses + At line 122 in file startup_stm32h723xx.s + At line 353 in file startup_stm32h723xx.s + +UART4_IRQHandler 0000001E + +Symbol: UART4_IRQHandler + Definitions + At line 499 in file startup_stm32h723xx.s + Uses + At line 130 in file startup_stm32h723xx.s + At line 361 in file startup_stm32h723xx.s + +UART5_IRQHandler 0000001E + +Symbol: UART5_IRQHandler + Definitions + At line 500 in file startup_stm32h723xx.s + Uses + At line 131 in file startup_stm32h723xx.s + + + +ARM Macro Assembler Page 22 Alphabetic symbol ordering +Relocatable symbols + + At line 362 in file startup_stm32h723xx.s + +UART7_IRQHandler 0000001E + +Symbol: UART7_IRQHandler + Definitions + At line 524 in file startup_stm32h723xx.s + Uses + At line 160 in file startup_stm32h723xx.s + At line 386 in file startup_stm32h723xx.s + +UART8_IRQHandler 0000001E + +Symbol: UART8_IRQHandler + Definitions + At line 525 in file startup_stm32h723xx.s + Uses + At line 161 in file startup_stm32h723xx.s + At line 387 in file startup_stm32h723xx.s + +UART9_IRQHandler 0000001E + +Symbol: UART9_IRQHandler + Definitions + At line 577 in file startup_stm32h723xx.s + Uses + At line 233 in file startup_stm32h723xx.s + At line 439 in file startup_stm32h723xx.s + +USART10_IRQHandler 0000001E + +Symbol: USART10_IRQHandler + Definitions + At line 578 in file startup_stm32h723xx.s + Uses + At line 234 in file startup_stm32h723xx.s + At line 440 in file startup_stm32h723xx.s + +USART1_IRQHandler 0000001E + +Symbol: USART1_IRQHandler + Definitions + At line 485 in file startup_stm32h723xx.s + Uses + At line 115 in file startup_stm32h723xx.s + At line 347 in file startup_stm32h723xx.s + +USART2_IRQHandler 0000001E + +Symbol: USART2_IRQHandler + Definitions + At line 486 in file startup_stm32h723xx.s + Uses + At line 116 in file startup_stm32h723xx.s + At line 348 in file startup_stm32h723xx.s + +USART3_IRQHandler 0000001E + +Symbol: USART3_IRQHandler + + + +ARM Macro Assembler Page 23 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 487 in file startup_stm32h723xx.s + Uses + At line 117 in file startup_stm32h723xx.s + At line 349 in file startup_stm32h723xx.s + +USART6_IRQHandler 0000001E + +Symbol: USART6_IRQHandler + Definitions + At line 514 in file startup_stm32h723xx.s + Uses + At line 149 in file startup_stm32h723xx.s + At line 376 in file startup_stm32h723xx.s + +UsageFault_Handler 00000014 + +Symbol: UsageFault_Handler + Definitions + At line 285 in file startup_stm32h723xx.s + Uses + At line 66 in file startup_stm32h723xx.s + At line 286 in file startup_stm32h723xx.s + +WAKEUP_PIN_IRQHandler 0000001E + +Symbol: WAKEUP_PIN_IRQHandler + Definitions + At line 573 in file startup_stm32h723xx.s + Uses + At line 227 in file startup_stm32h723xx.s + At line 435 in file startup_stm32h723xx.s + +WWDG_IRQHandler 0000001E + +Symbol: WWDG_IRQHandler + Definitions + At line 448 in file startup_stm32h723xx.s + Uses + At line 78 in file startup_stm32h723xx.s + At line 309 in file startup_stm32h723xx.s + +__user_initial_stackheap 00000020 + +Symbol: __user_initial_stackheap + Definitions + At line 606 in file startup_stm32h723xx.s + Uses + At line 604 in file startup_stm32h723xx.s +Comment: __user_initial_stackheap used once +150 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 43 in file startup_stm32h723xx.s + Uses + At line 47 in file startup_stm32h723xx.s + At line 610 in file startup_stm32h723xx.s + +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 32 in file startup_stm32h723xx.s + Uses + At line 35 in file startup_stm32h723xx.s + At line 609 in file startup_stm32h723xx.s + +__Vectors_Size 000002CC + +Symbol: __Vectors_Size + Definitions + At line 244 in file startup_stm32h723xx.s + Uses + At line 58 in file startup_stm32h723xx.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +ExitRun0Mode 00000000 + +Symbol: ExitRun0Mode + Definitions + At line 251 in file startup_stm32h723xx.s + Uses + At line 255 in file startup_stm32h723xx.s +Comment: ExitRun0Mode used once +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 252 in file startup_stm32h723xx.s + Uses + At line 257 in file startup_stm32h723xx.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 253 in file startup_stm32h723xx.s + Uses + At line 259 in file startup_stm32h723xx.s +Comment: __main used once +__use_two_region_memory 00000000 + +Symbol: __use_two_region_memory + Definitions + At line 603 in file startup_stm32h723xx.s + Uses + None +Comment: __use_two_region_memory unused +4 symbols +505 symbols in table diff --git a/MDK-ARM/startup_stm32h723xx.s b/MDK-ARM/startup_stm32h723xx.s new file mode 100644 index 0000000..f218e3b --- /dev/null +++ b/MDK-ARM/startup_stm32h723xx.s @@ -0,0 +1,619 @@ +;******************************************************************************** +;* File Name : startup_stm32h723xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD 0 ; Reserved + DCD OCTOSPI1_IRQHandler ; OCTOSPI1 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; DTS interrupt + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMAC_IRQHandler ; FMAC Interrupt + DCD CORDIC_IRQHandler ; CORDIC Interrupt + DCD UART9_IRQHandler ; UART9 Interrupt + DCD USART10_IRQHandler ; UART10 Interrupt + DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt + DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT ExitRun0Mode + IMPORT SystemInit + IMPORT __main + + LDR R0, =ExitRun0Mode + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_PSSI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT OCTOSPI1_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT DTS_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + EXPORT OCTOSPI2_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT USART10_IRQHandler [WEAK] + EXPORT I2C5_EV_IRQHandler [WEAK] + EXPORT I2C5_ER_IRQHandler [WEAK] + EXPORT FDCAN3_IT0_IRQHandler [WEAK] + EXPORT FDCAN3_IT1_IRQHandler [WEAK] + EXPORT TIM23_IRQHandler [WEAK] + EXPORT TIM24_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_PSSI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +OCTOSPI1_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DMAMUX1_OVR_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +DTS_IRQHandler +WAKEUP_PIN_IRQHandler +OCTOSPI2_IRQHandler +FMAC_IRQHandler +CORDIC_IRQHandler +UART9_IRQHandler +USART10_IRQHandler +I2C5_EV_IRQHandler +I2C5_ER_IRQHandler +FDCAN3_IT0_IRQHandler +FDCAN3_IT1_IRQHandler +TIM23_IRQHandler +TIM24_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h new file mode 100644 index 0000000..711408a --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h @@ -0,0 +1,846 @@ +/* + * Copyright (c) 2013-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 10. January 2017 + * $Revision: V2.1.0 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h FreeRTOS header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedefs + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * Version 2.0.0 + * OS objects creation without macros (dynamic creation and resource allocation): + * - added: osXxxxNew functions which replace osXxxxCreate + * - added: osXxxxAttr_t structures + * - deprecated: osXxxxCreate functions, osXxxxDef_t structures + * - deprecated: osXxxxDef and osXxxx macros + * osStatus codes simplified and renamed to osStatus_t + * osEvent return structure deprecated + * Kernel: + * - added: osKernelInfo_t and osKernelGetInfo + * - added: osKernelState_t and osKernelGetState (replaces osKernelRunning) + * - added: osKernelLock, osKernelUnlock + * - added: osKernelSuspend, osKernelResume + * - added: osKernelGetTickCount, osKernelGetTickFreq + * - renamed osKernelSysTick to osKernelGetSysTimerCount + * - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq + * - deprecated osKernelSysTickMicroSec + * Thread: + * - extended number of thread priorities + * - renamed osPrioriry to osPrioriry_t + * - replaced osThreadCreate with osThreadNew + * - added: osThreadGetName + * - added: osThreadState_t and osThreadGetState + * - added: osThreadGetStackSize, osThreadGetStackSpace + * - added: osThreadSuspend, osThreadResume + * - added: osThreadJoin, osThreadDetach, osThreadExit + * - added: osThreadGetCount, osThreadEnumerate + * - added: Thread Flags (moved from Signals) + * Signals: + * - renamed osSignals to osThreadFlags (moved to Thread Flags) + * - changed return value of Set/Clear/Wait functions + * - Clear function limited to current running thread + * - extended Wait function (options) + * - added: osThreadFlagsGet + * Event Flags: + * - added new independent object for handling Event Flags + * Delay and Wait functions: + * - added: osDelayUntil + * - deprecated: osWait + * Timer: + * - replaced osTimerCreate with osTimerNew + * - added: osTimerGetName, osTimerIsRunning + * Mutex: + * - extended: attributes (Recursive, Priority Inherit, Robust) + * - replaced osMutexCreate with osMutexNew + * - renamed osMutexWait to osMutexAcquire + * - added: osMutexGetName, osMutexGetOwner + * Semaphore: + * - extended: maximum and initial token count + * - replaced osSemaphoreCreate with osSemaphoreNew + * - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value) + * - added: osSemaphoreGetName, osSemaphoreGetCount + * Memory Pool: + * - using osMemoryPool prefix instead of osPool + * - replaced osPoolCreate with osMemoryPoolNew + * - extended osMemoryPoolAlloc (timeout) + * - added: osMemoryPoolGetName + * - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize + * - added: osMemoryPoolGetCount, osMemoryPoolGetSpace + * - added: osMemoryPoolDelete + * - deprecated: osPoolCAlloc + * Message Queue: + * - extended: fixed size message instead of a single 32-bit value + * - using osMessageQueue prefix instead of osMessage + * - replaced osMessageCreate with osMessageQueueNew + * - updated: osMessageQueuePut, osMessageQueueGet + * - added: osMessageQueueGetName + * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize + * - added: osMessageQueueGetCount, osMessageQueueGetSpace + * - added: osMessageQueueReset, osMessageQueueDelete + * Mail Queue: + * - deprecated (superseded by extended Message Queue functionality) + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS_H_ +#define CMSIS_OS_H_ + +#include "FreeRTOS.h" +#include "task.h" + +#define RTOS_ID_n ((tskKERNEL_VERSION_MAJOR << 16) | (tskKERNEL_VERSION_MINOR)) +#define RTOS_ID_s ("FreeRTOS " tskKERNEL_VERSION_NUMBER) + +#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) + +#define osCMSIS_FreeRTOS RTOS_ID_n ///< RTOS identification and version (main[31:16].sub[15:0]) + +#define osKernelSystemId RTOS_ID_s ///< RTOS identification string + +#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Signals 24U ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available +#define osFeature_Pool 0 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_MailQ 0 ///< Mail Queues: 1=available, 0=not available + +#if defined(__CC_ARM) +#define os_InRegs __value_in_regs +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define os_InRegs __attribute__((value_in_regs)) +#else +#define os_InRegs +#endif + +#include "cmsis_os2.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Priority values. +#if (osCMSIS < 0x20000U) +typedef enum { + osPriorityIdle = -3, ///< Priority: idle (lowest) + osPriorityLow = -2, ///< Priority: low + osPriorityBelowNormal = -1, ///< Priority: below normal + osPriorityNormal = 0, ///< Priority: normal (default) + osPriorityAboveNormal = +1, ///< Priority: above normal + osPriorityHigh = +2, ///< Priority: high + osPriorityRealtime = +3, ///< Priority: realtime (highest) + osPriorityError = 0x84, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority; +#else +#define osPriority osPriority_t +#endif + +/// Entry point of a thread. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +typedef void (*os_ptimer) (void const *argument); + +/// Timer type. +#if (osCMSIS < 0x20000U) +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} os_timer_type; +#else +#define os_timer_type osTimerType_t +#endif + +/// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +/// Status code values returned by CMSIS-RTOS functions. +#if (osCMSIS < 0x20000U) +typedef enum { + osOK = 0, ///< Function completed; no error or event occurred. + osEventSignal = 0x08, ///< Function completed; signal event occurred. + osEventMessage = 0x10, ///< Function completed; message event occurred. + osEventMail = 0x20, ///< Function completed; mail event occurred. + osEventTimeout = 0x40, ///< Function completed; timeout occurred. + osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< Resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< Value of a parameter is out of range. + osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus; +#else +typedef int32_t osStatus; +#define osEventSignal (0x08) +#define osEventMessage (0x10) +#define osEventMail (0x20) +#define osEventTimeout (0x40) +#define osErrorOS osError +#define osErrorTimeoutResource osErrorTimeout +#define osErrorISRRecursive (-126) +#define osErrorValue (-127) +#define osErrorPriority (-128) +#endif + + +// >>> the following data type definitions may be adapted towards a specific RTOS + +/// Thread ID identifies the thread. +#if (osCMSIS < 0x20000U) +typedef void *osThreadId; +#else +#define osThreadId osThreadId_t +#endif + +/// Timer ID identifies the timer. +#if (osCMSIS < 0x20000U) +typedef void *osTimerId; +#else +#define osTimerId osTimerId_t +#endif + +/// Mutex ID identifies the mutex. +#if (osCMSIS < 0x20000U) +typedef void *osMutexId; +#else +#define osMutexId osMutexId_t +#endif + +/// Semaphore ID identifies the semaphore. +#if (osCMSIS < 0x20000U) +typedef void *osSemaphoreId; +#else +#define osSemaphoreId osSemaphoreId_t +#endif + +/// Pool ID identifies the memory pool. +typedef void *osPoolId; + +/// Message ID identifies the message queue. +typedef void *osMessageQId; + +/// Mail ID identifies the mail queue. +typedef void *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +#if (osCMSIS < 0x20000U) +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; +#else +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osThreadAttr_t attr; ///< thread attributes +} osThreadDef_t; +#endif + +/// Timer Definition structure contains timer parameters. +#if (osCMSIS < 0x20000U) +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; +#else +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function + osTimerAttr_t attr; ///< timer attributes +} osTimerDef_t; +#endif + +/// Mutex Definition structure contains setup information for a mutex. +#if (osCMSIS < 0x20000U) +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value +} osMutexDef_t; +#else +#define osMutexDef_t osMutexAttr_t +#endif + +/// Semaphore Definition structure contains setup information for a semaphore. +#if (osCMSIS < 0x20000U) +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value +} osSemaphoreDef_t; +#else +#define osSemaphoreDef_t osSemaphoreAttr_t +#endif + +/// Definition structure for memory block allocation. +#if (osCMSIS < 0x20000U) +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; +#else +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + osMemoryPoolAttr_t attr; ///< memory pool attributes +} osPoolDef_t; +#endif + +/// Definition structure for message queue. +#if (osCMSIS < 0x20000U) +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + void *pool; ///< memory array for messages +} osMessageQDef_t; +#else +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + osMessageQueueAttr_t attr; ///< message queue attributes +} osMessageQDef_t; +#endif + +/// Definition structure for mail queue. +#if (osCMSIS < 0x20000U) +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; +#else +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *mail; ///< pointer to mail + osMemoryPoolAttr_t mp_attr; ///< memory pool attributes + osMessageQueueAttr_t mq_attr; ///< message queue attributes +} osMailQDef_t; +#endif + + +/// Event structure contains detailed information about an event. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelInitialize (void); +#endif + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelStart (void); +#endif + +/// Check if the RTOS kernel is already started. +/// \return 0 RTOS is not started, 1 RTOS is started. +#if (osCMSIS < 0x20000U) +int32_t osKernelRunning(void); +#endif + +#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter. +/// \return RTOS kernel system timer as 32-bit value +#if (osCMSIS < 0x20000U) +uint32_t osKernelSysTick (void); +#else +#define osKernelSysTick osKernelGetSysTimerCount +#endif + +/// The RTOS kernel system timer frequency in Hz. +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#if (osCMSIS < 0x20000U) +#define osKernelSysTickFrequency 100000000 +#endif + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#if (osCMSIS < 0x20000U) +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) +#else +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000) +#endif + +#endif // System Timer available + + +// ==== Thread Management Functions ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1]; \ +static StaticTask_t os_thread_cb_##name; \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), \ + { NULL, osThreadDetached, \ + (instances == 1) ? (&os_thread_cb_##name) : NULL,\ + (instances == 1) ? sizeof(StaticTask_t) : 0U, \ + ((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \ + 8*((stacksz+7)/8), \ + (priority), 0U, 0U } } +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +#if (osCMSIS < 0x20000U) +osThreadId osThreadGetId (void); +#endif + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); +#endif + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the specified thread. +#if (osCMSIS < 0x20000U) +osPriority osThreadGetPriority (osThreadId thread_id); +#endif + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadYield (void); +#endif + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadTerminate (osThreadId thread_id); +#endif + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osDelay (uint32_t millisec); +#endif + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +os_InRegs osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== + +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +static StaticTimer_t os_timer_cb_##name; \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create and Initialize a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); +#endif + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStop (osTimerId timer_id); +#endif + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerDelete (osTimerId timer_id); +#endif + + +// ==== Mutex Management Functions ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +static StaticSemaphore_t os_mutex_cb_##name; \ +const osMutexDef_t os_mutex_def_##name = \ +{ NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); +#else +#define osMutexWait osMutexAcquire +#endif + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexRelease (osMutexId mutex_id); +#endif + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexDelete (osMutexId mutex_id); +#endif + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +static StaticSemaphore_t os_semaphore_cb_##name; \ +const osSemaphoreDef_t os_semaphore_def_##name = \ +{ NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count maximum and initial number of available tokens. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); +#endif + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); +#endif + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), {NULL} } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a Memory Pool object. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a Memory Pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool available + + +// ==== Message Queue Management Functions ==== + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +static StaticQueue_t os_mq_cb_##name; \ +static uint32_t os_mq_data_##name[(queue_sz) * sizeof(type)]; \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), \ + { NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \ + (&os_mq_data_##name), sizeof(os_mq_data_##name) } } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue object. +/// \param[in] queue_def message queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queue available + + +// ==== Mail Queue Management Functions ==== + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of mails in the queue. +/// \param type data type of a single mail element. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), NULL } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize a Mail Queue object. +/// \param[in] queue_def mail queue definition referenced with \ref osMailQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block for mail from a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block for mail from a mail memory pool and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a Mail into a Queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory with mail to put into a queue. +/// \return status code that indicates the execution status of the function. +osStatus osMailPut (osMailQId queue_id, const void *mail); + +/// Get a Mail from a Queue or timeout if Queue is empty. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block by returning it to a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queue available + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS_H_ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c new file mode 100644 index 0000000..69ac328 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c @@ -0,0 +1,2482 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: cmsis_os2.c + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#include + +#include "cmsis_os2.h" // ::CMSIS:RTOS2 +#include "cmsis_compiler.h" // Compiler agnostic definitions + +#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core +#include "task.h" // ARM.FreeRTOS::RTOS:Core +#include "event_groups.h" // ARM.FreeRTOS::RTOS:Event Groups +#include "semphr.h" // ARM.FreeRTOS::RTOS:Core + +#include "freertos_mpool.h" // osMemoryPool definitions +#include "freertos_os2.h" // Configuration check and setup + +/*---------------------------------------------------------------------------*/ +#ifndef __ARM_ARCH_6M__ + #define __ARM_ARCH_6M__ 0 +#endif +#ifndef __ARM_ARCH_7M__ + #define __ARM_ARCH_7M__ 0 +#endif +#ifndef __ARM_ARCH_7EM__ + #define __ARM_ARCH_7EM__ 0 +#endif +#ifndef __ARM_ARCH_8M_MAIN__ + #define __ARM_ARCH_8M_MAIN__ 0 +#endif +#ifndef __ARM_ARCH_7A__ + #define __ARM_ARCH_7A__ 0 +#endif + +#if ((__ARM_ARCH_7M__ == 1U) || \ + (__ARM_ARCH_7EM__ == 1U) || \ + (__ARM_ARCH_8M_MAIN__ == 1U)) +#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U)) +#elif (__ARM_ARCH_6M__ == 1U) +#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) +#elif (__ARM_ARCH_7A__ == 1U) +/* CPSR mask bits */ +#define CPSR_MASKBIT_I 0x80U + +#define IS_IRQ_MASKED() ((__get_CPSR() & CPSR_MASKBIT_I) != 0U) +#else +#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) +#endif + +#if (__ARM_ARCH_7A__ == 1U) +/* CPSR mode bitmasks */ +#define CPSR_MODE_USER 0x10U +#define CPSR_MODE_SYSTEM 0x1FU + +#define IS_IRQ_MODE() ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM)) +#else +#define IS_IRQ_MODE() (__get_IPSR() != 0U) +#endif + +#define IS_IRQ() IS_IRQ_MODE() + +#define SVCall_IRQ_NBR (IRQn_Type) -5 /* SVCall_IRQ_NBR added as SV_Call handler name is not the same for CM0 and for all other CMx */ + +/* Limits */ +#define MAX_BITS_TASK_NOTIFY 31U +#define MAX_BITS_EVENT_GROUPS 24U + +#define THREAD_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_TASK_NOTIFY) - 1U)) +#define EVENT_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_EVENT_GROUPS) - 1U)) + +/* Kernel version and identification string definition (major.minor.rev: mmnnnrrrr dec) */ +#define KERNEL_VERSION (((uint32_t)tskKERNEL_VERSION_MAJOR * 10000000UL) | \ + ((uint32_t)tskKERNEL_VERSION_MINOR * 10000UL) | \ + ((uint32_t)tskKERNEL_VERSION_BUILD * 1UL)) + +#define KERNEL_ID ("FreeRTOS " tskKERNEL_VERSION_NUMBER) + +/* Timer callback information structure definition */ +typedef struct { + osTimerFunc_t func; + void *arg; +} TimerCallback_t; + +/* Kernel initialization state */ +static osKernelState_t KernelState = osKernelInactive; + +/* + Heap region definition used by heap_5 variant + + Define configAPPLICATION_ALLOCATED_HEAP as nonzero value in FreeRTOSConfig.h if + heap regions are already defined and vPortDefineHeapRegions is called in application. + + Otherwise vPortDefineHeapRegions will be called by osKernelInitialize using + definition configHEAP_5_REGIONS as parameter. Overriding configHEAP_5_REGIONS + is possible by defining it globally or in FreeRTOSConfig.h. +*/ +#if defined(USE_FreeRTOS_HEAP_5) +#if (configAPPLICATION_ALLOCATED_HEAP == 0) + /* + FreeRTOS heap is not defined by the application. + Single region of size configTOTAL_HEAP_SIZE (defined in FreeRTOSConfig.h) + is provided by default. Define configHEAP_5_REGIONS to provide custom + HeapRegion_t array. + */ + #define HEAP_5_REGION_SETUP 1 + + #ifndef configHEAP_5_REGIONS + #define configHEAP_5_REGIONS xHeapRegions + + static uint8_t ucHeap[configTOTAL_HEAP_SIZE]; + + static HeapRegion_t xHeapRegions[] = { + { ucHeap, configTOTAL_HEAP_SIZE }, + { NULL, 0 } + }; + #else + /* Global definition is provided to override default heap array */ + extern HeapRegion_t configHEAP_5_REGIONS[]; + #endif +#else + /* + The application already defined the array used for the FreeRTOS heap and + called vPortDefineHeapRegions to initialize heap. + */ + #define HEAP_5_REGION_SETUP 0 +#endif /* configAPPLICATION_ALLOCATED_HEAP */ +#endif /* USE_FreeRTOS_HEAP_5 */ + +#if defined(SysTick) +#undef SysTick_Handler + +/* CMSIS SysTick interrupt handler prototype */ +extern void SysTick_Handler (void); +/* FreeRTOS tick timer interrupt handler prototype */ +extern void xPortSysTickHandler (void); + +/* + SysTick handler implementation that also clears overflow flag. +*/ +#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) +void SysTick_Handler (void) { + /* Clear overflow flag */ + SysTick->CTRL; + + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { + /* Call tick handler */ + xPortSysTickHandler(); + } +} +#endif +#endif /* SysTick */ + +/* + Setup SVC to reset value. +*/ +__STATIC_INLINE void SVC_Setup (void) { +#if (__ARM_ARCH_7A__ == 0U) + /* Service Call interrupt might be configured before kernel start */ + /* and when its priority is lower or equal to BASEPRI, svc intruction */ + /* causes a Hard Fault. */ + NVIC_SetPriority (SVCall_IRQ_NBR, 0U); +#endif +} + +/* + Function macro used to retrieve semaphore count from ISR +*/ +#ifndef uxSemaphoreGetCountFromISR +#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) ) +#endif + +/* Get OS Tick count value */ +static uint32_t OS_Tick_GetCount (void); +/* Get OS Tick overflow status */ +static uint32_t OS_Tick_GetOverflow (void); +/* Get OS Tick interval */ +static uint32_t OS_Tick_GetInterval (void); +/*---------------------------------------------------------------------------*/ + +osStatus_t osKernelInitialize (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + if (KernelState == osKernelInactive) { + #if defined(USE_TRACE_EVENT_RECORDER) + EvrFreeRTOSSetup(0U); + #endif + #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) + vPortDefineHeapRegions (configHEAP_5_REGIONS); + #endif + KernelState = osKernelReady; + stat = osOK; + } else { + stat = osError; + } + } + + return (stat); +} + +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { + + if (version != NULL) { + /* Version encoding is major.minor.rev: mmnnnrrrr dec */ + version->api = KERNEL_VERSION; + version->kernel = KERNEL_VERSION; + } + + if ((id_buf != NULL) && (id_size != 0U)) { + if (id_size > sizeof(KERNEL_ID)) { + id_size = sizeof(KERNEL_ID); + } + memcpy(id_buf, KERNEL_ID, id_size); + } + + return (osOK); +} + +osKernelState_t osKernelGetState (void) { + osKernelState_t state; + + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_RUNNING: + state = osKernelRunning; + break; + + case taskSCHEDULER_SUSPENDED: + state = osKernelLocked; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + if (KernelState == osKernelReady) { + state = osKernelReady; + } else { + state = osKernelInactive; + } + break; + } + + return (state); +} + +osStatus_t osKernelStart (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + if (KernelState == osKernelReady) { + /* Ensure SVC priority is at the reset value */ + SVC_Setup(); + /* Change state to enable IRQ masking check */ + KernelState = osKernelRunning; + /* Start the kernel scheduler */ + vTaskStartScheduler(); + stat = osOK; + } else { + stat = osError; + } + } + + return (stat); +} + +int32_t osKernelLock (void) { + int32_t lock; + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + lock = 1; + break; + + case taskSCHEDULER_RUNNING: + vTaskSuspendAll(); + lock = 0; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +int32_t osKernelUnlock (void) { + int32_t lock; + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + lock = 1; + + if (xTaskResumeAll() != pdTRUE) { + if (xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED) { + lock = (int32_t)osError; + } + } + break; + + case taskSCHEDULER_RUNNING: + lock = 0; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +int32_t osKernelRestoreLock (int32_t lock) { + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + case taskSCHEDULER_RUNNING: + if (lock == 1) { + vTaskSuspendAll(); + } + else { + if (lock != 0) { + lock = (int32_t)osError; + } + else { + if (xTaskResumeAll() != pdTRUE) { + if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) { + lock = (int32_t)osError; + } + } + } + } + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +uint32_t osKernelGetTickCount (void) { + TickType_t ticks; + + if (IS_IRQ()) { + ticks = xTaskGetTickCountFromISR(); + } else { + ticks = xTaskGetTickCount(); + } + + return (ticks); +} + +uint32_t osKernelGetTickFreq (void) { + return (configTICK_RATE_HZ); +} + +/* Get OS Tick count value */ +static uint32_t OS_Tick_GetCount (void) { + uint32_t load = SysTick->LOAD; + return (load - SysTick->VAL); +} + +/* Get OS Tick overflow status */ +static uint32_t OS_Tick_GetOverflow (void) { + return ((SysTick->CTRL >> 16) & 1U); +} + +/* Get OS Tick interval */ +static uint32_t OS_Tick_GetInterval (void) { + return (SysTick->LOAD + 1U); +} + +uint32_t osKernelGetSysTimerCount (void) { + uint32_t irqmask = IS_IRQ_MASKED(); + TickType_t ticks; + uint32_t val; + + __disable_irq(); + + ticks = xTaskGetTickCount(); + val = OS_Tick_GetCount(); + + if (OS_Tick_GetOverflow() != 0U) { + val = OS_Tick_GetCount(); + ticks++; + } + val += ticks * OS_Tick_GetInterval(); + + if (irqmask == 0U) { + __enable_irq(); + } + + return (val); +} + +uint32_t osKernelGetSysTimerFreq (void) { + return (configCPU_CLOCK_HZ); +} + +/*---------------------------------------------------------------------------*/ + +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { + const char *name; + uint32_t stack; + TaskHandle_t hTask; + UBaseType_t prio; + int32_t mem; + + hTask = NULL; + + if (!IS_IRQ() && (func != NULL)) { + stack = configMINIMAL_STACK_SIZE; + prio = (UBaseType_t)osPriorityNormal; + + name = NULL; + mem = -1; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + if (attr->priority != osPriorityNone) { + prio = (UBaseType_t)attr->priority; + } + + if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { + return (NULL); + } + + if (attr->stack_size > 0U) { + /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ + /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ + stack = attr->stack_size / sizeof(StackType_t); + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && + (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, + (StaticTask_t *)attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { + hTask = NULL; + } + #endif + } + } + } + + return ((osThreadId_t)hTask); +} + +const char *osThreadGetName (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + const char *name; + + if (IS_IRQ() || (hTask == NULL)) { + name = NULL; + } else { + name = pcTaskGetName (hTask); + } + + return (name); +} + +osThreadId_t osThreadGetId (void) { + osThreadId_t id; + + id = (osThreadId_t)xTaskGetCurrentTaskHandle(); + + return (id); +} + +osThreadState_t osThreadGetState (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osThreadState_t state; + + if (IS_IRQ() || (hTask == NULL)) { + state = osThreadError; + } + else { + switch (eTaskGetState (hTask)) { + case eRunning: state = osThreadRunning; break; + case eReady: state = osThreadReady; break; + case eBlocked: + case eSuspended: state = osThreadBlocked; break; + case eDeleted: state = osThreadTerminated; break; + case eInvalid: + default: state = osThreadError; break; + } + } + + return (state); +} + +uint32_t osThreadGetStackSpace (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + uint32_t sz; + + if (IS_IRQ() || (hTask == NULL)) { + sz = 0U; + } else { + sz = (uint32_t)(uxTaskGetStackHighWaterMark(hTask) * sizeof(StackType_t)); + } + + return (sz); +} + +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if ((hTask == NULL) || (priority < osPriorityIdle) || (priority > osPriorityISR)) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskPrioritySet (hTask, (UBaseType_t)priority); + } + + return (stat); +} + +osPriority_t osThreadGetPriority (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osPriority_t prio; + + if (IS_IRQ() || (hTask == NULL)) { + prio = osPriorityError; + } else { + prio = (osPriority_t)((int32_t)uxTaskPriorityGet (hTask)); + } + + return (prio); +} + +osStatus_t osThreadYield (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } else { + stat = osOK; + taskYIELD(); + } + + return (stat); +} + +#if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) +osStatus_t osThreadSuspend (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskSuspend (hTask); + } + + return (stat); +} + +osStatus_t osThreadResume (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskResume (hTask); + } + + return (stat); +} +#endif /* (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) */ + +__NO_RETURN void osThreadExit (void) { +#ifndef USE_FreeRTOS_HEAP_1 + vTaskDelete (NULL); +#endif + for (;;); +} + +osStatus_t osThreadTerminate (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + eTaskState tstate; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + tstate = eTaskGetState (hTask); + + if (tstate != eDeleted) { + stat = osOK; + vTaskDelete (hTask); + } else { + stat = osErrorResource; + } + } +#else + stat = osError; +#endif + + return (stat); +} + +uint32_t osThreadGetCount (void) { + uint32_t count; + + if (IS_IRQ()) { + count = 0U; + } else { + count = uxTaskGetNumberOfTasks(); + } + + return (count); +} + +#if (configUSE_OS2_THREAD_ENUMERATE == 1) +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) { + uint32_t i, count; + TaskStatus_t *task; + + if (IS_IRQ() || (thread_array == NULL) || (array_items == 0U)) { + count = 0U; + } else { + vTaskSuspendAll(); + + count = uxTaskGetNumberOfTasks(); + task = pvPortMalloc (count * sizeof(TaskStatus_t)); + + if (task != NULL) { + count = uxTaskGetSystemState (task, count, NULL); + + for (i = 0U; (i < count) && (i < array_items); i++) { + thread_array[i] = (osThreadId_t)task[i].xHandle; + } + count = i; + } + (void)xTaskResumeAll(); + + vPortFree (task); + } + + return (count); +} +#endif /* (configUSE_OS2_THREAD_ENUMERATE == 1) */ + +#if (configUSE_OS2_THREAD_FLAGS == 1) +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + uint32_t rflags; + BaseType_t yield; + + if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else { + rflags = (uint32_t)osError; + + if (IS_IRQ()) { + yield = pdFALSE; + + (void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield); + (void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL); + + portYIELD_FROM_ISR (yield); + } + else { + (void)xTaskNotify (hTask, flags, eSetBits); + (void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags); + } + } + /* Return flags after setting */ + return (rflags); +} + +uint32_t osThreadFlagsClear (uint32_t flags) { + TaskHandle_t hTask; + uint32_t rflags, cflags; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) { + rflags = (uint32_t)osErrorParameter; + } + else { + hTask = xTaskGetCurrentTaskHandle(); + + if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &cflags) == pdPASS) { + rflags = cflags; + cflags &= ~flags; + + if (xTaskNotify (hTask, cflags, eSetValueWithOverwrite) != pdPASS) { + rflags = (uint32_t)osError; + } + } + else { + rflags = (uint32_t)osError; + } + } + + /* Return flags before clearing */ + return (rflags); +} + +uint32_t osThreadFlagsGet (void) { + TaskHandle_t hTask; + uint32_t rflags; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else { + hTask = xTaskGetCurrentTaskHandle(); + + if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags) != pdPASS) { + rflags = (uint32_t)osError; + } + } + + return (rflags); +} + +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { + uint32_t rflags, nval; + uint32_t clear; + TickType_t t0, td, tout; + BaseType_t rval; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) { + rflags = (uint32_t)osErrorParameter; + } + else { + if ((options & osFlagsNoClear) == osFlagsNoClear) { + clear = 0U; + } else { + clear = flags; + } + + rflags = 0U; + tout = timeout; + + t0 = xTaskGetTickCount(); + do { + rval = xTaskNotifyWait (0, clear, &nval, tout); + + if (rval == pdPASS) { + rflags &= flags; + rflags |= nval; + + if ((options & osFlagsWaitAll) == osFlagsWaitAll) { + if ((flags & rflags) == flags) { + break; + } else { + if (timeout == 0U) { + rflags = (uint32_t)osErrorResource; + break; + } + } + } + else { + if ((flags & rflags) != 0) { + break; + } else { + if (timeout == 0U) { + rflags = (uint32_t)osErrorResource; + break; + } + } + } + + /* Update timeout */ + td = xTaskGetTickCount() - t0; + + if (td > tout) { + tout = 0; + } else { + tout -= td; + } + } + else { + if (timeout == 0) { + rflags = (uint32_t)osErrorResource; + } else { + rflags = (uint32_t)osErrorTimeout; + } + } + } + while (rval != pdFAIL); + } + + /* Return flags before clearing */ + return (rflags); +} +#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ + +osStatus_t osDelay (uint32_t ticks) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + stat = osOK; + + if (ticks != 0U) { + vTaskDelay(ticks); + } + } + + return (stat); +} + +osStatus_t osDelayUntil (uint32_t ticks) { + TickType_t tcnt, delay; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + stat = osOK; + tcnt = xTaskGetTickCount(); + + /* Determine remaining number of ticks to delay */ + delay = (TickType_t)ticks - tcnt; + + /* Check if target tick has not expired */ + if((delay != 0U) && (0 == (delay >> (8 * sizeof(TickType_t) - 1)))) { + vTaskDelayUntil (&tcnt, delay); + } + else + { + /* No delay or already expired */ + stat = osErrorParameter; + } + } + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#if (configUSE_OS2_TIMER == 1) + +static void TimerCallback (TimerHandle_t hTimer) { + TimerCallback_t *callb; + + callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); + + if (callb != NULL) { + callb->func (callb->arg); + } +} + +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { + const char *name; + TimerHandle_t hTimer; + TimerCallback_t *callb; + UBaseType_t reload; + int32_t mem; + + hTimer = NULL; + + if (!IS_IRQ() && (func != NULL)) { + /* Allocate memory to store callback function and argument */ + callb = pvPortMalloc (sizeof(TimerCallback_t)); + + if (callb != NULL) { + callb->func = func; + callb->arg = argument; + + if (type == osTimerOnce) { + reload = pdFALSE; + } else { + reload = pdTRUE; + } + + mem = -1; + name = NULL; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); + #endif + } + } + + if ((hTimer == NULL) && (callb != NULL)) { + vPortFree (callb); + } + } + } + + return ((osTimerId_t)hTimer); +} + +const char *osTimerGetName (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + const char *p; + + if (IS_IRQ() || (hTimer == NULL)) { + p = NULL; + } else { + p = pcTimerGetName (hTimer); + } + + return (p); +} + +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { + stat = osOK; + } else { + stat = osErrorResource; + } + } + + return (stat); +} + +osStatus_t osTimerStop (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + if (xTimerIsTimerActive (hTimer) == pdFALSE) { + stat = osErrorResource; + } + else { + if (xTimerStop (hTimer, 0) == pdPASS) { + stat = osOK; + } else { + stat = osError; + } + } + } + + return (stat); +} + +uint32_t osTimerIsRunning (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + uint32_t running; + + if (IS_IRQ() || (hTimer == NULL)) { + running = 0U; + } else { + running = (uint32_t)xTimerIsTimerActive (hTimer); + } + + return (running); +} + +osStatus_t osTimerDelete (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + TimerCallback_t *callb; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); + + if (xTimerDelete (hTimer, 0) == pdPASS) { + vPortFree (callb); + stat = osOK; + } else { + stat = osErrorResource; + } + } +#else + stat = osError; +#endif + + return (stat); +} +#endif /* (configUSE_OS2_TIMER == 1) */ + +/*---------------------------------------------------------------------------*/ + +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) { + EventGroupHandle_t hEventGroup; + int32_t mem; + + hEventGroup = NULL; + + if (!IS_IRQ()) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticEventGroup_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hEventGroup = xEventGroupCreateStatic (attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hEventGroup = xEventGroupCreate(); + #endif + } + } + } + + return ((osEventFlagsId_t)hEventGroup); +} + +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + BaseType_t yield; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { + #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0) + (void)yield; + /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */ + rflags = (uint32_t)osErrorResource; + #else + yield = pdFALSE; + + if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) == pdFAIL) { + rflags = (uint32_t)osErrorResource; + } else { + rflags = flags; + portYIELD_FROM_ISR (yield); + } + #endif + } + else { + rflags = xEventGroupSetBits (hEventGroup, (EventBits_t)flags); + } + + return (rflags); +} + +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { + #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0) + /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */ + rflags = (uint32_t)osErrorResource; + #else + rflags = xEventGroupGetBitsFromISR (hEventGroup); + + if (xEventGroupClearBitsFromISR (hEventGroup, (EventBits_t)flags) == pdFAIL) { + rflags = (uint32_t)osErrorResource; + } + #endif + } + else { + rflags = xEventGroupClearBits (hEventGroup, (EventBits_t)flags); + } + + return (rflags); +} + +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + + if (ef_id == NULL) { + rflags = 0U; + } + else if (IS_IRQ()) { + rflags = xEventGroupGetBitsFromISR (hEventGroup); + } + else { + rflags = xEventGroupGetBits (hEventGroup); + } + + return (rflags); +} + +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + BaseType_t wait_all; + BaseType_t exit_clr; + uint32_t rflags; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else { + if (options & osFlagsWaitAll) { + wait_all = pdTRUE; + } else { + wait_all = pdFAIL; + } + + if (options & osFlagsNoClear) { + exit_clr = pdFAIL; + } else { + exit_clr = pdTRUE; + } + + rflags = xEventGroupWaitBits (hEventGroup, (EventBits_t)flags, exit_clr, wait_all, (TickType_t)timeout); + + if (options & osFlagsWaitAll) { + if ((flags & rflags) != flags) { + if (timeout > 0U) { + rflags = (uint32_t)osErrorTimeout; + } else { + rflags = (uint32_t)osErrorResource; + } + } + } + else { + if ((flags & rflags) == 0U) { + if (timeout > 0U) { + rflags = (uint32_t)osErrorTimeout; + } else { + rflags = (uint32_t)osErrorResource; + } + } + } + } + + return (rflags); +} + +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hEventGroup == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vEventGroupDelete (hEventGroup); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#if (configUSE_OS2_MUTEX == 1) + +osMutexId_t osMutexNew (const osMutexAttr_t *attr) { + SemaphoreHandle_t hMutex; + uint32_t type; + uint32_t rmtx; + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hMutex = NULL; + + if (!IS_IRQ()) { + if (attr != NULL) { + type = attr->attr_bits; + } else { + type = 0U; + } + + if ((type & osMutexRecursive) == osMutexRecursive) { + rmtx = 1U; + } else { + rmtx = 0U; + } + + if ((type & osMutexRobust) != osMutexRobust) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); + #endif + } + else { + hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); + } + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + hMutex = xSemaphoreCreateRecursiveMutex (); + #endif + } else { + hMutex = xSemaphoreCreateMutex (); + } + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hMutex != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hMutex, name); + } + #endif + + if ((hMutex != NULL) && (rmtx != 0U)) { + hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); + } + } + } + + return ((osMutexId_t)hMutex); +} + +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { + SemaphoreHandle_t hMutex; + osStatus_t stat; + uint32_t rmtx; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + rmtx = (uint32_t)mutex_id & 1U; + + stat = osOK; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + #endif + } + else { + if (xSemaphoreTake (hMutex, timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +osStatus_t osMutexRelease (osMutexId_t mutex_id) { + SemaphoreHandle_t hMutex; + osStatus_t stat; + uint32_t rmtx; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + rmtx = (uint32_t)mutex_id & 1U; + + stat = osOK; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { + stat = osErrorResource; + } + #endif + } + else { + if (xSemaphoreGive (hMutex) != pdPASS) { + stat = osErrorResource; + } + } + } + + return (stat); +} + +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) { + SemaphoreHandle_t hMutex; + osThreadId_t owner; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + if (IS_IRQ() || (hMutex == NULL)) { + owner = NULL; + } else { + owner = (osThreadId_t)xSemaphoreGetMutexHolder (hMutex); + } + + return (owner); +} + +osStatus_t osMutexDelete (osMutexId_t mutex_id) { + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + SemaphoreHandle_t hMutex; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + #if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hMutex); + #endif + stat = osOK; + vSemaphoreDelete (hMutex); + } +#else + stat = osError; +#endif + + return (stat); +} +#endif /* (configUSE_OS2_MUTEX == 1) */ + +/*---------------------------------------------------------------------------*/ + +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { + SemaphoreHandle_t hSemaphore; + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hSemaphore = NULL; + + if (!IS_IRQ() && (max_count > 0U) && (initial_count <= max_count)) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem != -1) { + if (max_count == 1U) { + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem); + #endif + } + else { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateBinary(); + #endif + } + + if ((hSemaphore != NULL) && (initial_count != 0U)) { + if (xSemaphoreGive (hSemaphore) != pdPASS) { + vSemaphoreDelete (hSemaphore); + hSemaphore = NULL; + } + } + } + else { + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem); + #endif + } + else { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateCounting (max_count, initial_count); + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hSemaphore != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hSemaphore, name); + } + #endif + } + } + + return ((osSemaphoreId_t)hSemaphore); +} + +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + BaseType_t yield; + + stat = osOK; + + if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else if (IS_IRQ()) { + if (timeout != 0U) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + + return (stat); +} + +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + BaseType_t yield; + + stat = osOK; + + if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else if (IS_IRQ()) { + yield = pdFALSE; + + if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + else { + if (xSemaphoreGive (hSemaphore) != pdPASS) { + stat = osErrorResource; + } + } + + return (stat); +} + +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + uint32_t count; + + if (hSemaphore == NULL) { + count = 0U; + } + else if (IS_IRQ()) { + count = uxQueueMessagesWaitingFromISR (hSemaphore); + } else { + count = (uint32_t)uxSemaphoreGetCount (hSemaphore); + } + + return (count); +} + +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else { + #if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hSemaphore); + #endif + + stat = osOK; + vSemaphoreDelete (hSemaphore); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ + +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { + QueueHandle_t hQueue; + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hQueue = NULL; + + if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && + (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && + (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hQueue = xQueueCreate (msg_count, msg_size); + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hQueue != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hQueue, name); + } + #endif + + } + + return ((osMessageQueueId_t)hQueue); +} + +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + BaseType_t yield; + + (void)msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if (IS_IRQ()) { + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } + else { + if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + BaseType_t yield; + + (void)msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if (IS_IRQ()) { + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } + else { + if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t capacity; + + if (mq == NULL) { + capacity = 0U; + } else { + /* capacity = pxQueue->uxLength */ + capacity = mq->uxDummy4[1]; + } + + return (capacity); +} + +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t size; + + if (mq == NULL) { + size = 0U; + } else { + /* size = pxQueue->uxItemSize */ + size = mq->uxDummy4[2]; + } + + return (size); +} + +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + UBaseType_t count; + + if (hQueue == NULL) { + count = 0U; + } + else if (IS_IRQ()) { + count = uxQueueMessagesWaitingFromISR (hQueue); + } + else { + count = uxQueueMessagesWaiting (hQueue); + } + + return ((uint32_t)count); +} + +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t space; + uint32_t isrm; + + if (mq == NULL) { + space = 0U; + } + else if (IS_IRQ()) { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */ + space = mq->uxDummy4[1] - mq->uxDummy4[0]; + + taskEXIT_CRITICAL_FROM_ISR(isrm); + } + else { + space = (uint32_t)uxQueueSpacesAvailable ((QueueHandle_t)mq); + } + + return (space); +} + +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hQueue == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + (void)xQueueReset (hQueue); + } + + return (stat); +} + +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hQueue == NULL) { + stat = osErrorParameter; + } + else { + #if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hQueue); + #endif + + stat = osOK; + vQueueDelete (hQueue); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#ifdef FREERTOS_MPOOL_H_ + +/* Static memory pool functions */ +static void FreeBlock (MemPool_t *mp, void *block); +static void *AllocBlock (MemPool_t *mp); +static void *CreateBlock (MemPool_t *mp); + +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { + MemPool_t *mp; + const char *name; + int32_t mem_cb, mem_mp; + uint32_t sz; + + if (IS_IRQ()) { + mp = NULL; + } + else if ((block_count == 0U) || (block_size == 0U)) { + mp = NULL; + } + else { + mp = NULL; + sz = MEMPOOL_ARR_SIZE (block_count, block_size); + + name = NULL; + mem_cb = -1; + mem_mp = -1; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(MemPool_t))) { + /* Static control block is provided */ + mem_cb = 1; + } + else if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + /* Allocate control block memory on heap */ + mem_cb = 0; + } + + if ((attr->mp_mem == NULL) && (attr->mp_size == 0U)) { + /* Allocate memory array on heap */ + mem_mp = 0; + } + else { + if (attr->mp_mem != NULL) { + /* Check if array is 4-byte aligned */ + if (((uint32_t)attr->mp_mem & 3U) == 0U) { + /* Check if array big enough */ + if (attr->mp_size >= sz) { + /* Static memory pool array is provided */ + mem_mp = 1; + } + } + } + } + } + else { + /* Attributes not provided, allocate memory on heap */ + mem_cb = 0; + mem_mp = 0; + } + + if (mem_cb == 0) { + mp = pvPortMalloc (sizeof(MemPool_t)); + } else { + mp = attr->cb_mem; + } + + if (mp != NULL) { + /* Create a semaphore (max count == initial count == block_count) */ + #if (configSUPPORT_STATIC_ALLOCATION == 1) + mp->sem = xSemaphoreCreateCountingStatic (block_count, block_count, &mp->mem_sem); + #elif (configSUPPORT_DYNAMIC_ALLOCATION == 1) + mp->sem = xSemaphoreCreateCounting (block_count, block_count); + #else + mp->sem == NULL; + #endif + + if (mp->sem != NULL) { + /* Setup memory array */ + if (mem_mp == 0) { + mp->mem_arr = pvPortMalloc (sz); + } else { + mp->mem_arr = attr->mp_mem; + } + } + } + + if ((mp != NULL) && (mp->mem_arr != NULL)) { + /* Memory pool can be created */ + mp->head = NULL; + mp->mem_sz = sz; + mp->name = name; + mp->bl_sz = block_size; + mp->bl_cnt = block_count; + mp->n = 0U; + + /* Set heap allocated memory flags */ + mp->status = MPOOL_STATUS; + + if (mem_cb == 0) { + /* Control block on heap */ + mp->status |= 1U; + } + if (mem_mp == 0) { + /* Memory array on heap */ + mp->status |= 2U; + } + } + else { + /* Memory pool cannot be created, release allocated resources */ + if ((mem_cb == 0) && (mp != NULL)) { + /* Free control block memory */ + vPortFree (mp); + } + mp = NULL; + } + } + + return (mp); +} + +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) { + MemPool_t *mp = (osMemoryPoolId_t)mp_id; + const char *p; + + if (IS_IRQ()) { + p = NULL; + } + else if (mp_id == NULL) { + p = NULL; + } + else { + p = mp->name; + } + + return (p); +} + +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { + MemPool_t *mp; + void *block; + uint32_t isrm; + + if (mp_id == NULL) { + /* Invalid input parameters */ + block = NULL; + } + else { + block = NULL; + + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + if (IS_IRQ()) { + if (timeout == 0U) { + if (xSemaphoreTakeFromISR (mp->sem, NULL) == pdTRUE) { + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* Get a block from the free-list */ + block = AllocBlock(mp); + + if (block == NULL) { + /* List of free blocks is empty, 'create' new block */ + block = CreateBlock(mp); + } + + taskEXIT_CRITICAL_FROM_ISR(isrm); + } + } + } + } + else { + if (xSemaphoreTake (mp->sem, (TickType_t)timeout) == pdTRUE) { + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + taskENTER_CRITICAL(); + + /* Get a block from the free-list */ + block = AllocBlock(mp); + + if (block == NULL) { + /* List of free blocks is empty, 'create' new block */ + block = CreateBlock(mp); + } + + taskEXIT_CRITICAL(); + } + } + } + } + } + + return (block); +} + +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { + MemPool_t *mp; + osStatus_t stat; + uint32_t isrm; + BaseType_t yield; + + if ((mp_id == NULL) || (block == NULL)) { + /* Invalid input parameters */ + stat = osErrorParameter; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + stat = osErrorResource; + } + else if ((block < (void *)&mp->mem_arr[0]) || (block > (void*)&mp->mem_arr[mp->mem_sz-1])) { + /* Block pointer outside of memory array area */ + stat = osErrorParameter; + } + else { + stat = osOK; + + if (IS_IRQ()) { + if (uxSemaphoreGetCountFromISR (mp->sem) == mp->bl_cnt) { + stat = osErrorResource; + } + else { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* Add block to the list of free blocks */ + FreeBlock(mp, block); + + taskEXIT_CRITICAL_FROM_ISR(isrm); + + yield = pdFALSE; + xSemaphoreGiveFromISR (mp->sem, &yield); + portYIELD_FROM_ISR (yield); + } + } + else { + if (uxSemaphoreGetCount (mp->sem) == mp->bl_cnt) { + stat = osErrorResource; + } + else { + taskENTER_CRITICAL(); + + /* Add block to the list of free blocks */ + FreeBlock(mp, block); + + taskEXIT_CRITICAL(); + + xSemaphoreGive (mp->sem); + } + } + } + } + + return (stat); +} + +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + n = mp->bl_cnt; + } + } + + /* Return maximum number of memory blocks */ + return (n); +} + +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t sz; + + if (mp_id == NULL) { + /* Invalid input parameters */ + sz = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + sz = 0U; + } + else { + sz = mp->bl_sz; + } + } + + /* Return memory block size in bytes */ + return (sz); +} + +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + if (IS_IRQ()) { + n = uxSemaphoreGetCountFromISR (mp->sem); + } else { + n = uxSemaphoreGetCount (mp->sem); + } + + n = mp->bl_cnt - n; + } + } + + /* Return number of memory blocks used */ + return (n); +} + +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + if (IS_IRQ()) { + n = uxSemaphoreGetCountFromISR (mp->sem); + } else { + n = uxSemaphoreGetCount (mp->sem); + } + } + } + + /* Return number of memory blocks available */ + return (n); +} + +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + osStatus_t stat; + + if (mp_id == NULL) { + /* Invalid input parameters */ + stat = osErrorParameter; + } + else if (IS_IRQ()) { + stat = osErrorISR; + } + else { + mp = (MemPool_t *)mp_id; + + taskENTER_CRITICAL(); + + /* Invalidate control block status */ + mp->status = mp->status & 3U; + + /* Wake-up tasks waiting for pool semaphore */ + while (xSemaphoreGive (mp->sem) == pdTRUE); + + mp->head = NULL; + mp->bl_sz = 0U; + mp->bl_cnt = 0U; + + if ((mp->status & 2U) != 0U) { + /* Memory pool array allocated on heap */ + vPortFree (mp->mem_arr); + } + if ((mp->status & 1U) != 0U) { + /* Memory pool control block allocated on heap */ + vPortFree (mp); + } + + taskEXIT_CRITICAL(); + + stat = osOK; + } + + return (stat); +} + +/* + Create new block given according to the current block index. +*/ +static void *CreateBlock (MemPool_t *mp) { + MemPoolBlock_t *p = NULL; + + if (mp->n < mp->bl_cnt) { + /* Unallocated blocks exist, set pointer to new block */ + p = (void *)(mp->mem_arr + (mp->bl_sz * mp->n)); + + /* Increment block index */ + mp->n += 1U; + } + + return (p); +} + +/* + Allocate a block by reading the list of free blocks. +*/ +static void *AllocBlock (MemPool_t *mp) { + MemPoolBlock_t *p = NULL; + + if (mp->head != NULL) { + /* List of free block exists, get head block */ + p = mp->head; + + /* Head block is now next on the list */ + mp->head = p->next; + } + + return (p); +} + +/* + Free block by putting it to the list of free blocks. +*/ +static void FreeBlock (MemPool_t *mp, void *block) { + MemPoolBlock_t *p = block; + + /* Store current head into block memory space */ + p->next = mp->head; + + /* Store current block as new head */ + mp->head = p; +} +#endif /* FREERTOS_MPOOL_H_ */ +/*---------------------------------------------------------------------------*/ + +/* Callback function prototypes */ +extern void vApplicationIdleHook (void); +extern void vApplicationTickHook (void); +extern void vApplicationMallocFailedHook (void); +extern void vApplicationDaemonTaskStartupHook (void); +extern void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName); + +/** + Dummy implementation of the callback function vApplicationIdleHook(). +*/ +#if (configUSE_IDLE_HOOK == 1) +__WEAK void vApplicationIdleHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationTickHook(). +*/ +#if (configUSE_TICK_HOOK == 1) + __WEAK void vApplicationTickHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationMallocFailedHook(). +*/ +#if (configUSE_MALLOC_FAILED_HOOK == 1) +__WEAK void vApplicationMallocFailedHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationDaemonTaskStartupHook(). +*/ +#if (configUSE_DAEMON_TASK_STARTUP_HOOK == 1) +__WEAK void vApplicationDaemonTaskStartupHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationStackOverflowHook(). +*/ +#if (configCHECK_FOR_STACK_OVERFLOW > 0) +__WEAK void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName) { + (void)xTask; + (void)pcTaskName; + configASSERT(0); +} +#endif + +/*---------------------------------------------------------------------------*/ +#if (configSUPPORT_STATIC_ALLOCATION == 1) +/* External Idle and Timer task static memory allocation functions */ +extern void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize); +extern void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize); + +/* + vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { + /* Idle task control block and stack */ + static StaticTask_t Idle_TCB; + static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; + + *ppxIdleTaskTCBBuffer = &Idle_TCB; + *ppxIdleTaskStackBuffer = &Idle_Stack[0]; + *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; +} + +/* + vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { + /* Timer task control block and stack */ + static StaticTask_t Timer_TCB; + static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; + + *ppxTimerTaskTCBBuffer = &Timer_TCB; + *ppxTimerTaskStackBuffer = &Timer_Stack[0]; + *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; +} +#endif diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h new file mode 100644 index 0000000..9774cc7 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h @@ -0,0 +1,734 @@ +/* -------------------------------------------------------------------------- + * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * -------------------------------------------------------------------------- + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: cmsis_os2.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS2_H_ +#define CMSIS_OS2_H_ + +#ifndef __NO_RETURN +#if defined(__CC_ARM) +#define __NO_RETURN __declspec(noreturn) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__GNUC__) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__ICCARM__) +#define __NO_RETURN __noreturn +#else +#define __NO_RETURN +#endif +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Version information. +typedef struct { + uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec). + uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec). +} osVersion_t; + +/// Kernel state. +typedef enum { + osKernelInactive = 0, ///< Inactive. + osKernelReady = 1, ///< Ready. + osKernelRunning = 2, ///< Running. + osKernelLocked = 3, ///< Locked. + osKernelSuspended = 4, ///< Suspended. + osKernelError = -1, ///< Error. + osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization. +} osKernelState_t; + +/// Thread state. +typedef enum { + osThreadInactive = 0, ///< Inactive. + osThreadReady = 1, ///< Ready. + osThreadRunning = 2, ///< Running. + osThreadBlocked = 3, ///< Blocked. + osThreadTerminated = 4, ///< Terminated. + osThreadError = -1, ///< Error. + osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osThreadState_t; + +/// Priority values. +typedef enum { + osPriorityNone = 0, ///< No priority (not initialized). + osPriorityIdle = 1, ///< Reserved for Idle thread. + osPriorityLow = 8, ///< Priority: low + osPriorityLow1 = 8+1, ///< Priority: low + 1 + osPriorityLow2 = 8+2, ///< Priority: low + 2 + osPriorityLow3 = 8+3, ///< Priority: low + 3 + osPriorityLow4 = 8+4, ///< Priority: low + 4 + osPriorityLow5 = 8+5, ///< Priority: low + 5 + osPriorityLow6 = 8+6, ///< Priority: low + 6 + osPriorityLow7 = 8+7, ///< Priority: low + 7 + osPriorityBelowNormal = 16, ///< Priority: below normal + osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1 + osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2 + osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3 + osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4 + osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5 + osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6 + osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7 + osPriorityNormal = 24, ///< Priority: normal + osPriorityNormal1 = 24+1, ///< Priority: normal + 1 + osPriorityNormal2 = 24+2, ///< Priority: normal + 2 + osPriorityNormal3 = 24+3, ///< Priority: normal + 3 + osPriorityNormal4 = 24+4, ///< Priority: normal + 4 + osPriorityNormal5 = 24+5, ///< Priority: normal + 5 + osPriorityNormal6 = 24+6, ///< Priority: normal + 6 + osPriorityNormal7 = 24+7, ///< Priority: normal + 7 + osPriorityAboveNormal = 32, ///< Priority: above normal + osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1 + osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2 + osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3 + osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4 + osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5 + osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6 + osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7 + osPriorityHigh = 40, ///< Priority: high + osPriorityHigh1 = 40+1, ///< Priority: high + 1 + osPriorityHigh2 = 40+2, ///< Priority: high + 2 + osPriorityHigh3 = 40+3, ///< Priority: high + 3 + osPriorityHigh4 = 40+4, ///< Priority: high + 4 + osPriorityHigh5 = 40+5, ///< Priority: high + 5 + osPriorityHigh6 = 40+6, ///< Priority: high + 6 + osPriorityHigh7 = 40+7, ///< Priority: high + 7 + osPriorityRealtime = 48, ///< Priority: realtime + osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1 + osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2 + osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3 + osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4 + osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5 + osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6 + osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7 + osPriorityISR = 56, ///< Reserved for ISR deferred thread. + osPriorityError = -1, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority_t; + +/// Entry point of a thread. +typedef void (*osThreadFunc_t) (void *argument); + +/// Timer callback function. +typedef void (*osTimerFunc_t) (void *argument); + +/// Timer type. +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} osTimerType_t; + +// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). +#define osFlagsWaitAll 0x00000001U ///< Wait for all flags. +#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. + +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +#define osFlagsError 0x80000000U ///< Error indicator. +#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). +#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). +#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3). +#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). +#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). + +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode + +// Mutex attributes (attr_bits in \ref osMutexAttr_t). +#define osMutexRecursive 0x00000001U ///< Recursive mutex. +#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. +#define osMutexRobust 0x00000008U ///< Robust mutex. + +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + + +/// \details Thread ID identifies the thread. +typedef void *osThreadId_t; + +/// \details Timer ID identifies the timer. +typedef void *osTimerId_t; + +/// \details Event Flags ID identifies the event flags. +typedef void *osEventFlagsId_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +/// \details Semaphore ID identifies the semaphore. +typedef void *osSemaphoreId_t; + +/// \details Memory Pool ID identifies the memory pool. +typedef void *osMemoryPoolId_t; + +/// \details Message Queue ID identifies the message queue. +typedef void *osMessageQueueId_t; + + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + + +/// Attributes structure for thread. +typedef struct { + const char *name; ///< name of the thread + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *stack_mem; ///< memory for stack + uint32_t stack_size; ///< size of stack + osPriority_t priority; ///< initial thread priority (default: osPriorityNormal) + TZ_ModuleId_t tz_module; ///< TrustZone module identifier + uint32_t reserved; ///< reserved (must be 0) +} osThreadAttr_t; + +/// Attributes structure for timer. +typedef struct { + const char *name; ///< name of the timer + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osTimerAttr_t; + +/// Attributes structure for event flags. +typedef struct { + const char *name; ///< name of the event flags + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osEventFlagsAttr_t; + +/// Attributes structure for mutex. +typedef struct { + const char *name; ///< name of the mutex + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osMutexAttr_t; + +/// Attributes structure for semaphore. +typedef struct { + const char *name; ///< name of the semaphore + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osSemaphoreAttr_t; + +/// Attributes structure for memory pool. +typedef struct { + const char *name; ///< name of the memory pool + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mp_mem; ///< memory for data storage + uint32_t mp_size; ///< size of provided memory for data storage +} osMemoryPoolAttr_t; + +/// Attributes structure for message queue. +typedef struct { + const char *name; ///< name of the message queue + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mq_mem; ///< memory for data storage + uint32_t mq_size; ///< size of provided memory for data storage +} osMessageQueueAttr_t; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelInitialize (void); + +/// Get RTOS Kernel Information. +/// \param[out] version pointer to buffer for retrieving version information. +/// \param[out] id_buf pointer to buffer for retrieving kernel identification string. +/// \param[in] id_size size of buffer for kernel identification string. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); + +/// Get the current RTOS Kernel state. +/// \return current RTOS Kernel state. +osKernelState_t osKernelGetState (void); + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelStart (void); + +/// Lock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelLock (void); + +/// Unlock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelUnlock (void); + +/// Restore the RTOS Kernel scheduler lock state. +/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +/// \return new lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelRestoreLock (int32_t lock); + +/// Suspend the RTOS Kernel scheduler. +/// \return time in ticks, for how long the system can sleep or power-down. +uint32_t osKernelSuspend (void); + +/// Resume the RTOS Kernel scheduler. +/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode. +void osKernelResume (uint32_t sleep_ticks); + +/// Get the RTOS kernel tick count. +/// \return RTOS kernel current tick count. +uint32_t osKernelGetTickCount (void); + +/// Get the RTOS kernel tick frequency. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. +uint32_t osKernelGetTickFreq (void); + +/// Get the RTOS kernel system timer count. +/// \return RTOS kernel current system timer count as 32-bit value. +uint32_t osKernelGetSysTimerCount (void); + +/// Get the RTOS kernel system timer frequency. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. +uint32_t osKernelGetSysTimerFreq (void); + + +// ==== Thread Management Functions ==== + +/// Create a thread and add it to Active Threads. +/// \param[in] func thread function. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \param[in] attr thread attributes; NULL: default values. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); + +/// Get name of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return name as NULL terminated string. +const char *osThreadGetName (osThreadId_t thread_id); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadGetId (void); + +/// Get current thread state of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current thread state of the specified thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id); + +/// Get stack size of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return stack size in bytes. +uint32_t osThreadGetStackSize (osThreadId_t thread_id); + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return remaining stack space in bytes. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id); + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current priority value of the specified thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadYield (void); + +/// Suspend execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSuspend (osThreadId_t thread_id); + +/// Resume execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadResume (osThreadId_t thread_id); + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadDetach (osThreadId_t thread_id); + +/// Wait for specified thread to terminate. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadJoin (osThreadId_t thread_id); + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void); + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadTerminate (osThreadId_t thread_id); + +/// Get number of active threads. +/// \return number of active threads. +uint32_t osThreadGetCount (void); + +/// Enumerate active threads. +/// \param[out] thread_array pointer to array for retrieving thread IDs. +/// \param[in] array_items maximum number of items in array for retrieving thread IDs. +/// \return number of enumerated threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); + + +// ==== Thread Flags Functions ==== + +/// Set the specified Thread Flags of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] flags specifies the flags of the thread that shall be set. +/// \return thread flags after setting or error code if highest bit set. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); + +/// Clear the specified Thread Flags of current running thread. +/// \param[in] flags specifies the flags of the thread that shall be cleared. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsClear (uint32_t flags); + +/// Get the current Thread Flags of current running thread. +/// \return current thread flags. +uint32_t osThreadFlagsGet (void); + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value +/// \return status code that indicates the execution status of the function. +osStatus_t osDelay (uint32_t ticks); + +/// Wait until specified time. +/// \param[in] ticks absolute time in ticks +/// \return status code that indicates the execution status of the function. +osStatus_t osDelayUntil (uint32_t ticks); + + +// ==== Timer Management Functions ==== + +/// Create and Initialize a timer. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. +/// \param[in] attr timer attributes; NULL: default values. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); + +/// Get name of a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return name as NULL terminated string. +const char *osTimerGetName (osTimerId_t timer_id); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks); + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStop (osTimerId_t timer_id); + +/// Check if a timer is running. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return 0 not running, 1 running. +uint32_t osTimerIsRunning (osTimerId_t timer_id); + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerDelete (osTimerId_t timer_id); + + +// ==== Event Flags Management Functions ==== + +/// Create and Initialize an Event Flags object. +/// \param[in] attr event flags attributes; NULL: default values. +/// \return event flags ID for reference by other functions or NULL in case of error. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); + +/// Get name of an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return name as NULL terminated string. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id); + +/// Set the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be set. +/// \return event flags after setting or error code if highest bit set. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); + +/// Clear the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be cleared. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); + +/// Get the current Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return current event flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id); + +/// Wait for one or more Event Flags to become signaled. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); + +/// Delete an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id); + + +// ==== Mutex Management Functions ==== + +/// Create and Initialize a Mutex object. +/// \param[in] attr mutex attributes; NULL: default values. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId_t osMutexNew (const osMutexAttr_t *attr); + +/// Get name of a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return name as NULL terminated string. +const char *osMutexGetName (osMutexId_t mutex_id); + +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease (osMutexId_t mutex_id); + +/// Get Thread which owns a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return thread ID of owner thread or NULL when mutex was not acquired. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id); + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexDelete (osMutexId_t mutex_id); + + +// ==== Semaphore Management Functions ==== + +/// Create and Initialize a Semaphore object. +/// \param[in] max_count maximum number of available tokens. +/// \param[in] initial_count initial number of available tokens. +/// \param[in] attr semaphore attributes; NULL: default values. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); + +/// Get name of a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return name as NULL terminated string. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); + +/// Release a Semaphore token up to the initial maximum count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); + +/// Get current Semaphore token count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return number of tokens available. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id); + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id); + + +// ==== Memory Pool Management Functions ==== + +/// Create and Initialize a Memory Pool object. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size memory block size in bytes. +/// \param[in] attr memory pool attributes; NULL: default values. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); + +/// Get name of a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return name as NULL terminated string. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); + +/// Get maximum number of memory blocks in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return maximum number of memory blocks. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); + +/// Get memory block size in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return memory block size in bytes. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks used in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks used. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks available in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks available. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id); + +/// Delete a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id); + + +// ==== Message Queue Management Functions ==== + +/// Create and Initialize a Message Queue object. +/// \param[in] msg_count maximum number of messages in queue. +/// \param[in] msg_size maximum message size in bytes. +/// \param[in] attr message queue attributes; NULL: default values. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); + +/// Get name of a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return name as NULL terminated string. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id); + +/// Put a Message into a Queue or timeout if Queue is full. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[in] msg_ptr pointer to buffer with message to put into a queue. +/// \param[in] msg_prio message priority. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[out] msg_ptr pointer to buffer for message to get from a queue. +/// \param[out] msg_prio pointer to buffer for message priority or NULL. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); + +/// Get maximum number of messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum number of messages. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id); + +/// Get maximum message size in a Memory Pool. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum message size in bytes. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id); + +/// Get number of queued messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of queued messages. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id); + +/// Get number of available slots for messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of available slots for messages. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id); + +/// Reset a Message Queue to initial empty state. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id); + +/// Delete a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS2_H_ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h new file mode 100644 index 0000000..cea5017 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h @@ -0,0 +1,63 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: freertos_mpool.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef FREERTOS_MPOOL_H_ +#define FREERTOS_MPOOL_H_ + +#include +#include "FreeRTOS.h" +#include "semphr.h" + +/* Memory Pool implementation definitions */ +#define MPOOL_STATUS 0x5EED0000U + +/* Memory Block header */ +typedef struct { + void *next; /* Pointer to next block */ +} MemPoolBlock_t; + +/* Memory Pool control block */ +typedef struct MemPoolDef_t { + MemPoolBlock_t *head; /* Pointer to head block */ + SemaphoreHandle_t sem; /* Pool semaphore handle */ + uint8_t *mem_arr; /* Pool memory array */ + uint32_t mem_sz; /* Pool memory array size */ + const char *name; /* Pointer to name string */ + uint32_t bl_sz; /* Size of a single block */ + uint32_t bl_cnt; /* Number of blocks */ + uint32_t n; /* Block allocation index */ + volatile uint32_t status; /* Object status flags */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t mem_sem; /* Semaphore object memory */ +#endif +} MemPool_t; + +/* No need to hide static object type, just align to coding style */ +#define StaticMemPool_t MemPool_t + +/* Define memory pool control block size */ +#define MEMPOOL_CB_SIZE (sizeof(StaticMemPool_t)) + +/* Define size of the byte array required to create count of blocks of given size */ +#define MEMPOOL_ARR_SIZE(bl_count, bl_size) (((((bl_size) + (4 - 1)) / 4) * 4)*(bl_count)) + +#endif /* FREERTOS_MPOOL_H_ */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h new file mode 100644 index 0000000..c125e2a --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h @@ -0,0 +1,310 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: freertos_os2.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef FREERTOS_OS2_H_ +#define FREERTOS_OS2_H_ + +#include +#include + +#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core + +#include CMSIS_device_header + +/* + CMSIS-RTOS2 FreeRTOS image size optimization definitions. + + Note: Definitions configUSE_OS2 can be used to optimize FreeRTOS image size when + certain functionality is not required when using CMSIS-RTOS2 API. + In general optimization decisions are left to the tool chain but in cases + when coding style prevents it to optimize the code following optional + definitions can be used. +*/ + +/* + Option to exclude CMSIS-RTOS2 functions osThreadSuspend and osThreadResume from + the application image. +*/ +#ifndef configUSE_OS2_THREAD_SUSPEND_RESUME +#define configUSE_OS2_THREAD_SUSPEND_RESUME 1 +#endif + +/* + Option to exclude CMSIS-RTOS2 function osThreadEnumerate from the application image. +*/ +#ifndef configUSE_OS2_THREAD_ENUMERATE +#define configUSE_OS2_THREAD_ENUMERATE 1 +#endif + +/* + Option to disable CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear + operation from ISR. +*/ +#ifndef configUSE_OS2_EVENTFLAGS_FROM_ISR +#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1 +#endif + +/* + Option to exclude CMSIS-RTOS2 Thread Flags API functions from the application image. +*/ +#ifndef configUSE_OS2_THREAD_FLAGS +#define configUSE_OS2_THREAD_FLAGS configUSE_TASK_NOTIFICATIONS +#endif + +/* + Option to exclude CMSIS-RTOS2 Timer API functions from the application image. +*/ +#ifndef configUSE_OS2_TIMER +#define configUSE_OS2_TIMER configUSE_TIMERS +#endif + +/* + Option to exclude CMSIS-RTOS2 Mutex API functions from the application image. +*/ +#ifndef configUSE_OS2_MUTEX +#define configUSE_OS2_MUTEX configUSE_MUTEXES +#endif + + +/* + CMSIS-RTOS2 FreeRTOS configuration check (FreeRTOSConfig.h). + + Note: CMSIS-RTOS API requires functions included by using following definitions. + In case if certain API function is not used compiler will optimize it away. +*/ +#if (INCLUDE_xSemaphoreGetMutexHolder == 0) + /* + CMSIS-RTOS2 function osMutexGetOwner uses FreeRTOS function xSemaphoreGetMutexHolder. In case if + osMutexGetOwner is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_xSemaphoreGetMutexHolder 1 to fix this error. + */ + #error "Definition INCLUDE_xSemaphoreGetMutexHolder must equal 1 to implement Mutex Management API." +#endif +#if (INCLUDE_vTaskDelay == 0) + /* + CMSIS-RTOS2 function osDelay uses FreeRTOS function vTaskDelay. In case if + osDelay is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskDelay 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelay must equal 1 to implement Generic Wait Functions API." +#endif +#if (INCLUDE_vTaskDelayUntil == 0) + /* + CMSIS-RTOS2 function osDelayUntil uses FreeRTOS function vTaskDelayUntil. In case if + osDelayUntil is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskDelayUntil 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelayUntil must equal 1 to implement Generic Wait Functions API." +#endif +#if (INCLUDE_vTaskDelete == 0) + /* + CMSIS-RTOS2 function osThreadTerminate and osThreadExit uses FreeRTOS function + vTaskDelete. In case if they are not used in the application image, compiler + will optimize them away. + Set #define INCLUDE_vTaskDelete 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelete must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_xTaskGetCurrentTaskHandle == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function xTaskGetCurrentTaskHandle to implement + functions osThreadGetId, osThreadFlagsClear and osThreadFlagsGet. In case if these + functions are not used in the application image, compiler will optimize them away. + Set #define INCLUDE_xTaskGetCurrentTaskHandle 1 to fix this error. + */ + #error "Definition INCLUDE_xTaskGetCurrentTaskHandle must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_xTaskGetSchedulerState == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function xTaskGetSchedulerState to implement Kernel + tick handling and therefore it is vital that xTaskGetSchedulerState is included into + the application image. + Set #define INCLUDE_xTaskGetSchedulerState 1 to fix this error. + */ + #error "Definition INCLUDE_xTaskGetSchedulerState must equal 1 to implement Kernel Information and Control API." +#endif +#if (INCLUDE_uxTaskGetStackHighWaterMark == 0) + /* + CMSIS-RTOS2 function osThreadGetStackSpace uses FreeRTOS function uxTaskGetStackHighWaterMark. + In case if osThreadGetStackSpace is not used in the application image, compiler will + optimize it away. + Set #define INCLUDE_uxTaskGetStackHighWaterMark 1 to fix this error. + */ + #error "Definition INCLUDE_uxTaskGetStackHighWaterMark must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_uxTaskPriorityGet == 0) + /* + CMSIS-RTOS2 function osThreadGetPriority uses FreeRTOS function uxTaskPriorityGet. In case if + osThreadGetPriority is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_uxTaskPriorityGet 1 to fix this error. + */ + #error "Definition INCLUDE_uxTaskPriorityGet must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_vTaskPrioritySet == 0) + /* + CMSIS-RTOS2 function osThreadSetPriority uses FreeRTOS function vTaskPrioritySet. In case if + osThreadSetPriority is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskPrioritySet 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskPrioritySet must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_eTaskGetState == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function vTaskDelayUntil to implement functions osThreadGetState + and osThreadTerminate. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define INCLUDE_eTaskGetState 1 to fix this error. + */ + #error "Definition INCLUDE_eTaskGetState must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_vTaskSuspend == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS functions vTaskSuspend and vTaskResume to implement + functions osThreadSuspend and osThreadResume. In case if these functions are not + used in the application image, compiler will optimize them away. + Set #define INCLUDE_vTaskSuspend 1 to fix this error. + + Alternatively, if the application does not use osThreadSuspend and + osThreadResume they can be excluded from the image code by setting: + #define configUSE_OS2_THREAD_SUSPEND_RESUME 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) + #error "Definition INCLUDE_vTaskSuspend must equal 1 to implement Kernel Information and Control API." + #endif +#endif +#if (INCLUDE_xTimerPendFunctionCall == 0) + /* + CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear, when called from + the ISR, call FreeRTOS functions xEventGroupSetBitsFromISR and + xEventGroupClearBitsFromISR which are only enabled if timers are operational and + xTimerPendFunctionCall in enabled. + Set #define INCLUDE_xTimerPendFunctionCall 1 and #define configUSE_TIMERS 1 + to fix this error. + + Alternatively, if the application does not use osEventFlagsSet and osEventFlagsClear + from the ISR their operation from ISR can be restricted by setting: + #define configUSE_OS2_EVENTFLAGS_FROM_ISR 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 1) + #error "Definition INCLUDE_xTimerPendFunctionCall must equal 1 to implement Event Flags API." + #endif +#endif + +#if (configUSE_TIMERS == 0) + /* + CMSIS-RTOS2 Timer Management API functions use FreeRTOS timer functions to implement + timer management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_TIMERS 1 to fix this error. + + Alternatively, if the application does not use timer functions they can be + excluded from the image code by setting: + #define configUSE_OS2_TIMER 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_TIMER == 1) + #error "Definition configUSE_TIMERS must equal 1 to implement Timer Management API." + #endif +#endif + +#if (configUSE_MUTEXES == 0) + /* + CMSIS-RTOS2 Mutex Management API functions use FreeRTOS mutex functions to implement + mutex management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_MUTEXES 1 to fix this error. + + Alternatively, if the application does not use mutex functions they can be + excluded from the image code by setting: + #define configUSE_OS2_MUTEX 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_MUTEX == 1) + #error "Definition configUSE_MUTEXES must equal 1 to implement Mutex Management API." + #endif +#endif + +#if (configUSE_COUNTING_SEMAPHORES == 0) + /* + CMSIS-RTOS2 Memory Pool functions use FreeRTOS function xSemaphoreCreateCounting + to implement memory pools. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_COUNTING_SEMAPHORES 1 to fix this error. + */ + #error "Definition configUSE_COUNTING_SEMAPHORES must equal 1 to implement Memory Pool API." +#endif +#if (configUSE_TASK_NOTIFICATIONS == 0) + /* + CMSIS-RTOS2 Thread Flags API functions use FreeRTOS Task Notification functions to implement + thread flag management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_TASK_NOTIFICATIONS 1 to fix this error. + + Alternatively, if the application does not use thread flags functions they can be + excluded from the image code by setting: + #define configUSE_OS2_THREAD_FLAGS 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_FLAGS == 1) + #error "Definition configUSE_TASK_NOTIFICATIONS must equal 1 to implement Thread Flags API." + #endif +#endif + +#if (configUSE_TRACE_FACILITY == 0) + /* + CMSIS-RTOS2 function osThreadEnumerate requires FreeRTOS function uxTaskGetSystemState + which is only enabled if configUSE_TRACE_FACILITY == 1. + Set #define configUSE_TRACE_FACILITY 1 to fix this error. + + Alternatively, if the application does not use osThreadEnumerate it can be + excluded from the image code by setting: + #define configUSE_OS2_THREAD_ENUMERATE 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_ENUMERATE == 1) + #error "Definition configUSE_TRACE_FACILITY must equal 1 to implement osThreadEnumerate." + #endif +#endif + +#if (configUSE_16_BIT_TICKS == 1) + /* + CMSIS-RTOS2 wrapper for FreeRTOS relies on 32-bit tick timer which is also optimal on + a 32-bit CPU architectures. + Set #define configUSE_16_BIT_TICKS 0 to fix this error. + */ + #error "Definition configUSE_16_BIT_TICKS must be zero to implement CMSIS-RTOS2 API." +#endif + +#if (configMAX_PRIORITIES != 56) + /* + CMSIS-RTOS2 defines 56 different priorities (see osPriority_t) and portable CMSIS-RTOS2 + implementation should implement the same number of priorities. + Set #define configMAX_PRIORITIES 56 to fix this error. + */ + #error "Definition configMAX_PRIORITIES must equal 56 to implement Thread Management API." +#endif +#if (configUSE_PORT_OPTIMISED_TASK_SELECTION != 0) + /* + CMSIS-RTOS2 requires handling of 56 different priorities (see osPriority_t) while FreeRTOS port + optimised selection for Cortex core only handles 32 different priorities. + Set #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 to fix this error. + */ + #error "Definition configUSE_PORT_OPTIMISED_TASK_SELECTION must be zero to implement Thread Management API." +#endif + +#endif /* FREERTOS_OS2_H_ */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/LICENSE b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE new file mode 100644 index 0000000..2ce4711 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE @@ -0,0 +1,18 @@ +Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c new file mode 100644 index 0000000..9ce5003 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c @@ -0,0 +1,353 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file is co-routines are not being used. */ +#if( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER + #define static +#endif + + +/* Lists for ready and blocked co-routines. --------------------*/ +static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ +static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ +static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ +static List_t * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ +static List_t * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ +static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ +CRCB_t * pxCurrentCoRoutine = NULL; +static UBaseType_t uxTopCoRoutineReadyPriority = 0; +static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; + +/* The initial state of the co-routine when it is created. */ +#define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ +#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ +{ \ + if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ +} + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ +static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ +static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ +static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ) +{ +BaseType_t xReturn; +CRCB_t *pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + This is so we can get back to the containing CRCB from a generic item + in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ) +{ +TickType_t xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckPendingReadyList( void ) +{ + /* Are there any co-routines waiting to get moved to the ready list? These + are co-routines that have been readied by an ISR. The ISR cannot access + the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t *pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckDelayedList( void ) +{ +CRCB_t *pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + section. If this is the case then the generic list item will + have been moved to the pending ready list and the following + line is still valid. Also the pvContainer parameter will have + been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pxContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineSchedule( void ) +{ + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + + return; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseCoRoutineLists( void ) +{ +UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; +} +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ) +{ +CRCB_t *pxUnblockedCRCB; +BaseType_t xReturn; + + /* This function is called from within an interrupt. It can only access + event lists and the pending ready list. This function assumes that a + check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} + +#endif /* configUSE_CO_ROUTINES == 0 */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c new file mode 100644 index 0000000..bf4ec24 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c @@ -0,0 +1,753 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining +all the API functions to use the MPU wrappers. That should only be done when +task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ + +/* The following bit fields convey control information in a task's event list +item value. It is important they don't clash with the +taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct EventGroupDef_t +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) + { + EventGroup_t *pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticEventGroup_t equals the size of the real + event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + this event group was created statically in case the event group + is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + /* xEventGroupCreateStatic should only ever be called with + pxEventGroupBuffer pointing to a pre-allocated (compile time + allocated) StaticEventGroup_t variable. */ + traceEVENT_GROUP_CREATE_FAILED(); + } + + return pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t *pxEventBits; + + /* Allocate the event group. Justification for MISRA deviation as + follows: pvPortMalloc() always ensures returned memory blocks are + aligned per the requirements of the MCU stack. In this case + pvPortMalloc() must return a pointer that is guaranteed to meet the + alignment requirements of the EventGroup_t structure - which (if you + follow it through) is the alignment requirements of the TickType_t type + (EventBits_t being of TickType_t itself). Therefore, whenever the + stack alignment requirements are greater than or equal to the + TickType_t alignment requirements the cast is safe. In other cases, + where the natural word size of the architecture is less than + sizeof( TickType_t ), the TickType_t variables will be accessed in two + or more reads operations, and the alignment requirements is only that + of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + event group was allocated statically in case the event group is + later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ + } + + return pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) +{ +EventBits_t uxOriginalBitValue, uxReturn; +EventGroup_t *pxEventBits = xEventGroup; +BaseType_t xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + the task unblocks, but some compilers mistakenly generate a + warning about uxReturn being returned without being set if the + assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + bits it was waiting for were set, it is possible that since it + unblocked another task has set the bits. If this is the case + then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) +{ +EventGroup_t *pxEventBits = xEventGroup; +EventBits_t uxReturn, uxControlBits = 0; +BaseType_t xWaitConditionMet, xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + set. uxControlBits are used to remember the specified behaviour of + this call to xEventGroupWaitBits() - for use when the event bits + unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + some compilers mistakenly generate a warning about the variable + being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) +{ +EventGroup_t *pxEventBits = xEventGroup; +EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ +UBaseType_t uxSavedInterruptStatus; +EventGroup_t const * const pxEventBits = xEventGroup; +EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) +{ +ListItem_t *pxListItem, *pxNext; +ListItem_t const *pxListEnd; +List_t const * pxList; +EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; +EventGroup_t *pxEventBits = xEventGroup; +BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + item before removing the task from the event list. The + eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + that is was unblocked due to its required bits matching, rather + than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + used here as the list item may have been removed from the event list + and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ +EventGroup_t *pxEventBits = xEventGroup; +const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + it again. */ + vPortFree( pxEventBits ); + } + #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + ( void ) xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from +an interrupt. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from +an interrupt. */ +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) +{ +BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h new file mode 100644 index 0000000..ceb469a --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h @@ -0,0 +1,1295 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifndef INCLUDE_vTaskDelayUntil + #define INCLUDE_vTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* configPRECONDITION should be defined as configASSERT. +The CBMC proofs need a way to track assumptions and assertions. +A configPRECONDITION statement should express an implicit invariant or +assumption made. A configASSERT statement should express an invariant that must +hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT(X) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + /* Used to perform any necessary initialisation - for example, open a file + into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + /* Use to close a trace, for example close a file into which trace has been + written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + /* Called after a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + /* Called before stepping the tick count after waking from tickless idle + sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + /* Called before a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + /* Called when a task attempts to take a mutex that is already held by a + lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + that holds the mutex. uxInheritedPriority is the priority the mutex holder + will inherit (the priority of the task that is attempting to obtain the + muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + /* Called when a task releases a mutex, the holding of which had resulted in + the task inheriting the priority of a higher priority task. + pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + /* Task is about to block because it cannot write to a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the write was attempted. pxCurrentTCB points to the TCB of the + task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE() +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT() +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY() +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR() +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR() +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + /* Defaults to uint16_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + /* Defaults to size_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if lengths will always be less than the number of bytes + in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if( configUSE_TICKLESS_IDLE != 0 ) + #if( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if( portTICK_TYPE_IS_ATOMIC == 0 ) + /* Either variables of tick type cannot be read atomically, or + portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + /* The tick type can be read atomically, so critical sections used when the + tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to +V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + /* configPRINTF() was not defined, so define it away to nothing. To use + configPRINTF() then define it as follows (where MyPrintFunction() is + provided by the application writer): + + void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + + Then call like a standard printf() function, but placing brackets around + all parameters so they are passed as a single parameter. For example: + configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + + /* Backward compatibility within the scheduler code only - these definitions + are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + + /* For libraries that break the list data hiding, and access list structure + members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even +if floating point hardware is otherwise supported by the FreeRTOS port in use. +This constant is not supported by all FreeRTOS ports that include floating +point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. +This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on +the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be know. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 4 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void *pvDummy3; + StaticMiniListItem_t xDummy4; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be know. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void *pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void *pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void *pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void *pxDummy14; + #endif + #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void *pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18; + uint8_t ucDummy19; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be know. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void *pvDummy1[ 3 ]; + + union + { + void *pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void *pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif + +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif + +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be know. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void *pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void *pvDummy5; + TaskFunction_t pvDummy6; + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; + +} StaticTimer_t; + +/* +* In line with software engineering best practice, especially when supplying a +* library that is likely to change in future versions, FreeRTOS implements a +* strict data hiding policy. This means the stream buffer structure used +* internally by FreeRTOS is not accessible to application code. However, if +* the application writer wants to statically allocate the memory required to +* create a stream buffer then the size of the stream buffer object needs to be +* know. The StaticStreamBuffer_t structure below is provided for this purpose. +* Its size and alignment requirements are guaranteed to match those of the +* genuine structure, no matter which architecture is being used, and no matter +* how the values in FreeRTOSConfig.h are set. Its contents are somewhat +* obfuscated in the hope users will recognise that it would be unwise to make +* direct use of the structure members. +*/ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +#ifdef __cplusplus +} +#endif + +#endif /* INC_FREERTOS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h new file mode 100644 index 0000000..5643991 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. +#endif + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h b/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h new file mode 100644 index 0000000..ceca696 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h @@ -0,0 +1,414 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/** + * @file atomic.h + * @brief FreeRTOS atomic operation support. + * + * This file implements atomic functions by disabling interrupts globally. + * Implementations with architecture specific atomic instructions can be + * provided under each compiler directory. + */ + +#ifndef ATOMIC_H +#define ATOMIC_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include atomic.h" +#endif + +/* Standard includes. */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Port specific definitions -- entering/exiting critical section. + * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h + * + * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with + * ATOMIC_ENTER_CRITICAL(). + * + */ +#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) + + /* Nested interrupt scheme is supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() \ + UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() + + #define ATOMIC_EXIT_CRITICAL() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) + +#else + + /* Nested interrupt scheme is NOT supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() + #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() + +#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ + +/* + * Port specific definition -- "always inline". + * Inline is compiler specific, and may not always get inlined depending on your + * optimization level. Also, inline is considered as performance optimization + * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h, + * instead of resulting error, simply define it away. + */ +#ifndef portFORCE_INLINE + #define portFORCE_INLINE +#endif + +#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ +#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ + +/*----------------------------- Swap && CAS ------------------------------*/ + +/** + * Atomic compare-and-swap + * + * @brief Performs an atomic compare-and-swap operation on the specified values. + * + * @param[in, out] pulDestination Pointer to memory location from where value is + * to be loaded and checked. + * @param[in] ulExchange If condition meets, write this value to memory. + * @param[in] ulComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *pulDestination with ulExchange, if previous + * *pulDestination value equals ulComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination, + uint32_t ulExchange, + uint32_t ulComparand ) +{ +uint32_t ulReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + if( *pulDestination == ulComparand ) + { + *pulDestination = ulExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + else + { + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic swap (pointers) + * + * @brief Atomically sets the address pointed to by *ppvDestination to the value + * of *pvExchange. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and written back to. + * @param[in] pvExchange Pointer value to be written to *ppvDestination. + * + * @return The initial value of *ppvDestination. + */ +static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange ) +{ +void * pReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + pReturnValue = *ppvDestination; + *ppvDestination = pvExchange; + } + ATOMIC_EXIT_CRITICAL(); + + return pReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic compare-and-swap (pointers) + * + * @brief Performs an atomic compare-and-swap operation on the specified pointer + * values. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and checked. + * @param[in] pvExchange If condition meets, write this value to memory. + * @param[in] pvComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *ppvDestination with pvExchange, if previous + * *ppvDestination value equals pvComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange, + void * pvComparand ) +{ +uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + + ATOMIC_ENTER_CRITICAL(); + { + if( *ppvDestination == pvComparand ) + { + *ppvDestination = pvExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} + + +/*----------------------------- Arithmetic ------------------------------*/ + +/** + * Atomic add + * + * @brief Atomically adds count to the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be added to *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic subtract + * + * @brief Atomically subtracts count from the value of the specified pointer + * pointers to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be subtract from *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic increment + * + * @brief Atomically increments the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before increment. + */ +static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic decrement + * + * @brief Atomically decrements the value of the specified pointer points to + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before decrement. + */ +static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/*----------------------------- Bitwise Logical ------------------------------*/ + +/** + * Atomic OR + * + * @brief Performs an atomic OR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination |= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic AND + * + * @brief Performs an atomic AND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination &= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic NAND + * + * @brief Performs an atomic NAND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be NANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination = ~( ulCurrent & ulValue ); + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic XOR + * + * @brief Performs an atomic XOR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be XORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination ^= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +#ifdef __cplusplus +} +#endif + +#endif /* ATOMIC_H */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h new file mode 100644 index 0000000..8d7069c --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h @@ -0,0 +1,720 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Used to hide the implementation of the co-routine control block. The +control block structure however has to be included in the header due to +the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + *
    + BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );
    + * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+
    + * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ); + + +/** + * croutine. h + *
    + void vCoRoutineSchedule( void );
    + * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + 
    + // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineSchedule() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+
    + * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * 
    + crSTART( CoRoutineHandle_t xHandle );
    + * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
    + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0: + +/** + * croutine. h + * 
    + crEND();
    + * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
    + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): +#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): + +/** + * croutine. h + *
    + crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
    + * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
    + * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * 
    + crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )
    + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + 
    + // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }
    + * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
    +  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )
    + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + 
    + // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }
    + * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
    +  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )
    + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + 
    + // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }
    + * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * 
    +  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )
    + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + 
    + // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }
    + * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ); + +#ifdef __cplusplus +} +#endif + +#endif /* CO_ROUTINE_H */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h new file mode 100644 index 0000000..21657b9 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h @@ -0,0 +1,279 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a +pre-processor definition was used to ensure the pre-processor found the correct +portmacro.h file for the port being used. That scheme was deprecated in favour +of setting the compiler's include path such that it found the correct +portmacro.h file - removing the need for the constant and allowing the +portmacro.h file to be located anywhere in relation to the port being used. The +definitions below remain in the code for backward compatibility only. New +projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h new file mode 100644 index 0000000..a87fdf3 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h @@ -0,0 +1,757 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + *
    + EventGroupHandle_t xEventGroupCreate( void );
+
    + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See http://www.freertos.org/a00111.html + * + * Example usage: + 
    +	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+
    + * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
    + EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+
    + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + 
    +	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+
    + */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+
    + * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + 
    +   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+
    + * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+
    + * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + 
    +   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+
    + * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
    +	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
    + * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
    +   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+
    + * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
    + * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + 
    +   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+
    + * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
    +	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+
    + * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
    +   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+
    + * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+
    + * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + 
    + // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+
    + * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+
    + * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+
    + * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
    +	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+
    + * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if (configUSE_TRACE_FACILITY == 1) + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* EVENT_GROUPS_H */ + + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h new file mode 100644 index 0000000..a3e3024 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h @@ -0,0 +1,412 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + +#ifndef INC_FREERTOS_H + #error FreeRTOS.h must be included before list.h +#endif + +#ifndef LIST_H +#define LIST_H + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macros that can be used to place known values within the list structures, +then check that the known values do not get corrupted during the execution of +the application. These may catch the list data structures being overwritten in +memory. They will not catch data errors caused by incorrect configuration or +use of FreeRTOS.*/ +#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + + /* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + + /* Define macros that will assert if one of the structure members does not + contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the next list item. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ +{ \ +List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ +} + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h new file mode 100644 index 0000000..0c3edb9 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h @@ -0,0 +1,803 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include message_buffer.h" +#endif + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +#if defined( __cplusplus ) +extern "C" { +#endif + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * +
    +MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+
    + * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: +
    +
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+
    + * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * +
    +MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+
    + * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: +
    +
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+
    + * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * +
    +size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+
    + *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+
    +void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+
    
+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+
    +size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+
    + *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+
    +// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+
    
+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
    +size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+
    
+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+
    +void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+
    
+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+
    +size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+
    +// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+
    
+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
    +void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+
    
+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
    +BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+
    
+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
    +BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+
    
+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
    +BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+
    
+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+
    +size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+
    
+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ 
    + size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ 
    
+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+
    +BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
    +BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
new file mode 100644
index 0000000..a21b7a6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
@@ -0,0 +1,160 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 0000000..5f63d4f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,189 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define ulTaskGetIdleRunTimeCounter				MPU_ulTaskGetIdleRunTimeCounter
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+		#define ulTaskNotifyValueClear					MPU_ulTaskNotifyValueClear
+		#define xTaskCatchUpTicks						MPU_xTaskCatchUpTicks
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
+		#define uxTimerGetReloadMode					MPU_uxTimerGetReloadMode
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
+		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define FREERTOS_SYSTEM_CALL
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
new file mode 100644
index 0000000..a2099c3
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,199 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+	#define portHAS_STACK_OVERFLOW_CHECKING 0
+#endif
+
+#ifndef portARCH_NAME
+	#define portARCH_NAME NULL
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#endif
+#else
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#endif
+#endif
+
+/* Used by heap_5.c to define the start address and size of each memory region
+that together comprise the total FreeRTOS heap space. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/* Used to pass information about the heap out of vPortGetHeapStats(). */
+typedef struct xHeapStats
+{
+	size_t xAvailableHeapSpaceInBytes;		/* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
+	size_t xSizeOfLargestFreeBlockInBytes; 	/* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xNumberOfFreeBlocks;				/* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xMinimumEverFreeBytesRemaining;	/* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
+	size_t xNumberOfSuccessfulAllocations;	/* The number of calls to pvPortMalloc() that have returned a valid memory block. */
+	size_t xNumberOfSuccessfulFrees;		/* The number of calls to vPortFree() that has successfully freed a block of memory. */
+} HeapStats_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns a HeapStats_t structure filled with information about the current
+ * heap state.
+ */
+void vPortGetHeapStats( HeapStats_t *pxHeapStats );
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 0000000..0d95130
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
new file mode 100644
index 0000000..52ccca5
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1655 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * 
    + QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * 
    
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * 
    + QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * 
    
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 
    
+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 
    
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * 
    
+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * 
    
+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   
    +
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ 
    
+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * 
    
+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );
    
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);
    
+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);
    
+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
    
+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
    
+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    void vQueueDelete( QueueHandle_t xQueue );
    
+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 
    
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
    + void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 
    
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 
    
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
    + void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 
    
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * 
    
+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   
    +
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ 
    
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ 
    
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
    + void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ 
    
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ 
    
+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
    + void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		portYIELD_FROM_ISR();
+	}
+ }
+ 
    
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * 
    
+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
    +
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ 
    
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 0000000..787c791
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,1140 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * 
    vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )
    
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * Macro that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 
    
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateBinary( void )
    
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )
    
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ 
    
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
    xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )
    
+ *
+ * Macro to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * Macro to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * 
    xSemaphoreGive( SemaphoreHandle_t xSemaphore )
    
+ *
+ * Macro to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * 
    xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )
    
+ *
+ * Macro to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * 
    + xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )
    
+ *
+ * Macro to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ 
    + \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
    + xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )
    
+ *
+ * Macro to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateMutex( void )
    
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )
    
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 
    
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )
    
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )
    
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 
    
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )
    
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )
    
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ 
    
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
    void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
    
+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
    TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
    
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
    TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );
    
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
    UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );
    
+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
new file mode 100644
index 0000000..b5bac08
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
+			( pulStack[ 1 ] != ulCheckValue ) ||														\
+			( pulStack[ 2 ] != ulCheckValue ) ||														\
+			( pulStack[ 3 ] != ulCheckValue ) )															\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
new file mode 100644
index 0000000..a8b68ad
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
@@ -0,0 +1,859 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
+#endif
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+
    +StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+
    
+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+
    +
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+
    
+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+
    +StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+
    
+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+
    +
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+
    
+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+
    
+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+
    +void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+
    
+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+
    +// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+
    
+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+
    
+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+
    +void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+
    
+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+
    +// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+
    
+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+
    
+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
new file mode 100644
index 0000000..b0cc60b
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
@@ -0,0 +1,2543 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.3.1"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 3
+#define tskKERNEL_VERSION_BUILD 1
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY			( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE		( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER		( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY		( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY		( 1UL << 4UL )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid		/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	configSTACK_DEPTH_TYPE usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *
    + BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  configSTACK_DEPTH_TYPE usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );
    
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
    + // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+	 configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+	 if( xHandle != NULL )
+	 {
+	 	vTaskDelete( xHandle );
+	 }
+ }
+   
    
+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
    + TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );
    
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and a handle to the created task is returned.  If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+   
    +
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   
    
+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *
    + BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
    
+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
    +// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   
    
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
    + BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
    
+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
    +// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   
    
+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
    + void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
    
+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   
    +// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   
    
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskDelete( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   
    + void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   
    
+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
    void vTaskDelay( const TickType_t xTicksToDelay );
    
+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );
    
+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   
    + // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   
    
+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskAbortDelay( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * There is no 'FromISR' version of this function as an interrupt would need to
+ * know which object a task was blocked on in order to know which actions to
+ * take.  For example, if the task was blocked on a queue the interrupt handler
+ * would then need to know if the queue was locked.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );
    
+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   
    
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );
    
+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    eTaskState eTaskGetState( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
    
+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   
    
+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
    
+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   
    
+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskSuspend( TaskHandle_t xTaskToSuspend );
    
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   
    
+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskResume( TaskHandle_t xTaskToResume );
    
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   
    
+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void xTaskResumeFromISR( TaskHandle_t xTaskToResume );
    
+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
    void vTaskStartScheduler( void );
    
+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   
    
+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskEndScheduler( void );
    
+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   
    + void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   
    
+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskSuspendAll( void );
    
+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   
    + void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   
    
+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskResumeAll( void );
    
+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   
    + void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   
    
+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
    TickType_t xTaskGetTickCount( void );
    
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    TickType_t xTaskGetTickCountFromISR( void );
    
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    uint16_t uxTaskGetNumberOfTasks( void );
    
+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    char *pcTaskGetName( TaskHandle_t xTaskToQuery );
    
+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
    TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );
    
+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * 
    UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * 
    void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
    
+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
    void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
    
+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
+		 * call from an interrupt service routine - call
+		 * xTaskGetApplicationTaskTagFromISR() instead.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
    void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );
    
+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Can
+		 * be called from an interrupt service routine.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * 
    BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
    
+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   
    +    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	
    
+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskList( char *pcWriteBuffer );
    
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
    void vTaskGetRunTimeStats( char *pcWriteBuffer );
    
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+* task. h
+* 
    uint32_t ulTaskGetIdleRunTimeCounter( void );
    
+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available.  The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively.  The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task.  The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task.  This is the amount of time the
+* idle task has actually been executing.  The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
    
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
    
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
    
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );
    
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * 
    void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
    
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
    
+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/**
+* task. h
+* 
    uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );
    
+*
+* Clears the bits specified by the ulBitsToClear bit mask in the notification
+* value of the task referenced by xTask.
+*
+* Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear
+* the notification value to 0.  Set ulBitsToClear to 0 to query the task's
+* notification value without clearing any bits.
+*
+* @return The value of the target task's notification value before the bits
+* specified by ulBitsToClear were cleared.
+* \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear
+* \ingroup TaskNotifications
+*/
+uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
    void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
    
+ *
+ * Capture the current time for future use with xTaskCheckForTimeOut().
+ *
+ * @param pxTimeOut Pointer to a timeout object into which the current time
+ * is to be captured.  The captured time includes the tick count and the number
+ * of times the tick count has overflowed since the system first booted.
+ * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState
+ * \ingroup TaskCtrl
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
    BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
    
+ *
+ * Determines if pxTicksToWait ticks has passed since a time was captured
+ * using a call to vTaskSetTimeOutState().  The captured time includes the tick
+ * count and the number of times the tick count has overflowed.
+ *
+ * @param pxTimeOut The time status as captured previously using
+ * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated
+ * to reflect the current time status.
+ * @param pxTicksToWait The number of ticks to check for timeout i.e. if
+ * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by
+ * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.
+ * If the timeout has not occurred, pxTIcksToWait is updated to reflect the
+ * number of remaining ticks.
+ *
+ * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is
+ * returned and pxTicksToWait is updated to reflect the number of remaining
+ * ticks.
+ *
+ * @see https://www.freertos.org/xTaskCheckForTimeOut.html
+ *
+ * Example Usage:
+ * 
    +	// Driver library function used to receive uxWantedBytes from an Rx buffer
+	// that is filled by a UART interrupt. If there are not enough bytes in the
+	// Rx buffer then the task enters the Blocked state until it is notified that
+	// more data has been placed into the buffer. If there is still not enough
+	// data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+	// is used to re-calculate the Block time to ensure the total amount of time
+	// spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+	// continues until either the buffer contains at least uxWantedBytes bytes,
+	// or the total amount of time spent in the Blocked state reaches
+	// MAX_TIME_TO_WAIT – at which point the task reads however many bytes are
+	// available up to a maximum of uxWantedBytes.
+
+	size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+	{
+	size_t uxReceived = 0;
+	TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+	TimeOut_t xTimeOut;
+
+		// Initialize xTimeOut.  This records the time at which this function
+		// was entered.
+		vTaskSetTimeOutState( &xTimeOut );
+
+		// Loop until the buffer contains the wanted number of bytes, or a
+		// timeout occurs.
+		while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+		{
+			// The buffer didn't contain enough data so this task is going to
+			// enter the Blocked state. Adjusting xTicksToWait to account for
+			// any time that has been spent in the Blocked state within this
+			// function so far to ensure the total amount of time spent in the
+			// Blocked state does not exceed MAX_TIME_TO_WAIT.
+			if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+			{
+				//Timed out before the wanted number of bytes were available,
+				// exit the loop.
+				break;
+			}
+
+			// Wait for a maximum of xTicksToWait ticks to be notified that the
+			// receive interrupt has placed more data into the buffer.
+			ulTaskNotifyTake( pdTRUE, xTicksToWait );
+		}
+
+		// Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+		// The actual number of bytes read (which might be less than
+		// uxWantedBytes) is returned.
+		uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+													pucBuffer,
+													uxWantedBytes );
+
+		return uxReceived;
+	}
+ 
    
+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/* Correct the tick count value after the application code has held
+interrupts disabled for an extended period.  xTicksToCatchUp is the number
+of tick interrupts that have been missed due to interrupts being disabled.
+Its value is not computed automatically, so must be computed by the
+application writer.
+
+This function is similar to vTaskStepTick(), however, unlike
+vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a
+time at which a task should be removed from the blocked state.  That means
+tasks may have to be removed from the blocked state as the tick count is
+moved. */
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
new file mode 100644
index 0000000..307ea1f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1309 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  Time timer period must be greater than 0.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created because there is
+ * insufficient FreeRTOS heap remaining to allocate the timer
+ * structures then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  The timer period must be greater than 0.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+* UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
+*
+* Queries a timer to determine if it is an auto-reload timer, in which case the timer
+* automatically resets itself each time it expires, or a one-shot timer, in
+* which case the timer will only expire once unless it is manually restarted.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
+* pdFALSE is returned.
+*/
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/list.c b/Middlewares/Third_Party/FreeRTOS/Source/list.c
new file mode 100644
index 0000000..7618ee8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include 
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pxContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCBs which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		https://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   https://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pxContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 0000000..eaf443f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,492 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of calls to allocate and free memory as well as the
+number of free bytes remaining, but says nothing about fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+static size_t xNumberOfSuccessfulAllocations = 0;
+static size_t xNumberOfSuccessfulFrees = 0;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+					xNumberOfSuccessfulAllocations++;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+					xNumberOfSuccessfulFrees++;
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortGetHeapStats( HeapStats_t *pxHeapStats )
+{
+BlockLink_t *pxBlock;
+size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+
+	vTaskSuspendAll();
+	{
+		pxBlock = xStart.pxNextFreeBlock;
+
+		/* pxBlock will be NULL if the heap has not been initialised.  The heap
+		is initialised automatically when the first allocation is made. */
+		if( pxBlock != NULL )
+		{
+			do
+			{
+				/* Increment the number of blocks and record the largest block seen
+				so far. */
+				xBlocks++;
+
+				if( pxBlock->xBlockSize > xMaxSize )
+				{
+					xMaxSize = pxBlock->xBlockSize;
+				}
+
+				if( pxBlock->xBlockSize < xMinSize )
+				{
+					xMinSize = pxBlock->xBlockSize;
+				}
+
+				/* Move to the next block in the chain until the last block is
+				reached. */
+				pxBlock = pxBlock->pxNextFreeBlock;
+			} while( pxBlock != pxEnd );
+		}
+	}
+	xTaskResumeAll();
+
+	pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
+	pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
+	pxHeapStats->xNumberOfFreeBlocks = xBlocks;
+
+	taskENTER_CRITICAL();
+	{
+		pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
+		pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
+		pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
+		pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
+	}
+	taskEXIT_CRITICAL();
+}
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
new file mode 100644
index 0000000..6cd7542
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
@@ -0,0 +1,788 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __TARGET_FPU_VFP
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Legacy macro for backward compatibility only.  This macro used to be used to
+replace the function that configures the clock used to generate the tick
+interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
+the application writer can override it by simply defining a function of the
+same name (vApplicationSetupTickInterrupt()). */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+	#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+r0p1 port. */
+#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR					( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS	( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR			( 0x01000000 )
+#define portINITIAL_EXC_RETURN		( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER		( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR	( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Functions defined in portasm.s to enable the VFP.
+ */
+static void prvEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSVCHandler( void )
+{
+	PRESERVE8
+
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvStartFirstTask( void )
+{
+	PRESERVE8
+
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Globally enable interrupts. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	/* Call SVC to start the first task. */
+	svc 0
+	nop
+	nop
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvEnableVFP( void )
+{
+	PRESERVE8
+
+	/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+	nop
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	/* This port can be used on all revisions of the Cortex-M7 core other than
+	the r0p1 parts.  r0p1 parts should use the port from the
+	/source/portable/GCC/ARM_CM7/r0p1 directory. */
+	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* The kernel interrupt priority should be set to the lowest
+		priority. */
+		configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	prvEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+	extern uxCriticalNesting;
+	extern pxCurrentTCB;
+	extern vTaskSwitchContext;
+
+	PRESERVE8
+
+	mrs r0, psp
+	isb
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	/* Save the core registers. */
+	stmdb r0!, {r4-r11, r14}
+
+	/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+
+	/* Is the task using the FPU context?  If so, pop the high vfp registers
+	too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
+		#if WORKAROUND_PMU_CM001 == 1
+			push { r14 }
+			pop { pc }
+			nop
+		#endif
+	#endif
+
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known - therefore the slightly faster vPortRaiseBASEPRI() function is used
+	in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
+	vPortRaiseBASEPRI();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	vPortClearBASEPRIFromISR();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__disable_irq();
+		__dsb( portSY_FULL_READ_WRITE );
+		__isb( portSY_FULL_READ_WRITE );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above __disable_irq() call
+			above. */
+			__enable_irq();
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__dsb( portSY_FULL_READ_WRITE );
+				__wfi();
+				__isb( portSY_FULL_READ_WRITE );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__enable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__disable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrupts enabled. */
+			__enable_irq();
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the SysTick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+	__weak void vPortSetupTimerInterrupt( void )
+	{
+		/* Calculate the constants required to configure the tick interrupt. */
+		#if( configUSE_TICKLESS_IDLE == 1 )
+		{
+			ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+			xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+			ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+
+		/* Stop and clear the SysTick. */
+		portNVIC_SYSTICK_CTRL_REG = 0UL;
+		portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+		/* Configure SysTick to interrupt at the requested rate. */
+		portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+		portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+	}
+
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+__asm uint32_t vPortGetIPSR( void )
+{
+	PRESERVE8
+
+	mrs r0, ipsr
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		ulCurrentInterrupt = vPortGetIPSR();
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..2b07ff1
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
@@ -0,0 +1,252 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/* Constants used with memory barrier intrinsics. */
+#define portSY_FULL_READ_WRITE		( 15 )
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()																\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__dsb( portSY_FULL_READ_WRITE );											\
+	__isb( portSY_FULL_READ_WRITE );											\
+}
+/*-----------------------------------------------------------*/
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Port specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE __forceinline
+#endif
+
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+	__asm
+	{
+		/* Barrier instructions are not used as this function is only used to
+		lower the BASEPRI value. */
+		msr basepri, ulBASEPRI
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+	__asm
+	{
+		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+		used to lower the mask in an interrupt, so memory barriers are not 
+		used. */
+		msr basepri, #0
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		mrs ulReturn, basepri
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+	}
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm
+	{
+		mrs ulCurrentInterrupt, ipsr
+	}
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
new file mode 100644
index 0000000..b3203b8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
@@ -0,0 +1,2945 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+structure instead holds a pointer to the mutex holder (if any).  Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+typedef struct QueuePointers
+{
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
+	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union
+	{
+		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
+		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* Allocate enough space to hold the maximum number of items that
+		can be in the queue at any time.  It is valid for uxItemSize to be
+		zero in the case the queue is used as a semaphore. */
+		xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+		/* Allocate the queue and storage area.  Justification for MISRA
+		deviation as follows:  pvPortMalloc() always ensures returned memory
+		blocks are aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then xMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+				const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					
+					/* Not used in this path. */
+					( void ) uxPreviousMessagesWaiting;
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	uxReturn = pxQueue->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+		{
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+				{
+					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+			{
+				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
new file mode 100644
index 0000000..7ad5d54
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
@@ -0,0 +1,1263 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+	uint8_t ucFlags;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		if( xIsMessageBuffer == pdTRUE )
+		{
+			/* Is a message buffer but not statically allocated. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		}
+		else
+		{
+			/* Not a message buffer and not statically allocated. */
+			ucFlags = 0;
+			configASSERT( xBufferSizeBytes > 0 );
+		}
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   ucFlags );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+	uint8_t ucFlags;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		if( xIsMessageBuffer != pdFALSE )
+		{
+			/* Statically allocated message buffer. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+		else
+		{
+			/* Statically allocated stream buffer. */
+			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  ucFlags );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	taskENTER_CRITICAL();
+	{
+		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+		{
+			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+			{
+				prvInitialiseNewStreamBuffer( pxStreamBuffer,
+											  pxStreamBuffer->pucBuffer,
+											  pxStreamBuffer->xLength,
+											  pxStreamBuffer->xTriggerLevelBytes,
+											  pxStreamBuffer->ucFlags );
+				xReturn = pdPASS;
+
+				#if( configUSE_TRACE_FACILITY == 1 )
+				{
+					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				}
+				#endif
+
+				traceSTREAM_BUFFER_RESET( xStreamBuffer );
+			}
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1;
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+		/* Overflow? */
+		configASSERT( xRequiredSpace > xDataLengthBytes );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* Ensure the stream buffer is being used as a message buffer. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+		{
+			/* The number of bytes available is greater than the number of bytes
+			required to hold the length of the next message, so another message
+			is available.  Return its length without removing the length bytes
+			from the buffer.  A copy of the tail is stored so the buffer can be
+			returned to its prior state as the message is not actually being
+			removed from the buffer. */
+			xOriginalTail = pxStreamBuffer->xTail;
+			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+			xReturn = ( size_t ) xTempReturn;
+			pxStreamBuffer->xTail = xOriginalTail;
+		}
+		else
+		{
+			/* The minimum amount of bytes in a message buffer is
+			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+			value is 0. */
+			configASSERT( xBytesAvailable == 0 );
+			xReturn = 0;
+		}
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+	#endif
+
+	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+	pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return xStreamBuffer->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
new file mode 100644
index 0000000..f6a6a9b
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
@@ -0,0 +1,5310 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include 
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Bits used to recored how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR		( 'X' )
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks.
+
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments in FreeRTOS.h with the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;				/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+	PRIVILEGED_DATA static List_t xTasksWaitingTermination;				/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList;					/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+	int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile TickType_t xPendedTicks 			= ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	/* Do not move these variables to function scope as doing so prevents the
+	code working with debuggers that need to remove the static qualifier. */
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+
+	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	if( pcName != NULL )
+	{
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+		{
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+			{
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+	}
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready/delayed list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* Call the delete hook before portPRE_TASK_DELETE_HOOK() as
+				portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
+				traceTASK_DELETE( pxTCB );
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				traceTASK_DELETE( pxTCB );
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+	const TCB_t * const pxTCB = xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxDelayedList = pxDelayedTaskList;
+				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it blocked
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						#if( configUSE_TASK_NOTIFICATIONS == 1 )
+						{
+							/* The task does not appear on the event list item of
+							and of the RTOS objects, but could still be in the
+							blocked state if it is waiting on its notification
+							rather than waiting on an object. */
+							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+							{
+								eReturn = eBlocked;
+							}
+							else
+							{
+								eReturn = eSuspended;
+							}
+						}
+						#else
+						{
+							eReturn = eSuspended;
+						}
+						#endif
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the task
+			that called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change its priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												configIDLE_TASK_NAME,
+												ulIdleTaskStackSize,
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		traceTASK_SWITCHED_IN();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+
+	/* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
+	do not otherwise exhibit real time behaviour. */
+	portSOFTWARE_BARRIER();
+
+	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
+	is used to allow calls to vTaskSuspendAll() to nest. */
+	++uxSchedulerSuspended;
+
+	/* Enforces ordering for ports and optimised compilers that may otherwise place
+	the above increment elsewhere. */
+	portMEMORY_BARRIER();
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+
+					if( xPendedCounts > ( TickType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--xPendedCounts;
+						} while( xPendedCounts > ( TickType_t ) 0U );
+
+						xPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+	BaseType_t xBreakLoop;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				xBreakLoop = pdFALSE;
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						xBreakLoop = pdTRUE;
+					}
+					else if( cNextChar == ( char ) 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						xBreakLoop = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					if( xBreakLoop != pdFALSE )
+					{
+						break;
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
+{
+BaseType_t xYieldRequired = pdFALSE;
+
+	/* Must not be called with the scheduler suspended as the implementation
+	relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
+	configASSERT( uxSchedulerSuspended == 0 );
+
+	/* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
+	the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
+	vTaskSuspendAll();
+	xPendedTicks += xTicksToCatchUp;
+	xYieldRequired = xTaskResumeAll();
+
+	return xYieldRequired;
+}
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = xTask;
+	BaseType_t xReturn;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				xReturn = pdPASS;
+
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+
+						/* This lets the task know it was forcibly removed from the
+						blocked state so it should not re-evaluate its block time and
+						then block again. */
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( xPendedTicks == ( TickType_t ) 0 )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+
+		#if ( configUSE_PREEMPTION == 1 )
+		{
+			if( xYieldPending != pdFALSE )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_PREEMPTION */
+	}
+	else
+	{
+		++xPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xTCB->pxTaskTag = pxHookFunction;
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+	UBaseType_t uxSavedInterruptStatus;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+			#else
+				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+			#endif
+
+			/* Add the amount of time the task has been running to the
+			accumulated time so far.  The time the task started running was
+			stored in ulTaskSwitchedInTime.  Note that there is no overflow
+			protection here so count values are only valid until the timer
+			overflows.  The guard against negative values is to protect
+			against suspect run time stat counter implementations - which
+			are provided by the application, not the kernel. */
+			if( ulTotalRunTime > ulTaskSwitchedInTime )
+			{
+				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Before the currently running task is switched out, save its errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+		}
+		#endif
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		traceTASK_SWITCHED_IN();
+
+		/* After the new task is switched in, update the global errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+		}
+		#endif
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+
+		#if( configUSE_TICKLESS_IDLE != 0 )
+		{
+			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+			might be set to the blocked task's time out time.  If the task is
+			unblocked for a reason other than a timeout xNextTaskUnblockTime is
+			normally left unchanged, because it is automatically reset to a new
+			value when the tick count equals xNextTaskUnblockTime.  However if
+			tickless idling is used it might be more important to enter sleep mode
+			at the earliest possible time - so reset xNextTaskUnblockTime here to
+			ensure it is updated at the earliest possible time. */
+			prvResetNextTaskUnblockTime();
+		}
+		#endif
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	#if( configUSE_TICKLESS_IDLE != 0 )
+	{
+		/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+		might be set to the blocked task's time out time.  If the task is
+		unblocked for a reason other than a timeout xNextTaskUnblockTime is
+		normally left unchanged, because it is automatically reset to a new
+		value when the tick count equals xNextTaskUnblockTime.  However if
+		tickless idling is used it might be more important to enter sleep mode
+		at the earliest possible time - so reset xNextTaskUnblockTime here to
+		ensure it is updated at the earliest possible time. */
+		prvResetNextTaskUnblockTime();
+	}
+	#endif
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
+		xYieldPending = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t const *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t * pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		/* This function must be called from a critical section. */
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			configASSERT( pxTCB != NULL );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			taskENTER_CRITICAL();
+			{
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
+			}
+			taskEXIT_CRITICAL();
+
+			prvDeleteTCB( pxTCB );
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+	user to determine the return type.  It gets around the problem of the value
+	overflowing on 8-bit types without breaking backward compatibility for
+	applications that expect an 8-bit return type. */
+	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	configSTACK_DEPTH_TYPE uxReturn;
+
+		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+		the same except for their return type.  Using configSTACK_DEPTH_TYPE
+		allows the user to determine the return type.  It gets around the
+		problem of the value overflowing on 8-bit types without breaking
+		backward compatibility for applications that expect an 8-bit return
+		type. */
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready/delayed list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							/* It is known that the task is in its ready list so
+							there is no need to check again and the port level
+							reset macro can be called directly. */
+							portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = ( char ) 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					case eInvalid:		/* Fall through. */
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = ( char ) 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0UL )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter to an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter in an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear )
+	{
+	TCB_t *pxTCB;
+	uint32_t ulReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			/* Return the notification as it was before the bits were cleared,
+			then clear the bit mask. */
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+			pxTCB->ulNotifiedValue &= ~ulBitsToClear;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+	uint32_t ulTaskGetIdleRunTimeCounter( void )
+	{
+		return xIdleTaskHandle->ulRunTimeCounter;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		static void freertos_tasks_c_additions_init( void )
+		{
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		}
+	#endif
+
+#endif
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
new file mode 100644
index 0000000..00200b8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
@@ -0,0 +1,1127 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1;
+PRIVILEGED_DATA static List_t xActiveTimerList2;
+PRIVILEGED_DATA static List_t *pxCurrentTimerList;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto-reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													configTIMER_SERVICE_TASK_NAME,
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									configTIMER_SERVICE_TASK_NAME,
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction )
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Status is thus far zero as the timer is not created statically
+			and has not been started.  The auto-reload bit may get set in
+			prvInitialiseNewTimer. */
+			pxNewTimer->ucStatus = 0x00;
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer )
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structure. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Timers can be created statically or dynamically so note this
+			timer was created statically in case it is later deleted.  The
+			auto-reload bit may get set in prvInitialiseNewTimer(). */
+			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer )
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		if( uxAutoReload != pdFALSE )
+		{
+			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer =  xTimer;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( uxAutoReload != pdFALSE )
+		{
+			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		else
+		{
+			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+UBaseType_t uxReturn;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
+		{
+			/* Not an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdFALSE;
+		}
+		else
+		{
+			/* Is an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto-reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+					{
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+						}
+					}
+					#else
+					{
+						/* If dynamic allocation is not enabled, the memory
+						could not have been dynamically allocated. So there is
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+		{
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/STM32H723XG_FLASH.ld b/STM32H723XG_FLASH.ld
new file mode 100644
index 0000000..4cad470
--- /dev/null
+++ b/STM32H723XG_FLASH.ld
@@ -0,0 +1,253 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Author		: STM32CubeMX
+**
+**  Abstract    : Linker script for STM32H723VGTx series
+**                1024Kbytes FLASH and 560Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** 
    © COPYRIGHT(c) 2025 STMicroelectronics
    
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Specify the memory areas */
+MEMORY
+{
+DTCMRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
+RAM_D1 (xrw)      : ORIGIN = 0x24000000, LENGTH = 320K
+RAM_D2 (xrw)      : ORIGIN = 0x30000000, LENGTH = 32K
+RAM_D3 (xrw)      : ORIGIN = 0x38000000, LENGTH = 16K
+ITCMRAM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+  } >DTCMRAM AT> FLASH
+
+ /* Initialized TLS data section */
+  .tdata : ALIGN(4)
+  {
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+    PROVIDE(__data_end = .);
+    PROVIDE(__tdata_end = .);
+  } >DTCMRAM AT> FLASH
+
+  PROVIDE( __tdata_start = ADDR(.tdata) );
+  PROVIDE( __tdata_size = __tdata_end - __tdata_start );
+
+  PROVIDE( __data_start = ADDR(.data) );
+  PROVIDE( __data_size = __data_end - __data_start );
+
+  PROVIDE( __tdata_source = LOADADDR(.tdata) );
+  PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+  PROVIDE( __tdata_source_size = __tdata_source_end - __tdata_source );
+
+  PROVIDE( __data_source = LOADADDR(.data) );
+  PROVIDE( __data_source_end = __tdata_source_end );
+  PROVIDE( __data_source_size = __data_source_end - __data_source );
+  /* Uninitialized data section */
+  .tbss (NOLOAD) : ALIGN(4)
+  {
+     /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.tbss .tbss.*)
+    . = ALIGN(4);
+    PROVIDE( __tbss_end = . );
+  } >DTCMRAM
+
+  PROVIDE( __tbss_start = ADDR(.tbss) );
+  PROVIDE( __tbss_size = __tbss_end - __tbss_start );
+  PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+
+  PROVIDE( __tls_base = __tdata_start );
+  PROVIDE( __tls_end = __tbss_end );
+  PROVIDE( __tls_size = __tls_end - __tls_base );
+  PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+  PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1) );
+  PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+  PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+  .bss (NOLOAD) : ALIGN(4)
+  {
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+      . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+      PROVIDE( __bss_end = .);
+  } >DTCMRAM
+  PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+
+  PROVIDE( __bss_start = __tbss_start );
+  PROVIDE( __bss_size = __bss_end - __bss_start );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack (NOLOAD) :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >DTCMRAM
+
+
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a:* ( * )
+    libm.a:* ( * )
+    libgcc.a:* ( * )
+  }
+
+}
diff --git a/User/bsp/bsp.h b/User/bsp/bsp.h
new file mode 100644
index 0000000..440aa9a
--- /dev/null
+++ b/User/bsp/bsp.h
@@ -0,0 +1,29 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER INCLUDE BEGIN */
+#include "stm32h7xx_hal.h"
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+#define BSP_OK (0)
+#define BSP_ERR (-1)
+#define BSP_ERR_NULL (-2)
+#define BSP_ERR_INITED (-3)
+#define BSP_ERR_NO_DEV (-4)
+#define BSP_ERR_TIMEOUT (-5)
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/bsp/bsp_config.yaml b/User/bsp/bsp_config.yaml
new file mode 100644
index 0000000..1b89fd5
--- /dev/null
+++ b/User/bsp/bsp_config.yaml
@@ -0,0 +1,86 @@
+can:
+  devices:
+  - instance: CAN1
+    name: '1'
+  - instance: CAN2
+    name: '2'
+  enabled: true
+dwt:
+  enabled: true
+gpio:
+  configs:
+  - custom_name: USER_KEY
+    has_exti: true
+    ioc_label: USER_KEY
+    pin: PA0-WKUP
+    type: EXTI
+  - custom_name: ACCL_CS
+    has_exti: false
+    ioc_label: ACCL_CS
+    pin: PA4
+    type: OUTPUT
+  - custom_name: GYRO_CS
+    has_exti: false
+    ioc_label: GYRO_CS
+    pin: PB0
+    type: OUTPUT
+  - custom_name: ACCL_INT
+    has_exti: true
+    ioc_label: ACCL_INT
+    pin: PC4
+    type: EXTI
+  - custom_name: GYRO_INT
+    has_exti: true
+    ioc_label: GYRO_INT
+    pin: PC5
+    type: EXTI
+  - custom_name: CMPS_INT
+    has_exti: true
+    ioc_label: CMPS_INT
+    pin: PG3
+    type: EXTI
+  - custom_name: CMPS_RST
+    has_exti: false
+    ioc_label: CMPS_RST
+    pin: PG6
+    type: OUTPUT
+  enabled: true
+mm:
+  enabled: true
+pwm:
+  configs:
+  - channel: TIM_CHANNEL_3
+    custom_name: BUZZER
+    label: BUZZER
+    timer: TIM4
+  - channel: TIM_CHANNEL_1
+    custom_name: IMU_HEAT_PWM
+    label: IMU_HEAT_PWM
+    timer: TIM10
+  - channel: TIM_CHANNEL_1
+    custom_name: LED_B
+    label: LED_B
+    timer: TIM5
+  - channel: TIM_CHANNEL_2
+    custom_name: LED_G
+    label: LED_G
+    timer: TIM5
+  - channel: TIM_CHANNEL_3
+    custom_name: LED_R
+    label: LED_R
+    timer: TIM5
+  enabled: true
+spi:
+  devices:
+  - instance: SPI1
+    name: BMI088
+  enabled: true
+time:
+  enabled: true
+uart:
+  devices:
+  - instance: USART3
+    name: AT9S_PRO
+  - instance: USART6
+    name: VOFA
+  enabled: true
diff --git a/User/bsp/fdcan.c b/User/bsp/fdcan.c
new file mode 100644
index 0000000..b2706f8
--- /dev/null
+++ b/User/bsp/fdcan.c
@@ -0,0 +1,527 @@
+/* Includes ----------------------------------------------------------------- */
+#include "fdcan.h"
+#include "bsp/fdcan.h"
+#include "bsp/bsp.h"
+#include "stm32h7xx_hal_gpio.h"
+#include 
+#include 
+#include 
+#include 
+/* Private define ----------------------------------------------------------- */
+#define FDCAN_QUEUE_MUTEX_TIMEOUT         100
+
+/* Private typedef ---------------------------------------------------------- */
+typedef struct BSP_FDCAN_QueueNode {
+    BSP_FDCAN_t fdcan;
+    uint32_t can_id;
+    osMessageQueueId_t queue;
+    uint8_t queue_size;
+    struct BSP_FDCAN_QueueNode *next;
+} BSP_FDCAN_QueueNode_t;
+
+/* Private variables -------------------------------------------------------- */
+static BSP_FDCAN_QueueNode_t *queue_list = NULL;
+static osMutexId_t queue_mutex = NULL;
+static osMutexId_t tx_queue_mutex[BSP_FDCAN_NUM] = { NULL };
+static void (*FDCAN_Callback[BSP_FDCAN_NUM][HAL_FDCAN_CB_NUM])(void);
+static bool inited = false;
+static BSP_FDCAN_IdParser_t id_parser = NULL;
+static BSP_FDCAN_TxQueue_t tx_queues[BSP_FDCAN_NUM];
+
+/* Private function prototypes ---------------------------------------------- */
+static BSP_FDCAN_t FDCAN_Get(FDCAN_HandleTypeDef *hfdcan);
+static osMessageQueueId_t BSP_FDCAN_FindQueue(BSP_FDCAN_t fdcan, uint32_t can_id);
+static int8_t BSP_FDCAN_CreateIdQueue(BSP_FDCAN_t fdcan, uint32_t can_id, uint8_t queue_size);
+static void BSP_FDCAN_RxFifo0Callback(void);
+static void BSP_FDCAN_RxFifo1Callback(void);
+static void BSP_FDCAN_TxCompleteCallback(void);
+static BSP_FDCAN_FrameType_t BSP_FDCAN_GetFrameType(FDCAN_RxHeaderTypeDef *header);
+static uint32_t BSP_FDCAN_DefaultIdParser(uint32_t original_id, BSP_FDCAN_FrameType_t frame_type);
+static void BSP_FDCAN_TxQueueInit(BSP_FDCAN_t fdcan);
+static bool BSP_FDCAN_TxQueuePush(BSP_FDCAN_t fdcan, BSP_FDCAN_TxMessage_t *msg);
+static bool BSP_FDCAN_TxQueuePop(BSP_FDCAN_t fdcan, BSP_FDCAN_TxMessage_t *msg);
+static bool BSP_FDCAN_TxQueueIsEmpty(BSP_FDCAN_t fdcan);
+
+/* Private functions -------------------------------------------------------- */
+static BSP_FDCAN_t FDCAN_Get(FDCAN_HandleTypeDef *hfdcan) {
+    if (hfdcan == NULL) return BSP_FDCAN_ERR;
+    if (hfdcan->Instance == FDCAN1) return BSP_FDCAN_1;
+    else if (hfdcan->Instance == FDCAN2) return BSP_FDCAN_2;
+    else return BSP_FDCAN_ERR;
+}
+
+static osMessageQueueId_t BSP_FDCAN_FindQueue(BSP_FDCAN_t fdcan, uint32_t can_id) {
+    BSP_FDCAN_QueueNode_t *node = queue_list;
+    while (node != NULL) {
+        if (node->fdcan == fdcan && node->can_id == can_id) return node->queue;
+        node = node->next;
+    }
+    return NULL;
+}
+
+static int8_t BSP_FDCAN_CreateIdQueue(BSP_FDCAN_t fdcan, uint32_t can_id, uint8_t queue_size) {
+  if (queue_size == 0) queue_size = BSP_FDCAN_DEFAULT_QUEUE_SIZE;
+  if (osMutexAcquire(queue_mutex, FDCAN_QUEUE_MUTEX_TIMEOUT) != osOK) return BSP_ERR_TIMEOUT;
+  BSP_FDCAN_QueueNode_t *node = queue_list;
+  while (node != NULL) {
+    if (node->fdcan == fdcan && node->can_id == can_id) {
+      osMutexRelease(queue_mutex);
+      return BSP_ERR;
+    }
+    node = node->next;
+  }
+  
+  BSP_FDCAN_QueueNode_t *new_node = (BSP_FDCAN_QueueNode_t *)BSP_Malloc(sizeof(BSP_FDCAN_QueueNode_t));
+  if (new_node == NULL) { osMutexRelease(queue_mutex); return BSP_ERR_NULL; }
+  new_node->queue = osMessageQueueNew(queue_size, sizeof(BSP_FDCAN_Message_t), NULL);
+  if (new_node->queue == NULL) { BSP_Free(new_node); osMutexRelease(queue_mutex); return BSP_ERR; }
+  new_node->fdcan = fdcan;
+  new_node->can_id = can_id;
+  new_node->queue_size = queue_size;
+  new_node->next = queue_list;
+  queue_list = new_node;
+  osMutexRelease(queue_mutex);
+  return BSP_OK;
+}
+
+static BSP_FDCAN_FrameType_t BSP_FDCAN_GetFrameType(FDCAN_RxHeaderTypeDef *header) {
+    if (header->RxFrameType == FDCAN_REMOTE_FRAME) {
+        return (header->IdType == FDCAN_EXTENDED_ID) ? BSP_FDCAN_FRAME_EXT_REMOTE : BSP_FDCAN_FRAME_STD_REMOTE;
+    } else {
+        return (header->IdType == FDCAN_EXTENDED_ID) ? BSP_FDCAN_FRAME_EXT_DATA : BSP_FDCAN_FRAME_STD_DATA;
+    }
+}
+
+static uint32_t BSP_FDCAN_DefaultIdParser(uint32_t original_id, BSP_FDCAN_FrameType_t frame_type) {
+    (void)frame_type;
+    return original_id;
+}
+
+static void BSP_FDCAN_TxQueueInit(BSP_FDCAN_t fdcan) {
+    if (fdcan >= BSP_FDCAN_NUM) return;
+    __atomic_store_n((uint32_t *)&tx_queues[fdcan].head, 0U, __ATOMIC_RELAXED);
+    __atomic_store_n((uint32_t *)&tx_queues[fdcan].tail, 0U, __ATOMIC_RELAXED);
+}
+
+static bool BSP_FDCAN_TxQueuePush(BSP_FDCAN_t fdcan, BSP_FDCAN_TxMessage_t *msg) {
+    if (fdcan >= BSP_FDCAN_NUM || msg == NULL) return false;
+    BSP_FDCAN_TxQueue_t *queue = &tx_queues[fdcan];
+    if (tx_queue_mutex[fdcan] == NULL) return false;
+    if (osMutexAcquire(tx_queue_mutex[fdcan], FDCAN_QUEUE_MUTEX_TIMEOUT) != osOK) return false;
+    uint32_t head = __atomic_load_n((uint32_t *)&queue->head, __ATOMIC_RELAXED);
+    uint32_t tail = __atomic_load_n((uint32_t *)&queue->tail, __ATOMIC_ACQUIRE);
+    uint32_t next_head = (head + 1) % BSP_FDCAN_TX_QUEUE_SIZE;
+    if (next_head == tail) {
+        osMutexRelease(tx_queue_mutex[fdcan]);
+        return false;
+    }
+    queue->buffer[head] = *msg;
+    __atomic_store_n((uint32_t *)&queue->head, next_head, __ATOMIC_RELEASE);
+    osMutexRelease(tx_queue_mutex[fdcan]);
+    return true;
+}
+
+static bool BSP_FDCAN_TxQueuePop(BSP_FDCAN_t fdcan, BSP_FDCAN_TxMessage_t *msg) {
+    if (fdcan >= BSP_FDCAN_NUM || msg == NULL) return false;
+    BSP_FDCAN_TxQueue_t *queue = &tx_queues[fdcan];
+    uint32_t head = __atomic_load_n((uint32_t *)&queue->head, __ATOMIC_ACQUIRE);
+    uint32_t tail = __atomic_load_n((uint32_t *)&queue->tail, __ATOMIC_RELAXED);
+    if (head == tail) return false;
+    *msg = queue->buffer[tail];
+    uint32_t next_tail = (tail + 1) % BSP_FDCAN_TX_QUEUE_SIZE;
+    __atomic_store_n((uint32_t *)&queue->tail, next_tail, __ATOMIC_RELEASE);
+    return true;
+}
+
+static bool BSP_FDCAN_TxQueueIsEmpty(BSP_FDCAN_t fdcan) {
+    if (fdcan >= BSP_FDCAN_NUM) return true;
+    uint32_t head = __atomic_load_n((uint32_t *)&tx_queues[fdcan].head, __ATOMIC_ACQUIRE);
+    uint32_t tail = __atomic_load_n((uint32_t *)&tx_queues[fdcan].tail, __ATOMIC_RELAXED);
+    return head == tail;
+}
+
+static void BSP_FDCAN_TxCompleteCallback(void) {
+    for (int i = 0; i < BSP_FDCAN_NUM; i++) {
+        BSP_FDCAN_t fdcan = (BSP_FDCAN_t)i;
+        FDCAN_HandleTypeDef *hfdcan = BSP_FDCAN_GetHandle(fdcan);
+        if (hfdcan == NULL) continue;
+        BSP_FDCAN_TxMessage_t msg;
+        /* 尝试从队列发送直到邮箱/ FIFO 满 */
+        while (!BSP_FDCAN_TxQueueIsEmpty(fdcan)) {
+            /* 此处使用 HAL 接口判断是否可发送 — 不同 MCU HAL 名称可能不同 */
+            if (HAL_FDCAN_GetTxFifoFreeLevel(hfdcan) == 0) break;
+            if (!BSP_FDCAN_TxQueuePop(fdcan, &msg)) break;
+            /* 发送消息 - 使用 HAL_FDCAN_AddMessageToTxFifoQ 或相应 API */
+            HAL_StatusTypeDef res = HAL_FDCAN_AddMessageToTxFifoQ(hfdcan, &msg.header, msg.data);
+            if (res != HAL_OK) {
+                break;
+            }
+        }
+    }
+}
+
+static void BSP_FDCAN_RxFifo0Callback(void) {
+    FDCAN_RxHeaderTypeDef rx_header;
+    uint8_t rx_data[BSP_FDCAN_MAX_DLC];
+    for (int fdcan_idx = 0; fdcan_idx < BSP_FDCAN_NUM; fdcan_idx++) {
+        FDCAN_HandleTypeDef *hfdcan = BSP_FDCAN_GetHandle((BSP_FDCAN_t)fdcan_idx);
+        if (hfdcan == NULL) continue;
+        while (HAL_FDCAN_GetRxFifoFillLevel(hfdcan, FDCAN_RX_FIFO0) > 0) {
+            if (HAL_FDCAN_GetRxMessage(hfdcan, FDCAN_RX_FIFO0, &rx_header, rx_data) == HAL_OK) {
+                uint32_t original_id = (rx_header.IdType == FDCAN_STANDARD_ID) ? rx_header.Identifier&0x7ff : rx_header.Identifier&0x1fffffff;
+                BSP_FDCAN_FrameType_t frame_type = BSP_FDCAN_GetFrameType(&rx_header);
+                uint32_t parsed_id = BSP_FDCAN_ParseId(original_id, frame_type);
+                osMessageQueueId_t queue = BSP_FDCAN_FindQueue((BSP_FDCAN_t)fdcan_idx, parsed_id);
+                if (queue != NULL) {
+                    BSP_FDCAN_Message_t msg;
+                    msg.frame_type = frame_type;
+                    msg.original_id = original_id;
+                    msg.parsed_id = parsed_id;
+                    msg.dlc = rx_header.DataLength / 8;
+                    if (msg.dlc > BSP_FDCAN_MAX_DLC) msg.dlc = BSP_FDCAN_MAX_DLC;
+                    memcpy(msg.data, rx_data, msg.dlc);
+                    osMessageQueuePut(queue, &msg, 0, 0);
+                }
+            } else {
+                break;
+            }
+        }
+    }
+}
+
+static void BSP_FDCAN_RxFifo1Callback(void) {
+    FDCAN_RxHeaderTypeDef rx_header;
+    uint8_t rx_data[BSP_FDCAN_MAX_DLC];
+    for (int fdcan_idx = 0; fdcan_idx < BSP_FDCAN_NUM; fdcan_idx++) {
+        FDCAN_HandleTypeDef *hfdcan = BSP_FDCAN_GetHandle((BSP_FDCAN_t)fdcan_idx);
+        if (hfdcan == NULL) continue;
+        while (HAL_FDCAN_GetRxFifoFillLevel(hfdcan, FDCAN_RX_FIFO1) > 0) {
+            if (HAL_FDCAN_GetRxMessage(hfdcan, FDCAN_RX_FIFO1, &rx_header, rx_data) == HAL_OK) {
+                uint32_t original_id = (rx_header.IdType == FDCAN_STANDARD_ID) ? rx_header.Identifier&0x7ff : rx_header.Identifier&0x1fffffff;
+                BSP_FDCAN_FrameType_t frame_type = BSP_FDCAN_GetFrameType(&rx_header);
+                uint32_t parsed_id = BSP_FDCAN_ParseId(original_id, frame_type);
+                osMessageQueueId_t queue = BSP_FDCAN_FindQueue((BSP_FDCAN_t)fdcan_idx, parsed_id);
+                if (queue != NULL) {
+                    BSP_FDCAN_Message_t msg;
+                    msg.frame_type = frame_type;
+                    msg.original_id = original_id;
+                    msg.parsed_id = parsed_id;
+                    msg.dlc = rx_header.DataLength / 8;
+                    if (msg.dlc > BSP_FDCAN_MAX_DLC) msg.dlc = BSP_FDCAN_MAX_DLC;
+                    memcpy(msg.data, rx_data, msg.dlc);
+                    osMessageQueuePut(queue, &msg, 0, 0);
+                }
+            } else {
+                break;
+            }
+        }
+    }
+}
+
+/* HAL Callback Stubs (map HAL FDCAN callbacks to user callbacks) */
+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs) {
+    BSP_FDCAN_t bsp_fdcan = FDCAN_Get(hfdcan);
+    if (bsp_fdcan != BSP_FDCAN_ERR) {
+        if (FDCAN_Callback[bsp_fdcan][HAL_FDCAN_TX_EVENT_FIFO_CB])
+            FDCAN_Callback[bsp_fdcan][HAL_FDCAN_TX_EVENT_FIFO_CB]();
+    }
+}
+
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex) {
+    BSP_FDCAN_t bsp_fdcan = FDCAN_Get(hfdcan);
+    if (bsp_fdcan != BSP_FDCAN_ERR) {
+        if (FDCAN_Callback[bsp_fdcan][HAL_FDCAN_TX_BUFFER_COMPLETE_CB])
+            FDCAN_Callback[bsp_fdcan][HAL_FDCAN_TX_BUFFER_COMPLETE_CB]();
+    }
+}
+
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex) {
+    BSP_FDCAN_t bsp_fdcan = FDCAN_Get(hfdcan);
+    if (bsp_fdcan != BSP_FDCAN_ERR) {
+        if (FDCAN_Callback[bsp_fdcan][HAL_FDCAN_TX_BUFFER_ABORT_CB])
+            FDCAN_Callback[bsp_fdcan][HAL_FDCAN_TX_BUFFER_ABORT_CB]();
+    }
+}
+
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs) {
+    BSP_FDCAN_t bsp_fdcan = FDCAN_Get(hfdcan);
+    if (bsp_fdcan != BSP_FDCAN_ERR) {
+        if (FDCAN_Callback[bsp_fdcan][HAL_FDCAN_RX_FIFO0_MSG_PENDING_CB])
+            FDCAN_Callback[bsp_fdcan][HAL_FDCAN_RX_FIFO0_MSG_PENDING_CB]();
+    }
+}
+
+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs) {
+    BSP_FDCAN_t bsp_fdcan = FDCAN_Get(hfdcan);
+    if (bsp_fdcan != BSP_FDCAN_ERR) {
+        if (FDCAN_Callback[bsp_fdcan][HAL_FDCAN_RX_FIFO1_MSG_PENDING_CB])
+            FDCAN_Callback[bsp_fdcan][HAL_FDCAN_RX_FIFO1_MSG_PENDING_CB]();
+    }
+}
+
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) {
+    BSP_FDCAN_t bsp_fdcan = FDCAN_Get(hfdcan);
+    if (bsp_fdcan != BSP_FDCAN_ERR) {
+        if (FDCAN_Callback[bsp_fdcan][HAL_FDCAN_ERROR_CB])
+            FDCAN_Callback[bsp_fdcan][HAL_FDCAN_ERROR_CB]();
+    }
+}
+
+/* Exported functions ------------------------------------------------------- */
+int8_t BSP_FDCAN_Init(void) {
+    if (inited) return BSP_ERR_INITED;
+
+    memset(FDCAN_Callback, 0, sizeof(FDCAN_Callback));
+
+    for (int i = 0; i < BSP_FDCAN_NUM; i++) BSP_FDCAN_TxQueueInit((BSP_FDCAN_t)i);
+
+    id_parser = BSP_FDCAN_DefaultIdParser;
+
+    queue_mutex = osMutexNew(NULL);
+
+    if (queue_mutex == NULL) return BSP_ERR;
+
+    /* create per-instance tx queue mutexes (producers will lock) */
+    for (int i = 0; i < BSP_FDCAN_NUM; i++) {
+        tx_queue_mutex[i] = osMutexNew(NULL);
+        if (tx_queue_mutex[i] == NULL) {
+            /* cleanup previously created */
+            for (int j = 0; j < i; j++) osMutexDelete(tx_queue_mutex[j]);
+            osMutexDelete(queue_mutex);
+            return BSP_ERR;
+        }
+    }
+
+    inited = true;
+
+  /* 配置并启动 FDCAN 实例，绑定中断/回调 */
+
+  //  过滤器编号：相对于每个（相当于经典can过滤器的bank）
+  //  sFilterConfig.FilterIndex = 0 to 127(标准ID) or 0 to 63(扩展ID);  
+  //  关于过滤器索引的说明：
+  //  由stm32h7xx_hal_fdcan.c的第1874行代码可知滤波器地址计算方式如下：
+  //  StandardFilterSA（字节） = SRAMCAN_BASE + (MessageRAMOffset * 4U)
+  //  标准滤波器物理地址（字节） = StandardFilterSA + (FilterIndex * 4U)（每个标准滤波器占 4 字节 = 1 word,扩展的则是8个字节）
+  //  
+  //
+  //  标识符类型:
+  //  sFilterConfig.IdType = FDCAN_STANDARD_ID or FDCAN_EXTENDED_ID;
+  //  过滤器类型: （仅介绍掩码模式）
+  //  sFilterConfig.FilterType = FDCAN_FILTER_MASK;(掩码模式）
+  //  过滤器配置:
+  //  sFilterConfig.FilterConfig = FDCAN_FILTER_DISABLE; (禁用该滤波器条目)
+  //                               FDCAN_FILTER_TO_RXFIFO0; (将匹配的消息放入 FIFO 0（普通优先级）)
+  //                               FDCAN_FILTER_TO_RXFIFO1; (将匹配的消息放入 FIFO 1（高优先级）)
+  //                               FDCAN_FILTER_TO_RXBUFFER; (将匹配的消息放入 指定的接收缓冲区)
+  //                               FDCAN_FILTER_REJECT; (拒绝接收该标识符对应的报文)
+  //                               FDCAN_FILTER_ACCEPT; (接受所有消息)
+  //                               FDCAN_FILTER_HP            (过滤器匹配时，将报文标记为高优先级)                            
+  //                               FDCAN_FILTER_TO_RXFIFO0_HP (过滤器匹配时，将报文标记为高优先级并存储至接收FIFO 0)          
+  //                               FDCAN_FILTER_TO_RXFIFO1_HP (过滤器匹配时，将报文标记为高优先级并存储至接收FIFO 1)          
+  //                               FDCAN_FILTER_TO_RXBUFFER   (将报文存储至接收缓冲区，过滤器类型（FilterType）配置项失效 )
+  //  过滤器ID与掩码(FilterType掩码模式下)
+  //  比较值（要匹配的 ID 的参考位）
+  //  sFilterConfig.FilterID1 = 0 to 0x7FF; 标准ID
+  //                            0 to 0x1FFFFFFF 扩展ID
+  //  掩码（1=比较该位，0=忽略该位）
+  //  sFilterConfig.FilterID2 = 0 to 0x7FF; 标准ID
+  //                            0 to 0x1FFFFFFF 扩展ID
+  //  接收缓冲区索引
+  //  FilterConfig == FDCAN_FILTER_TO_RXBUFFER 时有效;必须小于RxBuffersNbr配置的实际Rx buffer数量
+  //  sFilterConfig.RxBufferIndex = 0 to (RxBuffersNbr - 1);
+  //  标记校准信息（用于 FDCAN 校准/时钟相关单元作特殊处理或统计）
+  //  仅在FilterConfig 设为 FDCAN_FILTER_TO_RXBUFFER 时才有意义，通常设置为0
+  //  IsCalibrationMsg = 0 or 1; 
+
+  /* 依据上述说明，配置过滤器 */
+  FDCAN_FilterTypeDef sFilterConfig;
+  /* 配置 FDCAN1 过滤器 */
+  /* 索引0;标准ID;掩码模式;存入 FIFO 0（普通优先级）;不过滤; */
+  sFilterConfig.FilterIndex = 0;
+  sFilterConfig.IdType = FDCAN_STANDARD_ID; 
+  sFilterConfig.FilterType = FDCAN_FILTER_MASK; 
+  sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
+  sFilterConfig.FilterID1 = 0x000; 
+  sFilterConfig.FilterID2 = 0x000; 
+  sFilterConfig.RxBufferIndex = 0;
+  HAL_FDCAN_ConfigFilter(&hfdcan1, &sFilterConfig);
+  HAL_FDCAN_ConfigGlobalFilter(&hfdcan1,FDCAN_REJECT, FDCAN_REJECT, DISABLE, DISABLE);
+  /* 配置 FDCAN2 过滤器 */
+  /* 索引0;标准ID;掩码模式;存入 FIFO 1（普通优先级）;不过滤; */
+  sFilterConfig.FilterIndex = 0;  
+  sFilterConfig.IdType = FDCAN_STANDARD_ID;
+  sFilterConfig.FilterType = FDCAN_FILTER_MASK; 
+  sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO1;
+  sFilterConfig.FilterID1 = 0x000; 
+  sFilterConfig.FilterID2 = 0x000; 
+  sFilterConfig.RxBufferIndex = 0;
+  HAL_FDCAN_ConfigFilter(&hfdcan2, &sFilterConfig);
+  HAL_FDCAN_ConfigGlobalFilter(&hfdcan2,FDCAN_REJECT, FDCAN_REJECT, DISABLE, DISABLE);
+  /* 配置 FDCAN3 过滤器 */
+  /* 索引0;标准ID;掩码模式;存入 FIFO 1（普通优先级）;不过滤; */
+  sFilterConfig.FilterIndex = 0;  
+  sFilterConfig.IdType = FDCAN_STANDARD_ID;
+  sFilterConfig.FilterType = FDCAN_FILTER_MASK; 
+  sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO1;
+  sFilterConfig.FilterID1 = 0x000; 
+  sFilterConfig.FilterID2 = 0x000; 
+  sFilterConfig.RxBufferIndex = 0;
+  HAL_FDCAN_ConfigFilter(&hfdcan3, &sFilterConfig);
+  HAL_FDCAN_ConfigGlobalFilter(&hfdcan3,FDCAN_REJECT, FDCAN_REJECT, DISABLE, DISABLE);
+
+  /* __ ,启动！ */
+  HAL_FDCAN_Start(&hfdcan1);
+  HAL_FDCAN_Start(&hfdcan2);
+  HAL_FDCAN_Start(&hfdcan3);
+
+  HAL_FDCAN_ActivateNotification(&hfdcan1, FDCAN_IT_RX_FIFO0_NEW_MESSAGE 
+                                                              | FDCAN_IT_TX_EVT_FIFO_NEW_DATA 
+                                                              | FDCAN_IT_RAM_ACCESS_FAILURE, 0);//加一个RAM访问失败中断
+  HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_RX_FIFO1_NEW_MESSAGE 
+                                                              | FDCAN_IT_TX_EVT_FIFO_NEW_DATA
+                                                              | FDCAN_IT_RAM_ACCESS_FAILURE, 0);
+  HAL_FDCAN_ActivateNotification(&hfdcan3, FDCAN_IT_RX_FIFO1_NEW_MESSAGE 
+                                                              | FDCAN_IT_TX_EVT_FIFO_NEW_DATA
+                                                              | FDCAN_IT_RAM_ACCESS_FAILURE, 0);
+
+  BSP_FDCAN_RegisterCallback(BSP_FDCAN_1, HAL_FDCAN_RX_FIFO0_MSG_PENDING_CB, BSP_FDCAN_RxFifo0Callback);
+  BSP_FDCAN_RegisterCallback(BSP_FDCAN_1, HAL_FDCAN_TX_EVENT_FIFO_CB, BSP_FDCAN_TxCompleteCallback);
+  
+  BSP_FDCAN_RegisterCallback(BSP_FDCAN_2, HAL_FDCAN_RX_FIFO1_MSG_PENDING_CB, BSP_FDCAN_RxFifo1Callback);
+  BSP_FDCAN_RegisterCallback(BSP_FDCAN_2, HAL_FDCAN_TX_EVENT_FIFO_CB, BSP_FDCAN_TxCompleteCallback);
+
+  BSP_FDCAN_RegisterCallback(BSP_FDCAN_3, HAL_FDCAN_RX_FIFO1_MSG_PENDING_CB, BSP_FDCAN_RxFifo1Callback);
+  BSP_FDCAN_RegisterCallback(BSP_FDCAN_3, HAL_FDCAN_TX_EVENT_FIFO_CB, BSP_FDCAN_TxCompleteCallback);
+  
+  //POWER ENABLE
+  // HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+
+  return BSP_OK;
+}
+
+FDCAN_HandleTypeDef *BSP_FDCAN_GetHandle(BSP_FDCAN_t fdcan) {
+    if (fdcan >= BSP_FDCAN_NUM) return NULL;
+    switch (fdcan) {
+        case BSP_FDCAN_1: return &hfdcan1;
+        case BSP_FDCAN_2: return &hfdcan2;
+        default: return NULL;
+    }
+}
+
+int8_t BSP_FDCAN_RegisterCallback(BSP_FDCAN_t fdcan, BSP_FDCAN_Callback_t type, void (*callback)(void)) {
+    if (!inited) return BSP_ERR_INITED;
+    if (callback == NULL) return BSP_ERR_NULL;
+    if (fdcan >= BSP_FDCAN_NUM) return BSP_ERR;
+    if (type >= HAL_FDCAN_CB_NUM) return BSP_ERR;
+    FDCAN_Callback[fdcan][type] = callback;
+    return BSP_OK;
+}
+
+int8_t BSP_FDCAN_Transmit(BSP_FDCAN_t fdcan, BSP_FDCAN_Format_t format, uint32_t id, uint8_t *data, uint8_t dlc) {
+    if (!inited) return BSP_ERR_INITED;
+    if (fdcan >= BSP_FDCAN_NUM) return BSP_ERR;
+    if (data == NULL && format != BSP_FDCAN_FORMAT_STD_REMOTE && format != BSP_FDCAN_FORMAT_EXT_REMOTE) return BSP_ERR_NULL;
+    if (dlc > BSP_FDCAN_MAX_DLC) return BSP_ERR;
+    FDCAN_HandleTypeDef *hfdcan = BSP_FDCAN_GetHandle(fdcan);
+    if (hfdcan == NULL) return BSP_ERR_NULL;
+
+    BSP_FDCAN_TxMessage_t tx_msg = {0};
+    switch (format) {
+        case BSP_FDCAN_FORMAT_STD_DATA:
+            tx_msg.header.Identifier = id;
+            tx_msg.header.IdType = FDCAN_STANDARD_ID;
+            tx_msg.header.TxFrameType = FDCAN_DATA_FRAME;
+            break;
+        case BSP_FDCAN_FORMAT_EXT_DATA:
+            tx_msg.header.Identifier = id;
+            tx_msg.header.IdType = FDCAN_EXTENDED_ID;
+            tx_msg.header.TxFrameType = FDCAN_DATA_FRAME;
+            break;
+        case BSP_FDCAN_FORMAT_STD_REMOTE:
+            tx_msg.header.Identifier = id;
+            tx_msg.header.IdType = FDCAN_STANDARD_ID;
+            tx_msg.header.TxFrameType = FDCAN_REMOTE_FRAME;
+            break;
+        case BSP_FDCAN_FORMAT_EXT_REMOTE:
+            tx_msg.header.Identifier = id;
+            tx_msg.header.IdType = FDCAN_EXTENDED_ID;
+            tx_msg.header.TxFrameType = FDCAN_REMOTE_FRAME;
+            break;
+        default:
+            return BSP_ERR;
+    }
+    tx_msg.header.DataLength = dlc * 8;
+    if (data != NULL && dlc > 0) memcpy(tx_msg.data, data, dlc);
+
+    if (HAL_FDCAN_GetTxFifoFreeLevel(hfdcan) > 0) {
+        if (HAL_FDCAN_AddMessageToTxFifoQ(hfdcan, &tx_msg.header, tx_msg.data) == HAL_OK) return BSP_OK;
+    }
+    if (BSP_FDCAN_TxQueuePush(fdcan, &tx_msg)) return BSP_OK;
+    return BSP_ERR;
+}
+
+int8_t BSP_FDCAN_TransmitStdDataFrame(BSP_FDCAN_t fdcan, BSP_FDCAN_StdDataFrame_t *frame) {
+    if (frame == NULL) return BSP_ERR_NULL;
+    return BSP_FDCAN_Transmit(fdcan, BSP_FDCAN_FORMAT_STD_DATA, frame->id, frame->data, frame->dlc);
+}
+
+int8_t BSP_FDCAN_TransmitExtDataFrame(BSP_FDCAN_t fdcan, BSP_FDCAN_ExtDataFrame_t *frame) {
+    if (frame == NULL) return BSP_ERR_NULL;
+    return BSP_FDCAN_Transmit(fdcan, BSP_FDCAN_FORMAT_EXT_DATA, frame->id, frame->data, frame->dlc);
+}
+
+int8_t BSP_FDCAN_TransmitRemoteFrame(BSP_FDCAN_t fdcan, BSP_FDCAN_RemoteFrame_t *frame) {
+    if (frame == NULL) return BSP_ERR_NULL;
+    BSP_FDCAN_Format_t format = frame->is_extended ? BSP_FDCAN_FORMAT_EXT_REMOTE : BSP_FDCAN_FORMAT_STD_REMOTE;
+    return BSP_FDCAN_Transmit(fdcan, format, frame->id, NULL, frame->dlc);
+}
+
+int8_t BSP_FDCAN_RegisterId(BSP_FDCAN_t fdcan, uint32_t can_id, uint8_t queue_size) {
+    if (!inited) return BSP_ERR_INITED;
+    return BSP_FDCAN_CreateIdQueue(fdcan, can_id, queue_size);
+}
+
+int8_t BSP_FDCAN_GetMessage(BSP_FDCAN_t fdcan, uint32_t can_id, BSP_FDCAN_Message_t *msg, uint32_t timeout) {
+    if (!inited) return BSP_ERR_INITED;
+    if (msg == NULL) return BSP_ERR_NULL;
+    if (osMutexAcquire(queue_mutex, FDCAN_QUEUE_MUTEX_TIMEOUT) != osOK) return BSP_ERR_TIMEOUT;
+    osMessageQueueId_t queue = BSP_FDCAN_FindQueue(fdcan, can_id);
+    osMutexRelease(queue_mutex);
+    if (queue == NULL) return BSP_ERR_NO_DEV;
+    osStatus_t res = osMessageQueueGet(queue, msg, NULL, timeout);
+    return (res == osOK) ? BSP_OK : BSP_ERR;
+}
+
+int32_t BSP_FDCAN_GetQueueCount(BSP_FDCAN_t fdcan, uint32_t can_id) {
+    if (!inited) return -1;
+    if (osMutexAcquire(queue_mutex, FDCAN_QUEUE_MUTEX_TIMEOUT) != osOK) return -1;
+    osMessageQueueId_t queue = BSP_FDCAN_FindQueue(fdcan, can_id);
+    osMutexRelease(queue_mutex);
+    if (queue == NULL) return -1;
+    return (int32_t)osMessageQueueGetCount(queue);
+}
+
+int8_t BSP_FDCAN_FlushQueue(BSP_FDCAN_t fdcan, uint32_t can_id) {
+    if (!inited) return BSP_ERR_INITED;
+    if (osMutexAcquire(queue_mutex, FDCAN_QUEUE_MUTEX_TIMEOUT) != osOK) return BSP_ERR_TIMEOUT;
+    osMessageQueueId_t queue = BSP_FDCAN_FindQueue(fdcan, can_id);
+    osMutexRelease(queue_mutex);
+    if (queue == NULL) return BSP_ERR_NO_DEV;
+    BSP_FDCAN_Message_t tmp;
+    while (osMessageQueueGet(queue, &tmp, NULL, BSP_FDCAN_TIMEOUT_IMMEDIATE) == osOK) { }
+    return BSP_OK;
+}
+
+int8_t BSP_FDCAN_RegisterIdParser(BSP_FDCAN_IdParser_t parser) {
+    if (!inited) return BSP_ERR_INITED;
+    if (parser == NULL) return BSP_ERR_NULL;
+    id_parser = parser;
+    return BSP_OK;
+}
+
+uint32_t BSP_FDCAN_ParseId(uint32_t original_id, BSP_FDCAN_FrameType_t frame_type) {
+    if (id_parser != NULL) return id_parser(original_id, frame_type);
+    return BSP_FDCAN_DefaultIdParser(original_id, frame_type);
+}
+/* */
+
diff --git a/User/bsp/fdcan.h b/User/bsp/fdcan.h
new file mode 100644
index 0000000..56470d6
--- /dev/null
+++ b/User/bsp/fdcan.h
@@ -0,0 +1,118 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include 
+#include "bsp/bsp.h"
+#include "bsp/mm.h"
+#include 
+
+/* USER INCLUDE BEGIN */
+#include 
+#include 
+/* USER INCLUDE END */
+
+/* Exported constants ------------------------------------------------------- */
+#define BSP_FDCAN_MAX_DLC                 64
+#define BSP_FDCAN_DEFAULT_QUEUE_SIZE      10
+#define BSP_FDCAN_TIMEOUT_IMMEDIATE       0
+#define BSP_FDCAN_TIMEOUT_FOREVER         osWaitForever
+#define BSP_FDCAN_TX_QUEUE_SIZE           32
+
+/* Exported types ----------------------------------------------------------- */
+typedef enum {
+  BSP_FDCAN_1,
+  BSP_FDCAN_2,
+  BSP_FDCAN_3,
+  BSP_FDCAN_NUM,
+  BSP_FDCAN_ERR,
+} BSP_FDCAN_t;
+
+typedef enum {
+  HAL_FDCAN_TX_EVENT_FIFO_CB,
+  HAL_FDCAN_TX_BUFFER_COMPLETE_CB,
+  HAL_FDCAN_TX_BUFFER_ABORT_CB,
+  HAL_FDCAN_RX_FIFO0_MSG_PENDING_CB,
+  HAL_FDCAN_RX_FIFO0_FULL_CB,
+  HAL_FDCAN_RX_FIFO1_MSG_PENDING_CB,
+  HAL_FDCAN_RX_FIFO1_FULL_CB,
+  HAL_FDCAN_ERROR_CB,
+  HAL_FDCAN_CB_NUM,
+} BSP_FDCAN_Callback_t;
+
+typedef enum {
+  BSP_FDCAN_FORMAT_STD_DATA,
+  BSP_FDCAN_FORMAT_EXT_DATA,
+  BSP_FDCAN_FORMAT_STD_REMOTE,
+  BSP_FDCAN_FORMAT_EXT_REMOTE,
+} BSP_FDCAN_Format_t;
+
+typedef enum {
+  BSP_FDCAN_FRAME_STD_DATA,
+  BSP_FDCAN_FRAME_EXT_DATA,
+  BSP_FDCAN_FRAME_STD_REMOTE,
+  BSP_FDCAN_FRAME_EXT_REMOTE,
+} BSP_FDCAN_FrameType_t;
+
+typedef struct {
+    BSP_FDCAN_FrameType_t frame_type;
+    uint32_t original_id;
+    uint32_t parsed_id;
+    uint8_t dlc;
+    uint8_t data[BSP_FDCAN_MAX_DLC];
+    uint32_t timestamp;
+} BSP_FDCAN_Message_t;
+
+typedef struct {
+    uint32_t id;
+    uint8_t dlc;
+    uint8_t data[BSP_FDCAN_MAX_DLC];
+} BSP_FDCAN_StdDataFrame_t;
+
+typedef struct {
+    uint32_t id;
+    uint8_t dlc;
+    uint8_t data[BSP_FDCAN_MAX_DLC];
+} BSP_FDCAN_ExtDataFrame_t;
+
+typedef struct {
+    uint32_t id;
+    uint8_t dlc;
+    bool is_extended;
+} BSP_FDCAN_RemoteFrame_t;
+
+typedef uint32_t (*BSP_FDCAN_IdParser_t)(uint32_t original_id, BSP_FDCAN_FrameType_t frame_type);
+
+typedef struct {
+  FDCAN_TxHeaderTypeDef header; /* HAL FDCAN header type */
+  uint8_t data[BSP_FDCAN_MAX_DLC];
+} BSP_FDCAN_TxMessage_t;
+
+typedef struct {
+  BSP_FDCAN_TxMessage_t buffer[BSP_FDCAN_TX_QUEUE_SIZE];
+  atomic_uint_least32_t head;
+  atomic_uint_least32_t tail;
+} BSP_FDCAN_TxQueue_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+int8_t BSP_FDCAN_Init(void);
+FDCAN_HandleTypeDef *BSP_FDCAN_GetHandle(BSP_FDCAN_t can);
+int8_t BSP_FDCAN_RegisterCallback(BSP_FDCAN_t can, BSP_FDCAN_Callback_t type, void (*callback)(void));
+int8_t BSP_FDCAN_Transmit(BSP_FDCAN_t can, BSP_FDCAN_Format_t format, uint32_t id, uint8_t *data, uint8_t dlc);
+int8_t BSP_FDCAN_TransmitStdDataFrame(BSP_FDCAN_t can, BSP_FDCAN_StdDataFrame_t *frame);
+int8_t BSP_FDCAN_TransmitExtDataFrame(BSP_FDCAN_t can, BSP_FDCAN_ExtDataFrame_t *frame);
+int8_t BSP_FDCAN_TransmitRemoteFrame(BSP_FDCAN_t can, BSP_FDCAN_RemoteFrame_t *frame);
+int8_t BSP_FDCAN_RegisterId(BSP_FDCAN_t can, uint32_t can_id, uint8_t queue_size);
+int8_t BSP_FDCAN_GetMessage(BSP_FDCAN_t can, uint32_t can_id, BSP_FDCAN_Message_t *msg, uint32_t timeout);
+int32_t BSP_FDCAN_GetQueueCount(BSP_FDCAN_t can, uint32_t can_id);
+int8_t BSP_FDCAN_FlushQueue(BSP_FDCAN_t can, uint32_t can_id);
+int8_t BSP_FDCAN_RegisterIdParser(BSP_FDCAN_IdParser_t parser);
+uint32_t BSP_FDCAN_ParseId(uint32_t original_id, BSP_FDCAN_FrameType_t frame_type);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/bsp/mm.c b/User/bsp/mm.c
new file mode 100644
index 0000000..13d20c0
--- /dev/null
+++ b/User/bsp/mm.c
@@ -0,0 +1,30 @@
+/* Includes ----------------------------------------------------------------- */
+#include "bsp/mm.h"
+
+#include "FreeRTOS.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private variables -------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private function  -------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+inline void *BSP_Malloc(size_t size) { return pvPortMalloc(size); }
+
+inline void BSP_Free(void *pv) { vPortFree(pv); }
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/bsp/mm.h b/User/bsp/mm.h
new file mode 100644
index 0000000..d24634e
--- /dev/null
+++ b/User/bsp/mm.h
@@ -0,0 +1,32 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported types ----------------------------------------------------------- */
+/* Exported functions prototypes -------------------------------------------- */
+void *BSP_Malloc(size_t size);
+void BSP_Free(void *pv);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/bsp/time.c b/User/bsp/time.c
new file mode 100644
index 0000000..21918ed
--- /dev/null
+++ b/User/bsp/time.c
@@ -0,0 +1,81 @@
+/* Includes ----------------------------------------------------------------- */
+#include "bsp/time.h"
+#include "bsp.h"
+
+#include 
+#include "FreeRTOS.h"
+#include "main.h"
+#include "task.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+/* Private define ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+/* Private function  -------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+
+uint32_t BSP_TIME_Get_ms() { return xTaskGetTickCount(); }
+
+uint64_t BSP_TIME_Get_us() {
+  uint32_t tick_freq = osKernelGetTickFreq();
+  uint32_t ticks_old = xTaskGetTickCount()*(1000/tick_freq);
+  uint32_t tick_value_old = SysTick->VAL;
+  uint32_t ticks_new = xTaskGetTickCount()*(1000/tick_freq);
+  uint32_t tick_value_new = SysTick->VAL;
+  if (ticks_old == ticks_new) {
+    return ticks_new * 1000 + 1000 - tick_value_old * 1000 / (SysTick->LOAD + 1);
+  } else {
+    return ticks_new * 1000 + 1000 - tick_value_new * 1000 / (SysTick->LOAD + 1);
+  }
+}
+
+uint64_t BSP_TIME_Get() __attribute__((alias("BSP_TIME_Get_us")));
+
+int8_t BSP_TIME_Delay_ms(uint32_t ms) {
+  uint32_t tick_period = 1000u / osKernelGetTickFreq();
+  uint32_t ticks = ms / tick_period;
+
+  switch (osKernelGetState()) {
+    case osKernelError:
+    case osKernelReserved:
+    case osKernelLocked:
+    case osKernelSuspended:
+      return BSP_ERR;
+
+    case osKernelRunning:
+      osDelay(ticks ? ticks : 1);
+      break;
+
+    case osKernelInactive:
+    case osKernelReady:
+      HAL_Delay(ms);
+      break;
+  }
+  return BSP_OK;
+}
+
+/*阻塞us延迟*/
+int8_t BSP_TIME_Delay_us(uint32_t us) {
+    uint64_t start = BSP_TIME_Get_us();
+    while (BSP_TIME_Get_us() - start < us) {
+        // 等待us时间
+    }
+    return BSP_OK;
+}
+
+int8_t BSP_TIME_Delay(uint32_t ms) __attribute__((alias("BSP_TIME_Delay_ms")));
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
\ No newline at end of file
diff --git a/User/bsp/time.h b/User/bsp/time.h
new file mode 100644
index 0000000..c69085b
--- /dev/null
+++ b/User/bsp/time.h
@@ -0,0 +1,43 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+
+#include "bsp/bsp.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported types ----------------------------------------------------------- */
+/* Exported functions prototypes -------------------------------------------- */
+uint32_t BSP_TIME_Get_ms();
+
+uint64_t BSP_TIME_Get_us();
+
+uint64_t BSP_TIME_Get();
+
+int8_t BSP_TIME_Delay_ms(uint32_t ms);
+
+/*微秒阻塞延时，一般别用*/
+int8_t BSP_TIME_Delay_us(uint32_t us);
+
+int8_t BSP_TIME_Delay(uint32_t ms);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/component_config.yaml b/User/component/component_config.yaml
new file mode 100644
index 0000000..47e3fd3
--- /dev/null
+++ b/User/component/component_config.yaml
@@ -0,0 +1,22 @@
+ahrs:
+  dependencies:
+  - component/user_math.h
+  enabled: true
+filter:
+  dependencies:
+  - component/ahrs
+  enabled: true
+mixer:
+  dependencies:
+  - component/user_math.h
+  enabled: true
+pid:
+  dependencies:
+  - component/filter
+  enabled: true
+crc16:
+  dependencies: []
+  enabled: true
+user_math:
+  dependencies: []
+  enabled: true
diff --git a/User/component/crc16.c b/User/component/crc16.c
new file mode 100644
index 0000000..0d17eb0
--- /dev/null
+++ b/User/component/crc16.c
@@ -0,0 +1,62 @@
+#include "crc16.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+static const uint16_t crc16_tab[256] = {
+    0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, 0x8c48,
+    0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, 0x1081, 0x0108,
+    0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, 0x9cc9, 0x8d40, 0xbfdb,
+    0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, 0x2102, 0x308b, 0x0210, 0x1399,
+    0x6726, 0x76af, 0x4434, 0x55bd, 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e,
+    0xfae7, 0xc87c, 0xd9f5, 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e,
+    0x54b5, 0x453c, 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd,
+    0xc974, 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+    0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, 0x5285,
+    0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, 0xdecd, 0xcf44,
+    0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, 0x6306, 0x728f, 0x4014,
+    0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, 0xef4e, 0xfec7, 0xcc5c, 0xddd5,
+    0xa96a, 0xb8e3, 0x8a78, 0x9bf1, 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3,
+    0x242a, 0x16b1, 0x0738, 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862,
+    0x9af9, 0x8b70, 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e,
+    0xf0b7, 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+    0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, 0x18c1,
+    0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, 0xa50a, 0xb483,
+    0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, 0x2942, 0x38cb, 0x0a50,
+    0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, 0xb58b, 0xa402, 0x9699, 0x8710,
+    0xf3af, 0xe226, 0xd0bd, 0xc134, 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7,
+    0x6e6e, 0x5cf5, 0x4d7c, 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1,
+    0xa33a, 0xb2b3, 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72,
+    0x3efb, 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+    0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, 0xe70e,
+    0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, 0x6b46, 0x7acf,
+    0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, 0xf78f, 0xe606, 0xd49d,
+    0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, 0x7bc7, 0x6a4e, 0x58d5, 0x495c,
+    0x3de3, 0x2c6a, 0x1ef1, 0x0f78};
+
+static inline uint16_t CRC16_Byte(uint16_t crc, const uint8_t data) {
+  return (crc >> 8) ^ crc16_tab[(crc ^ data) & 0xff];
+}
+
+uint16_t CRC16_Calc(const uint8_t *buf, size_t len, uint16_t crc) {
+  while (len--) crc = CRC16_Byte(crc, *buf++);
+  return crc;
+}
+
+bool CRC16_Verify(const uint8_t *buf, size_t len) {
+  if (len < 2) return false;
+
+  uint16_t expected = CRC16_Calc(buf, len - sizeof(uint16_t), CRC16_INIT);
+  return expected ==
+         ((const uint16_t *)((const uint8_t *)buf +
+                             (len % 2)))[len / sizeof(uint16_t) - 1];
+}
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/component/crc16.h b/User/component/crc16.h
new file mode 100644
index 0000000..68b0a87
--- /dev/null
+++ b/User/component/crc16.h
@@ -0,0 +1,30 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+#define CRC16_INIT 0XFFFF
+
+uint16_t CRC16_Calc(const uint8_t *buf, size_t len, uint16_t crc);
+bool CRC16_Verify(const uint8_t *buf, size_t len);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/filter.c b/User/component/filter.c
new file mode 100644
index 0000000..5375b8e
--- /dev/null
+++ b/User/component/filter.c
@@ -0,0 +1,185 @@
+/*
+  各类滤波器。
+*/
+
+#include "filter.h"
+
+#include "user_math.h"
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param cutoff_freq 截止频率
+ */
+void LowPassFilter2p_Init(LowPassFilter2p_t *f, float sample_freq,
+                          float cutoff_freq) {
+  if (f == NULL) return;
+
+  f->cutoff_freq = cutoff_freq;
+
+  f->delay_element_1 = 0.0f;
+  f->delay_element_2 = 0.0f;
+
+  if (f->cutoff_freq <= 0.0f) {
+    /* no filtering */
+    f->b0 = 1.0f;
+    f->b1 = 0.0f;
+    f->b2 = 0.0f;
+
+    f->a1 = 0.0f;
+    f->a2 = 0.0f;
+
+    return;
+  }
+  const float fr = sample_freq / f->cutoff_freq;
+  const float ohm = tanf(M_PI / fr);
+  const float c = 1.0f + 2.0f * cosf(M_PI / 4.0f) * ohm + ohm * ohm;
+
+  f->b0 = ohm * ohm / c;
+  f->b1 = 2.0f * f->b0;
+  f->b2 = f->b0;
+
+  f->a1 = 2.0f * (ohm * ohm - 1.0f) / c;
+  f->a2 = (1.0f - 2.0f * cosf(M_PI / 4.0f) * ohm + ohm * ohm) / c;
+}
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Apply(LowPassFilter2p_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  /* do the filtering */
+  float delay_element_0 =
+      sample - f->delay_element_1 * f->a1 - f->delay_element_2 * f->a2;
+
+  if (isinf(delay_element_0)) {
+    /* don't allow bad values to propagate via the filter */
+    delay_element_0 = sample;
+  }
+
+  const float output = delay_element_0 * f->b0 + f->delay_element_1 * f->b1 +
+                       f->delay_element_2 * f->b2;
+
+  f->delay_element_2 = f->delay_element_1;
+  f->delay_element_1 = delay_element_0;
+
+  /* return the value. Should be no need to check limits */
+  return output;
+}
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Reset(LowPassFilter2p_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  const float dval = sample / (f->b0 + f->b1 + f->b2);
+
+  if (isfinite(dval)) {
+    f->delay_element_1 = dval;
+    f->delay_element_2 = dval;
+
+  } else {
+    f->delay_element_1 = sample;
+    f->delay_element_2 = sample;
+  }
+
+  return LowPassFilter2p_Apply(f, sample);
+}
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param notch_freq 中心频率
+ * @param bandwidth 带宽
+ */
+void NotchFilter_Init(NotchFilter_t *f, float sample_freq, float notch_freq,
+                      float bandwidth) {
+  if (f == NULL) return;
+
+  f->notch_freq = notch_freq;
+  f->bandwidth = bandwidth;
+
+  f->delay_element_1 = 0.0f;
+  f->delay_element_2 = 0.0f;
+
+  if (notch_freq <= 0.0f) {
+    /* no filtering */
+    f->b0 = 1.0f;
+    f->b1 = 0.0f;
+    f->b2 = 0.0f;
+
+    f->a1 = 0.0f;
+    f->a2 = 0.0f;
+
+    return;
+  }
+
+  const float alpha = tanf(M_PI * bandwidth / sample_freq);
+  const float beta = -cosf(M_2PI * notch_freq / sample_freq);
+  const float a0_inv = 1.0f / (alpha + 1.0f);
+
+  f->b0 = a0_inv;
+  f->b1 = 2.0f * beta * a0_inv;
+  f->b2 = a0_inv;
+
+  f->a1 = f->b1;
+  f->a2 = (1.0f - alpha) * a0_inv;
+}
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+inline float NotchFilter_Apply(NotchFilter_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  /* Direct Form II implementation */
+  const float delay_element_0 =
+      sample - f->delay_element_1 * f->a1 - f->delay_element_2 * f->a2;
+  const float output = delay_element_0 * f->b0 + f->delay_element_1 * f->b1 +
+                       f->delay_element_2 * f->b2;
+
+  f->delay_element_2 = f->delay_element_1;
+  f->delay_element_1 = delay_element_0;
+
+  return output;
+}
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float NotchFilter_Reset(NotchFilter_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  float dval = sample;
+
+  if (fabsf(f->b0 + f->b1 + f->b2) > FLT_EPSILON) {
+    dval = dval / (f->b0 + f->b1 + f->b2);
+  }
+
+  f->delay_element_1 = dval;
+  f->delay_element_2 = dval;
+
+  return NotchFilter_Apply(f, sample);
+}
diff --git a/User/component/filter.h b/User/component/filter.h
new file mode 100644
index 0000000..ae2b072
--- /dev/null
+++ b/User/component/filter.h
@@ -0,0 +1,120 @@
+/*
+  各类滤波器。
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* 二阶低通滤波器 */
+typedef struct {
+  float cutoff_freq; /* 截止频率 */
+
+  float a1;
+  float a2;
+
+  float b0;
+  float b1;
+  float b2;
+
+  float delay_element_1;
+  float delay_element_2;
+
+} LowPassFilter2p_t;
+
+/* 带阻滤波器 */
+typedef struct {
+  float notch_freq; /* 阻止频率 */
+  float bandwidth;  /* 带宽 */
+
+  float a1;
+  float a2;
+
+  float b0;
+  float b1;
+  float b2;
+  float delay_element_1;
+  float delay_element_2;
+
+} NotchFilter_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param cutoff_freq 截止频率
+ */
+void LowPassFilter2p_Init(LowPassFilter2p_t *f, float sample_freq,
+                          float cutoff_freq);
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Apply(LowPassFilter2p_t *f, float sample);
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Reset(LowPassFilter2p_t *f, float sample);
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param notch_freq 中心频率
+ * @param bandwidth 带宽
+ */
+void NotchFilter_Init(NotchFilter_t *f, float sample_freq, float notch_freq,
+                      float bandwidth);
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float NotchFilter_Apply(NotchFilter_t *f, float sample);
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float NotchFilter_Reset(NotchFilter_t *f, float sample);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/pid.c b/User/component/pid.c
new file mode 100644
index 0000000..0a3c7d4
--- /dev/null
+++ b/User/component/pid.c
@@ -0,0 +1,158 @@
+/*
+   Modified from
+   https://github.com/PX4/Firmware/blob/master/src/lib/pid/pid.cpp
+
+   参考资料：
+   https://github.com/PX4/Firmware/issues/12362
+   https://dev.px4.io/master/en/flight_stack/controller_diagrams.html
+   https://docs.px4.io/master/en/config_mc/pid_tuning_guide_multicopter.html#standard_form
+   https://www.controleng.com/articles/not-all-pid-controllers-are-the-same/
+   https://en.wikipedia.org/wiki/PID_controller
+   http://brettbeauregard.com/blog/2011/04/improving-the-beginner%E2%80%99s-pid-derivative-kick/
+*/
+
+#include "pid.h"
+
+#define SIGMA 0.000001f
+
+/**
+ * @brief 初始化PID
+ *
+ * @param pid PID结构体
+ * @param mode PID模式
+ * @param sample_freq 采样频率
+ * @param param PID参数
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_Init(KPID_t *pid, KPID_Mode_t mode, float sample_freq,
+                const KPID_Params_t *param) {
+  if (pid == NULL) return -1;
+
+  if (!isfinite(param->p)) return -1;
+  if (!isfinite(param->i)) return -1;
+  if (!isfinite(param->d)) return -1;
+  if (!isfinite(param->i_limit)) return -1;
+  if (!isfinite(param->out_limit)) return -1;
+  pid->param = param;
+
+  float dt_min = 1.0f / sample_freq;
+  if (isfinite(dt_min))
+    pid->dt_min = dt_min;
+  else
+    return -1;
+
+  LowPassFilter2p_Init(&(pid->dfilter), sample_freq, pid->param->d_cutoff_freq);
+
+  pid->mode = mode;
+  PID_Reset(pid);
+  return 0;
+}
+
+/**
+ * @brief PID计算
+ *
+ * @param pid PID结构体
+ * @param sp 设定值
+ * @param fb 反馈值
+ * @param fb_dot 反馈值微分
+ * @param dt 间隔时间
+ * @return float 计算的输出
+ */
+float PID_Calc(KPID_t *pid, float sp, float fb, float fb_dot, float dt) {
+  if (!isfinite(sp) || !isfinite(fb) || !isfinite(fb_dot) || !isfinite(dt)) {
+    return pid->last.out;
+  }
+
+  /* 计算误差值 */
+  const float err = CircleError(sp, fb, pid->param->range);
+
+  /* 计算P项 */
+  const float k_err = err * pid->param->k;
+
+  /* 计算D项 */
+  const float k_fb = pid->param->k * fb;
+  const float filtered_k_fb = LowPassFilter2p_Apply(&(pid->dfilter), k_fb);
+
+  float d;
+  switch (pid->mode) {
+    case KPID_MODE_CALC_D:
+      /* 通过fb计算D，避免了由于sp变化导致err突变的问题 */
+      /* 当sp不变时，err的微分等于负的fb的微分 */
+      d = (filtered_k_fb - pid->last.k_fb) / fmaxf(dt, pid->dt_min);
+      break;
+
+    case KPID_MODE_SET_D:
+      d = fb_dot;
+      break;
+
+    case KPID_MODE_NO_D:
+      d = 0.0f;
+      break;
+  }
+  pid->last.err = err;
+  pid->last.k_fb = filtered_k_fb;
+
+  if (!isfinite(d)) d = 0.0f;
+
+  /* 计算PD输出 */
+  float output = (k_err * pid->param->p) - (d * pid->param->d);
+
+  /* 计算I项 */
+  const float i = pid->i + (k_err * dt);
+  const float i_out = i * pid->param->i;
+  
+  if (pid->param->i > SIGMA) {
+    /* 检查是否饱和 */
+    if (isfinite(i)) {
+      if ((fabsf(output + i_out) <= pid->param->out_limit) &&
+          (fabsf(i) <= pid->param->i_limit)) {
+        /* 未饱和，使用新积分 */
+        pid->i = i;
+      }
+    }
+  }
+  
+  /* 计算PID输出 */
+  output += i_out;
+ 
+  /* 限制输出 */
+  if (isfinite(output)) {
+    if (pid->param->out_limit > SIGMA) {
+      output = AbsClip(output, pid->param->out_limit);
+    }
+    pid->last.out = output;
+  }
+  return pid->last.out;
+}
+
+/**
+ * @brief 重置微分项
+ *
+ * @param pid PID结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_ResetIntegral(KPID_t *pid) {
+  if (pid == NULL) return -1;
+
+  pid->i = 0.0f;
+
+  return 0;
+}
+
+/**
+ * @brief 重置PID
+ *
+ * @param pid PID结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_Reset(KPID_t *pid) {
+  if (pid == NULL) return -1;
+
+  pid->i = 0.0f;
+  pid->last.err = 0.0f;
+  pid->last.k_fb = 0.0f;
+  pid->last.out = 0.0f;
+  LowPassFilter2p_Reset(&(pid->dfilter), 0.0f);
+
+  return 0;
+}
diff --git a/User/component/pid.h b/User/component/pid.h
new file mode 100644
index 0000000..4b451eb
--- /dev/null
+++ b/User/component/pid.h
@@ -0,0 +1,107 @@
+/*
+  Modified from
+  https://github.com/PX4/Firmware/blob/master/src/lib/pid/pid.h
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+
+#include "filter.h"
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* PID模式 */
+typedef enum {
+  KPID_MODE_NO_D = 0, /* 不使用微分项，PI控制器 */
+  KPID_MODE_CALC_D, /* 根据反馈的值计算离散微分，忽略PID_Calc中的fb_dot */
+  KPID_MODE_SET_D /* 直接提供微分值，PID_Calc中的fb_dot将被使用，(Gyros) */
+} KPID_Mode_t;
+
+/* PID参数 */
+typedef struct {
+  float k;             /* 控制器增益，设置为1用于并行模式 */
+  float p;             /* 比例项增益，设置为1用于标准形式 */
+  float i;             /* 积分项增益 */
+  float d;             /* 微分项增益 */
+  float i_limit;       /* 积分项上限 */
+  float out_limit;     /* 输出绝对值限制 */
+  float d_cutoff_freq; /* D项低通截止频率 */
+  float range;         /* 计算循环误差时使用，大于0时启用 */
+} KPID_Params_t;
+
+/* PID主结构体 */
+typedef struct {
+  KPID_Mode_t mode;
+  const KPID_Params_t *param;
+
+  float dt_min; /* 最小PID_Calc调用间隔 */
+  float i;      /* 积分 */
+
+  struct {
+    float err;  /* 上次误差 */
+    float k_fb; /* 上次反馈值 */
+    float out;  /* 上次输出 */
+  } last;
+
+  LowPassFilter2p_t dfilter; /* D项低通滤波器 */
+} KPID_t;
+
+/**
+ * @brief 初始化PID
+ *
+ * @param pid PID结构体
+ * @param mode PID模式
+ * @param sample_freq 采样频率
+ * @param param PID参数
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_Init(KPID_t *pid, KPID_Mode_t mode, float sample_freq,
+                const KPID_Params_t *param);
+
+/**
+ * @brief PID计算
+ *
+ * @param pid PID结构体
+ * @param sp 设定值
+ * @param fb 反馈值
+ * @param fb_dot 反馈值微分
+ * @param dt 间隔时间
+ * @return float 计算的输出
+ */
+float PID_Calc(KPID_t *pid, float sp, float fb, float fb_dot, float dt);
+
+/**
+ * @brief 重置微分项
+ *
+ * @param pid PID结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_ResetIntegral(KPID_t *pid);
+
+/**
+ * @brief 重置PID
+ *
+ * @param pid PID结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_Reset(KPID_t *pid);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/user_math.c b/User/component/user_math.c
new file mode 100644
index 0000000..7db9056
--- /dev/null
+++ b/User/component/user_math.c
@@ -0,0 +1,147 @@
+/*
+  自定义的数学运算。
+*/
+
+#include "user_math.h"
+#include 
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+inline float InvSqrt(float x) {
+//#if 0
+  /* Fast inverse square-root */
+  /* See: http://en.wikipedia.org/wiki/Fast_inverse_square_root */
+	float halfx = 0.5f * x;
+	float y = x;
+	long i = *(long*)&y;
+	i = 0x5f3759df - (i>>1);
+	y = *(float*)&i;
+	y = y * (1.5f - (halfx * y * y));
+	y = y * (1.5f - (halfx * y * y));
+	return y;	
+//#else
+//  return 1.0f / sqrtf(x);
+//#endif
+}
+
+inline float AbsClip(float in, float limit) {
+  return (in < -limit) ? -limit : ((in > limit) ? limit : in);
+}
+
+float fAbs(float in){
+  return (in > 0) ? in : -in;
+}
+
+inline void Clip(float *origin, float min, float max) {
+  if (*origin > max) *origin = max;
+  if (*origin < min) *origin = min;
+}
+
+inline float Sign(float in) { return (in > 0) ? 1.0f : 0.0f; }
+
+/**
+ * \brief 将运动向量置零
+ *
+ * \param mv 被操作的值
+ */
+inline void ResetMoveVector(MoveVector_t *mv) { memset(mv, 0, sizeof(*mv)); }
+
+/**
+ * \brief 计算循环值的误差，适用于设定值与反馈值均在（x,y）范围内循环的情况，range应设定为y-x
+ * 例如：（-M_PI,M_PI）range=M_2PI;(0,M_2PI)range=M_2PI;（a,a+b）range=b;
+ * \param sp 设定值
+ * \param fb 反馈值
+ * \param range 被操作的值变化范围，正数时起效
+ * \return 函数运行结果
+ */
+inline float CircleError(float sp, float fb, float range) {
+  float error = sp - fb;
+  if (range > 0.0f) {
+    float half_range = range / 2.0f;
+
+    if (error > half_range)
+      error -= range;
+    else if (error < -half_range)
+      error += range;
+  }
+  return error;
+}
+
+/**
+ * \brief 循环加法，适用于被操作的值在（0,range）范围内循环的情况
+ * \param origin 被操作的值
+ * \param delta 变化量
+ * \param range 被操作的值变化范围，正数时起效
+ */
+inline void CircleAdd(float *origin, float delta, float range) {
+  float out = *origin + delta;
+  if (range > 0.0f) {
+    if (out >= range)
+      out -= range;
+    else if (out < 0.0f)
+      out += range;
+  }
+  *origin = out;
+}
+
+/**
+ * @brief 循环值取反
+ *
+ * @param origin 被操作的值
+ */
+inline void CircleReverse(float *origin) { *origin = -(*origin) + M_2PI; }
+
+/**
+ * @brief 根据目标弹丸速度计算摩擦轮转速
+ *
+ * @param bullet_speed 弹丸速度
+ * @param fric_radius 摩擦轮半径
+ * @param is17mm 是否为17mm
+ * @return 摩擦轮转速
+ */
+inline float CalculateRpm(float bullet_speed, float fric_radius, bool is17mm) {
+  if (bullet_speed == 0.0f) return 0.f;
+  if (is17mm) {
+    if (bullet_speed == 15.0f) return 4670.f;
+    if (bullet_speed == 18.0f) return 5200.f;
+    if (bullet_speed == 30.0f) return 7350.f;
+  } else {
+    if (bullet_speed == 10.0f) return 4450.f;
+    if (bullet_speed == 16.0f) return 5800.f;
+  }
+
+  /* 不为裁判系统设定值时,计算转速 */
+  return 60.0f * (float)bullet_speed / (M_2PI * fric_radius);
+}
+
+// /**
+//  * @brief 断言失败处理
+//  *
+//  * @param file 文件名
+//  * @param line 行号
+//  */
+// void VerifyFailed(const char *file, uint32_t line) {
+//   UNUSED(file);
+//   UNUSED(line);
+//   while (1) {
+//     __NOP();
+//   }
+// }
+
+/* USER FUNCTION BEGIN */
+	/**
+ * @brief 按比例缩放
+ *
+ * @param a 传入值1
+ * @param b 传入值2
+ */
+inline void ScaleSumTo1(float *a, float *b) {
+    float sum = *a + *b;
+    if (sum > 1.0f) {
+        float scale = 1.0f / sum;
+        *a *= scale;
+        *b *= scale;
+    }
+}
+/* USER FUNCTION END */
\ No newline at end of file
diff --git a/User/component/user_math.h b/User/component/user_math.h
new file mode 100644
index 0000000..0f38ce3
--- /dev/null
+++ b/User/component/user_math.h
@@ -0,0 +1,179 @@
+/*
+  自定义的数学运算。
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+#define M_DEG2RAD_MULT (0.01745329251f)
+#define M_RAD2DEG_MULT (57.2957795131f)
+
+#ifndef M_PI_2
+#define M_PI_2 1.57079632679f
+#endif
+
+#ifndef M_PI
+#define M_PI 3.14159265358979323846f
+#endif
+
+#ifndef M_2PI
+#define M_2PI 6.28318530717958647692f
+#endif
+
+#ifndef __packed
+  #define __packed __attribute__((__packed__))
+#endif /* __packed */
+
+#define max(a, b)           \
+  ({                        \
+    __typeof__(a) _a = (a); \
+    __typeof__(b) _b = (b); \
+    _a > _b ? _a : _b;      \
+  })
+
+#define min(a, b)           \
+  ({                        \
+    __typeof__(a) _a = (a); \
+    __typeof__(b) _b = (b); \
+    _a < _b ? _a : _b;      \
+  })
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+
+
+/* 移动向量 */
+typedef struct {
+  float vx; /* 前后平移 */
+  float vy; /* 左右平移 */
+  float wz; /* 转动 */
+} MoveVector_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+float InvSqrt(float x);
+
+float AbsClip(float in, float limit);
+
+float fAbs(float in);
+
+void Clip(float *origin, float min, float max);
+
+float Sign(float in);
+
+/**
+ * \brief 将运动向量置零
+ *
+ * \param mv 被操作的值
+ */
+void ResetMoveVector(MoveVector_t *mv);
+
+/**
+ * \brief 计算循环值的误差，适用于设定值与反馈值均在（x,y）范围内循环的情况，range应设定为y-x
+ * 例如：（-M_PI,M_PI）range=M_2PI;(0,M_2PI)range=M_2PI;（a,a+b）range=b;
+ * \param sp 设定值
+ * \param fb 反馈值
+ * \param range 被操作的值变化范围，正数时起效
+ * \return 函数运行结果
+ */
+float CircleError(float sp, float fb, float range);
+
+/**
+ * \brief 循环加法，适用于被操作的值在（0,range）范围内循环的情况
+ * \param origin 被操作的值
+ * \param delta 变化量
+ * \param range 被操作的值变化范围，正数时起效
+ */
+void CircleAdd(float *origin, float delta, float range);
+
+/**
+ * @brief 循环值取反
+ *
+ * @param origin 被操作的值
+ */
+void CircleReverse(float *origin);
+
+/**
+ * @brief 根据目标弹丸速度计算摩擦轮转速
+ *
+ * @param bullet_speed 弹丸速度
+ * @param fric_radius 摩擦轮半径
+ * @param is17mm 是否为17mm
+ * @return 摩擦轮转速
+ */
+float CalculateRpm(float bullet_speed, float fric_radius, bool is17mm);
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef DEBUG
+
+/**
+ * @brief 如果表达式的值为假则运行处理函数
+ *
+ */
+#define ASSERT(expr)                    \
+  do {                                  \
+    if (!(expr)) {                      \
+      VerifyFailed(__FILE__, __LINE__); \
+    }                                   \
+  } while (0)
+#else
+
+/**
+ * @brief 未定DEBUG，表达式不会运行，断言被忽略
+ *
+ */
+#define ASSERT(expr) ((void)(0))
+#endif
+
+#ifdef DEBUG
+
+/**
+ * @brief 如果表达式的值为假则运行处理函数
+ *
+ */
+#define VERIFY(expr)                    \
+  do {                                  \
+    if (!(expr)) {                      \
+      VerifyFailed(__FILE__, __LINE__); \
+    }                                   \
+  } while (0)
+#else
+
+/**
+ * @brief 表达式会运行，忽略表达式结果
+ *
+ */
+#define VERIFY(expr) ((void)(expr))
+#endif
+
+// /**
+//  * @brief 断言失败处理
+//  *
+//  * @param file 文件名
+//  * @param line 行号
+//  */
+// void VerifyFailed(const char *file, uint32_t line);
+
+/* USER FUNCTION BEGIN */
+void ScaleSumTo1(float *a, float *b);
+/* USER FUNCTION END */
\ No newline at end of file
diff --git a/User/device/device.h b/User/device/device.h
new file mode 100644
index 0000000..562e25e
--- /dev/null
+++ b/User/device/device.h
@@ -0,0 +1,52 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+#define DEVICE_OK (0)
+#define DEVICE_ERR (-1)
+#define DEVICE_ERR_NULL (-2)
+#define DEVICE_ERR_INITED (-3)
+#define DEVICE_ERR_NO_DEV (-4)
+
+/* AUTO GENERATED SIGNALS BEGIN */
+#define SIGNAL_DR16_RAW_REDY (1u << 0)
+#define SIGNAL_BMI088_ACCL_RAW_REDY (1u << 1)
+#define SIGNAL_BMI088_GYRO_RAW_REDY (1u << 2)
+#define SIGNAL_BMI088_ACCL_NEW_DATA (1u << 3)
+#define SIGNAL_BMI088_GYRO_NEW_DATA (1u << 4)
+/* AUTO GENERATED SIGNALS END */
+
+/* USER SIGNALS BEGIN */
+
+/* USER SIGNALS END */
+/*设备层通用Header*/
+typedef struct {
+    bool online;
+    uint64_t last_online_time;
+} DEVICE_Header_t;
+
+/* USER STRUCT BEGIN */
+#define SIGNAL_AT9S_RAW_REDY (1u << 7)
+#define SIGNAL_VT13_RAW_REDY (1u << 8)
+/* USER STRUCT END */
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/device/device_config.yaml b/User/device/device_config.yaml
new file mode 100644
index 0000000..f1bf5e3
--- /dev/null
+++ b/User/device/device_config.yaml
@@ -0,0 +1,29 @@
+bmi088:
+  bsp_config:
+    BSP_GPIO_ACCL_CS: BSP_GPIO_ACCL_CS
+    BSP_GPIO_ACCL_INT: BSP_GPIO_ACCL_INT
+    BSP_GPIO_GYRO_CS: BSP_GPIO_GYRO_CS
+    BSP_GPIO_GYRO_INT: BSP_GPIO_GYRO_INT
+    BSP_SPI_BMI088: BSP_SPI_BMI088
+  enabled: true
+buzzer:
+  BSP_PWM_BUZZER: BSP_PWM_TIM8_CH1
+  bsp_config: null
+  enabled: true
+dr16:
+  bsp_config:
+    BSP_UART_DR16: BSP_UART_AT9S_PRO
+  enabled: true
+motor:
+  bsp_config: {}
+  enabled: true
+motor_dm:
+  bsp_config: {}
+  enabled: true
+motor_rm:
+  bsp_config: {}
+  enabled: true
+vofa:
+  bsp_config:
+    BSP_UART_VOFA: BSP_UART_AT9S_PRO
+  enabled: true
diff --git a/User/task/blink.c b/User/task/blink.c
new file mode 100644
index 0000000..31c51c5
--- /dev/null
+++ b/User/task/blink.c
@@ -0,0 +1,56 @@
+/*
+    blink Task
+    
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "stm32h7xx_hal_gpio.h"
+#include "task/user_task.h"
+/* USER INCLUDE BEGIN */
+// #include "bsp/pwm.h"
+#include 
+/* USER INCLUDE END */
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private function --------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+void Task_blink(void *argument) {
+  (void)argument; /* 未使用argument，消除警告 */
+
+  
+  /* 计算任务运行到指定频率需要等待的tick数 */
+  const uint32_t delay_tick = osKernelGetTickFreq() / BLINK_FREQ;
+
+  osDelay(BLINK_INIT_DELAY); /* 延时一段时间再开启任务 */
+
+  uint32_t tick = osKernelGetTickCount(); /* 控制任务运行频率的计时 */
+  /* USER CODE INIT BEGIN */
+  // BSP_PWM_Stop(BSP_PWM_LED_R);
+  // BSP_PWM_Stop(BSP_PWM_LED_B);
+  // BSP_PWM_SetComp(BSP_PWM_LED_G, 0.0f);
+  // BSP_PWM_Start(BSP_PWM_LED_G);
+
+  // HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_SET);
+  // HAL_GPIO_WritePin(GPIOC, GPIO_PIN_14, GPIO_PIN_SET);
+  // HAL_GPIO_WritePin(GPIOC, GPIO_PIN_15, GPIO_PIN_SET);
+  /* USER CODE INIT END */
+  
+  while (1) {
+    tick += delay_tick; /* 计算下一个唤醒时刻 */
+    /* USER CODE BEGIN */
+    // 呼吸灯 - 基于tick的正弦波
+    // float duty = (sinf(tick * 0.003f) + 1.0f) * 0.5f; // 0到1之间的正弦波，加快频率
+    // BSP_PWM_SetComp(BSP_PWM_LED_G, duty);
+
+    /* USER CODE END */
+    osDelayUntil(tick); /* 运行结束，等待下一次唤醒 */
+  }
+  
+}
diff --git a/User/task/config.yaml b/User/task/config.yaml
new file mode 100644
index 0000000..50bb2a8
--- /dev/null
+++ b/User/task/config.yaml
@@ -0,0 +1,56 @@
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_rc
+  name: rc
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 1000.0
+  function: Task_atti_esti
+  name: atti_esti
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 100.0
+  function: Task_blink
+  name: blink
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_ctrl_chassis
+  name: ctrl_chassis
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_ctrl_gimbal
+  name: ctrl_gimbal
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_ctrl_shoot
+  name: ctrl_shoot
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_cmd
+  name: cmd
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_supercap
+  name: supercap
+  stack: 512
diff --git a/User/task/init.c b/User/task/init.c
new file mode 100644
index 0000000..15437b1
--- /dev/null
+++ b/User/task/init.c
@@ -0,0 +1,42 @@
+/*
+    Init Task
+    任务初始化，创建各个线程任务和消息队列
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "task/user_task.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* Private function --------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+
+/**
+ * \brief 初始化
+ *
+ * \param argument 未使用
+ */
+void Task_Init(void *argument) {
+  (void)argument; /* 未使用argument，消除警告 */
+    /* USER CODE INIT BEGIN */
+
+    /* USER CODE INIT END */
+  osKernelLock(); /* 锁定内核，防止任务切换 */
+  
+  /* 创建任务线程 */
+  task_runtime.thread.rc = osThreadNew(Task_rc, NULL, &attr_rc);
+  task_runtime.thread.blink = osThreadNew(Task_blink, NULL, &attr_blink);
+  // 创建消息队列
+  /* USER MESSAGE BEGIN */
+  task_runtime.msgq.user_msg= osMessageQueueNew(2u, 10, NULL);
+  /* USER MESSAGE END */
+
+  osKernelUnlock(); // 解锁内核
+  osThreadTerminate(osThreadGetId()); // 任务完成后结束自身
+}
diff --git a/User/task/user_task.c b/User/task/user_task.c
new file mode 100644
index 0000000..6052781
--- /dev/null
+++ b/User/task/user_task.c
@@ -0,0 +1,16 @@
+#include "task/user_task.h"
+
+Task_Runtime_t task_runtime;
+
+const osThreadAttr_t attr_init = {
+    .name = "Task_Init",
+    .priority = osPriorityRealtime,
+    .stack_size = 256 * 4,
+};
+
+/* User_task */
+const osThreadAttr_t attr_blink = {
+    .name = "blink",
+    .priority = osPriorityNormal,
+    .stack_size = 256 * 4,
+};
diff --git a/User/task/user_task.h b/User/task/user_task.h
new file mode 100644
index 0000000..2de8688
--- /dev/null
+++ b/User/task/user_task.h
@@ -0,0 +1,157 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+/* Exported constants ------------------------------------------------------- */
+/* 任务运行频率 */
+#define RC_FREQ (500.0)
+#define ATTI_ESTI_FREQ (1000.0)
+#define BLINK_FREQ (100.0)
+#define CTRL_CHASSIS_FREQ (500.0)
+#define CTRL_GIMBAL_FREQ (500.0)
+#define CTRL_SHOOT_FREQ (500.0)
+#define CMD_FREQ (500.0)
+#define SUPERCAP_FREQ (500.0)
+
+/* 任务初始化延时ms */
+#define TASK_INIT_DELAY (100u)
+#define RC_INIT_DELAY (0)
+#define ATTI_ESTI_INIT_DELAY (0)
+#define BLINK_INIT_DELAY (0)
+#define CTRL_CHASSIS_INIT_DELAY (0)
+#define CTRL_GIMBAL_INIT_DELAY (0)
+#define CTRL_SHOOT_INIT_DELAY (0)
+#define CMD_INIT_DELAY (0)
+#define SUPERCAP_INIT_DELAY (0)
+
+/* Exported defines --------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+
+/* 任务运行时结构体 */
+typedef struct {
+    /* 各任务，也可以叫做线程 */
+    struct {
+        osThreadId_t rc;
+        osThreadId_t atti_esti;
+        osThreadId_t blink;
+        osThreadId_t ctrl_chassis;
+        osThreadId_t ctrl_gimbal;
+        osThreadId_t ctrl_shoot;
+        osThreadId_t cmd;
+        osThreadId_t supercap;
+    } thread;
+
+    /* USER MESSAGE BEGIN */
+    struct {
+        osMessageQueueId_t user_msg; /* 用户自定义任务消息队列 */
+
+		struct {
+            osMessageQueueId_t imu;
+            osMessageQueueId_t cmd;
+            osMessageQueueId_t yaw;
+        }chassis;
+        struct {
+            osMessageQueueId_t imu;
+            osMessageQueueId_t cmd;
+        }gimbal;
+        struct{
+            osMessageQueueId_t cmd; 
+        }shoot;
+		struct{
+			osMessageQueueId_t rc; 
+            osMessageQueueId_t pc; 
+            osMessageQueueId_t nuc; 
+            osMessageQueueId_t ref; 
+        }cmd;
+
+
+    } msgq;
+    /* USER MESSAGE END */
+
+    /* 机器人状态 */
+    struct {
+        float battery; /* 电池电量百分比 */
+        float vbat; /* 电池电压 */
+        float cpu_temp; /* CPU温度 */
+    } status;
+
+    /* USER CONFIG BEGIN */
+
+    /* USER CONFIG END */
+
+    /* 各任务的stack使用 */
+    struct {
+        UBaseType_t rc;
+        UBaseType_t atti_esti;
+        UBaseType_t blink;
+        UBaseType_t ctrl_chassis;
+        UBaseType_t ctrl_gimbal;
+        UBaseType_t ctrl_shoot;
+        UBaseType_t cmd;
+        UBaseType_t supercap;
+    } stack_water_mark;
+
+    /* 各任务运行频率 */
+    struct {
+        float rc;
+        float atti_esti;
+        float blink;
+        float ctrl_chassis;
+        float ctrl_gimbal;
+        float ctrl_shoot;
+        float cmd;
+        float supercap;
+    } freq;
+
+    /* 任务最近运行时间 */
+    struct {
+        float rc;
+        float atti_esti;
+        float blink;
+        float ctrl_chassis;
+        float ctrl_gimbal;
+        float ctrl_shoot;
+        float cmd;
+        float supercap;
+    } last_up_time;
+
+} Task_Runtime_t;
+
+/* 任务运行时结构体 */
+extern Task_Runtime_t task_runtime;
+
+/* 初始化任务句柄 */
+extern const osThreadAttr_t attr_init;
+extern const osThreadAttr_t attr_rc;
+extern const osThreadAttr_t attr_atti_esti;
+extern const osThreadAttr_t attr_blink;
+extern const osThreadAttr_t attr_ctrl_chassis;
+extern const osThreadAttr_t attr_ctrl_gimbal;
+extern const osThreadAttr_t attr_ctrl_shoot;
+extern const osThreadAttr_t attr_cmd;
+extern const osThreadAttr_t attr_supercap;
+
+/* 任务函数声明 */
+void Task_Init(void *argument);
+void Task_rc(void *argument);
+void Task_atti_esti(void *argument);
+void Task_blink(void *argument);
+void Task_ctrl_chassis(void *argument);
+void Task_ctrl_gimbal(void *argument);
+void Task_ctrl_shoot(void *argument);
+void Task_cmd(void *argument);
+void Task_supercap(void *argument);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/cmake/gcc-arm-none-eabi.cmake b/cmake/gcc-arm-none-eabi.cmake
new file mode 100644
index 0000000..d70e902
--- /dev/null
+++ b/cmake/gcc-arm-none-eabi.cmake
@@ -0,0 +1,43 @@
+set(CMAKE_SYSTEM_NAME               Generic)
+set(CMAKE_SYSTEM_PROCESSOR          arm)
+
+set(CMAKE_C_COMPILER_ID GNU)
+set(CMAKE_CXX_COMPILER_ID GNU)
+
+# Some default GCC settings
+# arm-none-eabi- must be part of path environment
+set(TOOLCHAIN_PREFIX                arm-none-eabi-)
+
+set(CMAKE_C_COMPILER                ${TOOLCHAIN_PREFIX}gcc)
+set(CMAKE_ASM_COMPILER              ${CMAKE_C_COMPILER})
+set(CMAKE_CXX_COMPILER              ${TOOLCHAIN_PREFIX}g++)
+set(CMAKE_LINKER                    ${TOOLCHAIN_PREFIX}g++)
+set(CMAKE_OBJCOPY                   ${TOOLCHAIN_PREFIX}objcopy)
+set(CMAKE_SIZE                      ${TOOLCHAIN_PREFIX}size)
+
+set(CMAKE_EXECUTABLE_SUFFIX_ASM     ".elf")
+set(CMAKE_EXECUTABLE_SUFFIX_C       ".elf")
+set(CMAKE_EXECUTABLE_SUFFIX_CXX     ".elf")
+
+set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
+
+# MCU specific flags
+set(TARGET_FLAGS "-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard ")
+
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${TARGET_FLAGS}")
+set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp -MMD -MP")
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -fdata-sections -ffunction-sections")
+
+set(CMAKE_C_FLAGS_DEBUG "-O0 -g3")
+set(CMAKE_C_FLAGS_RELEASE "-Os -g0")
+set(CMAKE_CXX_FLAGS_DEBUG "-O0 -g3")
+set(CMAKE_CXX_FLAGS_RELEASE "-Os -g0")
+
+set(CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS} -fno-rtti -fno-exceptions -fno-threadsafe-statics")
+
+set(CMAKE_EXE_LINKER_FLAGS "${TARGET_FLAGS}")
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T \"${CMAKE_SOURCE_DIR}/STM32H723XG_FLASH.ld\"")
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} --specs=nano.specs")
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,-Map=${CMAKE_PROJECT_NAME}.map -Wl,--gc-sections")
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--print-memory-usage")
+set(TOOLCHAIN_LINK_LIBRARIES "m")
diff --git a/cmake/starm-clang.cmake b/cmake/starm-clang.cmake
new file mode 100644
index 0000000..e4ec5ca
--- /dev/null
+++ b/cmake/starm-clang.cmake
@@ -0,0 +1,65 @@
+set(CMAKE_SYSTEM_NAME               Generic)
+set(CMAKE_SYSTEM_PROCESSOR          arm)
+
+set(CMAKE_C_COMPILER_ID Clang)
+set(CMAKE_CXX_COMPILER_ID Clang)
+
+# Some default llvm settings
+set(TOOLCHAIN_PREFIX                starm-)
+
+set(CMAKE_C_COMPILER                ${TOOLCHAIN_PREFIX}clang)
+set(CMAKE_ASM_COMPILER              ${CMAKE_C_COMPILER})
+set(CMAKE_CXX_COMPILER              ${TOOLCHAIN_PREFIX}clang++)
+set(CMAKE_LINKER                    ${TOOLCHAIN_PREFIX}clang)
+set(CMAKE_OBJCOPY                   ${TOOLCHAIN_PREFIX}objcopy)
+set(CMAKE_SIZE                      ${TOOLCHAIN_PREFIX}size)
+
+set(CMAKE_EXECUTABLE_SUFFIX_ASM     ".elf")
+set(CMAKE_EXECUTABLE_SUFFIX_C       ".elf")
+set(CMAKE_EXECUTABLE_SUFFIX_CXX     ".elf")
+
+set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
+
+# STARM_TOOLCHAIN_CONFIG allows you to choose the toolchain configuration.
+# Possible values are:
+#  "STARM_HYBRID"   : Hybrid configuration using starm-clang Assemler and Compiler and GNU Linker
+#  "STARM_NEWLIB"   : starm-clang toolchain with NEWLIB C library
+#  "STARM_PICOLIBC" : starm-clang toolchain with PICOLIBC C library
+set(STARM_TOOLCHAIN_CONFIG "STARM_HYBRID")
+
+if(STARM_TOOLCHAIN_CONFIG STREQUAL "STARM_HYBRID")
+  set(TOOLCHAIN_MULTILIBS "--multi-lib-config=\"$ENV{CLANG_GCC_CMSIS_COMPILER}/multilib.gnu_tools_for_stm32.yaml\" --gcc-toolchain=\"$ENV{GCC_TOOLCHAIN_ROOT}/..\"")
+elseif (STARM_TOOLCHAIN_CONFIG STREQUAL "STARM_NEWLIB")
+  set(TOOLCHAIN_MULTILIBS "--config=newlib.cfg")
+endif()
+
+# MCU specific flags
+set(TARGET_FLAGS "-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard ${TOOLCHAIN_MULTILIBS}")
+
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${TARGET_FLAGS}")
+set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp -MP")
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -fdata-sections -ffunction-sections")
+
+set(CMAKE_C_FLAGS_DEBUG "-O0 -g3")
+set(CMAKE_C_FLAGS_RELEASE "-Os -g0")
+set(CMAKE_CXX_FLAGS_DEBUG "-O0 -g3")
+set(CMAKE_CXX_FLAGS_RELEASE "-Os -g0")
+
+set(CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS} -fno-rtti -fno-exceptions -fno-threadsafe-statics")
+
+set(CMAKE_EXE_LINKER_FLAGS "${TARGET_FLAGS}")
+
+if (STARM_TOOLCHAIN_CONFIG STREQUAL "STARM_HYBRID")
+  set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} --gcc-specs=nano.specs")
+  set(TOOLCHAIN_LINK_LIBRARIES "m")
+elseif(STARM_TOOLCHAIN_CONFIG STREQUAL "STARM_NEWLIB")
+  set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -lcrt0-nosys")
+elseif(STARM_TOOLCHAIN_CONFIG STREQUAL "STARM_PICOLIBC")
+  set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -lcrt0-hosted")
+
+endif()
+
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T \"${CMAKE_SOURCE_DIR}/STM32H723XG_FLASH.ld\"")
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,-Map=${CMAKE_PROJECT_NAME}.map -Wl,--gc-sections")
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -z noexecstack")
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--print-memory-usage ")
diff --git a/cmake/stm32cubemx/CMakeLists.txt b/cmake/stm32cubemx/CMakeLists.txt
new file mode 100644
index 0000000..e01f3d2
--- /dev/null
+++ b/cmake/stm32cubemx/CMakeLists.txt
@@ -0,0 +1,120 @@
+cmake_minimum_required(VERSION 3.22)
+# Enable CMake support for ASM and C languages
+enable_language(C ASM)
+# STM32CubeMX generated symbols (macros)
+set(MX_Defines_Syms 
+	USE_PWR_LDO_SUPPLY 
+	USE_HAL_DRIVER 
+	STM32H723xx
+    $<$:DEBUG>
+)
+
+# STM32CubeMX generated include paths
+set(MX_Include_Dirs
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Inc
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Inc
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/include
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/CMSIS/Device/ST/STM32H7xx/Include
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/CMSIS/Include
+)
+
+# STM32CubeMX generated application sources
+set(MX_Application_Src
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/main.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/gpio.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/freertos.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/fdcan.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/stm32h7xx_it.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/stm32h7xx_hal_msp.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/stm32h7xx_hal_timebase_tim.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/sysmem.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/syscalls.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../startup_stm32h723xx.s
+)
+
+# STM32 HAL/LL Drivers
+set(STM32_Drivers_Src
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/system_stm32h7xx.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
+)
+
+# Drivers Midllewares
+
+
+set(FreeRTOS_Src
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/list.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/../../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
+)
+
+# Link directories setup
+set(MX_LINK_DIRS
+
+)
+# Project static libraries
+set(MX_LINK_LIBS 
+    STM32_Drivers
+    ${TOOLCHAIN_LINK_LIBRARIES}
+    FreeRTOS
+	
+)
+# Interface library for includes and symbols
+add_library(stm32cubemx INTERFACE)
+target_include_directories(stm32cubemx INTERFACE ${MX_Include_Dirs})
+target_compile_definitions(stm32cubemx INTERFACE ${MX_Defines_Syms})
+
+# Create STM32_Drivers static library
+add_library(STM32_Drivers OBJECT)
+target_sources(STM32_Drivers PRIVATE ${STM32_Drivers_Src})
+target_link_libraries(STM32_Drivers PUBLIC stm32cubemx)
+
+
+# Create FreeRTOS static library
+add_library(FreeRTOS OBJECT)
+target_sources(FreeRTOS PRIVATE ${FreeRTOS_Src})
+target_link_libraries(FreeRTOS PUBLIC stm32cubemx)
+
+# Add STM32CubeMX generated application sources to the project
+target_sources(${CMAKE_PROJECT_NAME} PRIVATE ${MX_Application_Src})
+
+# Link directories setup
+target_link_directories(${CMAKE_PROJECT_NAME} PRIVATE ${MX_LINK_DIRS})
+
+# Add libraries to the project
+target_link_libraries(${CMAKE_PROJECT_NAME} ${MX_LINK_LIBS})
+
+# Add the map file to the list of files to be removed with 'clean' target
+set_target_properties(${CMAKE_PROJECT_NAME} PROPERTIES ADDITIONAL_CLEAN_FILES ${CMAKE_PROJECT_NAME}.map)
+
+# Validate that STM32CubeMX code is compatible with C standard
+if((CMAKE_C_STANDARD EQUAL 90) OR (CMAKE_C_STANDARD EQUAL 99))
+    message(ERROR "Generated code requires C11 or higher")
+endif()
diff --git a/startup_stm32h723xx.s b/startup_stm32h723xx.s
new file mode 100644
index 0000000..631bcc1
--- /dev/null
+++ b/startup_stm32h723xx.s
@@ -0,0 +1,759 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h723xx.s
+  * @author    MCD Application Team
+  * @brief     STM32H723xx Devices vector table for GCC based toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m7
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/* Call the ExitRun0Mode function to configure the power supply */
+  bl  ExitRun0Mode
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_AVD_IRQHandler                /* PVD/AVD through EXTI Line detection */
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
+  .word     FDCAN1_IT0_IRQHandler             /* FDCAN1 interrupt line 0      */
+  .word     FDCAN2_IT0_IRQHandler             /* FDCAN2 interrupt line 0      */
+  .word     FDCAN1_IT1_IRQHandler             /* FDCAN1 interrupt line 1      */
+  .word     FDCAN2_IT1_IRQHandler             /* FDCAN2 interrupt line 1      */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
+  .word     TIM1_BRK_IRQHandler               /* TIM1 Break interrupt         */
+  .word     TIM1_UP_IRQHandler                /* TIM1 Update interrupt        */
+  .word     TIM1_TRG_COM_IRQHandler           /* TIM1 Trigger and Commutation interrupt */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     TIM3_IRQHandler                   /* TIM3                         */
+  .word     TIM4_IRQHandler                   /* TIM4                         */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     USART3_IRQHandler                 /* USART3                       */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
+  .word     0                                 /* Reserved                     */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
+  .word     FMC_IRQHandler                    /* FMC                          */
+  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
+  .word     TIM5_IRQHandler                   /* TIM5                         */
+  .word     SPI3_IRQHandler                   /* SPI3                         */
+  .word     UART4_IRQHandler                  /* UART4                        */
+  .word     UART5_IRQHandler                  /* UART5                        */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
+  .word     ETH_IRQHandler                    /* Ethernet                     */
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */
+  .word     FDCAN_CAL_IRQHandler              /* FDCAN calibration unit interrupt*/
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
+  .word     USART6_IRQHandler                 /* USART6                       */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
+  .word     DCMI_PSSI_IRQHandler              /* DCMI, PSSI                   */
+  .word     0                                 /* Reserved                     */
+  .word     RNG_IRQHandler                    /* Rng                          */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5                         */
+  .word     SPI6_IRQHandler                   /* SPI6                         */
+  .word     SAI1_IRQHandler                   /* SAI1                         */
+  .word     LTDC_IRQHandler                   /* LTDC                         */
+  .word     LTDC_ER_IRQHandler                /* LTDC error                   */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  .word     0                                 /* Reserved                     */
+  .word     OCTOSPI1_IRQHandler               /* OCTOSPI1                     */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     CEC_IRQHandler                    /* HDMI_CEC                     */
+  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
+  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
+  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DMAMUX1_OVR_IRQHandler            /* DMAMUX1 Overrun interrupt    */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM Filter0 Interrupt      */
+  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM Filter1 Interrupt      */
+  .word     DFSDM1_FLT2_IRQHandler            /* DFSDM Filter2 Interrupt      */
+  .word     DFSDM1_FLT3_IRQHandler            /* DFSDM Filter3 Interrupt      */
+  .word     0                                 /* Reserved                     */
+  .word     SWPMI1_IRQHandler                 /* Serial Wire Interface 1 global interrupt */
+  .word     TIM15_IRQHandler                  /* TIM15 global Interrupt          */
+  .word     TIM16_IRQHandler                  /* TIM16 global Interrupt          */
+  .word     TIM17_IRQHandler                  /* TIM17 global Interrupt          */
+  .word     MDIOS_WKUP_IRQHandler             /* MDIOS Wakeup  Interrupt         */
+  .word     MDIOS_IRQHandler                  /* MDIOS global Interrupt          */
+  .word     0                                 /* Reserved                        */
+  .word     MDMA_IRQHandler                   /* MDMA global Interrupt           */
+  .word     0                                 /* Reserved                        */
+  .word     SDMMC2_IRQHandler                 /* SDMMC2 global Interrupt         */
+  .word     HSEM1_IRQHandler                  /* HSEM1 global Interrupt          */
+  .word     0                                 /* Reserved                        */
+  .word     ADC3_IRQHandler                   /* ADC3 global Interrupt           */
+  .word     DMAMUX2_OVR_IRQHandler            /* DMAMUX Overrun interrupt        */
+  .word     BDMA_Channel0_IRQHandler          /* BDMA Channel 0 global Interrupt */
+  .word     BDMA_Channel1_IRQHandler          /* BDMA Channel 1 global Interrupt */
+  .word     BDMA_Channel2_IRQHandler          /* BDMA Channel 2 global Interrupt */
+  .word     BDMA_Channel3_IRQHandler          /* BDMA Channel 3 global Interrupt */
+  .word     BDMA_Channel4_IRQHandler          /* BDMA Channel 4 global Interrupt */
+  .word     BDMA_Channel5_IRQHandler          /* BDMA Channel 5 global Interrupt */
+  .word     BDMA_Channel6_IRQHandler          /* BDMA Channel 6 global Interrupt */
+  .word     BDMA_Channel7_IRQHandler          /* BDMA Channel 7 global Interrupt */
+  .word     COMP1_IRQHandler                  /* COMP1 global Interrupt          */
+  .word     LPTIM2_IRQHandler                 /* LP TIM2 global interrupt        */
+  .word     LPTIM3_IRQHandler                 /* LP TIM3 global interrupt        */
+  .word     LPTIM4_IRQHandler                 /* LP TIM4 global interrupt        */
+  .word     LPTIM5_IRQHandler                 /* LP TIM5 global interrupt        */
+  .word     LPUART1_IRQHandler                /* LP UART1 interrupt              */
+  .word     0                                 /* Reserved                        */
+  .word     CRS_IRQHandler                    /* Clock Recovery Global Interrupt */
+  .word     ECC_IRQHandler                    /* ECC diagnostic Global Interrupt */
+  .word     SAI4_IRQHandler                   /* SAI4 global interrupt           */
+  .word     DTS_IRQHandler                    /* Digital Temperature Sensor  interrupt */
+  .word     0                                 /* Reserved                              */
+  .word     WAKEUP_PIN_IRQHandler             /* Interrupt for all 6 wake-up pins      */
+  .word     OCTOSPI2_IRQHandler               /* OCTOSPI2 Interrupt       */
+  .word     0                                 /* Reserved                 */
+  .word     0                                 /* Reserved                 */
+  .word     FMAC_IRQHandler                   /* FMAC Interrupt           */
+  .word     CORDIC_IRQHandler                 /* CORDIC Interrupt         */
+  .word     UART9_IRQHandler                  /* UART9 Interrupt          */
+  .word     USART10_IRQHandler                /* UART10 Interrupt         */
+  .word     I2C5_EV_IRQHandler                /* I2C5 Event Interrupt     */
+  .word     I2C5_ER_IRQHandler                /* I2C5 Error Interrupt     */
+  .word     FDCAN3_IT0_IRQHandler             /* FDCAN3 interrupt line 0  */
+  .word     FDCAN3_IT1_IRQHandler             /* FDCAN3 interrupt line 1  */
+  .word     TIM23_IRQHandler                  /* TIM23 global interrupt   */
+  .word     TIM24_IRQHandler                  /* TIM24 global interrupt   */
+
+  .size  g_pfnVectors, .-g_pfnVectors
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_AVD_IRQHandler
+   .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+   .weak      TAMP_STAMP_IRQHandler
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+   .weak      RTC_WKUP_IRQHandler
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream0_IRQHandler
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream1_IRQHandler
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream2_IRQHandler
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream3_IRQHandler
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream4_IRQHandler
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream5_IRQHandler
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream6_IRQHandler
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+   .weak      ADC_IRQHandler
+   .thumb_set ADC_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT0_IRQHandler
+   .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT0_IRQHandler
+   .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT1_IRQHandler
+   .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT1_IRQHandler
+   .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TIM1_BRK_IRQHandler
+   .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+   .weak      TIM1_UP_IRQHandler
+   .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_IRQHandler
+   .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+   .weak      TIM1_CC_IRQHandler
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM3_IRQHandler
+   .thumb_set TIM3_IRQHandler,Default_Handler
+
+   .weak      TIM4_IRQHandler
+   .thumb_set TIM4_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTC_Alarm_IRQHandler
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+   .weak      TIM8_BRK_TIM12_IRQHandler
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+   .weak      TIM8_UP_TIM13_IRQHandler
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+   .weak      TIM8_CC_IRQHandler
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream7_IRQHandler
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+   .weak      FMC_IRQHandler
+   .thumb_set FMC_IRQHandler,Default_Handler
+
+   .weak      SDMMC1_IRQHandler
+   .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+   .weak      TIM5_IRQHandler
+   .thumb_set TIM5_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TIM6_DAC_IRQHandler
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+   .weak      TIM7_IRQHandler
+   .thumb_set TIM7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream0_IRQHandler
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream1_IRQHandler
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream2_IRQHandler
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream3_IRQHandler
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream4_IRQHandler
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+   .weak      ETH_IRQHandler
+   .thumb_set ETH_IRQHandler,Default_Handler
+
+   .weak      ETH_WKUP_IRQHandler
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+   .weak      FDCAN_CAL_IRQHandler
+   .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream5_IRQHandler
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream6_IRQHandler
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream7_IRQHandler
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_OUT_IRQHandler
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_IN_IRQHandler
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_WKUP_IRQHandler
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_IRQHandler
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+   .weak      DCMI_PSSI_IRQHandler
+   .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+   .weak      RNG_IRQHandler
+   .thumb_set RNG_IRQHandler,Default_Handler
+
+   .weak      FPU_IRQHandler
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler
+   .thumb_set SPI6_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      LTDC_IRQHandler
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler
+   .thumb_set DMA2D_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI1_IRQHandler
+   .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+   .weak      LPTIM1_IRQHandler
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      CEC_IRQHandler
+   .thumb_set CEC_IRQHandler,Default_Handler
+
+   .weak      I2C4_EV_IRQHandler
+   .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+   .weak      I2C4_ER_IRQHandler
+   .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+   .weak      SPDIF_RX_IRQHandler
+   .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+   .weak      DMAMUX1_OVR_IRQHandler
+   .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT0_IRQHandler
+   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT1_IRQHandler
+   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT2_IRQHandler
+   .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT3_IRQHandler
+   .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+   .weak      SWPMI1_IRQHandler
+   .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+   .weak      TIM15_IRQHandler
+   .thumb_set TIM15_IRQHandler,Default_Handler
+
+   .weak      TIM16_IRQHandler
+   .thumb_set TIM16_IRQHandler,Default_Handler
+
+   .weak      TIM17_IRQHandler
+   .thumb_set TIM17_IRQHandler,Default_Handler
+
+   .weak      MDIOS_WKUP_IRQHandler
+   .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+   .weak      MDIOS_IRQHandler
+   .thumb_set MDIOS_IRQHandler,Default_Handler
+
+   .weak      MDMA_IRQHandler
+   .thumb_set MDMA_IRQHandler,Default_Handler
+
+   .weak      SDMMC2_IRQHandler
+   .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+   .weak      HSEM1_IRQHandler
+   .thumb_set HSEM1_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      DMAMUX2_OVR_IRQHandler
+   .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+   .weak      BDMA_Channel0_IRQHandler
+   .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+   .weak      BDMA_Channel1_IRQHandler
+   .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+   .weak      BDMA_Channel2_IRQHandler
+   .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+   .weak      BDMA_Channel3_IRQHandler
+   .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+   .weak      BDMA_Channel4_IRQHandler
+   .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+   .weak      BDMA_Channel5_IRQHandler
+   .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+   .weak      BDMA_Channel6_IRQHandler
+   .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+   .weak      BDMA_Channel7_IRQHandler
+   .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+   .weak      COMP1_IRQHandler
+   .thumb_set COMP1_IRQHandler,Default_Handler
+
+   .weak      LPTIM2_IRQHandler
+   .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+   .weak      LPTIM3_IRQHandler
+   .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+   .weak      LPTIM4_IRQHandler
+   .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+   .weak      LPTIM5_IRQHandler
+   .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+   .weak      LPUART1_IRQHandler
+   .thumb_set LPUART1_IRQHandler,Default_Handler
+
+   .weak      CRS_IRQHandler
+   .thumb_set CRS_IRQHandler,Default_Handler
+
+   .weak      ECC_IRQHandler
+   .thumb_set ECC_IRQHandler,Default_Handler
+
+   .weak      SAI4_IRQHandler
+   .thumb_set SAI4_IRQHandler,Default_Handler
+
+   .weak      DTS_IRQHandler
+   .thumb_set DTS_IRQHandler,Default_Handler
+
+   .weak      WAKEUP_PIN_IRQHandler
+   .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI2_IRQHandler
+   .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+   .weak      FMAC_IRQHandler
+   .thumb_set FMAC_IRQHandler,Default_Handler
+
+   .weak      CORDIC_IRQHandler
+   .thumb_set CORDIC_IRQHandler,Default_Handler
+
+   .weak      UART9_IRQHandler
+   .thumb_set UART9_IRQHandler,Default_Handler
+
+   .weak      USART10_IRQHandler
+   .thumb_set USART10_IRQHandler,Default_Handler
+
+   .weak      I2C5_EV_IRQHandler
+   .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+   .weak      I2C5_ER_IRQHandler
+   .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+   .weak      FDCAN3_IT0_IRQHandler
+   .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN3_IT1_IRQHandler
+   .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
+
+   .weak      TIM23_IRQHandler
+   .thumb_set TIM23_IRQHandler,Default_Handler
+
+   .weak      TIM24_IRQHandler
+   .thumb_set TIM24_IRQHandler,Default_Handler
+
+